2 * Copyright 2010-2011 Calxeda, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/kernel.h>
19 #include <linux/circ_buf.h>
20 #include <linux/interrupt.h>
21 #include <linux/etherdevice.h>
22 #include <linux/platform_device.h>
23 #include <linux/skbuff.h>
24 #include <linux/ethtool.h>
26 #include <linux/crc32.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/slab.h>
30 /* XGMAC Register definitions */
31 #define XGMAC_CONTROL 0x00000000 /* MAC Configuration */
32 #define XGMAC_FRAME_FILTER 0x00000004 /* MAC Frame Filter */
33 #define XGMAC_FLOW_CTRL 0x00000018 /* MAC Flow Control */
34 #define XGMAC_VLAN_TAG 0x0000001C /* VLAN Tags */
35 #define XGMAC_VERSION 0x00000020 /* Version */
36 #define XGMAC_VLAN_INCL 0x00000024 /* VLAN tag for tx frames */
37 #define XGMAC_LPI_CTRL 0x00000028 /* LPI Control and Status */
38 #define XGMAC_LPI_TIMER 0x0000002C /* LPI Timers Control */
39 #define XGMAC_TX_PACE 0x00000030 /* Transmit Pace and Stretch */
40 #define XGMAC_VLAN_HASH 0x00000034 /* VLAN Hash Table */
41 #define XGMAC_DEBUG 0x00000038 /* Debug */
42 #define XGMAC_INT_STAT 0x0000003C /* Interrupt and Control */
43 #define XGMAC_ADDR_HIGH(reg) (0x00000040 + ((reg) * 8))
44 #define XGMAC_ADDR_LOW(reg) (0x00000044 + ((reg) * 8))
45 #define XGMAC_HASH(n) (0x00000300 + (n) * 4) /* HASH table regs */
46 #define XGMAC_NUM_HASH 16
47 #define XGMAC_OMR 0x00000400
48 #define XGMAC_REMOTE_WAKE 0x00000700 /* Remote Wake-Up Frm Filter */
49 #define XGMAC_PMT 0x00000704 /* PMT Control and Status */
50 #define XGMAC_MMC_CTRL 0x00000800 /* XGMAC MMC Control */
51 #define XGMAC_MMC_INTR_RX 0x00000804 /* Recieve Interrupt */
52 #define XGMAC_MMC_INTR_TX 0x00000808 /* Transmit Interrupt */
53 #define XGMAC_MMC_INTR_MASK_RX 0x0000080c /* Recieve Interrupt Mask */
54 #define XGMAC_MMC_INTR_MASK_TX 0x00000810 /* Transmit Interrupt Mask */
56 /* Hardware TX Statistics Counters */
57 #define XGMAC_MMC_TXOCTET_GB_LO 0x00000814
58 #define XGMAC_MMC_TXOCTET_GB_HI 0x00000818
59 #define XGMAC_MMC_TXFRAME_GB_LO 0x0000081C
60 #define XGMAC_MMC_TXFRAME_GB_HI 0x00000820
61 #define XGMAC_MMC_TXBCFRAME_G 0x00000824
62 #define XGMAC_MMC_TXMCFRAME_G 0x0000082C
63 #define XGMAC_MMC_TXUCFRAME_GB 0x00000864
64 #define XGMAC_MMC_TXMCFRAME_GB 0x0000086C
65 #define XGMAC_MMC_TXBCFRAME_GB 0x00000874
66 #define XGMAC_MMC_TXUNDERFLOW 0x0000087C
67 #define XGMAC_MMC_TXOCTET_G_LO 0x00000884
68 #define XGMAC_MMC_TXOCTET_G_HI 0x00000888
69 #define XGMAC_MMC_TXFRAME_G_LO 0x0000088C
70 #define XGMAC_MMC_TXFRAME_G_HI 0x00000890
71 #define XGMAC_MMC_TXPAUSEFRAME 0x00000894
72 #define XGMAC_MMC_TXVLANFRAME 0x0000089C
74 /* Hardware RX Statistics Counters */
75 #define XGMAC_MMC_RXFRAME_GB_LO 0x00000900
76 #define XGMAC_MMC_RXFRAME_GB_HI 0x00000904
77 #define XGMAC_MMC_RXOCTET_GB_LO 0x00000908
78 #define XGMAC_MMC_RXOCTET_GB_HI 0x0000090C
79 #define XGMAC_MMC_RXOCTET_G_LO 0x00000910
80 #define XGMAC_MMC_RXOCTET_G_HI 0x00000914
81 #define XGMAC_MMC_RXBCFRAME_G 0x00000918
82 #define XGMAC_MMC_RXMCFRAME_G 0x00000920
83 #define XGMAC_MMC_RXCRCERR 0x00000928
84 #define XGMAC_MMC_RXRUNT 0x00000930
85 #define XGMAC_MMC_RXJABBER 0x00000934
86 #define XGMAC_MMC_RXUCFRAME_G 0x00000970
87 #define XGMAC_MMC_RXLENGTHERR 0x00000978
88 #define XGMAC_MMC_RXPAUSEFRAME 0x00000988
89 #define XGMAC_MMC_RXOVERFLOW 0x00000990
90 #define XGMAC_MMC_RXVLANFRAME 0x00000998
91 #define XGMAC_MMC_RXWATCHDOG 0x000009a0
93 /* DMA Control and Status Registers */
94 #define XGMAC_DMA_BUS_MODE 0x00000f00 /* Bus Mode */
95 #define XGMAC_DMA_TX_POLL 0x00000f04 /* Transmit Poll Demand */
96 #define XGMAC_DMA_RX_POLL 0x00000f08 /* Received Poll Demand */
97 #define XGMAC_DMA_RX_BASE_ADDR 0x00000f0c /* Receive List Base */
98 #define XGMAC_DMA_TX_BASE_ADDR 0x00000f10 /* Transmit List Base */
99 #define XGMAC_DMA_STATUS 0x00000f14 /* Status Register */
100 #define XGMAC_DMA_CONTROL 0x00000f18 /* Ctrl (Operational Mode) */
101 #define XGMAC_DMA_INTR_ENA 0x00000f1c /* Interrupt Enable */
102 #define XGMAC_DMA_MISS_FRAME_CTR 0x00000f20 /* Missed Frame Counter */
103 #define XGMAC_DMA_RI_WDOG_TIMER 0x00000f24 /* RX Intr Watchdog Timer */
104 #define XGMAC_DMA_AXI_BUS 0x00000f28 /* AXI Bus Mode */
105 #define XGMAC_DMA_AXI_STATUS 0x00000f2C /* AXI Status */
106 #define XGMAC_DMA_HW_FEATURE 0x00000f58 /* Enabled Hardware Features */
108 #define XGMAC_ADDR_AE 0x80000000
109 #define XGMAC_MAX_FILTER_ADDR 31
111 /* PMT Control and Status */
112 #define XGMAC_PMT_POINTER_RESET 0x80000000
113 #define XGMAC_PMT_GLBL_UNICAST 0x00000200
114 #define XGMAC_PMT_WAKEUP_RX_FRM 0x00000040
115 #define XGMAC_PMT_MAGIC_PKT 0x00000020
116 #define XGMAC_PMT_WAKEUP_FRM_EN 0x00000004
117 #define XGMAC_PMT_MAGIC_PKT_EN 0x00000002
118 #define XGMAC_PMT_POWERDOWN 0x00000001
120 #define XGMAC_CONTROL_SPD 0x40000000 /* Speed control */
121 #define XGMAC_CONTROL_SPD_MASK 0x60000000
122 #define XGMAC_CONTROL_SPD_1G 0x60000000
123 #define XGMAC_CONTROL_SPD_2_5G 0x40000000
124 #define XGMAC_CONTROL_SPD_10G 0x00000000
125 #define XGMAC_CONTROL_SARC 0x10000000 /* Source Addr Insert/Replace */
126 #define XGMAC_CONTROL_SARK_MASK 0x18000000
127 #define XGMAC_CONTROL_CAR 0x04000000 /* CRC Addition/Replacement */
128 #define XGMAC_CONTROL_CAR_MASK 0x06000000
129 #define XGMAC_CONTROL_DP 0x01000000 /* Disable Padding */
130 #define XGMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on rx */
131 #define XGMAC_CONTROL_JD 0x00400000 /* Jabber disable */
132 #define XGMAC_CONTROL_JE 0x00100000 /* Jumbo frame */
133 #define XGMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
134 #define XGMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */
135 #define XGMAC_CONTROL_ACS 0x00000080 /* Automatic Pad/FCS Strip */
136 #define XGMAC_CONTROL_DDIC 0x00000010 /* Disable Deficit Idle Count */
137 #define XGMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */
138 #define XGMAC_CONTROL_RE 0x00000004 /* Receiver Enable */
140 /* XGMAC Frame Filter defines */
141 #define XGMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */
142 #define XGMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */
143 #define XGMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */
144 #define XGMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */
145 #define XGMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */
146 #define XGMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */
147 #define XGMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */
148 #define XGMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */
149 #define XGMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */
150 #define XGMAC_FRAME_FILTER_VHF 0x00000800 /* VLAN Hash Filter */
151 #define XGMAC_FRAME_FILTER_VPF 0x00001000 /* VLAN Perfect Filter */
152 #define XGMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */
154 /* XGMAC FLOW CTRL defines */
155 #define XGMAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */
156 #define XGMAC_FLOW_CTRL_PT_SHIFT 16
157 #define XGMAC_FLOW_CTRL_DZQP 0x00000080 /* Disable Zero-Quanta Phase */
158 #define XGMAC_FLOW_CTRL_PLT 0x00000020 /* Pause Low Threshhold */
159 #define XGMAC_FLOW_CTRL_PLT_MASK 0x00000030 /* PLT MASK */
160 #define XGMAC_FLOW_CTRL_UP 0x00000008 /* Unicast Pause Frame Detect */
161 #define XGMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */
162 #define XGMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */
163 #define XGMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */
165 /* XGMAC_INT_STAT reg */
166 #define XGMAC_INT_STAT_PMTIM 0x00800000 /* PMT Interrupt Mask */
167 #define XGMAC_INT_STAT_PMT 0x0080 /* PMT Interrupt Status */
168 #define XGMAC_INT_STAT_LPI 0x0040 /* LPI Interrupt Status */
170 /* DMA Bus Mode register defines */
171 #define DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */
172 #define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */
173 #define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */
174 #define DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */
176 /* Programmable burst length */
177 #define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */
178 #define DMA_BUS_MODE_PBL_SHIFT 8
179 #define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */
180 #define DMA_BUS_MODE_RPBL_MASK 0x003e0000 /* Rx-Programmable Burst Len */
181 #define DMA_BUS_MODE_RPBL_SHIFT 17
182 #define DMA_BUS_MODE_USP 0x00800000
183 #define DMA_BUS_MODE_8PBL 0x01000000
184 #define DMA_BUS_MODE_AAL 0x02000000
186 /* DMA Bus Mode register defines */
187 #define DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */
188 #define DMA_BUS_PR_RATIO_SHIFT 14
189 #define DMA_BUS_FB 0x00010000 /* Fixed Burst */
191 /* DMA Control register defines */
192 #define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
193 #define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
194 #define DMA_CONTROL_DFF 0x01000000 /* Disable flush of rx frames */
195 #define DMA_CONTROL_OSF 0x00000004 /* Operate on 2nd tx frame */
197 /* DMA Normal interrupt */
198 #define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
199 #define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
200 #define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
201 #define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */
202 #define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */
203 #define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */
204 #define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */
205 #define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */
206 #define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
207 #define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */
208 #define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */
209 #define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */
210 #define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavail */
211 #define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */
212 #define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */
214 #define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
215 DMA_INTR_ENA_TUE | DMA_INTR_ENA_TIE)
217 #define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
218 DMA_INTR_ENA_RWE | DMA_INTR_ENA_RSE | \
219 DMA_INTR_ENA_RUE | DMA_INTR_ENA_UNE | \
220 DMA_INTR_ENA_OVE | DMA_INTR_ENA_TJE | \
223 /* DMA default interrupt mask */
224 #define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
226 /* DMA Status register defines */
227 #define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
228 #define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */
229 #define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */
230 #define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
231 #define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
232 #define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */
233 #define DMA_STATUS_TS_SHIFT 20
234 #define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */
235 #define DMA_STATUS_RS_SHIFT 17
236 #define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
237 #define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */
238 #define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
239 #define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */
240 #define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
241 #define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
242 #define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
243 #define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
244 #define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
245 #define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
246 #define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */
247 #define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
248 #define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavail */
249 #define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
250 #define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
252 /* Common MAC defines */
253 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
254 #define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */
256 /* XGMAC Operation Mode Register */
257 #define XGMAC_OMR_TSF 0x00200000 /* TX FIFO Store and Forward */
258 #define XGMAC_OMR_FTF 0x00100000 /* Flush Transmit FIFO */
259 #define XGMAC_OMR_TTC 0x00020000 /* Transmit Threshhold Ctrl */
260 #define XGMAC_OMR_TTC_MASK 0x00030000
261 #define XGMAC_OMR_RFD 0x00006000 /* FC Deactivation Threshhold */
262 #define XGMAC_OMR_RFD_MASK 0x00007000 /* FC Deact Threshhold MASK */
263 #define XGMAC_OMR_RFA 0x00000600 /* FC Activation Threshhold */
264 #define XGMAC_OMR_RFA_MASK 0x00000E00 /* FC Act Threshhold MASK */
265 #define XGMAC_OMR_EFC 0x00000100 /* Enable Hardware FC */
266 #define XGMAC_OMR_FEF 0x00000080 /* Forward Error Frames */
267 #define XGMAC_OMR_DT 0x00000040 /* Drop TCP/IP csum Errors */
268 #define XGMAC_OMR_RSF 0x00000020 /* RX FIFO Store and Forward */
269 #define XGMAC_OMR_RTC_256 0x00000018 /* RX Threshhold Ctrl */
270 #define XGMAC_OMR_RTC_MASK 0x00000018 /* RX Threshhold Ctrl MASK */
272 /* XGMAC HW Features Register */
273 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* TX Checksum offload */
275 #define XGMAC_MMC_CTRL_CNT_FRZ 0x00000008
277 /* XGMAC Descriptor Defines */
278 #define MAX_DESC_BUF_SZ (0x2000 - 8)
280 #define RXDESC_EXT_STATUS 0x00000001
281 #define RXDESC_CRC_ERR 0x00000002
282 #define RXDESC_RX_ERR 0x00000008
283 #define RXDESC_RX_WDOG 0x00000010
284 #define RXDESC_FRAME_TYPE 0x00000020
285 #define RXDESC_GIANT_FRAME 0x00000080
286 #define RXDESC_LAST_SEG 0x00000100
287 #define RXDESC_FIRST_SEG 0x00000200
288 #define RXDESC_VLAN_FRAME 0x00000400
289 #define RXDESC_OVERFLOW_ERR 0x00000800
290 #define RXDESC_LENGTH_ERR 0x00001000
291 #define RXDESC_SA_FILTER_FAIL 0x00002000
292 #define RXDESC_DESCRIPTOR_ERR 0x00004000
293 #define RXDESC_ERROR_SUMMARY 0x00008000
294 #define RXDESC_FRAME_LEN_OFFSET 16
295 #define RXDESC_FRAME_LEN_MASK 0x3fff0000
296 #define RXDESC_DA_FILTER_FAIL 0x40000000
298 #define RXDESC1_END_RING 0x00008000
300 #define RXDESC_IP_PAYLOAD_MASK 0x00000003
301 #define RXDESC_IP_PAYLOAD_UDP 0x00000001
302 #define RXDESC_IP_PAYLOAD_TCP 0x00000002
303 #define RXDESC_IP_PAYLOAD_ICMP 0x00000003
304 #define RXDESC_IP_HEADER_ERR 0x00000008
305 #define RXDESC_IP_PAYLOAD_ERR 0x00000010
306 #define RXDESC_IPV4_PACKET 0x00000040
307 #define RXDESC_IPV6_PACKET 0x00000080
308 #define TXDESC_UNDERFLOW_ERR 0x00000001
309 #define TXDESC_JABBER_TIMEOUT 0x00000002
310 #define TXDESC_LOCAL_FAULT 0x00000004
311 #define TXDESC_REMOTE_FAULT 0x00000008
312 #define TXDESC_VLAN_FRAME 0x00000010
313 #define TXDESC_FRAME_FLUSHED 0x00000020
314 #define TXDESC_IP_HEADER_ERR 0x00000040
315 #define TXDESC_PAYLOAD_CSUM_ERR 0x00000080
316 #define TXDESC_ERROR_SUMMARY 0x00008000
317 #define TXDESC_SA_CTRL_INSERT 0x00040000
318 #define TXDESC_SA_CTRL_REPLACE 0x00080000
319 #define TXDESC_2ND_ADDR_CHAINED 0x00100000
320 #define TXDESC_END_RING 0x00200000
321 #define TXDESC_CSUM_IP 0x00400000
322 #define TXDESC_CSUM_IP_PAYLD 0x00800000
323 #define TXDESC_CSUM_ALL 0x00C00000
324 #define TXDESC_CRC_EN_REPLACE 0x01000000
325 #define TXDESC_CRC_EN_APPEND 0x02000000
326 #define TXDESC_DISABLE_PAD 0x04000000
327 #define TXDESC_FIRST_SEG 0x10000000
328 #define TXDESC_LAST_SEG 0x20000000
329 #define TXDESC_INTERRUPT 0x40000000
331 #define DESC_OWN 0x80000000
332 #define DESC_BUFFER1_SZ_MASK 0x00001fff
333 #define DESC_BUFFER2_SZ_MASK 0x1fff0000
334 #define DESC_BUFFER2_SZ_OFFSET 16
336 struct xgmac_dma_desc
{
339 __le32 buf1_addr
; /* Buffer 1 Address Pointer */
340 __le32 buf2_addr
; /* Buffer 2 Address Pointer */
345 struct xgmac_extra_stats
{
346 /* Transmit errors */
347 unsigned long tx_jabber
;
348 unsigned long tx_frame_flushed
;
349 unsigned long tx_payload_error
;
350 unsigned long tx_ip_header_error
;
351 unsigned long tx_local_fault
;
352 unsigned long tx_remote_fault
;
354 unsigned long rx_watchdog
;
355 unsigned long rx_da_filter_fail
;
356 unsigned long rx_sa_filter_fail
;
357 unsigned long rx_payload_error
;
358 unsigned long rx_ip_header_error
;
359 /* Tx/Rx IRQ errors */
360 unsigned long tx_undeflow
;
361 unsigned long tx_process_stopped
;
362 unsigned long rx_buf_unav
;
363 unsigned long rx_process_stopped
;
364 unsigned long tx_early
;
365 unsigned long fatal_bus_error
;
369 struct xgmac_dma_desc
*dma_rx
;
370 struct sk_buff
**rx_skbuff
;
371 unsigned int rx_tail
;
372 unsigned int rx_head
;
374 struct xgmac_dma_desc
*dma_tx
;
375 struct sk_buff
**tx_skbuff
;
376 unsigned int tx_head
;
377 unsigned int tx_tail
;
381 unsigned int dma_buf_sz
;
382 dma_addr_t dma_rx_phy
;
383 dma_addr_t dma_tx_phy
;
385 struct net_device
*dev
;
386 struct device
*device
;
387 struct napi_struct napi
;
389 struct xgmac_extra_stats xstats
;
391 spinlock_t stats_lock
;
396 struct work_struct tx_timeout_work
;
399 /* XGMAC Configuration Settings */
401 #define PAUSE_TIME 0x400
403 #define DMA_RX_RING_SZ 256
404 #define DMA_TX_RING_SZ 128
405 /* minimum number of free TX descriptors required to wake up TX process */
406 #define TX_THRESH (DMA_TX_RING_SZ/4)
408 /* DMA descriptor ring helpers */
409 #define dma_ring_incr(n, s) (((n) + 1) & ((s) - 1))
410 #define dma_ring_space(h, t, s) CIRC_SPACE(h, t, s)
411 #define dma_ring_cnt(h, t, s) CIRC_CNT(h, t, s)
413 #define tx_dma_ring_space(p) \
414 dma_ring_space((p)->tx_head, (p)->tx_tail, DMA_TX_RING_SZ)
416 /* XGMAC Descriptor Access Helpers */
417 static inline void desc_set_buf_len(struct xgmac_dma_desc
*p
, u32 buf_sz
)
419 if (buf_sz
> MAX_DESC_BUF_SZ
)
420 p
->buf_size
= cpu_to_le32(MAX_DESC_BUF_SZ
|
421 (buf_sz
- MAX_DESC_BUF_SZ
) << DESC_BUFFER2_SZ_OFFSET
);
423 p
->buf_size
= cpu_to_le32(buf_sz
);
426 static inline int desc_get_buf_len(struct xgmac_dma_desc
*p
)
428 u32 len
= le32_to_cpu(p
->buf_size
);
429 return (len
& DESC_BUFFER1_SZ_MASK
) +
430 ((len
& DESC_BUFFER2_SZ_MASK
) >> DESC_BUFFER2_SZ_OFFSET
);
433 static inline void desc_init_rx_desc(struct xgmac_dma_desc
*p
, int ring_size
,
436 struct xgmac_dma_desc
*end
= p
+ ring_size
- 1;
438 memset(p
, 0, sizeof(*p
) * ring_size
);
440 for (; p
<= end
; p
++)
441 desc_set_buf_len(p
, buf_sz
);
443 end
->buf_size
|= cpu_to_le32(RXDESC1_END_RING
);
446 static inline void desc_init_tx_desc(struct xgmac_dma_desc
*p
, u32 ring_size
)
448 memset(p
, 0, sizeof(*p
) * ring_size
);
449 p
[ring_size
- 1].flags
= cpu_to_le32(TXDESC_END_RING
);
452 static inline int desc_get_owner(struct xgmac_dma_desc
*p
)
454 return le32_to_cpu(p
->flags
) & DESC_OWN
;
457 static inline void desc_set_rx_owner(struct xgmac_dma_desc
*p
)
459 /* Clear all fields and set the owner */
460 p
->flags
= cpu_to_le32(DESC_OWN
);
463 static inline void desc_set_tx_owner(struct xgmac_dma_desc
*p
, u32 flags
)
465 u32 tmpflags
= le32_to_cpu(p
->flags
);
466 tmpflags
&= TXDESC_END_RING
;
467 tmpflags
|= flags
| DESC_OWN
;
468 p
->flags
= cpu_to_le32(tmpflags
);
471 static inline int desc_get_tx_ls(struct xgmac_dma_desc
*p
)
473 return le32_to_cpu(p
->flags
) & TXDESC_LAST_SEG
;
476 static inline int desc_get_tx_fs(struct xgmac_dma_desc
*p
)
478 return le32_to_cpu(p
->flags
) & TXDESC_FIRST_SEG
;
481 static inline u32
desc_get_buf_addr(struct xgmac_dma_desc
*p
)
483 return le32_to_cpu(p
->buf1_addr
);
486 static inline void desc_set_buf_addr(struct xgmac_dma_desc
*p
,
489 p
->buf1_addr
= cpu_to_le32(paddr
);
490 if (len
> MAX_DESC_BUF_SZ
)
491 p
->buf2_addr
= cpu_to_le32(paddr
+ MAX_DESC_BUF_SZ
);
494 static inline void desc_set_buf_addr_and_size(struct xgmac_dma_desc
*p
,
497 desc_set_buf_len(p
, len
);
498 desc_set_buf_addr(p
, paddr
, len
);
501 static inline int desc_get_rx_frame_len(struct xgmac_dma_desc
*p
)
503 u32 data
= le32_to_cpu(p
->flags
);
504 u32 len
= (data
& RXDESC_FRAME_LEN_MASK
) >> RXDESC_FRAME_LEN_OFFSET
;
505 if (data
& RXDESC_FRAME_TYPE
)
511 static void xgmac_dma_flush_tx_fifo(void __iomem
*ioaddr
)
514 u32 reg
= readl(ioaddr
+ XGMAC_OMR
);
515 writel(reg
| XGMAC_OMR_FTF
, ioaddr
+ XGMAC_OMR
);
517 while ((timeout
-- > 0) && readl(ioaddr
+ XGMAC_OMR
) & XGMAC_OMR_FTF
)
521 static int desc_get_tx_status(struct xgmac_priv
*priv
, struct xgmac_dma_desc
*p
)
523 struct xgmac_extra_stats
*x
= &priv
->xstats
;
524 u32 status
= le32_to_cpu(p
->flags
);
526 if (!(status
& TXDESC_ERROR_SUMMARY
))
529 netdev_dbg(priv
->dev
, "tx desc error = 0x%08x\n", status
);
530 if (status
& TXDESC_JABBER_TIMEOUT
)
532 if (status
& TXDESC_FRAME_FLUSHED
)
533 x
->tx_frame_flushed
++;
534 if (status
& TXDESC_UNDERFLOW_ERR
)
535 xgmac_dma_flush_tx_fifo(priv
->base
);
536 if (status
& TXDESC_IP_HEADER_ERR
)
537 x
->tx_ip_header_error
++;
538 if (status
& TXDESC_LOCAL_FAULT
)
540 if (status
& TXDESC_REMOTE_FAULT
)
541 x
->tx_remote_fault
++;
542 if (status
& TXDESC_PAYLOAD_CSUM_ERR
)
543 x
->tx_payload_error
++;
548 static int desc_get_rx_status(struct xgmac_priv
*priv
, struct xgmac_dma_desc
*p
)
550 struct xgmac_extra_stats
*x
= &priv
->xstats
;
551 int ret
= CHECKSUM_UNNECESSARY
;
552 u32 status
= le32_to_cpu(p
->flags
);
553 u32 ext_status
= le32_to_cpu(p
->ext_status
);
555 if (status
& RXDESC_DA_FILTER_FAIL
) {
556 netdev_dbg(priv
->dev
, "XGMAC RX : Dest Address filter fail\n");
557 x
->rx_da_filter_fail
++;
561 /* All frames should fit into a single buffer */
562 if (!(status
& RXDESC_FIRST_SEG
) || !(status
& RXDESC_LAST_SEG
))
565 /* Check if packet has checksum already */
566 if ((status
& RXDESC_FRAME_TYPE
) && (status
& RXDESC_EXT_STATUS
) &&
567 !(ext_status
& RXDESC_IP_PAYLOAD_MASK
))
570 netdev_dbg(priv
->dev
, "rx status - frame type=%d, csum = %d, ext stat %08x\n",
571 (status
& RXDESC_FRAME_TYPE
) ? 1 : 0, ret
, ext_status
);
573 if (!(status
& RXDESC_ERROR_SUMMARY
))
576 /* Handle any errors */
577 if (status
& (RXDESC_DESCRIPTOR_ERR
| RXDESC_OVERFLOW_ERR
|
578 RXDESC_GIANT_FRAME
| RXDESC_LENGTH_ERR
| RXDESC_CRC_ERR
))
581 if (status
& RXDESC_EXT_STATUS
) {
582 if (ext_status
& RXDESC_IP_HEADER_ERR
)
583 x
->rx_ip_header_error
++;
584 if (ext_status
& RXDESC_IP_PAYLOAD_ERR
)
585 x
->rx_payload_error
++;
586 netdev_dbg(priv
->dev
, "IP checksum error - stat %08x\n",
588 return CHECKSUM_NONE
;
594 static inline void xgmac_mac_enable(void __iomem
*ioaddr
)
596 u32 value
= readl(ioaddr
+ XGMAC_CONTROL
);
597 value
|= MAC_ENABLE_RX
| MAC_ENABLE_TX
;
598 writel(value
, ioaddr
+ XGMAC_CONTROL
);
600 value
= readl(ioaddr
+ XGMAC_DMA_CONTROL
);
601 value
|= DMA_CONTROL_ST
| DMA_CONTROL_SR
;
602 writel(value
, ioaddr
+ XGMAC_DMA_CONTROL
);
605 static inline void xgmac_mac_disable(void __iomem
*ioaddr
)
607 u32 value
= readl(ioaddr
+ XGMAC_DMA_CONTROL
);
608 value
&= ~(DMA_CONTROL_ST
| DMA_CONTROL_SR
);
609 writel(value
, ioaddr
+ XGMAC_DMA_CONTROL
);
611 value
= readl(ioaddr
+ XGMAC_CONTROL
);
612 value
&= ~(MAC_ENABLE_TX
| MAC_ENABLE_RX
);
613 writel(value
, ioaddr
+ XGMAC_CONTROL
);
616 static void xgmac_set_mac_addr(void __iomem
*ioaddr
, unsigned char *addr
,
621 data
= (addr
[5] << 8) | addr
[4] | (num
? XGMAC_ADDR_AE
: 0);
622 writel(data
, ioaddr
+ XGMAC_ADDR_HIGH(num
));
623 data
= (addr
[3] << 24) | (addr
[2] << 16) | (addr
[1] << 8) | addr
[0];
624 writel(data
, ioaddr
+ XGMAC_ADDR_LOW(num
));
627 static void xgmac_get_mac_addr(void __iomem
*ioaddr
, unsigned char *addr
,
630 u32 hi_addr
, lo_addr
;
632 /* Read the MAC address from the hardware */
633 hi_addr
= readl(ioaddr
+ XGMAC_ADDR_HIGH(num
));
634 lo_addr
= readl(ioaddr
+ XGMAC_ADDR_LOW(num
));
636 /* Extract the MAC address from the high and low words */
637 addr
[0] = lo_addr
& 0xff;
638 addr
[1] = (lo_addr
>> 8) & 0xff;
639 addr
[2] = (lo_addr
>> 16) & 0xff;
640 addr
[3] = (lo_addr
>> 24) & 0xff;
641 addr
[4] = hi_addr
& 0xff;
642 addr
[5] = (hi_addr
>> 8) & 0xff;
645 static int xgmac_set_flow_ctrl(struct xgmac_priv
*priv
, int rx
, int tx
)
648 unsigned int flow
= 0;
655 flow
|= XGMAC_FLOW_CTRL_RFE
;
657 flow
|= XGMAC_FLOW_CTRL_TFE
;
659 flow
|= XGMAC_FLOW_CTRL_PLT
| XGMAC_FLOW_CTRL_UP
;
660 flow
|= (PAUSE_TIME
<< XGMAC_FLOW_CTRL_PT_SHIFT
);
662 writel(flow
, priv
->base
+ XGMAC_FLOW_CTRL
);
664 reg
= readl(priv
->base
+ XGMAC_OMR
);
665 reg
|= XGMAC_OMR_EFC
;
666 writel(reg
, priv
->base
+ XGMAC_OMR
);
668 writel(0, priv
->base
+ XGMAC_FLOW_CTRL
);
670 reg
= readl(priv
->base
+ XGMAC_OMR
);
671 reg
&= ~XGMAC_OMR_EFC
;
672 writel(reg
, priv
->base
+ XGMAC_OMR
);
678 static void xgmac_rx_refill(struct xgmac_priv
*priv
)
680 struct xgmac_dma_desc
*p
;
682 int bufsz
= priv
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
684 while (dma_ring_space(priv
->rx_head
, priv
->rx_tail
, DMA_RX_RING_SZ
) > 1) {
685 int entry
= priv
->rx_head
;
688 p
= priv
->dma_rx
+ entry
;
690 if (priv
->rx_skbuff
[entry
] == NULL
) {
691 skb
= netdev_alloc_skb_ip_align(priv
->dev
, bufsz
);
692 if (unlikely(skb
== NULL
))
695 priv
->rx_skbuff
[entry
] = skb
;
696 paddr
= dma_map_single(priv
->device
, skb
->data
,
697 bufsz
, DMA_FROM_DEVICE
);
698 desc_set_buf_addr(p
, paddr
, priv
->dma_buf_sz
);
701 netdev_dbg(priv
->dev
, "rx ring: head %d, tail %d\n",
702 priv
->rx_head
, priv
->rx_tail
);
704 priv
->rx_head
= dma_ring_incr(priv
->rx_head
, DMA_RX_RING_SZ
);
705 desc_set_rx_owner(p
);
710 * init_xgmac_dma_desc_rings - init the RX/TX descriptor rings
711 * @dev: net device structure
712 * Description: this function initializes the DMA RX/TX descriptors
713 * and allocates the socket buffers.
715 static int xgmac_dma_desc_rings_init(struct net_device
*dev
)
717 struct xgmac_priv
*priv
= netdev_priv(dev
);
720 /* Set the Buffer size according to the MTU;
721 * The total buffer size including any IP offset must be a multiple
724 bfsize
= ALIGN(dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ NET_IP_ALIGN
, 8);
726 netdev_dbg(priv
->dev
, "mtu [%d] bfsize [%d]\n", dev
->mtu
, bfsize
);
728 priv
->rx_skbuff
= kzalloc(sizeof(struct sk_buff
*) * DMA_RX_RING_SZ
,
730 if (!priv
->rx_skbuff
)
733 priv
->dma_rx
= dma_alloc_coherent(priv
->device
,
735 sizeof(struct xgmac_dma_desc
),
741 priv
->tx_skbuff
= kzalloc(sizeof(struct sk_buff
*) * DMA_TX_RING_SZ
,
743 if (!priv
->tx_skbuff
)
746 priv
->dma_tx
= dma_alloc_coherent(priv
->device
,
748 sizeof(struct xgmac_dma_desc
),
754 netdev_dbg(priv
->dev
, "DMA desc rings: virt addr (Rx %p, "
755 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
756 priv
->dma_rx
, priv
->dma_tx
,
757 (unsigned int)priv
->dma_rx_phy
, (unsigned int)priv
->dma_tx_phy
);
761 priv
->dma_buf_sz
= bfsize
;
762 desc_init_rx_desc(priv
->dma_rx
, DMA_RX_RING_SZ
, priv
->dma_buf_sz
);
763 xgmac_rx_refill(priv
);
767 desc_init_tx_desc(priv
->dma_tx
, DMA_TX_RING_SZ
);
769 writel(priv
->dma_tx_phy
, priv
->base
+ XGMAC_DMA_TX_BASE_ADDR
);
770 writel(priv
->dma_rx_phy
, priv
->base
+ XGMAC_DMA_RX_BASE_ADDR
);
775 kfree(priv
->tx_skbuff
);
777 dma_free_coherent(priv
->device
,
778 DMA_RX_RING_SZ
* sizeof(struct xgmac_dma_desc
),
779 priv
->dma_rx
, priv
->dma_rx_phy
);
781 kfree(priv
->rx_skbuff
);
785 static void xgmac_free_rx_skbufs(struct xgmac_priv
*priv
)
788 struct xgmac_dma_desc
*p
;
790 if (!priv
->rx_skbuff
)
793 for (i
= 0; i
< DMA_RX_RING_SZ
; i
++) {
794 if (priv
->rx_skbuff
[i
] == NULL
)
797 p
= priv
->dma_rx
+ i
;
798 dma_unmap_single(priv
->device
, desc_get_buf_addr(p
),
799 priv
->dma_buf_sz
, DMA_FROM_DEVICE
);
800 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
801 priv
->rx_skbuff
[i
] = NULL
;
805 static void xgmac_free_tx_skbufs(struct xgmac_priv
*priv
)
808 struct xgmac_dma_desc
*p
;
810 if (!priv
->tx_skbuff
)
813 for (i
= 0; i
< DMA_TX_RING_SZ
; i
++) {
814 if (priv
->tx_skbuff
[i
] == NULL
)
817 p
= priv
->dma_tx
+ i
;
818 if (desc_get_tx_fs(p
))
819 dma_unmap_single(priv
->device
, desc_get_buf_addr(p
),
820 desc_get_buf_len(p
), DMA_TO_DEVICE
);
822 dma_unmap_page(priv
->device
, desc_get_buf_addr(p
),
823 desc_get_buf_len(p
), DMA_TO_DEVICE
);
825 if (desc_get_tx_ls(p
))
826 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
827 priv
->tx_skbuff
[i
] = NULL
;
831 static void xgmac_free_dma_desc_rings(struct xgmac_priv
*priv
)
833 /* Release the DMA TX/RX socket buffers */
834 xgmac_free_rx_skbufs(priv
);
835 xgmac_free_tx_skbufs(priv
);
837 /* Free the consistent memory allocated for descriptor rings */
839 dma_free_coherent(priv
->device
,
840 DMA_TX_RING_SZ
* sizeof(struct xgmac_dma_desc
),
841 priv
->dma_tx
, priv
->dma_tx_phy
);
845 dma_free_coherent(priv
->device
,
846 DMA_RX_RING_SZ
* sizeof(struct xgmac_dma_desc
),
847 priv
->dma_rx
, priv
->dma_rx_phy
);
850 kfree(priv
->rx_skbuff
);
851 priv
->rx_skbuff
= NULL
;
852 kfree(priv
->tx_skbuff
);
853 priv
->tx_skbuff
= NULL
;
858 * @priv: private driver structure
859 * Description: it reclaims resources after transmission completes.
861 static void xgmac_tx_complete(struct xgmac_priv
*priv
)
863 while (dma_ring_cnt(priv
->tx_head
, priv
->tx_tail
, DMA_TX_RING_SZ
)) {
864 unsigned int entry
= priv
->tx_tail
;
865 struct sk_buff
*skb
= priv
->tx_skbuff
[entry
];
866 struct xgmac_dma_desc
*p
= priv
->dma_tx
+ entry
;
868 /* Check if the descriptor is owned by the DMA. */
869 if (desc_get_owner(p
))
872 netdev_dbg(priv
->dev
, "tx ring: curr %d, dirty %d\n",
873 priv
->tx_head
, priv
->tx_tail
);
875 if (desc_get_tx_fs(p
))
876 dma_unmap_single(priv
->device
, desc_get_buf_addr(p
),
877 desc_get_buf_len(p
), DMA_TO_DEVICE
);
879 dma_unmap_page(priv
->device
, desc_get_buf_addr(p
),
880 desc_get_buf_len(p
), DMA_TO_DEVICE
);
882 /* Check tx error on the last segment */
883 if (desc_get_tx_ls(p
)) {
884 desc_get_tx_status(priv
, p
);
888 priv
->tx_skbuff
[entry
] = NULL
;
889 priv
->tx_tail
= dma_ring_incr(entry
, DMA_TX_RING_SZ
);
892 /* Ensure tx_tail is visible to xgmac_xmit */
894 if (unlikely(netif_queue_stopped(priv
->dev
) &&
895 (tx_dma_ring_space(priv
) > MAX_SKB_FRAGS
)))
896 netif_wake_queue(priv
->dev
);
899 static void xgmac_tx_timeout_work(struct work_struct
*work
)
902 struct xgmac_priv
*priv
=
903 container_of(work
, struct xgmac_priv
, tx_timeout_work
);
905 napi_disable(&priv
->napi
);
907 writel(0, priv
->base
+ XGMAC_DMA_INTR_ENA
);
909 netif_tx_lock(priv
->dev
);
911 reg
= readl(priv
->base
+ XGMAC_DMA_CONTROL
);
912 writel(reg
& ~DMA_CONTROL_ST
, priv
->base
+ XGMAC_DMA_CONTROL
);
914 value
= readl(priv
->base
+ XGMAC_DMA_STATUS
) & 0x700000;
915 } while (value
&& (value
!= 0x600000));
917 xgmac_free_tx_skbufs(priv
);
918 desc_init_tx_desc(priv
->dma_tx
, DMA_TX_RING_SZ
);
921 writel(priv
->dma_tx_phy
, priv
->base
+ XGMAC_DMA_TX_BASE_ADDR
);
922 writel(reg
| DMA_CONTROL_ST
, priv
->base
+ XGMAC_DMA_CONTROL
);
924 writel(DMA_STATUS_TU
| DMA_STATUS_TPS
| DMA_STATUS_NIS
| DMA_STATUS_AIS
,
925 priv
->base
+ XGMAC_DMA_STATUS
);
927 netif_tx_unlock(priv
->dev
);
928 netif_wake_queue(priv
->dev
);
930 napi_enable(&priv
->napi
);
932 /* Enable interrupts */
933 writel(DMA_INTR_DEFAULT_MASK
, priv
->base
+ XGMAC_DMA_STATUS
);
934 writel(DMA_INTR_DEFAULT_MASK
, priv
->base
+ XGMAC_DMA_INTR_ENA
);
937 static int xgmac_hw_init(struct net_device
*dev
)
941 struct xgmac_priv
*priv
= netdev_priv(dev
);
942 void __iomem
*ioaddr
= priv
->base
;
944 /* Save the ctrl register value */
945 ctrl
= readl(ioaddr
+ XGMAC_CONTROL
) & XGMAC_CONTROL_SPD_MASK
;
948 value
= DMA_BUS_MODE_SFT_RESET
;
949 writel(value
, ioaddr
+ XGMAC_DMA_BUS_MODE
);
952 (readl(ioaddr
+ XGMAC_DMA_BUS_MODE
) & DMA_BUS_MODE_SFT_RESET
))
957 value
= (0x10 << DMA_BUS_MODE_PBL_SHIFT
) |
958 (0x10 << DMA_BUS_MODE_RPBL_SHIFT
) |
959 DMA_BUS_MODE_FB
| DMA_BUS_MODE_ATDS
| DMA_BUS_MODE_AAL
;
960 writel(value
, ioaddr
+ XGMAC_DMA_BUS_MODE
);
962 /* Enable interrupts */
963 writel(DMA_INTR_DEFAULT_MASK
, ioaddr
+ XGMAC_DMA_STATUS
);
964 writel(DMA_INTR_DEFAULT_MASK
, ioaddr
+ XGMAC_DMA_INTR_ENA
);
966 /* Mask power mgt interrupt */
967 writel(XGMAC_INT_STAT_PMTIM
, ioaddr
+ XGMAC_INT_STAT
);
969 /* XGMAC requires AXI bus init. This is a 'magic number' for now */
970 writel(0x0077000E, ioaddr
+ XGMAC_DMA_AXI_BUS
);
972 ctrl
|= XGMAC_CONTROL_DDIC
| XGMAC_CONTROL_JE
| XGMAC_CONTROL_ACS
|
974 if (dev
->features
& NETIF_F_RXCSUM
)
975 ctrl
|= XGMAC_CONTROL_IPC
;
976 writel(ctrl
, ioaddr
+ XGMAC_CONTROL
);
978 writel(DMA_CONTROL_OSF
, ioaddr
+ XGMAC_DMA_CONTROL
);
980 /* Set the HW DMA mode and the COE */
981 writel(XGMAC_OMR_TSF
| XGMAC_OMR_RFD
| XGMAC_OMR_RFA
|
985 /* Reset the MMC counters */
986 writel(1, ioaddr
+ XGMAC_MMC_CTRL
);
991 * xgmac_open - open entry point of the driver
992 * @dev : pointer to the device structure.
994 * This function is the open entry point of the driver.
996 * 0 on success and an appropriate (-)ve integer as defined in errno.h
999 static int xgmac_open(struct net_device
*dev
)
1002 struct xgmac_priv
*priv
= netdev_priv(dev
);
1003 void __iomem
*ioaddr
= priv
->base
;
1005 /* Check that the MAC address is valid. If its not, refuse
1006 * to bring the device up. The user must specify an
1007 * address using the following linux command:
1008 * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */
1009 if (!is_valid_ether_addr(dev
->dev_addr
)) {
1010 eth_hw_addr_random(dev
);
1011 netdev_dbg(priv
->dev
, "generated random MAC address %pM\n",
1015 memset(&priv
->xstats
, 0, sizeof(struct xgmac_extra_stats
));
1017 /* Initialize the XGMAC and descriptors */
1019 xgmac_set_mac_addr(ioaddr
, dev
->dev_addr
, 0);
1020 xgmac_set_flow_ctrl(priv
, priv
->rx_pause
, priv
->tx_pause
);
1022 ret
= xgmac_dma_desc_rings_init(dev
);
1026 /* Enable the MAC Rx/Tx */
1027 xgmac_mac_enable(ioaddr
);
1029 napi_enable(&priv
->napi
);
1030 netif_start_queue(dev
);
1036 * xgmac_release - close entry point of the driver
1037 * @dev : device pointer.
1039 * This is the stop entry point of the driver.
1041 static int xgmac_stop(struct net_device
*dev
)
1043 struct xgmac_priv
*priv
= netdev_priv(dev
);
1045 netif_stop_queue(dev
);
1047 if (readl(priv
->base
+ XGMAC_DMA_INTR_ENA
))
1048 napi_disable(&priv
->napi
);
1050 writel(0, priv
->base
+ XGMAC_DMA_INTR_ENA
);
1052 /* Disable the MAC core */
1053 xgmac_mac_disable(priv
->base
);
1055 /* Release and free the Rx/Tx resources */
1056 xgmac_free_dma_desc_rings(priv
);
1063 * @skb : the socket buffer
1064 * @dev : device pointer
1065 * Description : Tx entry point of the driver.
1067 static netdev_tx_t
xgmac_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1069 struct xgmac_priv
*priv
= netdev_priv(dev
);
1073 int nfrags
= skb_shinfo(skb
)->nr_frags
;
1074 struct xgmac_dma_desc
*desc
, *first
;
1075 unsigned int desc_flags
;
1079 priv
->tx_irq_cnt
= (priv
->tx_irq_cnt
+ 1) & (DMA_TX_RING_SZ
/4 - 1);
1080 irq_flag
= priv
->tx_irq_cnt
? 0 : TXDESC_INTERRUPT
;
1082 desc_flags
= (skb
->ip_summed
== CHECKSUM_PARTIAL
) ?
1083 TXDESC_CSUM_ALL
: 0;
1084 entry
= priv
->tx_head
;
1085 desc
= priv
->dma_tx
+ entry
;
1088 len
= skb_headlen(skb
);
1089 paddr
= dma_map_single(priv
->device
, skb
->data
, len
, DMA_TO_DEVICE
);
1090 if (dma_mapping_error(priv
->device
, paddr
)) {
1094 priv
->tx_skbuff
[entry
] = skb
;
1095 desc_set_buf_addr_and_size(desc
, paddr
, len
);
1097 for (i
= 0; i
< nfrags
; i
++) {
1098 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1102 paddr
= skb_frag_dma_map(priv
->device
, frag
, 0, len
,
1104 if (dma_mapping_error(priv
->device
, paddr
)) {
1109 entry
= dma_ring_incr(entry
, DMA_TX_RING_SZ
);
1110 desc
= priv
->dma_tx
+ entry
;
1111 priv
->tx_skbuff
[entry
] = skb
;
1113 desc_set_buf_addr_and_size(desc
, paddr
, len
);
1114 if (i
< (nfrags
- 1))
1115 desc_set_tx_owner(desc
, desc_flags
);
1118 /* Interrupt on completition only for the latest segment */
1120 desc_set_tx_owner(desc
, desc_flags
|
1121 TXDESC_LAST_SEG
| irq_flag
);
1123 desc_flags
|= TXDESC_LAST_SEG
| irq_flag
;
1125 /* Set owner on first desc last to avoid race condition */
1127 desc_set_tx_owner(first
, desc_flags
| TXDESC_FIRST_SEG
);
1129 writel(1, priv
->base
+ XGMAC_DMA_TX_POLL
);
1131 priv
->tx_head
= dma_ring_incr(entry
, DMA_TX_RING_SZ
);
1133 /* Ensure tx_head update is visible to tx completion */
1135 if (unlikely(tx_dma_ring_space(priv
) <= MAX_SKB_FRAGS
)) {
1136 netif_stop_queue(dev
);
1137 /* Ensure netif_stop_queue is visible to tx completion */
1139 if (tx_dma_ring_space(priv
) > MAX_SKB_FRAGS
)
1140 netif_start_queue(dev
);
1142 return NETDEV_TX_OK
;
1145 static int xgmac_rx(struct xgmac_priv
*priv
, int limit
)
1148 unsigned int count
= 0;
1149 struct xgmac_dma_desc
*p
;
1151 while (count
< limit
) {
1153 struct sk_buff
*skb
;
1156 if (!dma_ring_cnt(priv
->rx_head
, priv
->rx_tail
, DMA_RX_RING_SZ
))
1159 entry
= priv
->rx_tail
;
1160 p
= priv
->dma_rx
+ entry
;
1161 if (desc_get_owner(p
))
1165 priv
->rx_tail
= dma_ring_incr(priv
->rx_tail
, DMA_RX_RING_SZ
);
1167 /* read the status of the incoming frame */
1168 ip_checksum
= desc_get_rx_status(priv
, p
);
1169 if (ip_checksum
< 0)
1172 skb
= priv
->rx_skbuff
[entry
];
1173 if (unlikely(!skb
)) {
1174 netdev_err(priv
->dev
, "Inconsistent Rx descriptor chain\n");
1177 priv
->rx_skbuff
[entry
] = NULL
;
1179 frame_len
= desc_get_rx_frame_len(p
);
1180 netdev_dbg(priv
->dev
, "RX frame size %d, COE status: %d\n",
1181 frame_len
, ip_checksum
);
1183 skb_put(skb
, frame_len
);
1184 dma_unmap_single(priv
->device
, desc_get_buf_addr(p
),
1185 frame_len
, DMA_FROM_DEVICE
);
1187 skb
->protocol
= eth_type_trans(skb
, priv
->dev
);
1188 skb
->ip_summed
= ip_checksum
;
1189 if (ip_checksum
== CHECKSUM_NONE
)
1190 netif_receive_skb(skb
);
1192 napi_gro_receive(&priv
->napi
, skb
);
1195 xgmac_rx_refill(priv
);
1201 * xgmac_poll - xgmac poll method (NAPI)
1202 * @napi : pointer to the napi structure.
1203 * @budget : maximum number of packets that the current CPU can receive from
1206 * This function implements the the reception process.
1207 * Also it runs the TX completion thread
1209 static int xgmac_poll(struct napi_struct
*napi
, int budget
)
1211 struct xgmac_priv
*priv
= container_of(napi
,
1212 struct xgmac_priv
, napi
);
1215 xgmac_tx_complete(priv
);
1216 work_done
= xgmac_rx(priv
, budget
);
1218 if (work_done
< budget
) {
1219 napi_complete(napi
);
1220 __raw_writel(DMA_INTR_DEFAULT_MASK
, priv
->base
+ XGMAC_DMA_INTR_ENA
);
1227 * @dev : Pointer to net device structure
1228 * Description: this function is called when a packet transmission fails to
1229 * complete within a reasonable tmrate. The driver will mark the error in the
1230 * netdev structure and arrange for the device to be reset to a sane state
1231 * in order to transmit a new packet.
1233 static void xgmac_tx_timeout(struct net_device
*dev
)
1235 struct xgmac_priv
*priv
= netdev_priv(dev
);
1236 schedule_work(&priv
->tx_timeout_work
);
1240 * xgmac_set_rx_mode - entry point for multicast addressing
1241 * @dev : pointer to the device structure
1243 * This function is a driver entry point which gets called by the kernel
1244 * whenever multicast addresses must be enabled/disabled.
1248 static void xgmac_set_rx_mode(struct net_device
*dev
)
1251 struct xgmac_priv
*priv
= netdev_priv(dev
);
1252 void __iomem
*ioaddr
= priv
->base
;
1253 unsigned int value
= 0;
1254 u32 hash_filter
[XGMAC_NUM_HASH
];
1256 struct netdev_hw_addr
*ha
;
1257 bool use_hash
= false;
1259 netdev_dbg(priv
->dev
, "# mcasts %d, # unicast %d\n",
1260 netdev_mc_count(dev
), netdev_uc_count(dev
));
1262 if (dev
->flags
& IFF_PROMISC
) {
1263 writel(XGMAC_FRAME_FILTER_PR
, ioaddr
+ XGMAC_FRAME_FILTER
);
1267 memset(hash_filter
, 0, sizeof(hash_filter
));
1269 if (netdev_uc_count(dev
) > XGMAC_MAX_FILTER_ADDR
) {
1271 value
|= XGMAC_FRAME_FILTER_HUC
| XGMAC_FRAME_FILTER_HPF
;
1273 netdev_for_each_uc_addr(ha
, dev
) {
1275 u32 bit_nr
= ~ether_crc(ETH_ALEN
, ha
->addr
) >> 23;
1277 /* The most significant 4 bits determine the register to
1278 * use (H/L) while the other 5 bits determine the bit
1279 * within the register. */
1280 hash_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
1282 xgmac_set_mac_addr(ioaddr
, ha
->addr
, reg
);
1287 if (dev
->flags
& IFF_ALLMULTI
) {
1288 value
|= XGMAC_FRAME_FILTER_PM
;
1292 if ((netdev_mc_count(dev
) + reg
- 1) > XGMAC_MAX_FILTER_ADDR
) {
1294 value
|= XGMAC_FRAME_FILTER_HMC
| XGMAC_FRAME_FILTER_HPF
;
1296 netdev_for_each_mc_addr(ha
, dev
) {
1298 u32 bit_nr
= ~ether_crc(ETH_ALEN
, ha
->addr
) >> 23;
1300 /* The most significant 4 bits determine the register to
1301 * use (H/L) while the other 5 bits determine the bit
1302 * within the register. */
1303 hash_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
1305 xgmac_set_mac_addr(ioaddr
, ha
->addr
, reg
);
1311 for (i
= 0; i
< XGMAC_NUM_HASH
; i
++)
1312 writel(hash_filter
[i
], ioaddr
+ XGMAC_HASH(i
));
1314 writel(value
, ioaddr
+ XGMAC_FRAME_FILTER
);
1318 * xgmac_change_mtu - entry point to change MTU size for the device.
1319 * @dev : device pointer.
1320 * @new_mtu : the new MTU size for the device.
1321 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1322 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1323 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1325 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1328 static int xgmac_change_mtu(struct net_device
*dev
, int new_mtu
)
1330 struct xgmac_priv
*priv
= netdev_priv(dev
);
1333 if ((new_mtu
< 46) || (new_mtu
> MAX_MTU
)) {
1334 netdev_err(priv
->dev
, "invalid MTU, max MTU is: %d\n", MAX_MTU
);
1341 /* return early if the buffer sizes will not change */
1342 if (old_mtu
<= ETH_DATA_LEN
&& new_mtu
<= ETH_DATA_LEN
)
1344 if (old_mtu
== new_mtu
)
1347 /* Stop everything, get ready to change the MTU */
1348 if (!netif_running(dev
))
1351 /* Bring the interface down and then back up */
1353 return xgmac_open(dev
);
1356 static irqreturn_t
xgmac_pmt_interrupt(int irq
, void *dev_id
)
1359 struct net_device
*dev
= (struct net_device
*)dev_id
;
1360 struct xgmac_priv
*priv
= netdev_priv(dev
);
1361 void __iomem
*ioaddr
= priv
->base
;
1363 intr_status
= __raw_readl(ioaddr
+ XGMAC_INT_STAT
);
1364 if (intr_status
& XGMAC_INT_STAT_PMT
) {
1365 netdev_dbg(priv
->dev
, "received Magic frame\n");
1366 /* clear the PMT bits 5 and 6 by reading the PMT */
1367 readl(ioaddr
+ XGMAC_PMT
);
1372 static irqreturn_t
xgmac_interrupt(int irq
, void *dev_id
)
1375 struct net_device
*dev
= (struct net_device
*)dev_id
;
1376 struct xgmac_priv
*priv
= netdev_priv(dev
);
1377 struct xgmac_extra_stats
*x
= &priv
->xstats
;
1379 /* read the status register (CSR5) */
1380 intr_status
= __raw_readl(priv
->base
+ XGMAC_DMA_STATUS
);
1381 intr_status
&= __raw_readl(priv
->base
+ XGMAC_DMA_INTR_ENA
);
1382 __raw_writel(intr_status
, priv
->base
+ XGMAC_DMA_STATUS
);
1384 /* It displays the DMA process states (CSR5 register) */
1385 /* ABNORMAL interrupts */
1386 if (unlikely(intr_status
& DMA_STATUS_AIS
)) {
1387 if (intr_status
& DMA_STATUS_TJT
) {
1388 netdev_err(priv
->dev
, "transmit jabber\n");
1391 if (intr_status
& DMA_STATUS_RU
)
1393 if (intr_status
& DMA_STATUS_RPS
) {
1394 netdev_err(priv
->dev
, "receive process stopped\n");
1395 x
->rx_process_stopped
++;
1397 if (intr_status
& DMA_STATUS_ETI
) {
1398 netdev_err(priv
->dev
, "transmit early interrupt\n");
1401 if (intr_status
& DMA_STATUS_TPS
) {
1402 netdev_err(priv
->dev
, "transmit process stopped\n");
1403 x
->tx_process_stopped
++;
1404 schedule_work(&priv
->tx_timeout_work
);
1406 if (intr_status
& DMA_STATUS_FBI
) {
1407 netdev_err(priv
->dev
, "fatal bus error\n");
1408 x
->fatal_bus_error
++;
1412 /* TX/RX NORMAL interrupts */
1413 if (intr_status
& (DMA_STATUS_RI
| DMA_STATUS_TU
| DMA_STATUS_TI
)) {
1414 __raw_writel(DMA_INTR_ABNORMAL
, priv
->base
+ XGMAC_DMA_INTR_ENA
);
1415 napi_schedule(&priv
->napi
);
1421 #ifdef CONFIG_NET_POLL_CONTROLLER
1422 /* Polling receive - used by NETCONSOLE and other diagnostic tools
1423 * to allow network I/O with interrupts disabled. */
1424 static void xgmac_poll_controller(struct net_device
*dev
)
1426 disable_irq(dev
->irq
);
1427 xgmac_interrupt(dev
->irq
, dev
);
1428 enable_irq(dev
->irq
);
1432 static struct rtnl_link_stats64
*
1433 xgmac_get_stats64(struct net_device
*dev
,
1434 struct rtnl_link_stats64
*storage
)
1436 struct xgmac_priv
*priv
= netdev_priv(dev
);
1437 void __iomem
*base
= priv
->base
;
1440 spin_lock_bh(&priv
->stats_lock
);
1441 writel(XGMAC_MMC_CTRL_CNT_FRZ
, base
+ XGMAC_MMC_CTRL
);
1443 storage
->rx_bytes
= readl(base
+ XGMAC_MMC_RXOCTET_G_LO
);
1444 storage
->rx_bytes
|= (u64
)(readl(base
+ XGMAC_MMC_RXOCTET_G_HI
)) << 32;
1446 storage
->rx_packets
= readl(base
+ XGMAC_MMC_RXFRAME_GB_LO
);
1447 storage
->multicast
= readl(base
+ XGMAC_MMC_RXMCFRAME_G
);
1448 storage
->rx_crc_errors
= readl(base
+ XGMAC_MMC_RXCRCERR
);
1449 storage
->rx_length_errors
= readl(base
+ XGMAC_MMC_RXLENGTHERR
);
1450 storage
->rx_missed_errors
= readl(base
+ XGMAC_MMC_RXOVERFLOW
);
1452 storage
->tx_bytes
= readl(base
+ XGMAC_MMC_TXOCTET_G_LO
);
1453 storage
->tx_bytes
|= (u64
)(readl(base
+ XGMAC_MMC_TXOCTET_G_HI
)) << 32;
1455 count
= readl(base
+ XGMAC_MMC_TXFRAME_GB_LO
);
1456 storage
->tx_errors
= count
- readl(base
+ XGMAC_MMC_TXFRAME_G_LO
);
1457 storage
->tx_packets
= count
;
1458 storage
->tx_fifo_errors
= readl(base
+ XGMAC_MMC_TXUNDERFLOW
);
1460 writel(0, base
+ XGMAC_MMC_CTRL
);
1461 spin_unlock_bh(&priv
->stats_lock
);
1465 static int xgmac_set_mac_address(struct net_device
*dev
, void *p
)
1467 struct xgmac_priv
*priv
= netdev_priv(dev
);
1468 void __iomem
*ioaddr
= priv
->base
;
1469 struct sockaddr
*addr
= p
;
1471 if (!is_valid_ether_addr(addr
->sa_data
))
1472 return -EADDRNOTAVAIL
;
1474 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
1476 xgmac_set_mac_addr(ioaddr
, dev
->dev_addr
, 0);
1481 static int xgmac_set_features(struct net_device
*dev
, netdev_features_t features
)
1484 struct xgmac_priv
*priv
= netdev_priv(dev
);
1485 void __iomem
*ioaddr
= priv
->base
;
1486 netdev_features_t changed
= dev
->features
^ features
;
1488 if (!(changed
& NETIF_F_RXCSUM
))
1491 ctrl
= readl(ioaddr
+ XGMAC_CONTROL
);
1492 if (features
& NETIF_F_RXCSUM
)
1493 ctrl
|= XGMAC_CONTROL_IPC
;
1495 ctrl
&= ~XGMAC_CONTROL_IPC
;
1496 writel(ctrl
, ioaddr
+ XGMAC_CONTROL
);
1501 static const struct net_device_ops xgmac_netdev_ops
= {
1502 .ndo_open
= xgmac_open
,
1503 .ndo_start_xmit
= xgmac_xmit
,
1504 .ndo_stop
= xgmac_stop
,
1505 .ndo_change_mtu
= xgmac_change_mtu
,
1506 .ndo_set_rx_mode
= xgmac_set_rx_mode
,
1507 .ndo_tx_timeout
= xgmac_tx_timeout
,
1508 .ndo_get_stats64
= xgmac_get_stats64
,
1509 #ifdef CONFIG_NET_POLL_CONTROLLER
1510 .ndo_poll_controller
= xgmac_poll_controller
,
1512 .ndo_set_mac_address
= xgmac_set_mac_address
,
1513 .ndo_set_features
= xgmac_set_features
,
1516 static int xgmac_ethtool_getsettings(struct net_device
*dev
,
1517 struct ethtool_cmd
*cmd
)
1520 cmd
->duplex
= DUPLEX_FULL
;
1521 ethtool_cmd_speed_set(cmd
, 10000);
1523 cmd
->advertising
= 0;
1524 cmd
->transceiver
= XCVR_INTERNAL
;
1528 static void xgmac_get_pauseparam(struct net_device
*netdev
,
1529 struct ethtool_pauseparam
*pause
)
1531 struct xgmac_priv
*priv
= netdev_priv(netdev
);
1533 pause
->rx_pause
= priv
->rx_pause
;
1534 pause
->tx_pause
= priv
->tx_pause
;
1537 static int xgmac_set_pauseparam(struct net_device
*netdev
,
1538 struct ethtool_pauseparam
*pause
)
1540 struct xgmac_priv
*priv
= netdev_priv(netdev
);
1545 return xgmac_set_flow_ctrl(priv
, pause
->rx_pause
, pause
->tx_pause
);
1548 struct xgmac_stats
{
1549 char stat_string
[ETH_GSTRING_LEN
];
1554 #define XGMAC_STAT(m) \
1555 { #m, offsetof(struct xgmac_priv, xstats.m), false }
1556 #define XGMAC_HW_STAT(m, reg_offset) \
1557 { #m, reg_offset, true }
1559 static const struct xgmac_stats xgmac_gstrings_stats
[] = {
1560 XGMAC_STAT(tx_frame_flushed
),
1561 XGMAC_STAT(tx_payload_error
),
1562 XGMAC_STAT(tx_ip_header_error
),
1563 XGMAC_STAT(tx_local_fault
),
1564 XGMAC_STAT(tx_remote_fault
),
1565 XGMAC_STAT(tx_early
),
1566 XGMAC_STAT(tx_process_stopped
),
1567 XGMAC_STAT(tx_jabber
),
1568 XGMAC_STAT(rx_buf_unav
),
1569 XGMAC_STAT(rx_process_stopped
),
1570 XGMAC_STAT(rx_payload_error
),
1571 XGMAC_STAT(rx_ip_header_error
),
1572 XGMAC_STAT(rx_da_filter_fail
),
1573 XGMAC_STAT(rx_sa_filter_fail
),
1574 XGMAC_STAT(fatal_bus_error
),
1575 XGMAC_HW_STAT(rx_watchdog
, XGMAC_MMC_RXWATCHDOG
),
1576 XGMAC_HW_STAT(tx_vlan
, XGMAC_MMC_TXVLANFRAME
),
1577 XGMAC_HW_STAT(rx_vlan
, XGMAC_MMC_RXVLANFRAME
),
1578 XGMAC_HW_STAT(tx_pause
, XGMAC_MMC_TXPAUSEFRAME
),
1579 XGMAC_HW_STAT(rx_pause
, XGMAC_MMC_RXPAUSEFRAME
),
1581 #define XGMAC_STATS_LEN ARRAY_SIZE(xgmac_gstrings_stats)
1583 static void xgmac_get_ethtool_stats(struct net_device
*dev
,
1584 struct ethtool_stats
*dummy
,
1587 struct xgmac_priv
*priv
= netdev_priv(dev
);
1591 for (i
= 0; i
< XGMAC_STATS_LEN
; i
++) {
1592 if (xgmac_gstrings_stats
[i
].is_reg
)
1593 *data
++ = readl(priv
->base
+
1594 xgmac_gstrings_stats
[i
].stat_offset
);
1596 *data
++ = *(u32
*)(p
+
1597 xgmac_gstrings_stats
[i
].stat_offset
);
1601 static int xgmac_get_sset_count(struct net_device
*netdev
, int sset
)
1605 return XGMAC_STATS_LEN
;
1611 static void xgmac_get_strings(struct net_device
*dev
, u32 stringset
,
1617 switch (stringset
) {
1619 for (i
= 0; i
< XGMAC_STATS_LEN
; i
++) {
1620 memcpy(p
, xgmac_gstrings_stats
[i
].stat_string
,
1622 p
+= ETH_GSTRING_LEN
;
1631 static void xgmac_get_wol(struct net_device
*dev
,
1632 struct ethtool_wolinfo
*wol
)
1634 struct xgmac_priv
*priv
= netdev_priv(dev
);
1636 if (device_can_wakeup(priv
->device
)) {
1637 wol
->supported
= WAKE_MAGIC
| WAKE_UCAST
;
1638 wol
->wolopts
= priv
->wolopts
;
1642 static int xgmac_set_wol(struct net_device
*dev
,
1643 struct ethtool_wolinfo
*wol
)
1645 struct xgmac_priv
*priv
= netdev_priv(dev
);
1646 u32 support
= WAKE_MAGIC
| WAKE_UCAST
;
1648 if (!device_can_wakeup(priv
->device
))
1651 if (wol
->wolopts
& ~support
)
1654 priv
->wolopts
= wol
->wolopts
;
1657 device_set_wakeup_enable(priv
->device
, 1);
1658 enable_irq_wake(dev
->irq
);
1660 device_set_wakeup_enable(priv
->device
, 0);
1661 disable_irq_wake(dev
->irq
);
1667 static const struct ethtool_ops xgmac_ethtool_ops
= {
1668 .get_settings
= xgmac_ethtool_getsettings
,
1669 .get_link
= ethtool_op_get_link
,
1670 .get_pauseparam
= xgmac_get_pauseparam
,
1671 .set_pauseparam
= xgmac_set_pauseparam
,
1672 .get_ethtool_stats
= xgmac_get_ethtool_stats
,
1673 .get_strings
= xgmac_get_strings
,
1674 .get_wol
= xgmac_get_wol
,
1675 .set_wol
= xgmac_set_wol
,
1676 .get_sset_count
= xgmac_get_sset_count
,
1681 * @pdev: platform device pointer
1682 * Description: the driver is initialized through platform_device.
1684 static int xgmac_probe(struct platform_device
*pdev
)
1687 struct resource
*res
;
1688 struct net_device
*ndev
= NULL
;
1689 struct xgmac_priv
*priv
= NULL
;
1692 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1696 if (!request_mem_region(res
->start
, resource_size(res
), pdev
->name
))
1699 ndev
= alloc_etherdev(sizeof(struct xgmac_priv
));
1705 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
1706 priv
= netdev_priv(ndev
);
1707 platform_set_drvdata(pdev
, ndev
);
1709 ndev
->netdev_ops
= &xgmac_netdev_ops
;
1710 SET_ETHTOOL_OPS(ndev
, &xgmac_ethtool_ops
);
1711 spin_lock_init(&priv
->stats_lock
);
1712 INIT_WORK(&priv
->tx_timeout_work
, xgmac_tx_timeout_work
);
1714 priv
->device
= &pdev
->dev
;
1719 priv
->base
= ioremap(res
->start
, resource_size(res
));
1721 netdev_err(ndev
, "ioremap failed\n");
1726 uid
= readl(priv
->base
+ XGMAC_VERSION
);
1727 netdev_info(ndev
, "h/w version is 0x%x\n", uid
);
1729 writel(0, priv
->base
+ XGMAC_DMA_INTR_ENA
);
1730 ndev
->irq
= platform_get_irq(pdev
, 0);
1731 if (ndev
->irq
== -ENXIO
) {
1732 netdev_err(ndev
, "No irq resource\n");
1737 ret
= request_irq(ndev
->irq
, xgmac_interrupt
, 0,
1738 dev_name(&pdev
->dev
), ndev
);
1740 netdev_err(ndev
, "Could not request irq %d - ret %d)\n",
1745 priv
->pmt_irq
= platform_get_irq(pdev
, 1);
1746 if (priv
->pmt_irq
== -ENXIO
) {
1747 netdev_err(ndev
, "No pmt irq resource\n");
1748 ret
= priv
->pmt_irq
;
1752 ret
= request_irq(priv
->pmt_irq
, xgmac_pmt_interrupt
, 0,
1753 dev_name(&pdev
->dev
), ndev
);
1755 netdev_err(ndev
, "Could not request irq %d - ret %d)\n",
1756 priv
->pmt_irq
, ret
);
1760 device_set_wakeup_capable(&pdev
->dev
, 1);
1761 if (device_can_wakeup(priv
->device
))
1762 priv
->wolopts
= WAKE_MAGIC
; /* Magic Frame as default */
1764 ndev
->hw_features
= NETIF_F_SG
| NETIF_F_HIGHDMA
;
1765 if (readl(priv
->base
+ XGMAC_DMA_HW_FEATURE
) & DMA_HW_FEAT_TXCOESEL
)
1766 ndev
->hw_features
|= NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
1768 ndev
->features
|= ndev
->hw_features
;
1769 ndev
->priv_flags
|= IFF_UNICAST_FLT
;
1771 /* Get the MAC address */
1772 xgmac_get_mac_addr(priv
->base
, ndev
->dev_addr
, 0);
1773 if (!is_valid_ether_addr(ndev
->dev_addr
))
1774 netdev_warn(ndev
, "MAC address %pM not valid",
1777 netif_napi_add(ndev
, &priv
->napi
, xgmac_poll
, 64);
1778 ret
= register_netdev(ndev
);
1785 netif_napi_del(&priv
->napi
);
1786 free_irq(priv
->pmt_irq
, ndev
);
1788 free_irq(ndev
->irq
, ndev
);
1790 iounmap(priv
->base
);
1794 release_mem_region(res
->start
, resource_size(res
));
1800 * @pdev: platform device pointer
1801 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1802 * changes the link status, releases the DMA descriptor rings,
1803 * unregisters the MDIO bus and unmaps the allocated memory.
1805 static int xgmac_remove(struct platform_device
*pdev
)
1807 struct net_device
*ndev
= platform_get_drvdata(pdev
);
1808 struct xgmac_priv
*priv
= netdev_priv(ndev
);
1809 struct resource
*res
;
1811 xgmac_mac_disable(priv
->base
);
1813 /* Free the IRQ lines */
1814 free_irq(ndev
->irq
, ndev
);
1815 free_irq(priv
->pmt_irq
, ndev
);
1817 unregister_netdev(ndev
);
1818 netif_napi_del(&priv
->napi
);
1820 iounmap(priv
->base
);
1821 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1822 release_mem_region(res
->start
, resource_size(res
));
1829 #ifdef CONFIG_PM_SLEEP
1830 static void xgmac_pmt(void __iomem
*ioaddr
, unsigned long mode
)
1832 unsigned int pmt
= 0;
1834 if (mode
& WAKE_MAGIC
)
1835 pmt
|= XGMAC_PMT_POWERDOWN
| XGMAC_PMT_MAGIC_PKT_EN
;
1836 if (mode
& WAKE_UCAST
)
1837 pmt
|= XGMAC_PMT_POWERDOWN
| XGMAC_PMT_GLBL_UNICAST
;
1839 writel(pmt
, ioaddr
+ XGMAC_PMT
);
1842 static int xgmac_suspend(struct device
*dev
)
1844 struct net_device
*ndev
= platform_get_drvdata(to_platform_device(dev
));
1845 struct xgmac_priv
*priv
= netdev_priv(ndev
);
1848 if (!ndev
|| !netif_running(ndev
))
1851 netif_device_detach(ndev
);
1852 napi_disable(&priv
->napi
);
1853 writel(0, priv
->base
+ XGMAC_DMA_INTR_ENA
);
1855 if (device_may_wakeup(priv
->device
)) {
1856 /* Stop TX/RX DMA Only */
1857 value
= readl(priv
->base
+ XGMAC_DMA_CONTROL
);
1858 value
&= ~(DMA_CONTROL_ST
| DMA_CONTROL_SR
);
1859 writel(value
, priv
->base
+ XGMAC_DMA_CONTROL
);
1861 xgmac_pmt(priv
->base
, priv
->wolopts
);
1863 xgmac_mac_disable(priv
->base
);
1868 static int xgmac_resume(struct device
*dev
)
1870 struct net_device
*ndev
= platform_get_drvdata(to_platform_device(dev
));
1871 struct xgmac_priv
*priv
= netdev_priv(ndev
);
1872 void __iomem
*ioaddr
= priv
->base
;
1874 if (!netif_running(ndev
))
1877 xgmac_pmt(ioaddr
, 0);
1879 /* Enable the MAC and DMA */
1880 xgmac_mac_enable(ioaddr
);
1881 writel(DMA_INTR_DEFAULT_MASK
, ioaddr
+ XGMAC_DMA_STATUS
);
1882 writel(DMA_INTR_DEFAULT_MASK
, ioaddr
+ XGMAC_DMA_INTR_ENA
);
1884 netif_device_attach(ndev
);
1885 napi_enable(&priv
->napi
);
1889 #endif /* CONFIG_PM_SLEEP */
1891 static SIMPLE_DEV_PM_OPS(xgmac_pm_ops
, xgmac_suspend
, xgmac_resume
);
1893 static const struct of_device_id xgmac_of_match
[] = {
1894 { .compatible
= "calxeda,hb-xgmac", },
1897 MODULE_DEVICE_TABLE(of
, xgmac_of_match
);
1899 static struct platform_driver xgmac_driver
= {
1901 .name
= "calxedaxgmac",
1902 .of_match_table
= xgmac_of_match
,
1904 .probe
= xgmac_probe
,
1905 .remove
= xgmac_remove
,
1906 .driver
.pm
= &xgmac_pm_ops
,
1909 module_platform_driver(xgmac_driver
);
1911 MODULE_AUTHOR("Calxeda, Inc.");
1912 MODULE_DESCRIPTION("Calxeda 10G XGMAC driver");
1913 MODULE_LICENSE("GPL v2");