drivers/net/ethernet/cavium/liquidio/octeon_config.h

   1 /**********************************************************************
   2  * Author: Cavium, Inc.
   3  *
   4  * Contact: support@cavium.com
   5  *          Please include "LiquidIO" in the subject.
   6  *
   7  * Copyright (c) 2003-2016 Cavium, Inc.
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more details.
  17  ***********************************************************************/
  18 /*! \file  octeon_config.h
  19  *  \brief Host Driver: Configuration data structures for the host driver.
  20  */
  21
  22 #ifndef __OCTEON_CONFIG_H__
  23 #define __OCTEON_CONFIG_H__
  24
  25 /*--------------------------CONFIG VALUES------------------------*/
  26
  27 /* The following macros affect the way the driver data structures
  28  * are generated for Octeon devices.
  29  * They can be modified.
  30  */
  31
  32 /* Maximum octeon devices defined as MAX_OCTEON_NICIF to support
  33  * multiple(<= MAX_OCTEON_NICIF) Miniports
  34  */
  35 #define   MAX_OCTEON_NICIF             128
  36 #define   MAX_OCTEON_DEVICES           MAX_OCTEON_NICIF
  37 #define   MAX_OCTEON_LINKS             MAX_OCTEON_NICIF
  38 #define   MAX_OCTEON_MULTICAST_ADDR    32
  39
  40 /* CN6xxx IQ configuration macros */
  41 #define   CN6XXX_MAX_INPUT_QUEUES      32
  42 #define   CN6XXX_MAX_IQ_DESCRIPTORS    2048
  43 #define   CN6XXX_DB_MIN                1
  44 #define   CN6XXX_DB_MAX                8
  45 #define   CN6XXX_DB_TIMEOUT            1
  46
  47 /* CN6xxx OQ configuration macros */
  48 #define   CN6XXX_MAX_OUTPUT_QUEUES     32
  49 #define   CN6XXX_MAX_OQ_DESCRIPTORS    2048
  50 #define   CN6XXX_OQ_BUF_SIZE           1664
  51 #define   CN6XXX_OQ_PKTSPER_INTR       ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \
  52                                         (CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128)
  53 #define   CN6XXX_OQ_REFIL_THRESHOLD    ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \
  54                                         (CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128)
  55
  56 #define   CN6XXX_OQ_INTR_PKT           64
  57 #define   CN6XXX_OQ_INTR_TIME          100
  58 #define   DEFAULT_NUM_NIC_PORTS_66XX   2
  59 #define   DEFAULT_NUM_NIC_PORTS_68XX   4
  60 #define   DEFAULT_NUM_NIC_PORTS_68XX_210NV  2
  61
  62 /* CN23xx  IQ configuration macros */
  63 #define   CN23XX_MAX_VFS_PER_PF_PASS_1_0 8
  64 #define   CN23XX_MAX_VFS_PER_PF_PASS_1_1 31
  65 #define   CN23XX_MAX_VFS_PER_PF          63
  66 #define   CN23XX_MAX_RINGS_PER_VF        8
  67
  68 #define   CN23XX_MAX_RINGS_PER_PF_PASS_1_0 12
  69 #define   CN23XX_MAX_RINGS_PER_PF_PASS_1_1 32
  70 #define   CN23XX_MAX_RINGS_PER_PF          64
  71 #define   CN23XX_MAX_RINGS_PER_VF          8
  72
  73 #define   CN23XX_MAX_INPUT_QUEUES       CN23XX_MAX_RINGS_PER_PF
  74 #define   CN23XX_MAX_IQ_DESCRIPTORS     512
  75 #define   CN23XX_DB_MIN                 1
  76 #define   CN23XX_DB_MAX                 8
  77 #define   CN23XX_DB_TIMEOUT             1
  78
  79 #define   CN23XX_MAX_OUTPUT_QUEUES      CN23XX_MAX_RINGS_PER_PF
  80 #define   CN23XX_MAX_OQ_DESCRIPTORS     512
  81 #define   CN23XX_OQ_BUF_SIZE            1664
  82 #define   CN23XX_OQ_PKTSPER_INTR        128
  83 /*#define CAVIUM_ONLY_CN23XX_RX_PERF*/
  84 #define   CN23XX_OQ_REFIL_THRESHOLD     16
  85
  86 #define   CN23XX_OQ_INTR_PKT            64
  87 #define   CN23XX_OQ_INTR_TIME           100
  88 #define   DEFAULT_NUM_NIC_PORTS_23XX    1
  89
  90 #define   CN23XX_CFG_IO_QUEUES          CN23XX_MAX_RINGS_PER_PF
  91 /* PEMs count */
  92 #define   CN23XX_MAX_MACS               4
  93
  94 #define   CN23XX_DEF_IQ_INTR_THRESHOLD  32
  95 #define   CN23XX_DEF_IQ_INTR_BYTE_THRESHOLD   (64 * 1024)
  96 /* common OCTEON configuration macros */
  97 #define   CN6XXX_CFG_IO_QUEUES         32
  98 #define   OCTEON_32BYTE_INSTR          32
  99 #define   OCTEON_64BYTE_INSTR          64
 100 #define   OCTEON_MAX_BASE_IOQ          4
 101
 102 #define   OCTEON_DMA_INTR_PKT          64
 103 #define   OCTEON_DMA_INTR_TIME         1000
 104
 105 #define MAX_TXQS_PER_INTF  8
 106 #define MAX_RXQS_PER_INTF  8
 107 #define DEF_TXQS_PER_INTF  4
 108 #define DEF_RXQS_PER_INTF  4
 109
 110 #define INVALID_IOQ_NO          0xff
 111
 112 #define   DEFAULT_POW_GRP       0
 113
 114 /* Macros to get octeon config params */
 115 #define CFG_GET_IQ_CFG(cfg)                      ((cfg)->iq)
 116 #define CFG_GET_IQ_MAX_Q(cfg)                    ((cfg)->iq.max_iqs)
 117 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg)        ((cfg)->iq.pending_list_size)
 118 #define CFG_GET_IQ_INSTR_TYPE(cfg)               ((cfg)->iq.instr_type)
 119 #define CFG_GET_IQ_DB_MIN(cfg)                   ((cfg)->iq.db_min)
 120 #define CFG_GET_IQ_DB_TIMEOUT(cfg)               ((cfg)->iq.db_timeout)
 121
 122 #define CFG_GET_IQ_INTR_PKT(cfg)                 ((cfg)->iq.iq_intr_pkt)
 123 #define CFG_SET_IQ_INTR_PKT(cfg, val)            (cfg)->iq.iq_intr_pkt = val
 124
 125 #define CFG_GET_OQ_MAX_Q(cfg)                    ((cfg)->oq.max_oqs)
 126 #define CFG_GET_OQ_PKTS_PER_INTR(cfg)            ((cfg)->oq.pkts_per_intr)
 127 #define CFG_GET_OQ_REFILL_THRESHOLD(cfg)         ((cfg)->oq.refill_threshold)
 128 #define CFG_GET_OQ_INTR_PKT(cfg)                 ((cfg)->oq.oq_intr_pkt)
 129 #define CFG_GET_OQ_INTR_TIME(cfg)                ((cfg)->oq.oq_intr_time)
 130 #define CFG_SET_OQ_INTR_PKT(cfg, val)            (cfg)->oq.oq_intr_pkt = val
 131 #define CFG_SET_OQ_INTR_TIME(cfg, val)           (cfg)->oq.oq_intr_time = val
 132
 133 #define CFG_GET_DMA_INTR_PKT(cfg)                ((cfg)->dma.dma_intr_pkt)
 134 #define CFG_GET_DMA_INTR_TIME(cfg)               ((cfg)->dma.dma_intr_time)
 135 #define CFG_GET_NUM_NIC_PORTS(cfg)               ((cfg)->num_nic_ports)
 136 #define CFG_GET_NUM_DEF_TX_DESCS(cfg)            ((cfg)->num_def_tx_descs)
 137 #define CFG_GET_NUM_DEF_RX_DESCS(cfg)            ((cfg)->num_def_rx_descs)
 138 #define CFG_GET_DEF_RX_BUF_SIZE(cfg)             ((cfg)->def_rx_buf_size)
 139
 140 #define CFG_GET_MAX_TXQS_NIC_IF(cfg, idx) \
 141                                 ((cfg)->nic_if_cfg[idx].max_txqs)
 142 #define CFG_GET_NUM_TXQS_NIC_IF(cfg, idx) \
 143                                 ((cfg)->nic_if_cfg[idx].num_txqs)
 144 #define CFG_GET_MAX_RXQS_NIC_IF(cfg, idx) \
 145                                 ((cfg)->nic_if_cfg[idx].max_rxqs)
 146 #define CFG_GET_NUM_RXQS_NIC_IF(cfg, idx) \
 147                                 ((cfg)->nic_if_cfg[idx].num_rxqs)
 148 #define CFG_GET_NUM_RX_DESCS_NIC_IF(cfg, idx) \
 149                                 ((cfg)->nic_if_cfg[idx].num_rx_descs)
 150 #define CFG_GET_NUM_TX_DESCS_NIC_IF(cfg, idx) \
 151                                 ((cfg)->nic_if_cfg[idx].num_tx_descs)
 152 #define CFG_GET_NUM_RX_BUF_SIZE_NIC_IF(cfg, idx) \
 153                                 ((cfg)->nic_if_cfg[idx].rx_buf_size)
 154 #define CFG_GET_BASE_QUE_NIC_IF(cfg, idx) \
 155                                 ((cfg)->nic_if_cfg[idx].base_queue)
 156 #define CFG_GET_GMXID_NIC_IF(cfg, idx) \
 157                                 ((cfg)->nic_if_cfg[idx].gmx_port_id)
 158
 159 #define CFG_GET_CTRL_Q_GRP(cfg)                  ((cfg)->misc.ctrlq_grp)
 160 #define CFG_GET_HOST_LINK_QUERY_INTERVAL(cfg) \
 161                                 ((cfg)->misc.host_link_query_interval)
 162 #define CFG_GET_OCT_LINK_QUERY_INTERVAL(cfg) \
 163                                 ((cfg)->misc.oct_link_query_interval)
 164 #define CFG_GET_IS_SLI_BP_ON(cfg)                ((cfg)->misc.enable_sli_oq_bp)
 165
 166 /* Max IOQs per OCTEON Link */
 167 #define MAX_IOQS_PER_NICIF              64
 168
 169 enum lio_card_type {
 170         LIO_210SV = 0, /* Two port, 66xx */
 171         LIO_210NV,     /* Two port, 68xx */
 172         LIO_410NV,     /* Four port, 68xx */
 173         LIO_23XX       /* 23xx */
 174 };
 175
 176 #define LIO_210SV_NAME "210sv"
 177 #define LIO_210NV_NAME "210nv"
 178 #define LIO_410NV_NAME "410nv"
 179 #define LIO_23XX_NAME  "23xx"
 180
 181 /** Structure to define the configuration attributes for each Input queue.
 182  *  Applicable to all Octeon processors
 183  **/
 184 struct octeon_iq_config {
 185 #ifdef __BIG_ENDIAN_BITFIELD
 186         u64 reserved:16;
 187
 188         /** Tx interrupt packets. Applicable to 23xx only */
 189         u64 iq_intr_pkt:16;
 190
 191         /** Minimum ticks to wait before checking for pending instructions. */
 192         u64 db_timeout:16;
 193
 194         /** Minimum number of commands pending to be posted to Octeon
 195          *  before driver hits the Input queue doorbell.
 196          */
 197         u64 db_min:8;
 198
 199         /** Command size - 32 or 64 bytes */
 200         u64 instr_type:32;
 201
 202         /** Pending list size (usually set to the sum of the size of all Input
 203          *  queues)
 204          */
 205         u64 pending_list_size:32;
 206
 207         /* Max number of IQs available */
 208         u64 max_iqs:8;
 209 #else
 210         /* Max number of IQs available */
 211         u64 max_iqs:8;
 212
 213         /** Pending list size (usually set to the sum of the size of all Input
 214          *  queues)
 215          */
 216         u64 pending_list_size:32;
 217
 218         /** Command size - 32 or 64 bytes */
 219         u64 instr_type:32;
 220
 221         /** Minimum number of commands pending to be posted to Octeon
 222          *  before driver hits the Input queue doorbell.
 223          */
 224         u64 db_min:8;
 225
 226         /** Minimum ticks to wait before checking for pending instructions. */
 227         u64 db_timeout:16;
 228
 229         /** Tx interrupt packets. Applicable to 23xx only */
 230         u64 iq_intr_pkt:16;
 231
 232         u64 reserved:16;
 233 #endif
 234 };
 235
 236 /** Structure to define the configuration attributes for each Output queue.
 237  *  Applicable to all Octeon processors
 238  **/
 239 struct octeon_oq_config {
 240 #ifdef __BIG_ENDIAN_BITFIELD
 241         u64 reserved:16;
 242
 243         u64 pkts_per_intr:16;
 244
 245         /** Interrupt Coalescing (Time Interval). Octeon will interrupt the
 246          *  host if atleast one packet was sent in the time interval specified
 247          *  by this field. The driver uses time interval interrupt coalescing
 248          *  by default. The time is specified in microseconds.
 249          */
 250         u64 oq_intr_time:16;
 251
 252         /** Interrupt Coalescing (Packet Count). Octeon will interrupt the host
 253          *  only if it sent as many packets as specified by this field.
 254          *  The driver
 255          *  usually does not use packet count interrupt coalescing.
 256          */
 257         u64 oq_intr_pkt:16;
 258
 259         /** The number of buffers that were consumed during packet processing by
 260          *   the driver on this Output queue before the driver attempts to
 261          *   replenish
 262          *   the descriptor ring with new buffers.
 263          */
 264         u64 refill_threshold:16;
 265
 266         /* Max number of OQs available */
 267         u64 max_oqs:8;
 268
 269 #else
 270         /* Max number of OQs available */
 271         u64 max_oqs:8;
 272
 273         /** The number of buffers that were consumed during packet processing by
 274          *   the driver on this Output queue before the driver attempts to
 275          *   replenish
 276          *   the descriptor ring with new buffers.
 277          */
 278         u64 refill_threshold:16;
 279
 280         /** Interrupt Coalescing (Packet Count). Octeon will interrupt the host
 281          *  only if it sent as many packets as specified by this field.
 282          *  The driver
 283          *  usually does not use packet count interrupt coalescing.
 284          */
 285         u64 oq_intr_pkt:16;
 286
 287         /** Interrupt Coalescing (Time Interval). Octeon will interrupt the
 288          *  host if atleast one packet was sent in the time interval specified
 289          *  by this field. The driver uses time interval interrupt coalescing
 290          *  by default.  The time is specified in microseconds.
 291          */
 292         u64 oq_intr_time:16;
 293
 294         u64 pkts_per_intr:16;
 295
 296         u64 reserved:16;
 297 #endif
 298
 299 };
 300
 301 /** This structure conatins the NIC link configuration attributes,
 302  *  common for all the OCTEON Modles.
 303  */
 304 struct octeon_nic_if_config {
 305 #ifdef __BIG_ENDIAN_BITFIELD
 306         u64 reserved:56;
 307
 308         u64 base_queue:16;
 309
 310         u64 gmx_port_id:8;
 311
 312         /* SKB size, We need not change buf size even for Jumbo frames.
 313          * Octeon can send jumbo frames in 4 consecutive descriptors,
 314          */
 315         u64 rx_buf_size:16;
 316
 317         /* Num of desc for tx rings */
 318         u64 num_tx_descs:16;
 319
 320         /* Num of desc for rx rings */
 321         u64 num_rx_descs:16;
 322
 323         /* Actual configured value. Range could be: 1...max_rxqs */
 324         u64 num_rxqs:16;
 325
 326         /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 327         u64 max_rxqs:16;
 328
 329         /* Actual configured value. Range could be: 1...max_txqs */
 330         u64 num_txqs:16;
 331
 332         /* Max Txqs: Half for each of the two ports :max_iq/2 */
 333         u64 max_txqs:16;
 334 #else
 335         /* Max Txqs: Half for each of the two ports :max_iq/2 */
 336         u64 max_txqs:16;
 337
 338         /* Actual configured value. Range could be: 1...max_txqs */
 339         u64 num_txqs:16;
 340
 341         /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 342         u64 max_rxqs:16;
 343
 344         /* Actual configured value. Range could be: 1...max_rxqs */
 345         u64 num_rxqs:16;
 346
 347         /* Num of desc for rx rings */
 348         u64 num_rx_descs:16;
 349
 350         /* Num of desc for tx rings */
 351         u64 num_tx_descs:16;
 352
 353         /* SKB size, We need not change buf size even for Jumbo frames.
 354          * Octeon can send jumbo frames in 4 consecutive descriptors,
 355          */
 356         u64 rx_buf_size:16;
 357
 358         u64 gmx_port_id:8;
 359
 360         u64 base_queue:16;
 361
 362         u64 reserved:56;
 363 #endif
 364
 365 };
 366
 367 /** Structure to define the configuration attributes for meta data.
 368  *  Applicable to all Octeon processors.
 369  */
 370
 371 struct octeon_misc_config {
 372 #ifdef __BIG_ENDIAN_BITFIELD
 373         /** Host link status polling period */
 374         u64 host_link_query_interval:32;
 375         /** Oct link status polling period */
 376         u64 oct_link_query_interval:32;
 377
 378         u64 enable_sli_oq_bp:1;
 379         /** Control IQ Group */
 380         u64 ctrlq_grp:4;
 381 #else
 382         /** Control IQ Group */
 383         u64 ctrlq_grp:4;
 384         /** BP for SLI OQ */
 385         u64 enable_sli_oq_bp:1;
 386         /** Host link status polling period */
 387         u64 oct_link_query_interval:32;
 388         /** Oct link status polling period */
 389         u64 host_link_query_interval:32;
 390 #endif
 391 };
 392
 393 /** Structure to define the configuration for all OCTEON processors. */
 394 struct octeon_config {
 395         u16 card_type;
 396         char *card_name;
 397
 398         /** Input Queue attributes. */
 399         struct octeon_iq_config iq;
 400
 401         /** Output Queue attributes. */
 402         struct octeon_oq_config oq;
 403
 404         /** NIC Port Configuration */
 405         struct octeon_nic_if_config nic_if_cfg[MAX_OCTEON_NICIF];
 406
 407         /** Miscellaneous attributes */
 408         struct octeon_misc_config misc;
 409
 410         int num_nic_ports;
 411
 412         int num_def_tx_descs;
 413
 414         /* Num of desc for rx rings */
 415         int num_def_rx_descs;
 416
 417         int def_rx_buf_size;
 418
 419 };
 420
 421 /* The following config values are fixed and should not be modified. */
 422
 423 #define  BAR1_INDEX_DYNAMIC_MAP          2
 424 #define  BAR1_INDEX_STATIC_MAP          15
 425 #define  OCTEON_BAR1_ENTRY_SIZE         (4 * 1024 * 1024)
 426
 427 #define  MAX_BAR1_IOREMAP_SIZE  (16 * OCTEON_BAR1_ENTRY_SIZE)
 428
 429 /* Response lists - 1 ordered, 1 unordered-blocking, 1 unordered-nonblocking
 430  * NoResponse Lists are now maintained with each IQ. (Dec' 2007).
 431  */
 432 #define MAX_RESPONSE_LISTS           4
 433
 434 /* Opcode hash bits. The opcode is hashed on the lower 6-bits to lookup the
 435  * dispatch table.
 436  */
 437 #define OPCODE_MASK_BITS             6
 438
 439 /* Mask for the 6-bit lookup hash */
 440 #define OCTEON_OPCODE_MASK           0x3f
 441
 442 /* Size of the dispatch table. The 6-bit hash can index into 2^6 entries */
 443 #define DISPATCH_LIST_SIZE                      BIT(OPCODE_MASK_BITS)
 444
 445 /* Maximum number of Octeon Instruction (command) queues */
 446 #define MAX_OCTEON_INSTR_QUEUES(oct)            \
 447                 (OCTEON_CN23XX_PF(oct) ? CN23XX_MAX_INPUT_QUEUES : \
 448                                         CN6XXX_MAX_INPUT_QUEUES)
 449
 450 /* Maximum number of Octeon Instruction (command) queues */
 451 #define MAX_OCTEON_OUTPUT_QUEUES(oct)           \
 452                 (OCTEON_CN23XX_PF(oct) ? CN23XX_MAX_OUTPUT_QUEUES : \
 453                                         CN6XXX_MAX_OUTPUT_QUEUES)
 454
 455 #define MAX_POSSIBLE_OCTEON_INSTR_QUEUES        CN23XX_MAX_INPUT_QUEUES
 456 #define MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES       CN23XX_MAX_OUTPUT_QUEUES
 457
 458 #define MAX_POSSIBLE_VFS                        64
 459
 460 #endif /* __OCTEON_CONFIG_H__  */