drivers/net/ethernet/cavium/liquidio/octeon_device.h

   1 /**********************************************************************
   2 * Author: Cavium, Inc.
   3 *
   4 * Contact: support@cavium.com
   5 *          Please include "LiquidIO" in the subject.
   6 *
   7 * Copyright (c) 2003-2015 Cavium, Inc.
   8 *
   9 * This file is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License, Version 2, as
  11 * published by the Free Software Foundation.
  12 *
  13 * This file is distributed in the hope that it will be useful, but
  14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16 * NONINFRINGEMENT.  See the GNU General Public License for more
  17 * details.
  18 *
  19 * This file may also be available under a different license from Cavium.
  20 * Contact Cavium, Inc. for more information
  21 **********************************************************************/
  22
  23 /*! \file octeon_device.h
  24  *  \brief Host Driver: This file defines the octeon device structure.
  25  */
  26
  27 #ifndef _OCTEON_DEVICE_H_
  28 #define  _OCTEON_DEVICE_H_
  29
  30 /** PCI VendorId Device Id */
  31 #define  OCTEON_CN68XX_PCIID          0x91177d
  32 #define  OCTEON_CN66XX_PCIID          0x92177d
  33
  34 /** Driver identifies chips by these Ids, created by clubbing together
  35  *  DeviceId+RevisionId; Where Revision Id is not used to distinguish
  36  *  between chips, a value of 0 is used for revision id.
  37  */
  38 #define  OCTEON_CN68XX                0x0091
  39 #define  OCTEON_CN66XX                0x0092
  40
  41 /** Endian-swap modes supported by Octeon. */
  42 enum octeon_pci_swap_mode {
  43         OCTEON_PCI_PASSTHROUGH = 0,
  44         OCTEON_PCI_64BIT_SWAP = 1,
  45         OCTEON_PCI_32BIT_BYTE_SWAP = 2,
  46         OCTEON_PCI_32BIT_LW_SWAP = 3
  47 };
  48
  49 /*---------------   PCI BAR1 index registers -------------*/
  50
  51 /* BAR1 Mask */
  52 #define    PCI_BAR1_ENABLE_CA            1
  53 #define    PCI_BAR1_ENDIAN_MODE          OCTEON_PCI_64BIT_SWAP
  54 #define    PCI_BAR1_ENTRY_VALID          1
  55 #define    PCI_BAR1_MASK                 ((PCI_BAR1_ENABLE_CA << 3)   \
  56                                             | (PCI_BAR1_ENDIAN_MODE << 1) \
  57                                             | PCI_BAR1_ENTRY_VALID)
  58
  59 /** Octeon Device state.
  60  *  Each octeon device goes through each of these states
  61  *  as it is initialized.
  62  */
  63 #define    OCT_DEV_BEGIN_STATE            0x0
  64 #define    OCT_DEV_PCI_MAP_DONE           0x1
  65 #define    OCT_DEV_DISPATCH_INIT_DONE     0x2
  66 #define    OCT_DEV_INSTR_QUEUE_INIT_DONE  0x3
  67 #define    OCT_DEV_SC_BUFF_POOL_INIT_DONE 0x4
  68 #define    OCT_DEV_RESP_LIST_INIT_DONE    0x5
  69 #define    OCT_DEV_DROQ_INIT_DONE         0x6
  70 #define    OCT_DEV_IO_QUEUES_DONE         0x7
  71 #define    OCT_DEV_CONSOLE_INIT_DONE      0x8
  72 #define    OCT_DEV_HOST_OK                0x9
  73 #define    OCT_DEV_CORE_OK                0xa
  74 #define    OCT_DEV_RUNNING                0xb
  75 #define    OCT_DEV_IN_RESET               0xc
  76 #define    OCT_DEV_STATE_INVALID          0xd
  77
  78 #define    OCT_DEV_STATES                 OCT_DEV_STATE_INVALID
  79
  80 /** Octeon Device interrupts
  81   *  These interrupt bits are set in int_status filed of
  82   *  octeon_device structure
  83   */
  84 #define    OCT_DEV_INTR_DMA0_FORCE        0x01
  85 #define    OCT_DEV_INTR_DMA1_FORCE        0x02
  86 #define    OCT_DEV_INTR_PKT_DATA          0x04
  87
  88 #define LIO_RESET_SECS (3)
  89
  90 /*---------------------------DISPATCH LIST-------------------------------*/
  91
  92 /** The dispatch list entry.
  93  *  The driver keeps a record of functions registered for each
  94  *  response header opcode in this structure. Since the opcode is
  95  *  hashed to index into the driver's list, more than one opcode
  96  *  can hash to the same entry, in which case the list field points
  97  *  to a linked list with the other entries.
  98  */
  99 struct octeon_dispatch {
 100         /** List head for this entry */
 101         struct list_head list;
 102
 103         /** The opcode for which the dispatch function & arg should be used */
 104         u16 opcode;
 105
 106         /** The function to be called for a packet received by the driver */
 107         octeon_dispatch_fn_t dispatch_fn;
 108
 109         /* The application specified argument to be passed to the above
 110          * function along with the received packet
 111          */
 112         void *arg;
 113 };
 114
 115 /** The dispatch list structure. */
 116 struct octeon_dispatch_list {
 117         /** access to dispatch list must be atomic */
 118         spinlock_t lock;
 119
 120         /** Count of dispatch functions currently registered */
 121         u32 count;
 122
 123         /** The list of dispatch functions */
 124         struct octeon_dispatch *dlist;
 125 };
 126
 127 /*-----------------------  THE OCTEON DEVICE  ---------------------------*/
 128
 129 #define OCT_MEM_REGIONS     3
 130 /** PCI address space mapping information.
 131  *  Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of
 132  *  Octeon gets mapped to different physical address spaces in
 133  *  the kernel.
 134  */
 135 struct octeon_mmio {
 136         /** PCI address to which the BAR is mapped. */
 137         u64 start;
 138
 139         /** Length of this PCI address space. */
 140         u32 len;
 141
 142         /** Length that has been mapped to phys. address space. */
 143         u32 mapped_len;
 144
 145         /** The physical address to which the PCI address space is mapped. */
 146         u8 __iomem *hw_addr;
 147
 148         /** Flag indicating the mapping was successful. */
 149         u32 done;
 150 };
 151
 152 #define   MAX_OCTEON_MAPS    32
 153
 154 struct octeon_io_enable {
 155         u32 iq;
 156         u32 oq;
 157         u32 iq64B;
 158 };
 159
 160 struct octeon_reg_list {
 161         u32 __iomem *pci_win_wr_addr_hi;
 162         u32 __iomem *pci_win_wr_addr_lo;
 163         u64 __iomem *pci_win_wr_addr;
 164
 165         u32 __iomem *pci_win_rd_addr_hi;
 166         u32 __iomem *pci_win_rd_addr_lo;
 167         u64 __iomem *pci_win_rd_addr;
 168
 169         u32 __iomem *pci_win_wr_data_hi;
 170         u32 __iomem *pci_win_wr_data_lo;
 171         u64 __iomem *pci_win_wr_data;
 172
 173         u32 __iomem *pci_win_rd_data_hi;
 174         u32 __iomem *pci_win_rd_data_lo;
 175         u64 __iomem *pci_win_rd_data;
 176 };
 177
 178 #define OCTEON_CONSOLE_MAX_READ_BYTES 512
 179 struct octeon_console {
 180         u32 active;
 181         u32 waiting;
 182         u64 addr;
 183         u32 buffer_size;
 184         u64 input_base_addr;
 185         u64 output_base_addr;
 186         char leftover[OCTEON_CONSOLE_MAX_READ_BYTES];
 187 };
 188
 189 struct octeon_board_info {
 190         char name[OCT_BOARD_NAME];
 191         char serial_number[OCT_SERIAL_LEN];
 192         u64 major;
 193         u64 minor;
 194 };
 195
 196 struct octeon_fn_list {
 197         void (*setup_iq_regs)(struct octeon_device *, u32);
 198         void (*setup_oq_regs)(struct octeon_device *, u32);
 199
 200         irqreturn_t (*process_interrupt_regs)(void *);
 201         int (*soft_reset)(struct octeon_device *);
 202         int (*setup_device_regs)(struct octeon_device *);
 203         void (*reinit_regs)(struct octeon_device *);
 204         void (*bar1_idx_setup)(struct octeon_device *, u64, u32, int);
 205         void (*bar1_idx_write)(struct octeon_device *, u32, u32);
 206         u32 (*bar1_idx_read)(struct octeon_device *, u32);
 207         u32 (*update_iq_read_idx)(struct octeon_device *,
 208                                   struct octeon_instr_queue *);
 209
 210         void (*enable_oq_pkt_time_intr)(struct octeon_device *, u32);
 211         void (*disable_oq_pkt_time_intr)(struct octeon_device *, u32);
 212
 213         void (*enable_interrupt)(void *);
 214         void (*disable_interrupt)(void *);
 215
 216         void (*enable_io_queues)(struct octeon_device *);
 217         void (*disable_io_queues)(struct octeon_device *);
 218 };
 219
 220 /* Must be multiple of 8, changing breaks ABI */
 221 #define CVMX_BOOTMEM_NAME_LEN 128
 222
 223 /* Structure for named memory blocks
 224  * Number of descriptors
 225  * available can be changed without affecting compatiblity,
 226  * but name length changes require a bump in the bootmem
 227  * descriptor version
 228  * Note: This structure must be naturally 64 bit aligned, as a single
 229  * memory image will be used by both 32 and 64 bit programs.
 230  */
 231 struct cvmx_bootmem_named_block_desc {
 232         /** Base address of named block */
 233         u64 base_addr;
 234
 235         /** Size actually allocated for named block */
 236         u64 size;
 237
 238         /** name of named block */
 239         char name[CVMX_BOOTMEM_NAME_LEN];
 240 };
 241
 242 struct oct_fw_info {
 243         u32 max_nic_ports;      /** max nic ports for the device */
 244         u32 num_gmx_ports;      /** num gmx ports */
 245         u64 app_cap_flags;      /** firmware cap flags */
 246
 247         /** The core application is running in this mode.
 248          * See octeon-drv-opcodes.h for values.
 249          */
 250         u32 app_mode;
 251         char   liquidio_firmware_version[32];
 252 };
 253
 254 /* wrappers around work structs */
 255 struct cavium_wk {
 256         struct delayed_work work;
 257         void *ctxptr;
 258         size_t ctxul;
 259 };
 260
 261 struct cavium_wq {
 262         struct workqueue_struct *wq;
 263         struct cavium_wk wk;
 264 };
 265
 266 struct octdev_props {
 267         /* Each interface in the Octeon device has a network
 268          * device pointer (used for OS specific calls).
 269          */
 270         int    gmxport;
 271         struct net_device *netdev;
 272 };
 273
 274 /** The Octeon device.
 275  *  Each Octeon device has this structure to represent all its
 276  *  components.
 277  */
 278 struct octeon_device {
 279         /** Lock for PCI window configuration accesses */
 280         spinlock_t pci_win_lock;
 281
 282         /** Lock for memory accesses */
 283         spinlock_t mem_access_lock;
 284
 285         /** PCI device pointer */
 286         struct pci_dev *pci_dev;
 287
 288         /** Chip specific information. */
 289         void *chip;
 290
 291         /** Number of interfaces detected in this octeon device. */
 292         u32 ifcount;
 293
 294         struct octdev_props props[MAX_OCTEON_LINKS];
 295
 296         /** Octeon Chip type. */
 297         u16 chip_id;
 298         u16 rev_id;
 299
 300         /** This device's id - set by the driver. */
 301         u32 octeon_id;
 302
 303         /** This device's PCIe port used for traffic. */
 304         u16 pcie_port;
 305
 306         u16 flags;
 307 #define LIO_FLAG_MSI_ENABLED                  (u32)(1 << 1)
 308 #define LIO_FLAG_MSIX_ENABLED                 (u32)(1 << 2)
 309
 310         /** The state of this device */
 311         atomic_t status;
 312
 313         /** memory mapped io range */
 314         struct octeon_mmio mmio[OCT_MEM_REGIONS];
 315
 316         struct octeon_reg_list reg_list;
 317
 318         struct octeon_fn_list fn_list;
 319
 320         struct octeon_board_info boardinfo;
 321
 322         u32 num_iqs;
 323
 324         /* The pool containing pre allocated buffers used for soft commands */
 325         struct octeon_sc_buffer_pool    sc_buf_pool;
 326
 327         /** The input instruction queues */
 328         struct octeon_instr_queue *instr_queue[MAX_OCTEON_INSTR_QUEUES];
 329
 330         /** The doubly-linked list of instruction response */
 331         struct octeon_response_list response_list[MAX_RESPONSE_LISTS];
 332
 333         u32 num_oqs;
 334
 335         /** The DROQ output queues  */
 336         struct octeon_droq *droq[MAX_OCTEON_OUTPUT_QUEUES];
 337
 338         struct octeon_io_enable io_qmask;
 339
 340         /** List of dispatch functions */
 341         struct octeon_dispatch_list dispatch;
 342
 343         /* Interrupt Moderation */
 344         struct oct_intrmod_cfg intrmod;
 345
 346         u32 int_status;
 347
 348         u64 droq_intr;
 349
 350         /** Physical location of the cvmx_bootmem_desc_t in octeon memory */
 351         u64 bootmem_desc_addr;
 352
 353         /** Placeholder memory for named blocks.
 354          * Assumes single-threaded access
 355          */
 356         struct cvmx_bootmem_named_block_desc bootmem_named_block_desc;
 357
 358         /** Address of consoles descriptor */
 359         u64 console_desc_addr;
 360
 361         /** Number of consoles available. 0 means they are inaccessible */
 362         u32 num_consoles;
 363
 364         /* Console caches */
 365         struct octeon_console console[MAX_OCTEON_MAPS];
 366
 367         /* Coprocessor clock rate. */
 368         u64 coproc_clock_rate;
 369
 370         /** The core application is running in this mode. See liquidio_common.h
 371          * for values.
 372          */
 373         u32 app_mode;
 374
 375         struct oct_fw_info fw_info;
 376
 377         /** The name given to this device. */
 378         char device_name[32];
 379
 380         /** Application Context */
 381         void *app_ctx;
 382
 383         struct cavium_wq dma_comp_wq;
 384
 385         struct cavium_wq check_db_wq[MAX_OCTEON_INSTR_QUEUES];
 386
 387         struct cavium_wk nic_poll_work;
 388
 389         struct cavium_wk console_poll_work[MAX_OCTEON_MAPS];
 390
 391         void *priv;
 392 };
 393
 394 #define  OCTEON_CN6XXX(oct)           ((oct->chip_id == OCTEON_CN66XX) || \
 395                                        (oct->chip_id == OCTEON_CN68XX))
 396 #define CHIP_FIELD(oct, TYPE, field)             \
 397         (((struct octeon_ ## TYPE  *)(oct->chip))->field)
 398
 399 struct oct_intrmod_cmd {
 400         struct octeon_device *oct_dev;
 401         struct octeon_soft_command *sc;
 402         struct oct_intrmod_cfg *cfg;
 403 };
 404
 405 /*------------------ Function Prototypes ----------------------*/
 406
 407 /** Initialize device list memory */
 408 void octeon_init_device_list(int conf_type);
 409
 410 /** Free memory for Input and Output queue structures for a octeon device */
 411 void octeon_free_device_mem(struct octeon_device *);
 412
 413 /* Look up a free entry in the octeon_device table and allocate resources
 414  * for the octeon_device structure for an octeon device. Called at init
 415  * time.
 416  */
 417 struct octeon_device *octeon_allocate_device(u32 pci_id,
 418                                              u32 priv_size);
 419
 420 /**  Initialize the driver's dispatch list which is a mix of a hash table
 421  *  and a linked list. This is done at driver load time.
 422  *  @param octeon_dev - pointer to the octeon device structure.
 423  *  @return 0 on success, else -ve error value
 424  */
 425 int octeon_init_dispatch_list(struct octeon_device *octeon_dev);
 426
 427 /**  Delete the driver's dispatch list and all registered entries.
 428  * This is done at driver unload time.
 429  *  @param octeon_dev - pointer to the octeon device structure.
 430  */
 431 void octeon_delete_dispatch_list(struct octeon_device *octeon_dev);
 432
 433 /** Initialize the core device fields with the info returned by the FW.
 434  * @param recv_info - Receive info structure
 435  * @param buf       - Receive buffer
 436  */
 437 int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf);
 438
 439 /** Gets the dispatch function registered to receive packets with a
 440  *  given opcode/subcode.
 441  *  @param  octeon_dev  - the octeon device pointer.
 442  *  @param  opcode      - the opcode for which the dispatch function
 443  *                        is to checked.
 444  *  @param  subcode     - the subcode for which the dispatch function
 445  *                        is to checked.
 446  *
 447  *  @return Success: octeon_dispatch_fn_t (dispatch function pointer)
 448  *  @return Failure: NULL
 449  *
 450  *  Looks up the dispatch list to get the dispatch function for a
 451  *  given opcode.
 452  */
 453 octeon_dispatch_fn_t
 454 octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode,
 455                     u16 subcode);
 456
 457 /** Get the octeon device pointer.
 458  *  @param octeon_id  - The id for which the octeon device pointer is required.
 459  *  @return Success: Octeon device pointer.
 460  *  @return Failure: NULL.
 461  */
 462 struct octeon_device *lio_get_device(u32 octeon_id);
 463
 464 /** Get the octeon id assigned to the octeon device passed as argument.
 465  *  This function is exported to other modules.
 466  *  @param dev - octeon device pointer passed as a void *.
 467  *  @return octeon device id
 468  */
 469 int lio_get_device_id(void *dev);
 470
 471 static inline u16 OCTEON_MAJOR_REV(struct octeon_device *oct)
 472 {
 473         u16 rev = (oct->rev_id & 0xC) >> 2;
 474
 475         return (rev == 0) ? 1 : rev;
 476 }
 477
 478 static inline u16 OCTEON_MINOR_REV(struct octeon_device *oct)
 479 {
 480         return oct->rev_id & 0x3;
 481 }
 482
 483 /** Read windowed register.
 484  *  @param  oct   -  pointer to the Octeon device.
 485  *  @param  addr  -  Address of the register to read.
 486  *
 487  *  This routine is called to read from the indirectly accessed
 488  *  Octeon registers that are visible through a PCI BAR0 mapped window
 489  *  register.
 490  *  @return  - 64 bit value read from the register.
 491  */
 492
 493 u64 lio_pci_readq(struct octeon_device *oct, u64 addr);
 494
 495 /** Write windowed register.
 496  *  @param  oct  -  pointer to the Octeon device.
 497  *  @param  val  -  Value to write
 498  *  @param  addr -  Address of the register to write
 499  *
 500  *  This routine is called to write to the indirectly accessed
 501  *  Octeon registers that are visible through a PCI BAR0 mapped window
 502  *  register.
 503  *  @return   Nothing.
 504  */
 505 void lio_pci_writeq(struct octeon_device *oct, u64 val, u64 addr);
 506
 507 /* Routines for reading and writing CSRs */
 508 #define   octeon_write_csr(oct_dev, reg_off, value) \
 509                 writel(value, oct_dev->mmio[0].hw_addr + reg_off)
 510
 511 #define   octeon_write_csr64(oct_dev, reg_off, val64) \
 512                 writeq(val64, oct_dev->mmio[0].hw_addr + reg_off)
 513
 514 #define   octeon_read_csr(oct_dev, reg_off)         \
 515                 readl(oct_dev->mmio[0].hw_addr + reg_off)
 516
 517 #define   octeon_read_csr64(oct_dev, reg_off)         \
 518                 readq(oct_dev->mmio[0].hw_addr + reg_off)
 519
 520 /**
 521  * Checks if memory access is okay
 522  *
 523  * @param oct which octeon to send to
 524  * @return Zero on success, negative on failure.
 525  */
 526 int octeon_mem_access_ok(struct octeon_device *oct);
 527
 528 /**
 529  * Waits for DDR initialization.
 530  *
 531  * @param oct which octeon to send to
 532  * @param timeout_in_ms pointer to how long to wait until DDR is initialized
 533  * in ms.
 534  *                      If contents are 0, it waits until contents are non-zero
 535  *                      before starting to check.
 536  * @return Zero on success, negative on failure.
 537  */
 538 int octeon_wait_for_ddr_init(struct octeon_device *oct,
 539                              u32 *timeout_in_ms);
 540
 541 /**
 542  * Wait for u-boot to boot and be waiting for a command.
 543  *
 544  * @param wait_time_hundredths
 545  *               Maximum time to wait
 546  *
 547  * @return Zero on success, negative on failure.
 548  */
 549 int octeon_wait_for_bootloader(struct octeon_device *oct,
 550                                u32 wait_time_hundredths);
 551
 552 /**
 553  * Initialize console access
 554  *
 555  * @param oct which octeon initialize
 556  * @return Zero on success, negative on failure.
 557  */
 558 int octeon_init_consoles(struct octeon_device *oct);
 559
 560 /**
 561  * Adds access to a console to the device.
 562  *
 563  * @param oct which octeon to add to
 564  * @param console_num which console
 565  * @return Zero on success, negative on failure.
 566  */
 567 int octeon_add_console(struct octeon_device *oct, u32 console_num);
 568
 569 /** write or read from a console */
 570 int octeon_console_write(struct octeon_device *oct, u32 console_num,
 571                          char *buffer, u32 write_request_size, u32 flags);
 572 int octeon_console_write_avail(struct octeon_device *oct, u32 console_num);
 573 int octeon_console_read(struct octeon_device *oct, u32 console_num,
 574                         char *buffer, u32 buf_size, u32 flags);
 575 int octeon_console_read_avail(struct octeon_device *oct, u32 console_num);
 576
 577 /** Removes all attached consoles. */
 578 void octeon_remove_consoles(struct octeon_device *oct);
 579
 580 /**
 581  * Send a string to u-boot on console 0 as a command.
 582  *
 583  * @param oct which octeon to send to
 584  * @param cmd_str String to send
 585  * @param wait_hundredths Time to wait for u-boot to accept the command.
 586  *
 587  * @return Zero on success, negative on failure.
 588  */
 589 int octeon_console_send_cmd(struct octeon_device *oct, char *cmd_str,
 590                             u32 wait_hundredths);
 591
 592 /** Parses, validates, and downloads firmware, then boots associated cores.
 593  *  @param oct which octeon to download firmware to
 594  *  @param data  - The complete firmware file image
 595  *  @param size  - The size of the data
 596  *
 597  *  @return 0 if success.
 598  *         -EINVAL if file is incompatible or badly formatted.
 599  *         -ENODEV if no handler was found for the application type or an
 600  *         invalid octeon id was passed.
 601  */
 602 int octeon_download_firmware(struct octeon_device *oct, const u8 *data,
 603                              size_t size);
 604
 605 char *lio_get_state_string(atomic_t *state_ptr);
 606
 607 /** Sets up instruction queues for the device
 608  *  @param oct which octeon to setup
 609  *
 610  *  @return 0 if success. 1 if fails
 611  */
 612 int octeon_setup_instr_queues(struct octeon_device *oct);
 613
 614 /** Sets up output queues for the device
 615  *  @param oct which octeon to setup
 616  *
 617  *  @return 0 if success. 1 if fails
 618  */
 619 int octeon_setup_output_queues(struct octeon_device *oct);
 620
 621 int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no);
 622
 623 int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no);
 624
 625 /** Turns off the input and output queues for the device
 626  *  @param oct which octeon to disable
 627  */
 628 void octeon_set_io_queues_off(struct octeon_device *oct);
 629
 630 /** Turns on or off the given output queue for the device
 631  *  @param oct which octeon to change
 632  *  @param q_no which queue
 633  *  @param enable 1 to enable, 0 to disable
 634  */
 635 void octeon_set_droq_pkt_op(struct octeon_device *oct, u32 q_no, u32 enable);
 636
 637 /** Retrieve the config for the device
 638  *  @param oct which octeon
 639  *  @param card_type type of card
 640  *
 641  *  @returns pointer to configuration
 642  */
 643 void *oct_get_config_info(struct octeon_device *oct, u16 card_type);
 644
 645 /** Gets the octeon device configuration
 646  *  @return - pointer to the octeon configuration struture
 647  */
 648 struct octeon_config *octeon_get_conf(struct octeon_device *oct);
 649
 650 #endif