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liquidio: add cleanup in octeon_setup_iq()
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / cavium / liquidio / request_manager.c
1 /**********************************************************************
2 * Author: Cavium, Inc.
3 *
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
6 *
7 * Copyright (c) 2003-2016 Cavium, Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 **********************************************************************/
19 #include <linux/pci.h>
20 #include <linux/netdevice.h>
21 #include <linux/vmalloc.h>
22 #include "liquidio_common.h"
23 #include "octeon_droq.h"
24 #include "octeon_iq.h"
25 #include "response_manager.h"
26 #include "octeon_device.h"
27 #include "octeon_main.h"
28 #include "octeon_network.h"
29 #include "cn66xx_device.h"
30 #include "cn23xx_pf_device.h"
31 #include "cn23xx_vf_device.h"
32
33 struct iq_post_status {
34 int status;
35 int index;
36 };
37
38 static void check_db_timeout(struct work_struct *work);
39 static void __check_db_timeout(struct octeon_device *oct, u64 iq_no);
40
41 static void (*reqtype_free_fn[MAX_OCTEON_DEVICES][REQTYPE_LAST + 1]) (void *);
42
43 static inline int IQ_INSTR_MODE_64B(struct octeon_device *oct, int iq_no)
44 {
45 struct octeon_instr_queue *iq =
46 (struct octeon_instr_queue *)oct->instr_queue[iq_no];
47 return iq->iqcmd_64B;
48 }
49
50 #define IQ_INSTR_MODE_32B(oct, iq_no) (!IQ_INSTR_MODE_64B(oct, iq_no))
51
52 /* Define this to return the request status comaptible to old code */
53 /*#define OCTEON_USE_OLD_REQ_STATUS*/
54
55 /* Return 0 on success, 1 on failure */
56 int octeon_init_instr_queue(struct octeon_device *oct,
57 union oct_txpciq txpciq,
58 u32 num_descs)
59 {
60 struct octeon_instr_queue *iq;
61 struct octeon_iq_config *conf = NULL;
62 u32 iq_no = (u32)txpciq.s.q_no;
63 u32 q_size;
64 struct cavium_wq *db_wq;
65 int numa_node = dev_to_node(&oct->pci_dev->dev);
66
67 if (OCTEON_CN6XXX(oct))
68 conf = &(CFG_GET_IQ_CFG(CHIP_CONF(oct, cn6xxx)));
69 else if (OCTEON_CN23XX_PF(oct))
70 conf = &(CFG_GET_IQ_CFG(CHIP_CONF(oct, cn23xx_pf)));
71 else if (OCTEON_CN23XX_VF(oct))
72 conf = &(CFG_GET_IQ_CFG(CHIP_CONF(oct, cn23xx_vf)));
73
74 if (!conf) {
75 dev_err(&oct->pci_dev->dev, "Unsupported Chip %x\n",
76 oct->chip_id);
77 return 1;
78 }
79
80 q_size = (u32)conf->instr_type * num_descs;
81
82 iq = oct->instr_queue[iq_no];
83
84 iq->oct_dev = oct;
85
86 iq->base_addr = lio_dma_alloc(oct, q_size, &iq->base_addr_dma);
87 if (!iq->base_addr) {
88 dev_err(&oct->pci_dev->dev, "Cannot allocate memory for instr queue %d\n",
89 iq_no);
90 return 1;
91 }
92
93 iq->max_count = num_descs;
94
95 /* Initialize a list to holds requests that have been posted to Octeon
96 * but has yet to be fetched by octeon
97 */
98 iq->request_list = vmalloc_node((sizeof(*iq->request_list) * num_descs),
99 numa_node);
100 if (!iq->request_list)
101 iq->request_list = vmalloc(sizeof(*iq->request_list) *
102 num_descs);
103 if (!iq->request_list) {
104 lio_dma_free(oct, q_size, iq->base_addr, iq->base_addr_dma);
105 dev_err(&oct->pci_dev->dev, "Alloc failed for IQ[%d] nr free list\n",
106 iq_no);
107 return 1;
108 }
109
110 memset(iq->request_list, 0, sizeof(*iq->request_list) * num_descs);
111
112 dev_dbg(&oct->pci_dev->dev, "IQ[%d]: base: %p basedma: %llx count: %d\n",
113 iq_no, iq->base_addr, iq->base_addr_dma, iq->max_count);
114
115 iq->txpciq.u64 = txpciq.u64;
116 iq->fill_threshold = (u32)conf->db_min;
117 iq->fill_cnt = 0;
118 iq->host_write_index = 0;
119 iq->octeon_read_index = 0;
120 iq->flush_index = 0;
121 iq->last_db_time = 0;
122 iq->do_auto_flush = 1;
123 iq->db_timeout = (u32)conf->db_timeout;
124 atomic_set(&iq->instr_pending, 0);
125
126 /* Initialize the spinlock for this instruction queue */
127 spin_lock_init(&iq->lock);
128 spin_lock_init(&iq->post_lock);
129
130 spin_lock_init(&iq->iq_flush_running_lock);
131
132 oct->io_qmask.iq |= BIT_ULL(iq_no);
133
134 /* Set the 32B/64B mode for each input queue */
135 oct->io_qmask.iq64B |= ((conf->instr_type == 64) << iq_no);
136 iq->iqcmd_64B = (conf->instr_type == 64);
137
138 oct->fn_list.setup_iq_regs(oct, iq_no);
139
140 oct->check_db_wq[iq_no].wq = alloc_workqueue("check_iq_db",
141 WQ_MEM_RECLAIM,
142 0);
143 if (!oct->check_db_wq[iq_no].wq) {
144 vfree(iq->request_list);
145 iq->request_list = NULL;
146 lio_dma_free(oct, q_size, iq->base_addr, iq->base_addr_dma);
147 dev_err(&oct->pci_dev->dev, "check db wq create failed for iq %d\n",
148 iq_no);
149 return 1;
150 }
151
152 db_wq = &oct->check_db_wq[iq_no];
153
154 INIT_DELAYED_WORK(&db_wq->wk.work, check_db_timeout);
155 db_wq->wk.ctxptr = oct;
156 db_wq->wk.ctxul = iq_no;
157 queue_delayed_work(db_wq->wq, &db_wq->wk.work, msecs_to_jiffies(1));
158
159 return 0;
160 }
161
162 int octeon_delete_instr_queue(struct octeon_device *oct, u32 iq_no)
163 {
164 u64 desc_size = 0, q_size;
165 struct octeon_instr_queue *iq = oct->instr_queue[iq_no];
166
167 cancel_delayed_work_sync(&oct->check_db_wq[iq_no].wk.work);
168 destroy_workqueue(oct->check_db_wq[iq_no].wq);
169
170 if (OCTEON_CN6XXX(oct))
171 desc_size =
172 CFG_GET_IQ_INSTR_TYPE(CHIP_CONF(oct, cn6xxx));
173 else if (OCTEON_CN23XX_PF(oct))
174 desc_size =
175 CFG_GET_IQ_INSTR_TYPE(CHIP_CONF(oct, cn23xx_pf));
176 else if (OCTEON_CN23XX_VF(oct))
177 desc_size =
178 CFG_GET_IQ_INSTR_TYPE(CHIP_CONF(oct, cn23xx_vf));
179
180 vfree(iq->request_list);
181
182 if (iq->base_addr) {
183 q_size = iq->max_count * desc_size;
184 lio_dma_free(oct, (u32)q_size, iq->base_addr,
185 iq->base_addr_dma);
186 oct->io_qmask.iq &= ~(1ULL << iq_no);
187 vfree(oct->instr_queue[iq_no]);
188 oct->instr_queue[iq_no] = NULL;
189 oct->num_iqs--;
190 return 0;
191 }
192 return 1;
193 }
194
195 /* Return 0 on success, 1 on failure */
196 int octeon_setup_iq(struct octeon_device *oct,
197 int ifidx,
198 int q_index,
199 union oct_txpciq txpciq,
200 u32 num_descs,
201 void *app_ctx)
202 {
203 u32 iq_no = (u32)txpciq.s.q_no;
204 int numa_node = dev_to_node(&oct->pci_dev->dev);
205
206 if (oct->instr_queue[iq_no]) {
207 dev_dbg(&oct->pci_dev->dev, "IQ is in use. Cannot create the IQ: %d again\n",
208 iq_no);
209 oct->instr_queue[iq_no]->txpciq.u64 = txpciq.u64;
210 oct->instr_queue[iq_no]->app_ctx = app_ctx;
211 return 0;
212 }
213 oct->instr_queue[iq_no] =
214 vmalloc_node(sizeof(struct octeon_instr_queue), numa_node);
215 if (!oct->instr_queue[iq_no])
216 oct->instr_queue[iq_no] =
217 vmalloc(sizeof(struct octeon_instr_queue));
218 if (!oct->instr_queue[iq_no])
219 return 1;
220
221 memset(oct->instr_queue[iq_no], 0,
222 sizeof(struct octeon_instr_queue));
223
224 oct->instr_queue[iq_no]->q_index = q_index;
225 oct->instr_queue[iq_no]->app_ctx = app_ctx;
226 oct->instr_queue[iq_no]->ifidx = ifidx;
227
228 if (octeon_init_instr_queue(oct, txpciq, num_descs)) {
229 vfree(oct->instr_queue[iq_no]);
230 oct->instr_queue[iq_no] = NULL;
231 return 1;
232 }
233
234 oct->num_iqs++;
235 if (oct->fn_list.enable_io_queues(oct)) {
236 octeon_delete_instr_queue(oct, iq_no);
237 return 1;
238 }
239
240 return 0;
241 }
242
243 int lio_wait_for_instr_fetch(struct octeon_device *oct)
244 {
245 int i, retry = 1000, pending, instr_cnt = 0;
246
247 do {
248 instr_cnt = 0;
249
250 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
251 if (!(oct->io_qmask.iq & BIT_ULL(i)))
252 continue;
253 pending =
254 atomic_read(&oct->instr_queue[i]->instr_pending);
255 if (pending)
256 __check_db_timeout(oct, i);
257 instr_cnt += pending;
258 }
259
260 if (instr_cnt == 0)
261 break;
262
263 schedule_timeout_uninterruptible(1);
264
265 } while (retry-- && instr_cnt);
266
267 return instr_cnt;
268 }
269
270 static inline void
271 ring_doorbell(struct octeon_device *oct, struct octeon_instr_queue *iq)
272 {
273 if (atomic_read(&oct->status) == OCT_DEV_RUNNING) {
274 writel(iq->fill_cnt, iq->doorbell_reg);
275 /* make sure doorbell write goes through */
276 mmiowb();
277 iq->fill_cnt = 0;
278 iq->last_db_time = jiffies;
279 return;
280 }
281 }
282
283 void
284 octeon_ring_doorbell_locked(struct octeon_device *oct, u32 iq_no)
285 {
286 struct octeon_instr_queue *iq;
287
288 iq = oct->instr_queue[iq_no];
289 spin_lock(&iq->post_lock);
290 if (iq->fill_cnt)
291 ring_doorbell(oct, iq);
292 spin_unlock(&iq->post_lock);
293 }
294
295 static inline void __copy_cmd_into_iq(struct octeon_instr_queue *iq,
296 u8 *cmd)
297 {
298 u8 *iqptr, cmdsize;
299
300 cmdsize = ((iq->iqcmd_64B) ? 64 : 32);
301 iqptr = iq->base_addr + (cmdsize * iq->host_write_index);
302
303 memcpy(iqptr, cmd, cmdsize);
304 }
305
306 static inline struct iq_post_status
307 __post_command2(struct octeon_instr_queue *iq, u8 *cmd)
308 {
309 struct iq_post_status st;
310
311 st.status = IQ_SEND_OK;
312
313 /* This ensures that the read index does not wrap around to the same
314 * position if queue gets full before Octeon could fetch any instr.
315 */
316 if (atomic_read(&iq->instr_pending) >= (s32)(iq->max_count - 1)) {
317 st.status = IQ_SEND_FAILED;
318 st.index = -1;
319 return st;
320 }
321
322 if (atomic_read(&iq->instr_pending) >= (s32)(iq->max_count - 2))
323 st.status = IQ_SEND_STOP;
324
325 __copy_cmd_into_iq(iq, cmd);
326
327 /* "index" is returned, host_write_index is modified. */
328 st.index = iq->host_write_index;
329 iq->host_write_index = incr_index(iq->host_write_index, 1,
330 iq->max_count);
331 iq->fill_cnt++;
332
333 /* Flush the command into memory. We need to be sure the data is in
334 * memory before indicating that the instruction is pending.
335 */
336 wmb();
337
338 atomic_inc(&iq->instr_pending);
339
340 return st;
341 }
342
343 int
344 octeon_register_reqtype_free_fn(struct octeon_device *oct, int reqtype,
345 void (*fn)(void *))
346 {
347 if (reqtype > REQTYPE_LAST) {
348 dev_err(&oct->pci_dev->dev, "%s: Invalid reqtype: %d\n",
349 __func__, reqtype);
350 return -EINVAL;
351 }
352
353 reqtype_free_fn[oct->octeon_id][reqtype] = fn;
354
355 return 0;
356 }
357
358 static inline void
359 __add_to_request_list(struct octeon_instr_queue *iq,
360 int idx, void *buf, int reqtype)
361 {
362 iq->request_list[idx].buf = buf;
363 iq->request_list[idx].reqtype = reqtype;
364 }
365
366 /* Can only run in process context */
367 int
368 lio_process_iq_request_list(struct octeon_device *oct,
369 struct octeon_instr_queue *iq, u32 napi_budget)
370 {
371 int reqtype;
372 void *buf;
373 u32 old = iq->flush_index;
374 u32 inst_count = 0;
375 unsigned int pkts_compl = 0, bytes_compl = 0;
376 struct octeon_soft_command *sc;
377 struct octeon_instr_irh *irh;
378 unsigned long flags;
379
380 while (old != iq->octeon_read_index) {
381 reqtype = iq->request_list[old].reqtype;
382 buf = iq->request_list[old].buf;
383
384 if (reqtype == REQTYPE_NONE)
385 goto skip_this;
386
387 octeon_update_tx_completion_counters(buf, reqtype, &pkts_compl,
388 &bytes_compl);
389
390 switch (reqtype) {
391 case REQTYPE_NORESP_NET:
392 case REQTYPE_NORESP_NET_SG:
393 case REQTYPE_RESP_NET_SG:
394 reqtype_free_fn[oct->octeon_id][reqtype](buf);
395 break;
396 case REQTYPE_RESP_NET:
397 case REQTYPE_SOFT_COMMAND:
398 sc = buf;
399
400 if (OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct))
401 irh = (struct octeon_instr_irh *)
402 &sc->cmd.cmd3.irh;
403 else
404 irh = (struct octeon_instr_irh *)
405 &sc->cmd.cmd2.irh;
406 if (irh->rflag) {
407 /* We're expecting a response from Octeon.
408 * It's up to lio_process_ordered_list() to
409 * process sc. Add sc to the ordered soft
410 * command response list because we expect
411 * a response from Octeon.
412 */
413 spin_lock_irqsave
414 (&oct->response_list
415 [OCTEON_ORDERED_SC_LIST].lock,
416 flags);
417 atomic_inc(&oct->response_list
418 [OCTEON_ORDERED_SC_LIST].
419 pending_req_count);
420 list_add_tail(&sc->node, &oct->response_list
421 [OCTEON_ORDERED_SC_LIST].head);
422 spin_unlock_irqrestore
423 (&oct->response_list
424 [OCTEON_ORDERED_SC_LIST].lock,
425 flags);
426 } else {
427 if (sc->callback) {
428 /* This callback must not sleep */
429 sc->callback(oct, OCTEON_REQUEST_DONE,
430 sc->callback_arg);
431 }
432 }
433 break;
434 default:
435 dev_err(&oct->pci_dev->dev,
436 "%s Unknown reqtype: %d buf: %p at idx %d\n",
437 __func__, reqtype, buf, old);
438 }
439
440 iq->request_list[old].buf = NULL;
441 iq->request_list[old].reqtype = 0;
442
443 skip_this:
444 inst_count++;
445 old = incr_index(old, 1, iq->max_count);
446
447 if ((napi_budget) && (inst_count >= napi_budget))
448 break;
449 }
450 if (bytes_compl)
451 octeon_report_tx_completion_to_bql(iq->app_ctx, pkts_compl,
452 bytes_compl);
453 iq->flush_index = old;
454
455 return inst_count;
456 }
457
458 /* Can only be called from process context */
459 int
460 octeon_flush_iq(struct octeon_device *oct, struct octeon_instr_queue *iq,
461 u32 napi_budget)
462 {
463 u32 inst_processed = 0;
464 u32 tot_inst_processed = 0;
465 int tx_done = 1;
466
467 if (!spin_trylock(&iq->iq_flush_running_lock))
468 return tx_done;
469
470 spin_lock_bh(&iq->lock);
471
472 iq->octeon_read_index = oct->fn_list.update_iq_read_idx(iq);
473
474 do {
475 /* Process any outstanding IQ packets. */
476 if (iq->flush_index == iq->octeon_read_index)
477 break;
478
479 if (napi_budget)
480 inst_processed =
481 lio_process_iq_request_list(oct, iq,
482 napi_budget -
483 tot_inst_processed);
484 else
485 inst_processed =
486 lio_process_iq_request_list(oct, iq, 0);
487
488 if (inst_processed) {
489 atomic_sub(inst_processed, &iq->instr_pending);
490 iq->stats.instr_processed += inst_processed;
491 }
492
493 tot_inst_processed += inst_processed;
494 } while (tot_inst_processed < napi_budget);
495
496 if (napi_budget && (tot_inst_processed >= napi_budget))
497 tx_done = 0;
498
499 iq->last_db_time = jiffies;
500
501 spin_unlock_bh(&iq->lock);
502
503 spin_unlock(&iq->iq_flush_running_lock);
504
505 return tx_done;
506 }
507
508 /* Process instruction queue after timeout.
509 * This routine gets called from a workqueue or when removing the module.
510 */
511 static void __check_db_timeout(struct octeon_device *oct, u64 iq_no)
512 {
513 struct octeon_instr_queue *iq;
514 u64 next_time;
515
516 if (!oct)
517 return;
518
519 iq = oct->instr_queue[iq_no];
520 if (!iq)
521 return;
522
523 /* return immediately, if no work pending */
524 if (!atomic_read(&iq->instr_pending))
525 return;
526 /* If jiffies - last_db_time < db_timeout do nothing */
527 next_time = iq->last_db_time + iq->db_timeout;
528 if (!time_after(jiffies, (unsigned long)next_time))
529 return;
530 iq->last_db_time = jiffies;
531
532 /* Flush the instruction queue */
533 octeon_flush_iq(oct, iq, 0);
534
535 lio_enable_irq(NULL, iq);
536 }
537
538 /* Called by the Poll thread at regular intervals to check the instruction
539 * queue for commands to be posted and for commands that were fetched by Octeon.
540 */
541 static void check_db_timeout(struct work_struct *work)
542 {
543 struct cavium_wk *wk = (struct cavium_wk *)work;
544 struct octeon_device *oct = (struct octeon_device *)wk->ctxptr;
545 u64 iq_no = wk->ctxul;
546 struct cavium_wq *db_wq = &oct->check_db_wq[iq_no];
547 u32 delay = 10;
548
549 __check_db_timeout(oct, iq_no);
550 queue_delayed_work(db_wq->wq, &db_wq->wk.work, msecs_to_jiffies(delay));
551 }
552
553 int
554 octeon_send_command(struct octeon_device *oct, u32 iq_no,
555 u32 force_db, void *cmd, void *buf,
556 u32 datasize, u32 reqtype)
557 {
558 int xmit_stopped;
559 struct iq_post_status st;
560 struct octeon_instr_queue *iq = oct->instr_queue[iq_no];
561
562 /* Get the lock and prevent other tasks and tx interrupt handler from
563 * running.
564 */
565 spin_lock_bh(&iq->post_lock);
566
567 st = __post_command2(iq, cmd);
568
569 if (st.status != IQ_SEND_FAILED) {
570 xmit_stopped = octeon_report_sent_bytes_to_bql(buf, reqtype);
571 __add_to_request_list(iq, st.index, buf, reqtype);
572 INCR_INSTRQUEUE_PKT_COUNT(oct, iq_no, bytes_sent, datasize);
573 INCR_INSTRQUEUE_PKT_COUNT(oct, iq_no, instr_posted, 1);
574
575 if (iq->fill_cnt >= MAX_OCTEON_FILL_COUNT || force_db ||
576 xmit_stopped || st.status == IQ_SEND_STOP)
577 ring_doorbell(oct, iq);
578 } else {
579 INCR_INSTRQUEUE_PKT_COUNT(oct, iq_no, instr_dropped, 1);
580 }
581
582 spin_unlock_bh(&iq->post_lock);
583
584 /* This is only done here to expedite packets being flushed
585 * for cases where there are no IQ completion interrupts.
586 */
587
588 return st.status;
589 }
590
591 void
592 octeon_prepare_soft_command(struct octeon_device *oct,
593 struct octeon_soft_command *sc,
594 u8 opcode,
595 u8 subcode,
596 u32 irh_ossp,
597 u64 ossp0,
598 u64 ossp1)
599 {
600 struct octeon_config *oct_cfg;
601 struct octeon_instr_ih2 *ih2;
602 struct octeon_instr_ih3 *ih3;
603 struct octeon_instr_pki_ih3 *pki_ih3;
604 struct octeon_instr_irh *irh;
605 struct octeon_instr_rdp *rdp;
606
607 WARN_ON(opcode > 15);
608 WARN_ON(subcode > 127);
609
610 oct_cfg = octeon_get_conf(oct);
611
612 if (OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct)) {
613 ih3 = (struct octeon_instr_ih3 *)&sc->cmd.cmd3.ih3;
614
615 ih3->pkind = oct->instr_queue[sc->iq_no]->txpciq.s.pkind;
616
617 pki_ih3 = (struct octeon_instr_pki_ih3 *)&sc->cmd.cmd3.pki_ih3;
618
619 pki_ih3->w = 1;
620 pki_ih3->raw = 1;
621 pki_ih3->utag = 1;
622 pki_ih3->uqpg =
623 oct->instr_queue[sc->iq_no]->txpciq.s.use_qpg;
624 pki_ih3->utt = 1;
625 pki_ih3->tag = LIO_CONTROL;
626 pki_ih3->tagtype = ATOMIC_TAG;
627 pki_ih3->qpg =
628 oct->instr_queue[sc->iq_no]->txpciq.s.qpg;
629 pki_ih3->pm = 0x7;
630 pki_ih3->sl = 8;
631
632 if (sc->datasize)
633 ih3->dlengsz = sc->datasize;
634
635 irh = (struct octeon_instr_irh *)&sc->cmd.cmd3.irh;
636 irh->opcode = opcode;
637 irh->subcode = subcode;
638
639 /* opcode/subcode specific parameters (ossp) */
640 irh->ossp = irh_ossp;
641 sc->cmd.cmd3.ossp[0] = ossp0;
642 sc->cmd.cmd3.ossp[1] = ossp1;
643
644 if (sc->rdatasize) {
645 rdp = (struct octeon_instr_rdp *)&sc->cmd.cmd3.rdp;
646 rdp->pcie_port = oct->pcie_port;
647 rdp->rlen = sc->rdatasize;
648
649 irh->rflag = 1;
650 /*PKI IH3*/
651 /* pki_ih3 irh+ossp[0]+ossp[1]+rdp+rptr = 48 bytes */
652 ih3->fsz = LIO_SOFTCMDRESP_IH3;
653 } else {
654 irh->rflag = 0;
655 /*PKI IH3*/
656 /* pki_h3 + irh + ossp[0] + ossp[1] = 32 bytes */
657 ih3->fsz = LIO_PCICMD_O3;
658 }
659
660 } else {
661 ih2 = (struct octeon_instr_ih2 *)&sc->cmd.cmd2.ih2;
662 ih2->tagtype = ATOMIC_TAG;
663 ih2->tag = LIO_CONTROL;
664 ih2->raw = 1;
665 ih2->grp = CFG_GET_CTRL_Q_GRP(oct_cfg);
666
667 if (sc->datasize) {
668 ih2->dlengsz = sc->datasize;
669 ih2->rs = 1;
670 }
671
672 irh = (struct octeon_instr_irh *)&sc->cmd.cmd2.irh;
673 irh->opcode = opcode;
674 irh->subcode = subcode;
675
676 /* opcode/subcode specific parameters (ossp) */
677 irh->ossp = irh_ossp;
678 sc->cmd.cmd2.ossp[0] = ossp0;
679 sc->cmd.cmd2.ossp[1] = ossp1;
680
681 if (sc->rdatasize) {
682 rdp = (struct octeon_instr_rdp *)&sc->cmd.cmd2.rdp;
683 rdp->pcie_port = oct->pcie_port;
684 rdp->rlen = sc->rdatasize;
685
686 irh->rflag = 1;
687 /* irh+ossp[0]+ossp[1]+rdp+rptr = 40 bytes */
688 ih2->fsz = LIO_SOFTCMDRESP_IH2;
689 } else {
690 irh->rflag = 0;
691 /* irh + ossp[0] + ossp[1] = 24 bytes */
692 ih2->fsz = LIO_PCICMD_O2;
693 }
694 }
695 }
696
697 int octeon_send_soft_command(struct octeon_device *oct,
698 struct octeon_soft_command *sc)
699 {
700 struct octeon_instr_ih2 *ih2;
701 struct octeon_instr_ih3 *ih3;
702 struct octeon_instr_irh *irh;
703 u32 len;
704
705 if (OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct)) {
706 ih3 = (struct octeon_instr_ih3 *)&sc->cmd.cmd3.ih3;
707 if (ih3->dlengsz) {
708 WARN_ON(!sc->dmadptr);
709 sc->cmd.cmd3.dptr = sc->dmadptr;
710 }
711 irh = (struct octeon_instr_irh *)&sc->cmd.cmd3.irh;
712 if (irh->rflag) {
713 WARN_ON(!sc->dmarptr);
714 WARN_ON(!sc->status_word);
715 *sc->status_word = COMPLETION_WORD_INIT;
716 sc->cmd.cmd3.rptr = sc->dmarptr;
717 }
718 len = (u32)ih3->dlengsz;
719 } else {
720 ih2 = (struct octeon_instr_ih2 *)&sc->cmd.cmd2.ih2;
721 if (ih2->dlengsz) {
722 WARN_ON(!sc->dmadptr);
723 sc->cmd.cmd2.dptr = sc->dmadptr;
724 }
725 irh = (struct octeon_instr_irh *)&sc->cmd.cmd2.irh;
726 if (irh->rflag) {
727 WARN_ON(!sc->dmarptr);
728 WARN_ON(!sc->status_word);
729 *sc->status_word = COMPLETION_WORD_INIT;
730 sc->cmd.cmd2.rptr = sc->dmarptr;
731 }
732 len = (u32)ih2->dlengsz;
733 }
734
735 if (sc->wait_time)
736 sc->timeout = jiffies + sc->wait_time;
737
738 return (octeon_send_command(oct, sc->iq_no, 1, &sc->cmd, sc,
739 len, REQTYPE_SOFT_COMMAND));
740 }
741
742 int octeon_setup_sc_buffer_pool(struct octeon_device *oct)
743 {
744 int i;
745 u64 dma_addr;
746 struct octeon_soft_command *sc;
747
748 INIT_LIST_HEAD(&oct->sc_buf_pool.head);
749 spin_lock_init(&oct->sc_buf_pool.lock);
750 atomic_set(&oct->sc_buf_pool.alloc_buf_count, 0);
751
752 for (i = 0; i < MAX_SOFT_COMMAND_BUFFERS; i++) {
753 sc = (struct octeon_soft_command *)
754 lio_dma_alloc(oct,
755 SOFT_COMMAND_BUFFER_SIZE,
756 (dma_addr_t *)&dma_addr);
757 if (!sc) {
758 octeon_free_sc_buffer_pool(oct);
759 return 1;
760 }
761
762 sc->dma_addr = dma_addr;
763 sc->size = SOFT_COMMAND_BUFFER_SIZE;
764
765 list_add_tail(&sc->node, &oct->sc_buf_pool.head);
766 }
767
768 return 0;
769 }
770
771 int octeon_free_sc_buffer_pool(struct octeon_device *oct)
772 {
773 struct list_head *tmp, *tmp2;
774 struct octeon_soft_command *sc;
775
776 spin_lock_bh(&oct->sc_buf_pool.lock);
777
778 list_for_each_safe(tmp, tmp2, &oct->sc_buf_pool.head) {
779 list_del(tmp);
780
781 sc = (struct octeon_soft_command *)tmp;
782
783 lio_dma_free(oct, sc->size, sc, sc->dma_addr);
784 }
785
786 INIT_LIST_HEAD(&oct->sc_buf_pool.head);
787
788 spin_unlock_bh(&oct->sc_buf_pool.lock);
789
790 return 0;
791 }
792
793 struct octeon_soft_command *octeon_alloc_soft_command(struct octeon_device *oct,
794 u32 datasize,
795 u32 rdatasize,
796 u32 ctxsize)
797 {
798 u64 dma_addr;
799 u32 size;
800 u32 offset = sizeof(struct octeon_soft_command);
801 struct octeon_soft_command *sc = NULL;
802 struct list_head *tmp;
803
804 WARN_ON((offset + datasize + rdatasize + ctxsize) >
805 SOFT_COMMAND_BUFFER_SIZE);
806
807 spin_lock_bh(&oct->sc_buf_pool.lock);
808
809 if (list_empty(&oct->sc_buf_pool.head)) {
810 spin_unlock_bh(&oct->sc_buf_pool.lock);
811 return NULL;
812 }
813
814 list_for_each(tmp, &oct->sc_buf_pool.head)
815 break;
816
817 list_del(tmp);
818
819 atomic_inc(&oct->sc_buf_pool.alloc_buf_count);
820
821 spin_unlock_bh(&oct->sc_buf_pool.lock);
822
823 sc = (struct octeon_soft_command *)tmp;
824
825 dma_addr = sc->dma_addr;
826 size = sc->size;
827
828 memset(sc, 0, sc->size);
829
830 sc->dma_addr = dma_addr;
831 sc->size = size;
832
833 if (ctxsize) {
834 sc->ctxptr = (u8 *)sc + offset;
835 sc->ctxsize = ctxsize;
836 }
837
838 /* Start data at 128 byte boundary */
839 offset = (offset + ctxsize + 127) & 0xffffff80;
840
841 if (datasize) {
842 sc->virtdptr = (u8 *)sc + offset;
843 sc->dmadptr = dma_addr + offset;
844 sc->datasize = datasize;
845 }
846
847 /* Start rdata at 128 byte boundary */
848 offset = (offset + datasize + 127) & 0xffffff80;
849
850 if (rdatasize) {
851 WARN_ON(rdatasize < 16);
852 sc->virtrptr = (u8 *)sc + offset;
853 sc->dmarptr = dma_addr + offset;
854 sc->rdatasize = rdatasize;
855 sc->status_word = (u64 *)((u8 *)(sc->virtrptr) + rdatasize - 8);
856 }
857
858 return sc;
859 }
860
861 void octeon_free_soft_command(struct octeon_device *oct,
862 struct octeon_soft_command *sc)
863 {
864 spin_lock_bh(&oct->sc_buf_pool.lock);
865
866 list_add_tail(&sc->node, &oct->sc_buf_pool.head);
867
868 atomic_dec(&oct->sc_buf_pool.alloc_buf_count);
869
870 spin_unlock_bh(&oct->sc_buf_pool.lock);
871 }
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