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Merge tag 'for-linus-20170825' of git://git.infradead.org/linux-mtd
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / cavium / thunder / thunder_bgx.c
1 /*
2 * Copyright (C) 2015 Cavium, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
9 #include <linux/acpi.h>
10 #include <linux/module.h>
11 #include <linux/interrupt.h>
12 #include <linux/pci.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/phy.h>
16 #include <linux/of.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_net.h>
19
20 #include "nic_reg.h"
21 #include "nic.h"
22 #include "thunder_bgx.h"
23
24 #define DRV_NAME "thunder-BGX"
25 #define DRV_VERSION "1.0"
26
27 struct lmac {
28 struct bgx *bgx;
29 int dmac;
30 u8 mac[ETH_ALEN];
31 u8 lmac_type;
32 u8 lane_to_sds;
33 bool use_training;
34 bool autoneg;
35 bool link_up;
36 int lmacid; /* ID within BGX */
37 int lmacid_bd; /* ID on board */
38 struct net_device netdev;
39 struct phy_device *phydev;
40 unsigned int last_duplex;
41 unsigned int last_link;
42 unsigned int last_speed;
43 bool is_sgmii;
44 struct delayed_work dwork;
45 struct workqueue_struct *check_link;
46 };
47
48 struct bgx {
49 u8 bgx_id;
50 struct lmac lmac[MAX_LMAC_PER_BGX];
51 u8 lmac_count;
52 u8 max_lmac;
53 u8 acpi_lmac_idx;
54 void __iomem *reg_base;
55 struct pci_dev *pdev;
56 bool is_dlm;
57 bool is_rgx;
58 };
59
60 static struct bgx *bgx_vnic[MAX_BGX_THUNDER];
61 static int lmac_count; /* Total no of LMACs in system */
62
63 static int bgx_xaui_check_link(struct lmac *lmac);
64
65 /* Supported devices */
66 static const struct pci_device_id bgx_id_table[] = {
67 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_BGX) },
68 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_RGX) },
69 { 0, } /* end of table */
70 };
71
72 MODULE_AUTHOR("Cavium Inc");
73 MODULE_DESCRIPTION("Cavium Thunder BGX/MAC Driver");
74 MODULE_LICENSE("GPL v2");
75 MODULE_VERSION(DRV_VERSION);
76 MODULE_DEVICE_TABLE(pci, bgx_id_table);
77
78 /* The Cavium ThunderX network controller can *only* be found in SoCs
79 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
80 * registers on this platform are implicitly strongly ordered with respect
81 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
82 * with no memory barriers in this driver. The readq()/writeq() functions add
83 * explicit ordering operation which in this case are redundant, and only
84 * add overhead.
85 */
86
87 /* Register read/write APIs */
88 static u64 bgx_reg_read(struct bgx *bgx, u8 lmac, u64 offset)
89 {
90 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
91
92 return readq_relaxed(addr);
93 }
94
95 static void bgx_reg_write(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
96 {
97 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
98
99 writeq_relaxed(val, addr);
100 }
101
102 static void bgx_reg_modify(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
103 {
104 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
105
106 writeq_relaxed(val | readq_relaxed(addr), addr);
107 }
108
109 static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero)
110 {
111 int timeout = 100;
112 u64 reg_val;
113
114 while (timeout) {
115 reg_val = bgx_reg_read(bgx, lmac, reg);
116 if (zero && !(reg_val & mask))
117 return 0;
118 if (!zero && (reg_val & mask))
119 return 0;
120 usleep_range(1000, 2000);
121 timeout--;
122 }
123 return 1;
124 }
125
126 static int max_bgx_per_node;
127 static void set_max_bgx_per_node(struct pci_dev *pdev)
128 {
129 u16 sdevid;
130
131 if (max_bgx_per_node)
132 return;
133
134 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid);
135 switch (sdevid) {
136 case PCI_SUBSYS_DEVID_81XX_BGX:
137 case PCI_SUBSYS_DEVID_81XX_RGX:
138 max_bgx_per_node = MAX_BGX_PER_CN81XX;
139 break;
140 case PCI_SUBSYS_DEVID_83XX_BGX:
141 max_bgx_per_node = MAX_BGX_PER_CN83XX;
142 break;
143 case PCI_SUBSYS_DEVID_88XX_BGX:
144 default:
145 max_bgx_per_node = MAX_BGX_PER_CN88XX;
146 break;
147 }
148 }
149
150 static struct bgx *get_bgx(int node, int bgx_idx)
151 {
152 int idx = (node * max_bgx_per_node) + bgx_idx;
153
154 return bgx_vnic[idx];
155 }
156
157 /* Return number of BGX present in HW */
158 unsigned bgx_get_map(int node)
159 {
160 int i;
161 unsigned map = 0;
162
163 for (i = 0; i < max_bgx_per_node; i++) {
164 if (bgx_vnic[(node * max_bgx_per_node) + i])
165 map |= (1 << i);
166 }
167
168 return map;
169 }
170 EXPORT_SYMBOL(bgx_get_map);
171
172 /* Return number of LMAC configured for this BGX */
173 int bgx_get_lmac_count(int node, int bgx_idx)
174 {
175 struct bgx *bgx;
176
177 bgx = get_bgx(node, bgx_idx);
178 if (bgx)
179 return bgx->lmac_count;
180
181 return 0;
182 }
183 EXPORT_SYMBOL(bgx_get_lmac_count);
184
185 /* Returns the current link status of LMAC */
186 void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status)
187 {
188 struct bgx_link_status *link = (struct bgx_link_status *)status;
189 struct bgx *bgx;
190 struct lmac *lmac;
191
192 bgx = get_bgx(node, bgx_idx);
193 if (!bgx)
194 return;
195
196 lmac = &bgx->lmac[lmacid];
197 link->mac_type = lmac->lmac_type;
198 link->link_up = lmac->link_up;
199 link->duplex = lmac->last_duplex;
200 link->speed = lmac->last_speed;
201 }
202 EXPORT_SYMBOL(bgx_get_lmac_link_state);
203
204 const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid)
205 {
206 struct bgx *bgx = get_bgx(node, bgx_idx);
207
208 if (bgx)
209 return bgx->lmac[lmacid].mac;
210
211 return NULL;
212 }
213 EXPORT_SYMBOL(bgx_get_lmac_mac);
214
215 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac)
216 {
217 struct bgx *bgx = get_bgx(node, bgx_idx);
218
219 if (!bgx)
220 return;
221
222 ether_addr_copy(bgx->lmac[lmacid].mac, mac);
223 }
224 EXPORT_SYMBOL(bgx_set_lmac_mac);
225
226 void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable)
227 {
228 struct bgx *bgx = get_bgx(node, bgx_idx);
229 struct lmac *lmac;
230 u64 cfg;
231
232 if (!bgx)
233 return;
234 lmac = &bgx->lmac[lmacid];
235
236 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
237 if (enable)
238 cfg |= CMR_PKT_RX_EN | CMR_PKT_TX_EN;
239 else
240 cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
241 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
242
243 if (bgx->is_rgx)
244 xcv_setup_link(enable ? lmac->link_up : 0, lmac->last_speed);
245 }
246 EXPORT_SYMBOL(bgx_lmac_rx_tx_enable);
247
248 void bgx_lmac_get_pfc(int node, int bgx_idx, int lmacid, void *pause)
249 {
250 struct pfc *pfc = (struct pfc *)pause;
251 struct bgx *bgx = get_bgx(node, bgx_idx);
252 struct lmac *lmac;
253 u64 cfg;
254
255 if (!bgx)
256 return;
257 lmac = &bgx->lmac[lmacid];
258 if (lmac->is_sgmii)
259 return;
260
261 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_CBFC_CTL);
262 pfc->fc_rx = cfg & RX_EN;
263 pfc->fc_tx = cfg & TX_EN;
264 pfc->autoneg = 0;
265 }
266 EXPORT_SYMBOL(bgx_lmac_get_pfc);
267
268 void bgx_lmac_set_pfc(int node, int bgx_idx, int lmacid, void *pause)
269 {
270 struct pfc *pfc = (struct pfc *)pause;
271 struct bgx *bgx = get_bgx(node, bgx_idx);
272 struct lmac *lmac;
273 u64 cfg;
274
275 if (!bgx)
276 return;
277 lmac = &bgx->lmac[lmacid];
278 if (lmac->is_sgmii)
279 return;
280
281 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_CBFC_CTL);
282 cfg &= ~(RX_EN | TX_EN);
283 cfg |= (pfc->fc_rx ? RX_EN : 0x00);
284 cfg |= (pfc->fc_tx ? TX_EN : 0x00);
285 bgx_reg_write(bgx, lmacid, BGX_SMUX_CBFC_CTL, cfg);
286 }
287 EXPORT_SYMBOL(bgx_lmac_set_pfc);
288
289 static void bgx_sgmii_change_link_state(struct lmac *lmac)
290 {
291 struct bgx *bgx = lmac->bgx;
292 u64 cmr_cfg;
293 u64 port_cfg = 0;
294 u64 misc_ctl = 0;
295 bool tx_en, rx_en;
296
297 cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG);
298 tx_en = cmr_cfg & CMR_PKT_TX_EN;
299 rx_en = cmr_cfg & CMR_PKT_RX_EN;
300 cmr_cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
301 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
302
303 /* Wait for BGX RX to be idle */
304 if (bgx_poll_reg(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG,
305 GMI_PORT_CFG_RX_IDLE, false)) {
306 dev_err(&bgx->pdev->dev, "BGX%d LMAC%d GMI RX not idle\n",
307 bgx->bgx_id, lmac->lmacid);
308 return;
309 }
310
311 /* Wait for BGX TX to be idle */
312 if (bgx_poll_reg(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG,
313 GMI_PORT_CFG_TX_IDLE, false)) {
314 dev_err(&bgx->pdev->dev, "BGX%d LMAC%d GMI TX not idle\n",
315 bgx->bgx_id, lmac->lmacid);
316 return;
317 }
318
319 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
320 misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL);
321
322 if (lmac->link_up) {
323 misc_ctl &= ~PCS_MISC_CTL_GMX_ENO;
324 port_cfg &= ~GMI_PORT_CFG_DUPLEX;
325 port_cfg |= (lmac->last_duplex << 2);
326 } else {
327 misc_ctl |= PCS_MISC_CTL_GMX_ENO;
328 }
329
330 switch (lmac->last_speed) {
331 case 10:
332 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
333 port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */
334 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
335 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
336 misc_ctl |= 50; /* samp_pt */
337 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
338 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
339 break;
340 case 100:
341 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
342 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
343 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
344 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
345 misc_ctl |= 5; /* samp_pt */
346 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
347 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
348 break;
349 case 1000:
350 port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */
351 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
352 port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */
353 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
354 misc_ctl |= 1; /* samp_pt */
355 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512);
356 if (lmac->last_duplex)
357 bgx_reg_write(bgx, lmac->lmacid,
358 BGX_GMP_GMI_TXX_BURST, 0);
359 else
360 bgx_reg_write(bgx, lmac->lmacid,
361 BGX_GMP_GMI_TXX_BURST, 8192);
362 break;
363 default:
364 break;
365 }
366 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl);
367 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg);
368
369 /* Restore CMR config settings */
370 cmr_cfg |= (rx_en ? CMR_PKT_RX_EN : 0) | (tx_en ? CMR_PKT_TX_EN : 0);
371 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
372
373 if (bgx->is_rgx && (cmr_cfg & (CMR_PKT_RX_EN | CMR_PKT_TX_EN)))
374 xcv_setup_link(lmac->link_up, lmac->last_speed);
375 }
376
377 static void bgx_lmac_handler(struct net_device *netdev)
378 {
379 struct lmac *lmac = container_of(netdev, struct lmac, netdev);
380 struct phy_device *phydev;
381 int link_changed = 0;
382
383 if (!lmac)
384 return;
385
386 phydev = lmac->phydev;
387
388 if (!phydev->link && lmac->last_link)
389 link_changed = -1;
390
391 if (phydev->link &&
392 (lmac->last_duplex != phydev->duplex ||
393 lmac->last_link != phydev->link ||
394 lmac->last_speed != phydev->speed)) {
395 link_changed = 1;
396 }
397
398 lmac->last_link = phydev->link;
399 lmac->last_speed = phydev->speed;
400 lmac->last_duplex = phydev->duplex;
401
402 if (!link_changed)
403 return;
404
405 if (link_changed > 0)
406 lmac->link_up = true;
407 else
408 lmac->link_up = false;
409
410 if (lmac->is_sgmii)
411 bgx_sgmii_change_link_state(lmac);
412 else
413 bgx_xaui_check_link(lmac);
414 }
415
416 u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx)
417 {
418 struct bgx *bgx;
419
420 bgx = get_bgx(node, bgx_idx);
421 if (!bgx)
422 return 0;
423
424 if (idx > 8)
425 lmac = 0;
426 return bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8));
427 }
428 EXPORT_SYMBOL(bgx_get_rx_stats);
429
430 u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx)
431 {
432 struct bgx *bgx;
433
434 bgx = get_bgx(node, bgx_idx);
435 if (!bgx)
436 return 0;
437
438 return bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8));
439 }
440 EXPORT_SYMBOL(bgx_get_tx_stats);
441
442 static void bgx_flush_dmac_addrs(struct bgx *bgx, int lmac)
443 {
444 u64 offset;
445
446 while (bgx->lmac[lmac].dmac > 0) {
447 offset = ((bgx->lmac[lmac].dmac - 1) * sizeof(u64)) +
448 (lmac * MAX_DMAC_PER_LMAC * sizeof(u64));
449 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + offset, 0);
450 bgx->lmac[lmac].dmac--;
451 }
452 }
453
454 /* Configure BGX LMAC in internal loopback mode */
455 void bgx_lmac_internal_loopback(int node, int bgx_idx,
456 int lmac_idx, bool enable)
457 {
458 struct bgx *bgx;
459 struct lmac *lmac;
460 u64 cfg;
461
462 bgx = get_bgx(node, bgx_idx);
463 if (!bgx)
464 return;
465
466 lmac = &bgx->lmac[lmac_idx];
467 if (lmac->is_sgmii) {
468 cfg = bgx_reg_read(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL);
469 if (enable)
470 cfg |= PCS_MRX_CTL_LOOPBACK1;
471 else
472 cfg &= ~PCS_MRX_CTL_LOOPBACK1;
473 bgx_reg_write(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL, cfg);
474 } else {
475 cfg = bgx_reg_read(bgx, lmac_idx, BGX_SPUX_CONTROL1);
476 if (enable)
477 cfg |= SPU_CTL_LOOPBACK;
478 else
479 cfg &= ~SPU_CTL_LOOPBACK;
480 bgx_reg_write(bgx, lmac_idx, BGX_SPUX_CONTROL1, cfg);
481 }
482 }
483 EXPORT_SYMBOL(bgx_lmac_internal_loopback);
484
485 static int bgx_lmac_sgmii_init(struct bgx *bgx, struct lmac *lmac)
486 {
487 int lmacid = lmac->lmacid;
488 u64 cfg;
489
490 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30);
491 /* max packet size */
492 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE);
493
494 /* Disable frame alignment if using preamble */
495 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
496 if (cfg & 1)
497 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0);
498
499 /* Enable lmac */
500 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
501
502 /* PCS reset */
503 bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET);
504 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL,
505 PCS_MRX_CTL_RESET, true)) {
506 dev_err(&bgx->pdev->dev, "BGX PCS reset not completed\n");
507 return -1;
508 }
509
510 /* power down, reset autoneg, autoneg enable */
511 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL);
512 cfg &= ~PCS_MRX_CTL_PWR_DN;
513 cfg |= PCS_MRX_CTL_RST_AN;
514 if (lmac->phydev) {
515 cfg |= PCS_MRX_CTL_AN_EN;
516 } else {
517 /* In scenarios where PHY driver is not present or it's a
518 * non-standard PHY, FW sets AN_EN to inform Linux driver
519 * to do auto-neg and link polling or not.
520 */
521 if (cfg & PCS_MRX_CTL_AN_EN)
522 lmac->autoneg = true;
523 }
524 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg);
525
526 if (lmac->lmac_type == BGX_MODE_QSGMII) {
527 /* Disable disparity check for QSGMII */
528 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL);
529 cfg &= ~PCS_MISC_CTL_DISP_EN;
530 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL, cfg);
531 return 0;
532 }
533
534 if ((lmac->lmac_type == BGX_MODE_SGMII) && lmac->phydev) {
535 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS,
536 PCS_MRX_STATUS_AN_CPT, false)) {
537 dev_err(&bgx->pdev->dev, "BGX AN_CPT not completed\n");
538 return -1;
539 }
540 }
541
542 return 0;
543 }
544
545 static int bgx_lmac_xaui_init(struct bgx *bgx, struct lmac *lmac)
546 {
547 u64 cfg;
548 int lmacid = lmac->lmacid;
549
550 /* Reset SPU */
551 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET);
552 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
553 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
554 return -1;
555 }
556
557 /* Disable LMAC */
558 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
559 cfg &= ~CMR_EN;
560 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
561
562 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
563 /* Set interleaved running disparity for RXAUI */
564 if (lmac->lmac_type == BGX_MODE_RXAUI)
565 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL,
566 SPU_MISC_CTL_INTLV_RDISP);
567
568 /* Clear receive packet disable */
569 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL);
570 cfg &= ~SPU_MISC_CTL_RX_DIS;
571 bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg);
572
573 /* clear all interrupts */
574 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT);
575 bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg);
576 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT);
577 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg);
578 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
579 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
580
581 if (lmac->use_training) {
582 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00);
583 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00);
584 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00);
585 /* training enable */
586 bgx_reg_modify(bgx, lmacid,
587 BGX_SPUX_BR_PMD_CRTL, SPU_PMD_CRTL_TRAIN_EN);
588 }
589
590 /* Append FCS to each packet */
591 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D);
592
593 /* Disable forward error correction */
594 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL);
595 cfg &= ~SPU_FEC_CTL_FEC_EN;
596 bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg);
597
598 /* Disable autoneg */
599 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL);
600 cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN);
601 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg);
602
603 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV);
604 if (lmac->lmac_type == BGX_MODE_10G_KR)
605 cfg |= (1 << 23);
606 else if (lmac->lmac_type == BGX_MODE_40G_KR)
607 cfg |= (1 << 24);
608 else
609 cfg &= ~((1 << 23) | (1 << 24));
610 cfg = cfg & (~((1ULL << 25) | (1ULL << 22) | (1ULL << 12)));
611 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg);
612
613 cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL);
614 cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN;
615 bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg);
616
617 /* Enable lmac */
618 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
619
620 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1);
621 cfg &= ~SPU_CTL_LOW_POWER;
622 bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg);
623
624 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL);
625 cfg &= ~SMU_TX_CTL_UNI_EN;
626 cfg |= SMU_TX_CTL_DIC_EN;
627 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg);
628
629 /* Enable receive and transmission of pause frames */
630 bgx_reg_write(bgx, lmacid, BGX_SMUX_CBFC_CTL, ((0xffffULL << 32) |
631 BCK_EN | DRP_EN | TX_EN | RX_EN));
632 /* Configure pause time and interval */
633 bgx_reg_write(bgx, lmacid,
634 BGX_SMUX_TX_PAUSE_PKT_TIME, DEFAULT_PAUSE_TIME);
635 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_PAUSE_PKT_INTERVAL);
636 cfg &= ~0xFFFFull;
637 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_PAUSE_PKT_INTERVAL,
638 cfg | (DEFAULT_PAUSE_TIME - 0x1000));
639 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_PAUSE_ZERO, 0x01);
640
641 /* take lmac_count into account */
642 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1));
643 /* max packet size */
644 bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE);
645
646 return 0;
647 }
648
649 static int bgx_xaui_check_link(struct lmac *lmac)
650 {
651 struct bgx *bgx = lmac->bgx;
652 int lmacid = lmac->lmacid;
653 int lmac_type = lmac->lmac_type;
654 u64 cfg;
655
656 if (lmac->use_training) {
657 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
658 if (!(cfg & (1ull << 13))) {
659 cfg = (1ull << 13) | (1ull << 14);
660 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
661 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL);
662 cfg |= (1ull << 0);
663 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg);
664 return -1;
665 }
666 }
667
668 /* wait for PCS to come out of reset */
669 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
670 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
671 return -1;
672 }
673
674 if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) ||
675 (lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) {
676 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1,
677 SPU_BR_STATUS_BLK_LOCK, false)) {
678 dev_err(&bgx->pdev->dev,
679 "SPU_BR_STATUS_BLK_LOCK not completed\n");
680 return -1;
681 }
682 } else {
683 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS,
684 SPU_BX_STATUS_RX_ALIGN, false)) {
685 dev_err(&bgx->pdev->dev,
686 "SPU_BX_STATUS_RX_ALIGN not completed\n");
687 return -1;
688 }
689 }
690
691 /* Clear rcvflt bit (latching high) and read it back */
692 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT)
693 bgx_reg_modify(bgx, lmacid,
694 BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT);
695 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) {
696 dev_err(&bgx->pdev->dev, "Receive fault, retry training\n");
697 if (lmac->use_training) {
698 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
699 if (!(cfg & (1ull << 13))) {
700 cfg = (1ull << 13) | (1ull << 14);
701 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
702 cfg = bgx_reg_read(bgx, lmacid,
703 BGX_SPUX_BR_PMD_CRTL);
704 cfg |= (1ull << 0);
705 bgx_reg_write(bgx, lmacid,
706 BGX_SPUX_BR_PMD_CRTL, cfg);
707 return -1;
708 }
709 }
710 return -1;
711 }
712
713 /* Wait for BGX RX to be idle */
714 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_RX_IDLE, false)) {
715 dev_err(&bgx->pdev->dev, "SMU RX not idle\n");
716 return -1;
717 }
718
719 /* Wait for BGX TX to be idle */
720 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_TX_IDLE, false)) {
721 dev_err(&bgx->pdev->dev, "SMU TX not idle\n");
722 return -1;
723 }
724
725 /* Check for MAC RX faults */
726 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_CTL);
727 /* 0 - Link is okay, 1 - Local fault, 2 - Remote fault */
728 cfg &= SMU_RX_CTL_STATUS;
729 if (!cfg)
730 return 0;
731
732 /* Rx local/remote fault seen.
733 * Do lmac reinit to see if condition recovers
734 */
735 bgx_lmac_xaui_init(bgx, lmac);
736
737 return -1;
738 }
739
740 static void bgx_poll_for_sgmii_link(struct lmac *lmac)
741 {
742 u64 pcs_link, an_result;
743 u8 speed;
744
745 pcs_link = bgx_reg_read(lmac->bgx, lmac->lmacid,
746 BGX_GMP_PCS_MRX_STATUS);
747
748 /*Link state bit is sticky, read it again*/
749 if (!(pcs_link & PCS_MRX_STATUS_LINK))
750 pcs_link = bgx_reg_read(lmac->bgx, lmac->lmacid,
751 BGX_GMP_PCS_MRX_STATUS);
752
753 if (bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_GMP_PCS_MRX_STATUS,
754 PCS_MRX_STATUS_AN_CPT, false)) {
755 lmac->link_up = false;
756 lmac->last_speed = SPEED_UNKNOWN;
757 lmac->last_duplex = DUPLEX_UNKNOWN;
758 goto next_poll;
759 }
760
761 lmac->link_up = ((pcs_link & PCS_MRX_STATUS_LINK) != 0) ? true : false;
762 an_result = bgx_reg_read(lmac->bgx, lmac->lmacid,
763 BGX_GMP_PCS_ANX_AN_RESULTS);
764
765 speed = (an_result >> 3) & 0x3;
766 lmac->last_duplex = (an_result >> 1) & 0x1;
767 switch (speed) {
768 case 0:
769 lmac->last_speed = 10;
770 break;
771 case 1:
772 lmac->last_speed = 100;
773 break;
774 case 2:
775 lmac->last_speed = 1000;
776 break;
777 default:
778 lmac->link_up = false;
779 lmac->last_speed = SPEED_UNKNOWN;
780 lmac->last_duplex = DUPLEX_UNKNOWN;
781 break;
782 }
783
784 next_poll:
785
786 if (lmac->last_link != lmac->link_up) {
787 if (lmac->link_up)
788 bgx_sgmii_change_link_state(lmac);
789 lmac->last_link = lmac->link_up;
790 }
791
792 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 3);
793 }
794
795 static void bgx_poll_for_link(struct work_struct *work)
796 {
797 struct lmac *lmac;
798 u64 spu_link, smu_link;
799
800 lmac = container_of(work, struct lmac, dwork.work);
801 if (lmac->is_sgmii) {
802 bgx_poll_for_sgmii_link(lmac);
803 return;
804 }
805
806 /* Receive link is latching low. Force it high and verify it */
807 bgx_reg_modify(lmac->bgx, lmac->lmacid,
808 BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK);
809 bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1,
810 SPU_STATUS1_RCV_LNK, false);
811
812 spu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1);
813 smu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SMUX_RX_CTL);
814
815 if ((spu_link & SPU_STATUS1_RCV_LNK) &&
816 !(smu_link & SMU_RX_CTL_STATUS)) {
817 lmac->link_up = 1;
818 if (lmac->lmac_type == BGX_MODE_XLAUI)
819 lmac->last_speed = 40000;
820 else
821 lmac->last_speed = 10000;
822 lmac->last_duplex = 1;
823 } else {
824 lmac->link_up = 0;
825 lmac->last_speed = SPEED_UNKNOWN;
826 lmac->last_duplex = DUPLEX_UNKNOWN;
827 }
828
829 if (lmac->last_link != lmac->link_up) {
830 if (lmac->link_up) {
831 if (bgx_xaui_check_link(lmac)) {
832 /* Errors, clear link_up state */
833 lmac->link_up = 0;
834 lmac->last_speed = SPEED_UNKNOWN;
835 lmac->last_duplex = DUPLEX_UNKNOWN;
836 }
837 }
838 lmac->last_link = lmac->link_up;
839 }
840
841 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 2);
842 }
843
844 static int phy_interface_mode(u8 lmac_type)
845 {
846 if (lmac_type == BGX_MODE_QSGMII)
847 return PHY_INTERFACE_MODE_QSGMII;
848 if (lmac_type == BGX_MODE_RGMII)
849 return PHY_INTERFACE_MODE_RGMII;
850
851 return PHY_INTERFACE_MODE_SGMII;
852 }
853
854 static int bgx_lmac_enable(struct bgx *bgx, u8 lmacid)
855 {
856 struct lmac *lmac;
857 u64 cfg;
858
859 lmac = &bgx->lmac[lmacid];
860 lmac->bgx = bgx;
861
862 if ((lmac->lmac_type == BGX_MODE_SGMII) ||
863 (lmac->lmac_type == BGX_MODE_QSGMII) ||
864 (lmac->lmac_type == BGX_MODE_RGMII)) {
865 lmac->is_sgmii = 1;
866 if (bgx_lmac_sgmii_init(bgx, lmac))
867 return -1;
868 } else {
869 lmac->is_sgmii = 0;
870 if (bgx_lmac_xaui_init(bgx, lmac))
871 return -1;
872 }
873
874 if (lmac->is_sgmii) {
875 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
876 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
877 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg);
878 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1);
879 } else {
880 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND);
881 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
882 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg);
883 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4);
884 }
885
886 /* Enable lmac */
887 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
888
889 /* Restore default cfg, incase low level firmware changed it */
890 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03);
891
892 if ((lmac->lmac_type != BGX_MODE_XFI) &&
893 (lmac->lmac_type != BGX_MODE_XLAUI) &&
894 (lmac->lmac_type != BGX_MODE_40G_KR) &&
895 (lmac->lmac_type != BGX_MODE_10G_KR)) {
896 if (!lmac->phydev) {
897 if (lmac->autoneg) {
898 bgx_reg_write(bgx, lmacid,
899 BGX_GMP_PCS_LINKX_TIMER,
900 PCS_LINKX_TIMER_COUNT);
901 goto poll;
902 } else {
903 /* Default to below link speed and duplex */
904 lmac->link_up = true;
905 lmac->last_speed = 1000;
906 lmac->last_duplex = 1;
907 bgx_sgmii_change_link_state(lmac);
908 return 0;
909 }
910 }
911 lmac->phydev->dev_flags = 0;
912
913 if (phy_connect_direct(&lmac->netdev, lmac->phydev,
914 bgx_lmac_handler,
915 phy_interface_mode(lmac->lmac_type)))
916 return -ENODEV;
917
918 phy_start_aneg(lmac->phydev);
919 return 0;
920 }
921
922 poll:
923 lmac->check_link = alloc_workqueue("check_link", WQ_UNBOUND |
924 WQ_MEM_RECLAIM, 1);
925 if (!lmac->check_link)
926 return -ENOMEM;
927 INIT_DELAYED_WORK(&lmac->dwork, bgx_poll_for_link);
928 queue_delayed_work(lmac->check_link, &lmac->dwork, 0);
929
930 return 0;
931 }
932
933 static void bgx_lmac_disable(struct bgx *bgx, u8 lmacid)
934 {
935 struct lmac *lmac;
936 u64 cfg;
937
938 lmac = &bgx->lmac[lmacid];
939 if (lmac->check_link) {
940 /* Destroy work queue */
941 cancel_delayed_work_sync(&lmac->dwork);
942 destroy_workqueue(lmac->check_link);
943 }
944
945 /* Disable packet reception */
946 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
947 cfg &= ~CMR_PKT_RX_EN;
948 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
949
950 /* Give chance for Rx/Tx FIFO to get drained */
951 bgx_poll_reg(bgx, lmacid, BGX_CMRX_RX_FIFO_LEN, (u64)0x1FFF, true);
952 bgx_poll_reg(bgx, lmacid, BGX_CMRX_TX_FIFO_LEN, (u64)0x3FFF, true);
953
954 /* Disable packet transmission */
955 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
956 cfg &= ~CMR_PKT_TX_EN;
957 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
958
959 /* Disable serdes lanes */
960 if (!lmac->is_sgmii)
961 bgx_reg_modify(bgx, lmacid,
962 BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
963 else
964 bgx_reg_modify(bgx, lmacid,
965 BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_PWR_DN);
966
967 /* Disable LMAC */
968 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
969 cfg &= ~CMR_EN;
970 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
971
972 bgx_flush_dmac_addrs(bgx, lmacid);
973
974 if ((lmac->lmac_type != BGX_MODE_XFI) &&
975 (lmac->lmac_type != BGX_MODE_XLAUI) &&
976 (lmac->lmac_type != BGX_MODE_40G_KR) &&
977 (lmac->lmac_type != BGX_MODE_10G_KR) && lmac->phydev)
978 phy_disconnect(lmac->phydev);
979
980 lmac->phydev = NULL;
981 }
982
983 static void bgx_init_hw(struct bgx *bgx)
984 {
985 int i;
986 struct lmac *lmac;
987
988 bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP);
989 if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS))
990 dev_err(&bgx->pdev->dev, "BGX%d BIST failed\n", bgx->bgx_id);
991
992 /* Set lmac type and lane2serdes mapping */
993 for (i = 0; i < bgx->lmac_count; i++) {
994 lmac = &bgx->lmac[i];
995 bgx_reg_write(bgx, i, BGX_CMRX_CFG,
996 (lmac->lmac_type << 8) | lmac->lane_to_sds);
997 bgx->lmac[i].lmacid_bd = lmac_count;
998 lmac_count++;
999 }
1000
1001 bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count);
1002 bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count);
1003
1004 /* Set the backpressure AND mask */
1005 for (i = 0; i < bgx->lmac_count; i++)
1006 bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND,
1007 ((1ULL << MAX_BGX_CHANS_PER_LMAC) - 1) <<
1008 (i * MAX_BGX_CHANS_PER_LMAC));
1009
1010 /* Disable all MAC filtering */
1011 for (i = 0; i < RX_DMAC_COUNT; i++)
1012 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00);
1013
1014 /* Disable MAC steering (NCSI traffic) */
1015 for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++)
1016 bgx_reg_write(bgx, 0, BGX_CMR_RX_STREERING + (i * 8), 0x00);
1017 }
1018
1019 static u8 bgx_get_lane2sds_cfg(struct bgx *bgx, struct lmac *lmac)
1020 {
1021 return (u8)(bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG) & 0xFF);
1022 }
1023
1024 static void bgx_print_qlm_mode(struct bgx *bgx, u8 lmacid)
1025 {
1026 struct device *dev = &bgx->pdev->dev;
1027 struct lmac *lmac;
1028 char str[27];
1029
1030 if (!bgx->is_dlm && lmacid)
1031 return;
1032
1033 lmac = &bgx->lmac[lmacid];
1034 if (!bgx->is_dlm)
1035 sprintf(str, "BGX%d QLM mode", bgx->bgx_id);
1036 else
1037 sprintf(str, "BGX%d LMAC%d mode", bgx->bgx_id, lmacid);
1038
1039 switch (lmac->lmac_type) {
1040 case BGX_MODE_SGMII:
1041 dev_info(dev, "%s: SGMII\n", (char *)str);
1042 break;
1043 case BGX_MODE_XAUI:
1044 dev_info(dev, "%s: XAUI\n", (char *)str);
1045 break;
1046 case BGX_MODE_RXAUI:
1047 dev_info(dev, "%s: RXAUI\n", (char *)str);
1048 break;
1049 case BGX_MODE_XFI:
1050 if (!lmac->use_training)
1051 dev_info(dev, "%s: XFI\n", (char *)str);
1052 else
1053 dev_info(dev, "%s: 10G_KR\n", (char *)str);
1054 break;
1055 case BGX_MODE_XLAUI:
1056 if (!lmac->use_training)
1057 dev_info(dev, "%s: XLAUI\n", (char *)str);
1058 else
1059 dev_info(dev, "%s: 40G_KR4\n", (char *)str);
1060 break;
1061 case BGX_MODE_QSGMII:
1062 dev_info(dev, "%s: QSGMII\n", (char *)str);
1063 break;
1064 case BGX_MODE_RGMII:
1065 dev_info(dev, "%s: RGMII\n", (char *)str);
1066 break;
1067 case BGX_MODE_INVALID:
1068 /* Nothing to do */
1069 break;
1070 }
1071 }
1072
1073 static void lmac_set_lane2sds(struct bgx *bgx, struct lmac *lmac)
1074 {
1075 switch (lmac->lmac_type) {
1076 case BGX_MODE_SGMII:
1077 case BGX_MODE_XFI:
1078 lmac->lane_to_sds = lmac->lmacid;
1079 break;
1080 case BGX_MODE_XAUI:
1081 case BGX_MODE_XLAUI:
1082 case BGX_MODE_RGMII:
1083 lmac->lane_to_sds = 0xE4;
1084 break;
1085 case BGX_MODE_RXAUI:
1086 lmac->lane_to_sds = (lmac->lmacid) ? 0xE : 0x4;
1087 break;
1088 case BGX_MODE_QSGMII:
1089 /* There is no way to determine if DLM0/2 is QSGMII or
1090 * DLM1/3 is configured to QSGMII as bootloader will
1091 * configure all LMACs, so take whatever is configured
1092 * by low level firmware.
1093 */
1094 lmac->lane_to_sds = bgx_get_lane2sds_cfg(bgx, lmac);
1095 break;
1096 default:
1097 lmac->lane_to_sds = 0;
1098 break;
1099 }
1100 }
1101
1102 static void lmac_set_training(struct bgx *bgx, struct lmac *lmac, int lmacid)
1103 {
1104 if ((lmac->lmac_type != BGX_MODE_10G_KR) &&
1105 (lmac->lmac_type != BGX_MODE_40G_KR)) {
1106 lmac->use_training = 0;
1107 return;
1108 }
1109
1110 lmac->use_training = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL) &
1111 SPU_PMD_CRTL_TRAIN_EN;
1112 }
1113
1114 static void bgx_set_lmac_config(struct bgx *bgx, u8 idx)
1115 {
1116 struct lmac *lmac;
1117 u64 cmr_cfg;
1118 u8 lmac_type;
1119 u8 lane_to_sds;
1120
1121 lmac = &bgx->lmac[idx];
1122
1123 if (!bgx->is_dlm || bgx->is_rgx) {
1124 /* Read LMAC0 type to figure out QLM mode
1125 * This is configured by low level firmware
1126 */
1127 cmr_cfg = bgx_reg_read(bgx, 0, BGX_CMRX_CFG);
1128 lmac->lmac_type = (cmr_cfg >> 8) & 0x07;
1129 if (bgx->is_rgx)
1130 lmac->lmac_type = BGX_MODE_RGMII;
1131 lmac_set_training(bgx, lmac, 0);
1132 lmac_set_lane2sds(bgx, lmac);
1133 return;
1134 }
1135
1136 /* For DLMs or SLMs on 80/81/83xx so many lane configurations
1137 * are possible and vary across boards. Also Kernel doesn't have
1138 * any way to identify board type/info and since firmware does,
1139 * just take lmac type and serdes lane config as is.
1140 */
1141 cmr_cfg = bgx_reg_read(bgx, idx, BGX_CMRX_CFG);
1142 lmac_type = (u8)((cmr_cfg >> 8) & 0x07);
1143 lane_to_sds = (u8)(cmr_cfg & 0xFF);
1144 /* Check if config is reset value */
1145 if ((lmac_type == 0) && (lane_to_sds == 0xE4))
1146 lmac->lmac_type = BGX_MODE_INVALID;
1147 else
1148 lmac->lmac_type = lmac_type;
1149 lmac->lane_to_sds = lane_to_sds;
1150 lmac_set_training(bgx, lmac, lmac->lmacid);
1151 }
1152
1153 static void bgx_get_qlm_mode(struct bgx *bgx)
1154 {
1155 struct lmac *lmac;
1156 u8 idx;
1157
1158 /* Init all LMAC's type to invalid */
1159 for (idx = 0; idx < bgx->max_lmac; idx++) {
1160 lmac = &bgx->lmac[idx];
1161 lmac->lmacid = idx;
1162 lmac->lmac_type = BGX_MODE_INVALID;
1163 lmac->use_training = false;
1164 }
1165
1166 /* It is assumed that low level firmware sets this value */
1167 bgx->lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7;
1168 if (bgx->lmac_count > bgx->max_lmac)
1169 bgx->lmac_count = bgx->max_lmac;
1170
1171 for (idx = 0; idx < bgx->lmac_count; idx++) {
1172 bgx_set_lmac_config(bgx, idx);
1173 bgx_print_qlm_mode(bgx, idx);
1174 }
1175 }
1176
1177 #ifdef CONFIG_ACPI
1178
1179 static int acpi_get_mac_address(struct device *dev, struct acpi_device *adev,
1180 u8 *dst)
1181 {
1182 u8 mac[ETH_ALEN];
1183 int ret;
1184
1185 ret = fwnode_property_read_u8_array(acpi_fwnode_handle(adev),
1186 "mac-address", mac, ETH_ALEN);
1187 if (ret)
1188 goto out;
1189
1190 if (!is_valid_ether_addr(mac)) {
1191 dev_err(dev, "MAC address invalid: %pM\n", mac);
1192 ret = -EINVAL;
1193 goto out;
1194 }
1195
1196 dev_info(dev, "MAC address set to: %pM\n", mac);
1197
1198 memcpy(dst, mac, ETH_ALEN);
1199 out:
1200 return ret;
1201 }
1202
1203 /* Currently only sets the MAC address. */
1204 static acpi_status bgx_acpi_register_phy(acpi_handle handle,
1205 u32 lvl, void *context, void **rv)
1206 {
1207 struct bgx *bgx = context;
1208 struct device *dev = &bgx->pdev->dev;
1209 struct acpi_device *adev;
1210
1211 if (acpi_bus_get_device(handle, &adev))
1212 goto out;
1213
1214 acpi_get_mac_address(dev, adev, bgx->lmac[bgx->acpi_lmac_idx].mac);
1215
1216 SET_NETDEV_DEV(&bgx->lmac[bgx->acpi_lmac_idx].netdev, dev);
1217
1218 bgx->lmac[bgx->acpi_lmac_idx].lmacid = bgx->acpi_lmac_idx;
1219 bgx->acpi_lmac_idx++; /* move to next LMAC */
1220 out:
1221 return AE_OK;
1222 }
1223
1224 static acpi_status bgx_acpi_match_id(acpi_handle handle, u32 lvl,
1225 void *context, void **ret_val)
1226 {
1227 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1228 struct bgx *bgx = context;
1229 char bgx_sel[5];
1230
1231 snprintf(bgx_sel, 5, "BGX%d", bgx->bgx_id);
1232 if (ACPI_FAILURE(acpi_get_name(handle, ACPI_SINGLE_NAME, &string))) {
1233 pr_warn("Invalid link device\n");
1234 return AE_OK;
1235 }
1236
1237 if (strncmp(string.pointer, bgx_sel, 4))
1238 return AE_OK;
1239
1240 acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
1241 bgx_acpi_register_phy, NULL, bgx, NULL);
1242
1243 kfree(string.pointer);
1244 return AE_CTRL_TERMINATE;
1245 }
1246
1247 static int bgx_init_acpi_phy(struct bgx *bgx)
1248 {
1249 acpi_get_devices(NULL, bgx_acpi_match_id, bgx, (void **)NULL);
1250 return 0;
1251 }
1252
1253 #else
1254
1255 static int bgx_init_acpi_phy(struct bgx *bgx)
1256 {
1257 return -ENODEV;
1258 }
1259
1260 #endif /* CONFIG_ACPI */
1261
1262 #if IS_ENABLED(CONFIG_OF_MDIO)
1263
1264 static int bgx_init_of_phy(struct bgx *bgx)
1265 {
1266 struct fwnode_handle *fwn;
1267 struct device_node *node = NULL;
1268 u8 lmac = 0;
1269
1270 device_for_each_child_node(&bgx->pdev->dev, fwn) {
1271 struct phy_device *pd;
1272 struct device_node *phy_np;
1273 const char *mac;
1274
1275 /* Should always be an OF node. But if it is not, we
1276 * cannot handle it, so exit the loop.
1277 */
1278 node = to_of_node(fwn);
1279 if (!node)
1280 break;
1281
1282 mac = of_get_mac_address(node);
1283 if (mac)
1284 ether_addr_copy(bgx->lmac[lmac].mac, mac);
1285
1286 SET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev);
1287 bgx->lmac[lmac].lmacid = lmac;
1288
1289 phy_np = of_parse_phandle(node, "phy-handle", 0);
1290 /* If there is no phy or defective firmware presents
1291 * this cortina phy, for which there is no driver
1292 * support, ignore it.
1293 */
1294 if (phy_np &&
1295 !of_device_is_compatible(phy_np, "cortina,cs4223-slice")) {
1296 /* Wait until the phy drivers are available */
1297 pd = of_phy_find_device(phy_np);
1298 if (!pd)
1299 goto defer;
1300 bgx->lmac[lmac].phydev = pd;
1301 }
1302
1303 lmac++;
1304 if (lmac == bgx->max_lmac) {
1305 of_node_put(node);
1306 break;
1307 }
1308 }
1309 return 0;
1310
1311 defer:
1312 /* We are bailing out, try not to leak device reference counts
1313 * for phy devices we may have already found.
1314 */
1315 while (lmac) {
1316 if (bgx->lmac[lmac].phydev) {
1317 put_device(&bgx->lmac[lmac].phydev->mdio.dev);
1318 bgx->lmac[lmac].phydev = NULL;
1319 }
1320 lmac--;
1321 }
1322 of_node_put(node);
1323 return -EPROBE_DEFER;
1324 }
1325
1326 #else
1327
1328 static int bgx_init_of_phy(struct bgx *bgx)
1329 {
1330 return -ENODEV;
1331 }
1332
1333 #endif /* CONFIG_OF_MDIO */
1334
1335 static int bgx_init_phy(struct bgx *bgx)
1336 {
1337 if (!acpi_disabled)
1338 return bgx_init_acpi_phy(bgx);
1339
1340 return bgx_init_of_phy(bgx);
1341 }
1342
1343 static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1344 {
1345 int err;
1346 struct device *dev = &pdev->dev;
1347 struct bgx *bgx = NULL;
1348 u8 lmac;
1349 u16 sdevid;
1350
1351 bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL);
1352 if (!bgx)
1353 return -ENOMEM;
1354 bgx->pdev = pdev;
1355
1356 pci_set_drvdata(pdev, bgx);
1357
1358 err = pci_enable_device(pdev);
1359 if (err) {
1360 dev_err(dev, "Failed to enable PCI device\n");
1361 pci_set_drvdata(pdev, NULL);
1362 return err;
1363 }
1364
1365 err = pci_request_regions(pdev, DRV_NAME);
1366 if (err) {
1367 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1368 goto err_disable_device;
1369 }
1370
1371 /* MAP configuration registers */
1372 bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1373 if (!bgx->reg_base) {
1374 dev_err(dev, "BGX: Cannot map CSR memory space, aborting\n");
1375 err = -ENOMEM;
1376 goto err_release_regions;
1377 }
1378
1379 set_max_bgx_per_node(pdev);
1380
1381 pci_read_config_word(pdev, PCI_DEVICE_ID, &sdevid);
1382 if (sdevid != PCI_DEVICE_ID_THUNDER_RGX) {
1383 bgx->bgx_id = (pci_resource_start(pdev,
1384 PCI_CFG_REG_BAR_NUM) >> 24) & BGX_ID_MASK;
1385 bgx->bgx_id += nic_get_node_id(pdev) * max_bgx_per_node;
1386 bgx->max_lmac = MAX_LMAC_PER_BGX;
1387 bgx_vnic[bgx->bgx_id] = bgx;
1388 } else {
1389 bgx->is_rgx = true;
1390 bgx->max_lmac = 1;
1391 bgx->bgx_id = MAX_BGX_PER_CN81XX - 1;
1392 bgx_vnic[bgx->bgx_id] = bgx;
1393 xcv_init_hw();
1394 }
1395
1396 /* On 81xx all are DLMs and on 83xx there are 3 BGX QLMs and one
1397 * BGX i.e BGX2 can be split across 2 DLMs.
1398 */
1399 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid);
1400 if ((sdevid == PCI_SUBSYS_DEVID_81XX_BGX) ||
1401 ((sdevid == PCI_SUBSYS_DEVID_83XX_BGX) && (bgx->bgx_id == 2)))
1402 bgx->is_dlm = true;
1403
1404 bgx_get_qlm_mode(bgx);
1405
1406 err = bgx_init_phy(bgx);
1407 if (err)
1408 goto err_enable;
1409
1410 bgx_init_hw(bgx);
1411
1412 /* Enable all LMACs */
1413 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
1414 err = bgx_lmac_enable(bgx, lmac);
1415 if (err) {
1416 dev_err(dev, "BGX%d failed to enable lmac%d\n",
1417 bgx->bgx_id, lmac);
1418 while (lmac)
1419 bgx_lmac_disable(bgx, --lmac);
1420 goto err_enable;
1421 }
1422 }
1423
1424 return 0;
1425
1426 err_enable:
1427 bgx_vnic[bgx->bgx_id] = NULL;
1428 err_release_regions:
1429 pci_release_regions(pdev);
1430 err_disable_device:
1431 pci_disable_device(pdev);
1432 pci_set_drvdata(pdev, NULL);
1433 return err;
1434 }
1435
1436 static void bgx_remove(struct pci_dev *pdev)
1437 {
1438 struct bgx *bgx = pci_get_drvdata(pdev);
1439 u8 lmac;
1440
1441 /* Disable all LMACs */
1442 for (lmac = 0; lmac < bgx->lmac_count; lmac++)
1443 bgx_lmac_disable(bgx, lmac);
1444
1445 bgx_vnic[bgx->bgx_id] = NULL;
1446 pci_release_regions(pdev);
1447 pci_disable_device(pdev);
1448 pci_set_drvdata(pdev, NULL);
1449 }
1450
1451 static struct pci_driver bgx_driver = {
1452 .name = DRV_NAME,
1453 .id_table = bgx_id_table,
1454 .probe = bgx_probe,
1455 .remove = bgx_remove,
1456 };
1457
1458 static int __init bgx_init_module(void)
1459 {
1460 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1461
1462 return pci_register_driver(&bgx_driver);
1463 }
1464
1465 static void __exit bgx_cleanup_module(void)
1466 {
1467 pci_unregister_driver(&bgx_driver);
1468 }
1469
1470 module_init(bgx_init_module);
1471 module_exit(bgx_cleanup_module);
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