2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/bitops.h>
41 #include <linux/cache.h>
42 #include <linux/interrupt.h>
43 #include <linux/list.h>
44 #include <linux/netdevice.h>
45 #include <linux/pci.h>
46 #include <linux/spinlock.h>
47 #include <linux/timer.h>
48 #include <linux/vmalloc.h>
49 #include <linux/etherdevice.h>
50 #include <linux/net_tstamp.h>
52 #include "t4_chip_type.h"
53 #include "cxgb4_uld.h"
55 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
56 extern struct list_head adapter_list
;
57 extern struct mutex uld_mutex
;
60 MAX_NPORTS
= 4, /* max # of ports */
61 SERNUM_LEN
= 24, /* Serial # length */
62 EC_LEN
= 16, /* E/C length */
63 ID_LEN
= 16, /* ID length */
64 PN_LEN
= 16, /* Part Number length */
65 MACADDR_LEN
= 12, /* MAC Address length */
69 T4_REGMAP_SIZE
= (160 * 1024),
70 T5_REGMAP_SIZE
= (332 * 1024),
82 MEMWIN0_APERTURE
= 2048,
83 MEMWIN0_BASE
= 0x1b800,
84 MEMWIN1_APERTURE
= 32768,
85 MEMWIN1_BASE
= 0x28000,
86 MEMWIN1_BASE_T5
= 0x52000,
87 MEMWIN2_APERTURE
= 65536,
88 MEMWIN2_BASE
= 0x30000,
89 MEMWIN2_APERTURE_T5
= 131072,
90 MEMWIN2_BASE_T5
= 0x60000,
108 PAUSE_AUTONEG
= 1 << 2
112 u64 tx_octets
; /* total # of octets in good frames */
113 u64 tx_frames
; /* all good frames */
114 u64 tx_bcast_frames
; /* all broadcast frames */
115 u64 tx_mcast_frames
; /* all multicast frames */
116 u64 tx_ucast_frames
; /* all unicast frames */
117 u64 tx_error_frames
; /* all error frames */
119 u64 tx_frames_64
; /* # of Tx frames in a particular range */
120 u64 tx_frames_65_127
;
121 u64 tx_frames_128_255
;
122 u64 tx_frames_256_511
;
123 u64 tx_frames_512_1023
;
124 u64 tx_frames_1024_1518
;
125 u64 tx_frames_1519_max
;
127 u64 tx_drop
; /* # of dropped Tx frames */
128 u64 tx_pause
; /* # of transmitted pause frames */
129 u64 tx_ppp0
; /* # of transmitted PPP prio 0 frames */
130 u64 tx_ppp1
; /* # of transmitted PPP prio 1 frames */
131 u64 tx_ppp2
; /* # of transmitted PPP prio 2 frames */
132 u64 tx_ppp3
; /* # of transmitted PPP prio 3 frames */
133 u64 tx_ppp4
; /* # of transmitted PPP prio 4 frames */
134 u64 tx_ppp5
; /* # of transmitted PPP prio 5 frames */
135 u64 tx_ppp6
; /* # of transmitted PPP prio 6 frames */
136 u64 tx_ppp7
; /* # of transmitted PPP prio 7 frames */
138 u64 rx_octets
; /* total # of octets in good frames */
139 u64 rx_frames
; /* all good frames */
140 u64 rx_bcast_frames
; /* all broadcast frames */
141 u64 rx_mcast_frames
; /* all multicast frames */
142 u64 rx_ucast_frames
; /* all unicast frames */
143 u64 rx_too_long
; /* # of frames exceeding MTU */
144 u64 rx_jabber
; /* # of jabber frames */
145 u64 rx_fcs_err
; /* # of received frames with bad FCS */
146 u64 rx_len_err
; /* # of received frames with length error */
147 u64 rx_symbol_err
; /* symbol errors */
148 u64 rx_runt
; /* # of short frames */
150 u64 rx_frames_64
; /* # of Rx frames in a particular range */
151 u64 rx_frames_65_127
;
152 u64 rx_frames_128_255
;
153 u64 rx_frames_256_511
;
154 u64 rx_frames_512_1023
;
155 u64 rx_frames_1024_1518
;
156 u64 rx_frames_1519_max
;
158 u64 rx_pause
; /* # of received pause frames */
159 u64 rx_ppp0
; /* # of received PPP prio 0 frames */
160 u64 rx_ppp1
; /* # of received PPP prio 1 frames */
161 u64 rx_ppp2
; /* # of received PPP prio 2 frames */
162 u64 rx_ppp3
; /* # of received PPP prio 3 frames */
163 u64 rx_ppp4
; /* # of received PPP prio 4 frames */
164 u64 rx_ppp5
; /* # of received PPP prio 5 frames */
165 u64 rx_ppp6
; /* # of received PPP prio 6 frames */
166 u64 rx_ppp7
; /* # of received PPP prio 7 frames */
168 u64 rx_ovflow0
; /* drops due to buffer-group 0 overflows */
169 u64 rx_ovflow1
; /* drops due to buffer-group 1 overflows */
170 u64 rx_ovflow2
; /* drops due to buffer-group 2 overflows */
171 u64 rx_ovflow3
; /* drops due to buffer-group 3 overflows */
172 u64 rx_trunc0
; /* buffer-group 0 truncated packets */
173 u64 rx_trunc1
; /* buffer-group 1 truncated packets */
174 u64 rx_trunc2
; /* buffer-group 2 truncated packets */
175 u64 rx_trunc3
; /* buffer-group 3 truncated packets */
178 struct lb_port_stats
{
191 u64 frames_1024_1518
;
206 struct tp_tcp_stats
{
210 u64 tcp_retrans_segs
;
213 struct tp_usm_stats
{
219 struct tp_fcoe_stats
{
225 struct tp_err_stats
{
229 u32 tnl_cong_drops
[4];
230 u32 ofld_chan_drops
[4];
232 u32 ofld_vlan_drops
[4];
238 struct tp_cpl_stats
{
243 struct tp_rdma_stats
{
249 u32 hps
; /* host page size for our PF/VF */
250 u32 eq_qpp
; /* egress queues/page for our PF/VF */
251 u32 iq_qpp
; /* egress queues/page for our PF/VF */
255 unsigned int tre
; /* log2 of core clocks per TP tick */
256 unsigned int la_mask
; /* what events are recorded by TP LA */
257 unsigned short tx_modq_map
; /* TX modulation scheduler queue to */
260 uint32_t dack_re
; /* DACK timer resolution */
261 unsigned short tx_modq
[NCHAN
]; /* channel to modulation queue map */
263 u32 vlan_pri_map
; /* cached TP_VLAN_PRI_MAP */
264 u32 ingress_config
; /* cached TP_INGRESS_CONFIG */
266 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
267 * subset of the set of fields which may be present in the Compressed
268 * Filter Tuple portion of filters and TCP TCB connections. The
269 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
270 * Since a variable number of fields may or may not be present, their
271 * shifted field positions within the Compressed Filter Tuple may
272 * vary, or not even be present if the field isn't selected in
273 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
274 * places we store their offsets here, or a -1 if the field isn't
286 u8 sn
[SERNUM_LEN
+ 1];
289 u8 na
[MACADDR_LEN
+ 1];
297 struct devlog_params
{
298 u32 memtype
; /* which memory (EDC0, EDC1, MC) */
299 u32 start
; /* start of log in firmware memory */
300 u32 size
; /* size of log */
303 /* Stores chip specific parameters */
304 struct arch_specific_params
{
307 u8 cng_ch_bits_log
; /* congestion channel map bits width */
314 struct adapter_params
{
315 struct sge_params sge
;
317 struct vpd_params vpd
;
318 struct pci_params pci
;
319 struct devlog_params devlog
;
320 enum pcie_memwin drv_memwin
;
322 unsigned int cim_la_size
;
324 unsigned int sf_size
; /* serial flash size in bytes */
325 unsigned int sf_nsec
; /* # of flash sectors */
326 unsigned int sf_fw_start
; /* start of FW image in flash */
328 unsigned int fw_vers
;
329 unsigned int bs_vers
; /* bootstrap version */
330 unsigned int tp_vers
;
331 unsigned int er_vers
; /* expansion ROM version */
334 unsigned short mtus
[NMTUS
];
335 unsigned short a_wnd
[NCCTRL_WIN
];
336 unsigned short b_wnd
[NCCTRL_WIN
];
338 unsigned char nports
; /* # of ethernet ports */
339 unsigned char portvec
;
340 enum chip_type chip
; /* chip code */
341 struct arch_specific_params arch
; /* chip specific params */
342 unsigned char offload
;
343 unsigned char crypto
; /* HW capability for crypto */
345 unsigned char bypass
;
347 unsigned int ofldq_wr_cred
;
348 bool ulptx_memwrite_dsgl
; /* use of T5 DSGL allowed */
350 unsigned int nsched_cls
; /* number of traffic classes */
351 unsigned int max_ordird_qp
; /* Max read depth per RDMA QP */
352 unsigned int max_ird_adapter
; /* Max read depth per adapter */
355 /* State needed to monitor the forward progress of SGE Ingress DMA activities
356 * and possible hangs.
358 struct sge_idma_monitor_state
{
359 unsigned int idma_1s_thresh
; /* 1s threshold in Core Clock ticks */
360 unsigned int idma_stalled
[2]; /* synthesized stalled timers in HZ */
361 unsigned int idma_state
[2]; /* IDMA Hang detect state */
362 unsigned int idma_qid
[2]; /* IDMA Hung Ingress Queue ID */
363 unsigned int idma_warn
[2]; /* time to warning in HZ */
366 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format.
367 * The access and execute times are signed in order to accommodate negative
371 u64 cmd
[MBOX_LEN
/ 8]; /* a Firmware Mailbox Command/Reply */
372 u64 timestamp
; /* OS-dependent timestamp */
373 u32 seqno
; /* sequence number */
374 s16 access
; /* time (ms) to access mailbox */
375 s16 execute
; /* time (ms) to execute */
378 struct mbox_cmd_log
{
379 unsigned int size
; /* number of entries in the log */
380 unsigned int cursor
; /* next position in the log to write */
381 u32 seqno
; /* next sequence number */
382 /* variable length mailbox command log starts here */
385 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index,
386 * return a pointer to the specified entry.
388 static inline struct mbox_cmd
*mbox_cmd_log_entry(struct mbox_cmd_log
*log
,
389 unsigned int entry_idx
)
391 return &((struct mbox_cmd
*)&(log
)[1])[entry_idx
];
394 #include "t4fw_api.h"
396 #define FW_VERSION(chip) ( \
397 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
398 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
399 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
400 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
401 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
407 struct fw_hdr fw_hdr
;
410 struct trace_params
{
411 u32 data
[TRACE_LEN
/ 4];
412 u32 mask
[TRACE_LEN
/ 4];
413 unsigned short snap_len
;
414 unsigned short min_len
;
415 unsigned char skip_ofst
;
416 unsigned char skip_len
;
417 unsigned char invert
;
422 unsigned short supported
; /* link capabilities */
423 unsigned short advertising
; /* advertised capabilities */
424 unsigned short lp_advertising
; /* peer advertised capabilities */
425 unsigned int requested_speed
; /* speed user has requested */
426 unsigned int speed
; /* actual link speed */
427 unsigned char requested_fc
; /* flow control user has requested */
428 unsigned char fc
; /* actual link flow control */
429 unsigned char autoneg
; /* autonegotiating? */
430 unsigned char link_ok
; /* link up? */
431 unsigned char link_down_rc
; /* link down reason */
434 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
437 MAX_ETH_QSETS
= 32, /* # of Ethernet Tx/Rx queue sets */
438 MAX_OFLD_QSETS
= 16, /* # of offload Tx, iscsi Rx queue sets */
439 MAX_CTRL_QUEUES
= NCHAN
, /* # of control Tx queues */
443 MAX_TXQ_ENTRIES
= 16384,
444 MAX_CTRL_TXQ_ENTRIES
= 1024,
445 MAX_RSPQ_ENTRIES
= 16384,
446 MAX_RX_BUFFERS
= 16384,
447 MIN_TXQ_ENTRIES
= 32,
448 MIN_CTRL_TXQ_ENTRIES
= 32,
449 MIN_RSPQ_ENTRIES
= 128,
454 INGQ_EXTRAS
= 2, /* firmware event queue and */
455 /* forwarded interrupts */
456 MAX_INGQ
= MAX_ETH_QSETS
+ INGQ_EXTRAS
,
462 #include "cxgb4_dcb.h"
464 #ifdef CONFIG_CHELSIO_T4_FCOE
465 #include "cxgb4_fcoe.h"
466 #endif /* CONFIG_CHELSIO_T4_FCOE */
469 struct adapter
*adapter
;
471 s16 xact_addr_filt
; /* index of exact MAC address filter */
472 u16 rss_size
; /* size of VI's RSS table slice */
474 enum fw_port_type port_type
;
478 u8 lport
; /* associated offload logical port */
479 u8 nqsets
; /* # of qsets */
480 u8 first_qset
; /* index of first qset */
482 struct link_config link_cfg
;
484 struct port_stats stats_base
;
485 #ifdef CONFIG_CHELSIO_T4_DCB
486 struct port_dcb_info dcb
; /* Data Center Bridging support */
488 #ifdef CONFIG_CHELSIO_T4_FCOE
489 struct cxgb_fcoe fcoe
;
490 #endif /* CONFIG_CHELSIO_T4_FCOE */
491 bool rxtstamp
; /* Enable TS */
492 struct hwtstamp_config tstamp_config
;
493 struct sched_table
*sched_tbl
;
499 enum { /* adapter flags */
500 FULL_INIT_DONE
= (1 << 0),
501 DEV_ENABLED
= (1 << 1),
502 USING_MSI
= (1 << 2),
503 USING_MSIX
= (1 << 3),
505 RSS_TNLALLLOOKUP
= (1 << 5),
506 USING_SOFT_PARAMS
= (1 << 6),
507 MASTER_PF
= (1 << 7),
508 FW_OFLD_CONN
= (1 << 9),
512 ULP_CRYPTO_LOOKASIDE
= 1 << 0,
517 struct sge_fl
{ /* SGE free-buffer queue state */
518 unsigned int avail
; /* # of available Rx buffers */
519 unsigned int pend_cred
; /* new buffers since last FL DB ring */
520 unsigned int cidx
; /* consumer index */
521 unsigned int pidx
; /* producer index */
522 unsigned long alloc_failed
; /* # of times buffer allocation failed */
523 unsigned long large_alloc_failed
;
524 unsigned long mapping_err
; /* # of RX Buffer DMA Mapping failures */
525 unsigned long low
; /* # of times momentarily starving */
526 unsigned long starving
;
528 unsigned int cntxt_id
; /* SGE context id for the free list */
529 unsigned int size
; /* capacity of free list */
530 struct rx_sw_desc
*sdesc
; /* address of SW Rx descriptor ring */
531 __be64
*desc
; /* address of HW Rx descriptor ring */
532 dma_addr_t addr
; /* bus address of HW ring start */
533 void __iomem
*bar2_addr
; /* address of BAR2 Queue registers */
534 unsigned int bar2_qid
; /* Queue ID for BAR2 Queue registers */
537 /* A packet gather list */
539 u64 sgetstamp
; /* SGE Time Stamp for Ingress Packet */
540 struct page_frag frags
[MAX_SKB_FRAGS
];
541 void *va
; /* virtual address of first byte */
542 unsigned int nfrags
; /* # of fragments */
543 unsigned int tot_len
; /* total length of fragments */
546 typedef int (*rspq_handler_t
)(struct sge_rspq
*q
, const __be64
*rsp
,
547 const struct pkt_gl
*gl
);
548 typedef void (*rspq_flush_handler_t
)(struct sge_rspq
*q
);
549 /* LRO related declarations for ULD */
551 #define MAX_LRO_SESSIONS 64
552 u8 lro_session_cnt
; /* # of sessions to aggregate */
553 unsigned long lro_pkts
; /* # of LRO super packets */
554 unsigned long lro_merged
; /* # of wire packets merged by LRO */
555 struct sk_buff_head lroq
; /* list of aggregated sessions */
558 struct sge_rspq
{ /* state for an SGE response queue */
559 struct napi_struct napi
;
560 const __be64
*cur_desc
; /* current descriptor in queue */
561 unsigned int cidx
; /* consumer index */
562 u8 gen
; /* current generation bit */
563 u8 intr_params
; /* interrupt holdoff parameters */
564 u8 next_intr_params
; /* holdoff params for next interrupt */
566 u8 pktcnt_idx
; /* interrupt packet threshold */
567 u8 uld
; /* ULD handling this queue */
568 u8 idx
; /* queue index within its group */
569 int offset
; /* offset into current Rx buffer */
570 u16 cntxt_id
; /* SGE context id for the response q */
571 u16 abs_id
; /* absolute SGE id for the response q */
572 __be64
*desc
; /* address of HW response ring */
573 dma_addr_t phys_addr
; /* physical address of the ring */
574 void __iomem
*bar2_addr
; /* address of BAR2 Queue registers */
575 unsigned int bar2_qid
; /* Queue ID for BAR2 Queue registers */
576 unsigned int iqe_len
; /* entry size */
577 unsigned int size
; /* capacity of response queue */
578 struct adapter
*adap
;
579 struct net_device
*netdev
; /* associated net device */
580 rspq_handler_t handler
;
581 rspq_flush_handler_t flush_handler
;
582 struct t4_lro_mgr lro_mgr
;
583 #ifdef CONFIG_NET_RX_BUSY_POLL
584 #define CXGB_POLL_STATE_IDLE 0
585 #define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */
586 #define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */
587 #define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */
588 #define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */
589 #define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \
590 CXGB_POLL_STATE_POLL_YIELD)
591 #define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \
592 CXGB_POLL_STATE_POLL)
593 #define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \
594 CXGB_POLL_STATE_POLL_YIELD)
595 unsigned int bpoll_state
;
596 spinlock_t bpoll_lock
; /* lock for busy poll */
597 #endif /* CONFIG_NET_RX_BUSY_POLL */
601 struct sge_eth_stats
{ /* Ethernet queue statistics */
602 unsigned long pkts
; /* # of ethernet packets */
603 unsigned long lro_pkts
; /* # of LRO super packets */
604 unsigned long lro_merged
; /* # of wire packets merged by LRO */
605 unsigned long rx_cso
; /* # of Rx checksum offloads */
606 unsigned long vlan_ex
; /* # of Rx VLAN extractions */
607 unsigned long rx_drops
; /* # of packets dropped due to no mem */
610 struct sge_eth_rxq
{ /* SW Ethernet Rx queue */
611 struct sge_rspq rspq
;
613 struct sge_eth_stats stats
;
614 } ____cacheline_aligned_in_smp
;
616 struct sge_ofld_stats
{ /* offload queue statistics */
617 unsigned long pkts
; /* # of packets */
618 unsigned long imm
; /* # of immediate-data packets */
619 unsigned long an
; /* # of asynchronous notifications */
620 unsigned long nomem
; /* # of responses deferred due to no mem */
623 struct sge_ofld_rxq
{ /* SW offload Rx queue */
624 struct sge_rspq rspq
;
626 struct sge_ofld_stats stats
;
627 } ____cacheline_aligned_in_smp
;
636 unsigned int in_use
; /* # of in-use Tx descriptors */
637 unsigned int size
; /* # of descriptors */
638 unsigned int cidx
; /* SW consumer index */
639 unsigned int pidx
; /* producer index */
640 unsigned long stops
; /* # of times q has been stopped */
641 unsigned long restarts
; /* # of queue restarts */
642 unsigned int cntxt_id
; /* SGE context id for the Tx q */
643 struct tx_desc
*desc
; /* address of HW Tx descriptor ring */
644 struct tx_sw_desc
*sdesc
; /* address of SW Tx descriptor ring */
645 struct sge_qstat
*stat
; /* queue status entry */
646 dma_addr_t phys_addr
; /* physical address of the ring */
649 unsigned short db_pidx
;
650 unsigned short db_pidx_inc
;
651 void __iomem
*bar2_addr
; /* address of BAR2 Queue registers */
652 unsigned int bar2_qid
; /* Queue ID for BAR2 Queue registers */
655 struct sge_eth_txq
{ /* state for an SGE Ethernet Tx queue */
657 struct netdev_queue
*txq
; /* associated netdev TX queue */
658 #ifdef CONFIG_CHELSIO_T4_DCB
659 u8 dcb_prio
; /* DCB Priority bound to queue */
661 unsigned long tso
; /* # of TSO requests */
662 unsigned long tx_cso
; /* # of Tx checksum offloads */
663 unsigned long vlan_ins
; /* # of Tx VLAN insertions */
664 unsigned long mapping_err
; /* # of I/O MMU packet mapping errors */
665 } ____cacheline_aligned_in_smp
;
667 struct sge_ofld_txq
{ /* state for an SGE offload Tx queue */
669 struct adapter
*adap
;
670 struct sk_buff_head sendq
; /* list of backpressured packets */
671 struct tasklet_struct qresume_tsk
; /* restarts the queue */
672 bool service_ofldq_running
; /* service_ofldq() is processing sendq */
673 u8 full
; /* the Tx ring is full */
674 unsigned long mapping_err
; /* # of I/O MMU packet mapping errors */
675 } ____cacheline_aligned_in_smp
;
677 struct sge_ctrl_txq
{ /* state for an SGE control Tx queue */
679 struct adapter
*adap
;
680 struct sk_buff_head sendq
; /* list of backpressured packets */
681 struct tasklet_struct qresume_tsk
; /* restarts the queue */
682 u8 full
; /* the Tx ring is full */
683 } ____cacheline_aligned_in_smp
;
685 struct sge_uld_rxq_info
{
686 char name
[IFNAMSIZ
]; /* name of ULD driver */
687 struct sge_ofld_rxq
*uldrxq
; /* Rxq's for ULD */
688 u16
*msix_tbl
; /* msix_tbl for uld */
689 u16
*rspq_id
; /* response queue id's of rxq */
690 u16 nrxq
; /* # of ingress uld queues */
691 u16 nciq
; /* # of completion queues */
692 u8 uld
; /* uld type */
696 struct sge_eth_txq ethtxq
[MAX_ETH_QSETS
];
697 struct sge_ofld_txq ofldtxq
[MAX_OFLD_QSETS
];
698 struct sge_ctrl_txq ctrlq
[MAX_CTRL_QUEUES
];
700 struct sge_eth_rxq ethrxq
[MAX_ETH_QSETS
];
701 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp
;
702 struct sge_uld_rxq_info
**uld_rxq_info
;
704 struct sge_rspq intrq ____cacheline_aligned_in_smp
;
705 spinlock_t intrq_lock
;
707 u16 max_ethqsets
; /* # of available Ethernet queue sets */
708 u16 ethqsets
; /* # of active Ethernet queue sets */
709 u16 ethtxq_rover
; /* Tx queue to clean up next */
710 u16 ofldqsets
; /* # of active ofld queue sets */
711 u16 nqs_per_uld
; /* # of Rx queues per ULD */
712 u16 timer_val
[SGE_NTIMERS
];
713 u8 counter_val
[SGE_NCOUNTERS
];
714 u32 fl_pg_order
; /* large page allocation size */
715 u32 stat_len
; /* length of status page at ring end */
716 u32 pktshift
; /* padding between CPL & packet data */
717 u32 fl_align
; /* response queue message alignment */
718 u32 fl_starve_thres
; /* Free List starvation threshold */
720 struct sge_idma_monitor_state idma_monitor
;
721 unsigned int egr_start
;
723 unsigned int ingr_start
;
724 unsigned int ingr_sz
;
725 void **egr_map
; /* qid->queue egress queue map */
726 struct sge_rspq
**ingr_map
; /* qid->queue ingress queue map */
727 unsigned long *starving_fl
;
728 unsigned long *txq_maperr
;
729 unsigned long *blocked_fl
;
730 struct timer_list rx_timer
; /* refills starving FLs */
731 struct timer_list tx_timer
; /* checks Tx queues */
734 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
735 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
739 #ifdef CONFIG_PCI_IOV
741 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
742 * Configuration initialization for T5 only has SR-IOV functionality enabled
743 * on PF0-3 in order to simplify everything.
745 #define NUM_OF_PF_WITH_SRIOV 4
749 struct doorbell_stats
{
755 struct hash_mac_addr
{
756 struct list_head list
;
760 struct uld_msix_bmap
{
761 unsigned long *msix_bmap
;
762 unsigned int mapsize
;
763 spinlock_t lock
; /* lock for acquiring bitmap */
766 struct uld_msix_info
{
768 char desc
[IFNAMSIZ
+ 10];
773 unsigned char vf_mac_addr
[ETH_ALEN
];
781 struct pci_dev
*pdev
;
782 struct device
*pdev_dev
;
787 unsigned int adap_idx
;
792 struct adapter_params params
;
793 struct cxgb4_virt_res vres
;
798 char desc
[IFNAMSIZ
+ 10];
799 } msix_info
[MAX_INGQ
+ 1];
800 struct uld_msix_info
*msix_info_ulds
; /* msix info for uld's */
801 struct uld_msix_bmap msix_bmap_ulds
; /* msix bitmap for all uld */
804 struct doorbell_stats db_stats
;
807 struct net_device
*port
[MAX_NPORTS
];
808 u8 chan_map
[NCHAN
]; /* channel -> port map */
810 struct vf_info
*vfinfo
;
814 unsigned int l2t_start
;
815 unsigned int l2t_end
;
816 struct l2t_data
*l2t
;
817 unsigned int clipt_start
;
818 unsigned int clipt_end
;
819 struct clip_tbl
*clipt
;
820 struct cxgb4_uld_info
*uld
;
821 void *uld_handle
[CXGB4_ULD_MAX
];
822 unsigned int num_uld
;
823 unsigned int num_ofld_uld
;
824 struct list_head list_node
;
825 struct list_head rcu_node
;
826 struct list_head mac_hlist
; /* list of MAC addresses in MPS Hash */
830 struct tid_info tids
;
831 void **tid_release_head
;
832 spinlock_t tid_release_lock
;
833 struct workqueue_struct
*workq
;
834 struct work_struct tid_release_task
;
835 struct work_struct db_full_task
;
836 struct work_struct db_drop_task
;
837 bool tid_release_task_busy
;
839 /* support for mailbox command/reply logging */
840 #define T4_OS_LOG_MBOX_CMDS 256
841 struct mbox_cmd_log
*mbox_log
;
843 struct mutex uld_mutex
;
845 struct dentry
*debugfs_root
;
846 bool use_bd
; /* Use SGE Back Door intfc for reading SGE Contexts */
847 bool trace_rss
; /* 1 implies that different RSS flit per filter is
848 * used per filter else if 0 default RSS flit is
849 * used for all 4 filters.
852 spinlock_t stats_lock
;
853 spinlock_t win0_lock ____cacheline_aligned_in_smp
;
856 struct cxgb4_tc_u32_table
*tc_u32
;
859 /* Support for "sched-class" command to allow a TX Scheduling Class to be
860 * programmed with various parameters.
862 struct ch_sched_params
{
863 s8 type
; /* packet or flow */
866 s8 level
; /* scheduler hierarchy level */
867 s8 mode
; /* per-class or per-flow */
868 s8 rateunit
; /* bit or packet rate */
869 s8 ratemode
; /* %port relative or kbps absolute */
870 s8 channel
; /* scheduler channel [0..N] */
871 s8
class; /* scheduler class [0..N] */
872 s32 minrate
; /* minimum rate */
873 s32 maxrate
; /* maximum rate */
874 s16 weight
; /* percent weight */
875 s16 pktsize
; /* average packet size */
881 SCHED_CLASS_TYPE_PACKET
= 0, /* class type */
885 SCHED_CLASS_LEVEL_CL_RL
= 0, /* class rate limiter */
889 SCHED_CLASS_MODE_CLASS
= 0, /* per-class scheduling */
893 SCHED_CLASS_RATEUNIT_BITS
= 0, /* bit rate scheduling */
897 SCHED_CLASS_RATEMODE_ABS
= 1, /* Kb/s */
900 /* Support for "sched_queue" command to allow one or more NIC TX Queues
901 * to be bound to a TX Scheduling Class.
903 struct ch_sched_queue
{
904 s8 queue
; /* queue index */
905 s8
class; /* class index */
908 /* Defined bit width of user definable filter tuples
910 #define ETHTYPE_BITWIDTH 16
911 #define FRAG_BITWIDTH 1
912 #define MACIDX_BITWIDTH 9
913 #define FCOE_BITWIDTH 1
914 #define IPORT_BITWIDTH 3
915 #define MATCHTYPE_BITWIDTH 3
916 #define PROTO_BITWIDTH 8
917 #define TOS_BITWIDTH 8
918 #define PF_BITWIDTH 8
919 #define VF_BITWIDTH 8
920 #define IVLAN_BITWIDTH 16
921 #define OVLAN_BITWIDTH 16
923 /* Filter matching rules. These consist of a set of ingress packet field
924 * (value, mask) tuples. The associated ingress packet field matches the
925 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
926 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
927 * matches an ingress packet when all of the individual individual field
928 * matching rules are true.
930 * Partial field masks are always valid, however, while it may be easy to
931 * understand their meanings for some fields (e.g. IP address to match a
932 * subnet), for others making sensible partial masks is less intuitive (e.g.
933 * MPS match type) ...
935 * Most of the following data structures are modeled on T4 capabilities.
936 * Drivers for earlier chips use the subsets which make sense for those chips.
937 * We really need to come up with a hardware-independent mechanism to
938 * represent hardware filter capabilities ...
940 struct ch_filter_tuple
{
941 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
942 * register selects which of these fields will participate in the
943 * filter match rules -- up to a maximum of 36 bits. Because
944 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
947 uint32_t ethtype
:ETHTYPE_BITWIDTH
; /* Ethernet type */
948 uint32_t frag
:FRAG_BITWIDTH
; /* IP fragmentation header */
949 uint32_t ivlan_vld
:1; /* inner VLAN valid */
950 uint32_t ovlan_vld
:1; /* outer VLAN valid */
951 uint32_t pfvf_vld
:1; /* PF/VF valid */
952 uint32_t macidx
:MACIDX_BITWIDTH
; /* exact match MAC index */
953 uint32_t fcoe
:FCOE_BITWIDTH
; /* FCoE packet */
954 uint32_t iport
:IPORT_BITWIDTH
; /* ingress port */
955 uint32_t matchtype
:MATCHTYPE_BITWIDTH
; /* MPS match type */
956 uint32_t proto
:PROTO_BITWIDTH
; /* protocol type */
957 uint32_t tos
:TOS_BITWIDTH
; /* TOS/Traffic Type */
958 uint32_t pf
:PF_BITWIDTH
; /* PCI-E PF ID */
959 uint32_t vf
:VF_BITWIDTH
; /* PCI-E VF ID */
960 uint32_t ivlan
:IVLAN_BITWIDTH
; /* inner VLAN */
961 uint32_t ovlan
:OVLAN_BITWIDTH
; /* outer VLAN */
963 /* Uncompressed header matching field rules. These are always
964 * available for field rules.
966 uint8_t lip
[16]; /* local IP address (IPv4 in [3:0]) */
967 uint8_t fip
[16]; /* foreign IP address (IPv4 in [3:0]) */
968 uint16_t lport
; /* local port */
969 uint16_t fport
; /* foreign port */
972 /* A filter ioctl command.
974 struct ch_filter_specification
{
975 /* Administrative fields for filter.
977 uint32_t hitcnts
:1; /* count filter hits in TCB */
978 uint32_t prio
:1; /* filter has priority over active/server */
980 /* Fundamental filter typing. This is the one element of filter
981 * matching that doesn't exist as a (value, mask) tuple.
983 uint32_t type
:1; /* 0 => IPv4, 1 => IPv6 */
985 /* Packet dispatch information. Ingress packets which match the
986 * filter rules will be dropped, passed to the host or switched back
987 * out as egress packets.
989 uint32_t action
:2; /* drop, pass, switch */
991 uint32_t rpttid
:1; /* report TID in RSS hash field */
993 uint32_t dirsteer
:1; /* 0 => RSS, 1 => steer to iq */
994 uint32_t iq
:10; /* ingress queue */
996 uint32_t maskhash
:1; /* dirsteer=0: store RSS hash in TCB */
997 uint32_t dirsteerhash
:1;/* dirsteer=1: 0 => TCB contains RSS hash */
998 /* 1 => TCB contains IQ ID */
1000 /* Switch proxy/rewrite fields. An ingress packet which matches a
1001 * filter with "switch" set will be looped back out as an egress
1002 * packet -- potentially with some Ethernet header rewriting.
1004 uint32_t eport
:2; /* egress port to switch packet out */
1005 uint32_t newdmac
:1; /* rewrite destination MAC address */
1006 uint32_t newsmac
:1; /* rewrite source MAC address */
1007 uint32_t newvlan
:2; /* rewrite VLAN Tag */
1008 uint8_t dmac
[ETH_ALEN
]; /* new destination MAC address */
1009 uint8_t smac
[ETH_ALEN
]; /* new source MAC address */
1010 uint16_t vlan
; /* VLAN Tag to insert */
1012 /* Filter rule value/mask pairs.
1014 struct ch_filter_tuple val
;
1015 struct ch_filter_tuple mask
;
1019 FILTER_PASS
= 0, /* default */
1025 VLAN_NOCHANGE
= 0, /* default */
1031 /* Host shadow copy of ingress filter entry. This is in host native format
1032 * and doesn't match the ordering or bit order, etc. of the hardware of the
1033 * firmware command. The use of bit-field structure elements is purely to
1034 * remind ourselves of the field size limitations and save memory in the case
1035 * where the filter table is large.
1037 struct filter_entry
{
1038 /* Administrative fields for filter. */
1039 u32 valid
:1; /* filter allocated and valid */
1040 u32 locked
:1; /* filter is administratively locked */
1042 u32 pending
:1; /* filter action is pending firmware reply */
1043 u32 smtidx
:8; /* Source MAC Table index for smac */
1044 struct filter_ctx
*ctx
; /* Caller's completion hook */
1045 struct l2t_entry
*l2t
; /* Layer Two Table entry for dmac */
1046 struct net_device
*dev
; /* Associated net device */
1047 u32 tid
; /* This will store the actual tid */
1049 /* The filter itself. Most of this is a straight copy of information
1050 * provided by the extended ioctl(). Some fields are translated to
1051 * internal forms -- for instance the Ingress Queue ID passed in from
1052 * the ioctl() is translated into the Absolute Ingress Queue ID.
1054 struct ch_filter_specification fs
;
1057 static inline int is_offload(const struct adapter
*adap
)
1059 return adap
->params
.offload
;
1062 static inline int is_pci_uld(const struct adapter
*adap
)
1064 return adap
->params
.crypto
;
1067 static inline int is_uld(const struct adapter
*adap
)
1069 return (adap
->params
.offload
|| adap
->params
.crypto
);
1072 static inline u32
t4_read_reg(struct adapter
*adap
, u32 reg_addr
)
1074 return readl(adap
->regs
+ reg_addr
);
1077 static inline void t4_write_reg(struct adapter
*adap
, u32 reg_addr
, u32 val
)
1079 writel(val
, adap
->regs
+ reg_addr
);
1083 static inline u64
readq(const volatile void __iomem
*addr
)
1085 return readl(addr
) + ((u64
)readl(addr
+ 4) << 32);
1088 static inline void writeq(u64 val
, volatile void __iomem
*addr
)
1091 writel(val
>> 32, addr
+ 4);
1095 static inline u64
t4_read_reg64(struct adapter
*adap
, u32 reg_addr
)
1097 return readq(adap
->regs
+ reg_addr
);
1100 static inline void t4_write_reg64(struct adapter
*adap
, u32 reg_addr
, u64 val
)
1102 writeq(val
, adap
->regs
+ reg_addr
);
1106 * t4_set_hw_addr - store a port's MAC address in SW
1107 * @adapter: the adapter
1108 * @port_idx: the port index
1109 * @hw_addr: the Ethernet address
1111 * Store the Ethernet address of the given port in SW. Called by the common
1112 * code when it retrieves a port's Ethernet address from EEPROM.
1114 static inline void t4_set_hw_addr(struct adapter
*adapter
, int port_idx
,
1117 ether_addr_copy(adapter
->port
[port_idx
]->dev_addr
, hw_addr
);
1118 ether_addr_copy(adapter
->port
[port_idx
]->perm_addr
, hw_addr
);
1122 * netdev2pinfo - return the port_info structure associated with a net_device
1125 * Return the struct port_info associated with a net_device
1127 static inline struct port_info
*netdev2pinfo(const struct net_device
*dev
)
1129 return netdev_priv(dev
);
1133 * adap2pinfo - return the port_info of a port
1134 * @adap: the adapter
1135 * @idx: the port index
1137 * Return the port_info structure for the port of the given index.
1139 static inline struct port_info
*adap2pinfo(struct adapter
*adap
, int idx
)
1141 return netdev_priv(adap
->port
[idx
]);
1145 * netdev2adap - return the adapter structure associated with a net_device
1148 * Return the struct adapter associated with a net_device
1150 static inline struct adapter
*netdev2adap(const struct net_device
*dev
)
1152 return netdev2pinfo(dev
)->adapter
;
1155 #ifdef CONFIG_NET_RX_BUSY_POLL
1156 static inline void cxgb_busy_poll_init_lock(struct sge_rspq
*q
)
1158 spin_lock_init(&q
->bpoll_lock
);
1159 q
->bpoll_state
= CXGB_POLL_STATE_IDLE
;
1162 static inline bool cxgb_poll_lock_napi(struct sge_rspq
*q
)
1166 spin_lock(&q
->bpoll_lock
);
1167 if (q
->bpoll_state
& CXGB_POLL_LOCKED
) {
1168 q
->bpoll_state
|= CXGB_POLL_STATE_NAPI_YIELD
;
1171 q
->bpoll_state
= CXGB_POLL_STATE_NAPI
;
1173 spin_unlock(&q
->bpoll_lock
);
1177 static inline bool cxgb_poll_unlock_napi(struct sge_rspq
*q
)
1181 spin_lock(&q
->bpoll_lock
);
1182 if (q
->bpoll_state
& CXGB_POLL_STATE_POLL_YIELD
)
1184 q
->bpoll_state
= CXGB_POLL_STATE_IDLE
;
1185 spin_unlock(&q
->bpoll_lock
);
1189 static inline bool cxgb_poll_lock_poll(struct sge_rspq
*q
)
1193 spin_lock_bh(&q
->bpoll_lock
);
1194 if (q
->bpoll_state
& CXGB_POLL_LOCKED
) {
1195 q
->bpoll_state
|= CXGB_POLL_STATE_POLL_YIELD
;
1198 q
->bpoll_state
|= CXGB_POLL_STATE_POLL
;
1200 spin_unlock_bh(&q
->bpoll_lock
);
1204 static inline bool cxgb_poll_unlock_poll(struct sge_rspq
*q
)
1208 spin_lock_bh(&q
->bpoll_lock
);
1209 if (q
->bpoll_state
& CXGB_POLL_STATE_POLL_YIELD
)
1211 q
->bpoll_state
= CXGB_POLL_STATE_IDLE
;
1212 spin_unlock_bh(&q
->bpoll_lock
);
1216 static inline bool cxgb_poll_busy_polling(struct sge_rspq
*q
)
1218 return q
->bpoll_state
& CXGB_POLL_USER_PEND
;
1221 static inline void cxgb_busy_poll_init_lock(struct sge_rspq
*q
)
1225 static inline bool cxgb_poll_lock_napi(struct sge_rspq
*q
)
1230 static inline bool cxgb_poll_unlock_napi(struct sge_rspq
*q
)
1235 static inline bool cxgb_poll_lock_poll(struct sge_rspq
*q
)
1240 static inline bool cxgb_poll_unlock_poll(struct sge_rspq
*q
)
1245 static inline bool cxgb_poll_busy_polling(struct sge_rspq
*q
)
1249 #endif /* CONFIG_NET_RX_BUSY_POLL */
1251 /* Return a version number to identify the type of adapter. The scheme is:
1252 * - bits 0..9: chip version
1253 * - bits 10..15: chip revision
1254 * - bits 16..23: register dump version
1256 static inline unsigned int mk_adap_vers(struct adapter
*ap
)
1258 return CHELSIO_CHIP_VERSION(ap
->params
.chip
) |
1259 (CHELSIO_CHIP_RELEASE(ap
->params
.chip
) << 10) | (1 << 16);
1262 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */
1263 static inline unsigned int qtimer_val(const struct adapter
*adap
,
1264 const struct sge_rspq
*q
)
1266 unsigned int idx
= q
->intr_params
>> 1;
1268 return idx
< SGE_NTIMERS
? adap
->sge
.timer_val
[idx
] : 0;
1271 /* driver version & name used for ethtool_drvinfo */
1272 extern char cxgb4_driver_name
[];
1273 extern const char cxgb4_driver_version
[];
1275 void t4_os_portmod_changed(const struct adapter
*adap
, int port_id
);
1276 void t4_os_link_changed(struct adapter
*adap
, int port_id
, int link_stat
);
1278 void *t4_alloc_mem(size_t size
);
1280 void t4_free_sge_resources(struct adapter
*adap
);
1281 void t4_free_ofld_rxqs(struct adapter
*adap
, int n
, struct sge_ofld_rxq
*q
);
1282 irq_handler_t
t4_intr_handler(struct adapter
*adap
);
1283 netdev_tx_t
t4_eth_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
1284 int t4_ethrx_handler(struct sge_rspq
*q
, const __be64
*rsp
,
1285 const struct pkt_gl
*gl
);
1286 int t4_mgmt_tx(struct adapter
*adap
, struct sk_buff
*skb
);
1287 int t4_ofld_send(struct adapter
*adap
, struct sk_buff
*skb
);
1288 int t4_sge_alloc_rxq(struct adapter
*adap
, struct sge_rspq
*iq
, bool fwevtq
,
1289 struct net_device
*dev
, int intr_idx
,
1290 struct sge_fl
*fl
, rspq_handler_t hnd
,
1291 rspq_flush_handler_t flush_handler
, int cong
);
1292 int t4_sge_alloc_eth_txq(struct adapter
*adap
, struct sge_eth_txq
*txq
,
1293 struct net_device
*dev
, struct netdev_queue
*netdevq
,
1295 int t4_sge_alloc_ctrl_txq(struct adapter
*adap
, struct sge_ctrl_txq
*txq
,
1296 struct net_device
*dev
, unsigned int iqid
,
1297 unsigned int cmplqid
);
1298 int t4_sge_mod_ctrl_txq(struct adapter
*adap
, unsigned int eqid
,
1299 unsigned int cmplqid
);
1300 int t4_sge_alloc_ofld_txq(struct adapter
*adap
, struct sge_ofld_txq
*txq
,
1301 struct net_device
*dev
, unsigned int iqid
);
1302 irqreturn_t
t4_sge_intr_msix(int irq
, void *cookie
);
1303 int t4_sge_init(struct adapter
*adap
);
1304 void t4_sge_start(struct adapter
*adap
);
1305 void t4_sge_stop(struct adapter
*adap
);
1306 int cxgb_busy_poll(struct napi_struct
*napi
);
1307 void cxgb4_set_ethtool_ops(struct net_device
*netdev
);
1308 int cxgb4_write_rss(const struct port_info
*pi
, const u16
*queues
);
1309 extern int dbfifo_int_thresh
;
1311 #define for_each_port(adapter, iter) \
1312 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1314 static inline int is_bypass(struct adapter
*adap
)
1316 return adap
->params
.bypass
;
1319 static inline int is_bypass_device(int device
)
1321 /* this should be set based upon device capabilities */
1331 static inline int is_10gbt_device(int device
)
1333 /* this should be set based upon device capabilities */
1344 static inline unsigned int core_ticks_per_usec(const struct adapter
*adap
)
1346 return adap
->params
.vpd
.cclk
/ 1000;
1349 static inline unsigned int us_to_core_ticks(const struct adapter
*adap
,
1352 return (us
* adap
->params
.vpd
.cclk
) / 1000;
1355 static inline unsigned int core_ticks_to_us(const struct adapter
*adapter
,
1358 /* add Core Clock / 2 to round ticks to nearest uS */
1359 return ((ticks
* 1000 + adapter
->params
.vpd
.cclk
/2) /
1360 adapter
->params
.vpd
.cclk
);
1363 void t4_set_reg_field(struct adapter
*adap
, unsigned int addr
, u32 mask
,
1366 int t4_wr_mbox_meat_timeout(struct adapter
*adap
, int mbox
, const void *cmd
,
1367 int size
, void *rpl
, bool sleep_ok
, int timeout
);
1368 int t4_wr_mbox_meat(struct adapter
*adap
, int mbox
, const void *cmd
, int size
,
1369 void *rpl
, bool sleep_ok
);
1371 static inline int t4_wr_mbox_timeout(struct adapter
*adap
, int mbox
,
1372 const void *cmd
, int size
, void *rpl
,
1375 return t4_wr_mbox_meat_timeout(adap
, mbox
, cmd
, size
, rpl
, true,
1379 static inline int t4_wr_mbox(struct adapter
*adap
, int mbox
, const void *cmd
,
1380 int size
, void *rpl
)
1382 return t4_wr_mbox_meat(adap
, mbox
, cmd
, size
, rpl
, true);
1385 static inline int t4_wr_mbox_ns(struct adapter
*adap
, int mbox
, const void *cmd
,
1386 int size
, void *rpl
)
1388 return t4_wr_mbox_meat(adap
, mbox
, cmd
, size
, rpl
, false);
1392 * hash_mac_addr - return the hash value of a MAC address
1393 * @addr: the 48-bit Ethernet MAC address
1395 * Hashes a MAC address according to the hash function used by HW inexact
1396 * (hash) address matching.
1398 static inline int hash_mac_addr(const u8
*addr
)
1400 u32 a
= ((u32
)addr
[0] << 16) | ((u32
)addr
[1] << 8) | addr
[2];
1401 u32 b
= ((u32
)addr
[3] << 16) | ((u32
)addr
[4] << 8) | addr
[5];
1409 int cxgb4_set_rspq_intr_params(struct sge_rspq
*q
, unsigned int us
,
1411 static inline void init_rspq(struct adapter
*adap
, struct sge_rspq
*q
,
1412 unsigned int us
, unsigned int cnt
,
1413 unsigned int size
, unsigned int iqe_size
)
1416 cxgb4_set_rspq_intr_params(q
, us
, cnt
);
1417 q
->iqe_len
= iqe_size
;
1421 void t4_write_indirect(struct adapter
*adap
, unsigned int addr_reg
,
1422 unsigned int data_reg
, const u32
*vals
,
1423 unsigned int nregs
, unsigned int start_idx
);
1424 void t4_read_indirect(struct adapter
*adap
, unsigned int addr_reg
,
1425 unsigned int data_reg
, u32
*vals
, unsigned int nregs
,
1426 unsigned int start_idx
);
1427 void t4_hw_pci_read_cfg4(struct adapter
*adapter
, int reg
, u32
*val
);
1429 struct fw_filter_wr
;
1431 void t4_intr_enable(struct adapter
*adapter
);
1432 void t4_intr_disable(struct adapter
*adapter
);
1433 int t4_slow_intr_handler(struct adapter
*adapter
);
1435 int t4_wait_dev_ready(void __iomem
*regs
);
1436 int t4_link_l1cfg(struct adapter
*adap
, unsigned int mbox
, unsigned int port
,
1437 struct link_config
*lc
);
1438 int t4_restart_aneg(struct adapter
*adap
, unsigned int mbox
, unsigned int port
);
1440 u32
t4_read_pcie_cfg4(struct adapter
*adap
, int reg
);
1441 u32
t4_get_util_window(struct adapter
*adap
);
1442 void t4_setup_memwin(struct adapter
*adap
, u32 memwin_base
, u32 window
);
1444 #define T4_MEMORY_WRITE 0
1445 #define T4_MEMORY_READ 1
1446 int t4_memory_rw(struct adapter
*adap
, int win
, int mtype
, u32 addr
, u32 len
,
1447 void *buf
, int dir
);
1448 static inline int t4_memory_write(struct adapter
*adap
, int mtype
, u32 addr
,
1449 u32 len
, __be32
*buf
)
1451 return t4_memory_rw(adap
, 0, mtype
, addr
, len
, buf
, 0);
1454 unsigned int t4_get_regs_len(struct adapter
*adapter
);
1455 void t4_get_regs(struct adapter
*adap
, void *buf
, size_t buf_size
);
1457 int t4_seeprom_wp(struct adapter
*adapter
, bool enable
);
1458 int t4_get_raw_vpd_params(struct adapter
*adapter
, struct vpd_params
*p
);
1459 int t4_get_vpd_params(struct adapter
*adapter
, struct vpd_params
*p
);
1460 int t4_read_flash(struct adapter
*adapter
, unsigned int addr
,
1461 unsigned int nwords
, u32
*data
, int byte_oriented
);
1462 int t4_load_fw(struct adapter
*adapter
, const u8
*fw_data
, unsigned int size
);
1463 int t4_load_phy_fw(struct adapter
*adap
,
1464 int win
, spinlock_t
*lock
,
1465 int (*phy_fw_version
)(const u8
*, size_t),
1466 const u8
*phy_fw_data
, size_t phy_fw_size
);
1467 int t4_phy_fw_ver(struct adapter
*adap
, int *phy_fw_ver
);
1468 int t4_fwcache(struct adapter
*adap
, enum fw_params_param_dev_fwcache op
);
1469 int t4_fw_upgrade(struct adapter
*adap
, unsigned int mbox
,
1470 const u8
*fw_data
, unsigned int size
, int force
);
1471 int t4_fl_pkt_align(struct adapter
*adap
);
1472 unsigned int t4_flash_cfg_addr(struct adapter
*adapter
);
1473 int t4_check_fw_version(struct adapter
*adap
);
1474 int t4_get_fw_version(struct adapter
*adapter
, u32
*vers
);
1475 int t4_get_bs_version(struct adapter
*adapter
, u32
*vers
);
1476 int t4_get_tp_version(struct adapter
*adapter
, u32
*vers
);
1477 int t4_get_exprom_version(struct adapter
*adapter
, u32
*vers
);
1478 int t4_prep_fw(struct adapter
*adap
, struct fw_info
*fw_info
,
1479 const u8
*fw_data
, unsigned int fw_size
,
1480 struct fw_hdr
*card_fw
, enum dev_state state
, int *reset
);
1481 int t4_prep_adapter(struct adapter
*adapter
);
1483 enum t4_bar2_qtype
{ T4_BAR2_QTYPE_EGRESS
, T4_BAR2_QTYPE_INGRESS
};
1484 int t4_bar2_sge_qregs(struct adapter
*adapter
,
1486 enum t4_bar2_qtype qtype
,
1489 unsigned int *pbar2_qid
);
1491 unsigned int qtimer_val(const struct adapter
*adap
,
1492 const struct sge_rspq
*q
);
1494 int t4_init_devlog_params(struct adapter
*adapter
);
1495 int t4_init_sge_params(struct adapter
*adapter
);
1496 int t4_init_tp_params(struct adapter
*adap
);
1497 int t4_filter_field_shift(const struct adapter
*adap
, int filter_sel
);
1498 int t4_init_rss_mode(struct adapter
*adap
, int mbox
);
1499 int t4_init_portinfo(struct port_info
*pi
, int mbox
,
1500 int port
, int pf
, int vf
, u8 mac
[]);
1501 int t4_port_init(struct adapter
*adap
, int mbox
, int pf
, int vf
);
1502 void t4_fatal_err(struct adapter
*adapter
);
1503 int t4_config_rss_range(struct adapter
*adapter
, int mbox
, unsigned int viid
,
1504 int start
, int n
, const u16
*rspq
, unsigned int nrspq
);
1505 int t4_config_glbl_rss(struct adapter
*adapter
, int mbox
, unsigned int mode
,
1506 unsigned int flags
);
1507 int t4_config_vi_rss(struct adapter
*adapter
, int mbox
, unsigned int viid
,
1508 unsigned int flags
, unsigned int defq
);
1509 int t4_read_rss(struct adapter
*adapter
, u16
*entries
);
1510 void t4_read_rss_key(struct adapter
*adapter
, u32
*key
);
1511 void t4_write_rss_key(struct adapter
*adap
, const u32
*key
, int idx
);
1512 void t4_read_rss_pf_config(struct adapter
*adapter
, unsigned int index
,
1514 void t4_read_rss_vf_config(struct adapter
*adapter
, unsigned int index
,
1515 u32
*vfl
, u32
*vfh
);
1516 u32
t4_read_rss_pf_map(struct adapter
*adapter
);
1517 u32
t4_read_rss_pf_mask(struct adapter
*adapter
);
1519 unsigned int t4_get_mps_bg_map(struct adapter
*adapter
, int idx
);
1520 void t4_pmtx_get_stats(struct adapter
*adap
, u32 cnt
[], u64 cycles
[]);
1521 void t4_pmrx_get_stats(struct adapter
*adap
, u32 cnt
[], u64 cycles
[]);
1522 int t4_read_cim_ibq(struct adapter
*adap
, unsigned int qid
, u32
*data
,
1524 int t4_read_cim_obq(struct adapter
*adap
, unsigned int qid
, u32
*data
,
1526 int t4_cim_read(struct adapter
*adap
, unsigned int addr
, unsigned int n
,
1527 unsigned int *valp
);
1528 int t4_cim_write(struct adapter
*adap
, unsigned int addr
, unsigned int n
,
1529 const unsigned int *valp
);
1530 int t4_cim_read_la(struct adapter
*adap
, u32
*la_buf
, unsigned int *wrptr
);
1531 void t4_cim_read_pif_la(struct adapter
*adap
, u32
*pif_req
, u32
*pif_rsp
,
1532 unsigned int *pif_req_wrptr
,
1533 unsigned int *pif_rsp_wrptr
);
1534 void t4_cim_read_ma_la(struct adapter
*adap
, u32
*ma_req
, u32
*ma_rsp
);
1535 void t4_read_cimq_cfg(struct adapter
*adap
, u16
*base
, u16
*size
, u16
*thres
);
1536 const char *t4_get_port_type_description(enum fw_port_type port_type
);
1537 void t4_get_port_stats(struct adapter
*adap
, int idx
, struct port_stats
*p
);
1538 void t4_get_port_stats_offset(struct adapter
*adap
, int idx
,
1539 struct port_stats
*stats
,
1540 struct port_stats
*offset
);
1541 void t4_get_lb_stats(struct adapter
*adap
, int idx
, struct lb_port_stats
*p
);
1542 void t4_read_mtu_tbl(struct adapter
*adap
, u16
*mtus
, u8
*mtu_log
);
1543 void t4_read_cong_tbl(struct adapter
*adap
, u16 incr
[NMTUS
][NCCTRL_WIN
]);
1544 void t4_tp_wr_bits_indirect(struct adapter
*adap
, unsigned int addr
,
1545 unsigned int mask
, unsigned int val
);
1546 void t4_tp_read_la(struct adapter
*adap
, u64
*la_buf
, unsigned int *wrptr
);
1547 void t4_tp_get_err_stats(struct adapter
*adap
, struct tp_err_stats
*st
);
1548 void t4_tp_get_cpl_stats(struct adapter
*adap
, struct tp_cpl_stats
*st
);
1549 void t4_tp_get_rdma_stats(struct adapter
*adap
, struct tp_rdma_stats
*st
);
1550 void t4_get_usm_stats(struct adapter
*adap
, struct tp_usm_stats
*st
);
1551 void t4_tp_get_tcp_stats(struct adapter
*adap
, struct tp_tcp_stats
*v4
,
1552 struct tp_tcp_stats
*v6
);
1553 void t4_get_fcoe_stats(struct adapter
*adap
, unsigned int idx
,
1554 struct tp_fcoe_stats
*st
);
1555 void t4_load_mtus(struct adapter
*adap
, const unsigned short *mtus
,
1556 const unsigned short *alpha
, const unsigned short *beta
);
1558 void t4_ulprx_read_la(struct adapter
*adap
, u32
*la_buf
);
1560 void t4_get_chan_txrate(struct adapter
*adap
, u64
*nic_rate
, u64
*ofld_rate
);
1561 void t4_mk_filtdelwr(unsigned int ftid
, struct fw_filter_wr
*wr
, int qid
);
1563 void t4_wol_magic_enable(struct adapter
*adap
, unsigned int port
,
1565 int t4_wol_pat_enable(struct adapter
*adap
, unsigned int port
, unsigned int map
,
1566 u64 mask0
, u64 mask1
, unsigned int crc
, bool enable
);
1568 int t4_fw_hello(struct adapter
*adap
, unsigned int mbox
, unsigned int evt_mbox
,
1569 enum dev_master master
, enum dev_state
*state
);
1570 int t4_fw_bye(struct adapter
*adap
, unsigned int mbox
);
1571 int t4_early_init(struct adapter
*adap
, unsigned int mbox
);
1572 int t4_fw_reset(struct adapter
*adap
, unsigned int mbox
, int reset
);
1573 int t4_fixup_host_params(struct adapter
*adap
, unsigned int page_size
,
1574 unsigned int cache_line_size
);
1575 int t4_fw_initialize(struct adapter
*adap
, unsigned int mbox
);
1576 int t4_query_params(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1577 unsigned int vf
, unsigned int nparams
, const u32
*params
,
1579 int t4_query_params_rw(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1580 unsigned int vf
, unsigned int nparams
, const u32
*params
,
1582 int t4_set_params_timeout(struct adapter
*adap
, unsigned int mbox
,
1583 unsigned int pf
, unsigned int vf
,
1584 unsigned int nparams
, const u32
*params
,
1585 const u32
*val
, int timeout
);
1586 int t4_set_params(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1587 unsigned int vf
, unsigned int nparams
, const u32
*params
,
1589 int t4_cfg_pfvf(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1590 unsigned int vf
, unsigned int txq
, unsigned int txq_eth_ctrl
,
1591 unsigned int rxqi
, unsigned int rxq
, unsigned int tc
,
1592 unsigned int vi
, unsigned int cmask
, unsigned int pmask
,
1593 unsigned int nexact
, unsigned int rcaps
, unsigned int wxcaps
);
1594 int t4_alloc_vi(struct adapter
*adap
, unsigned int mbox
, unsigned int port
,
1595 unsigned int pf
, unsigned int vf
, unsigned int nmac
, u8
*mac
,
1596 unsigned int *rss_size
);
1597 int t4_free_vi(struct adapter
*adap
, unsigned int mbox
,
1598 unsigned int pf
, unsigned int vf
,
1600 int t4_set_rxmode(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
1601 int mtu
, int promisc
, int all_multi
, int bcast
, int vlanex
,
1603 int t4_alloc_mac_filt(struct adapter
*adap
, unsigned int mbox
,
1604 unsigned int viid
, bool free
, unsigned int naddr
,
1605 const u8
**addr
, u16
*idx
, u64
*hash
, bool sleep_ok
);
1606 int t4_free_mac_filt(struct adapter
*adap
, unsigned int mbox
,
1607 unsigned int viid
, unsigned int naddr
,
1608 const u8
**addr
, bool sleep_ok
);
1609 int t4_change_mac(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
1610 int idx
, const u8
*addr
, bool persist
, bool add_smt
);
1611 int t4_set_addr_hash(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
1612 bool ucast
, u64 vec
, bool sleep_ok
);
1613 int t4_enable_vi_params(struct adapter
*adap
, unsigned int mbox
,
1614 unsigned int viid
, bool rx_en
, bool tx_en
, bool dcb_en
);
1615 int t4_enable_vi(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
1616 bool rx_en
, bool tx_en
);
1617 int t4_identify_port(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
1618 unsigned int nblinks
);
1619 int t4_mdio_rd(struct adapter
*adap
, unsigned int mbox
, unsigned int phy_addr
,
1620 unsigned int mmd
, unsigned int reg
, u16
*valp
);
1621 int t4_mdio_wr(struct adapter
*adap
, unsigned int mbox
, unsigned int phy_addr
,
1622 unsigned int mmd
, unsigned int reg
, u16 val
);
1623 int t4_iq_stop(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1624 unsigned int vf
, unsigned int iqtype
, unsigned int iqid
,
1625 unsigned int fl0id
, unsigned int fl1id
);
1626 int t4_iq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1627 unsigned int vf
, unsigned int iqtype
, unsigned int iqid
,
1628 unsigned int fl0id
, unsigned int fl1id
);
1629 int t4_eth_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1630 unsigned int vf
, unsigned int eqid
);
1631 int t4_ctrl_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1632 unsigned int vf
, unsigned int eqid
);
1633 int t4_ofld_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1634 unsigned int vf
, unsigned int eqid
);
1635 int t4_sge_ctxt_flush(struct adapter
*adap
, unsigned int mbox
);
1636 void t4_handle_get_port_info(struct port_info
*pi
, const __be64
*rpl
);
1637 int t4_handle_fw_rpl(struct adapter
*adap
, const __be64
*rpl
);
1638 void t4_db_full(struct adapter
*adapter
);
1639 void t4_db_dropped(struct adapter
*adapter
);
1640 int t4_set_trace_filter(struct adapter
*adapter
, const struct trace_params
*tp
,
1641 int filter_index
, int enable
);
1642 void t4_get_trace_filter(struct adapter
*adapter
, struct trace_params
*tp
,
1643 int filter_index
, int *enabled
);
1644 int t4_fwaddrspace_write(struct adapter
*adap
, unsigned int mbox
,
1646 int t4_sched_params(struct adapter
*adapter
, int type
, int level
, int mode
,
1647 int rateunit
, int ratemode
, int channel
, int class,
1648 int minrate
, int maxrate
, int weight
, int pktsize
);
1649 void t4_sge_decode_idma_state(struct adapter
*adapter
, int state
);
1650 void t4_free_mem(void *addr
);
1651 void t4_idma_monitor_init(struct adapter
*adapter
,
1652 struct sge_idma_monitor_state
*idma
);
1653 void t4_idma_monitor(struct adapter
*adapter
,
1654 struct sge_idma_monitor_state
*idma
,
1656 int t4_set_vf_mac_acl(struct adapter
*adapter
, unsigned int vf
,
1657 unsigned int naddr
, u8
*addr
);
1658 void t4_uld_mem_free(struct adapter
*adap
);
1659 int t4_uld_mem_alloc(struct adapter
*adap
);
1660 void t4_uld_clean_up(struct adapter
*adap
);
1661 void t4_register_netevent_notifier(void);
1662 void free_rspq_fl(struct adapter
*adap
, struct sge_rspq
*rq
, struct sge_fl
*fl
);
1663 #endif /* __CXGB4_H__ */