2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/bitops.h>
41 #include <linux/cache.h>
42 #include <linux/interrupt.h>
43 #include <linux/list.h>
44 #include <linux/netdevice.h>
45 #include <linux/pci.h>
46 #include <linux/spinlock.h>
47 #include <linux/timer.h>
48 #include <linux/vmalloc.h>
49 #include <linux/etherdevice.h>
50 #include <linux/net_tstamp.h>
52 #include "t4_chip_type.h"
53 #include "cxgb4_uld.h"
55 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
58 MAX_NPORTS
= 4, /* max # of ports */
59 SERNUM_LEN
= 24, /* Serial # length */
60 EC_LEN
= 16, /* E/C length */
61 ID_LEN
= 16, /* ID length */
62 PN_LEN
= 16, /* Part Number length */
63 MACADDR_LEN
= 12, /* MAC Address length */
67 T4_REGMAP_SIZE
= (160 * 1024),
68 T5_REGMAP_SIZE
= (332 * 1024),
80 MEMWIN0_APERTURE
= 2048,
81 MEMWIN0_BASE
= 0x1b800,
82 MEMWIN1_APERTURE
= 32768,
83 MEMWIN1_BASE
= 0x28000,
84 MEMWIN1_BASE_T5
= 0x52000,
85 MEMWIN2_APERTURE
= 65536,
86 MEMWIN2_BASE
= 0x30000,
87 MEMWIN2_APERTURE_T5
= 131072,
88 MEMWIN2_BASE_T5
= 0x60000,
106 PAUSE_AUTONEG
= 1 << 2
110 u64 tx_octets
; /* total # of octets in good frames */
111 u64 tx_frames
; /* all good frames */
112 u64 tx_bcast_frames
; /* all broadcast frames */
113 u64 tx_mcast_frames
; /* all multicast frames */
114 u64 tx_ucast_frames
; /* all unicast frames */
115 u64 tx_error_frames
; /* all error frames */
117 u64 tx_frames_64
; /* # of Tx frames in a particular range */
118 u64 tx_frames_65_127
;
119 u64 tx_frames_128_255
;
120 u64 tx_frames_256_511
;
121 u64 tx_frames_512_1023
;
122 u64 tx_frames_1024_1518
;
123 u64 tx_frames_1519_max
;
125 u64 tx_drop
; /* # of dropped Tx frames */
126 u64 tx_pause
; /* # of transmitted pause frames */
127 u64 tx_ppp0
; /* # of transmitted PPP prio 0 frames */
128 u64 tx_ppp1
; /* # of transmitted PPP prio 1 frames */
129 u64 tx_ppp2
; /* # of transmitted PPP prio 2 frames */
130 u64 tx_ppp3
; /* # of transmitted PPP prio 3 frames */
131 u64 tx_ppp4
; /* # of transmitted PPP prio 4 frames */
132 u64 tx_ppp5
; /* # of transmitted PPP prio 5 frames */
133 u64 tx_ppp6
; /* # of transmitted PPP prio 6 frames */
134 u64 tx_ppp7
; /* # of transmitted PPP prio 7 frames */
136 u64 rx_octets
; /* total # of octets in good frames */
137 u64 rx_frames
; /* all good frames */
138 u64 rx_bcast_frames
; /* all broadcast frames */
139 u64 rx_mcast_frames
; /* all multicast frames */
140 u64 rx_ucast_frames
; /* all unicast frames */
141 u64 rx_too_long
; /* # of frames exceeding MTU */
142 u64 rx_jabber
; /* # of jabber frames */
143 u64 rx_fcs_err
; /* # of received frames with bad FCS */
144 u64 rx_len_err
; /* # of received frames with length error */
145 u64 rx_symbol_err
; /* symbol errors */
146 u64 rx_runt
; /* # of short frames */
148 u64 rx_frames_64
; /* # of Rx frames in a particular range */
149 u64 rx_frames_65_127
;
150 u64 rx_frames_128_255
;
151 u64 rx_frames_256_511
;
152 u64 rx_frames_512_1023
;
153 u64 rx_frames_1024_1518
;
154 u64 rx_frames_1519_max
;
156 u64 rx_pause
; /* # of received pause frames */
157 u64 rx_ppp0
; /* # of received PPP prio 0 frames */
158 u64 rx_ppp1
; /* # of received PPP prio 1 frames */
159 u64 rx_ppp2
; /* # of received PPP prio 2 frames */
160 u64 rx_ppp3
; /* # of received PPP prio 3 frames */
161 u64 rx_ppp4
; /* # of received PPP prio 4 frames */
162 u64 rx_ppp5
; /* # of received PPP prio 5 frames */
163 u64 rx_ppp6
; /* # of received PPP prio 6 frames */
164 u64 rx_ppp7
; /* # of received PPP prio 7 frames */
166 u64 rx_ovflow0
; /* drops due to buffer-group 0 overflows */
167 u64 rx_ovflow1
; /* drops due to buffer-group 1 overflows */
168 u64 rx_ovflow2
; /* drops due to buffer-group 2 overflows */
169 u64 rx_ovflow3
; /* drops due to buffer-group 3 overflows */
170 u64 rx_trunc0
; /* buffer-group 0 truncated packets */
171 u64 rx_trunc1
; /* buffer-group 1 truncated packets */
172 u64 rx_trunc2
; /* buffer-group 2 truncated packets */
173 u64 rx_trunc3
; /* buffer-group 3 truncated packets */
176 struct lb_port_stats
{
189 u64 frames_1024_1518
;
204 struct tp_tcp_stats
{
208 u64 tcp_retrans_segs
;
211 struct tp_usm_stats
{
217 struct tp_fcoe_stats
{
223 struct tp_err_stats
{
227 u32 tnl_cong_drops
[4];
228 u32 ofld_chan_drops
[4];
230 u32 ofld_vlan_drops
[4];
236 struct tp_cpl_stats
{
241 struct tp_rdma_stats
{
247 u32 hps
; /* host page size for our PF/VF */
248 u32 eq_qpp
; /* egress queues/page for our PF/VF */
249 u32 iq_qpp
; /* egress queues/page for our PF/VF */
253 unsigned int tre
; /* log2 of core clocks per TP tick */
254 unsigned int la_mask
; /* what events are recorded by TP LA */
255 unsigned short tx_modq_map
; /* TX modulation scheduler queue to */
258 uint32_t dack_re
; /* DACK timer resolution */
259 unsigned short tx_modq
[NCHAN
]; /* channel to modulation queue map */
261 u32 vlan_pri_map
; /* cached TP_VLAN_PRI_MAP */
262 u32 ingress_config
; /* cached TP_INGRESS_CONFIG */
264 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
265 * subset of the set of fields which may be present in the Compressed
266 * Filter Tuple portion of filters and TCP TCB connections. The
267 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
268 * Since a variable number of fields may or may not be present, their
269 * shifted field positions within the Compressed Filter Tuple may
270 * vary, or not even be present if the field isn't selected in
271 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
272 * places we store their offsets here, or a -1 if the field isn't
284 u8 sn
[SERNUM_LEN
+ 1];
287 u8 na
[MACADDR_LEN
+ 1];
295 struct devlog_params
{
296 u32 memtype
; /* which memory (EDC0, EDC1, MC) */
297 u32 start
; /* start of log in firmware memory */
298 u32 size
; /* size of log */
301 /* Stores chip specific parameters */
302 struct arch_specific_params
{
305 u8 cng_ch_bits_log
; /* congestion channel map bits width */
312 struct adapter_params
{
313 struct sge_params sge
;
315 struct vpd_params vpd
;
316 struct pci_params pci
;
317 struct devlog_params devlog
;
318 enum pcie_memwin drv_memwin
;
320 unsigned int cim_la_size
;
322 unsigned int sf_size
; /* serial flash size in bytes */
323 unsigned int sf_nsec
; /* # of flash sectors */
324 unsigned int sf_fw_start
; /* start of FW image in flash */
326 unsigned int fw_vers
;
327 unsigned int bs_vers
; /* bootstrap version */
328 unsigned int tp_vers
;
329 unsigned int er_vers
; /* expansion ROM version */
332 unsigned short mtus
[NMTUS
];
333 unsigned short a_wnd
[NCCTRL_WIN
];
334 unsigned short b_wnd
[NCCTRL_WIN
];
336 unsigned char nports
; /* # of ethernet ports */
337 unsigned char portvec
;
338 enum chip_type chip
; /* chip code */
339 struct arch_specific_params arch
; /* chip specific params */
340 unsigned char offload
;
342 unsigned char bypass
;
344 unsigned int ofldq_wr_cred
;
345 bool ulptx_memwrite_dsgl
; /* use of T5 DSGL allowed */
347 unsigned int max_ordird_qp
; /* Max read depth per RDMA QP */
348 unsigned int max_ird_adapter
; /* Max read depth per adapter */
351 /* State needed to monitor the forward progress of SGE Ingress DMA activities
352 * and possible hangs.
354 struct sge_idma_monitor_state
{
355 unsigned int idma_1s_thresh
; /* 1s threshold in Core Clock ticks */
356 unsigned int idma_stalled
[2]; /* synthesized stalled timers in HZ */
357 unsigned int idma_state
[2]; /* IDMA Hang detect state */
358 unsigned int idma_qid
[2]; /* IDMA Hung Ingress Queue ID */
359 unsigned int idma_warn
[2]; /* time to warning in HZ */
362 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format.
363 * The access and execute times are signed in order to accommodate negative
367 u64 cmd
[MBOX_LEN
/ 8]; /* a Firmware Mailbox Command/Reply */
368 u64 timestamp
; /* OS-dependent timestamp */
369 u32 seqno
; /* sequence number */
370 s16 access
; /* time (ms) to access mailbox */
371 s16 execute
; /* time (ms) to execute */
374 struct mbox_cmd_log
{
375 unsigned int size
; /* number of entries in the log */
376 unsigned int cursor
; /* next position in the log to write */
377 u32 seqno
; /* next sequence number */
378 /* variable length mailbox command log starts here */
381 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index,
382 * return a pointer to the specified entry.
384 static inline struct mbox_cmd
*mbox_cmd_log_entry(struct mbox_cmd_log
*log
,
385 unsigned int entry_idx
)
387 return &((struct mbox_cmd
*)&(log
)[1])[entry_idx
];
390 #include "t4fw_api.h"
392 #define FW_VERSION(chip) ( \
393 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
394 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
395 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
396 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
397 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
403 struct fw_hdr fw_hdr
;
407 struct trace_params
{
408 u32 data
[TRACE_LEN
/ 4];
409 u32 mask
[TRACE_LEN
/ 4];
410 unsigned short snap_len
;
411 unsigned short min_len
;
412 unsigned char skip_ofst
;
413 unsigned char skip_len
;
414 unsigned char invert
;
419 unsigned short supported
; /* link capabilities */
420 unsigned short advertising
; /* advertised capabilities */
421 unsigned short lp_advertising
; /* peer advertised capabilities */
422 unsigned short requested_speed
; /* speed user has requested */
423 unsigned short speed
; /* actual link speed */
424 unsigned char requested_fc
; /* flow control user has requested */
425 unsigned char fc
; /* actual link flow control */
426 unsigned char autoneg
; /* autonegotiating? */
427 unsigned char link_ok
; /* link up? */
428 unsigned char link_down_rc
; /* link down reason */
431 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
434 MAX_ETH_QSETS
= 32, /* # of Ethernet Tx/Rx queue sets */
435 MAX_OFLD_QSETS
= 16, /* # of offload Tx, iscsi Rx queue sets */
436 MAX_CTRL_QUEUES
= NCHAN
, /* # of control Tx queues */
437 MAX_RDMA_QUEUES
= NCHAN
, /* # of streaming RDMA Rx queues */
438 MAX_RDMA_CIQS
= 32, /* # of RDMA concentrator IQs */
440 /* # of streaming iSCSIT Rx queues */
441 MAX_ISCSIT_QUEUES
= MAX_OFLD_QSETS
,
445 MAX_TXQ_ENTRIES
= 16384,
446 MAX_CTRL_TXQ_ENTRIES
= 1024,
447 MAX_RSPQ_ENTRIES
= 16384,
448 MAX_RX_BUFFERS
= 16384,
449 MIN_TXQ_ENTRIES
= 32,
450 MIN_CTRL_TXQ_ENTRIES
= 32,
451 MIN_RSPQ_ENTRIES
= 128,
456 INGQ_EXTRAS
= 2, /* firmware event queue and */
457 /* forwarded interrupts */
458 MAX_INGQ
= MAX_ETH_QSETS
+ MAX_OFLD_QSETS
+ MAX_RDMA_QUEUES
+
459 MAX_RDMA_CIQS
+ MAX_ISCSIT_QUEUES
+ INGQ_EXTRAS
,
465 #include "cxgb4_dcb.h"
467 #ifdef CONFIG_CHELSIO_T4_FCOE
468 #include "cxgb4_fcoe.h"
469 #endif /* CONFIG_CHELSIO_T4_FCOE */
472 struct adapter
*adapter
;
474 s16 xact_addr_filt
; /* index of exact MAC address filter */
475 u16 rss_size
; /* size of VI's RSS table slice */
477 enum fw_port_type port_type
;
481 u8 lport
; /* associated offload logical port */
482 u8 nqsets
; /* # of qsets */
483 u8 first_qset
; /* index of first qset */
485 struct link_config link_cfg
;
487 struct port_stats stats_base
;
488 #ifdef CONFIG_CHELSIO_T4_DCB
489 struct port_dcb_info dcb
; /* Data Center Bridging support */
491 #ifdef CONFIG_CHELSIO_T4_FCOE
492 struct cxgb_fcoe fcoe
;
493 #endif /* CONFIG_CHELSIO_T4_FCOE */
494 bool rxtstamp
; /* Enable TS */
495 struct hwtstamp_config tstamp_config
;
501 enum { /* adapter flags */
502 FULL_INIT_DONE
= (1 << 0),
503 DEV_ENABLED
= (1 << 1),
504 USING_MSI
= (1 << 2),
505 USING_MSIX
= (1 << 3),
507 RSS_TNLALLLOOKUP
= (1 << 5),
508 USING_SOFT_PARAMS
= (1 << 6),
509 MASTER_PF
= (1 << 7),
510 FW_OFLD_CONN
= (1 << 9),
515 struct sge_fl
{ /* SGE free-buffer queue state */
516 unsigned int avail
; /* # of available Rx buffers */
517 unsigned int pend_cred
; /* new buffers since last FL DB ring */
518 unsigned int cidx
; /* consumer index */
519 unsigned int pidx
; /* producer index */
520 unsigned long alloc_failed
; /* # of times buffer allocation failed */
521 unsigned long large_alloc_failed
;
522 unsigned long mapping_err
; /* # of RX Buffer DMA Mapping failures */
523 unsigned long low
; /* # of times momentarily starving */
524 unsigned long starving
;
526 unsigned int cntxt_id
; /* SGE context id for the free list */
527 unsigned int size
; /* capacity of free list */
528 struct rx_sw_desc
*sdesc
; /* address of SW Rx descriptor ring */
529 __be64
*desc
; /* address of HW Rx descriptor ring */
530 dma_addr_t addr
; /* bus address of HW ring start */
531 void __iomem
*bar2_addr
; /* address of BAR2 Queue registers */
532 unsigned int bar2_qid
; /* Queue ID for BAR2 Queue registers */
535 /* A packet gather list */
537 u64 sgetstamp
; /* SGE Time Stamp for Ingress Packet */
538 struct page_frag frags
[MAX_SKB_FRAGS
];
539 void *va
; /* virtual address of first byte */
540 unsigned int nfrags
; /* # of fragments */
541 unsigned int tot_len
; /* total length of fragments */
544 typedef int (*rspq_handler_t
)(struct sge_rspq
*q
, const __be64
*rsp
,
545 const struct pkt_gl
*gl
);
546 typedef void (*rspq_flush_handler_t
)(struct sge_rspq
*q
);
547 /* LRO related declarations for ULD */
549 #define MAX_LRO_SESSIONS 64
550 u8 lro_session_cnt
; /* # of sessions to aggregate */
551 unsigned long lro_pkts
; /* # of LRO super packets */
552 unsigned long lro_merged
; /* # of wire packets merged by LRO */
553 struct sk_buff_head lroq
; /* list of aggregated sessions */
556 struct sge_rspq
{ /* state for an SGE response queue */
557 struct napi_struct napi
;
558 const __be64
*cur_desc
; /* current descriptor in queue */
559 unsigned int cidx
; /* consumer index */
560 u8 gen
; /* current generation bit */
561 u8 intr_params
; /* interrupt holdoff parameters */
562 u8 next_intr_params
; /* holdoff params for next interrupt */
564 u8 pktcnt_idx
; /* interrupt packet threshold */
565 u8 uld
; /* ULD handling this queue */
566 u8 idx
; /* queue index within its group */
567 int offset
; /* offset into current Rx buffer */
568 u16 cntxt_id
; /* SGE context id for the response q */
569 u16 abs_id
; /* absolute SGE id for the response q */
570 __be64
*desc
; /* address of HW response ring */
571 dma_addr_t phys_addr
; /* physical address of the ring */
572 void __iomem
*bar2_addr
; /* address of BAR2 Queue registers */
573 unsigned int bar2_qid
; /* Queue ID for BAR2 Queue registers */
574 unsigned int iqe_len
; /* entry size */
575 unsigned int size
; /* capacity of response queue */
576 struct adapter
*adap
;
577 struct net_device
*netdev
; /* associated net device */
578 rspq_handler_t handler
;
579 rspq_flush_handler_t flush_handler
;
580 struct t4_lro_mgr lro_mgr
;
581 #ifdef CONFIG_NET_RX_BUSY_POLL
582 #define CXGB_POLL_STATE_IDLE 0
583 #define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */
584 #define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */
585 #define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */
586 #define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */
587 #define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \
588 CXGB_POLL_STATE_POLL_YIELD)
589 #define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \
590 CXGB_POLL_STATE_POLL)
591 #define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \
592 CXGB_POLL_STATE_POLL_YIELD)
593 unsigned int bpoll_state
;
594 spinlock_t bpoll_lock
; /* lock for busy poll */
595 #endif /* CONFIG_NET_RX_BUSY_POLL */
599 struct sge_eth_stats
{ /* Ethernet queue statistics */
600 unsigned long pkts
; /* # of ethernet packets */
601 unsigned long lro_pkts
; /* # of LRO super packets */
602 unsigned long lro_merged
; /* # of wire packets merged by LRO */
603 unsigned long rx_cso
; /* # of Rx checksum offloads */
604 unsigned long vlan_ex
; /* # of Rx VLAN extractions */
605 unsigned long rx_drops
; /* # of packets dropped due to no mem */
608 struct sge_eth_rxq
{ /* SW Ethernet Rx queue */
609 struct sge_rspq rspq
;
611 struct sge_eth_stats stats
;
612 } ____cacheline_aligned_in_smp
;
614 struct sge_ofld_stats
{ /* offload queue statistics */
615 unsigned long pkts
; /* # of packets */
616 unsigned long imm
; /* # of immediate-data packets */
617 unsigned long an
; /* # of asynchronous notifications */
618 unsigned long nomem
; /* # of responses deferred due to no mem */
621 struct sge_ofld_rxq
{ /* SW offload Rx queue */
622 struct sge_rspq rspq
;
624 struct sge_ofld_stats stats
;
625 } ____cacheline_aligned_in_smp
;
634 unsigned int in_use
; /* # of in-use Tx descriptors */
635 unsigned int size
; /* # of descriptors */
636 unsigned int cidx
; /* SW consumer index */
637 unsigned int pidx
; /* producer index */
638 unsigned long stops
; /* # of times q has been stopped */
639 unsigned long restarts
; /* # of queue restarts */
640 unsigned int cntxt_id
; /* SGE context id for the Tx q */
641 struct tx_desc
*desc
; /* address of HW Tx descriptor ring */
642 struct tx_sw_desc
*sdesc
; /* address of SW Tx descriptor ring */
643 struct sge_qstat
*stat
; /* queue status entry */
644 dma_addr_t phys_addr
; /* physical address of the ring */
647 unsigned short db_pidx
;
648 unsigned short db_pidx_inc
;
649 void __iomem
*bar2_addr
; /* address of BAR2 Queue registers */
650 unsigned int bar2_qid
; /* Queue ID for BAR2 Queue registers */
653 struct sge_eth_txq
{ /* state for an SGE Ethernet Tx queue */
655 struct netdev_queue
*txq
; /* associated netdev TX queue */
656 #ifdef CONFIG_CHELSIO_T4_DCB
657 u8 dcb_prio
; /* DCB Priority bound to queue */
659 unsigned long tso
; /* # of TSO requests */
660 unsigned long tx_cso
; /* # of Tx checksum offloads */
661 unsigned long vlan_ins
; /* # of Tx VLAN insertions */
662 unsigned long mapping_err
; /* # of I/O MMU packet mapping errors */
663 } ____cacheline_aligned_in_smp
;
665 struct sge_ofld_txq
{ /* state for an SGE offload Tx queue */
667 struct adapter
*adap
;
668 struct sk_buff_head sendq
; /* list of backpressured packets */
669 struct tasklet_struct qresume_tsk
; /* restarts the queue */
670 bool service_ofldq_running
; /* service_ofldq() is processing sendq */
671 u8 full
; /* the Tx ring is full */
672 unsigned long mapping_err
; /* # of I/O MMU packet mapping errors */
673 } ____cacheline_aligned_in_smp
;
675 struct sge_ctrl_txq
{ /* state for an SGE control Tx queue */
677 struct adapter
*adap
;
678 struct sk_buff_head sendq
; /* list of backpressured packets */
679 struct tasklet_struct qresume_tsk
; /* restarts the queue */
680 u8 full
; /* the Tx ring is full */
681 } ____cacheline_aligned_in_smp
;
684 struct sge_eth_txq ethtxq
[MAX_ETH_QSETS
];
685 struct sge_ofld_txq ofldtxq
[MAX_OFLD_QSETS
];
686 struct sge_ctrl_txq ctrlq
[MAX_CTRL_QUEUES
];
688 struct sge_eth_rxq ethrxq
[MAX_ETH_QSETS
];
689 struct sge_ofld_rxq iscsirxq
[MAX_OFLD_QSETS
];
690 struct sge_ofld_rxq iscsitrxq
[MAX_ISCSIT_QUEUES
];
691 struct sge_ofld_rxq rdmarxq
[MAX_RDMA_QUEUES
];
692 struct sge_ofld_rxq rdmaciq
[MAX_RDMA_CIQS
];
693 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp
;
695 struct sge_rspq intrq ____cacheline_aligned_in_smp
;
696 spinlock_t intrq_lock
;
698 u16 max_ethqsets
; /* # of available Ethernet queue sets */
699 u16 ethqsets
; /* # of active Ethernet queue sets */
700 u16 ethtxq_rover
; /* Tx queue to clean up next */
701 u16 iscsiqsets
; /* # of active iSCSI queue sets */
702 u16 niscsitq
; /* # of available iSCST Rx queues */
703 u16 rdmaqs
; /* # of available RDMA Rx queues */
704 u16 rdmaciqs
; /* # of available RDMA concentrator IQs */
705 u16 iscsi_rxq
[MAX_OFLD_QSETS
];
706 u16 iscsit_rxq
[MAX_ISCSIT_QUEUES
];
707 u16 rdma_rxq
[MAX_RDMA_QUEUES
];
708 u16 rdma_ciq
[MAX_RDMA_CIQS
];
709 u16 timer_val
[SGE_NTIMERS
];
710 u8 counter_val
[SGE_NCOUNTERS
];
711 u32 fl_pg_order
; /* large page allocation size */
712 u32 stat_len
; /* length of status page at ring end */
713 u32 pktshift
; /* padding between CPL & packet data */
714 u32 fl_align
; /* response queue message alignment */
715 u32 fl_starve_thres
; /* Free List starvation threshold */
717 struct sge_idma_monitor_state idma_monitor
;
718 unsigned int egr_start
;
720 unsigned int ingr_start
;
721 unsigned int ingr_sz
;
722 void **egr_map
; /* qid->queue egress queue map */
723 struct sge_rspq
**ingr_map
; /* qid->queue ingress queue map */
724 unsigned long *starving_fl
;
725 unsigned long *txq_maperr
;
726 unsigned long *blocked_fl
;
727 struct timer_list rx_timer
; /* refills starving FLs */
728 struct timer_list tx_timer
; /* checks Tx queues */
731 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
732 #define for_each_iscsirxq(sge, i) for (i = 0; i < (sge)->iscsiqsets; i++)
733 #define for_each_iscsitrxq(sge, i) for (i = 0; i < (sge)->niscsitq; i++)
734 #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
735 #define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++)
739 #ifdef CONFIG_PCI_IOV
741 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
742 * Configuration initialization for T5 only has SR-IOV functionality enabled
743 * on PF0-3 in order to simplify everything.
745 #define NUM_OF_PF_WITH_SRIOV 4
749 struct doorbell_stats
{
755 struct hash_mac_addr
{
756 struct list_head list
;
764 struct pci_dev
*pdev
;
765 struct device
*pdev_dev
;
774 struct adapter_params params
;
775 struct cxgb4_virt_res vres
;
780 char desc
[IFNAMSIZ
+ 10];
781 } msix_info
[MAX_INGQ
+ 1];
783 struct doorbell_stats db_stats
;
786 struct net_device
*port
[MAX_NPORTS
];
787 u8 chan_map
[NCHAN
]; /* channel -> port map */
790 unsigned int l2t_start
;
791 unsigned int l2t_end
;
792 struct l2t_data
*l2t
;
793 unsigned int clipt_start
;
794 unsigned int clipt_end
;
795 struct clip_tbl
*clipt
;
796 void *uld_handle
[CXGB4_ULD_MAX
];
797 struct list_head list_node
;
798 struct list_head rcu_node
;
799 struct list_head mac_hlist
; /* list of MAC addresses in MPS Hash */
803 struct tid_info tids
;
804 void **tid_release_head
;
805 spinlock_t tid_release_lock
;
806 struct workqueue_struct
*workq
;
807 struct work_struct tid_release_task
;
808 struct work_struct db_full_task
;
809 struct work_struct db_drop_task
;
810 bool tid_release_task_busy
;
812 /* support for mailbox command/reply logging */
813 #define T4_OS_LOG_MBOX_CMDS 256
814 struct mbox_cmd_log
*mbox_log
;
816 struct dentry
*debugfs_root
;
817 bool use_bd
; /* Use SGE Back Door intfc for reading SGE Contexts */
818 bool trace_rss
; /* 1 implies that different RSS flit per filter is
819 * used per filter else if 0 default RSS flit is
820 * used for all 4 filters.
823 spinlock_t stats_lock
;
824 spinlock_t win0_lock ____cacheline_aligned_in_smp
;
827 /* Defined bit width of user definable filter tuples
829 #define ETHTYPE_BITWIDTH 16
830 #define FRAG_BITWIDTH 1
831 #define MACIDX_BITWIDTH 9
832 #define FCOE_BITWIDTH 1
833 #define IPORT_BITWIDTH 3
834 #define MATCHTYPE_BITWIDTH 3
835 #define PROTO_BITWIDTH 8
836 #define TOS_BITWIDTH 8
837 #define PF_BITWIDTH 8
838 #define VF_BITWIDTH 8
839 #define IVLAN_BITWIDTH 16
840 #define OVLAN_BITWIDTH 16
842 /* Filter matching rules. These consist of a set of ingress packet field
843 * (value, mask) tuples. The associated ingress packet field matches the
844 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
845 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
846 * matches an ingress packet when all of the individual individual field
847 * matching rules are true.
849 * Partial field masks are always valid, however, while it may be easy to
850 * understand their meanings for some fields (e.g. IP address to match a
851 * subnet), for others making sensible partial masks is less intuitive (e.g.
852 * MPS match type) ...
854 * Most of the following data structures are modeled on T4 capabilities.
855 * Drivers for earlier chips use the subsets which make sense for those chips.
856 * We really need to come up with a hardware-independent mechanism to
857 * represent hardware filter capabilities ...
859 struct ch_filter_tuple
{
860 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
861 * register selects which of these fields will participate in the
862 * filter match rules -- up to a maximum of 36 bits. Because
863 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
866 uint32_t ethtype
:ETHTYPE_BITWIDTH
; /* Ethernet type */
867 uint32_t frag
:FRAG_BITWIDTH
; /* IP fragmentation header */
868 uint32_t ivlan_vld
:1; /* inner VLAN valid */
869 uint32_t ovlan_vld
:1; /* outer VLAN valid */
870 uint32_t pfvf_vld
:1; /* PF/VF valid */
871 uint32_t macidx
:MACIDX_BITWIDTH
; /* exact match MAC index */
872 uint32_t fcoe
:FCOE_BITWIDTH
; /* FCoE packet */
873 uint32_t iport
:IPORT_BITWIDTH
; /* ingress port */
874 uint32_t matchtype
:MATCHTYPE_BITWIDTH
; /* MPS match type */
875 uint32_t proto
:PROTO_BITWIDTH
; /* protocol type */
876 uint32_t tos
:TOS_BITWIDTH
; /* TOS/Traffic Type */
877 uint32_t pf
:PF_BITWIDTH
; /* PCI-E PF ID */
878 uint32_t vf
:VF_BITWIDTH
; /* PCI-E VF ID */
879 uint32_t ivlan
:IVLAN_BITWIDTH
; /* inner VLAN */
880 uint32_t ovlan
:OVLAN_BITWIDTH
; /* outer VLAN */
882 /* Uncompressed header matching field rules. These are always
883 * available for field rules.
885 uint8_t lip
[16]; /* local IP address (IPv4 in [3:0]) */
886 uint8_t fip
[16]; /* foreign IP address (IPv4 in [3:0]) */
887 uint16_t lport
; /* local port */
888 uint16_t fport
; /* foreign port */
891 /* A filter ioctl command.
893 struct ch_filter_specification
{
894 /* Administrative fields for filter.
896 uint32_t hitcnts
:1; /* count filter hits in TCB */
897 uint32_t prio
:1; /* filter has priority over active/server */
899 /* Fundamental filter typing. This is the one element of filter
900 * matching that doesn't exist as a (value, mask) tuple.
902 uint32_t type
:1; /* 0 => IPv4, 1 => IPv6 */
904 /* Packet dispatch information. Ingress packets which match the
905 * filter rules will be dropped, passed to the host or switched back
906 * out as egress packets.
908 uint32_t action
:2; /* drop, pass, switch */
910 uint32_t rpttid
:1; /* report TID in RSS hash field */
912 uint32_t dirsteer
:1; /* 0 => RSS, 1 => steer to iq */
913 uint32_t iq
:10; /* ingress queue */
915 uint32_t maskhash
:1; /* dirsteer=0: store RSS hash in TCB */
916 uint32_t dirsteerhash
:1;/* dirsteer=1: 0 => TCB contains RSS hash */
917 /* 1 => TCB contains IQ ID */
919 /* Switch proxy/rewrite fields. An ingress packet which matches a
920 * filter with "switch" set will be looped back out as an egress
921 * packet -- potentially with some Ethernet header rewriting.
923 uint32_t eport
:2; /* egress port to switch packet out */
924 uint32_t newdmac
:1; /* rewrite destination MAC address */
925 uint32_t newsmac
:1; /* rewrite source MAC address */
926 uint32_t newvlan
:2; /* rewrite VLAN Tag */
927 uint8_t dmac
[ETH_ALEN
]; /* new destination MAC address */
928 uint8_t smac
[ETH_ALEN
]; /* new source MAC address */
929 uint16_t vlan
; /* VLAN Tag to insert */
931 /* Filter rule value/mask pairs.
933 struct ch_filter_tuple val
;
934 struct ch_filter_tuple mask
;
938 FILTER_PASS
= 0, /* default */
944 VLAN_NOCHANGE
= 0, /* default */
950 static inline int is_offload(const struct adapter
*adap
)
952 return adap
->params
.offload
;
955 static inline u32
t4_read_reg(struct adapter
*adap
, u32 reg_addr
)
957 return readl(adap
->regs
+ reg_addr
);
960 static inline void t4_write_reg(struct adapter
*adap
, u32 reg_addr
, u32 val
)
962 writel(val
, adap
->regs
+ reg_addr
);
966 static inline u64
readq(const volatile void __iomem
*addr
)
968 return readl(addr
) + ((u64
)readl(addr
+ 4) << 32);
971 static inline void writeq(u64 val
, volatile void __iomem
*addr
)
974 writel(val
>> 32, addr
+ 4);
978 static inline u64
t4_read_reg64(struct adapter
*adap
, u32 reg_addr
)
980 return readq(adap
->regs
+ reg_addr
);
983 static inline void t4_write_reg64(struct adapter
*adap
, u32 reg_addr
, u64 val
)
985 writeq(val
, adap
->regs
+ reg_addr
);
989 * t4_set_hw_addr - store a port's MAC address in SW
990 * @adapter: the adapter
991 * @port_idx: the port index
992 * @hw_addr: the Ethernet address
994 * Store the Ethernet address of the given port in SW. Called by the common
995 * code when it retrieves a port's Ethernet address from EEPROM.
997 static inline void t4_set_hw_addr(struct adapter
*adapter
, int port_idx
,
1000 ether_addr_copy(adapter
->port
[port_idx
]->dev_addr
, hw_addr
);
1001 ether_addr_copy(adapter
->port
[port_idx
]->perm_addr
, hw_addr
);
1005 * netdev2pinfo - return the port_info structure associated with a net_device
1008 * Return the struct port_info associated with a net_device
1010 static inline struct port_info
*netdev2pinfo(const struct net_device
*dev
)
1012 return netdev_priv(dev
);
1016 * adap2pinfo - return the port_info of a port
1017 * @adap: the adapter
1018 * @idx: the port index
1020 * Return the port_info structure for the port of the given index.
1022 static inline struct port_info
*adap2pinfo(struct adapter
*adap
, int idx
)
1024 return netdev_priv(adap
->port
[idx
]);
1028 * netdev2adap - return the adapter structure associated with a net_device
1031 * Return the struct adapter associated with a net_device
1033 static inline struct adapter
*netdev2adap(const struct net_device
*dev
)
1035 return netdev2pinfo(dev
)->adapter
;
1038 #ifdef CONFIG_NET_RX_BUSY_POLL
1039 static inline void cxgb_busy_poll_init_lock(struct sge_rspq
*q
)
1041 spin_lock_init(&q
->bpoll_lock
);
1042 q
->bpoll_state
= CXGB_POLL_STATE_IDLE
;
1045 static inline bool cxgb_poll_lock_napi(struct sge_rspq
*q
)
1049 spin_lock(&q
->bpoll_lock
);
1050 if (q
->bpoll_state
& CXGB_POLL_LOCKED
) {
1051 q
->bpoll_state
|= CXGB_POLL_STATE_NAPI_YIELD
;
1054 q
->bpoll_state
= CXGB_POLL_STATE_NAPI
;
1056 spin_unlock(&q
->bpoll_lock
);
1060 static inline bool cxgb_poll_unlock_napi(struct sge_rspq
*q
)
1064 spin_lock(&q
->bpoll_lock
);
1065 if (q
->bpoll_state
& CXGB_POLL_STATE_POLL_YIELD
)
1067 q
->bpoll_state
= CXGB_POLL_STATE_IDLE
;
1068 spin_unlock(&q
->bpoll_lock
);
1072 static inline bool cxgb_poll_lock_poll(struct sge_rspq
*q
)
1076 spin_lock_bh(&q
->bpoll_lock
);
1077 if (q
->bpoll_state
& CXGB_POLL_LOCKED
) {
1078 q
->bpoll_state
|= CXGB_POLL_STATE_POLL_YIELD
;
1081 q
->bpoll_state
|= CXGB_POLL_STATE_POLL
;
1083 spin_unlock_bh(&q
->bpoll_lock
);
1087 static inline bool cxgb_poll_unlock_poll(struct sge_rspq
*q
)
1091 spin_lock_bh(&q
->bpoll_lock
);
1092 if (q
->bpoll_state
& CXGB_POLL_STATE_POLL_YIELD
)
1094 q
->bpoll_state
= CXGB_POLL_STATE_IDLE
;
1095 spin_unlock_bh(&q
->bpoll_lock
);
1099 static inline bool cxgb_poll_busy_polling(struct sge_rspq
*q
)
1101 return q
->bpoll_state
& CXGB_POLL_USER_PEND
;
1104 static inline void cxgb_busy_poll_init_lock(struct sge_rspq
*q
)
1108 static inline bool cxgb_poll_lock_napi(struct sge_rspq
*q
)
1113 static inline bool cxgb_poll_unlock_napi(struct sge_rspq
*q
)
1118 static inline bool cxgb_poll_lock_poll(struct sge_rspq
*q
)
1123 static inline bool cxgb_poll_unlock_poll(struct sge_rspq
*q
)
1128 static inline bool cxgb_poll_busy_polling(struct sge_rspq
*q
)
1132 #endif /* CONFIG_NET_RX_BUSY_POLL */
1134 /* Return a version number to identify the type of adapter. The scheme is:
1135 * - bits 0..9: chip version
1136 * - bits 10..15: chip revision
1137 * - bits 16..23: register dump version
1139 static inline unsigned int mk_adap_vers(struct adapter
*ap
)
1141 return CHELSIO_CHIP_VERSION(ap
->params
.chip
) |
1142 (CHELSIO_CHIP_RELEASE(ap
->params
.chip
) << 10) | (1 << 16);
1145 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */
1146 static inline unsigned int qtimer_val(const struct adapter
*adap
,
1147 const struct sge_rspq
*q
)
1149 unsigned int idx
= q
->intr_params
>> 1;
1151 return idx
< SGE_NTIMERS
? adap
->sge
.timer_val
[idx
] : 0;
1154 /* driver version & name used for ethtool_drvinfo */
1155 extern char cxgb4_driver_name
[];
1156 extern const char cxgb4_driver_version
[];
1158 void t4_os_portmod_changed(const struct adapter
*adap
, int port_id
);
1159 void t4_os_link_changed(struct adapter
*adap
, int port_id
, int link_stat
);
1161 void *t4_alloc_mem(size_t size
);
1163 void t4_free_sge_resources(struct adapter
*adap
);
1164 void t4_free_ofld_rxqs(struct adapter
*adap
, int n
, struct sge_ofld_rxq
*q
);
1165 irq_handler_t
t4_intr_handler(struct adapter
*adap
);
1166 netdev_tx_t
t4_eth_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
1167 int t4_ethrx_handler(struct sge_rspq
*q
, const __be64
*rsp
,
1168 const struct pkt_gl
*gl
);
1169 int t4_mgmt_tx(struct adapter
*adap
, struct sk_buff
*skb
);
1170 int t4_ofld_send(struct adapter
*adap
, struct sk_buff
*skb
);
1171 int t4_sge_alloc_rxq(struct adapter
*adap
, struct sge_rspq
*iq
, bool fwevtq
,
1172 struct net_device
*dev
, int intr_idx
,
1173 struct sge_fl
*fl
, rspq_handler_t hnd
,
1174 rspq_flush_handler_t flush_handler
, int cong
);
1175 int t4_sge_alloc_eth_txq(struct adapter
*adap
, struct sge_eth_txq
*txq
,
1176 struct net_device
*dev
, struct netdev_queue
*netdevq
,
1178 int t4_sge_alloc_ctrl_txq(struct adapter
*adap
, struct sge_ctrl_txq
*txq
,
1179 struct net_device
*dev
, unsigned int iqid
,
1180 unsigned int cmplqid
);
1181 int t4_sge_alloc_ofld_txq(struct adapter
*adap
, struct sge_ofld_txq
*txq
,
1182 struct net_device
*dev
, unsigned int iqid
);
1183 irqreturn_t
t4_sge_intr_msix(int irq
, void *cookie
);
1184 int t4_sge_init(struct adapter
*adap
);
1185 void t4_sge_start(struct adapter
*adap
);
1186 void t4_sge_stop(struct adapter
*adap
);
1187 int cxgb_busy_poll(struct napi_struct
*napi
);
1188 int cxgb4_set_rspq_intr_params(struct sge_rspq
*q
, unsigned int us
,
1190 void cxgb4_set_ethtool_ops(struct net_device
*netdev
);
1191 int cxgb4_write_rss(const struct port_info
*pi
, const u16
*queues
);
1192 extern int dbfifo_int_thresh
;
1194 #define for_each_port(adapter, iter) \
1195 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1197 static inline int is_bypass(struct adapter
*adap
)
1199 return adap
->params
.bypass
;
1202 static inline int is_bypass_device(int device
)
1204 /* this should be set based upon device capabilities */
1214 static inline int is_10gbt_device(int device
)
1216 /* this should be set based upon device capabilities */
1227 static inline unsigned int core_ticks_per_usec(const struct adapter
*adap
)
1229 return adap
->params
.vpd
.cclk
/ 1000;
1232 static inline unsigned int us_to_core_ticks(const struct adapter
*adap
,
1235 return (us
* adap
->params
.vpd
.cclk
) / 1000;
1238 static inline unsigned int core_ticks_to_us(const struct adapter
*adapter
,
1241 /* add Core Clock / 2 to round ticks to nearest uS */
1242 return ((ticks
* 1000 + adapter
->params
.vpd
.cclk
/2) /
1243 adapter
->params
.vpd
.cclk
);
1246 void t4_set_reg_field(struct adapter
*adap
, unsigned int addr
, u32 mask
,
1249 int t4_wr_mbox_meat_timeout(struct adapter
*adap
, int mbox
, const void *cmd
,
1250 int size
, void *rpl
, bool sleep_ok
, int timeout
);
1251 int t4_wr_mbox_meat(struct adapter
*adap
, int mbox
, const void *cmd
, int size
,
1252 void *rpl
, bool sleep_ok
);
1254 static inline int t4_wr_mbox_timeout(struct adapter
*adap
, int mbox
,
1255 const void *cmd
, int size
, void *rpl
,
1258 return t4_wr_mbox_meat_timeout(adap
, mbox
, cmd
, size
, rpl
, true,
1262 static inline int t4_wr_mbox(struct adapter
*adap
, int mbox
, const void *cmd
,
1263 int size
, void *rpl
)
1265 return t4_wr_mbox_meat(adap
, mbox
, cmd
, size
, rpl
, true);
1268 static inline int t4_wr_mbox_ns(struct adapter
*adap
, int mbox
, const void *cmd
,
1269 int size
, void *rpl
)
1271 return t4_wr_mbox_meat(adap
, mbox
, cmd
, size
, rpl
, false);
1275 * hash_mac_addr - return the hash value of a MAC address
1276 * @addr: the 48-bit Ethernet MAC address
1278 * Hashes a MAC address according to the hash function used by HW inexact
1279 * (hash) address matching.
1281 static inline int hash_mac_addr(const u8
*addr
)
1283 u32 a
= ((u32
)addr
[0] << 16) | ((u32
)addr
[1] << 8) | addr
[2];
1284 u32 b
= ((u32
)addr
[3] << 16) | ((u32
)addr
[4] << 8) | addr
[5];
1292 void t4_write_indirect(struct adapter
*adap
, unsigned int addr_reg
,
1293 unsigned int data_reg
, const u32
*vals
,
1294 unsigned int nregs
, unsigned int start_idx
);
1295 void t4_read_indirect(struct adapter
*adap
, unsigned int addr_reg
,
1296 unsigned int data_reg
, u32
*vals
, unsigned int nregs
,
1297 unsigned int start_idx
);
1298 void t4_hw_pci_read_cfg4(struct adapter
*adapter
, int reg
, u32
*val
);
1300 struct fw_filter_wr
;
1302 void t4_intr_enable(struct adapter
*adapter
);
1303 void t4_intr_disable(struct adapter
*adapter
);
1304 int t4_slow_intr_handler(struct adapter
*adapter
);
1306 int t4_wait_dev_ready(void __iomem
*regs
);
1307 int t4_link_l1cfg(struct adapter
*adap
, unsigned int mbox
, unsigned int port
,
1308 struct link_config
*lc
);
1309 int t4_restart_aneg(struct adapter
*adap
, unsigned int mbox
, unsigned int port
);
1311 u32
t4_read_pcie_cfg4(struct adapter
*adap
, int reg
);
1312 u32
t4_get_util_window(struct adapter
*adap
);
1313 void t4_setup_memwin(struct adapter
*adap
, u32 memwin_base
, u32 window
);
1315 #define T4_MEMORY_WRITE 0
1316 #define T4_MEMORY_READ 1
1317 int t4_memory_rw(struct adapter
*adap
, int win
, int mtype
, u32 addr
, u32 len
,
1318 void *buf
, int dir
);
1319 static inline int t4_memory_write(struct adapter
*adap
, int mtype
, u32 addr
,
1320 u32 len
, __be32
*buf
)
1322 return t4_memory_rw(adap
, 0, mtype
, addr
, len
, buf
, 0);
1325 unsigned int t4_get_regs_len(struct adapter
*adapter
);
1326 void t4_get_regs(struct adapter
*adap
, void *buf
, size_t buf_size
);
1328 int t4_seeprom_wp(struct adapter
*adapter
, bool enable
);
1329 int t4_get_raw_vpd_params(struct adapter
*adapter
, struct vpd_params
*p
);
1330 int t4_get_vpd_params(struct adapter
*adapter
, struct vpd_params
*p
);
1331 int t4_read_flash(struct adapter
*adapter
, unsigned int addr
,
1332 unsigned int nwords
, u32
*data
, int byte_oriented
);
1333 int t4_load_fw(struct adapter
*adapter
, const u8
*fw_data
, unsigned int size
);
1334 int t4_load_phy_fw(struct adapter
*adap
,
1335 int win
, spinlock_t
*lock
,
1336 int (*phy_fw_version
)(const u8
*, size_t),
1337 const u8
*phy_fw_data
, size_t phy_fw_size
);
1338 int t4_phy_fw_ver(struct adapter
*adap
, int *phy_fw_ver
);
1339 int t4_fwcache(struct adapter
*adap
, enum fw_params_param_dev_fwcache op
);
1340 int t4_fw_upgrade(struct adapter
*adap
, unsigned int mbox
,
1341 const u8
*fw_data
, unsigned int size
, int force
);
1342 int t4_fl_pkt_align(struct adapter
*adap
);
1343 unsigned int t4_flash_cfg_addr(struct adapter
*adapter
);
1344 int t4_check_fw_version(struct adapter
*adap
);
1345 int t4_get_fw_version(struct adapter
*adapter
, u32
*vers
);
1346 int t4_get_bs_version(struct adapter
*adapter
, u32
*vers
);
1347 int t4_get_tp_version(struct adapter
*adapter
, u32
*vers
);
1348 int t4_get_exprom_version(struct adapter
*adapter
, u32
*vers
);
1349 int t4_prep_fw(struct adapter
*adap
, struct fw_info
*fw_info
,
1350 const u8
*fw_data
, unsigned int fw_size
,
1351 struct fw_hdr
*card_fw
, enum dev_state state
, int *reset
);
1352 int t4_prep_adapter(struct adapter
*adapter
);
1354 enum t4_bar2_qtype
{ T4_BAR2_QTYPE_EGRESS
, T4_BAR2_QTYPE_INGRESS
};
1355 int t4_bar2_sge_qregs(struct adapter
*adapter
,
1357 enum t4_bar2_qtype qtype
,
1360 unsigned int *pbar2_qid
);
1362 unsigned int qtimer_val(const struct adapter
*adap
,
1363 const struct sge_rspq
*q
);
1365 int t4_init_devlog_params(struct adapter
*adapter
);
1366 int t4_init_sge_params(struct adapter
*adapter
);
1367 int t4_init_tp_params(struct adapter
*adap
);
1368 int t4_filter_field_shift(const struct adapter
*adap
, int filter_sel
);
1369 int t4_init_rss_mode(struct adapter
*adap
, int mbox
);
1370 int t4_init_portinfo(struct port_info
*pi
, int mbox
,
1371 int port
, int pf
, int vf
, u8 mac
[]);
1372 int t4_port_init(struct adapter
*adap
, int mbox
, int pf
, int vf
);
1373 void t4_fatal_err(struct adapter
*adapter
);
1374 int t4_config_rss_range(struct adapter
*adapter
, int mbox
, unsigned int viid
,
1375 int start
, int n
, const u16
*rspq
, unsigned int nrspq
);
1376 int t4_config_glbl_rss(struct adapter
*adapter
, int mbox
, unsigned int mode
,
1377 unsigned int flags
);
1378 int t4_config_vi_rss(struct adapter
*adapter
, int mbox
, unsigned int viid
,
1379 unsigned int flags
, unsigned int defq
);
1380 int t4_read_rss(struct adapter
*adapter
, u16
*entries
);
1381 void t4_read_rss_key(struct adapter
*adapter
, u32
*key
);
1382 void t4_write_rss_key(struct adapter
*adap
, const u32
*key
, int idx
);
1383 void t4_read_rss_pf_config(struct adapter
*adapter
, unsigned int index
,
1385 void t4_read_rss_vf_config(struct adapter
*adapter
, unsigned int index
,
1386 u32
*vfl
, u32
*vfh
);
1387 u32
t4_read_rss_pf_map(struct adapter
*adapter
);
1388 u32
t4_read_rss_pf_mask(struct adapter
*adapter
);
1390 unsigned int t4_get_mps_bg_map(struct adapter
*adapter
, int idx
);
1391 void t4_pmtx_get_stats(struct adapter
*adap
, u32 cnt
[], u64 cycles
[]);
1392 void t4_pmrx_get_stats(struct adapter
*adap
, u32 cnt
[], u64 cycles
[]);
1393 int t4_read_cim_ibq(struct adapter
*adap
, unsigned int qid
, u32
*data
,
1395 int t4_read_cim_obq(struct adapter
*adap
, unsigned int qid
, u32
*data
,
1397 int t4_cim_read(struct adapter
*adap
, unsigned int addr
, unsigned int n
,
1398 unsigned int *valp
);
1399 int t4_cim_write(struct adapter
*adap
, unsigned int addr
, unsigned int n
,
1400 const unsigned int *valp
);
1401 int t4_cim_read_la(struct adapter
*adap
, u32
*la_buf
, unsigned int *wrptr
);
1402 void t4_cim_read_pif_la(struct adapter
*adap
, u32
*pif_req
, u32
*pif_rsp
,
1403 unsigned int *pif_req_wrptr
,
1404 unsigned int *pif_rsp_wrptr
);
1405 void t4_cim_read_ma_la(struct adapter
*adap
, u32
*ma_req
, u32
*ma_rsp
);
1406 void t4_read_cimq_cfg(struct adapter
*adap
, u16
*base
, u16
*size
, u16
*thres
);
1407 const char *t4_get_port_type_description(enum fw_port_type port_type
);
1408 void t4_get_port_stats(struct adapter
*adap
, int idx
, struct port_stats
*p
);
1409 void t4_get_port_stats_offset(struct adapter
*adap
, int idx
,
1410 struct port_stats
*stats
,
1411 struct port_stats
*offset
);
1412 void t4_get_lb_stats(struct adapter
*adap
, int idx
, struct lb_port_stats
*p
);
1413 void t4_read_mtu_tbl(struct adapter
*adap
, u16
*mtus
, u8
*mtu_log
);
1414 void t4_read_cong_tbl(struct adapter
*adap
, u16 incr
[NMTUS
][NCCTRL_WIN
]);
1415 void t4_tp_wr_bits_indirect(struct adapter
*adap
, unsigned int addr
,
1416 unsigned int mask
, unsigned int val
);
1417 void t4_tp_read_la(struct adapter
*adap
, u64
*la_buf
, unsigned int *wrptr
);
1418 void t4_tp_get_err_stats(struct adapter
*adap
, struct tp_err_stats
*st
);
1419 void t4_tp_get_cpl_stats(struct adapter
*adap
, struct tp_cpl_stats
*st
);
1420 void t4_tp_get_rdma_stats(struct adapter
*adap
, struct tp_rdma_stats
*st
);
1421 void t4_get_usm_stats(struct adapter
*adap
, struct tp_usm_stats
*st
);
1422 void t4_tp_get_tcp_stats(struct adapter
*adap
, struct tp_tcp_stats
*v4
,
1423 struct tp_tcp_stats
*v6
);
1424 void t4_get_fcoe_stats(struct adapter
*adap
, unsigned int idx
,
1425 struct tp_fcoe_stats
*st
);
1426 void t4_load_mtus(struct adapter
*adap
, const unsigned short *mtus
,
1427 const unsigned short *alpha
, const unsigned short *beta
);
1429 void t4_ulprx_read_la(struct adapter
*adap
, u32
*la_buf
);
1431 void t4_get_chan_txrate(struct adapter
*adap
, u64
*nic_rate
, u64
*ofld_rate
);
1432 void t4_mk_filtdelwr(unsigned int ftid
, struct fw_filter_wr
*wr
, int qid
);
1434 void t4_wol_magic_enable(struct adapter
*adap
, unsigned int port
,
1436 int t4_wol_pat_enable(struct adapter
*adap
, unsigned int port
, unsigned int map
,
1437 u64 mask0
, u64 mask1
, unsigned int crc
, bool enable
);
1439 int t4_fw_hello(struct adapter
*adap
, unsigned int mbox
, unsigned int evt_mbox
,
1440 enum dev_master master
, enum dev_state
*state
);
1441 int t4_fw_bye(struct adapter
*adap
, unsigned int mbox
);
1442 int t4_early_init(struct adapter
*adap
, unsigned int mbox
);
1443 int t4_fw_reset(struct adapter
*adap
, unsigned int mbox
, int reset
);
1444 int t4_fixup_host_params(struct adapter
*adap
, unsigned int page_size
,
1445 unsigned int cache_line_size
);
1446 int t4_fw_initialize(struct adapter
*adap
, unsigned int mbox
);
1447 int t4_query_params(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1448 unsigned int vf
, unsigned int nparams
, const u32
*params
,
1450 int t4_query_params_rw(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1451 unsigned int vf
, unsigned int nparams
, const u32
*params
,
1453 int t4_set_params_timeout(struct adapter
*adap
, unsigned int mbox
,
1454 unsigned int pf
, unsigned int vf
,
1455 unsigned int nparams
, const u32
*params
,
1456 const u32
*val
, int timeout
);
1457 int t4_set_params(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1458 unsigned int vf
, unsigned int nparams
, const u32
*params
,
1460 int t4_cfg_pfvf(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1461 unsigned int vf
, unsigned int txq
, unsigned int txq_eth_ctrl
,
1462 unsigned int rxqi
, unsigned int rxq
, unsigned int tc
,
1463 unsigned int vi
, unsigned int cmask
, unsigned int pmask
,
1464 unsigned int nexact
, unsigned int rcaps
, unsigned int wxcaps
);
1465 int t4_alloc_vi(struct adapter
*adap
, unsigned int mbox
, unsigned int port
,
1466 unsigned int pf
, unsigned int vf
, unsigned int nmac
, u8
*mac
,
1467 unsigned int *rss_size
);
1468 int t4_free_vi(struct adapter
*adap
, unsigned int mbox
,
1469 unsigned int pf
, unsigned int vf
,
1471 int t4_set_rxmode(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
1472 int mtu
, int promisc
, int all_multi
, int bcast
, int vlanex
,
1474 int t4_alloc_mac_filt(struct adapter
*adap
, unsigned int mbox
,
1475 unsigned int viid
, bool free
, unsigned int naddr
,
1476 const u8
**addr
, u16
*idx
, u64
*hash
, bool sleep_ok
);
1477 int t4_free_mac_filt(struct adapter
*adap
, unsigned int mbox
,
1478 unsigned int viid
, unsigned int naddr
,
1479 const u8
**addr
, bool sleep_ok
);
1480 int t4_change_mac(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
1481 int idx
, const u8
*addr
, bool persist
, bool add_smt
);
1482 int t4_set_addr_hash(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
1483 bool ucast
, u64 vec
, bool sleep_ok
);
1484 int t4_enable_vi_params(struct adapter
*adap
, unsigned int mbox
,
1485 unsigned int viid
, bool rx_en
, bool tx_en
, bool dcb_en
);
1486 int t4_enable_vi(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
1487 bool rx_en
, bool tx_en
);
1488 int t4_identify_port(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
1489 unsigned int nblinks
);
1490 int t4_mdio_rd(struct adapter
*adap
, unsigned int mbox
, unsigned int phy_addr
,
1491 unsigned int mmd
, unsigned int reg
, u16
*valp
);
1492 int t4_mdio_wr(struct adapter
*adap
, unsigned int mbox
, unsigned int phy_addr
,
1493 unsigned int mmd
, unsigned int reg
, u16 val
);
1494 int t4_iq_stop(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1495 unsigned int vf
, unsigned int iqtype
, unsigned int iqid
,
1496 unsigned int fl0id
, unsigned int fl1id
);
1497 int t4_iq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1498 unsigned int vf
, unsigned int iqtype
, unsigned int iqid
,
1499 unsigned int fl0id
, unsigned int fl1id
);
1500 int t4_eth_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1501 unsigned int vf
, unsigned int eqid
);
1502 int t4_ctrl_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1503 unsigned int vf
, unsigned int eqid
);
1504 int t4_ofld_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1505 unsigned int vf
, unsigned int eqid
);
1506 int t4_sge_ctxt_flush(struct adapter
*adap
, unsigned int mbox
);
1507 void t4_handle_get_port_info(struct port_info
*pi
, const __be64
*rpl
);
1508 int t4_handle_fw_rpl(struct adapter
*adap
, const __be64
*rpl
);
1509 void t4_db_full(struct adapter
*adapter
);
1510 void t4_db_dropped(struct adapter
*adapter
);
1511 int t4_set_trace_filter(struct adapter
*adapter
, const struct trace_params
*tp
,
1512 int filter_index
, int enable
);
1513 void t4_get_trace_filter(struct adapter
*adapter
, struct trace_params
*tp
,
1514 int filter_index
, int *enabled
);
1515 int t4_fwaddrspace_write(struct adapter
*adap
, unsigned int mbox
,
1517 void t4_sge_decode_idma_state(struct adapter
*adapter
, int state
);
1518 void t4_free_mem(void *addr
);
1519 void t4_idma_monitor_init(struct adapter
*adapter
,
1520 struct sge_idma_monitor_state
*idma
);
1521 void t4_idma_monitor(struct adapter
*adapter
,
1522 struct sge_idma_monitor_state
*idma
,
1524 #endif /* __CXGB4_H__ */