2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37 #include <linux/bitmap.h>
38 #include <linux/crc32.h>
39 #include <linux/ctype.h>
40 #include <linux/debugfs.h>
41 #include <linux/err.h>
42 #include <linux/etherdevice.h>
43 #include <linux/firmware.h>
45 #include <linux/if_vlan.h>
46 #include <linux/init.h>
47 #include <linux/log2.h>
48 #include <linux/mdio.h>
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/mutex.h>
52 #include <linux/netdevice.h>
53 #include <linux/pci.h>
54 #include <linux/aer.h>
55 #include <linux/rtnetlink.h>
56 #include <linux/sched.h>
57 #include <linux/seq_file.h>
58 #include <linux/sockios.h>
59 #include <linux/vmalloc.h>
60 #include <linux/workqueue.h>
61 #include <net/neighbour.h>
62 #include <net/netevent.h>
63 #include <net/addrconf.h>
64 #include <asm/uaccess.h>
70 #include "cxgb4_dcb.h"
73 #include <../drivers/net/bonding/bonding.h>
78 #define DRV_VERSION "2.0.0-ko"
79 #define DRV_DESC "Chelsio T4/T5 Network Driver"
82 * Max interrupt hold-off timer value in us. Queues fall back to this value
83 * under extreme memory pressure so it's largish to give the system time to
86 #define MAX_SGE_TIMERVAL 200U
90 * Physical Function provisioning constants.
92 PFRES_NVI
= 4, /* # of Virtual Interfaces */
93 PFRES_NETHCTRL
= 128, /* # of EQs used for ETH or CTRL Qs */
94 PFRES_NIQFLINT
= 128, /* # of ingress Qs/w Free List(s)/intr
96 PFRES_NEQ
= 256, /* # of egress queues */
97 PFRES_NIQ
= 0, /* # of ingress queues */
98 PFRES_TC
= 0, /* PCI-E traffic class */
99 PFRES_NEXACTF
= 128, /* # of exact MPS filters */
101 PFRES_R_CAPS
= FW_CMD_CAP_PF
,
102 PFRES_WX_CAPS
= FW_CMD_CAP_PF
,
104 #ifdef CONFIG_PCI_IOV
106 * Virtual Function provisioning constants. We need two extra Ingress
107 * Queues with Interrupt capability to serve as the VF's Firmware
108 * Event Queue and Forwarded Interrupt Queue (when using MSI mode) --
109 * neither will have Free Lists associated with them). For each
110 * Ethernet/Control Egress Queue and for each Free List, we need an
113 VFRES_NPORTS
= 1, /* # of "ports" per VF */
114 VFRES_NQSETS
= 2, /* # of "Queue Sets" per VF */
116 VFRES_NVI
= VFRES_NPORTS
, /* # of Virtual Interfaces */
117 VFRES_NETHCTRL
= VFRES_NQSETS
, /* # of EQs used for ETH or CTRL Qs */
118 VFRES_NIQFLINT
= VFRES_NQSETS
+2,/* # of ingress Qs/w Free List(s)/intr */
119 VFRES_NEQ
= VFRES_NQSETS
*2, /* # of egress queues */
120 VFRES_NIQ
= 0, /* # of non-fl/int ingress queues */
121 VFRES_TC
= 0, /* PCI-E traffic class */
122 VFRES_NEXACTF
= 16, /* # of exact MPS filters */
124 VFRES_R_CAPS
= FW_CMD_CAP_DMAQ
|FW_CMD_CAP_VF
|FW_CMD_CAP_PORT
,
125 VFRES_WX_CAPS
= FW_CMD_CAP_DMAQ
|FW_CMD_CAP_VF
,
130 * Provide a Port Access Rights Mask for the specified PF/VF. This is very
131 * static and likely not to be useful in the long run. We really need to
132 * implement some form of persistent configuration which the firmware
135 static unsigned int pfvfres_pmask(struct adapter
*adapter
,
136 unsigned int pf
, unsigned int vf
)
138 unsigned int portn
, portvec
;
141 * Give PF's access to all of the ports.
144 return FW_PFVF_CMD_PMASK_MASK
;
147 * For VFs, we'll assign them access to the ports based purely on the
148 * PF. We assign active ports in order, wrapping around if there are
149 * fewer active ports than PFs: e.g. active port[pf % nports].
150 * Unfortunately the adapter's port_info structs haven't been
151 * initialized yet so we have to compute this.
153 if (adapter
->params
.nports
== 0)
156 portn
= pf
% adapter
->params
.nports
;
157 portvec
= adapter
->params
.portvec
;
160 * Isolate the lowest set bit in the port vector. If we're at
161 * the port number that we want, return that as the pmask.
162 * otherwise mask that bit out of the port vector and
163 * decrement our port number ...
165 unsigned int pmask
= portvec
^ (portvec
& (portvec
-1));
175 MAX_TXQ_ENTRIES
= 16384,
176 MAX_CTRL_TXQ_ENTRIES
= 1024,
177 MAX_RSPQ_ENTRIES
= 16384,
178 MAX_RX_BUFFERS
= 16384,
179 MIN_TXQ_ENTRIES
= 32,
180 MIN_CTRL_TXQ_ENTRIES
= 32,
181 MIN_RSPQ_ENTRIES
= 128,
185 /* Host shadow copy of ingress filter entry. This is in host native format
186 * and doesn't match the ordering or bit order, etc. of the hardware of the
187 * firmware command. The use of bit-field structure elements is purely to
188 * remind ourselves of the field size limitations and save memory in the case
189 * where the filter table is large.
191 struct filter_entry
{
192 /* Administrative fields for filter.
194 u32 valid
:1; /* filter allocated and valid */
195 u32 locked
:1; /* filter is administratively locked */
197 u32 pending
:1; /* filter action is pending firmware reply */
198 u32 smtidx
:8; /* Source MAC Table index for smac */
199 struct l2t_entry
*l2t
; /* Layer Two Table entry for dmac */
201 /* The filter itself. Most of this is a straight copy of information
202 * provided by the extended ioctl(). Some fields are translated to
203 * internal forms -- for instance the Ingress Queue ID passed in from
204 * the ioctl() is translated into the Absolute Ingress Queue ID.
206 struct ch_filter_specification fs
;
209 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
210 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
211 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
213 #define CH_DEVICE(devid, data) { PCI_VDEVICE(CHELSIO, devid), (data) }
215 static const struct pci_device_id cxgb4_pci_tbl
[] = {
216 CH_DEVICE(0xa000, 0), /* PE10K */
217 CH_DEVICE(0x4001, -1),
218 CH_DEVICE(0x4002, -1),
219 CH_DEVICE(0x4003, -1),
220 CH_DEVICE(0x4004, -1),
221 CH_DEVICE(0x4005, -1),
222 CH_DEVICE(0x4006, -1),
223 CH_DEVICE(0x4007, -1),
224 CH_DEVICE(0x4008, -1),
225 CH_DEVICE(0x4009, -1),
226 CH_DEVICE(0x400a, -1),
227 CH_DEVICE(0x400d, -1),
228 CH_DEVICE(0x400e, -1),
229 CH_DEVICE(0x4080, -1),
230 CH_DEVICE(0x4081, -1),
231 CH_DEVICE(0x4082, -1),
232 CH_DEVICE(0x4083, -1),
233 CH_DEVICE(0x4084, -1),
234 CH_DEVICE(0x4085, -1),
235 CH_DEVICE(0x4086, -1),
236 CH_DEVICE(0x4087, -1),
237 CH_DEVICE(0x4088, -1),
238 CH_DEVICE(0x4401, 4),
239 CH_DEVICE(0x4402, 4),
240 CH_DEVICE(0x4403, 4),
241 CH_DEVICE(0x4404, 4),
242 CH_DEVICE(0x4405, 4),
243 CH_DEVICE(0x4406, 4),
244 CH_DEVICE(0x4407, 4),
245 CH_DEVICE(0x4408, 4),
246 CH_DEVICE(0x4409, 4),
247 CH_DEVICE(0x440a, 4),
248 CH_DEVICE(0x440d, 4),
249 CH_DEVICE(0x440e, 4),
250 CH_DEVICE(0x4480, 4),
251 CH_DEVICE(0x4481, 4),
252 CH_DEVICE(0x4482, 4),
253 CH_DEVICE(0x4483, 4),
254 CH_DEVICE(0x4484, 4),
255 CH_DEVICE(0x4485, 4),
256 CH_DEVICE(0x4486, 4),
257 CH_DEVICE(0x4487, 4),
258 CH_DEVICE(0x4488, 4),
259 CH_DEVICE(0x5001, 4),
260 CH_DEVICE(0x5002, 4),
261 CH_DEVICE(0x5003, 4),
262 CH_DEVICE(0x5004, 4),
263 CH_DEVICE(0x5005, 4),
264 CH_DEVICE(0x5006, 4),
265 CH_DEVICE(0x5007, 4),
266 CH_DEVICE(0x5008, 4),
267 CH_DEVICE(0x5009, 4),
268 CH_DEVICE(0x500A, 4),
269 CH_DEVICE(0x500B, 4),
270 CH_DEVICE(0x500C, 4),
271 CH_DEVICE(0x500D, 4),
272 CH_DEVICE(0x500E, 4),
273 CH_DEVICE(0x500F, 4),
274 CH_DEVICE(0x5010, 4),
275 CH_DEVICE(0x5011, 4),
276 CH_DEVICE(0x5012, 4),
277 CH_DEVICE(0x5013, 4),
278 CH_DEVICE(0x5014, 4),
279 CH_DEVICE(0x5015, 4),
280 CH_DEVICE(0x5080, 4),
281 CH_DEVICE(0x5081, 4),
282 CH_DEVICE(0x5082, 4),
283 CH_DEVICE(0x5083, 4),
284 CH_DEVICE(0x5084, 4),
285 CH_DEVICE(0x5085, 4),
286 CH_DEVICE(0x5401, 4),
287 CH_DEVICE(0x5402, 4),
288 CH_DEVICE(0x5403, 4),
289 CH_DEVICE(0x5404, 4),
290 CH_DEVICE(0x5405, 4),
291 CH_DEVICE(0x5406, 4),
292 CH_DEVICE(0x5407, 4),
293 CH_DEVICE(0x5408, 4),
294 CH_DEVICE(0x5409, 4),
295 CH_DEVICE(0x540A, 4),
296 CH_DEVICE(0x540B, 4),
297 CH_DEVICE(0x540C, 4),
298 CH_DEVICE(0x540D, 4),
299 CH_DEVICE(0x540E, 4),
300 CH_DEVICE(0x540F, 4),
301 CH_DEVICE(0x5410, 4),
302 CH_DEVICE(0x5411, 4),
303 CH_DEVICE(0x5412, 4),
304 CH_DEVICE(0x5413, 4),
305 CH_DEVICE(0x5414, 4),
306 CH_DEVICE(0x5415, 4),
307 CH_DEVICE(0x5480, 4),
308 CH_DEVICE(0x5481, 4),
309 CH_DEVICE(0x5482, 4),
310 CH_DEVICE(0x5483, 4),
311 CH_DEVICE(0x5484, 4),
312 CH_DEVICE(0x5485, 4),
316 #define FW4_FNAME "cxgb4/t4fw.bin"
317 #define FW5_FNAME "cxgb4/t5fw.bin"
318 #define FW4_CFNAME "cxgb4/t4-config.txt"
319 #define FW5_CFNAME "cxgb4/t5-config.txt"
321 MODULE_DESCRIPTION(DRV_DESC
);
322 MODULE_AUTHOR("Chelsio Communications");
323 MODULE_LICENSE("Dual BSD/GPL");
324 MODULE_VERSION(DRV_VERSION
);
325 MODULE_DEVICE_TABLE(pci
, cxgb4_pci_tbl
);
326 MODULE_FIRMWARE(FW4_FNAME
);
327 MODULE_FIRMWARE(FW5_FNAME
);
330 * Normally we're willing to become the firmware's Master PF but will be happy
331 * if another PF has already become the Master and initialized the adapter.
332 * Setting "force_init" will cause this driver to forcibly establish itself as
333 * the Master PF and initialize the adapter.
335 static uint force_init
;
337 module_param(force_init
, uint
, 0644);
338 MODULE_PARM_DESC(force_init
, "Forcibly become Master PF and initialize adapter");
341 * Normally if the firmware we connect to has Configuration File support, we
342 * use that and only fall back to the old Driver-based initialization if the
343 * Configuration File fails for some reason. If force_old_init is set, then
344 * we'll always use the old Driver-based initialization sequence.
346 static uint force_old_init
;
348 module_param(force_old_init
, uint
, 0644);
349 MODULE_PARM_DESC(force_old_init
, "Force old initialization sequence");
351 static int dflt_msg_enable
= DFLT_MSG_ENABLE
;
353 module_param(dflt_msg_enable
, int, 0644);
354 MODULE_PARM_DESC(dflt_msg_enable
, "Chelsio T4 default message enable bitmap");
357 * The driver uses the best interrupt scheme available on a platform in the
358 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
359 * of these schemes the driver may consider as follows:
361 * msi = 2: choose from among all three options
362 * msi = 1: only consider MSI and INTx interrupts
363 * msi = 0: force INTx interrupts
367 module_param(msi
, int, 0644);
368 MODULE_PARM_DESC(msi
, "whether to use INTx (0), MSI (1) or MSI-X (2)");
371 * Queue interrupt hold-off timer values. Queues default to the first of these
374 static unsigned int intr_holdoff
[SGE_NTIMERS
- 1] = { 5, 10, 20, 50, 100 };
376 module_param_array(intr_holdoff
, uint
, NULL
, 0644);
377 MODULE_PARM_DESC(intr_holdoff
, "values for queue interrupt hold-off timers "
378 "0..4 in microseconds");
380 static unsigned int intr_cnt
[SGE_NCOUNTERS
- 1] = { 4, 8, 16 };
382 module_param_array(intr_cnt
, uint
, NULL
, 0644);
383 MODULE_PARM_DESC(intr_cnt
,
384 "thresholds 1..3 for queue interrupt packet counters");
387 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
388 * offset by 2 bytes in order to have the IP headers line up on 4-byte
389 * boundaries. This is a requirement for many architectures which will throw
390 * a machine check fault if an attempt is made to access one of the 4-byte IP
391 * header fields on a non-4-byte boundary. And it's a major performance issue
392 * even on some architectures which allow it like some implementations of the
393 * x86 ISA. However, some architectures don't mind this and for some very
394 * edge-case performance sensitive applications (like forwarding large volumes
395 * of small packets), setting this DMA offset to 0 will decrease the number of
396 * PCI-E Bus transfers enough to measurably affect performance.
398 static int rx_dma_offset
= 2;
402 #ifdef CONFIG_PCI_IOV
403 module_param(vf_acls
, bool, 0644);
404 MODULE_PARM_DESC(vf_acls
, "if set enable virtualization L2 ACL enforcement");
406 /* Configure the number of PCI-E Virtual Function which are to be instantiated
407 * on SR-IOV Capable Physical Functions.
409 static unsigned int num_vf
[NUM_OF_PF_WITH_SRIOV
];
411 module_param_array(num_vf
, uint
, NULL
, 0644);
412 MODULE_PARM_DESC(num_vf
, "number of VFs for each of PFs 0-3");
415 /* TX Queue select used to determine what algorithm to use for selecting TX
416 * queue. Select between the kernel provided function (select_queue=0) or user
417 * cxgb_select_queue function (select_queue=1)
419 * Default: select_queue=0
421 static int select_queue
;
422 module_param(select_queue
, int, 0644);
423 MODULE_PARM_DESC(select_queue
,
424 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
427 * The filter TCAM has a fixed portion and a variable portion. The fixed
428 * portion can match on source/destination IP IPv4/IPv6 addresses and TCP/UDP
429 * ports. The variable portion is 36 bits which can include things like Exact
430 * Match MAC Index (9 bits), Ether Type (16 bits), IP Protocol (8 bits),
431 * [Inner] VLAN Tag (17 bits), etc. which, if all were somehow selected, would
432 * far exceed the 36-bit budget for this "compressed" header portion of the
433 * filter. Thus, we have a scarce resource which must be carefully managed.
435 * By default we set this up to mostly match the set of filter matching
436 * capabilities of T3 but with accommodations for some of T4's more
437 * interesting features:
439 * { IP Fragment (1), MPS Match Type (3), IP Protocol (8),
440 * [Inner] VLAN (17), Port (3), FCoE (1) }
443 TP_VLAN_PRI_MAP_DEFAULT
= HW_TPL_FR_MT_PR_IV_P_FC
,
444 TP_VLAN_PRI_MAP_FIRST
= FCOE_SHIFT
,
445 TP_VLAN_PRI_MAP_LAST
= FRAGMENTATION_SHIFT
,
448 static unsigned int tp_vlan_pri_map
= TP_VLAN_PRI_MAP_DEFAULT
;
450 module_param(tp_vlan_pri_map
, uint
, 0644);
451 MODULE_PARM_DESC(tp_vlan_pri_map
, "global compressed filter configuration");
453 static struct dentry
*cxgb4_debugfs_root
;
455 static LIST_HEAD(adapter_list
);
456 static DEFINE_MUTEX(uld_mutex
);
457 /* Adapter list to be accessed from atomic context */
458 static LIST_HEAD(adap_rcu_list
);
459 static DEFINE_SPINLOCK(adap_rcu_lock
);
460 static struct cxgb4_uld_info ulds
[CXGB4_ULD_MAX
];
461 static const char *uld_str
[] = { "RDMA", "iSCSI" };
463 static void link_report(struct net_device
*dev
)
465 if (!netif_carrier_ok(dev
))
466 netdev_info(dev
, "link down\n");
468 static const char *fc
[] = { "no", "Rx", "Tx", "Tx/Rx" };
470 const char *s
= "10Mbps";
471 const struct port_info
*p
= netdev_priv(dev
);
473 switch (p
->link_cfg
.speed
) {
488 netdev_info(dev
, "link up, %s, full-duplex, %s PAUSE\n", s
,
493 #ifdef CONFIG_CHELSIO_T4_DCB
494 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
495 static void dcb_tx_queue_prio_enable(struct net_device
*dev
, int enable
)
497 struct port_info
*pi
= netdev_priv(dev
);
498 struct adapter
*adap
= pi
->adapter
;
499 struct sge_eth_txq
*txq
= &adap
->sge
.ethtxq
[pi
->first_qset
];
502 /* We use a simple mapping of Port TX Queue Index to DCB
503 * Priority when we're enabling DCB.
505 for (i
= 0; i
< pi
->nqsets
; i
++, txq
++) {
509 name
= (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ
) |
510 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH
) |
511 FW_PARAMS_PARAM_YZ(txq
->q
.cntxt_id
));
512 value
= enable
? i
: 0xffffffff;
514 /* Since we can be called while atomic (from "interrupt
515 * level") we need to issue the Set Parameters Commannd
516 * without sleeping (timeout < 0).
518 err
= t4_set_params_nosleep(adap
, adap
->mbox
, adap
->fn
, 0, 1,
522 dev_err(adap
->pdev_dev
,
523 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
524 enable
? "set" : "unset", pi
->port_id
, i
, -err
);
526 txq
->dcb_prio
= value
;
529 #endif /* CONFIG_CHELSIO_T4_DCB */
531 void t4_os_link_changed(struct adapter
*adapter
, int port_id
, int link_stat
)
533 struct net_device
*dev
= adapter
->port
[port_id
];
535 /* Skip changes from disabled ports. */
536 if (netif_running(dev
) && link_stat
!= netif_carrier_ok(dev
)) {
538 netif_carrier_on(dev
);
540 #ifdef CONFIG_CHELSIO_T4_DCB
541 cxgb4_dcb_state_init(dev
);
542 dcb_tx_queue_prio_enable(dev
, false);
543 #endif /* CONFIG_CHELSIO_T4_DCB */
544 netif_carrier_off(dev
);
551 void t4_os_portmod_changed(const struct adapter
*adap
, int port_id
)
553 static const char *mod_str
[] = {
554 NULL
, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
557 const struct net_device
*dev
= adap
->port
[port_id
];
558 const struct port_info
*pi
= netdev_priv(dev
);
560 if (pi
->mod_type
== FW_PORT_MOD_TYPE_NONE
)
561 netdev_info(dev
, "port module unplugged\n");
562 else if (pi
->mod_type
< ARRAY_SIZE(mod_str
))
563 netdev_info(dev
, "%s module inserted\n", mod_str
[pi
->mod_type
]);
567 * Configure the exact and hash address filters to handle a port's multicast
568 * and secondary unicast MAC addresses.
570 static int set_addr_filters(const struct net_device
*dev
, bool sleep
)
578 const struct netdev_hw_addr
*ha
;
579 int uc_cnt
= netdev_uc_count(dev
);
580 int mc_cnt
= netdev_mc_count(dev
);
581 const struct port_info
*pi
= netdev_priv(dev
);
582 unsigned int mb
= pi
->adapter
->fn
;
584 /* first do the secondary unicast addresses */
585 netdev_for_each_uc_addr(ha
, dev
) {
586 addr
[naddr
++] = ha
->addr
;
587 if (--uc_cnt
== 0 || naddr
>= ARRAY_SIZE(addr
)) {
588 ret
= t4_alloc_mac_filt(pi
->adapter
, mb
, pi
->viid
, free
,
589 naddr
, addr
, filt_idx
, &uhash
, sleep
);
598 /* next set up the multicast addresses */
599 netdev_for_each_mc_addr(ha
, dev
) {
600 addr
[naddr
++] = ha
->addr
;
601 if (--mc_cnt
== 0 || naddr
>= ARRAY_SIZE(addr
)) {
602 ret
= t4_alloc_mac_filt(pi
->adapter
, mb
, pi
->viid
, free
,
603 naddr
, addr
, filt_idx
, &mhash
, sleep
);
612 return t4_set_addr_hash(pi
->adapter
, mb
, pi
->viid
, uhash
!= 0,
613 uhash
| mhash
, sleep
);
616 int dbfifo_int_thresh
= 10; /* 10 == 640 entry threshold */
617 module_param(dbfifo_int_thresh
, int, 0644);
618 MODULE_PARM_DESC(dbfifo_int_thresh
, "doorbell fifo interrupt threshold");
621 * usecs to sleep while draining the dbfifo
623 static int dbfifo_drain_delay
= 1000;
624 module_param(dbfifo_drain_delay
, int, 0644);
625 MODULE_PARM_DESC(dbfifo_drain_delay
,
626 "usecs to sleep while draining the dbfifo");
629 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
630 * If @mtu is -1 it is left unchanged.
632 static int set_rxmode(struct net_device
*dev
, int mtu
, bool sleep_ok
)
635 struct port_info
*pi
= netdev_priv(dev
);
637 ret
= set_addr_filters(dev
, sleep_ok
);
639 ret
= t4_set_rxmode(pi
->adapter
, pi
->adapter
->fn
, pi
->viid
, mtu
,
640 (dev
->flags
& IFF_PROMISC
) ? 1 : 0,
641 (dev
->flags
& IFF_ALLMULTI
) ? 1 : 0, 1, -1,
647 * link_start - enable a port
648 * @dev: the port to enable
650 * Performs the MAC and PHY actions needed to enable a port.
652 static int link_start(struct net_device
*dev
)
655 struct port_info
*pi
= netdev_priv(dev
);
656 unsigned int mb
= pi
->adapter
->fn
;
659 * We do not set address filters and promiscuity here, the stack does
660 * that step explicitly.
662 ret
= t4_set_rxmode(pi
->adapter
, mb
, pi
->viid
, dev
->mtu
, -1, -1, -1,
663 !!(dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
), true);
665 ret
= t4_change_mac(pi
->adapter
, mb
, pi
->viid
,
666 pi
->xact_addr_filt
, dev
->dev_addr
, true,
669 pi
->xact_addr_filt
= ret
;
674 ret
= t4_link_start(pi
->adapter
, mb
, pi
->tx_chan
,
678 ret
= t4_enable_vi_params(pi
->adapter
, mb
, pi
->viid
, true,
679 true, CXGB4_DCB_ENABLED
);
686 int cxgb4_dcb_enabled(const struct net_device
*dev
)
688 #ifdef CONFIG_CHELSIO_T4_DCB
689 struct port_info
*pi
= netdev_priv(dev
);
691 return pi
->dcb
.state
== CXGB4_DCB_STATE_FW_ALLSYNCED
;
696 EXPORT_SYMBOL(cxgb4_dcb_enabled
);
698 #ifdef CONFIG_CHELSIO_T4_DCB
699 /* Handle a Data Center Bridging update message from the firmware. */
700 static void dcb_rpl(struct adapter
*adap
, const struct fw_port_cmd
*pcmd
)
702 int port
= FW_PORT_CMD_PORTID_GET(ntohl(pcmd
->op_to_portid
));
703 struct net_device
*dev
= adap
->port
[port
];
704 int old_dcb_enabled
= cxgb4_dcb_enabled(dev
);
707 cxgb4_dcb_handle_fw_update(adap
, pcmd
);
708 new_dcb_enabled
= cxgb4_dcb_enabled(dev
);
710 /* If the DCB has become enabled or disabled on the port then we're
711 * going to need to set up/tear down DCB Priority parameters for the
712 * TX Queues associated with the port.
714 if (new_dcb_enabled
!= old_dcb_enabled
)
715 dcb_tx_queue_prio_enable(dev
, new_dcb_enabled
);
717 #endif /* CONFIG_CHELSIO_T4_DCB */
719 /* Clear a filter and release any of its resources that we own. This also
720 * clears the filter's "pending" status.
722 static void clear_filter(struct adapter
*adap
, struct filter_entry
*f
)
724 /* If the new or old filter have loopback rewriteing rules then we'll
725 * need to free any existing Layer Two Table (L2T) entries of the old
726 * filter rule. The firmware will handle freeing up any Source MAC
727 * Table (SMT) entries used for rewriting Source MAC Addresses in
731 cxgb4_l2t_release(f
->l2t
);
733 /* The zeroing of the filter rule below clears the filter valid,
734 * pending, locked flags, l2t pointer, etc. so it's all we need for
737 memset(f
, 0, sizeof(*f
));
740 /* Handle a filter write/deletion reply.
742 static void filter_rpl(struct adapter
*adap
, const struct cpl_set_tcb_rpl
*rpl
)
744 unsigned int idx
= GET_TID(rpl
);
745 unsigned int nidx
= idx
- adap
->tids
.ftid_base
;
747 struct filter_entry
*f
;
749 if (idx
>= adap
->tids
.ftid_base
&& nidx
<
750 (adap
->tids
.nftids
+ adap
->tids
.nsftids
)) {
752 ret
= GET_TCB_COOKIE(rpl
->cookie
);
753 f
= &adap
->tids
.ftid_tab
[idx
];
755 if (ret
== FW_FILTER_WR_FLT_DELETED
) {
756 /* Clear the filter when we get confirmation from the
757 * hardware that the filter has been deleted.
759 clear_filter(adap
, f
);
760 } else if (ret
== FW_FILTER_WR_SMT_TBL_FULL
) {
761 dev_err(adap
->pdev_dev
, "filter %u setup failed due to full SMT\n",
763 clear_filter(adap
, f
);
764 } else if (ret
== FW_FILTER_WR_FLT_ADDED
) {
765 f
->smtidx
= (be64_to_cpu(rpl
->oldval
) >> 24) & 0xff;
766 f
->pending
= 0; /* asynchronous setup completed */
769 /* Something went wrong. Issue a warning about the
770 * problem and clear everything out.
772 dev_err(adap
->pdev_dev
, "filter %u setup failed with error %u\n",
774 clear_filter(adap
, f
);
779 /* Response queue handler for the FW event queue.
781 static int fwevtq_handler(struct sge_rspq
*q
, const __be64
*rsp
,
782 const struct pkt_gl
*gl
)
784 u8 opcode
= ((const struct rss_header
*)rsp
)->opcode
;
786 rsp
++; /* skip RSS header */
788 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
790 if (unlikely(opcode
== CPL_FW4_MSG
&&
791 ((const struct cpl_fw4_msg
*)rsp
)->type
== FW_TYPE_RSSCPL
)) {
793 opcode
= ((const struct rss_header
*)rsp
)->opcode
;
795 if (opcode
!= CPL_SGE_EGR_UPDATE
) {
796 dev_err(q
->adap
->pdev_dev
, "unexpected FW4/CPL %#x on FW event queue\n"
802 if (likely(opcode
== CPL_SGE_EGR_UPDATE
)) {
803 const struct cpl_sge_egr_update
*p
= (void *)rsp
;
804 unsigned int qid
= EGR_QID(ntohl(p
->opcode_qid
));
807 txq
= q
->adap
->sge
.egr_map
[qid
- q
->adap
->sge
.egr_start
];
809 if ((u8
*)txq
< (u8
*)q
->adap
->sge
.ofldtxq
) {
810 struct sge_eth_txq
*eq
;
812 eq
= container_of(txq
, struct sge_eth_txq
, q
);
813 netif_tx_wake_queue(eq
->txq
);
815 struct sge_ofld_txq
*oq
;
817 oq
= container_of(txq
, struct sge_ofld_txq
, q
);
818 tasklet_schedule(&oq
->qresume_tsk
);
820 } else if (opcode
== CPL_FW6_MSG
|| opcode
== CPL_FW4_MSG
) {
821 const struct cpl_fw6_msg
*p
= (void *)rsp
;
823 #ifdef CONFIG_CHELSIO_T4_DCB
824 const struct fw_port_cmd
*pcmd
= (const void *)p
->data
;
825 unsigned int cmd
= FW_CMD_OP_GET(ntohl(pcmd
->op_to_portid
));
826 unsigned int action
=
827 FW_PORT_CMD_ACTION_GET(ntohl(pcmd
->action_to_len16
));
829 if (cmd
== FW_PORT_CMD
&&
830 action
== FW_PORT_ACTION_GET_PORT_INFO
) {
831 int port
= FW_PORT_CMD_PORTID_GET(
832 be32_to_cpu(pcmd
->op_to_portid
));
833 struct net_device
*dev
= q
->adap
->port
[port
];
834 int state_input
= ((pcmd
->u
.info
.dcbxdis_pkd
&
836 ? CXGB4_DCB_INPUT_FW_DISABLED
837 : CXGB4_DCB_INPUT_FW_ENABLED
);
839 cxgb4_dcb_state_fsm(dev
, state_input
);
842 if (cmd
== FW_PORT_CMD
&&
843 action
== FW_PORT_ACTION_L2_DCB_CFG
)
844 dcb_rpl(q
->adap
, pcmd
);
848 t4_handle_fw_rpl(q
->adap
, p
->data
);
849 } else if (opcode
== CPL_L2T_WRITE_RPL
) {
850 const struct cpl_l2t_write_rpl
*p
= (void *)rsp
;
852 do_l2t_write_rpl(q
->adap
, p
);
853 } else if (opcode
== CPL_SET_TCB_RPL
) {
854 const struct cpl_set_tcb_rpl
*p
= (void *)rsp
;
856 filter_rpl(q
->adap
, p
);
858 dev_err(q
->adap
->pdev_dev
,
859 "unexpected CPL %#x on FW event queue\n", opcode
);
865 * uldrx_handler - response queue handler for ULD queues
866 * @q: the response queue that received the packet
867 * @rsp: the response queue descriptor holding the offload message
868 * @gl: the gather list of packet fragments
870 * Deliver an ingress offload packet to a ULD. All processing is done by
871 * the ULD, we just maintain statistics.
873 static int uldrx_handler(struct sge_rspq
*q
, const __be64
*rsp
,
874 const struct pkt_gl
*gl
)
876 struct sge_ofld_rxq
*rxq
= container_of(q
, struct sge_ofld_rxq
, rspq
);
878 /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
880 if (((const struct rss_header
*)rsp
)->opcode
== CPL_FW4_MSG
&&
881 ((const struct cpl_fw4_msg
*)(rsp
+ 1))->type
== FW_TYPE_RSSCPL
)
884 if (ulds
[q
->uld
].rx_handler(q
->adap
->uld_handle
[q
->uld
], rsp
, gl
)) {
890 else if (gl
== CXGB4_MSG_AN
)
897 static void disable_msi(struct adapter
*adapter
)
899 if (adapter
->flags
& USING_MSIX
) {
900 pci_disable_msix(adapter
->pdev
);
901 adapter
->flags
&= ~USING_MSIX
;
902 } else if (adapter
->flags
& USING_MSI
) {
903 pci_disable_msi(adapter
->pdev
);
904 adapter
->flags
&= ~USING_MSI
;
909 * Interrupt handler for non-data events used with MSI-X.
911 static irqreturn_t
t4_nondata_intr(int irq
, void *cookie
)
913 struct adapter
*adap
= cookie
;
915 u32 v
= t4_read_reg(adap
, MYPF_REG(PL_PF_INT_CAUSE
));
918 t4_write_reg(adap
, MYPF_REG(PL_PF_INT_CAUSE
), v
);
920 t4_slow_intr_handler(adap
);
925 * Name the MSI-X interrupts.
927 static void name_msix_vecs(struct adapter
*adap
)
929 int i
, j
, msi_idx
= 2, n
= sizeof(adap
->msix_info
[0].desc
);
931 /* non-data interrupts */
932 snprintf(adap
->msix_info
[0].desc
, n
, "%s", adap
->port
[0]->name
);
935 snprintf(adap
->msix_info
[1].desc
, n
, "%s-FWeventq",
936 adap
->port
[0]->name
);
938 /* Ethernet queues */
939 for_each_port(adap
, j
) {
940 struct net_device
*d
= adap
->port
[j
];
941 const struct port_info
*pi
= netdev_priv(d
);
943 for (i
= 0; i
< pi
->nqsets
; i
++, msi_idx
++)
944 snprintf(adap
->msix_info
[msi_idx
].desc
, n
, "%s-Rx%d",
949 for_each_ofldrxq(&adap
->sge
, i
)
950 snprintf(adap
->msix_info
[msi_idx
++].desc
, n
, "%s-ofld%d",
951 adap
->port
[0]->name
, i
);
953 for_each_rdmarxq(&adap
->sge
, i
)
954 snprintf(adap
->msix_info
[msi_idx
++].desc
, n
, "%s-rdma%d",
955 adap
->port
[0]->name
, i
);
957 for_each_rdmaciq(&adap
->sge
, i
)
958 snprintf(adap
->msix_info
[msi_idx
++].desc
, n
, "%s-rdma-ciq%d",
959 adap
->port
[0]->name
, i
);
962 static int request_msix_queue_irqs(struct adapter
*adap
)
964 struct sge
*s
= &adap
->sge
;
965 int err
, ethqidx
, ofldqidx
= 0, rdmaqidx
= 0, rdmaciqqidx
= 0;
968 err
= request_irq(adap
->msix_info
[1].vec
, t4_sge_intr_msix
, 0,
969 adap
->msix_info
[1].desc
, &s
->fw_evtq
);
973 for_each_ethrxq(s
, ethqidx
) {
974 err
= request_irq(adap
->msix_info
[msi_index
].vec
,
976 adap
->msix_info
[msi_index
].desc
,
977 &s
->ethrxq
[ethqidx
].rspq
);
982 for_each_ofldrxq(s
, ofldqidx
) {
983 err
= request_irq(adap
->msix_info
[msi_index
].vec
,
985 adap
->msix_info
[msi_index
].desc
,
986 &s
->ofldrxq
[ofldqidx
].rspq
);
991 for_each_rdmarxq(s
, rdmaqidx
) {
992 err
= request_irq(adap
->msix_info
[msi_index
].vec
,
994 adap
->msix_info
[msi_index
].desc
,
995 &s
->rdmarxq
[rdmaqidx
].rspq
);
1000 for_each_rdmaciq(s
, rdmaciqqidx
) {
1001 err
= request_irq(adap
->msix_info
[msi_index
].vec
,
1002 t4_sge_intr_msix
, 0,
1003 adap
->msix_info
[msi_index
].desc
,
1004 &s
->rdmaciq
[rdmaciqqidx
].rspq
);
1012 while (--rdmaciqqidx
>= 0)
1013 free_irq(adap
->msix_info
[--msi_index
].vec
,
1014 &s
->rdmaciq
[rdmaciqqidx
].rspq
);
1015 while (--rdmaqidx
>= 0)
1016 free_irq(adap
->msix_info
[--msi_index
].vec
,
1017 &s
->rdmarxq
[rdmaqidx
].rspq
);
1018 while (--ofldqidx
>= 0)
1019 free_irq(adap
->msix_info
[--msi_index
].vec
,
1020 &s
->ofldrxq
[ofldqidx
].rspq
);
1021 while (--ethqidx
>= 0)
1022 free_irq(adap
->msix_info
[--msi_index
].vec
,
1023 &s
->ethrxq
[ethqidx
].rspq
);
1024 free_irq(adap
->msix_info
[1].vec
, &s
->fw_evtq
);
1028 static void free_msix_queue_irqs(struct adapter
*adap
)
1030 int i
, msi_index
= 2;
1031 struct sge
*s
= &adap
->sge
;
1033 free_irq(adap
->msix_info
[1].vec
, &s
->fw_evtq
);
1034 for_each_ethrxq(s
, i
)
1035 free_irq(adap
->msix_info
[msi_index
++].vec
, &s
->ethrxq
[i
].rspq
);
1036 for_each_ofldrxq(s
, i
)
1037 free_irq(adap
->msix_info
[msi_index
++].vec
, &s
->ofldrxq
[i
].rspq
);
1038 for_each_rdmarxq(s
, i
)
1039 free_irq(adap
->msix_info
[msi_index
++].vec
, &s
->rdmarxq
[i
].rspq
);
1040 for_each_rdmaciq(s
, i
)
1041 free_irq(adap
->msix_info
[msi_index
++].vec
, &s
->rdmaciq
[i
].rspq
);
1045 * write_rss - write the RSS table for a given port
1047 * @queues: array of queue indices for RSS
1049 * Sets up the portion of the HW RSS table for the port's VI to distribute
1050 * packets to the Rx queues in @queues.
1052 static int write_rss(const struct port_info
*pi
, const u16
*queues
)
1056 const struct sge_eth_rxq
*q
= &pi
->adapter
->sge
.ethrxq
[pi
->first_qset
];
1058 rss
= kmalloc(pi
->rss_size
* sizeof(u16
), GFP_KERNEL
);
1062 /* map the queue indices to queue ids */
1063 for (i
= 0; i
< pi
->rss_size
; i
++, queues
++)
1064 rss
[i
] = q
[*queues
].rspq
.abs_id
;
1066 err
= t4_config_rss_range(pi
->adapter
, pi
->adapter
->fn
, pi
->viid
, 0,
1067 pi
->rss_size
, rss
, pi
->rss_size
);
1073 * setup_rss - configure RSS
1074 * @adap: the adapter
1076 * Sets up RSS for each port.
1078 static int setup_rss(struct adapter
*adap
)
1082 for_each_port(adap
, i
) {
1083 const struct port_info
*pi
= adap2pinfo(adap
, i
);
1085 err
= write_rss(pi
, pi
->rss
);
1093 * Return the channel of the ingress queue with the given qid.
1095 static unsigned int rxq_to_chan(const struct sge
*p
, unsigned int qid
)
1097 qid
-= p
->ingr_start
;
1098 return netdev2pinfo(p
->ingr_map
[qid
]->netdev
)->tx_chan
;
1102 * Wait until all NAPI handlers are descheduled.
1104 static void quiesce_rx(struct adapter
*adap
)
1108 for (i
= 0; i
< ARRAY_SIZE(adap
->sge
.ingr_map
); i
++) {
1109 struct sge_rspq
*q
= adap
->sge
.ingr_map
[i
];
1111 if (q
&& q
->handler
)
1112 napi_disable(&q
->napi
);
1117 * Enable NAPI scheduling and interrupt generation for all Rx queues.
1119 static void enable_rx(struct adapter
*adap
)
1123 for (i
= 0; i
< ARRAY_SIZE(adap
->sge
.ingr_map
); i
++) {
1124 struct sge_rspq
*q
= adap
->sge
.ingr_map
[i
];
1129 napi_enable(&q
->napi
);
1130 /* 0-increment GTS to start the timer and enable interrupts */
1131 t4_write_reg(adap
, MYPF_REG(SGE_PF_GTS
),
1132 SEINTARM(q
->intr_params
) |
1133 INGRESSQID(q
->cntxt_id
));
1138 * setup_sge_queues - configure SGE Tx/Rx/response queues
1139 * @adap: the adapter
1141 * Determines how many sets of SGE queues to use and initializes them.
1142 * We support multiple queue sets per port if we have MSI-X, otherwise
1143 * just one queue set per port.
1145 static int setup_sge_queues(struct adapter
*adap
)
1147 int err
, msi_idx
, i
, j
;
1148 struct sge
*s
= &adap
->sge
;
1150 bitmap_zero(s
->starving_fl
, MAX_EGRQ
);
1151 bitmap_zero(s
->txq_maperr
, MAX_EGRQ
);
1153 if (adap
->flags
& USING_MSIX
)
1154 msi_idx
= 1; /* vector 0 is for non-queue interrupts */
1156 err
= t4_sge_alloc_rxq(adap
, &s
->intrq
, false, adap
->port
[0], 0,
1160 msi_idx
= -((int)s
->intrq
.abs_id
+ 1);
1163 err
= t4_sge_alloc_rxq(adap
, &s
->fw_evtq
, true, adap
->port
[0],
1164 msi_idx
, NULL
, fwevtq_handler
);
1166 freeout
: t4_free_sge_resources(adap
);
1170 for_each_port(adap
, i
) {
1171 struct net_device
*dev
= adap
->port
[i
];
1172 struct port_info
*pi
= netdev_priv(dev
);
1173 struct sge_eth_rxq
*q
= &s
->ethrxq
[pi
->first_qset
];
1174 struct sge_eth_txq
*t
= &s
->ethtxq
[pi
->first_qset
];
1176 for (j
= 0; j
< pi
->nqsets
; j
++, q
++) {
1179 err
= t4_sge_alloc_rxq(adap
, &q
->rspq
, false, dev
,
1185 memset(&q
->stats
, 0, sizeof(q
->stats
));
1187 for (j
= 0; j
< pi
->nqsets
; j
++, t
++) {
1188 err
= t4_sge_alloc_eth_txq(adap
, t
, dev
,
1189 netdev_get_tx_queue(dev
, j
),
1190 s
->fw_evtq
.cntxt_id
);
1196 j
= s
->ofldqsets
/ adap
->params
.nports
; /* ofld queues per channel */
1197 for_each_ofldrxq(s
, i
) {
1198 struct sge_ofld_rxq
*q
= &s
->ofldrxq
[i
];
1199 struct net_device
*dev
= adap
->port
[i
/ j
];
1203 err
= t4_sge_alloc_rxq(adap
, &q
->rspq
, false, dev
, msi_idx
,
1204 q
->fl
.size
? &q
->fl
: NULL
,
1208 memset(&q
->stats
, 0, sizeof(q
->stats
));
1209 s
->ofld_rxq
[i
] = q
->rspq
.abs_id
;
1210 err
= t4_sge_alloc_ofld_txq(adap
, &s
->ofldtxq
[i
], dev
,
1211 s
->fw_evtq
.cntxt_id
);
1216 for_each_rdmarxq(s
, i
) {
1217 struct sge_ofld_rxq
*q
= &s
->rdmarxq
[i
];
1221 err
= t4_sge_alloc_rxq(adap
, &q
->rspq
, false, adap
->port
[i
],
1222 msi_idx
, q
->fl
.size
? &q
->fl
: NULL
,
1226 memset(&q
->stats
, 0, sizeof(q
->stats
));
1227 s
->rdma_rxq
[i
] = q
->rspq
.abs_id
;
1230 for_each_rdmaciq(s
, i
) {
1231 struct sge_ofld_rxq
*q
= &s
->rdmaciq
[i
];
1235 err
= t4_sge_alloc_rxq(adap
, &q
->rspq
, false, adap
->port
[i
],
1236 msi_idx
, q
->fl
.size
? &q
->fl
: NULL
,
1240 memset(&q
->stats
, 0, sizeof(q
->stats
));
1241 s
->rdma_ciq
[i
] = q
->rspq
.abs_id
;
1244 for_each_port(adap
, i
) {
1246 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1247 * have RDMA queues, and that's the right value.
1249 err
= t4_sge_alloc_ctrl_txq(adap
, &s
->ctrlq
[i
], adap
->port
[i
],
1250 s
->fw_evtq
.cntxt_id
,
1251 s
->rdmarxq
[i
].rspq
.cntxt_id
);
1256 t4_write_reg(adap
, is_t4(adap
->params
.chip
) ?
1257 MPS_TRC_RSS_CONTROL
:
1258 MPS_T5_TRC_RSS_CONTROL
,
1259 RSSCONTROL(netdev2pinfo(adap
->port
[0])->tx_chan
) |
1260 QUEUENUMBER(s
->ethrxq
[0].rspq
.abs_id
));
1265 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1266 * The allocated memory is cleared.
1268 void *t4_alloc_mem(size_t size
)
1270 void *p
= kzalloc(size
, GFP_KERNEL
| __GFP_NOWARN
);
1278 * Free memory allocated through alloc_mem().
1280 static void t4_free_mem(void *addr
)
1282 if (is_vmalloc_addr(addr
))
1288 /* Send a Work Request to write the filter at a specified index. We construct
1289 * a Firmware Filter Work Request to have the work done and put the indicated
1290 * filter into "pending" mode which will prevent any further actions against
1291 * it till we get a reply from the firmware on the completion status of the
1294 static int set_filter_wr(struct adapter
*adapter
, int fidx
)
1296 struct filter_entry
*f
= &adapter
->tids
.ftid_tab
[fidx
];
1297 struct sk_buff
*skb
;
1298 struct fw_filter_wr
*fwr
;
1301 /* If the new filter requires loopback Destination MAC and/or VLAN
1302 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1305 if (f
->fs
.newdmac
|| f
->fs
.newvlan
) {
1306 /* allocate L2T entry for new filter */
1307 f
->l2t
= t4_l2t_alloc_switching(adapter
->l2t
);
1310 if (t4_l2t_set_switching(adapter
, f
->l2t
, f
->fs
.vlan
,
1311 f
->fs
.eport
, f
->fs
.dmac
)) {
1312 cxgb4_l2t_release(f
->l2t
);
1318 ftid
= adapter
->tids
.ftid_base
+ fidx
;
1320 skb
= alloc_skb(sizeof(*fwr
), GFP_KERNEL
| __GFP_NOFAIL
);
1321 fwr
= (struct fw_filter_wr
*)__skb_put(skb
, sizeof(*fwr
));
1322 memset(fwr
, 0, sizeof(*fwr
));
1324 /* It would be nice to put most of the following in t4_hw.c but most
1325 * of the work is translating the cxgbtool ch_filter_specification
1326 * into the Work Request and the definition of that structure is
1327 * currently in cxgbtool.h which isn't appropriate to pull into the
1328 * common code. We may eventually try to come up with a more neutral
1329 * filter specification structure but for now it's easiest to simply
1330 * put this fairly direct code in line ...
1332 fwr
->op_pkd
= htonl(FW_WR_OP(FW_FILTER_WR
));
1333 fwr
->len16_pkd
= htonl(FW_WR_LEN16(sizeof(*fwr
)/16));
1335 htonl(V_FW_FILTER_WR_TID(ftid
) |
1336 V_FW_FILTER_WR_RQTYPE(f
->fs
.type
) |
1337 V_FW_FILTER_WR_NOREPLY(0) |
1338 V_FW_FILTER_WR_IQ(f
->fs
.iq
));
1339 fwr
->del_filter_to_l2tix
=
1340 htonl(V_FW_FILTER_WR_RPTTID(f
->fs
.rpttid
) |
1341 V_FW_FILTER_WR_DROP(f
->fs
.action
== FILTER_DROP
) |
1342 V_FW_FILTER_WR_DIRSTEER(f
->fs
.dirsteer
) |
1343 V_FW_FILTER_WR_MASKHASH(f
->fs
.maskhash
) |
1344 V_FW_FILTER_WR_DIRSTEERHASH(f
->fs
.dirsteerhash
) |
1345 V_FW_FILTER_WR_LPBK(f
->fs
.action
== FILTER_SWITCH
) |
1346 V_FW_FILTER_WR_DMAC(f
->fs
.newdmac
) |
1347 V_FW_FILTER_WR_SMAC(f
->fs
.newsmac
) |
1348 V_FW_FILTER_WR_INSVLAN(f
->fs
.newvlan
== VLAN_INSERT
||
1349 f
->fs
.newvlan
== VLAN_REWRITE
) |
1350 V_FW_FILTER_WR_RMVLAN(f
->fs
.newvlan
== VLAN_REMOVE
||
1351 f
->fs
.newvlan
== VLAN_REWRITE
) |
1352 V_FW_FILTER_WR_HITCNTS(f
->fs
.hitcnts
) |
1353 V_FW_FILTER_WR_TXCHAN(f
->fs
.eport
) |
1354 V_FW_FILTER_WR_PRIO(f
->fs
.prio
) |
1355 V_FW_FILTER_WR_L2TIX(f
->l2t
? f
->l2t
->idx
: 0));
1356 fwr
->ethtype
= htons(f
->fs
.val
.ethtype
);
1357 fwr
->ethtypem
= htons(f
->fs
.mask
.ethtype
);
1358 fwr
->frag_to_ovlan_vldm
=
1359 (V_FW_FILTER_WR_FRAG(f
->fs
.val
.frag
) |
1360 V_FW_FILTER_WR_FRAGM(f
->fs
.mask
.frag
) |
1361 V_FW_FILTER_WR_IVLAN_VLD(f
->fs
.val
.ivlan_vld
) |
1362 V_FW_FILTER_WR_OVLAN_VLD(f
->fs
.val
.ovlan_vld
) |
1363 V_FW_FILTER_WR_IVLAN_VLDM(f
->fs
.mask
.ivlan_vld
) |
1364 V_FW_FILTER_WR_OVLAN_VLDM(f
->fs
.mask
.ovlan_vld
));
1366 fwr
->rx_chan_rx_rpl_iq
=
1367 htons(V_FW_FILTER_WR_RX_CHAN(0) |
1368 V_FW_FILTER_WR_RX_RPL_IQ(adapter
->sge
.fw_evtq
.abs_id
));
1369 fwr
->maci_to_matchtypem
=
1370 htonl(V_FW_FILTER_WR_MACI(f
->fs
.val
.macidx
) |
1371 V_FW_FILTER_WR_MACIM(f
->fs
.mask
.macidx
) |
1372 V_FW_FILTER_WR_FCOE(f
->fs
.val
.fcoe
) |
1373 V_FW_FILTER_WR_FCOEM(f
->fs
.mask
.fcoe
) |
1374 V_FW_FILTER_WR_PORT(f
->fs
.val
.iport
) |
1375 V_FW_FILTER_WR_PORTM(f
->fs
.mask
.iport
) |
1376 V_FW_FILTER_WR_MATCHTYPE(f
->fs
.val
.matchtype
) |
1377 V_FW_FILTER_WR_MATCHTYPEM(f
->fs
.mask
.matchtype
));
1378 fwr
->ptcl
= f
->fs
.val
.proto
;
1379 fwr
->ptclm
= f
->fs
.mask
.proto
;
1380 fwr
->ttyp
= f
->fs
.val
.tos
;
1381 fwr
->ttypm
= f
->fs
.mask
.tos
;
1382 fwr
->ivlan
= htons(f
->fs
.val
.ivlan
);
1383 fwr
->ivlanm
= htons(f
->fs
.mask
.ivlan
);
1384 fwr
->ovlan
= htons(f
->fs
.val
.ovlan
);
1385 fwr
->ovlanm
= htons(f
->fs
.mask
.ovlan
);
1386 memcpy(fwr
->lip
, f
->fs
.val
.lip
, sizeof(fwr
->lip
));
1387 memcpy(fwr
->lipm
, f
->fs
.mask
.lip
, sizeof(fwr
->lipm
));
1388 memcpy(fwr
->fip
, f
->fs
.val
.fip
, sizeof(fwr
->fip
));
1389 memcpy(fwr
->fipm
, f
->fs
.mask
.fip
, sizeof(fwr
->fipm
));
1390 fwr
->lp
= htons(f
->fs
.val
.lport
);
1391 fwr
->lpm
= htons(f
->fs
.mask
.lport
);
1392 fwr
->fp
= htons(f
->fs
.val
.fport
);
1393 fwr
->fpm
= htons(f
->fs
.mask
.fport
);
1395 memcpy(fwr
->sma
, f
->fs
.smac
, sizeof(fwr
->sma
));
1397 /* Mark the filter as "pending" and ship off the Filter Work Request.
1398 * When we get the Work Request Reply we'll clear the pending status.
1401 set_wr_txq(skb
, CPL_PRIORITY_CONTROL
, f
->fs
.val
.iport
& 0x3);
1402 t4_ofld_send(adapter
, skb
);
1406 /* Delete the filter at a specified index.
1408 static int del_filter_wr(struct adapter
*adapter
, int fidx
)
1410 struct filter_entry
*f
= &adapter
->tids
.ftid_tab
[fidx
];
1411 struct sk_buff
*skb
;
1412 struct fw_filter_wr
*fwr
;
1413 unsigned int len
, ftid
;
1416 ftid
= adapter
->tids
.ftid_base
+ fidx
;
1418 skb
= alloc_skb(len
, GFP_KERNEL
| __GFP_NOFAIL
);
1419 fwr
= (struct fw_filter_wr
*)__skb_put(skb
, len
);
1420 t4_mk_filtdelwr(ftid
, fwr
, adapter
->sge
.fw_evtq
.abs_id
);
1422 /* Mark the filter as "pending" and ship off the Filter Work Request.
1423 * When we get the Work Request Reply we'll clear the pending status.
1426 t4_mgmt_tx(adapter
, skb
);
1430 static u16
cxgb_select_queue(struct net_device
*dev
, struct sk_buff
*skb
,
1431 void *accel_priv
, select_queue_fallback_t fallback
)
1435 #ifdef CONFIG_CHELSIO_T4_DCB
1436 /* If a Data Center Bridging has been successfully negotiated on this
1437 * link then we'll use the skb's priority to map it to a TX Queue.
1438 * The skb's priority is determined via the VLAN Tag Priority Code
1441 if (cxgb4_dcb_enabled(dev
)) {
1445 err
= vlan_get_tag(skb
, &vlan_tci
);
1446 if (unlikely(err
)) {
1447 if (net_ratelimit())
1449 "TX Packet without VLAN Tag on DCB Link\n");
1452 txq
= (vlan_tci
& VLAN_PRIO_MASK
) >> VLAN_PRIO_SHIFT
;
1456 #endif /* CONFIG_CHELSIO_T4_DCB */
1459 txq
= (skb_rx_queue_recorded(skb
)
1460 ? skb_get_rx_queue(skb
)
1461 : smp_processor_id());
1463 while (unlikely(txq
>= dev
->real_num_tx_queues
))
1464 txq
-= dev
->real_num_tx_queues
;
1469 return fallback(dev
, skb
) % dev
->real_num_tx_queues
;
1472 static inline int is_offload(const struct adapter
*adap
)
1474 return adap
->params
.offload
;
1478 * Implementation of ethtool operations.
1481 static u32
get_msglevel(struct net_device
*dev
)
1483 return netdev2adap(dev
)->msg_enable
;
1486 static void set_msglevel(struct net_device
*dev
, u32 val
)
1488 netdev2adap(dev
)->msg_enable
= val
;
1491 static char stats_strings
[][ETH_GSTRING_LEN
] = {
1494 "TxBroadcastFrames ",
1495 "TxMulticastFrames ",
1501 "TxFrames128To255 ",
1502 "TxFrames256To511 ",
1503 "TxFrames512To1023 ",
1504 "TxFrames1024To1518 ",
1505 "TxFrames1519ToMax ",
1520 "RxBroadcastFrames ",
1521 "RxMulticastFrames ",
1533 "RxFrames128To255 ",
1534 "RxFrames256To511 ",
1535 "RxFrames512To1023 ",
1536 "RxFrames1024To1518 ",
1537 "RxFrames1519ToMax ",
1549 "RxBG0FramesDropped ",
1550 "RxBG1FramesDropped ",
1551 "RxBG2FramesDropped ",
1552 "RxBG3FramesDropped ",
1553 "RxBG0FramesTrunc ",
1554 "RxBG1FramesTrunc ",
1555 "RxBG2FramesTrunc ",
1556 "RxBG3FramesTrunc ",
1565 "WriteCoalSuccess ",
1569 static int get_sset_count(struct net_device
*dev
, int sset
)
1573 return ARRAY_SIZE(stats_strings
);
1579 #define T4_REGMAP_SIZE (160 * 1024)
1580 #define T5_REGMAP_SIZE (332 * 1024)
1582 static int get_regs_len(struct net_device
*dev
)
1584 struct adapter
*adap
= netdev2adap(dev
);
1585 if (is_t4(adap
->params
.chip
))
1586 return T4_REGMAP_SIZE
;
1588 return T5_REGMAP_SIZE
;
1591 static int get_eeprom_len(struct net_device
*dev
)
1596 static void get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
1598 struct adapter
*adapter
= netdev2adap(dev
);
1600 strlcpy(info
->driver
, KBUILD_MODNAME
, sizeof(info
->driver
));
1601 strlcpy(info
->version
, DRV_VERSION
, sizeof(info
->version
));
1602 strlcpy(info
->bus_info
, pci_name(adapter
->pdev
),
1603 sizeof(info
->bus_info
));
1605 if (adapter
->params
.fw_vers
)
1606 snprintf(info
->fw_version
, sizeof(info
->fw_version
),
1607 "%u.%u.%u.%u, TP %u.%u.%u.%u",
1608 FW_HDR_FW_VER_MAJOR_GET(adapter
->params
.fw_vers
),
1609 FW_HDR_FW_VER_MINOR_GET(adapter
->params
.fw_vers
),
1610 FW_HDR_FW_VER_MICRO_GET(adapter
->params
.fw_vers
),
1611 FW_HDR_FW_VER_BUILD_GET(adapter
->params
.fw_vers
),
1612 FW_HDR_FW_VER_MAJOR_GET(adapter
->params
.tp_vers
),
1613 FW_HDR_FW_VER_MINOR_GET(adapter
->params
.tp_vers
),
1614 FW_HDR_FW_VER_MICRO_GET(adapter
->params
.tp_vers
),
1615 FW_HDR_FW_VER_BUILD_GET(adapter
->params
.tp_vers
));
1618 static void get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1620 if (stringset
== ETH_SS_STATS
)
1621 memcpy(data
, stats_strings
, sizeof(stats_strings
));
1625 * port stats maintained per queue of the port. They should be in the same
1626 * order as in stats_strings above.
1628 struct queue_port_stats
{
1638 static void collect_sge_port_stats(const struct adapter
*adap
,
1639 const struct port_info
*p
, struct queue_port_stats
*s
)
1642 const struct sge_eth_txq
*tx
= &adap
->sge
.ethtxq
[p
->first_qset
];
1643 const struct sge_eth_rxq
*rx
= &adap
->sge
.ethrxq
[p
->first_qset
];
1645 memset(s
, 0, sizeof(*s
));
1646 for (i
= 0; i
< p
->nqsets
; i
++, rx
++, tx
++) {
1648 s
->tx_csum
+= tx
->tx_cso
;
1649 s
->rx_csum
+= rx
->stats
.rx_cso
;
1650 s
->vlan_ex
+= rx
->stats
.vlan_ex
;
1651 s
->vlan_ins
+= tx
->vlan_ins
;
1652 s
->gro_pkts
+= rx
->stats
.lro_pkts
;
1653 s
->gro_merged
+= rx
->stats
.lro_merged
;
1657 static void get_stats(struct net_device
*dev
, struct ethtool_stats
*stats
,
1660 struct port_info
*pi
= netdev_priv(dev
);
1661 struct adapter
*adapter
= pi
->adapter
;
1664 t4_get_port_stats(adapter
, pi
->tx_chan
, (struct port_stats
*)data
);
1666 data
+= sizeof(struct port_stats
) / sizeof(u64
);
1667 collect_sge_port_stats(adapter
, pi
, (struct queue_port_stats
*)data
);
1668 data
+= sizeof(struct queue_port_stats
) / sizeof(u64
);
1669 if (!is_t4(adapter
->params
.chip
)) {
1670 t4_write_reg(adapter
, SGE_STAT_CFG
, STATSOURCE_T5(7));
1671 val1
= t4_read_reg(adapter
, SGE_STAT_TOTAL
);
1672 val2
= t4_read_reg(adapter
, SGE_STAT_MATCH
);
1673 *data
= val1
- val2
;
1678 memset(data
, 0, 2 * sizeof(u64
));
1684 * Return a version number to identify the type of adapter. The scheme is:
1685 * - bits 0..9: chip version
1686 * - bits 10..15: chip revision
1687 * - bits 16..23: register dump version
1689 static inline unsigned int mk_adap_vers(const struct adapter
*ap
)
1691 return CHELSIO_CHIP_VERSION(ap
->params
.chip
) |
1692 (CHELSIO_CHIP_RELEASE(ap
->params
.chip
) << 10) | (1 << 16);
1695 static void reg_block_dump(struct adapter
*ap
, void *buf
, unsigned int start
,
1698 u32
*p
= buf
+ start
;
1700 for ( ; start
<= end
; start
+= sizeof(u32
))
1701 *p
++ = t4_read_reg(ap
, start
);
1704 static void get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1707 static const unsigned int t4_reg_ranges
[] = {
1928 static const unsigned int t5_reg_ranges
[] = {
2357 struct adapter
*ap
= netdev2adap(dev
);
2358 static const unsigned int *reg_ranges
;
2359 int arr_size
= 0, buf_size
= 0;
2361 if (is_t4(ap
->params
.chip
)) {
2362 reg_ranges
= &t4_reg_ranges
[0];
2363 arr_size
= ARRAY_SIZE(t4_reg_ranges
);
2364 buf_size
= T4_REGMAP_SIZE
;
2366 reg_ranges
= &t5_reg_ranges
[0];
2367 arr_size
= ARRAY_SIZE(t5_reg_ranges
);
2368 buf_size
= T5_REGMAP_SIZE
;
2371 regs
->version
= mk_adap_vers(ap
);
2373 memset(buf
, 0, buf_size
);
2374 for (i
= 0; i
< arr_size
; i
+= 2)
2375 reg_block_dump(ap
, buf
, reg_ranges
[i
], reg_ranges
[i
+ 1]);
2378 static int restart_autoneg(struct net_device
*dev
)
2380 struct port_info
*p
= netdev_priv(dev
);
2382 if (!netif_running(dev
))
2384 if (p
->link_cfg
.autoneg
!= AUTONEG_ENABLE
)
2386 t4_restart_aneg(p
->adapter
, p
->adapter
->fn
, p
->tx_chan
);
2390 static int identify_port(struct net_device
*dev
,
2391 enum ethtool_phys_id_state state
)
2394 struct adapter
*adap
= netdev2adap(dev
);
2396 if (state
== ETHTOOL_ID_ACTIVE
)
2398 else if (state
== ETHTOOL_ID_INACTIVE
)
2403 return t4_identify_port(adap
, adap
->fn
, netdev2pinfo(dev
)->viid
, val
);
2406 static unsigned int from_fw_linkcaps(unsigned int type
, unsigned int caps
)
2410 if (type
== FW_PORT_TYPE_BT_SGMII
|| type
== FW_PORT_TYPE_BT_XFI
||
2411 type
== FW_PORT_TYPE_BT_XAUI
) {
2413 if (caps
& FW_PORT_CAP_SPEED_100M
)
2414 v
|= SUPPORTED_100baseT_Full
;
2415 if (caps
& FW_PORT_CAP_SPEED_1G
)
2416 v
|= SUPPORTED_1000baseT_Full
;
2417 if (caps
& FW_PORT_CAP_SPEED_10G
)
2418 v
|= SUPPORTED_10000baseT_Full
;
2419 } else if (type
== FW_PORT_TYPE_KX4
|| type
== FW_PORT_TYPE_KX
) {
2420 v
|= SUPPORTED_Backplane
;
2421 if (caps
& FW_PORT_CAP_SPEED_1G
)
2422 v
|= SUPPORTED_1000baseKX_Full
;
2423 if (caps
& FW_PORT_CAP_SPEED_10G
)
2424 v
|= SUPPORTED_10000baseKX4_Full
;
2425 } else if (type
== FW_PORT_TYPE_KR
)
2426 v
|= SUPPORTED_Backplane
| SUPPORTED_10000baseKR_Full
;
2427 else if (type
== FW_PORT_TYPE_BP_AP
)
2428 v
|= SUPPORTED_Backplane
| SUPPORTED_10000baseR_FEC
|
2429 SUPPORTED_10000baseKR_Full
| SUPPORTED_1000baseKX_Full
;
2430 else if (type
== FW_PORT_TYPE_BP4_AP
)
2431 v
|= SUPPORTED_Backplane
| SUPPORTED_10000baseR_FEC
|
2432 SUPPORTED_10000baseKR_Full
| SUPPORTED_1000baseKX_Full
|
2433 SUPPORTED_10000baseKX4_Full
;
2434 else if (type
== FW_PORT_TYPE_FIBER_XFI
||
2435 type
== FW_PORT_TYPE_FIBER_XAUI
|| type
== FW_PORT_TYPE_SFP
)
2436 v
|= SUPPORTED_FIBRE
;
2437 else if (type
== FW_PORT_TYPE_BP40_BA
)
2438 v
|= SUPPORTED_40000baseSR4_Full
;
2440 if (caps
& FW_PORT_CAP_ANEG
)
2441 v
|= SUPPORTED_Autoneg
;
2445 static unsigned int to_fw_linkcaps(unsigned int caps
)
2449 if (caps
& ADVERTISED_100baseT_Full
)
2450 v
|= FW_PORT_CAP_SPEED_100M
;
2451 if (caps
& ADVERTISED_1000baseT_Full
)
2452 v
|= FW_PORT_CAP_SPEED_1G
;
2453 if (caps
& ADVERTISED_10000baseT_Full
)
2454 v
|= FW_PORT_CAP_SPEED_10G
;
2455 if (caps
& ADVERTISED_40000baseSR4_Full
)
2456 v
|= FW_PORT_CAP_SPEED_40G
;
2460 static int get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2462 const struct port_info
*p
= netdev_priv(dev
);
2464 if (p
->port_type
== FW_PORT_TYPE_BT_SGMII
||
2465 p
->port_type
== FW_PORT_TYPE_BT_XFI
||
2466 p
->port_type
== FW_PORT_TYPE_BT_XAUI
)
2467 cmd
->port
= PORT_TP
;
2468 else if (p
->port_type
== FW_PORT_TYPE_FIBER_XFI
||
2469 p
->port_type
== FW_PORT_TYPE_FIBER_XAUI
)
2470 cmd
->port
= PORT_FIBRE
;
2471 else if (p
->port_type
== FW_PORT_TYPE_SFP
||
2472 p
->port_type
== FW_PORT_TYPE_QSFP_10G
||
2473 p
->port_type
== FW_PORT_TYPE_QSFP
) {
2474 if (p
->mod_type
== FW_PORT_MOD_TYPE_LR
||
2475 p
->mod_type
== FW_PORT_MOD_TYPE_SR
||
2476 p
->mod_type
== FW_PORT_MOD_TYPE_ER
||
2477 p
->mod_type
== FW_PORT_MOD_TYPE_LRM
)
2478 cmd
->port
= PORT_FIBRE
;
2479 else if (p
->mod_type
== FW_PORT_MOD_TYPE_TWINAX_PASSIVE
||
2480 p
->mod_type
== FW_PORT_MOD_TYPE_TWINAX_ACTIVE
)
2481 cmd
->port
= PORT_DA
;
2483 cmd
->port
= PORT_OTHER
;
2485 cmd
->port
= PORT_OTHER
;
2487 if (p
->mdio_addr
>= 0) {
2488 cmd
->phy_address
= p
->mdio_addr
;
2489 cmd
->transceiver
= XCVR_EXTERNAL
;
2490 cmd
->mdio_support
= p
->port_type
== FW_PORT_TYPE_BT_SGMII
?
2491 MDIO_SUPPORTS_C22
: MDIO_SUPPORTS_C45
;
2493 cmd
->phy_address
= 0; /* not really, but no better option */
2494 cmd
->transceiver
= XCVR_INTERNAL
;
2495 cmd
->mdio_support
= 0;
2498 cmd
->supported
= from_fw_linkcaps(p
->port_type
, p
->link_cfg
.supported
);
2499 cmd
->advertising
= from_fw_linkcaps(p
->port_type
,
2500 p
->link_cfg
.advertising
);
2501 ethtool_cmd_speed_set(cmd
,
2502 netif_carrier_ok(dev
) ? p
->link_cfg
.speed
: 0);
2503 cmd
->duplex
= DUPLEX_FULL
;
2504 cmd
->autoneg
= p
->link_cfg
.autoneg
;
2510 static unsigned int speed_to_caps(int speed
)
2513 return FW_PORT_CAP_SPEED_100M
;
2515 return FW_PORT_CAP_SPEED_1G
;
2517 return FW_PORT_CAP_SPEED_10G
;
2519 return FW_PORT_CAP_SPEED_40G
;
2523 static int set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2526 struct port_info
*p
= netdev_priv(dev
);
2527 struct link_config
*lc
= &p
->link_cfg
;
2528 u32 speed
= ethtool_cmd_speed(cmd
);
2530 if (cmd
->duplex
!= DUPLEX_FULL
) /* only full-duplex supported */
2533 if (!(lc
->supported
& FW_PORT_CAP_ANEG
)) {
2535 * PHY offers a single speed. See if that's what's
2538 if (cmd
->autoneg
== AUTONEG_DISABLE
&&
2539 (lc
->supported
& speed_to_caps(speed
)))
2544 if (cmd
->autoneg
== AUTONEG_DISABLE
) {
2545 cap
= speed_to_caps(speed
);
2547 if (!(lc
->supported
& cap
) ||
2552 lc
->requested_speed
= cap
;
2553 lc
->advertising
= 0;
2555 cap
= to_fw_linkcaps(cmd
->advertising
);
2556 if (!(lc
->supported
& cap
))
2558 lc
->requested_speed
= 0;
2559 lc
->advertising
= cap
| FW_PORT_CAP_ANEG
;
2561 lc
->autoneg
= cmd
->autoneg
;
2563 if (netif_running(dev
))
2564 return t4_link_start(p
->adapter
, p
->adapter
->fn
, p
->tx_chan
,
2569 static void get_pauseparam(struct net_device
*dev
,
2570 struct ethtool_pauseparam
*epause
)
2572 struct port_info
*p
= netdev_priv(dev
);
2574 epause
->autoneg
= (p
->link_cfg
.requested_fc
& PAUSE_AUTONEG
) != 0;
2575 epause
->rx_pause
= (p
->link_cfg
.fc
& PAUSE_RX
) != 0;
2576 epause
->tx_pause
= (p
->link_cfg
.fc
& PAUSE_TX
) != 0;
2579 static int set_pauseparam(struct net_device
*dev
,
2580 struct ethtool_pauseparam
*epause
)
2582 struct port_info
*p
= netdev_priv(dev
);
2583 struct link_config
*lc
= &p
->link_cfg
;
2585 if (epause
->autoneg
== AUTONEG_DISABLE
)
2586 lc
->requested_fc
= 0;
2587 else if (lc
->supported
& FW_PORT_CAP_ANEG
)
2588 lc
->requested_fc
= PAUSE_AUTONEG
;
2592 if (epause
->rx_pause
)
2593 lc
->requested_fc
|= PAUSE_RX
;
2594 if (epause
->tx_pause
)
2595 lc
->requested_fc
|= PAUSE_TX
;
2596 if (netif_running(dev
))
2597 return t4_link_start(p
->adapter
, p
->adapter
->fn
, p
->tx_chan
,
2602 static void get_sge_param(struct net_device
*dev
, struct ethtool_ringparam
*e
)
2604 const struct port_info
*pi
= netdev_priv(dev
);
2605 const struct sge
*s
= &pi
->adapter
->sge
;
2607 e
->rx_max_pending
= MAX_RX_BUFFERS
;
2608 e
->rx_mini_max_pending
= MAX_RSPQ_ENTRIES
;
2609 e
->rx_jumbo_max_pending
= 0;
2610 e
->tx_max_pending
= MAX_TXQ_ENTRIES
;
2612 e
->rx_pending
= s
->ethrxq
[pi
->first_qset
].fl
.size
- 8;
2613 e
->rx_mini_pending
= s
->ethrxq
[pi
->first_qset
].rspq
.size
;
2614 e
->rx_jumbo_pending
= 0;
2615 e
->tx_pending
= s
->ethtxq
[pi
->first_qset
].q
.size
;
2618 static int set_sge_param(struct net_device
*dev
, struct ethtool_ringparam
*e
)
2621 const struct port_info
*pi
= netdev_priv(dev
);
2622 struct adapter
*adapter
= pi
->adapter
;
2623 struct sge
*s
= &adapter
->sge
;
2625 if (e
->rx_pending
> MAX_RX_BUFFERS
|| e
->rx_jumbo_pending
||
2626 e
->tx_pending
> MAX_TXQ_ENTRIES
||
2627 e
->rx_mini_pending
> MAX_RSPQ_ENTRIES
||
2628 e
->rx_mini_pending
< MIN_RSPQ_ENTRIES
||
2629 e
->rx_pending
< MIN_FL_ENTRIES
|| e
->tx_pending
< MIN_TXQ_ENTRIES
)
2632 if (adapter
->flags
& FULL_INIT_DONE
)
2635 for (i
= 0; i
< pi
->nqsets
; ++i
) {
2636 s
->ethtxq
[pi
->first_qset
+ i
].q
.size
= e
->tx_pending
;
2637 s
->ethrxq
[pi
->first_qset
+ i
].fl
.size
= e
->rx_pending
+ 8;
2638 s
->ethrxq
[pi
->first_qset
+ i
].rspq
.size
= e
->rx_mini_pending
;
2643 static int closest_timer(const struct sge
*s
, int time
)
2645 int i
, delta
, match
= 0, min_delta
= INT_MAX
;
2647 for (i
= 0; i
< ARRAY_SIZE(s
->timer_val
); i
++) {
2648 delta
= time
- s
->timer_val
[i
];
2651 if (delta
< min_delta
) {
2659 static int closest_thres(const struct sge
*s
, int thres
)
2661 int i
, delta
, match
= 0, min_delta
= INT_MAX
;
2663 for (i
= 0; i
< ARRAY_SIZE(s
->counter_val
); i
++) {
2664 delta
= thres
- s
->counter_val
[i
];
2667 if (delta
< min_delta
) {
2676 * Return a queue's interrupt hold-off time in us. 0 means no timer.
2678 static unsigned int qtimer_val(const struct adapter
*adap
,
2679 const struct sge_rspq
*q
)
2681 unsigned int idx
= q
->intr_params
>> 1;
2683 return idx
< SGE_NTIMERS
? adap
->sge
.timer_val
[idx
] : 0;
2687 * set_rspq_intr_params - set a queue's interrupt holdoff parameters
2689 * @us: the hold-off time in us, or 0 to disable timer
2690 * @cnt: the hold-off packet count, or 0 to disable counter
2692 * Sets an Rx queue's interrupt hold-off time and packet count. At least
2693 * one of the two needs to be enabled for the queue to generate interrupts.
2695 static int set_rspq_intr_params(struct sge_rspq
*q
,
2696 unsigned int us
, unsigned int cnt
)
2698 struct adapter
*adap
= q
->adap
;
2700 if ((us
| cnt
) == 0)
2707 new_idx
= closest_thres(&adap
->sge
, cnt
);
2708 if (q
->desc
&& q
->pktcnt_idx
!= new_idx
) {
2709 /* the queue has already been created, update it */
2710 v
= FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ
) |
2711 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH
) |
2712 FW_PARAMS_PARAM_YZ(q
->cntxt_id
);
2713 err
= t4_set_params(adap
, adap
->fn
, adap
->fn
, 0, 1, &v
,
2718 q
->pktcnt_idx
= new_idx
;
2721 us
= us
== 0 ? 6 : closest_timer(&adap
->sge
, us
);
2722 q
->intr_params
= QINTR_TIMER_IDX(us
) | (cnt
> 0 ? QINTR_CNT_EN
: 0);
2727 * set_rx_intr_params - set a net devices's RX interrupt holdoff paramete!
2728 * @dev: the network device
2729 * @us: the hold-off time in us, or 0 to disable timer
2730 * @cnt: the hold-off packet count, or 0 to disable counter
2732 * Set the RX interrupt hold-off parameters for a network device.
2734 static int set_rx_intr_params(struct net_device
*dev
,
2735 unsigned int us
, unsigned int cnt
)
2738 struct port_info
*pi
= netdev_priv(dev
);
2739 struct adapter
*adap
= pi
->adapter
;
2740 struct sge_eth_rxq
*q
= &adap
->sge
.ethrxq
[pi
->first_qset
];
2742 for (i
= 0; i
< pi
->nqsets
; i
++, q
++) {
2743 err
= set_rspq_intr_params(&q
->rspq
, us
, cnt
);
2750 static int set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*c
)
2752 return set_rx_intr_params(dev
, c
->rx_coalesce_usecs
,
2753 c
->rx_max_coalesced_frames
);
2756 static int get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*c
)
2758 const struct port_info
*pi
= netdev_priv(dev
);
2759 const struct adapter
*adap
= pi
->adapter
;
2760 const struct sge_rspq
*rq
= &adap
->sge
.ethrxq
[pi
->first_qset
].rspq
;
2762 c
->rx_coalesce_usecs
= qtimer_val(adap
, rq
);
2763 c
->rx_max_coalesced_frames
= (rq
->intr_params
& QINTR_CNT_EN
) ?
2764 adap
->sge
.counter_val
[rq
->pktcnt_idx
] : 0;
2769 * eeprom_ptov - translate a physical EEPROM address to virtual
2770 * @phys_addr: the physical EEPROM address
2771 * @fn: the PCI function number
2772 * @sz: size of function-specific area
2774 * Translate a physical EEPROM address to virtual. The first 1K is
2775 * accessed through virtual addresses starting at 31K, the rest is
2776 * accessed through virtual addresses starting at 0.
2778 * The mapping is as follows:
2779 * [0..1K) -> [31K..32K)
2780 * [1K..1K+A) -> [31K-A..31K)
2781 * [1K+A..ES) -> [0..ES-A-1K)
2783 * where A = @fn * @sz, and ES = EEPROM size.
2785 static int eeprom_ptov(unsigned int phys_addr
, unsigned int fn
, unsigned int sz
)
2788 if (phys_addr
< 1024)
2789 return phys_addr
+ (31 << 10);
2790 if (phys_addr
< 1024 + fn
)
2791 return 31744 - fn
+ phys_addr
- 1024;
2792 if (phys_addr
< EEPROMSIZE
)
2793 return phys_addr
- 1024 - fn
;
2798 * The next two routines implement eeprom read/write from physical addresses.
2800 static int eeprom_rd_phys(struct adapter
*adap
, unsigned int phys_addr
, u32
*v
)
2802 int vaddr
= eeprom_ptov(phys_addr
, adap
->fn
, EEPROMPFSIZE
);
2805 vaddr
= pci_read_vpd(adap
->pdev
, vaddr
, sizeof(u32
), v
);
2806 return vaddr
< 0 ? vaddr
: 0;
2809 static int eeprom_wr_phys(struct adapter
*adap
, unsigned int phys_addr
, u32 v
)
2811 int vaddr
= eeprom_ptov(phys_addr
, adap
->fn
, EEPROMPFSIZE
);
2814 vaddr
= pci_write_vpd(adap
->pdev
, vaddr
, sizeof(u32
), &v
);
2815 return vaddr
< 0 ? vaddr
: 0;
2818 #define EEPROM_MAGIC 0x38E2F10C
2820 static int get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*e
,
2824 struct adapter
*adapter
= netdev2adap(dev
);
2826 u8
*buf
= kmalloc(EEPROMSIZE
, GFP_KERNEL
);
2830 e
->magic
= EEPROM_MAGIC
;
2831 for (i
= e
->offset
& ~3; !err
&& i
< e
->offset
+ e
->len
; i
+= 4)
2832 err
= eeprom_rd_phys(adapter
, i
, (u32
*)&buf
[i
]);
2835 memcpy(data
, buf
+ e
->offset
, e
->len
);
2840 static int set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
2845 u32 aligned_offset
, aligned_len
, *p
;
2846 struct adapter
*adapter
= netdev2adap(dev
);
2848 if (eeprom
->magic
!= EEPROM_MAGIC
)
2851 aligned_offset
= eeprom
->offset
& ~3;
2852 aligned_len
= (eeprom
->len
+ (eeprom
->offset
& 3) + 3) & ~3;
2854 if (adapter
->fn
> 0) {
2855 u32 start
= 1024 + adapter
->fn
* EEPROMPFSIZE
;
2857 if (aligned_offset
< start
||
2858 aligned_offset
+ aligned_len
> start
+ EEPROMPFSIZE
)
2862 if (aligned_offset
!= eeprom
->offset
|| aligned_len
!= eeprom
->len
) {
2864 * RMW possibly needed for first or last words.
2866 buf
= kmalloc(aligned_len
, GFP_KERNEL
);
2869 err
= eeprom_rd_phys(adapter
, aligned_offset
, (u32
*)buf
);
2870 if (!err
&& aligned_len
> 4)
2871 err
= eeprom_rd_phys(adapter
,
2872 aligned_offset
+ aligned_len
- 4,
2873 (u32
*)&buf
[aligned_len
- 4]);
2876 memcpy(buf
+ (eeprom
->offset
& 3), data
, eeprom
->len
);
2880 err
= t4_seeprom_wp(adapter
, false);
2884 for (p
= (u32
*)buf
; !err
&& aligned_len
; aligned_len
-= 4, p
++) {
2885 err
= eeprom_wr_phys(adapter
, aligned_offset
, *p
);
2886 aligned_offset
+= 4;
2890 err
= t4_seeprom_wp(adapter
, true);
2897 static int set_flash(struct net_device
*netdev
, struct ethtool_flash
*ef
)
2900 const struct firmware
*fw
;
2901 struct adapter
*adap
= netdev2adap(netdev
);
2903 ef
->data
[sizeof(ef
->data
) - 1] = '\0';
2904 ret
= request_firmware(&fw
, ef
->data
, adap
->pdev_dev
);
2908 ret
= t4_load_fw(adap
, fw
->data
, fw
->size
);
2909 release_firmware(fw
);
2911 dev_info(adap
->pdev_dev
, "loaded firmware %s\n", ef
->data
);
2915 #define WOL_SUPPORTED (WAKE_BCAST | WAKE_MAGIC)
2916 #define BCAST_CRC 0xa0ccc1a6
2918 static void get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2920 wol
->supported
= WAKE_BCAST
| WAKE_MAGIC
;
2921 wol
->wolopts
= netdev2adap(dev
)->wol
;
2922 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
2925 static int set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2928 struct port_info
*pi
= netdev_priv(dev
);
2930 if (wol
->wolopts
& ~WOL_SUPPORTED
)
2932 t4_wol_magic_enable(pi
->adapter
, pi
->tx_chan
,
2933 (wol
->wolopts
& WAKE_MAGIC
) ? dev
->dev_addr
: NULL
);
2934 if (wol
->wolopts
& WAKE_BCAST
) {
2935 err
= t4_wol_pat_enable(pi
->adapter
, pi
->tx_chan
, 0xfe, ~0ULL,
2938 err
= t4_wol_pat_enable(pi
->adapter
, pi
->tx_chan
, 1,
2939 ~6ULL, ~0ULL, BCAST_CRC
, true);
2941 t4_wol_pat_enable(pi
->adapter
, pi
->tx_chan
, 0, 0, 0, 0, false);
2945 static int cxgb_set_features(struct net_device
*dev
, netdev_features_t features
)
2947 const struct port_info
*pi
= netdev_priv(dev
);
2948 netdev_features_t changed
= dev
->features
^ features
;
2951 if (!(changed
& NETIF_F_HW_VLAN_CTAG_RX
))
2954 err
= t4_set_rxmode(pi
->adapter
, pi
->adapter
->fn
, pi
->viid
, -1,
2956 !!(features
& NETIF_F_HW_VLAN_CTAG_RX
), true);
2958 dev
->features
= features
^ NETIF_F_HW_VLAN_CTAG_RX
;
2962 static u32
get_rss_table_size(struct net_device
*dev
)
2964 const struct port_info
*pi
= netdev_priv(dev
);
2966 return pi
->rss_size
;
2969 static int get_rss_table(struct net_device
*dev
, u32
*p
, u8
*key
)
2971 const struct port_info
*pi
= netdev_priv(dev
);
2972 unsigned int n
= pi
->rss_size
;
2979 static int set_rss_table(struct net_device
*dev
, const u32
*p
, const u8
*key
)
2982 struct port_info
*pi
= netdev_priv(dev
);
2984 for (i
= 0; i
< pi
->rss_size
; i
++)
2986 if (pi
->adapter
->flags
& FULL_INIT_DONE
)
2987 return write_rss(pi
, pi
->rss
);
2991 static int get_rxnfc(struct net_device
*dev
, struct ethtool_rxnfc
*info
,
2994 const struct port_info
*pi
= netdev_priv(dev
);
2996 switch (info
->cmd
) {
2997 case ETHTOOL_GRXFH
: {
2998 unsigned int v
= pi
->rss_mode
;
3001 switch (info
->flow_type
) {
3003 if (v
& FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN
)
3004 info
->data
= RXH_IP_SRC
| RXH_IP_DST
|
3005 RXH_L4_B_0_1
| RXH_L4_B_2_3
;
3006 else if (v
& FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN
)
3007 info
->data
= RXH_IP_SRC
| RXH_IP_DST
;
3010 if ((v
& FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN
) &&
3011 (v
& FW_RSS_VI_CONFIG_CMD_UDPEN
))
3012 info
->data
= RXH_IP_SRC
| RXH_IP_DST
|
3013 RXH_L4_B_0_1
| RXH_L4_B_2_3
;
3014 else if (v
& FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN
)
3015 info
->data
= RXH_IP_SRC
| RXH_IP_DST
;
3018 case AH_ESP_V4_FLOW
:
3020 if (v
& FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN
)
3021 info
->data
= RXH_IP_SRC
| RXH_IP_DST
;
3024 if (v
& FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN
)
3025 info
->data
= RXH_IP_SRC
| RXH_IP_DST
|
3026 RXH_L4_B_0_1
| RXH_L4_B_2_3
;
3027 else if (v
& FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN
)
3028 info
->data
= RXH_IP_SRC
| RXH_IP_DST
;
3031 if ((v
& FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN
) &&
3032 (v
& FW_RSS_VI_CONFIG_CMD_UDPEN
))
3033 info
->data
= RXH_IP_SRC
| RXH_IP_DST
|
3034 RXH_L4_B_0_1
| RXH_L4_B_2_3
;
3035 else if (v
& FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN
)
3036 info
->data
= RXH_IP_SRC
| RXH_IP_DST
;
3039 case AH_ESP_V6_FLOW
:
3041 if (v
& FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN
)
3042 info
->data
= RXH_IP_SRC
| RXH_IP_DST
;
3047 case ETHTOOL_GRXRINGS
:
3048 info
->data
= pi
->nqsets
;
3054 static const struct ethtool_ops cxgb_ethtool_ops
= {
3055 .get_settings
= get_settings
,
3056 .set_settings
= set_settings
,
3057 .get_drvinfo
= get_drvinfo
,
3058 .get_msglevel
= get_msglevel
,
3059 .set_msglevel
= set_msglevel
,
3060 .get_ringparam
= get_sge_param
,
3061 .set_ringparam
= set_sge_param
,
3062 .get_coalesce
= get_coalesce
,
3063 .set_coalesce
= set_coalesce
,
3064 .get_eeprom_len
= get_eeprom_len
,
3065 .get_eeprom
= get_eeprom
,
3066 .set_eeprom
= set_eeprom
,
3067 .get_pauseparam
= get_pauseparam
,
3068 .set_pauseparam
= set_pauseparam
,
3069 .get_link
= ethtool_op_get_link
,
3070 .get_strings
= get_strings
,
3071 .set_phys_id
= identify_port
,
3072 .nway_reset
= restart_autoneg
,
3073 .get_sset_count
= get_sset_count
,
3074 .get_ethtool_stats
= get_stats
,
3075 .get_regs_len
= get_regs_len
,
3076 .get_regs
= get_regs
,
3079 .get_rxnfc
= get_rxnfc
,
3080 .get_rxfh_indir_size
= get_rss_table_size
,
3081 .get_rxfh
= get_rss_table
,
3082 .set_rxfh
= set_rss_table
,
3083 .flash_device
= set_flash
,
3089 static ssize_t
mem_read(struct file
*file
, char __user
*buf
, size_t count
,
3093 loff_t avail
= file_inode(file
)->i_size
;
3094 unsigned int mem
= (uintptr_t)file
->private_data
& 3;
3095 struct adapter
*adap
= file
->private_data
- mem
;
3103 if (count
> avail
- pos
)
3104 count
= avail
- pos
;
3106 data
= t4_alloc_mem(count
);
3110 spin_lock(&adap
->win0_lock
);
3111 ret
= t4_memory_rw(adap
, 0, mem
, pos
, count
, data
, T4_MEMORY_READ
);
3112 spin_unlock(&adap
->win0_lock
);
3117 ret
= copy_to_user(buf
, data
, count
);
3123 *ppos
= pos
+ count
;
3127 static const struct file_operations mem_debugfs_fops
= {
3128 .owner
= THIS_MODULE
,
3129 .open
= simple_open
,
3131 .llseek
= default_llseek
,
3134 static void add_debugfs_mem(struct adapter
*adap
, const char *name
,
3135 unsigned int idx
, unsigned int size_mb
)
3139 de
= debugfs_create_file(name
, S_IRUSR
, adap
->debugfs_root
,
3140 (void *)adap
+ idx
, &mem_debugfs_fops
);
3141 if (de
&& de
->d_inode
)
3142 de
->d_inode
->i_size
= size_mb
<< 20;
3145 static int setup_debugfs(struct adapter
*adap
)
3150 if (IS_ERR_OR_NULL(adap
->debugfs_root
))
3153 i
= t4_read_reg(adap
, MA_TARGET_MEM_ENABLE
);
3154 if (i
& EDRAM0_ENABLE
) {
3155 size
= t4_read_reg(adap
, MA_EDRAM0_BAR
);
3156 add_debugfs_mem(adap
, "edc0", MEM_EDC0
, EDRAM_SIZE_GET(size
));
3158 if (i
& EDRAM1_ENABLE
) {
3159 size
= t4_read_reg(adap
, MA_EDRAM1_BAR
);
3160 add_debugfs_mem(adap
, "edc1", MEM_EDC1
, EDRAM_SIZE_GET(size
));
3162 if (is_t4(adap
->params
.chip
)) {
3163 size
= t4_read_reg(adap
, MA_EXT_MEMORY_BAR
);
3164 if (i
& EXT_MEM_ENABLE
)
3165 add_debugfs_mem(adap
, "mc", MEM_MC
,
3166 EXT_MEM_SIZE_GET(size
));
3168 if (i
& EXT_MEM_ENABLE
) {
3169 size
= t4_read_reg(adap
, MA_EXT_MEMORY_BAR
);
3170 add_debugfs_mem(adap
, "mc0", MEM_MC0
,
3171 EXT_MEM_SIZE_GET(size
));
3173 if (i
& EXT_MEM1_ENABLE
) {
3174 size
= t4_read_reg(adap
, MA_EXT_MEMORY1_BAR
);
3175 add_debugfs_mem(adap
, "mc1", MEM_MC1
,
3176 EXT_MEM_SIZE_GET(size
));
3180 debugfs_create_file("l2t", S_IRUSR
, adap
->debugfs_root
, adap
,
3186 * upper-layer driver support
3190 * Allocate an active-open TID and set it to the supplied value.
3192 int cxgb4_alloc_atid(struct tid_info
*t
, void *data
)
3196 spin_lock_bh(&t
->atid_lock
);
3198 union aopen_entry
*p
= t
->afree
;
3200 atid
= (p
- t
->atid_tab
) + t
->atid_base
;
3205 spin_unlock_bh(&t
->atid_lock
);
3208 EXPORT_SYMBOL(cxgb4_alloc_atid
);
3211 * Release an active-open TID.
3213 void cxgb4_free_atid(struct tid_info
*t
, unsigned int atid
)
3215 union aopen_entry
*p
= &t
->atid_tab
[atid
- t
->atid_base
];
3217 spin_lock_bh(&t
->atid_lock
);
3221 spin_unlock_bh(&t
->atid_lock
);
3223 EXPORT_SYMBOL(cxgb4_free_atid
);
3226 * Allocate a server TID and set it to the supplied value.
3228 int cxgb4_alloc_stid(struct tid_info
*t
, int family
, void *data
)
3232 spin_lock_bh(&t
->stid_lock
);
3233 if (family
== PF_INET
) {
3234 stid
= find_first_zero_bit(t
->stid_bmap
, t
->nstids
);
3235 if (stid
< t
->nstids
)
3236 __set_bit(stid
, t
->stid_bmap
);
3240 stid
= bitmap_find_free_region(t
->stid_bmap
, t
->nstids
, 2);
3245 t
->stid_tab
[stid
].data
= data
;
3246 stid
+= t
->stid_base
;
3247 /* IPv6 requires max of 520 bits or 16 cells in TCAM
3248 * This is equivalent to 4 TIDs. With CLIP enabled it
3251 if (family
== PF_INET
)
3254 t
->stids_in_use
+= 4;
3256 spin_unlock_bh(&t
->stid_lock
);
3259 EXPORT_SYMBOL(cxgb4_alloc_stid
);
3261 /* Allocate a server filter TID and set it to the supplied value.
3263 int cxgb4_alloc_sftid(struct tid_info
*t
, int family
, void *data
)
3267 spin_lock_bh(&t
->stid_lock
);
3268 if (family
== PF_INET
) {
3269 stid
= find_next_zero_bit(t
->stid_bmap
,
3270 t
->nstids
+ t
->nsftids
, t
->nstids
);
3271 if (stid
< (t
->nstids
+ t
->nsftids
))
3272 __set_bit(stid
, t
->stid_bmap
);
3279 t
->stid_tab
[stid
].data
= data
;
3281 stid
+= t
->sftid_base
;
3284 spin_unlock_bh(&t
->stid_lock
);
3287 EXPORT_SYMBOL(cxgb4_alloc_sftid
);
3289 /* Release a server TID.
3291 void cxgb4_free_stid(struct tid_info
*t
, unsigned int stid
, int family
)
3293 /* Is it a server filter TID? */
3294 if (t
->nsftids
&& (stid
>= t
->sftid_base
)) {
3295 stid
-= t
->sftid_base
;
3298 stid
-= t
->stid_base
;
3301 spin_lock_bh(&t
->stid_lock
);
3302 if (family
== PF_INET
)
3303 __clear_bit(stid
, t
->stid_bmap
);
3305 bitmap_release_region(t
->stid_bmap
, stid
, 2);
3306 t
->stid_tab
[stid
].data
= NULL
;
3307 if (family
== PF_INET
)
3310 t
->stids_in_use
-= 4;
3311 spin_unlock_bh(&t
->stid_lock
);
3313 EXPORT_SYMBOL(cxgb4_free_stid
);
3316 * Populate a TID_RELEASE WR. Caller must properly size the skb.
3318 static void mk_tid_release(struct sk_buff
*skb
, unsigned int chan
,
3321 struct cpl_tid_release
*req
;
3323 set_wr_txq(skb
, CPL_PRIORITY_SETUP
, chan
);
3324 req
= (struct cpl_tid_release
*)__skb_put(skb
, sizeof(*req
));
3325 INIT_TP_WR(req
, tid
);
3326 OPCODE_TID(req
) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE
, tid
));
3330 * Queue a TID release request and if necessary schedule a work queue to
3333 static void cxgb4_queue_tid_release(struct tid_info
*t
, unsigned int chan
,
3336 void **p
= &t
->tid_tab
[tid
];
3337 struct adapter
*adap
= container_of(t
, struct adapter
, tids
);
3339 spin_lock_bh(&adap
->tid_release_lock
);
3340 *p
= adap
->tid_release_head
;
3341 /* Low 2 bits encode the Tx channel number */
3342 adap
->tid_release_head
= (void **)((uintptr_t)p
| chan
);
3343 if (!adap
->tid_release_task_busy
) {
3344 adap
->tid_release_task_busy
= true;
3345 queue_work(adap
->workq
, &adap
->tid_release_task
);
3347 spin_unlock_bh(&adap
->tid_release_lock
);
3351 * Process the list of pending TID release requests.
3353 static void process_tid_release_list(struct work_struct
*work
)
3355 struct sk_buff
*skb
;
3356 struct adapter
*adap
;
3358 adap
= container_of(work
, struct adapter
, tid_release_task
);
3360 spin_lock_bh(&adap
->tid_release_lock
);
3361 while (adap
->tid_release_head
) {
3362 void **p
= adap
->tid_release_head
;
3363 unsigned int chan
= (uintptr_t)p
& 3;
3364 p
= (void *)p
- chan
;
3366 adap
->tid_release_head
= *p
;
3368 spin_unlock_bh(&adap
->tid_release_lock
);
3370 while (!(skb
= alloc_skb(sizeof(struct cpl_tid_release
),
3372 schedule_timeout_uninterruptible(1);
3374 mk_tid_release(skb
, chan
, p
- adap
->tids
.tid_tab
);
3375 t4_ofld_send(adap
, skb
);
3376 spin_lock_bh(&adap
->tid_release_lock
);
3378 adap
->tid_release_task_busy
= false;
3379 spin_unlock_bh(&adap
->tid_release_lock
);
3383 * Release a TID and inform HW. If we are unable to allocate the release
3384 * message we defer to a work queue.
3386 void cxgb4_remove_tid(struct tid_info
*t
, unsigned int chan
, unsigned int tid
)
3389 struct sk_buff
*skb
;
3390 struct adapter
*adap
= container_of(t
, struct adapter
, tids
);
3392 old
= t
->tid_tab
[tid
];
3393 skb
= alloc_skb(sizeof(struct cpl_tid_release
), GFP_ATOMIC
);
3395 t
->tid_tab
[tid
] = NULL
;
3396 mk_tid_release(skb
, chan
, tid
);
3397 t4_ofld_send(adap
, skb
);
3399 cxgb4_queue_tid_release(t
, chan
, tid
);
3401 atomic_dec(&t
->tids_in_use
);
3403 EXPORT_SYMBOL(cxgb4_remove_tid
);
3406 * Allocate and initialize the TID tables. Returns 0 on success.
3408 static int tid_init(struct tid_info
*t
)
3411 unsigned int stid_bmap_size
;
3412 unsigned int natids
= t
->natids
;
3413 struct adapter
*adap
= container_of(t
, struct adapter
, tids
);
3415 stid_bmap_size
= BITS_TO_LONGS(t
->nstids
+ t
->nsftids
);
3416 size
= t
->ntids
* sizeof(*t
->tid_tab
) +
3417 natids
* sizeof(*t
->atid_tab
) +
3418 t
->nstids
* sizeof(*t
->stid_tab
) +
3419 t
->nsftids
* sizeof(*t
->stid_tab
) +
3420 stid_bmap_size
* sizeof(long) +
3421 t
->nftids
* sizeof(*t
->ftid_tab
) +
3422 t
->nsftids
* sizeof(*t
->ftid_tab
);
3424 t
->tid_tab
= t4_alloc_mem(size
);
3428 t
->atid_tab
= (union aopen_entry
*)&t
->tid_tab
[t
->ntids
];
3429 t
->stid_tab
= (struct serv_entry
*)&t
->atid_tab
[natids
];
3430 t
->stid_bmap
= (unsigned long *)&t
->stid_tab
[t
->nstids
+ t
->nsftids
];
3431 t
->ftid_tab
= (struct filter_entry
*)&t
->stid_bmap
[stid_bmap_size
];
3432 spin_lock_init(&t
->stid_lock
);
3433 spin_lock_init(&t
->atid_lock
);
3435 t
->stids_in_use
= 0;
3437 t
->atids_in_use
= 0;
3438 atomic_set(&t
->tids_in_use
, 0);
3440 /* Setup the free list for atid_tab and clear the stid bitmap. */
3443 t
->atid_tab
[natids
- 1].next
= &t
->atid_tab
[natids
];
3444 t
->afree
= t
->atid_tab
;
3446 bitmap_zero(t
->stid_bmap
, t
->nstids
+ t
->nsftids
);
3447 /* Reserve stid 0 for T4/T5 adapters */
3448 if (!t
->stid_base
&&
3449 (is_t4(adap
->params
.chip
) || is_t5(adap
->params
.chip
)))
3450 __set_bit(0, t
->stid_bmap
);
3455 int cxgb4_clip_get(const struct net_device
*dev
,
3456 const struct in6_addr
*lip
)
3458 struct adapter
*adap
;
3459 struct fw_clip_cmd c
;
3461 adap
= netdev2adap(dev
);
3462 memset(&c
, 0, sizeof(c
));
3463 c
.op_to_write
= htonl(FW_CMD_OP(FW_CLIP_CMD
) |
3464 FW_CMD_REQUEST
| FW_CMD_WRITE
);
3465 c
.alloc_to_len16
= htonl(F_FW_CLIP_CMD_ALLOC
| FW_LEN16(c
));
3466 c
.ip_hi
= *(__be64
*)(lip
->s6_addr
);
3467 c
.ip_lo
= *(__be64
*)(lip
->s6_addr
+ 8);
3468 return t4_wr_mbox_meat(adap
, adap
->mbox
, &c
, sizeof(c
), &c
, false);
3470 EXPORT_SYMBOL(cxgb4_clip_get
);
3472 int cxgb4_clip_release(const struct net_device
*dev
,
3473 const struct in6_addr
*lip
)
3475 struct adapter
*adap
;
3476 struct fw_clip_cmd c
;
3478 adap
= netdev2adap(dev
);
3479 memset(&c
, 0, sizeof(c
));
3480 c
.op_to_write
= htonl(FW_CMD_OP(FW_CLIP_CMD
) |
3481 FW_CMD_REQUEST
| FW_CMD_READ
);
3482 c
.alloc_to_len16
= htonl(F_FW_CLIP_CMD_FREE
| FW_LEN16(c
));
3483 c
.ip_hi
= *(__be64
*)(lip
->s6_addr
);
3484 c
.ip_lo
= *(__be64
*)(lip
->s6_addr
+ 8);
3485 return t4_wr_mbox_meat(adap
, adap
->mbox
, &c
, sizeof(c
), &c
, false);
3487 EXPORT_SYMBOL(cxgb4_clip_release
);
3490 * cxgb4_create_server - create an IP server
3492 * @stid: the server TID
3493 * @sip: local IP address to bind server to
3494 * @sport: the server's TCP port
3495 * @queue: queue to direct messages from this server to
3497 * Create an IP server for the given port and address.
3498 * Returns <0 on error and one of the %NET_XMIT_* values on success.
3500 int cxgb4_create_server(const struct net_device
*dev
, unsigned int stid
,
3501 __be32 sip
, __be16 sport
, __be16 vlan
,
3505 struct sk_buff
*skb
;
3506 struct adapter
*adap
;
3507 struct cpl_pass_open_req
*req
;
3510 skb
= alloc_skb(sizeof(*req
), GFP_KERNEL
);
3514 adap
= netdev2adap(dev
);
3515 req
= (struct cpl_pass_open_req
*)__skb_put(skb
, sizeof(*req
));
3517 OPCODE_TID(req
) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ
, stid
));
3518 req
->local_port
= sport
;
3519 req
->peer_port
= htons(0);
3520 req
->local_ip
= sip
;
3521 req
->peer_ip
= htonl(0);
3522 chan
= rxq_to_chan(&adap
->sge
, queue
);
3523 req
->opt0
= cpu_to_be64(TX_CHAN(chan
));
3524 req
->opt1
= cpu_to_be64(CONN_POLICY_ASK
|
3525 SYN_RSS_ENABLE
| SYN_RSS_QUEUE(queue
));
3526 ret
= t4_mgmt_tx(adap
, skb
);
3527 return net_xmit_eval(ret
);
3529 EXPORT_SYMBOL(cxgb4_create_server
);
3531 /* cxgb4_create_server6 - create an IPv6 server
3533 * @stid: the server TID
3534 * @sip: local IPv6 address to bind server to
3535 * @sport: the server's TCP port
3536 * @queue: queue to direct messages from this server to
3538 * Create an IPv6 server for the given port and address.
3539 * Returns <0 on error and one of the %NET_XMIT_* values on success.
3541 int cxgb4_create_server6(const struct net_device
*dev
, unsigned int stid
,
3542 const struct in6_addr
*sip
, __be16 sport
,
3546 struct sk_buff
*skb
;
3547 struct adapter
*adap
;
3548 struct cpl_pass_open_req6
*req
;
3551 skb
= alloc_skb(sizeof(*req
), GFP_KERNEL
);
3555 adap
= netdev2adap(dev
);
3556 req
= (struct cpl_pass_open_req6
*)__skb_put(skb
, sizeof(*req
));
3558 OPCODE_TID(req
) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6
, stid
));
3559 req
->local_port
= sport
;
3560 req
->peer_port
= htons(0);
3561 req
->local_ip_hi
= *(__be64
*)(sip
->s6_addr
);
3562 req
->local_ip_lo
= *(__be64
*)(sip
->s6_addr
+ 8);
3563 req
->peer_ip_hi
= cpu_to_be64(0);
3564 req
->peer_ip_lo
= cpu_to_be64(0);
3565 chan
= rxq_to_chan(&adap
->sge
, queue
);
3566 req
->opt0
= cpu_to_be64(TX_CHAN(chan
));
3567 req
->opt1
= cpu_to_be64(CONN_POLICY_ASK
|
3568 SYN_RSS_ENABLE
| SYN_RSS_QUEUE(queue
));
3569 ret
= t4_mgmt_tx(adap
, skb
);
3570 return net_xmit_eval(ret
);
3572 EXPORT_SYMBOL(cxgb4_create_server6
);
3574 int cxgb4_remove_server(const struct net_device
*dev
, unsigned int stid
,
3575 unsigned int queue
, bool ipv6
)
3577 struct sk_buff
*skb
;
3578 struct adapter
*adap
;
3579 struct cpl_close_listsvr_req
*req
;
3582 adap
= netdev2adap(dev
);
3584 skb
= alloc_skb(sizeof(*req
), GFP_KERNEL
);
3588 req
= (struct cpl_close_listsvr_req
*)__skb_put(skb
, sizeof(*req
));
3590 OPCODE_TID(req
) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ
, stid
));
3591 req
->reply_ctrl
= htons(NO_REPLY(0) | (ipv6
? LISTSVR_IPV6(1) :
3592 LISTSVR_IPV6(0)) | QUEUENO(queue
));
3593 ret
= t4_mgmt_tx(adap
, skb
);
3594 return net_xmit_eval(ret
);
3596 EXPORT_SYMBOL(cxgb4_remove_server
);
3599 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
3600 * @mtus: the HW MTU table
3601 * @mtu: the target MTU
3602 * @idx: index of selected entry in the MTU table
3604 * Returns the index and the value in the HW MTU table that is closest to
3605 * but does not exceed @mtu, unless @mtu is smaller than any value in the
3606 * table, in which case that smallest available value is selected.
3608 unsigned int cxgb4_best_mtu(const unsigned short *mtus
, unsigned short mtu
,
3613 while (i
< NMTUS
- 1 && mtus
[i
+ 1] <= mtu
)
3619 EXPORT_SYMBOL(cxgb4_best_mtu
);
3622 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
3623 * @mtus: the HW MTU table
3624 * @header_size: Header Size
3625 * @data_size_max: maximum Data Segment Size
3626 * @data_size_align: desired Data Segment Size Alignment (2^N)
3627 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
3629 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
3630 * MTU Table based solely on a Maximum MTU parameter, we break that
3631 * parameter up into a Header Size and Maximum Data Segment Size, and
3632 * provide a desired Data Segment Size Alignment. If we find an MTU in
3633 * the Hardware MTU Table which will result in a Data Segment Size with
3634 * the requested alignment _and_ that MTU isn't "too far" from the
3635 * closest MTU, then we'll return that rather than the closest MTU.
3637 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus
,
3638 unsigned short header_size
,
3639 unsigned short data_size_max
,
3640 unsigned short data_size_align
,
3641 unsigned int *mtu_idxp
)
3643 unsigned short max_mtu
= header_size
+ data_size_max
;
3644 unsigned short data_size_align_mask
= data_size_align
- 1;
3645 int mtu_idx
, aligned_mtu_idx
;
3647 /* Scan the MTU Table till we find an MTU which is larger than our
3648 * Maximum MTU or we reach the end of the table. Along the way,
3649 * record the last MTU found, if any, which will result in a Data
3650 * Segment Length matching the requested alignment.
3652 for (mtu_idx
= 0, aligned_mtu_idx
= -1; mtu_idx
< NMTUS
; mtu_idx
++) {
3653 unsigned short data_size
= mtus
[mtu_idx
] - header_size
;
3655 /* If this MTU minus the Header Size would result in a
3656 * Data Segment Size of the desired alignment, remember it.
3658 if ((data_size
& data_size_align_mask
) == 0)
3659 aligned_mtu_idx
= mtu_idx
;
3661 /* If we're not at the end of the Hardware MTU Table and the
3662 * next element is larger than our Maximum MTU, drop out of
3665 if (mtu_idx
+1 < NMTUS
&& mtus
[mtu_idx
+1] > max_mtu
)
3669 /* If we fell out of the loop because we ran to the end of the table,
3670 * then we just have to use the last [largest] entry.
3672 if (mtu_idx
== NMTUS
)
3675 /* If we found an MTU which resulted in the requested Data Segment
3676 * Length alignment and that's "not far" from the largest MTU which is
3677 * less than or equal to the maximum MTU, then use that.
3679 if (aligned_mtu_idx
>= 0 &&
3680 mtu_idx
- aligned_mtu_idx
<= 1)
3681 mtu_idx
= aligned_mtu_idx
;
3683 /* If the caller has passed in an MTU Index pointer, pass the
3684 * MTU Index back. Return the MTU value.
3687 *mtu_idxp
= mtu_idx
;
3688 return mtus
[mtu_idx
];
3690 EXPORT_SYMBOL(cxgb4_best_aligned_mtu
);
3693 * cxgb4_port_chan - get the HW channel of a port
3694 * @dev: the net device for the port
3696 * Return the HW Tx channel of the given port.
3698 unsigned int cxgb4_port_chan(const struct net_device
*dev
)
3700 return netdev2pinfo(dev
)->tx_chan
;
3702 EXPORT_SYMBOL(cxgb4_port_chan
);
3704 unsigned int cxgb4_dbfifo_count(const struct net_device
*dev
, int lpfifo
)
3706 struct adapter
*adap
= netdev2adap(dev
);
3707 u32 v1
, v2
, lp_count
, hp_count
;
3709 v1
= t4_read_reg(adap
, A_SGE_DBFIFO_STATUS
);
3710 v2
= t4_read_reg(adap
, SGE_DBFIFO_STATUS2
);
3711 if (is_t4(adap
->params
.chip
)) {
3712 lp_count
= G_LP_COUNT(v1
);
3713 hp_count
= G_HP_COUNT(v1
);
3715 lp_count
= G_LP_COUNT_T5(v1
);
3716 hp_count
= G_HP_COUNT_T5(v2
);
3718 return lpfifo
? lp_count
: hp_count
;
3720 EXPORT_SYMBOL(cxgb4_dbfifo_count
);
3723 * cxgb4_port_viid - get the VI id of a port
3724 * @dev: the net device for the port
3726 * Return the VI id of the given port.
3728 unsigned int cxgb4_port_viid(const struct net_device
*dev
)
3730 return netdev2pinfo(dev
)->viid
;
3732 EXPORT_SYMBOL(cxgb4_port_viid
);
3735 * cxgb4_port_idx - get the index of a port
3736 * @dev: the net device for the port
3738 * Return the index of the given port.
3740 unsigned int cxgb4_port_idx(const struct net_device
*dev
)
3742 return netdev2pinfo(dev
)->port_id
;
3744 EXPORT_SYMBOL(cxgb4_port_idx
);
3746 void cxgb4_get_tcp_stats(struct pci_dev
*pdev
, struct tp_tcp_stats
*v4
,
3747 struct tp_tcp_stats
*v6
)
3749 struct adapter
*adap
= pci_get_drvdata(pdev
);
3751 spin_lock(&adap
->stats_lock
);
3752 t4_tp_get_tcp_stats(adap
, v4
, v6
);
3753 spin_unlock(&adap
->stats_lock
);
3755 EXPORT_SYMBOL(cxgb4_get_tcp_stats
);
3757 void cxgb4_iscsi_init(struct net_device
*dev
, unsigned int tag_mask
,
3758 const unsigned int *pgsz_order
)
3760 struct adapter
*adap
= netdev2adap(dev
);
3762 t4_write_reg(adap
, ULP_RX_ISCSI_TAGMASK
, tag_mask
);
3763 t4_write_reg(adap
, ULP_RX_ISCSI_PSZ
, HPZ0(pgsz_order
[0]) |
3764 HPZ1(pgsz_order
[1]) | HPZ2(pgsz_order
[2]) |
3765 HPZ3(pgsz_order
[3]));
3767 EXPORT_SYMBOL(cxgb4_iscsi_init
);
3769 int cxgb4_flush_eq_cache(struct net_device
*dev
)
3771 struct adapter
*adap
= netdev2adap(dev
);
3774 ret
= t4_fwaddrspace_write(adap
, adap
->mbox
,
3775 0xe1000000 + A_SGE_CTXT_CMD
, 0x20000000);
3778 EXPORT_SYMBOL(cxgb4_flush_eq_cache
);
3780 static int read_eq_indices(struct adapter
*adap
, u16 qid
, u16
*pidx
, u16
*cidx
)
3782 u32 addr
= t4_read_reg(adap
, A_SGE_DBQ_CTXT_BADDR
) + 24 * qid
+ 8;
3786 spin_lock(&adap
->win0_lock
);
3787 ret
= t4_memory_rw(adap
, 0, MEM_EDC0
, addr
,
3788 sizeof(indices
), (__be32
*)&indices
,
3790 spin_unlock(&adap
->win0_lock
);
3792 *cidx
= (be64_to_cpu(indices
) >> 25) & 0xffff;
3793 *pidx
= (be64_to_cpu(indices
) >> 9) & 0xffff;
3798 int cxgb4_sync_txq_pidx(struct net_device
*dev
, u16 qid
, u16 pidx
,
3801 struct adapter
*adap
= netdev2adap(dev
);
3802 u16 hw_pidx
, hw_cidx
;
3805 ret
= read_eq_indices(adap
, qid
, &hw_pidx
, &hw_cidx
);
3809 if (pidx
!= hw_pidx
) {
3812 if (pidx
>= hw_pidx
)
3813 delta
= pidx
- hw_pidx
;
3815 delta
= size
- hw_pidx
+ pidx
;
3817 t4_write_reg(adap
, MYPF_REG(SGE_PF_KDOORBELL
),
3818 QID(qid
) | PIDX(delta
));
3823 EXPORT_SYMBOL(cxgb4_sync_txq_pidx
);
3825 void cxgb4_disable_db_coalescing(struct net_device
*dev
)
3827 struct adapter
*adap
;
3829 adap
= netdev2adap(dev
);
3830 t4_set_reg_field(adap
, A_SGE_DOORBELL_CONTROL
, F_NOCOALESCE
,
3833 EXPORT_SYMBOL(cxgb4_disable_db_coalescing
);
3835 void cxgb4_enable_db_coalescing(struct net_device
*dev
)
3837 struct adapter
*adap
;
3839 adap
= netdev2adap(dev
);
3840 t4_set_reg_field(adap
, A_SGE_DOORBELL_CONTROL
, F_NOCOALESCE
, 0);
3842 EXPORT_SYMBOL(cxgb4_enable_db_coalescing
);
3844 int cxgb4_read_tpte(struct net_device
*dev
, u32 stag
, __be32
*tpte
)
3846 struct adapter
*adap
;
3847 u32 offset
, memtype
, memaddr
;
3848 u32 edc0_size
, edc1_size
, mc0_size
, mc1_size
;
3849 u32 edc0_end
, edc1_end
, mc0_end
, mc1_end
;
3852 adap
= netdev2adap(dev
);
3854 offset
= ((stag
>> 8) * 32) + adap
->vres
.stag
.start
;
3856 /* Figure out where the offset lands in the Memory Type/Address scheme.
3857 * This code assumes that the memory is laid out starting at offset 0
3858 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
3859 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
3860 * MC0, and some have both MC0 and MC1.
3862 edc0_size
= EDRAM_SIZE_GET(t4_read_reg(adap
, MA_EDRAM0_BAR
)) << 20;
3863 edc1_size
= EDRAM_SIZE_GET(t4_read_reg(adap
, MA_EDRAM1_BAR
)) << 20;
3864 mc0_size
= EXT_MEM_SIZE_GET(t4_read_reg(adap
, MA_EXT_MEMORY_BAR
)) << 20;
3866 edc0_end
= edc0_size
;
3867 edc1_end
= edc0_end
+ edc1_size
;
3868 mc0_end
= edc1_end
+ mc0_size
;
3870 if (offset
< edc0_end
) {
3873 } else if (offset
< edc1_end
) {
3875 memaddr
= offset
- edc0_end
;
3877 if (offset
< mc0_end
) {
3879 memaddr
= offset
- edc1_end
;
3880 } else if (is_t4(adap
->params
.chip
)) {
3881 /* T4 only has a single memory channel */
3884 mc1_size
= EXT_MEM_SIZE_GET(
3886 MA_EXT_MEMORY1_BAR
)) << 20;
3887 mc1_end
= mc0_end
+ mc1_size
;
3888 if (offset
< mc1_end
) {
3890 memaddr
= offset
- mc0_end
;
3892 /* offset beyond the end of any memory */
3898 spin_lock(&adap
->win0_lock
);
3899 ret
= t4_memory_rw(adap
, 0, memtype
, memaddr
, 32, tpte
, T4_MEMORY_READ
);
3900 spin_unlock(&adap
->win0_lock
);
3904 dev_err(adap
->pdev_dev
, "stag %#x, offset %#x out of range\n",
3908 EXPORT_SYMBOL(cxgb4_read_tpte
);
3910 u64
cxgb4_read_sge_timestamp(struct net_device
*dev
)
3913 struct adapter
*adap
;
3915 adap
= netdev2adap(dev
);
3916 lo
= t4_read_reg(adap
, SGE_TIMESTAMP_LO
);
3917 hi
= GET_TSVAL(t4_read_reg(adap
, SGE_TIMESTAMP_HI
));
3919 return ((u64
)hi
<< 32) | (u64
)lo
;
3921 EXPORT_SYMBOL(cxgb4_read_sge_timestamp
);
3923 static struct pci_driver cxgb4_driver
;
3925 static void check_neigh_update(struct neighbour
*neigh
)
3927 const struct device
*parent
;
3928 const struct net_device
*netdev
= neigh
->dev
;
3930 if (netdev
->priv_flags
& IFF_802_1Q_VLAN
)
3931 netdev
= vlan_dev_real_dev(netdev
);
3932 parent
= netdev
->dev
.parent
;
3933 if (parent
&& parent
->driver
== &cxgb4_driver
.driver
)
3934 t4_l2t_update(dev_get_drvdata(parent
), neigh
);
3937 static int netevent_cb(struct notifier_block
*nb
, unsigned long event
,
3941 case NETEVENT_NEIGH_UPDATE
:
3942 check_neigh_update(data
);
3944 case NETEVENT_REDIRECT
:
3951 static bool netevent_registered
;
3952 static struct notifier_block cxgb4_netevent_nb
= {
3953 .notifier_call
= netevent_cb
3956 static void drain_db_fifo(struct adapter
*adap
, int usecs
)
3958 u32 v1
, v2
, lp_count
, hp_count
;
3961 v1
= t4_read_reg(adap
, A_SGE_DBFIFO_STATUS
);
3962 v2
= t4_read_reg(adap
, SGE_DBFIFO_STATUS2
);
3963 if (is_t4(adap
->params
.chip
)) {
3964 lp_count
= G_LP_COUNT(v1
);
3965 hp_count
= G_HP_COUNT(v1
);
3967 lp_count
= G_LP_COUNT_T5(v1
);
3968 hp_count
= G_HP_COUNT_T5(v2
);
3971 if (lp_count
== 0 && hp_count
== 0)
3973 set_current_state(TASK_UNINTERRUPTIBLE
);
3974 schedule_timeout(usecs_to_jiffies(usecs
));
3978 static void disable_txq_db(struct sge_txq
*q
)
3980 unsigned long flags
;
3982 spin_lock_irqsave(&q
->db_lock
, flags
);
3984 spin_unlock_irqrestore(&q
->db_lock
, flags
);
3987 static void enable_txq_db(struct adapter
*adap
, struct sge_txq
*q
)
3989 spin_lock_irq(&q
->db_lock
);
3990 if (q
->db_pidx_inc
) {
3991 /* Make sure that all writes to the TX descriptors
3992 * are committed before we tell HW about them.
3995 t4_write_reg(adap
, MYPF_REG(SGE_PF_KDOORBELL
),
3996 QID(q
->cntxt_id
) | PIDX(q
->db_pidx_inc
));
4000 spin_unlock_irq(&q
->db_lock
);
4003 static void disable_dbs(struct adapter
*adap
)
4007 for_each_ethrxq(&adap
->sge
, i
)
4008 disable_txq_db(&adap
->sge
.ethtxq
[i
].q
);
4009 for_each_ofldrxq(&adap
->sge
, i
)
4010 disable_txq_db(&adap
->sge
.ofldtxq
[i
].q
);
4011 for_each_port(adap
, i
)
4012 disable_txq_db(&adap
->sge
.ctrlq
[i
].q
);
4015 static void enable_dbs(struct adapter
*adap
)
4019 for_each_ethrxq(&adap
->sge
, i
)
4020 enable_txq_db(adap
, &adap
->sge
.ethtxq
[i
].q
);
4021 for_each_ofldrxq(&adap
->sge
, i
)
4022 enable_txq_db(adap
, &adap
->sge
.ofldtxq
[i
].q
);
4023 for_each_port(adap
, i
)
4024 enable_txq_db(adap
, &adap
->sge
.ctrlq
[i
].q
);
4027 static void notify_rdma_uld(struct adapter
*adap
, enum cxgb4_control cmd
)
4029 if (adap
->uld_handle
[CXGB4_ULD_RDMA
])
4030 ulds
[CXGB4_ULD_RDMA
].control(adap
->uld_handle
[CXGB4_ULD_RDMA
],
4034 static void process_db_full(struct work_struct
*work
)
4036 struct adapter
*adap
;
4038 adap
= container_of(work
, struct adapter
, db_full_task
);
4040 drain_db_fifo(adap
, dbfifo_drain_delay
);
4042 notify_rdma_uld(adap
, CXGB4_CONTROL_DB_EMPTY
);
4043 t4_set_reg_field(adap
, SGE_INT_ENABLE3
,
4044 DBFIFO_HP_INT
| DBFIFO_LP_INT
,
4045 DBFIFO_HP_INT
| DBFIFO_LP_INT
);
4048 static void sync_txq_pidx(struct adapter
*adap
, struct sge_txq
*q
)
4050 u16 hw_pidx
, hw_cidx
;
4053 spin_lock_irq(&q
->db_lock
);
4054 ret
= read_eq_indices(adap
, (u16
)q
->cntxt_id
, &hw_pidx
, &hw_cidx
);
4057 if (q
->db_pidx
!= hw_pidx
) {
4060 if (q
->db_pidx
>= hw_pidx
)
4061 delta
= q
->db_pidx
- hw_pidx
;
4063 delta
= q
->size
- hw_pidx
+ q
->db_pidx
;
4065 t4_write_reg(adap
, MYPF_REG(SGE_PF_KDOORBELL
),
4066 QID(q
->cntxt_id
) | PIDX(delta
));
4071 spin_unlock_irq(&q
->db_lock
);
4073 CH_WARN(adap
, "DB drop recovery failed.\n");
4075 static void recover_all_queues(struct adapter
*adap
)
4079 for_each_ethrxq(&adap
->sge
, i
)
4080 sync_txq_pidx(adap
, &adap
->sge
.ethtxq
[i
].q
);
4081 for_each_ofldrxq(&adap
->sge
, i
)
4082 sync_txq_pidx(adap
, &adap
->sge
.ofldtxq
[i
].q
);
4083 for_each_port(adap
, i
)
4084 sync_txq_pidx(adap
, &adap
->sge
.ctrlq
[i
].q
);
4087 static void process_db_drop(struct work_struct
*work
)
4089 struct adapter
*adap
;
4091 adap
= container_of(work
, struct adapter
, db_drop_task
);
4093 if (is_t4(adap
->params
.chip
)) {
4094 drain_db_fifo(adap
, dbfifo_drain_delay
);
4095 notify_rdma_uld(adap
, CXGB4_CONTROL_DB_DROP
);
4096 drain_db_fifo(adap
, dbfifo_drain_delay
);
4097 recover_all_queues(adap
);
4098 drain_db_fifo(adap
, dbfifo_drain_delay
);
4100 notify_rdma_uld(adap
, CXGB4_CONTROL_DB_EMPTY
);
4102 u32 dropped_db
= t4_read_reg(adap
, 0x010ac);
4103 u16 qid
= (dropped_db
>> 15) & 0x1ffff;
4104 u16 pidx_inc
= dropped_db
& 0x1fff;
4106 unsigned short udb_density
;
4107 unsigned long qpshift
;
4111 dev_warn(adap
->pdev_dev
,
4112 "Dropped DB 0x%x qid %d bar2 %d coalesce %d pidx %d\n",
4114 (dropped_db
>> 14) & 1,
4115 (dropped_db
>> 13) & 1,
4118 drain_db_fifo(adap
, 1);
4120 s_qpp
= QUEUESPERPAGEPF1
* adap
->fn
;
4121 udb_density
= 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adap
,
4122 SGE_EGRESS_QUEUES_PER_PAGE_PF
) >> s_qpp
);
4123 qpshift
= PAGE_SHIFT
- ilog2(udb_density
);
4124 udb
= qid
<< qpshift
;
4126 page
= udb
/ PAGE_SIZE
;
4127 udb
+= (qid
- (page
* udb_density
)) * 128;
4129 writel(PIDX(pidx_inc
), adap
->bar2
+ udb
+ 8);
4131 /* Re-enable BAR2 WC */
4132 t4_set_reg_field(adap
, 0x10b0, 1<<15, 1<<15);
4135 t4_set_reg_field(adap
, A_SGE_DOORBELL_CONTROL
, F_DROPPED_DB
, 0);
4138 void t4_db_full(struct adapter
*adap
)
4140 if (is_t4(adap
->params
.chip
)) {
4142 notify_rdma_uld(adap
, CXGB4_CONTROL_DB_FULL
);
4143 t4_set_reg_field(adap
, SGE_INT_ENABLE3
,
4144 DBFIFO_HP_INT
| DBFIFO_LP_INT
, 0);
4145 queue_work(adap
->workq
, &adap
->db_full_task
);
4149 void t4_db_dropped(struct adapter
*adap
)
4151 if (is_t4(adap
->params
.chip
)) {
4153 notify_rdma_uld(adap
, CXGB4_CONTROL_DB_FULL
);
4155 queue_work(adap
->workq
, &adap
->db_drop_task
);
4158 static void uld_attach(struct adapter
*adap
, unsigned int uld
)
4161 struct cxgb4_lld_info lli
;
4164 lli
.pdev
= adap
->pdev
;
4166 lli
.l2t
= adap
->l2t
;
4167 lli
.tids
= &adap
->tids
;
4168 lli
.ports
= adap
->port
;
4169 lli
.vr
= &adap
->vres
;
4170 lli
.mtus
= adap
->params
.mtus
;
4171 if (uld
== CXGB4_ULD_RDMA
) {
4172 lli
.rxq_ids
= adap
->sge
.rdma_rxq
;
4173 lli
.ciq_ids
= adap
->sge
.rdma_ciq
;
4174 lli
.nrxq
= adap
->sge
.rdmaqs
;
4175 lli
.nciq
= adap
->sge
.rdmaciqs
;
4176 } else if (uld
== CXGB4_ULD_ISCSI
) {
4177 lli
.rxq_ids
= adap
->sge
.ofld_rxq
;
4178 lli
.nrxq
= adap
->sge
.ofldqsets
;
4180 lli
.ntxq
= adap
->sge
.ofldqsets
;
4181 lli
.nchan
= adap
->params
.nports
;
4182 lli
.nports
= adap
->params
.nports
;
4183 lli
.wr_cred
= adap
->params
.ofldq_wr_cred
;
4184 lli
.adapter_type
= adap
->params
.chip
;
4185 lli
.iscsi_iolen
= MAXRXDATA_GET(t4_read_reg(adap
, TP_PARA_REG2
));
4186 lli
.cclk_ps
= 1000000000 / adap
->params
.vpd
.cclk
;
4187 lli
.udb_density
= 1 << QUEUESPERPAGEPF0_GET(
4188 t4_read_reg(adap
, SGE_EGRESS_QUEUES_PER_PAGE_PF
) >>
4190 lli
.ucq_density
= 1 << QUEUESPERPAGEPF0_GET(
4191 t4_read_reg(adap
, SGE_INGRESS_QUEUES_PER_PAGE_PF
) >>
4193 lli
.filt_mode
= adap
->params
.tp
.vlan_pri_map
;
4194 /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
4195 for (i
= 0; i
< NCHAN
; i
++)
4197 lli
.gts_reg
= adap
->regs
+ MYPF_REG(SGE_PF_GTS
);
4198 lli
.db_reg
= adap
->regs
+ MYPF_REG(SGE_PF_KDOORBELL
);
4199 lli
.fw_vers
= adap
->params
.fw_vers
;
4200 lli
.dbfifo_int_thresh
= dbfifo_int_thresh
;
4201 lli
.sge_ingpadboundary
= adap
->sge
.fl_align
;
4202 lli
.sge_egrstatuspagesize
= adap
->sge
.stat_len
;
4203 lli
.sge_pktshift
= adap
->sge
.pktshift
;
4204 lli
.enable_fw_ofld_conn
= adap
->flags
& FW_OFLD_CONN
;
4205 lli
.max_ordird_qp
= adap
->params
.max_ordird_qp
;
4206 lli
.max_ird_adapter
= adap
->params
.max_ird_adapter
;
4207 lli
.ulptx_memwrite_dsgl
= adap
->params
.ulptx_memwrite_dsgl
;
4209 handle
= ulds
[uld
].add(&lli
);
4210 if (IS_ERR(handle
)) {
4211 dev_warn(adap
->pdev_dev
,
4212 "could not attach to the %s driver, error %ld\n",
4213 uld_str
[uld
], PTR_ERR(handle
));
4217 adap
->uld_handle
[uld
] = handle
;
4219 if (!netevent_registered
) {
4220 register_netevent_notifier(&cxgb4_netevent_nb
);
4221 netevent_registered
= true;
4224 if (adap
->flags
& FULL_INIT_DONE
)
4225 ulds
[uld
].state_change(handle
, CXGB4_STATE_UP
);
4228 static void attach_ulds(struct adapter
*adap
)
4232 spin_lock(&adap_rcu_lock
);
4233 list_add_tail_rcu(&adap
->rcu_node
, &adap_rcu_list
);
4234 spin_unlock(&adap_rcu_lock
);
4236 mutex_lock(&uld_mutex
);
4237 list_add_tail(&adap
->list_node
, &adapter_list
);
4238 for (i
= 0; i
< CXGB4_ULD_MAX
; i
++)
4240 uld_attach(adap
, i
);
4241 mutex_unlock(&uld_mutex
);
4244 static void detach_ulds(struct adapter
*adap
)
4248 mutex_lock(&uld_mutex
);
4249 list_del(&adap
->list_node
);
4250 for (i
= 0; i
< CXGB4_ULD_MAX
; i
++)
4251 if (adap
->uld_handle
[i
]) {
4252 ulds
[i
].state_change(adap
->uld_handle
[i
],
4253 CXGB4_STATE_DETACH
);
4254 adap
->uld_handle
[i
] = NULL
;
4256 if (netevent_registered
&& list_empty(&adapter_list
)) {
4257 unregister_netevent_notifier(&cxgb4_netevent_nb
);
4258 netevent_registered
= false;
4260 mutex_unlock(&uld_mutex
);
4262 spin_lock(&adap_rcu_lock
);
4263 list_del_rcu(&adap
->rcu_node
);
4264 spin_unlock(&adap_rcu_lock
);
4267 static void notify_ulds(struct adapter
*adap
, enum cxgb4_state new_state
)
4271 mutex_lock(&uld_mutex
);
4272 for (i
= 0; i
< CXGB4_ULD_MAX
; i
++)
4273 if (adap
->uld_handle
[i
])
4274 ulds
[i
].state_change(adap
->uld_handle
[i
], new_state
);
4275 mutex_unlock(&uld_mutex
);
4279 * cxgb4_register_uld - register an upper-layer driver
4280 * @type: the ULD type
4281 * @p: the ULD methods
4283 * Registers an upper-layer driver with this driver and notifies the ULD
4284 * about any presently available devices that support its type. Returns
4285 * %-EBUSY if a ULD of the same type is already registered.
4287 int cxgb4_register_uld(enum cxgb4_uld type
, const struct cxgb4_uld_info
*p
)
4290 struct adapter
*adap
;
4292 if (type
>= CXGB4_ULD_MAX
)
4294 mutex_lock(&uld_mutex
);
4295 if (ulds
[type
].add
) {
4300 list_for_each_entry(adap
, &adapter_list
, list_node
)
4301 uld_attach(adap
, type
);
4302 out
: mutex_unlock(&uld_mutex
);
4305 EXPORT_SYMBOL(cxgb4_register_uld
);
4308 * cxgb4_unregister_uld - unregister an upper-layer driver
4309 * @type: the ULD type
4311 * Unregisters an existing upper-layer driver.
4313 int cxgb4_unregister_uld(enum cxgb4_uld type
)
4315 struct adapter
*adap
;
4317 if (type
>= CXGB4_ULD_MAX
)
4319 mutex_lock(&uld_mutex
);
4320 list_for_each_entry(adap
, &adapter_list
, list_node
)
4321 adap
->uld_handle
[type
] = NULL
;
4322 ulds
[type
].add
= NULL
;
4323 mutex_unlock(&uld_mutex
);
4326 EXPORT_SYMBOL(cxgb4_unregister_uld
);
4328 /* Check if netdev on which event is occured belongs to us or not. Return
4329 * success (true) if it belongs otherwise failure (false).
4330 * Called with rcu_read_lock() held.
4332 static bool cxgb4_netdev(const struct net_device
*netdev
)
4334 struct adapter
*adap
;
4337 list_for_each_entry_rcu(adap
, &adap_rcu_list
, rcu_node
)
4338 for (i
= 0; i
< MAX_NPORTS
; i
++)
4339 if (adap
->port
[i
] == netdev
)
4344 static int clip_add(struct net_device
*event_dev
, struct inet6_ifaddr
*ifa
,
4345 unsigned long event
)
4347 int ret
= NOTIFY_DONE
;
4350 if (cxgb4_netdev(event_dev
)) {
4353 ret
= cxgb4_clip_get(event_dev
,
4354 (const struct in6_addr
*)ifa
->addr
.s6_addr
);
4362 cxgb4_clip_release(event_dev
,
4363 (const struct in6_addr
*)ifa
->addr
.s6_addr
);
4374 static int cxgb4_inet6addr_handler(struct notifier_block
*this,
4375 unsigned long event
, void *data
)
4377 struct inet6_ifaddr
*ifa
= data
;
4378 struct net_device
*event_dev
;
4379 int ret
= NOTIFY_DONE
;
4380 struct bonding
*bond
= netdev_priv(ifa
->idev
->dev
);
4381 struct list_head
*iter
;
4382 struct slave
*slave
;
4383 struct pci_dev
*first_pdev
= NULL
;
4385 if (ifa
->idev
->dev
->priv_flags
& IFF_802_1Q_VLAN
) {
4386 event_dev
= vlan_dev_real_dev(ifa
->idev
->dev
);
4387 ret
= clip_add(event_dev
, ifa
, event
);
4388 } else if (ifa
->idev
->dev
->flags
& IFF_MASTER
) {
4389 /* It is possible that two different adapters are bonded in one
4390 * bond. We need to find such different adapters and add clip
4391 * in all of them only once.
4393 read_lock(&bond
->lock
);
4394 bond_for_each_slave(bond
, slave
, iter
) {
4396 ret
= clip_add(slave
->dev
, ifa
, event
);
4397 /* If clip_add is success then only initialize
4398 * first_pdev since it means it is our device
4400 if (ret
== NOTIFY_OK
)
4401 first_pdev
= to_pci_dev(
4402 slave
->dev
->dev
.parent
);
4403 } else if (first_pdev
!=
4404 to_pci_dev(slave
->dev
->dev
.parent
))
4405 ret
= clip_add(slave
->dev
, ifa
, event
);
4407 read_unlock(&bond
->lock
);
4409 ret
= clip_add(ifa
->idev
->dev
, ifa
, event
);
4414 static struct notifier_block cxgb4_inet6addr_notifier
= {
4415 .notifier_call
= cxgb4_inet6addr_handler
4418 /* Retrieves IPv6 addresses from a root device (bond, vlan) associated with
4419 * a physical device.
4420 * The physical device reference is needed to send the actul CLIP command.
4422 static int update_dev_clip(struct net_device
*root_dev
, struct net_device
*dev
)
4424 struct inet6_dev
*idev
= NULL
;
4425 struct inet6_ifaddr
*ifa
;
4428 idev
= __in6_dev_get(root_dev
);
4432 read_lock_bh(&idev
->lock
);
4433 list_for_each_entry(ifa
, &idev
->addr_list
, if_list
) {
4434 ret
= cxgb4_clip_get(dev
,
4435 (const struct in6_addr
*)ifa
->addr
.s6_addr
);
4439 read_unlock_bh(&idev
->lock
);
4444 static int update_root_dev_clip(struct net_device
*dev
)
4446 struct net_device
*root_dev
= NULL
;
4449 /* First populate the real net device's IPv6 addresses */
4450 ret
= update_dev_clip(dev
, dev
);
4454 /* Parse all bond and vlan devices layered on top of the physical dev */
4455 for (i
= 0; i
< VLAN_N_VID
; i
++) {
4456 root_dev
= __vlan_find_dev_deep_rcu(dev
, htons(ETH_P_8021Q
), i
);
4460 ret
= update_dev_clip(root_dev
, dev
);
4467 static void update_clip(const struct adapter
*adap
)
4470 struct net_device
*dev
;
4475 for (i
= 0; i
< MAX_NPORTS
; i
++) {
4476 dev
= adap
->port
[i
];
4480 ret
= update_root_dev_clip(dev
);
4489 * cxgb_up - enable the adapter
4490 * @adap: adapter being enabled
4492 * Called when the first port is enabled, this function performs the
4493 * actions necessary to make an adapter operational, such as completing
4494 * the initialization of HW modules, and enabling interrupts.
4496 * Must be called with the rtnl lock held.
4498 static int cxgb_up(struct adapter
*adap
)
4502 err
= setup_sge_queues(adap
);
4505 err
= setup_rss(adap
);
4509 if (adap
->flags
& USING_MSIX
) {
4510 name_msix_vecs(adap
);
4511 err
= request_irq(adap
->msix_info
[0].vec
, t4_nondata_intr
, 0,
4512 adap
->msix_info
[0].desc
, adap
);
4516 err
= request_msix_queue_irqs(adap
);
4518 free_irq(adap
->msix_info
[0].vec
, adap
);
4522 err
= request_irq(adap
->pdev
->irq
, t4_intr_handler(adap
),
4523 (adap
->flags
& USING_MSI
) ? 0 : IRQF_SHARED
,
4524 adap
->port
[0]->name
, adap
);
4530 t4_intr_enable(adap
);
4531 adap
->flags
|= FULL_INIT_DONE
;
4532 notify_ulds(adap
, CXGB4_STATE_UP
);
4537 dev_err(adap
->pdev_dev
, "request_irq failed, err %d\n", err
);
4539 t4_free_sge_resources(adap
);
4543 static void cxgb_down(struct adapter
*adapter
)
4545 t4_intr_disable(adapter
);
4546 cancel_work_sync(&adapter
->tid_release_task
);
4547 cancel_work_sync(&adapter
->db_full_task
);
4548 cancel_work_sync(&adapter
->db_drop_task
);
4549 adapter
->tid_release_task_busy
= false;
4550 adapter
->tid_release_head
= NULL
;
4552 if (adapter
->flags
& USING_MSIX
) {
4553 free_msix_queue_irqs(adapter
);
4554 free_irq(adapter
->msix_info
[0].vec
, adapter
);
4556 free_irq(adapter
->pdev
->irq
, adapter
);
4557 quiesce_rx(adapter
);
4558 t4_sge_stop(adapter
);
4559 t4_free_sge_resources(adapter
);
4560 adapter
->flags
&= ~FULL_INIT_DONE
;
4564 * net_device operations
4566 static int cxgb_open(struct net_device
*dev
)
4569 struct port_info
*pi
= netdev_priv(dev
);
4570 struct adapter
*adapter
= pi
->adapter
;
4572 netif_carrier_off(dev
);
4574 if (!(adapter
->flags
& FULL_INIT_DONE
)) {
4575 err
= cxgb_up(adapter
);
4580 err
= link_start(dev
);
4582 netif_tx_start_all_queues(dev
);
4586 static int cxgb_close(struct net_device
*dev
)
4588 struct port_info
*pi
= netdev_priv(dev
);
4589 struct adapter
*adapter
= pi
->adapter
;
4591 netif_tx_stop_all_queues(dev
);
4592 netif_carrier_off(dev
);
4593 return t4_enable_vi(adapter
, adapter
->fn
, pi
->viid
, false, false);
4596 /* Return an error number if the indicated filter isn't writable ...
4598 static int writable_filter(struct filter_entry
*f
)
4608 /* Delete the filter at the specified index (if valid). The checks for all
4609 * the common problems with doing this like the filter being locked, currently
4610 * pending in another operation, etc.
4612 static int delete_filter(struct adapter
*adapter
, unsigned int fidx
)
4614 struct filter_entry
*f
;
4617 if (fidx
>= adapter
->tids
.nftids
+ adapter
->tids
.nsftids
)
4620 f
= &adapter
->tids
.ftid_tab
[fidx
];
4621 ret
= writable_filter(f
);
4625 return del_filter_wr(adapter
, fidx
);
4630 int cxgb4_create_server_filter(const struct net_device
*dev
, unsigned int stid
,
4631 __be32 sip
, __be16 sport
, __be16 vlan
,
4632 unsigned int queue
, unsigned char port
, unsigned char mask
)
4635 struct filter_entry
*f
;
4636 struct adapter
*adap
;
4640 adap
= netdev2adap(dev
);
4642 /* Adjust stid to correct filter index */
4643 stid
-= adap
->tids
.sftid_base
;
4644 stid
+= adap
->tids
.nftids
;
4646 /* Check to make sure the filter requested is writable ...
4648 f
= &adap
->tids
.ftid_tab
[stid
];
4649 ret
= writable_filter(f
);
4653 /* Clear out any old resources being used by the filter before
4654 * we start constructing the new filter.
4657 clear_filter(adap
, f
);
4659 /* Clear out filter specifications */
4660 memset(&f
->fs
, 0, sizeof(struct ch_filter_specification
));
4661 f
->fs
.val
.lport
= cpu_to_be16(sport
);
4662 f
->fs
.mask
.lport
= ~0;
4664 if ((val
[0] | val
[1] | val
[2] | val
[3]) != 0) {
4665 for (i
= 0; i
< 4; i
++) {
4666 f
->fs
.val
.lip
[i
] = val
[i
];
4667 f
->fs
.mask
.lip
[i
] = ~0;
4669 if (adap
->params
.tp
.vlan_pri_map
& F_PORT
) {
4670 f
->fs
.val
.iport
= port
;
4671 f
->fs
.mask
.iport
= mask
;
4675 if (adap
->params
.tp
.vlan_pri_map
& F_PROTOCOL
) {
4676 f
->fs
.val
.proto
= IPPROTO_TCP
;
4677 f
->fs
.mask
.proto
= ~0;
4682 /* Mark filter as locked */
4686 ret
= set_filter_wr(adap
, stid
);
4688 clear_filter(adap
, f
);
4694 EXPORT_SYMBOL(cxgb4_create_server_filter
);
4696 int cxgb4_remove_server_filter(const struct net_device
*dev
, unsigned int stid
,
4697 unsigned int queue
, bool ipv6
)
4700 struct filter_entry
*f
;
4701 struct adapter
*adap
;
4703 adap
= netdev2adap(dev
);
4705 /* Adjust stid to correct filter index */
4706 stid
-= adap
->tids
.sftid_base
;
4707 stid
+= adap
->tids
.nftids
;
4709 f
= &adap
->tids
.ftid_tab
[stid
];
4710 /* Unlock the filter */
4713 ret
= delete_filter(adap
, stid
);
4719 EXPORT_SYMBOL(cxgb4_remove_server_filter
);
4721 static struct rtnl_link_stats64
*cxgb_get_stats(struct net_device
*dev
,
4722 struct rtnl_link_stats64
*ns
)
4724 struct port_stats stats
;
4725 struct port_info
*p
= netdev_priv(dev
);
4726 struct adapter
*adapter
= p
->adapter
;
4728 /* Block retrieving statistics during EEH error
4729 * recovery. Otherwise, the recovery might fail
4730 * and the PCI device will be removed permanently
4732 spin_lock(&adapter
->stats_lock
);
4733 if (!netif_device_present(dev
)) {
4734 spin_unlock(&adapter
->stats_lock
);
4737 t4_get_port_stats(adapter
, p
->tx_chan
, &stats
);
4738 spin_unlock(&adapter
->stats_lock
);
4740 ns
->tx_bytes
= stats
.tx_octets
;
4741 ns
->tx_packets
= stats
.tx_frames
;
4742 ns
->rx_bytes
= stats
.rx_octets
;
4743 ns
->rx_packets
= stats
.rx_frames
;
4744 ns
->multicast
= stats
.rx_mcast_frames
;
4746 /* detailed rx_errors */
4747 ns
->rx_length_errors
= stats
.rx_jabber
+ stats
.rx_too_long
+
4749 ns
->rx_over_errors
= 0;
4750 ns
->rx_crc_errors
= stats
.rx_fcs_err
;
4751 ns
->rx_frame_errors
= stats
.rx_symbol_err
;
4752 ns
->rx_fifo_errors
= stats
.rx_ovflow0
+ stats
.rx_ovflow1
+
4753 stats
.rx_ovflow2
+ stats
.rx_ovflow3
+
4754 stats
.rx_trunc0
+ stats
.rx_trunc1
+
4755 stats
.rx_trunc2
+ stats
.rx_trunc3
;
4756 ns
->rx_missed_errors
= 0;
4758 /* detailed tx_errors */
4759 ns
->tx_aborted_errors
= 0;
4760 ns
->tx_carrier_errors
= 0;
4761 ns
->tx_fifo_errors
= 0;
4762 ns
->tx_heartbeat_errors
= 0;
4763 ns
->tx_window_errors
= 0;
4765 ns
->tx_errors
= stats
.tx_error_frames
;
4766 ns
->rx_errors
= stats
.rx_symbol_err
+ stats
.rx_fcs_err
+
4767 ns
->rx_length_errors
+ stats
.rx_len_err
+ ns
->rx_fifo_errors
;
4771 static int cxgb_ioctl(struct net_device
*dev
, struct ifreq
*req
, int cmd
)
4774 int ret
= 0, prtad
, devad
;
4775 struct port_info
*pi
= netdev_priv(dev
);
4776 struct mii_ioctl_data
*data
= (struct mii_ioctl_data
*)&req
->ifr_data
;
4780 if (pi
->mdio_addr
< 0)
4782 data
->phy_id
= pi
->mdio_addr
;
4786 if (mdio_phy_id_is_c45(data
->phy_id
)) {
4787 prtad
= mdio_phy_id_prtad(data
->phy_id
);
4788 devad
= mdio_phy_id_devad(data
->phy_id
);
4789 } else if (data
->phy_id
< 32) {
4790 prtad
= data
->phy_id
;
4792 data
->reg_num
&= 0x1f;
4796 mbox
= pi
->adapter
->fn
;
4797 if (cmd
== SIOCGMIIREG
)
4798 ret
= t4_mdio_rd(pi
->adapter
, mbox
, prtad
, devad
,
4799 data
->reg_num
, &data
->val_out
);
4801 ret
= t4_mdio_wr(pi
->adapter
, mbox
, prtad
, devad
,
4802 data
->reg_num
, data
->val_in
);
4810 static void cxgb_set_rxmode(struct net_device
*dev
)
4812 /* unfortunately we can't return errors to the stack */
4813 set_rxmode(dev
, -1, false);
4816 static int cxgb_change_mtu(struct net_device
*dev
, int new_mtu
)
4819 struct port_info
*pi
= netdev_priv(dev
);
4821 if (new_mtu
< 81 || new_mtu
> MAX_MTU
) /* accommodate SACK */
4823 ret
= t4_set_rxmode(pi
->adapter
, pi
->adapter
->fn
, pi
->viid
, new_mtu
, -1,
4830 static int cxgb_set_mac_addr(struct net_device
*dev
, void *p
)
4833 struct sockaddr
*addr
= p
;
4834 struct port_info
*pi
= netdev_priv(dev
);
4836 if (!is_valid_ether_addr(addr
->sa_data
))
4837 return -EADDRNOTAVAIL
;
4839 ret
= t4_change_mac(pi
->adapter
, pi
->adapter
->fn
, pi
->viid
,
4840 pi
->xact_addr_filt
, addr
->sa_data
, true, true);
4844 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
4845 pi
->xact_addr_filt
= ret
;
4849 #ifdef CONFIG_NET_POLL_CONTROLLER
4850 static void cxgb_netpoll(struct net_device
*dev
)
4852 struct port_info
*pi
= netdev_priv(dev
);
4853 struct adapter
*adap
= pi
->adapter
;
4855 if (adap
->flags
& USING_MSIX
) {
4857 struct sge_eth_rxq
*rx
= &adap
->sge
.ethrxq
[pi
->first_qset
];
4859 for (i
= pi
->nqsets
; i
; i
--, rx
++)
4860 t4_sge_intr_msix(0, &rx
->rspq
);
4862 t4_intr_handler(adap
)(0, adap
);
4866 static const struct net_device_ops cxgb4_netdev_ops
= {
4867 .ndo_open
= cxgb_open
,
4868 .ndo_stop
= cxgb_close
,
4869 .ndo_start_xmit
= t4_eth_xmit
,
4870 .ndo_select_queue
= cxgb_select_queue
,
4871 .ndo_get_stats64
= cxgb_get_stats
,
4872 .ndo_set_rx_mode
= cxgb_set_rxmode
,
4873 .ndo_set_mac_address
= cxgb_set_mac_addr
,
4874 .ndo_set_features
= cxgb_set_features
,
4875 .ndo_validate_addr
= eth_validate_addr
,
4876 .ndo_do_ioctl
= cxgb_ioctl
,
4877 .ndo_change_mtu
= cxgb_change_mtu
,
4878 #ifdef CONFIG_NET_POLL_CONTROLLER
4879 .ndo_poll_controller
= cxgb_netpoll
,
4883 void t4_fatal_err(struct adapter
*adap
)
4885 t4_set_reg_field(adap
, SGE_CONTROL
, GLOBALENABLE
, 0);
4886 t4_intr_disable(adap
);
4887 dev_alert(adap
->pdev_dev
, "encountered fatal error, adapter stopped\n");
4890 /* Return the specified PCI-E Configuration Space register from our Physical
4891 * Function. We try first via a Firmware LDST Command since we prefer to let
4892 * the firmware own all of these registers, but if that fails we go for it
4893 * directly ourselves.
4895 static u32
t4_read_pcie_cfg4(struct adapter
*adap
, int reg
)
4897 struct fw_ldst_cmd ldst_cmd
;
4901 /* Construct and send the Firmware LDST Command to retrieve the
4902 * specified PCI-E Configuration Space register.
4904 memset(&ldst_cmd
, 0, sizeof(ldst_cmd
));
4905 ldst_cmd
.op_to_addrspace
=
4906 htonl(FW_CMD_OP(FW_LDST_CMD
) |
4909 FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE
));
4910 ldst_cmd
.cycles_to_len16
= htonl(FW_LEN16(ldst_cmd
));
4911 ldst_cmd
.u
.pcie
.select_naccess
= FW_LDST_CMD_NACCESS(1);
4912 ldst_cmd
.u
.pcie
.ctrl_to_fn
=
4913 (FW_LDST_CMD_LC
| FW_LDST_CMD_FN(adap
->fn
));
4914 ldst_cmd
.u
.pcie
.r
= reg
;
4915 ret
= t4_wr_mbox(adap
, adap
->mbox
, &ldst_cmd
, sizeof(ldst_cmd
),
4918 /* If the LDST Command suucceeded, exctract the returned register
4919 * value. Otherwise read it directly ourself.
4922 val
= ntohl(ldst_cmd
.u
.pcie
.data
[0]);
4924 t4_hw_pci_read_cfg4(adap
, reg
, &val
);
4929 static void setup_memwin(struct adapter
*adap
)
4931 u32 mem_win0_base
, mem_win1_base
, mem_win2_base
, mem_win2_aperture
;
4933 if (is_t4(adap
->params
.chip
)) {
4936 /* Truncation intentional: we only read the bottom 32-bits of
4937 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
4938 * mechanism to read BAR0 instead of using
4939 * pci_resource_start() because we could be operating from
4940 * within a Virtual Machine which is trapping our accesses to
4941 * our Configuration Space and we need to set up the PCI-E
4942 * Memory Window decoders with the actual addresses which will
4943 * be coming across the PCI-E link.
4945 bar0
= t4_read_pcie_cfg4(adap
, PCI_BASE_ADDRESS_0
);
4946 bar0
&= PCI_BASE_ADDRESS_MEM_MASK
;
4947 adap
->t4_bar0
= bar0
;
4949 mem_win0_base
= bar0
+ MEMWIN0_BASE
;
4950 mem_win1_base
= bar0
+ MEMWIN1_BASE
;
4951 mem_win2_base
= bar0
+ MEMWIN2_BASE
;
4952 mem_win2_aperture
= MEMWIN2_APERTURE
;
4954 /* For T5, only relative offset inside the PCIe BAR is passed */
4955 mem_win0_base
= MEMWIN0_BASE
;
4956 mem_win1_base
= MEMWIN1_BASE
;
4957 mem_win2_base
= MEMWIN2_BASE_T5
;
4958 mem_win2_aperture
= MEMWIN2_APERTURE_T5
;
4960 t4_write_reg(adap
, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN
, 0),
4961 mem_win0_base
| BIR(0) |
4962 WINDOW(ilog2(MEMWIN0_APERTURE
) - 10));
4963 t4_write_reg(adap
, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN
, 1),
4964 mem_win1_base
| BIR(0) |
4965 WINDOW(ilog2(MEMWIN1_APERTURE
) - 10));
4966 t4_write_reg(adap
, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN
, 2),
4967 mem_win2_base
| BIR(0) |
4968 WINDOW(ilog2(mem_win2_aperture
) - 10));
4969 t4_read_reg(adap
, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN
, 2));
4972 static void setup_memwin_rdma(struct adapter
*adap
)
4974 if (adap
->vres
.ocq
.size
) {
4978 start
= t4_read_pcie_cfg4(adap
, PCI_BASE_ADDRESS_2
);
4979 start
&= PCI_BASE_ADDRESS_MEM_MASK
;
4980 start
+= OCQ_WIN_OFFSET(adap
->pdev
, &adap
->vres
);
4981 sz_kb
= roundup_pow_of_two(adap
->vres
.ocq
.size
) >> 10;
4983 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN
, 3),
4984 start
| BIR(1) | WINDOW(ilog2(sz_kb
)));
4986 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET
, 3),
4987 adap
->vres
.ocq
.start
);
4989 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET
, 3));
4993 static int adap_init1(struct adapter
*adap
, struct fw_caps_config_cmd
*c
)
4998 /* get device capabilities */
4999 memset(c
, 0, sizeof(*c
));
5000 c
->op_to_write
= htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD
) |
5001 FW_CMD_REQUEST
| FW_CMD_READ
);
5002 c
->cfvalid_to_len16
= htonl(FW_LEN16(*c
));
5003 ret
= t4_wr_mbox(adap
, adap
->fn
, c
, sizeof(*c
), c
);
5007 /* select capabilities we'll be using */
5008 if (c
->niccaps
& htons(FW_CAPS_CONFIG_NIC_VM
)) {
5010 c
->niccaps
^= htons(FW_CAPS_CONFIG_NIC_VM
);
5012 c
->niccaps
= htons(FW_CAPS_CONFIG_NIC_VM
);
5013 } else if (vf_acls
) {
5014 dev_err(adap
->pdev_dev
, "virtualization ACLs not supported");
5017 c
->op_to_write
= htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD
) |
5018 FW_CMD_REQUEST
| FW_CMD_WRITE
);
5019 ret
= t4_wr_mbox(adap
, adap
->fn
, c
, sizeof(*c
), NULL
);
5023 ret
= t4_config_glbl_rss(adap
, adap
->fn
,
5024 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL
,
5025 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN
|
5026 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP
);
5030 ret
= t4_cfg_pfvf(adap
, adap
->fn
, adap
->fn
, 0, MAX_EGRQ
, 64, MAX_INGQ
,
5031 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF
, FW_CMD_CAP_PF
);
5037 /* tweak some settings */
5038 t4_write_reg(adap
, TP_SHIFT_CNT
, 0x64f8849);
5039 t4_write_reg(adap
, ULP_RX_TDDP_PSZ
, HPZ0(PAGE_SHIFT
- 12));
5040 t4_write_reg(adap
, TP_PIO_ADDR
, TP_INGRESS_CONFIG
);
5041 v
= t4_read_reg(adap
, TP_PIO_DATA
);
5042 t4_write_reg(adap
, TP_PIO_DATA
, v
& ~CSUM_HAS_PSEUDO_HDR
);
5044 /* first 4 Tx modulation queues point to consecutive Tx channels */
5045 adap
->params
.tp
.tx_modq_map
= 0xE4;
5046 t4_write_reg(adap
, A_TP_TX_MOD_QUEUE_REQ_MAP
,
5047 V_TX_MOD_QUEUE_REQ_MAP(adap
->params
.tp
.tx_modq_map
));
5049 /* associate each Tx modulation queue with consecutive Tx channels */
5051 t4_write_indirect(adap
, TP_PIO_ADDR
, TP_PIO_DATA
,
5052 &v
, 1, A_TP_TX_SCHED_HDR
);
5053 t4_write_indirect(adap
, TP_PIO_ADDR
, TP_PIO_DATA
,
5054 &v
, 1, A_TP_TX_SCHED_FIFO
);
5055 t4_write_indirect(adap
, TP_PIO_ADDR
, TP_PIO_DATA
,
5056 &v
, 1, A_TP_TX_SCHED_PCMD
);
5058 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
5059 if (is_offload(adap
)) {
5060 t4_write_reg(adap
, A_TP_TX_MOD_QUEUE_WEIGHT0
,
5061 V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT
) |
5062 V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT
) |
5063 V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT
) |
5064 V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT
));
5065 t4_write_reg(adap
, A_TP_TX_MOD_CHANNEL_WEIGHT
,
5066 V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT
) |
5067 V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT
) |
5068 V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT
) |
5069 V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT
));
5072 /* get basic stuff going */
5073 return t4_early_init(adap
, adap
->fn
);
5077 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
5079 #define MAX_ATIDS 8192U
5082 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
5084 * If the firmware we're dealing with has Configuration File support, then
5085 * we use that to perform all configuration
5089 * Tweak configuration based on module parameters, etc. Most of these have
5090 * defaults assigned to them by Firmware Configuration Files (if we're using
5091 * them) but need to be explicitly set if we're using hard-coded
5092 * initialization. But even in the case of using Firmware Configuration
5093 * Files, we'd like to expose the ability to change these via module
5094 * parameters so these are essentially common tweaks/settings for
5095 * Configuration Files and hard-coded initialization ...
5097 static int adap_init0_tweaks(struct adapter
*adapter
)
5100 * Fix up various Host-Dependent Parameters like Page Size, Cache
5101 * Line Size, etc. The firmware default is for a 4KB Page Size and
5102 * 64B Cache Line Size ...
5104 t4_fixup_host_params(adapter
, PAGE_SIZE
, L1_CACHE_BYTES
);
5107 * Process module parameters which affect early initialization.
5109 if (rx_dma_offset
!= 2 && rx_dma_offset
!= 0) {
5110 dev_err(&adapter
->pdev
->dev
,
5111 "Ignoring illegal rx_dma_offset=%d, using 2\n",
5115 t4_set_reg_field(adapter
, SGE_CONTROL
,
5117 PKTSHIFT(rx_dma_offset
));
5120 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
5121 * adds the pseudo header itself.
5123 t4_tp_wr_bits_indirect(adapter
, TP_INGRESS_CONFIG
,
5124 CSUM_HAS_PSEUDO_HDR
, 0);
5130 * Attempt to initialize the adapter via a Firmware Configuration File.
5132 static int adap_init0_config(struct adapter
*adapter
, int reset
)
5134 struct fw_caps_config_cmd caps_cmd
;
5135 const struct firmware
*cf
;
5136 unsigned long mtype
= 0, maddr
= 0;
5137 u32 finiver
, finicsum
, cfcsum
;
5139 int config_issued
= 0;
5140 char *fw_config_file
, fw_config_file_path
[256];
5141 char *config_name
= NULL
;
5144 * Reset device if necessary.
5147 ret
= t4_fw_reset(adapter
, adapter
->mbox
,
5148 PIORSTMODE
| PIORST
);
5154 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
5155 * then use that. Otherwise, use the configuration file stored
5156 * in the adapter flash ...
5158 switch (CHELSIO_CHIP_VERSION(adapter
->params
.chip
)) {
5160 fw_config_file
= FW4_CFNAME
;
5163 fw_config_file
= FW5_CFNAME
;
5166 dev_err(adapter
->pdev_dev
, "Device %d is not supported\n",
5167 adapter
->pdev
->device
);
5172 ret
= request_firmware(&cf
, fw_config_file
, adapter
->pdev_dev
);
5174 config_name
= "On FLASH";
5175 mtype
= FW_MEMTYPE_CF_FLASH
;
5176 maddr
= t4_flash_cfg_addr(adapter
);
5178 u32 params
[7], val
[7];
5180 sprintf(fw_config_file_path
,
5181 "/lib/firmware/%s", fw_config_file
);
5182 config_name
= fw_config_file_path
;
5184 if (cf
->size
>= FLASH_CFG_MAX_SIZE
)
5187 params
[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV
) |
5188 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF
));
5189 ret
= t4_query_params(adapter
, adapter
->mbox
,
5190 adapter
->fn
, 0, 1, params
, val
);
5193 * For t4_memory_rw() below addresses and
5194 * sizes have to be in terms of multiples of 4
5195 * bytes. So, if the Configuration File isn't
5196 * a multiple of 4 bytes in length we'll have
5197 * to write that out separately since we can't
5198 * guarantee that the bytes following the
5199 * residual byte in the buffer returned by
5200 * request_firmware() are zeroed out ...
5202 size_t resid
= cf
->size
& 0x3;
5203 size_t size
= cf
->size
& ~0x3;
5204 __be32
*data
= (__be32
*)cf
->data
;
5206 mtype
= FW_PARAMS_PARAM_Y_GET(val
[0]);
5207 maddr
= FW_PARAMS_PARAM_Z_GET(val
[0]) << 16;
5209 spin_lock(&adapter
->win0_lock
);
5210 ret
= t4_memory_rw(adapter
, 0, mtype
, maddr
,
5211 size
, data
, T4_MEMORY_WRITE
);
5212 if (ret
== 0 && resid
!= 0) {
5219 last
.word
= data
[size
>> 2];
5220 for (i
= resid
; i
< 4; i
++)
5222 ret
= t4_memory_rw(adapter
, 0, mtype
,
5227 spin_unlock(&adapter
->win0_lock
);
5231 release_firmware(cf
);
5237 * Issue a Capability Configuration command to the firmware to get it
5238 * to parse the Configuration File. We don't use t4_fw_config_file()
5239 * because we want the ability to modify various features after we've
5240 * processed the configuration file ...
5242 memset(&caps_cmd
, 0, sizeof(caps_cmd
));
5243 caps_cmd
.op_to_write
=
5244 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD
) |
5247 caps_cmd
.cfvalid_to_len16
=
5248 htonl(FW_CAPS_CONFIG_CMD_CFVALID
|
5249 FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype
) |
5250 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr
>> 16) |
5251 FW_LEN16(caps_cmd
));
5252 ret
= t4_wr_mbox(adapter
, adapter
->mbox
, &caps_cmd
, sizeof(caps_cmd
),
5255 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
5256 * Configuration File in FLASH), our last gasp effort is to use the
5257 * Firmware Configuration File which is embedded in the firmware. A
5258 * very few early versions of the firmware didn't have one embedded
5259 * but we can ignore those.
5261 if (ret
== -ENOENT
) {
5262 memset(&caps_cmd
, 0, sizeof(caps_cmd
));
5263 caps_cmd
.op_to_write
=
5264 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD
) |
5267 caps_cmd
.cfvalid_to_len16
= htonl(FW_LEN16(caps_cmd
));
5268 ret
= t4_wr_mbox(adapter
, adapter
->mbox
, &caps_cmd
,
5269 sizeof(caps_cmd
), &caps_cmd
);
5270 config_name
= "Firmware Default";
5277 finiver
= ntohl(caps_cmd
.finiver
);
5278 finicsum
= ntohl(caps_cmd
.finicsum
);
5279 cfcsum
= ntohl(caps_cmd
.cfcsum
);
5280 if (finicsum
!= cfcsum
)
5281 dev_warn(adapter
->pdev_dev
, "Configuration File checksum "\
5282 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
5286 * And now tell the firmware to use the configuration we just loaded.
5288 caps_cmd
.op_to_write
=
5289 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD
) |
5292 caps_cmd
.cfvalid_to_len16
= htonl(FW_LEN16(caps_cmd
));
5293 ret
= t4_wr_mbox(adapter
, adapter
->mbox
, &caps_cmd
, sizeof(caps_cmd
),
5299 * Tweak configuration based on system architecture, module
5302 ret
= adap_init0_tweaks(adapter
);
5307 * And finally tell the firmware to initialize itself using the
5308 * parameters from the Configuration File.
5310 ret
= t4_fw_initialize(adapter
, adapter
->mbox
);
5315 * Return successfully and note that we're operating with parameters
5316 * not supplied by the driver, rather than from hard-wired
5317 * initialization constants burried in the driver.
5319 adapter
->flags
|= USING_SOFT_PARAMS
;
5320 dev_info(adapter
->pdev_dev
, "Successfully configured using Firmware "\
5321 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
5322 config_name
, finiver
, cfcsum
);
5326 * Something bad happened. Return the error ... (If the "error"
5327 * is that there's no Configuration File on the adapter we don't
5328 * want to issue a warning since this is fairly common.)
5331 if (config_issued
&& ret
!= -ENOENT
)
5332 dev_warn(adapter
->pdev_dev
, "\"%s\" configuration file error %d\n",
5338 * Attempt to initialize the adapter via hard-coded, driver supplied
5341 static int adap_init0_no_config(struct adapter
*adapter
, int reset
)
5343 struct sge
*s
= &adapter
->sge
;
5344 struct fw_caps_config_cmd caps_cmd
;
5349 * Reset device if necessary
5352 ret
= t4_fw_reset(adapter
, adapter
->mbox
,
5353 PIORSTMODE
| PIORST
);
5359 * Get device capabilities and select which we'll be using.
5361 memset(&caps_cmd
, 0, sizeof(caps_cmd
));
5362 caps_cmd
.op_to_write
= htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD
) |
5363 FW_CMD_REQUEST
| FW_CMD_READ
);
5364 caps_cmd
.cfvalid_to_len16
= htonl(FW_LEN16(caps_cmd
));
5365 ret
= t4_wr_mbox(adapter
, adapter
->mbox
, &caps_cmd
, sizeof(caps_cmd
),
5370 if (caps_cmd
.niccaps
& htons(FW_CAPS_CONFIG_NIC_VM
)) {
5372 caps_cmd
.niccaps
^= htons(FW_CAPS_CONFIG_NIC_VM
);
5374 caps_cmd
.niccaps
= htons(FW_CAPS_CONFIG_NIC_VM
);
5375 } else if (vf_acls
) {
5376 dev_err(adapter
->pdev_dev
, "virtualization ACLs not supported");
5379 caps_cmd
.op_to_write
= htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD
) |
5380 FW_CMD_REQUEST
| FW_CMD_WRITE
);
5381 ret
= t4_wr_mbox(adapter
, adapter
->mbox
, &caps_cmd
, sizeof(caps_cmd
),
5387 * Tweak configuration based on system architecture, module
5390 ret
= adap_init0_tweaks(adapter
);
5395 * Select RSS Global Mode we want to use. We use "Basic Virtual"
5396 * mode which maps each Virtual Interface to its own section of
5397 * the RSS Table and we turn on all map and hash enables ...
5399 adapter
->flags
|= RSS_TNLALLLOOKUP
;
5400 ret
= t4_config_glbl_rss(adapter
, adapter
->mbox
,
5401 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL
,
5402 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN
|
5403 FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ
|
5404 ((adapter
->flags
& RSS_TNLALLLOOKUP
) ?
5405 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP
: 0));
5410 * Set up our own fundamental resource provisioning ...
5412 ret
= t4_cfg_pfvf(adapter
, adapter
->mbox
, adapter
->fn
, 0,
5413 PFRES_NEQ
, PFRES_NETHCTRL
,
5414 PFRES_NIQFLINT
, PFRES_NIQ
,
5415 PFRES_TC
, PFRES_NVI
,
5416 FW_PFVF_CMD_CMASK_MASK
,
5417 pfvfres_pmask(adapter
, adapter
->fn
, 0),
5419 PFRES_R_CAPS
, PFRES_WX_CAPS
);
5424 * Perform low level SGE initialization. We need to do this before we
5425 * send the firmware the INITIALIZE command because that will cause
5426 * any other PF Drivers which are waiting for the Master
5427 * Initialization to proceed forward.
5429 for (i
= 0; i
< SGE_NTIMERS
- 1; i
++)
5430 s
->timer_val
[i
] = min(intr_holdoff
[i
], MAX_SGE_TIMERVAL
);
5431 s
->timer_val
[SGE_NTIMERS
- 1] = MAX_SGE_TIMERVAL
;
5432 s
->counter_val
[0] = 1;
5433 for (i
= 1; i
< SGE_NCOUNTERS
; i
++)
5434 s
->counter_val
[i
] = min(intr_cnt
[i
- 1],
5435 THRESHOLD_0_GET(THRESHOLD_0_MASK
));
5436 t4_sge_init(adapter
);
5438 #ifdef CONFIG_PCI_IOV
5440 * Provision resource limits for Virtual Functions. We currently
5441 * grant them all the same static resource limits except for the Port
5442 * Access Rights Mask which we're assigning based on the PF. All of
5443 * the static provisioning stuff for both the PF and VF really needs
5444 * to be managed in a persistent manner for each device which the
5445 * firmware controls.
5450 for (pf
= 0; pf
< ARRAY_SIZE(num_vf
); pf
++) {
5451 if (num_vf
[pf
] <= 0)
5454 /* VF numbering starts at 1! */
5455 for (vf
= 1; vf
<= num_vf
[pf
]; vf
++) {
5456 ret
= t4_cfg_pfvf(adapter
, adapter
->mbox
,
5458 VFRES_NEQ
, VFRES_NETHCTRL
,
5459 VFRES_NIQFLINT
, VFRES_NIQ
,
5460 VFRES_TC
, VFRES_NVI
,
5461 FW_PFVF_CMD_CMASK_MASK
,
5465 VFRES_R_CAPS
, VFRES_WX_CAPS
);
5467 dev_warn(adapter
->pdev_dev
,
5469 "provision pf/vf=%d/%d; "
5470 "err=%d\n", pf
, vf
, ret
);
5477 * Set up the default filter mode. Later we'll want to implement this
5478 * via a firmware command, etc. ... This needs to be done before the
5479 * firmare initialization command ... If the selected set of fields
5480 * isn't equal to the default value, we'll need to make sure that the
5481 * field selections will fit in the 36-bit budget.
5483 if (tp_vlan_pri_map
!= TP_VLAN_PRI_MAP_DEFAULT
) {
5486 for (j
= TP_VLAN_PRI_MAP_FIRST
; j
<= TP_VLAN_PRI_MAP_LAST
; j
++)
5487 switch (tp_vlan_pri_map
& (1 << j
)) {
5489 /* compressed filter field not enabled */
5509 case ETHERTYPE_MASK
:
5515 case MPSHITTYPE_MASK
:
5518 case FRAGMENTATION_MASK
:
5524 dev_err(adapter
->pdev_dev
,
5525 "tp_vlan_pri_map=%#x needs %d bits > 36;"\
5526 " using %#x\n", tp_vlan_pri_map
, bits
,
5527 TP_VLAN_PRI_MAP_DEFAULT
);
5528 tp_vlan_pri_map
= TP_VLAN_PRI_MAP_DEFAULT
;
5531 v
= tp_vlan_pri_map
;
5532 t4_write_indirect(adapter
, TP_PIO_ADDR
, TP_PIO_DATA
,
5533 &v
, 1, TP_VLAN_PRI_MAP
);
5536 * We need Five Tuple Lookup mode to be set in TP_GLOBAL_CONFIG order
5537 * to support any of the compressed filter fields above. Newer
5538 * versions of the firmware do this automatically but it doesn't hurt
5539 * to set it here. Meanwhile, we do _not_ need to set Lookup Every
5540 * Packet in TP_INGRESS_CONFIG to support matching non-TCP packets
5541 * since the firmware automatically turns this on and off when we have
5542 * a non-zero number of filters active (since it does have a
5543 * performance impact).
5545 if (tp_vlan_pri_map
)
5546 t4_set_reg_field(adapter
, TP_GLOBAL_CONFIG
,
5547 FIVETUPLELOOKUP_MASK
,
5548 FIVETUPLELOOKUP_MASK
);
5551 * Tweak some settings.
5553 t4_write_reg(adapter
, TP_SHIFT_CNT
, SYNSHIFTMAX(6) |
5554 RXTSHIFTMAXR1(4) | RXTSHIFTMAXR2(15) |
5555 PERSHIFTBACKOFFMAX(8) | PERSHIFTMAX(8) |
5556 KEEPALIVEMAXR1(4) | KEEPALIVEMAXR2(9));
5559 * Get basic stuff going by issuing the Firmware Initialize command.
5560 * Note that this _must_ be after all PFVF commands ...
5562 ret
= t4_fw_initialize(adapter
, adapter
->mbox
);
5567 * Return successfully!
5569 dev_info(adapter
->pdev_dev
, "Successfully configured using built-in "\
5570 "driver parameters\n");
5574 * Something bad happened. Return the error ...
5580 static struct fw_info fw_info_array
[] = {
5583 .fs_name
= FW4_CFNAME
,
5584 .fw_mod_name
= FW4_FNAME
,
5586 .chip
= FW_HDR_CHIP_T4
,
5587 .fw_ver
= __cpu_to_be32(FW_VERSION(T4
)),
5588 .intfver_nic
= FW_INTFVER(T4
, NIC
),
5589 .intfver_vnic
= FW_INTFVER(T4
, VNIC
),
5590 .intfver_ri
= FW_INTFVER(T4
, RI
),
5591 .intfver_iscsi
= FW_INTFVER(T4
, ISCSI
),
5592 .intfver_fcoe
= FW_INTFVER(T4
, FCOE
),
5596 .fs_name
= FW5_CFNAME
,
5597 .fw_mod_name
= FW5_FNAME
,
5599 .chip
= FW_HDR_CHIP_T5
,
5600 .fw_ver
= __cpu_to_be32(FW_VERSION(T5
)),
5601 .intfver_nic
= FW_INTFVER(T5
, NIC
),
5602 .intfver_vnic
= FW_INTFVER(T5
, VNIC
),
5603 .intfver_ri
= FW_INTFVER(T5
, RI
),
5604 .intfver_iscsi
= FW_INTFVER(T5
, ISCSI
),
5605 .intfver_fcoe
= FW_INTFVER(T5
, FCOE
),
5610 static struct fw_info
*find_fw_info(int chip
)
5614 for (i
= 0; i
< ARRAY_SIZE(fw_info_array
); i
++) {
5615 if (fw_info_array
[i
].chip
== chip
)
5616 return &fw_info_array
[i
];
5622 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
5624 static int adap_init0(struct adapter
*adap
)
5628 enum dev_state state
;
5629 u32 params
[7], val
[7];
5630 struct fw_caps_config_cmd caps_cmd
;
5634 * Contact FW, advertising Master capability (and potentially forcing
5635 * ourselves as the Master PF if our module parameter force_init is
5638 ret
= t4_fw_hello(adap
, adap
->mbox
, adap
->fn
,
5639 force_init
? MASTER_MUST
: MASTER_MAY
,
5642 dev_err(adap
->pdev_dev
, "could not connect to FW, error %d\n",
5646 if (ret
== adap
->mbox
)
5647 adap
->flags
|= MASTER_PF
;
5648 if (force_init
&& state
== DEV_STATE_INIT
)
5649 state
= DEV_STATE_UNINIT
;
5652 * If we're the Master PF Driver and the device is uninitialized,
5653 * then let's consider upgrading the firmware ... (We always want
5654 * to check the firmware version number in order to A. get it for
5655 * later reporting and B. to warn if the currently loaded firmware
5656 * is excessively mismatched relative to the driver.)
5658 t4_get_fw_version(adap
, &adap
->params
.fw_vers
);
5659 t4_get_tp_version(adap
, &adap
->params
.tp_vers
);
5660 if ((adap
->flags
& MASTER_PF
) && state
!= DEV_STATE_INIT
) {
5661 struct fw_info
*fw_info
;
5662 struct fw_hdr
*card_fw
;
5663 const struct firmware
*fw
;
5664 const u8
*fw_data
= NULL
;
5665 unsigned int fw_size
= 0;
5667 /* This is the firmware whose headers the driver was compiled
5670 fw_info
= find_fw_info(CHELSIO_CHIP_VERSION(adap
->params
.chip
));
5671 if (fw_info
== NULL
) {
5672 dev_err(adap
->pdev_dev
,
5673 "unable to get firmware info for chip %d.\n",
5674 CHELSIO_CHIP_VERSION(adap
->params
.chip
));
5678 /* allocate memory to read the header of the firmware on the
5681 card_fw
= t4_alloc_mem(sizeof(*card_fw
));
5683 /* Get FW from from /lib/firmware/ */
5684 ret
= request_firmware(&fw
, fw_info
->fw_mod_name
,
5687 dev_err(adap
->pdev_dev
,
5688 "unable to load firmware image %s, error %d\n",
5689 fw_info
->fw_mod_name
, ret
);
5695 /* upgrade FW logic */
5696 ret
= t4_prep_fw(adap
, fw_info
, fw_data
, fw_size
, card_fw
,
5701 release_firmware(fw
);
5702 t4_free_mem(card_fw
);
5709 * Grab VPD parameters. This should be done after we establish a
5710 * connection to the firmware since some of the VPD parameters
5711 * (notably the Core Clock frequency) are retrieved via requests to
5712 * the firmware. On the other hand, we need these fairly early on
5713 * so we do this right after getting ahold of the firmware.
5715 ret
= get_vpd_params(adap
, &adap
->params
.vpd
);
5720 * Find out what ports are available to us. Note that we need to do
5721 * this before calling adap_init0_no_config() since it needs nports
5725 FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV
) |
5726 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC
);
5727 ret
= t4_query_params(adap
, adap
->mbox
, adap
->fn
, 0, 1, &v
, &port_vec
);
5731 adap
->params
.nports
= hweight32(port_vec
);
5732 adap
->params
.portvec
= port_vec
;
5735 * If the firmware is initialized already (and we're not forcing a
5736 * master initialization), note that we're living with existing
5737 * adapter parameters. Otherwise, it's time to try initializing the
5740 if (state
== DEV_STATE_INIT
) {
5741 dev_info(adap
->pdev_dev
, "Coming up as %s: "\
5742 "Adapter already initialized\n",
5743 adap
->flags
& MASTER_PF
? "MASTER" : "SLAVE");
5744 adap
->flags
|= USING_SOFT_PARAMS
;
5746 dev_info(adap
->pdev_dev
, "Coming up as MASTER: "\
5747 "Initializing adapter\n");
5750 * If the firmware doesn't support Configuration
5751 * Files warn user and exit,
5754 dev_warn(adap
->pdev_dev
, "Firmware doesn't support "
5755 "configuration file.\n");
5757 ret
= adap_init0_no_config(adap
, reset
);
5760 * Find out whether we're dealing with a version of
5761 * the firmware which has configuration file support.
5763 params
[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV
) |
5764 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF
));
5765 ret
= t4_query_params(adap
, adap
->mbox
, adap
->fn
, 0, 1,
5769 * If the firmware doesn't support Configuration
5770 * Files, use the old Driver-based, hard-wired
5771 * initialization. Otherwise, try using the
5772 * Configuration File support and fall back to the
5773 * Driver-based initialization if there's no
5774 * Configuration File found.
5777 ret
= adap_init0_no_config(adap
, reset
);
5780 * The firmware provides us with a memory
5781 * buffer where we can load a Configuration
5782 * File from the host if we want to override
5783 * the Configuration File in flash.
5786 ret
= adap_init0_config(adap
, reset
);
5787 if (ret
== -ENOENT
) {
5788 dev_info(adap
->pdev_dev
,
5789 "No Configuration File present "
5790 "on adapter. Using hard-wired "
5791 "configuration parameters.\n");
5792 ret
= adap_init0_no_config(adap
, reset
);
5797 dev_err(adap
->pdev_dev
,
5798 "could not initialize adapter, error %d\n",
5805 * If we're living with non-hard-coded parameters (either from a
5806 * Firmware Configuration File or values programmed by a different PF
5807 * Driver), give the SGE code a chance to pull in anything that it
5808 * needs ... Note that this must be called after we retrieve our VPD
5809 * parameters in order to know how to convert core ticks to seconds.
5811 if (adap
->flags
& USING_SOFT_PARAMS
) {
5812 ret
= t4_sge_init(adap
);
5817 if (is_bypass_device(adap
->pdev
->device
))
5818 adap
->params
.bypass
= 1;
5821 * Grab some of our basic fundamental operating parameters.
5823 #define FW_PARAM_DEV(param) \
5824 (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
5825 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
5827 #define FW_PARAM_PFVF(param) \
5828 FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
5829 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)| \
5830 FW_PARAMS_PARAM_Y(0) | \
5831 FW_PARAMS_PARAM_Z(0)
5833 params
[0] = FW_PARAM_PFVF(EQ_START
);
5834 params
[1] = FW_PARAM_PFVF(L2T_START
);
5835 params
[2] = FW_PARAM_PFVF(L2T_END
);
5836 params
[3] = FW_PARAM_PFVF(FILTER_START
);
5837 params
[4] = FW_PARAM_PFVF(FILTER_END
);
5838 params
[5] = FW_PARAM_PFVF(IQFLINT_START
);
5839 ret
= t4_query_params(adap
, adap
->mbox
, adap
->fn
, 0, 6, params
, val
);
5842 adap
->sge
.egr_start
= val
[0];
5843 adap
->l2t_start
= val
[1];
5844 adap
->l2t_end
= val
[2];
5845 adap
->tids
.ftid_base
= val
[3];
5846 adap
->tids
.nftids
= val
[4] - val
[3] + 1;
5847 adap
->sge
.ingr_start
= val
[5];
5849 /* query params related to active filter region */
5850 params
[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START
);
5851 params
[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END
);
5852 ret
= t4_query_params(adap
, adap
->mbox
, adap
->fn
, 0, 2, params
, val
);
5853 /* If Active filter size is set we enable establishing
5854 * offload connection through firmware work request
5856 if ((val
[0] != val
[1]) && (ret
>= 0)) {
5857 adap
->flags
|= FW_OFLD_CONN
;
5858 adap
->tids
.aftid_base
= val
[0];
5859 adap
->tids
.aftid_end
= val
[1];
5862 /* If we're running on newer firmware, let it know that we're
5863 * prepared to deal with encapsulated CPL messages. Older
5864 * firmware won't understand this and we'll just get
5865 * unencapsulated messages ...
5867 params
[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP
);
5869 (void) t4_set_params(adap
, adap
->mbox
, adap
->fn
, 0, 1, params
, val
);
5872 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
5873 * capability. Earlier versions of the firmware didn't have the
5874 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
5875 * permission to use ULPTX MEMWRITE DSGL.
5877 if (is_t4(adap
->params
.chip
)) {
5878 adap
->params
.ulptx_memwrite_dsgl
= false;
5880 params
[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL
);
5881 ret
= t4_query_params(adap
, adap
->mbox
, adap
->fn
, 0,
5883 adap
->params
.ulptx_memwrite_dsgl
= (ret
== 0 && val
[0] != 0);
5887 * Get device capabilities so we can determine what resources we need
5890 memset(&caps_cmd
, 0, sizeof(caps_cmd
));
5891 caps_cmd
.op_to_write
= htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD
) |
5892 FW_CMD_REQUEST
| FW_CMD_READ
);
5893 caps_cmd
.cfvalid_to_len16
= htonl(FW_LEN16(caps_cmd
));
5894 ret
= t4_wr_mbox(adap
, adap
->mbox
, &caps_cmd
, sizeof(caps_cmd
),
5899 if (caps_cmd
.ofldcaps
) {
5900 /* query offload-related parameters */
5901 params
[0] = FW_PARAM_DEV(NTID
);
5902 params
[1] = FW_PARAM_PFVF(SERVER_START
);
5903 params
[2] = FW_PARAM_PFVF(SERVER_END
);
5904 params
[3] = FW_PARAM_PFVF(TDDP_START
);
5905 params
[4] = FW_PARAM_PFVF(TDDP_END
);
5906 params
[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ
);
5907 ret
= t4_query_params(adap
, adap
->mbox
, adap
->fn
, 0, 6,
5911 adap
->tids
.ntids
= val
[0];
5912 adap
->tids
.natids
= min(adap
->tids
.ntids
/ 2, MAX_ATIDS
);
5913 adap
->tids
.stid_base
= val
[1];
5914 adap
->tids
.nstids
= val
[2] - val
[1] + 1;
5916 * Setup server filter region. Divide the availble filter
5917 * region into two parts. Regular filters get 1/3rd and server
5918 * filters get 2/3rd part. This is only enabled if workarond
5920 * 1. For regular filters.
5921 * 2. Server filter: This are special filters which are used
5922 * to redirect SYN packets to offload queue.
5924 if (adap
->flags
& FW_OFLD_CONN
&& !is_bypass(adap
)) {
5925 adap
->tids
.sftid_base
= adap
->tids
.ftid_base
+
5926 DIV_ROUND_UP(adap
->tids
.nftids
, 3);
5927 adap
->tids
.nsftids
= adap
->tids
.nftids
-
5928 DIV_ROUND_UP(adap
->tids
.nftids
, 3);
5929 adap
->tids
.nftids
= adap
->tids
.sftid_base
-
5930 adap
->tids
.ftid_base
;
5932 adap
->vres
.ddp
.start
= val
[3];
5933 adap
->vres
.ddp
.size
= val
[4] - val
[3] + 1;
5934 adap
->params
.ofldq_wr_cred
= val
[5];
5936 adap
->params
.offload
= 1;
5938 if (caps_cmd
.rdmacaps
) {
5939 params
[0] = FW_PARAM_PFVF(STAG_START
);
5940 params
[1] = FW_PARAM_PFVF(STAG_END
);
5941 params
[2] = FW_PARAM_PFVF(RQ_START
);
5942 params
[3] = FW_PARAM_PFVF(RQ_END
);
5943 params
[4] = FW_PARAM_PFVF(PBL_START
);
5944 params
[5] = FW_PARAM_PFVF(PBL_END
);
5945 ret
= t4_query_params(adap
, adap
->mbox
, adap
->fn
, 0, 6,
5949 adap
->vres
.stag
.start
= val
[0];
5950 adap
->vres
.stag
.size
= val
[1] - val
[0] + 1;
5951 adap
->vres
.rq
.start
= val
[2];
5952 adap
->vres
.rq
.size
= val
[3] - val
[2] + 1;
5953 adap
->vres
.pbl
.start
= val
[4];
5954 adap
->vres
.pbl
.size
= val
[5] - val
[4] + 1;
5956 params
[0] = FW_PARAM_PFVF(SQRQ_START
);
5957 params
[1] = FW_PARAM_PFVF(SQRQ_END
);
5958 params
[2] = FW_PARAM_PFVF(CQ_START
);
5959 params
[3] = FW_PARAM_PFVF(CQ_END
);
5960 params
[4] = FW_PARAM_PFVF(OCQ_START
);
5961 params
[5] = FW_PARAM_PFVF(OCQ_END
);
5962 ret
= t4_query_params(adap
, adap
->mbox
, adap
->fn
, 0, 6, params
,
5966 adap
->vres
.qp
.start
= val
[0];
5967 adap
->vres
.qp
.size
= val
[1] - val
[0] + 1;
5968 adap
->vres
.cq
.start
= val
[2];
5969 adap
->vres
.cq
.size
= val
[3] - val
[2] + 1;
5970 adap
->vres
.ocq
.start
= val
[4];
5971 adap
->vres
.ocq
.size
= val
[5] - val
[4] + 1;
5973 params
[0] = FW_PARAM_DEV(MAXORDIRD_QP
);
5974 params
[1] = FW_PARAM_DEV(MAXIRD_ADAPTER
);
5975 ret
= t4_query_params(adap
, adap
->mbox
, adap
->fn
, 0, 2, params
,
5978 adap
->params
.max_ordird_qp
= 8;
5979 adap
->params
.max_ird_adapter
= 32 * adap
->tids
.ntids
;
5982 adap
->params
.max_ordird_qp
= val
[0];
5983 adap
->params
.max_ird_adapter
= val
[1];
5985 dev_info(adap
->pdev_dev
,
5986 "max_ordird_qp %d max_ird_adapter %d\n",
5987 adap
->params
.max_ordird_qp
,
5988 adap
->params
.max_ird_adapter
);
5990 if (caps_cmd
.iscsicaps
) {
5991 params
[0] = FW_PARAM_PFVF(ISCSI_START
);
5992 params
[1] = FW_PARAM_PFVF(ISCSI_END
);
5993 ret
= t4_query_params(adap
, adap
->mbox
, adap
->fn
, 0, 2,
5997 adap
->vres
.iscsi
.start
= val
[0];
5998 adap
->vres
.iscsi
.size
= val
[1] - val
[0] + 1;
6000 #undef FW_PARAM_PFVF
6003 /* The MTU/MSS Table is initialized by now, so load their values. If
6004 * we're initializing the adapter, then we'll make any modifications
6005 * we want to the MTU/MSS Table and also initialize the congestion
6008 t4_read_mtu_tbl(adap
, adap
->params
.mtus
, NULL
);
6009 if (state
!= DEV_STATE_INIT
) {
6012 /* The default MTU Table contains values 1492 and 1500.
6013 * However, for TCP, it's better to have two values which are
6014 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
6015 * This allows us to have a TCP Data Payload which is a
6016 * multiple of 8 regardless of what combination of TCP Options
6017 * are in use (always a multiple of 4 bytes) which is
6018 * important for performance reasons. For instance, if no
6019 * options are in use, then we have a 20-byte IP header and a
6020 * 20-byte TCP header. In this case, a 1500-byte MSS would
6021 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
6022 * which is not a multiple of 8. So using an MSS of 1488 in
6023 * this case results in a TCP Data Payload of 1448 bytes which
6024 * is a multiple of 8. On the other hand, if 12-byte TCP Time
6025 * Stamps have been negotiated, then an MTU of 1500 bytes
6026 * results in a TCP Data Payload of 1448 bytes which, as
6027 * above, is a multiple of 8 bytes ...
6029 for (i
= 0; i
< NMTUS
; i
++)
6030 if (adap
->params
.mtus
[i
] == 1492) {
6031 adap
->params
.mtus
[i
] = 1488;
6035 t4_load_mtus(adap
, adap
->params
.mtus
, adap
->params
.a_wnd
,
6036 adap
->params
.b_wnd
);
6038 t4_init_tp_params(adap
);
6039 adap
->flags
|= FW_OK
;
6043 * Something bad happened. If a command timed out or failed with EIO
6044 * FW does not operate within its spec or something catastrophic
6045 * happened to HW/FW, stop issuing commands.
6048 if (ret
!= -ETIMEDOUT
&& ret
!= -EIO
)
6049 t4_fw_bye(adap
, adap
->mbox
);
6055 static pci_ers_result_t
eeh_err_detected(struct pci_dev
*pdev
,
6056 pci_channel_state_t state
)
6059 struct adapter
*adap
= pci_get_drvdata(pdev
);
6065 adap
->flags
&= ~FW_OK
;
6066 notify_ulds(adap
, CXGB4_STATE_START_RECOVERY
);
6067 spin_lock(&adap
->stats_lock
);
6068 for_each_port(adap
, i
) {
6069 struct net_device
*dev
= adap
->port
[i
];
6071 netif_device_detach(dev
);
6072 netif_carrier_off(dev
);
6074 spin_unlock(&adap
->stats_lock
);
6075 if (adap
->flags
& FULL_INIT_DONE
)
6078 if ((adap
->flags
& DEV_ENABLED
)) {
6079 pci_disable_device(pdev
);
6080 adap
->flags
&= ~DEV_ENABLED
;
6082 out
: return state
== pci_channel_io_perm_failure
?
6083 PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_NEED_RESET
;
6086 static pci_ers_result_t
eeh_slot_reset(struct pci_dev
*pdev
)
6089 struct fw_caps_config_cmd c
;
6090 struct adapter
*adap
= pci_get_drvdata(pdev
);
6093 pci_restore_state(pdev
);
6094 pci_save_state(pdev
);
6095 return PCI_ERS_RESULT_RECOVERED
;
6098 if (!(adap
->flags
& DEV_ENABLED
)) {
6099 if (pci_enable_device(pdev
)) {
6100 dev_err(&pdev
->dev
, "Cannot reenable PCI "
6101 "device after reset\n");
6102 return PCI_ERS_RESULT_DISCONNECT
;
6104 adap
->flags
|= DEV_ENABLED
;
6107 pci_set_master(pdev
);
6108 pci_restore_state(pdev
);
6109 pci_save_state(pdev
);
6110 pci_cleanup_aer_uncorrect_error_status(pdev
);
6112 if (t4_wait_dev_ready(adap
) < 0)
6113 return PCI_ERS_RESULT_DISCONNECT
;
6114 if (t4_fw_hello(adap
, adap
->fn
, adap
->fn
, MASTER_MUST
, NULL
) < 0)
6115 return PCI_ERS_RESULT_DISCONNECT
;
6116 adap
->flags
|= FW_OK
;
6117 if (adap_init1(adap
, &c
))
6118 return PCI_ERS_RESULT_DISCONNECT
;
6120 for_each_port(adap
, i
) {
6121 struct port_info
*p
= adap2pinfo(adap
, i
);
6123 ret
= t4_alloc_vi(adap
, adap
->fn
, p
->tx_chan
, adap
->fn
, 0, 1,
6126 return PCI_ERS_RESULT_DISCONNECT
;
6128 p
->xact_addr_filt
= -1;
6131 t4_load_mtus(adap
, adap
->params
.mtus
, adap
->params
.a_wnd
,
6132 adap
->params
.b_wnd
);
6135 return PCI_ERS_RESULT_DISCONNECT
;
6136 return PCI_ERS_RESULT_RECOVERED
;
6139 static void eeh_resume(struct pci_dev
*pdev
)
6142 struct adapter
*adap
= pci_get_drvdata(pdev
);
6148 for_each_port(adap
, i
) {
6149 struct net_device
*dev
= adap
->port
[i
];
6151 if (netif_running(dev
)) {
6153 cxgb_set_rxmode(dev
);
6155 netif_device_attach(dev
);
6160 static const struct pci_error_handlers cxgb4_eeh
= {
6161 .error_detected
= eeh_err_detected
,
6162 .slot_reset
= eeh_slot_reset
,
6163 .resume
= eeh_resume
,
6166 static inline bool is_x_10g_port(const struct link_config
*lc
)
6168 return (lc
->supported
& FW_PORT_CAP_SPEED_10G
) != 0 ||
6169 (lc
->supported
& FW_PORT_CAP_SPEED_40G
) != 0;
6172 static inline void init_rspq(struct adapter
*adap
, struct sge_rspq
*q
,
6173 unsigned int us
, unsigned int cnt
,
6174 unsigned int size
, unsigned int iqe_size
)
6177 set_rspq_intr_params(q
, us
, cnt
);
6178 q
->iqe_len
= iqe_size
;
6183 * Perform default configuration of DMA queues depending on the number and type
6184 * of ports we found and the number of available CPUs. Most settings can be
6185 * modified by the admin prior to actual use.
6187 static void cfg_queues(struct adapter
*adap
)
6189 struct sge
*s
= &adap
->sge
;
6190 int i
, n10g
= 0, qidx
= 0;
6191 #ifndef CONFIG_CHELSIO_T4_DCB
6196 for_each_port(adap
, i
)
6197 n10g
+= is_x_10g_port(&adap2pinfo(adap
, i
)->link_cfg
);
6198 #ifdef CONFIG_CHELSIO_T4_DCB
6199 /* For Data Center Bridging support we need to be able to support up
6200 * to 8 Traffic Priorities; each of which will be assigned to its
6201 * own TX Queue in order to prevent Head-Of-Line Blocking.
6203 if (adap
->params
.nports
* 8 > MAX_ETH_QSETS
) {
6204 dev_err(adap
->pdev_dev
, "MAX_ETH_QSETS=%d < %d!\n",
6205 MAX_ETH_QSETS
, adap
->params
.nports
* 8);
6209 for_each_port(adap
, i
) {
6210 struct port_info
*pi
= adap2pinfo(adap
, i
);
6212 pi
->first_qset
= qidx
;
6216 #else /* !CONFIG_CHELSIO_T4_DCB */
6218 * We default to 1 queue per non-10G port and up to # of cores queues
6222 q10g
= (MAX_ETH_QSETS
- (adap
->params
.nports
- n10g
)) / n10g
;
6223 if (q10g
> netif_get_num_default_rss_queues())
6224 q10g
= netif_get_num_default_rss_queues();
6226 for_each_port(adap
, i
) {
6227 struct port_info
*pi
= adap2pinfo(adap
, i
);
6229 pi
->first_qset
= qidx
;
6230 pi
->nqsets
= is_x_10g_port(&pi
->link_cfg
) ? q10g
: 1;
6233 #endif /* !CONFIG_CHELSIO_T4_DCB */
6236 s
->max_ethqsets
= qidx
; /* MSI-X may lower it later */
6238 if (is_offload(adap
)) {
6240 * For offload we use 1 queue/channel if all ports are up to 1G,
6241 * otherwise we divide all available queues amongst the channels
6242 * capped by the number of available cores.
6245 i
= min_t(int, ARRAY_SIZE(s
->ofldrxq
),
6247 s
->ofldqsets
= roundup(i
, adap
->params
.nports
);
6249 s
->ofldqsets
= adap
->params
.nports
;
6250 /* For RDMA one Rx queue per channel suffices */
6251 s
->rdmaqs
= adap
->params
.nports
;
6252 s
->rdmaciqs
= adap
->params
.nports
;
6255 for (i
= 0; i
< ARRAY_SIZE(s
->ethrxq
); i
++) {
6256 struct sge_eth_rxq
*r
= &s
->ethrxq
[i
];
6258 init_rspq(adap
, &r
->rspq
, 5, 10, 1024, 64);
6262 for (i
= 0; i
< ARRAY_SIZE(s
->ethtxq
); i
++)
6263 s
->ethtxq
[i
].q
.size
= 1024;
6265 for (i
= 0; i
< ARRAY_SIZE(s
->ctrlq
); i
++)
6266 s
->ctrlq
[i
].q
.size
= 512;
6268 for (i
= 0; i
< ARRAY_SIZE(s
->ofldtxq
); i
++)
6269 s
->ofldtxq
[i
].q
.size
= 1024;
6271 for (i
= 0; i
< ARRAY_SIZE(s
->ofldrxq
); i
++) {
6272 struct sge_ofld_rxq
*r
= &s
->ofldrxq
[i
];
6274 init_rspq(adap
, &r
->rspq
, 5, 1, 1024, 64);
6275 r
->rspq
.uld
= CXGB4_ULD_ISCSI
;
6279 for (i
= 0; i
< ARRAY_SIZE(s
->rdmarxq
); i
++) {
6280 struct sge_ofld_rxq
*r
= &s
->rdmarxq
[i
];
6282 init_rspq(adap
, &r
->rspq
, 5, 1, 511, 64);
6283 r
->rspq
.uld
= CXGB4_ULD_RDMA
;
6287 ciq_size
= 64 + adap
->vres
.cq
.size
+ adap
->tids
.nftids
;
6288 if (ciq_size
> SGE_MAX_IQ_SIZE
) {
6289 CH_WARN(adap
, "CIQ size too small for available IQs\n");
6290 ciq_size
= SGE_MAX_IQ_SIZE
;
6293 for (i
= 0; i
< ARRAY_SIZE(s
->rdmaciq
); i
++) {
6294 struct sge_ofld_rxq
*r
= &s
->rdmaciq
[i
];
6296 init_rspq(adap
, &r
->rspq
, 5, 1, ciq_size
, 64);
6297 r
->rspq
.uld
= CXGB4_ULD_RDMA
;
6300 init_rspq(adap
, &s
->fw_evtq
, 0, 1, 1024, 64);
6301 init_rspq(adap
, &s
->intrq
, 0, 1, 2 * MAX_INGQ
, 64);
6305 * Reduce the number of Ethernet queues across all ports to at most n.
6306 * n provides at least one queue per port.
6308 static void reduce_ethqs(struct adapter
*adap
, int n
)
6311 struct port_info
*pi
;
6313 while (n
< adap
->sge
.ethqsets
)
6314 for_each_port(adap
, i
) {
6315 pi
= adap2pinfo(adap
, i
);
6316 if (pi
->nqsets
> 1) {
6318 adap
->sge
.ethqsets
--;
6319 if (adap
->sge
.ethqsets
<= n
)
6325 for_each_port(adap
, i
) {
6326 pi
= adap2pinfo(adap
, i
);
6332 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
6333 #define EXTRA_VECS 2
6335 static int enable_msix(struct adapter
*adap
)
6339 struct sge
*s
= &adap
->sge
;
6340 unsigned int nchan
= adap
->params
.nports
;
6341 struct msix_entry entries
[MAX_INGQ
+ 1];
6343 for (i
= 0; i
< ARRAY_SIZE(entries
); ++i
)
6344 entries
[i
].entry
= i
;
6346 want
= s
->max_ethqsets
+ EXTRA_VECS
;
6347 if (is_offload(adap
)) {
6348 want
+= s
->rdmaqs
+ s
->rdmaciqs
+ s
->ofldqsets
;
6349 /* need nchan for each possible ULD */
6350 ofld_need
= 3 * nchan
;
6352 #ifdef CONFIG_CHELSIO_T4_DCB
6353 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
6356 need
= 8 * adap
->params
.nports
+ EXTRA_VECS
+ ofld_need
;
6358 need
= adap
->params
.nports
+ EXTRA_VECS
+ ofld_need
;
6360 want
= pci_enable_msix_range(adap
->pdev
, entries
, need
, want
);
6365 * Distribute available vectors to the various queue groups.
6366 * Every group gets its minimum requirement and NIC gets top
6367 * priority for leftovers.
6369 i
= want
- EXTRA_VECS
- ofld_need
;
6370 if (i
< s
->max_ethqsets
) {
6371 s
->max_ethqsets
= i
;
6372 if (i
< s
->ethqsets
)
6373 reduce_ethqs(adap
, i
);
6375 if (is_offload(adap
)) {
6376 i
= want
- EXTRA_VECS
- s
->max_ethqsets
;
6377 i
-= ofld_need
- nchan
;
6378 s
->ofldqsets
= (i
/ nchan
) * nchan
; /* round down */
6380 for (i
= 0; i
< want
; ++i
)
6381 adap
->msix_info
[i
].vec
= entries
[i
].vector
;
6388 static int init_rss(struct adapter
*adap
)
6392 for_each_port(adap
, i
) {
6393 struct port_info
*pi
= adap2pinfo(adap
, i
);
6395 pi
->rss
= kcalloc(pi
->rss_size
, sizeof(u16
), GFP_KERNEL
);
6398 for (j
= 0; j
< pi
->rss_size
; j
++)
6399 pi
->rss
[j
] = ethtool_rxfh_indir_default(j
, pi
->nqsets
);
6404 static void print_port_info(const struct net_device
*dev
)
6408 const char *spd
= "";
6409 const struct port_info
*pi
= netdev_priv(dev
);
6410 const struct adapter
*adap
= pi
->adapter
;
6412 if (adap
->params
.pci
.speed
== PCI_EXP_LNKSTA_CLS_2_5GB
)
6414 else if (adap
->params
.pci
.speed
== PCI_EXP_LNKSTA_CLS_5_0GB
)
6416 else if (adap
->params
.pci
.speed
== PCI_EXP_LNKSTA_CLS_8_0GB
)
6419 if (pi
->link_cfg
.supported
& FW_PORT_CAP_SPEED_100M
)
6420 bufp
+= sprintf(bufp
, "100/");
6421 if (pi
->link_cfg
.supported
& FW_PORT_CAP_SPEED_1G
)
6422 bufp
+= sprintf(bufp
, "1000/");
6423 if (pi
->link_cfg
.supported
& FW_PORT_CAP_SPEED_10G
)
6424 bufp
+= sprintf(bufp
, "10G/");
6425 if (pi
->link_cfg
.supported
& FW_PORT_CAP_SPEED_40G
)
6426 bufp
+= sprintf(bufp
, "40G/");
6429 sprintf(bufp
, "BASE-%s", t4_get_port_type_description(pi
->port_type
));
6431 netdev_info(dev
, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
6432 adap
->params
.vpd
.id
,
6433 CHELSIO_CHIP_RELEASE(adap
->params
.chip
), buf
,
6434 is_offload(adap
) ? "R" : "", adap
->params
.pci
.width
, spd
,
6435 (adap
->flags
& USING_MSIX
) ? " MSI-X" :
6436 (adap
->flags
& USING_MSI
) ? " MSI" : "");
6437 netdev_info(dev
, "S/N: %s, P/N: %s\n",
6438 adap
->params
.vpd
.sn
, adap
->params
.vpd
.pn
);
6441 static void enable_pcie_relaxed_ordering(struct pci_dev
*dev
)
6443 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL
, PCI_EXP_DEVCTL_RELAX_EN
);
6447 * Free the following resources:
6448 * - memory used for tables
6451 * - resources FW is holding for us
6453 static void free_some_resources(struct adapter
*adapter
)
6457 t4_free_mem(adapter
->l2t
);
6458 t4_free_mem(adapter
->tids
.tid_tab
);
6459 disable_msi(adapter
);
6461 for_each_port(adapter
, i
)
6462 if (adapter
->port
[i
]) {
6463 kfree(adap2pinfo(adapter
, i
)->rss
);
6464 free_netdev(adapter
->port
[i
]);
6466 if (adapter
->flags
& FW_OK
)
6467 t4_fw_bye(adapter
, adapter
->fn
);
6470 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
6471 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
6472 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
6473 #define SEGMENT_SIZE 128
6475 static int init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
6477 int func
, i
, err
, s_qpp
, qpp
, num_seg
;
6478 struct port_info
*pi
;
6479 bool highdma
= false;
6480 struct adapter
*adapter
= NULL
;
6483 printk_once(KERN_INFO
"%s - version %s\n", DRV_DESC
, DRV_VERSION
);
6485 err
= pci_request_regions(pdev
, KBUILD_MODNAME
);
6487 /* Just info, some other driver may have claimed the device. */
6488 dev_info(&pdev
->dev
, "cannot obtain PCI resources\n");
6492 err
= pci_enable_device(pdev
);
6494 dev_err(&pdev
->dev
, "cannot enable PCI device\n");
6495 goto out_release_regions
;
6498 regs
= pci_ioremap_bar(pdev
, 0);
6500 dev_err(&pdev
->dev
, "cannot map device registers\n");
6502 goto out_disable_device
;
6505 /* We control everything through one PF */
6506 func
= SOURCEPF_GET(readl(regs
+ PL_WHOAMI
));
6507 if (func
!= ent
->driver_data
) {
6509 pci_disable_device(pdev
);
6510 pci_save_state(pdev
); /* to restore SR-IOV later */
6514 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(64))) {
6516 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
6518 dev_err(&pdev
->dev
, "unable to obtain 64-bit DMA for "
6519 "coherent allocations\n");
6520 goto out_unmap_bar0
;
6523 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
6525 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
6526 goto out_unmap_bar0
;
6530 pci_enable_pcie_error_reporting(pdev
);
6531 enable_pcie_relaxed_ordering(pdev
);
6532 pci_set_master(pdev
);
6533 pci_save_state(pdev
);
6535 adapter
= kzalloc(sizeof(*adapter
), GFP_KERNEL
);
6538 goto out_unmap_bar0
;
6541 adapter
->workq
= create_singlethread_workqueue("cxgb4");
6542 if (!adapter
->workq
) {
6544 goto out_free_adapter
;
6547 /* PCI device has been enabled */
6548 adapter
->flags
|= DEV_ENABLED
;
6550 adapter
->regs
= regs
;
6551 adapter
->pdev
= pdev
;
6552 adapter
->pdev_dev
= &pdev
->dev
;
6553 adapter
->mbox
= func
;
6555 adapter
->msg_enable
= dflt_msg_enable
;
6556 memset(adapter
->chan_map
, 0xff, sizeof(adapter
->chan_map
));
6558 spin_lock_init(&adapter
->stats_lock
);
6559 spin_lock_init(&adapter
->tid_release_lock
);
6561 INIT_WORK(&adapter
->tid_release_task
, process_tid_release_list
);
6562 INIT_WORK(&adapter
->db_full_task
, process_db_full
);
6563 INIT_WORK(&adapter
->db_drop_task
, process_db_drop
);
6565 err
= t4_prep_adapter(adapter
);
6567 goto out_free_adapter
;
6570 if (!is_t4(adapter
->params
.chip
)) {
6571 s_qpp
= QUEUESPERPAGEPF1
* adapter
->fn
;
6572 qpp
= 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adapter
,
6573 SGE_EGRESS_QUEUES_PER_PAGE_PF
) >> s_qpp
);
6574 num_seg
= PAGE_SIZE
/ SEGMENT_SIZE
;
6576 /* Each segment size is 128B. Write coalescing is enabled only
6577 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
6578 * queue is less no of segments that can be accommodated in
6581 if (qpp
> num_seg
) {
6583 "Incorrect number of egress queues per page\n");
6585 goto out_free_adapter
;
6587 adapter
->bar2
= ioremap_wc(pci_resource_start(pdev
, 2),
6588 pci_resource_len(pdev
, 2));
6589 if (!adapter
->bar2
) {
6590 dev_err(&pdev
->dev
, "cannot map device bar2 region\n");
6592 goto out_free_adapter
;
6596 setup_memwin(adapter
);
6597 err
= adap_init0(adapter
);
6598 setup_memwin_rdma(adapter
);
6602 for_each_port(adapter
, i
) {
6603 struct net_device
*netdev
;
6605 netdev
= alloc_etherdev_mq(sizeof(struct port_info
),
6612 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
6614 adapter
->port
[i
] = netdev
;
6615 pi
= netdev_priv(netdev
);
6616 pi
->adapter
= adapter
;
6617 pi
->xact_addr_filt
= -1;
6619 netdev
->irq
= pdev
->irq
;
6621 netdev
->hw_features
= NETIF_F_SG
| TSO_FLAGS
|
6622 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
6623 NETIF_F_RXCSUM
| NETIF_F_RXHASH
|
6624 NETIF_F_HW_VLAN_CTAG_TX
| NETIF_F_HW_VLAN_CTAG_RX
;
6626 netdev
->hw_features
|= NETIF_F_HIGHDMA
;
6627 netdev
->features
|= netdev
->hw_features
;
6628 netdev
->vlan_features
= netdev
->features
& VLAN_FEAT
;
6630 netdev
->priv_flags
|= IFF_UNICAST_FLT
;
6632 netdev
->netdev_ops
= &cxgb4_netdev_ops
;
6633 #ifdef CONFIG_CHELSIO_T4_DCB
6634 netdev
->dcbnl_ops
= &cxgb4_dcb_ops
;
6635 cxgb4_dcb_state_init(netdev
);
6637 netdev
->ethtool_ops
= &cxgb_ethtool_ops
;
6640 pci_set_drvdata(pdev
, adapter
);
6642 if (adapter
->flags
& FW_OK
) {
6643 err
= t4_port_init(adapter
, func
, func
, 0);
6649 * Configure queues and allocate tables now, they can be needed as
6650 * soon as the first register_netdev completes.
6652 cfg_queues(adapter
);
6654 adapter
->l2t
= t4_init_l2t();
6655 if (!adapter
->l2t
) {
6656 /* We tolerate a lack of L2T, giving up some functionality */
6657 dev_warn(&pdev
->dev
, "could not allocate L2T, continuing\n");
6658 adapter
->params
.offload
= 0;
6661 if (is_offload(adapter
) && tid_init(&adapter
->tids
) < 0) {
6662 dev_warn(&pdev
->dev
, "could not allocate TID table, "
6664 adapter
->params
.offload
= 0;
6667 /* See what interrupts we'll be using */
6668 if (msi
> 1 && enable_msix(adapter
) == 0)
6669 adapter
->flags
|= USING_MSIX
;
6670 else if (msi
> 0 && pci_enable_msi(pdev
) == 0)
6671 adapter
->flags
|= USING_MSI
;
6673 err
= init_rss(adapter
);
6678 * The card is now ready to go. If any errors occur during device
6679 * registration we do not fail the whole card but rather proceed only
6680 * with the ports we manage to register successfully. However we must
6681 * register at least one net device.
6683 for_each_port(adapter
, i
) {
6684 pi
= adap2pinfo(adapter
, i
);
6685 netif_set_real_num_tx_queues(adapter
->port
[i
], pi
->nqsets
);
6686 netif_set_real_num_rx_queues(adapter
->port
[i
], pi
->nqsets
);
6688 err
= register_netdev(adapter
->port
[i
]);
6691 adapter
->chan_map
[pi
->tx_chan
] = i
;
6692 print_port_info(adapter
->port
[i
]);
6695 dev_err(&pdev
->dev
, "could not register any net devices\n");
6699 dev_warn(&pdev
->dev
, "only %d net devices registered\n", i
);
6703 if (cxgb4_debugfs_root
) {
6704 adapter
->debugfs_root
= debugfs_create_dir(pci_name(pdev
),
6705 cxgb4_debugfs_root
);
6706 setup_debugfs(adapter
);
6709 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
6710 pdev
->needs_freset
= 1;
6712 if (is_offload(adapter
))
6713 attach_ulds(adapter
);
6716 #ifdef CONFIG_PCI_IOV
6717 if (func
< ARRAY_SIZE(num_vf
) && num_vf
[func
] > 0)
6718 if (pci_enable_sriov(pdev
, num_vf
[func
]) == 0)
6719 dev_info(&pdev
->dev
,
6720 "instantiated %u virtual functions\n",
6726 free_some_resources(adapter
);
6728 if (!is_t4(adapter
->params
.chip
))
6729 iounmap(adapter
->bar2
);
6732 destroy_workqueue(adapter
->workq
);
6738 pci_disable_pcie_error_reporting(pdev
);
6739 pci_disable_device(pdev
);
6740 out_release_regions
:
6741 pci_release_regions(pdev
);
6745 static void remove_one(struct pci_dev
*pdev
)
6747 struct adapter
*adapter
= pci_get_drvdata(pdev
);
6749 #ifdef CONFIG_PCI_IOV
6750 pci_disable_sriov(pdev
);
6757 /* Tear down per-adapter Work Queue first since it can contain
6758 * references to our adapter data structure.
6760 destroy_workqueue(adapter
->workq
);
6762 if (is_offload(adapter
))
6763 detach_ulds(adapter
);
6765 for_each_port(adapter
, i
)
6766 if (adapter
->port
[i
]->reg_state
== NETREG_REGISTERED
)
6767 unregister_netdev(adapter
->port
[i
]);
6769 debugfs_remove_recursive(adapter
->debugfs_root
);
6771 /* If we allocated filters, free up state associated with any
6774 if (adapter
->tids
.ftid_tab
) {
6775 struct filter_entry
*f
= &adapter
->tids
.ftid_tab
[0];
6776 for (i
= 0; i
< (adapter
->tids
.nftids
+
6777 adapter
->tids
.nsftids
); i
++, f
++)
6779 clear_filter(adapter
, f
);
6782 if (adapter
->flags
& FULL_INIT_DONE
)
6785 free_some_resources(adapter
);
6786 iounmap(adapter
->regs
);
6787 if (!is_t4(adapter
->params
.chip
))
6788 iounmap(adapter
->bar2
);
6789 pci_disable_pcie_error_reporting(pdev
);
6790 if ((adapter
->flags
& DEV_ENABLED
)) {
6791 pci_disable_device(pdev
);
6792 adapter
->flags
&= ~DEV_ENABLED
;
6794 pci_release_regions(pdev
);
6798 pci_release_regions(pdev
);
6801 static struct pci_driver cxgb4_driver
= {
6802 .name
= KBUILD_MODNAME
,
6803 .id_table
= cxgb4_pci_tbl
,
6805 .remove
= remove_one
,
6806 .shutdown
= remove_one
,
6807 .err_handler
= &cxgb4_eeh
,
6810 static int __init
cxgb4_init_module(void)
6814 /* Debugfs support is optional, just warn if this fails */
6815 cxgb4_debugfs_root
= debugfs_create_dir(KBUILD_MODNAME
, NULL
);
6816 if (!cxgb4_debugfs_root
)
6817 pr_warn("could not create debugfs entry, continuing\n");
6819 ret
= pci_register_driver(&cxgb4_driver
);
6821 debugfs_remove(cxgb4_debugfs_root
);
6823 register_inet6addr_notifier(&cxgb4_inet6addr_notifier
);
6828 static void __exit
cxgb4_cleanup_module(void)
6830 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier
);
6831 pci_unregister_driver(&cxgb4_driver
);
6832 debugfs_remove(cxgb4_debugfs_root
); /* NULL ok */
6835 module_init(cxgb4_init_module
);
6836 module_exit(cxgb4_cleanup_module
);