2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
38 #include "t4_values.h"
40 #include "t4fw_version.h"
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
57 static int t4_wait_op_done_val(struct adapter
*adapter
, int reg
, u32 mask
,
58 int polarity
, int attempts
, int delay
, u32
*valp
)
61 u32 val
= t4_read_reg(adapter
, reg
);
63 if (!!(val
& mask
) == polarity
) {
75 static inline int t4_wait_op_done(struct adapter
*adapter
, int reg
, u32 mask
,
76 int polarity
, int attempts
, int delay
)
78 return t4_wait_op_done_val(adapter
, reg
, mask
, polarity
, attempts
,
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
89 * Sets a register field specified by the supplied mask to the
92 void t4_set_reg_field(struct adapter
*adapter
, unsigned int addr
, u32 mask
,
95 u32 v
= t4_read_reg(adapter
, addr
) & ~mask
;
97 t4_write_reg(adapter
, addr
, v
| val
);
98 (void) t4_read_reg(adapter
, addr
); /* flush */
102 * t4_read_indirect - read indirectly addressed registers
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
110 * Reads registers that are accessed indirectly through an address/data
113 void t4_read_indirect(struct adapter
*adap
, unsigned int addr_reg
,
114 unsigned int data_reg
, u32
*vals
,
115 unsigned int nregs
, unsigned int start_idx
)
118 t4_write_reg(adap
, addr_reg
, start_idx
);
119 *vals
++ = t4_read_reg(adap
, data_reg
);
125 * t4_write_indirect - write indirectly addressed registers
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
136 void t4_write_indirect(struct adapter
*adap
, unsigned int addr_reg
,
137 unsigned int data_reg
, const u32
*vals
,
138 unsigned int nregs
, unsigned int start_idx
)
141 t4_write_reg(adap
, addr_reg
, start_idx
++);
142 t4_write_reg(adap
, data_reg
, *vals
++);
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
152 void t4_hw_pci_read_cfg4(struct adapter
*adap
, int reg
, u32
*val
)
154 u32 req
= FUNCTION_V(adap
->pf
) | REGISTER_V(reg
);
156 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) <= CHELSIO_T5
)
161 if (is_t4(adap
->params
.chip
))
164 t4_write_reg(adap
, PCIE_CFG_SPACE_REQ_A
, req
);
165 *val
= t4_read_reg(adap
, PCIE_CFG_SPACE_DATA_A
);
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
172 t4_write_reg(adap
, PCIE_CFG_SPACE_REQ_A
, 0);
176 * t4_report_fw_error - report firmware error
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
183 static void t4_report_fw_error(struct adapter
*adap
)
185 static const char *const reason
[] = {
186 "Crash", /* PCIE_FW_EVAL_CRASH */
187 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
188 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
189 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
190 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
191 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
192 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
193 "Reserved", /* reserved */
197 pcie_fw
= t4_read_reg(adap
, PCIE_FW_A
);
198 if (pcie_fw
& PCIE_FW_ERR_F
) {
199 dev_err(adap
->pdev_dev
, "Firmware reports adapter error: %s\n",
200 reason
[PCIE_FW_EVAL_G(pcie_fw
)]);
201 adap
->flags
&= ~CXGB4_FW_OK
;
206 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
208 static void get_mbox_rpl(struct adapter
*adap
, __be64
*rpl
, int nflit
,
211 for ( ; nflit
; nflit
--, mbox_addr
+= 8)
212 *rpl
++ = cpu_to_be64(t4_read_reg64(adap
, mbox_addr
));
216 * Handle a FW assertion reported in a mailbox.
218 static void fw_asrt(struct adapter
*adap
, u32 mbox_addr
)
220 struct fw_debug_cmd asrt
;
222 get_mbox_rpl(adap
, (__be64
*)&asrt
, sizeof(asrt
) / 8, mbox_addr
);
223 dev_alert(adap
->pdev_dev
,
224 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
225 asrt
.u
.assert.filename_0_7
, be32_to_cpu(asrt
.u
.assert.line
),
226 be32_to_cpu(asrt
.u
.assert.x
), be32_to_cpu(asrt
.u
.assert.y
));
230 * t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
231 * @adapter: the adapter
232 * @cmd: the Firmware Mailbox Command or Reply
233 * @size: command length in bytes
234 * @access: the time (ms) needed to access the Firmware Mailbox
235 * @execute: the time (ms) the command spent being executed
237 static void t4_record_mbox(struct adapter
*adapter
,
238 const __be64
*cmd
, unsigned int size
,
239 int access
, int execute
)
241 struct mbox_cmd_log
*log
= adapter
->mbox_log
;
242 struct mbox_cmd
*entry
;
245 entry
= mbox_cmd_log_entry(log
, log
->cursor
++);
246 if (log
->cursor
== log
->size
)
249 for (i
= 0; i
< size
/ 8; i
++)
250 entry
->cmd
[i
] = be64_to_cpu(cmd
[i
]);
251 while (i
< MBOX_LEN
/ 8)
253 entry
->timestamp
= jiffies
;
254 entry
->seqno
= log
->seqno
++;
255 entry
->access
= access
;
256 entry
->execute
= execute
;
260 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
262 * @mbox: index of the mailbox to use
263 * @cmd: the command to write
264 * @size: command length in bytes
265 * @rpl: where to optionally store the reply
266 * @sleep_ok: if true we may sleep while awaiting command completion
267 * @timeout: time to wait for command to finish before timing out
269 * Sends the given command to FW through the selected mailbox and waits
270 * for the FW to execute the command. If @rpl is not %NULL it is used to
271 * store the FW's reply to the command. The command and its optional
272 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
273 * to respond. @sleep_ok determines whether we may sleep while awaiting
274 * the response. If sleeping is allowed we use progressive backoff
277 * The return value is 0 on success or a negative errno on failure. A
278 * failure can happen either because we are not able to execute the
279 * command or FW executes it but signals an error. In the latter case
280 * the return value is the error code indicated by FW (negated).
282 int t4_wr_mbox_meat_timeout(struct adapter
*adap
, int mbox
, const void *cmd
,
283 int size
, void *rpl
, bool sleep_ok
, int timeout
)
285 static const int delay
[] = {
286 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
289 struct mbox_list entry
;
294 int i
, ms
, delay_idx
, ret
;
295 const __be64
*p
= cmd
;
296 u32 data_reg
= PF_REG(mbox
, CIM_PF_MAILBOX_DATA_A
);
297 u32 ctl_reg
= PF_REG(mbox
, CIM_PF_MAILBOX_CTRL_A
);
298 __be64 cmd_rpl
[MBOX_LEN
/ 8];
301 if ((size
& 15) || size
> MBOX_LEN
)
305 * If the device is off-line, as in EEH, commands will time out.
306 * Fail them early so we don't waste time waiting.
308 if (adap
->pdev
->error_state
!= pci_channel_io_normal
)
311 /* If we have a negative timeout, that implies that we can't sleep. */
317 /* Queue ourselves onto the mailbox access list. When our entry is at
318 * the front of the list, we have rights to access the mailbox. So we
319 * wait [for a while] till we're at the front [or bail out with an
322 spin_lock_bh(&adap
->mbox_lock
);
323 list_add_tail(&entry
.list
, &adap
->mlist
.list
);
324 spin_unlock_bh(&adap
->mbox_lock
);
329 for (i
= 0; ; i
+= ms
) {
330 /* If we've waited too long, return a busy indication. This
331 * really ought to be based on our initial position in the
332 * mailbox access list but this is a start. We very rarely
333 * contend on access to the mailbox ...
335 pcie_fw
= t4_read_reg(adap
, PCIE_FW_A
);
336 if (i
> FW_CMD_MAX_TIMEOUT
|| (pcie_fw
& PCIE_FW_ERR_F
)) {
337 spin_lock_bh(&adap
->mbox_lock
);
338 list_del(&entry
.list
);
339 spin_unlock_bh(&adap
->mbox_lock
);
340 ret
= (pcie_fw
& PCIE_FW_ERR_F
) ? -ENXIO
: -EBUSY
;
341 t4_record_mbox(adap
, cmd
, size
, access
, ret
);
345 /* If we're at the head, break out and start the mailbox
348 if (list_first_entry(&adap
->mlist
.list
, struct mbox_list
,
352 /* Delay for a bit before checking again ... */
354 ms
= delay
[delay_idx
]; /* last element may repeat */
355 if (delay_idx
< ARRAY_SIZE(delay
) - 1)
363 /* Loop trying to get ownership of the mailbox. Return an error
364 * if we can't gain ownership.
366 v
= MBOWNER_G(t4_read_reg(adap
, ctl_reg
));
367 for (i
= 0; v
== MBOX_OWNER_NONE
&& i
< 3; i
++)
368 v
= MBOWNER_G(t4_read_reg(adap
, ctl_reg
));
369 if (v
!= MBOX_OWNER_DRV
) {
370 spin_lock_bh(&adap
->mbox_lock
);
371 list_del(&entry
.list
);
372 spin_unlock_bh(&adap
->mbox_lock
);
373 ret
= (v
== MBOX_OWNER_FW
) ? -EBUSY
: -ETIMEDOUT
;
374 t4_record_mbox(adap
, cmd
, size
, access
, ret
);
378 /* Copy in the new mailbox command and send it on its way ... */
379 t4_record_mbox(adap
, cmd
, size
, access
, 0);
380 for (i
= 0; i
< size
; i
+= 8)
381 t4_write_reg64(adap
, data_reg
+ i
, be64_to_cpu(*p
++));
383 t4_write_reg(adap
, ctl_reg
, MBMSGVALID_F
| MBOWNER_V(MBOX_OWNER_FW
));
384 t4_read_reg(adap
, ctl_reg
); /* flush write */
390 !((pcie_fw
= t4_read_reg(adap
, PCIE_FW_A
)) & PCIE_FW_ERR_F
) &&
394 ms
= delay
[delay_idx
]; /* last element may repeat */
395 if (delay_idx
< ARRAY_SIZE(delay
) - 1)
401 v
= t4_read_reg(adap
, ctl_reg
);
402 if (MBOWNER_G(v
) == MBOX_OWNER_DRV
) {
403 if (!(v
& MBMSGVALID_F
)) {
404 t4_write_reg(adap
, ctl_reg
, 0);
408 get_mbox_rpl(adap
, cmd_rpl
, MBOX_LEN
/ 8, data_reg
);
409 res
= be64_to_cpu(cmd_rpl
[0]);
411 if (FW_CMD_OP_G(res
>> 32) == FW_DEBUG_CMD
) {
412 fw_asrt(adap
, data_reg
);
413 res
= FW_CMD_RETVAL_V(EIO
);
415 memcpy(rpl
, cmd_rpl
, size
);
418 t4_write_reg(adap
, ctl_reg
, 0);
421 t4_record_mbox(adap
, cmd_rpl
,
422 MBOX_LEN
, access
, execute
);
423 spin_lock_bh(&adap
->mbox_lock
);
424 list_del(&entry
.list
);
425 spin_unlock_bh(&adap
->mbox_lock
);
426 return -FW_CMD_RETVAL_G((int)res
);
430 ret
= (pcie_fw
& PCIE_FW_ERR_F
) ? -ENXIO
: -ETIMEDOUT
;
431 t4_record_mbox(adap
, cmd
, size
, access
, ret
);
432 dev_err(adap
->pdev_dev
, "command %#x in mailbox %d timed out\n",
433 *(const u8
*)cmd
, mbox
);
434 t4_report_fw_error(adap
);
435 spin_lock_bh(&adap
->mbox_lock
);
436 list_del(&entry
.list
);
437 spin_unlock_bh(&adap
->mbox_lock
);
442 int t4_wr_mbox_meat(struct adapter
*adap
, int mbox
, const void *cmd
, int size
,
443 void *rpl
, bool sleep_ok
)
445 return t4_wr_mbox_meat_timeout(adap
, mbox
, cmd
, size
, rpl
, sleep_ok
,
449 static int t4_edc_err_read(struct adapter
*adap
, int idx
)
451 u32 edc_ecc_err_addr_reg
;
454 if (is_t4(adap
->params
.chip
)) {
455 CH_WARN(adap
, "%s: T4 NOT supported.\n", __func__
);
458 if (idx
!= 0 && idx
!= 1) {
459 CH_WARN(adap
, "%s: idx %d NOT supported.\n", __func__
, idx
);
463 edc_ecc_err_addr_reg
= EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A
, idx
);
464 rdata_reg
= EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A
, idx
);
467 "edc%d err addr 0x%x: 0x%x.\n",
468 idx
, edc_ecc_err_addr_reg
,
469 t4_read_reg(adap
, edc_ecc_err_addr_reg
));
471 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
473 (unsigned long long)t4_read_reg64(adap
, rdata_reg
),
474 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 8),
475 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 16),
476 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 24),
477 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 32),
478 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 40),
479 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 48),
480 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 56),
481 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 64));
487 * t4_memory_rw_init - Get memory window relative offset, base, and size.
489 * @win: PCI-E Memory Window to use
490 * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_HMA or MEM_MC
491 * @mem_off: memory relative offset with respect to @mtype.
492 * @mem_base: configured memory base address.
493 * @mem_aperture: configured memory window aperture.
495 * Get the configured memory window's relative offset, base, and size.
497 int t4_memory_rw_init(struct adapter
*adap
, int win
, int mtype
, u32
*mem_off
,
498 u32
*mem_base
, u32
*mem_aperture
)
500 u32 edc_size
, mc_size
, mem_reg
;
502 /* Offset into the region of memory which is being accessed
505 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
506 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
509 edc_size
= EDRAM0_SIZE_G(t4_read_reg(adap
, MA_EDRAM0_BAR_A
));
510 if (mtype
== MEM_HMA
) {
511 *mem_off
= 2 * (edc_size
* 1024 * 1024);
512 } else if (mtype
!= MEM_MC1
) {
513 *mem_off
= (mtype
* (edc_size
* 1024 * 1024));
515 mc_size
= EXT_MEM0_SIZE_G(t4_read_reg(adap
,
516 MA_EXT_MEMORY0_BAR_A
));
517 *mem_off
= (MEM_MC0
* edc_size
+ mc_size
) * 1024 * 1024;
520 /* Each PCI-E Memory Window is programmed with a window size -- or
521 * "aperture" -- which controls the granularity of its mapping onto
522 * adapter memory. We need to grab that aperture in order to know
523 * how to use the specified window. The window is also programmed
524 * with the base address of the Memory Window in BAR0's address
525 * space. For T4 this is an absolute PCI-E Bus Address. For T5
526 * the address is relative to BAR0.
528 mem_reg
= t4_read_reg(adap
,
529 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A
,
531 /* a dead adapter will return 0xffffffff for PIO reads */
532 if (mem_reg
== 0xffffffff)
535 *mem_aperture
= 1 << (WINDOW_G(mem_reg
) + WINDOW_SHIFT_X
);
536 *mem_base
= PCIEOFST_G(mem_reg
) << PCIEOFST_SHIFT_X
;
537 if (is_t4(adap
->params
.chip
))
538 *mem_base
-= adap
->t4_bar0
;
544 * t4_memory_update_win - Move memory window to specified address.
546 * @win: PCI-E Memory Window to use
547 * @addr: location to move.
549 * Move memory window to specified address.
551 void t4_memory_update_win(struct adapter
*adap
, int win
, u32 addr
)
554 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A
, win
),
556 /* Read it back to ensure that changes propagate before we
557 * attempt to use the new value.
560 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A
, win
));
564 * t4_memory_rw_residual - Read/Write residual data.
566 * @off: relative offset within residual to start read/write.
567 * @addr: address within indicated memory type.
568 * @buf: host memory buffer
569 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
571 * Read/Write residual data less than 32-bits.
573 void t4_memory_rw_residual(struct adapter
*adap
, u32 off
, u32 addr
, u8
*buf
,
583 if (dir
== T4_MEMORY_READ
) {
584 last
.word
= le32_to_cpu((__force __le32
)
585 t4_read_reg(adap
, addr
));
586 for (bp
= (unsigned char *)buf
, i
= off
; i
< 4; i
++)
587 bp
[i
] = last
.byte
[i
];
590 for (i
= off
; i
< 4; i
++)
592 t4_write_reg(adap
, addr
,
593 (__force u32
)cpu_to_le32(last
.word
));
598 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
600 * @win: PCI-E Memory Window to use
601 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
602 * @addr: address within indicated memory type
603 * @len: amount of memory to transfer
604 * @hbuf: host memory buffer
605 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
607 * Reads/writes an [almost] arbitrary memory region in the firmware: the
608 * firmware memory address and host buffer must be aligned on 32-bit
609 * boundaries; the length may be arbitrary. The memory is transferred as
610 * a raw byte sequence from/to the firmware's memory. If this memory
611 * contains data structures which contain multi-byte integers, it's the
612 * caller's responsibility to perform appropriate byte order conversions.
614 int t4_memory_rw(struct adapter
*adap
, int win
, int mtype
, u32 addr
,
615 u32 len
, void *hbuf
, int dir
)
617 u32 pos
, offset
, resid
, memoffset
;
618 u32 win_pf
, mem_aperture
, mem_base
;
622 /* Argument sanity checks ...
624 if (addr
& 0x3 || (uintptr_t)hbuf
& 0x3)
628 /* It's convenient to be able to handle lengths which aren't a
629 * multiple of 32-bits because we often end up transferring files to
630 * the firmware. So we'll handle that by normalizing the length here
631 * and then handling any residual transfer at the end.
636 ret
= t4_memory_rw_init(adap
, win
, mtype
, &memoffset
, &mem_base
,
641 /* Determine the PCIE_MEM_ACCESS_OFFSET */
642 addr
= addr
+ memoffset
;
644 win_pf
= is_t4(adap
->params
.chip
) ? 0 : PFNUM_V(adap
->pf
);
646 /* Calculate our initial PCI-E Memory Window Position and Offset into
649 pos
= addr
& ~(mem_aperture
- 1);
652 /* Set up initial PCI-E Memory Window to cover the start of our
655 t4_memory_update_win(adap
, win
, pos
| win_pf
);
657 /* Transfer data to/from the adapter as long as there's an integral
658 * number of 32-bit transfers to complete.
660 * A note on Endianness issues:
662 * The "register" reads and writes below from/to the PCI-E Memory
663 * Window invoke the standard adapter Big-Endian to PCI-E Link
664 * Little-Endian "swizzel." As a result, if we have the following
665 * data in adapter memory:
667 * Memory: ... | b0 | b1 | b2 | b3 | ...
668 * Address: i+0 i+1 i+2 i+3
670 * Then a read of the adapter memory via the PCI-E Memory Window
675 * [ b3 | b2 | b1 | b0 ]
677 * If this value is stored into local memory on a Little-Endian system
678 * it will show up correctly in local memory as:
680 * ( ..., b0, b1, b2, b3, ... )
682 * But on a Big-Endian system, the store will show up in memory
683 * incorrectly swizzled as:
685 * ( ..., b3, b2, b1, b0, ... )
687 * So we need to account for this in the reads and writes to the
688 * PCI-E Memory Window below by undoing the register read/write
692 if (dir
== T4_MEMORY_READ
)
693 *buf
++ = le32_to_cpu((__force __le32
)t4_read_reg(adap
,
696 t4_write_reg(adap
, mem_base
+ offset
,
697 (__force u32
)cpu_to_le32(*buf
++));
698 offset
+= sizeof(__be32
);
699 len
-= sizeof(__be32
);
701 /* If we've reached the end of our current window aperture,
702 * move the PCI-E Memory Window on to the next. Note that
703 * doing this here after "len" may be 0 allows us to set up
704 * the PCI-E Memory Window for a possible final residual
707 if (offset
== mem_aperture
) {
710 t4_memory_update_win(adap
, win
, pos
| win_pf
);
714 /* If the original transfer had a length which wasn't a multiple of
715 * 32-bits, now's where we need to finish off the transfer of the
716 * residual amount. The PCI-E Memory Window has already been moved
717 * above (if necessary) to cover this final transfer.
720 t4_memory_rw_residual(adap
, resid
, mem_base
+ offset
,
726 /* Return the specified PCI-E Configuration Space register from our Physical
727 * Function. We try first via a Firmware LDST Command since we prefer to let
728 * the firmware own all of these registers, but if that fails we go for it
729 * directly ourselves.
731 u32
t4_read_pcie_cfg4(struct adapter
*adap
, int reg
)
733 u32 val
, ldst_addrspace
;
735 /* If fw_attach != 0, construct and send the Firmware LDST Command to
736 * retrieve the specified PCI-E Configuration Space register.
738 struct fw_ldst_cmd ldst_cmd
;
741 memset(&ldst_cmd
, 0, sizeof(ldst_cmd
));
742 ldst_addrspace
= FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE
);
743 ldst_cmd
.op_to_addrspace
= cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
747 ldst_cmd
.cycles_to_len16
= cpu_to_be32(FW_LEN16(ldst_cmd
));
748 ldst_cmd
.u
.pcie
.select_naccess
= FW_LDST_CMD_NACCESS_V(1);
749 ldst_cmd
.u
.pcie
.ctrl_to_fn
=
750 (FW_LDST_CMD_LC_F
| FW_LDST_CMD_FN_V(adap
->pf
));
751 ldst_cmd
.u
.pcie
.r
= reg
;
753 /* If the LDST Command succeeds, return the result, otherwise
754 * fall through to reading it directly ourselves ...
756 ret
= t4_wr_mbox(adap
, adap
->mbox
, &ldst_cmd
, sizeof(ldst_cmd
),
759 val
= be32_to_cpu(ldst_cmd
.u
.pcie
.data
[0]);
761 /* Read the desired Configuration Space register via the PCI-E
762 * Backdoor mechanism.
764 t4_hw_pci_read_cfg4(adap
, reg
, &val
);
768 /* Get the window based on base passed to it.
769 * Window aperture is currently unhandled, but there is no use case for it
772 static u32
t4_get_window(struct adapter
*adap
, u32 pci_base
, u64 pci_mask
,
777 if (is_t4(adap
->params
.chip
)) {
780 /* Truncation intentional: we only read the bottom 32-bits of
781 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
782 * mechanism to read BAR0 instead of using
783 * pci_resource_start() because we could be operating from
784 * within a Virtual Machine which is trapping our accesses to
785 * our Configuration Space and we need to set up the PCI-E
786 * Memory Window decoders with the actual addresses which will
787 * be coming across the PCI-E link.
789 bar0
= t4_read_pcie_cfg4(adap
, pci_base
);
791 adap
->t4_bar0
= bar0
;
793 ret
= bar0
+ memwin_base
;
795 /* For T5, only relative offset inside the PCIe BAR is passed */
801 /* Get the default utility window (win0) used by everyone */
802 u32
t4_get_util_window(struct adapter
*adap
)
804 return t4_get_window(adap
, PCI_BASE_ADDRESS_0
,
805 PCI_BASE_ADDRESS_MEM_MASK
, MEMWIN0_BASE
);
808 /* Set up memory window for accessing adapter memory ranges. (Read
809 * back MA register to ensure that changes propagate before we attempt
810 * to use the new values.)
812 void t4_setup_memwin(struct adapter
*adap
, u32 memwin_base
, u32 window
)
815 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A
, window
),
816 memwin_base
| BIR_V(0) |
817 WINDOW_V(ilog2(MEMWIN0_APERTURE
) - WINDOW_SHIFT_X
));
819 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A
, window
));
823 * t4_get_regs_len - return the size of the chips register set
824 * @adapter: the adapter
826 * Returns the size of the chip's BAR0 register space.
828 unsigned int t4_get_regs_len(struct adapter
*adapter
)
830 unsigned int chip_version
= CHELSIO_CHIP_VERSION(adapter
->params
.chip
);
832 switch (chip_version
) {
834 return T4_REGMAP_SIZE
;
838 return T5_REGMAP_SIZE
;
841 dev_err(adapter
->pdev_dev
,
842 "Unsupported chip version %d\n", chip_version
);
847 * t4_get_regs - read chip registers into provided buffer
849 * @buf: register buffer
850 * @buf_size: size (in bytes) of register buffer
852 * If the provided register buffer isn't large enough for the chip's
853 * full register range, the register dump will be truncated to the
854 * register buffer's size.
856 void t4_get_regs(struct adapter
*adap
, void *buf
, size_t buf_size
)
858 static const unsigned int t4_reg_ranges
[] = {
1317 static const unsigned int t5_reg_ranges
[] = {
2084 static const unsigned int t6_reg_ranges
[] = {
2645 u32
*buf_end
= (u32
*)((char *)buf
+ buf_size
);
2646 const unsigned int *reg_ranges
;
2647 int reg_ranges_size
, range
;
2648 unsigned int chip_version
= CHELSIO_CHIP_VERSION(adap
->params
.chip
);
2650 /* Select the right set of register ranges to dump depending on the
2651 * adapter chip type.
2653 switch (chip_version
) {
2655 reg_ranges
= t4_reg_ranges
;
2656 reg_ranges_size
= ARRAY_SIZE(t4_reg_ranges
);
2660 reg_ranges
= t5_reg_ranges
;
2661 reg_ranges_size
= ARRAY_SIZE(t5_reg_ranges
);
2665 reg_ranges
= t6_reg_ranges
;
2666 reg_ranges_size
= ARRAY_SIZE(t6_reg_ranges
);
2670 dev_err(adap
->pdev_dev
,
2671 "Unsupported chip version %d\n", chip_version
);
2675 /* Clear the register buffer and insert the appropriate register
2676 * values selected by the above register ranges.
2678 memset(buf
, 0, buf_size
);
2679 for (range
= 0; range
< reg_ranges_size
; range
+= 2) {
2680 unsigned int reg
= reg_ranges
[range
];
2681 unsigned int last_reg
= reg_ranges
[range
+ 1];
2682 u32
*bufp
= (u32
*)((char *)buf
+ reg
);
2684 /* Iterate across the register range filling in the register
2685 * buffer but don't write past the end of the register buffer.
2687 while (reg
<= last_reg
&& bufp
< buf_end
) {
2688 *bufp
++ = t4_read_reg(adap
, reg
);
2694 #define EEPROM_STAT_ADDR 0x7bfc
2695 #define VPD_BASE 0x400
2696 #define VPD_BASE_OLD 0
2697 #define VPD_LEN 1024
2698 #define CHELSIO_VPD_UNIQUE_ID 0x82
2701 * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2702 * @phys_addr: the physical EEPROM address
2703 * @fn: the PCI function number
2704 * @sz: size of function-specific area
2706 * Translate a physical EEPROM address to virtual. The first 1K is
2707 * accessed through virtual addresses starting at 31K, the rest is
2708 * accessed through virtual addresses starting at 0.
2710 * The mapping is as follows:
2711 * [0..1K) -> [31K..32K)
2712 * [1K..1K+A) -> [31K-A..31K)
2713 * [1K+A..ES) -> [0..ES-A-1K)
2715 * where A = @fn * @sz, and ES = EEPROM size.
2717 int t4_eeprom_ptov(unsigned int phys_addr
, unsigned int fn
, unsigned int sz
)
2720 if (phys_addr
< 1024)
2721 return phys_addr
+ (31 << 10);
2722 if (phys_addr
< 1024 + fn
)
2723 return 31744 - fn
+ phys_addr
- 1024;
2724 if (phys_addr
< EEPROMSIZE
)
2725 return phys_addr
- 1024 - fn
;
2730 * t4_seeprom_wp - enable/disable EEPROM write protection
2731 * @adapter: the adapter
2732 * @enable: whether to enable or disable write protection
2734 * Enables or disables write protection on the serial EEPROM.
2736 int t4_seeprom_wp(struct adapter
*adapter
, bool enable
)
2738 unsigned int v
= enable
? 0xc : 0;
2739 int ret
= pci_write_vpd(adapter
->pdev
, EEPROM_STAT_ADDR
, 4, &v
);
2740 return ret
< 0 ? ret
: 0;
2744 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2745 * @adapter: adapter to read
2746 * @p: where to store the parameters
2748 * Reads card parameters stored in VPD EEPROM.
2750 int t4_get_raw_vpd_params(struct adapter
*adapter
, struct vpd_params
*p
)
2752 int i
, ret
= 0, addr
;
2755 unsigned int vpdr_len
, kw_offset
, id_len
;
2757 vpd
= vmalloc(VPD_LEN
);
2761 /* Card information normally starts at VPD_BASE but early cards had
2764 ret
= pci_read_vpd(adapter
->pdev
, VPD_BASE
, sizeof(u32
), vpd
);
2768 /* The VPD shall have a unique identifier specified by the PCI SIG.
2769 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2770 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2771 * is expected to automatically put this entry at the
2772 * beginning of the VPD.
2774 addr
= *vpd
== CHELSIO_VPD_UNIQUE_ID
? VPD_BASE
: VPD_BASE_OLD
;
2776 ret
= pci_read_vpd(adapter
->pdev
, addr
, VPD_LEN
, vpd
);
2780 if (vpd
[0] != PCI_VPD_LRDT_ID_STRING
) {
2781 dev_err(adapter
->pdev_dev
, "missing VPD ID string\n");
2786 id_len
= pci_vpd_lrdt_size(vpd
);
2787 if (id_len
> ID_LEN
)
2790 i
= pci_vpd_find_tag(vpd
, 0, VPD_LEN
, PCI_VPD_LRDT_RO_DATA
);
2792 dev_err(adapter
->pdev_dev
, "missing VPD-R section\n");
2797 vpdr_len
= pci_vpd_lrdt_size(&vpd
[i
]);
2798 kw_offset
= i
+ PCI_VPD_LRDT_TAG_SIZE
;
2799 if (vpdr_len
+ kw_offset
> VPD_LEN
) {
2800 dev_err(adapter
->pdev_dev
, "bad VPD-R length %u\n", vpdr_len
);
2805 #define FIND_VPD_KW(var, name) do { \
2806 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2808 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2812 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2815 FIND_VPD_KW(i
, "RV");
2816 for (csum
= 0; i
>= 0; i
--)
2820 dev_err(adapter
->pdev_dev
,
2821 "corrupted VPD EEPROM, actual csum %u\n", csum
);
2826 FIND_VPD_KW(ec
, "EC");
2827 FIND_VPD_KW(sn
, "SN");
2828 FIND_VPD_KW(pn
, "PN");
2829 FIND_VPD_KW(na
, "NA");
2832 memcpy(p
->id
, vpd
+ PCI_VPD_LRDT_TAG_SIZE
, id_len
);
2834 memcpy(p
->ec
, vpd
+ ec
, EC_LEN
);
2836 i
= pci_vpd_info_field_size(vpd
+ sn
- PCI_VPD_INFO_FLD_HDR_SIZE
);
2837 memcpy(p
->sn
, vpd
+ sn
, min(i
, SERNUM_LEN
));
2839 i
= pci_vpd_info_field_size(vpd
+ pn
- PCI_VPD_INFO_FLD_HDR_SIZE
);
2840 memcpy(p
->pn
, vpd
+ pn
, min(i
, PN_LEN
));
2842 memcpy(p
->na
, vpd
+ na
, min(i
, MACADDR_LEN
));
2843 strim((char *)p
->na
);
2847 return ret
< 0 ? ret
: 0;
2851 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2852 * @adapter: adapter to read
2853 * @p: where to store the parameters
2855 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2856 * Clock. This can only be called after a connection to the firmware
2859 int t4_get_vpd_params(struct adapter
*adapter
, struct vpd_params
*p
)
2861 u32 cclk_param
, cclk_val
;
2864 /* Grab the raw VPD parameters.
2866 ret
= t4_get_raw_vpd_params(adapter
, p
);
2870 /* Ask firmware for the Core Clock since it knows how to translate the
2871 * Reference Clock ('V2') VPD field into a Core Clock value ...
2873 cclk_param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
2874 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK
));
2875 ret
= t4_query_params(adapter
, adapter
->mbox
, adapter
->pf
, 0,
2876 1, &cclk_param
, &cclk_val
);
2886 * t4_get_pfres - retrieve VF resource limits
2887 * @adapter: the adapter
2889 * Retrieves configured resource limits and capabilities for a physical
2890 * function. The results are stored in @adapter->pfres.
2892 int t4_get_pfres(struct adapter
*adapter
)
2894 struct pf_resources
*pfres
= &adapter
->params
.pfres
;
2895 struct fw_pfvf_cmd cmd
, rpl
;
2899 /* Execute PFVF Read command to get VF resource limits; bail out early
2900 * with error on command failure.
2902 memset(&cmd
, 0, sizeof(cmd
));
2903 cmd
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD
) |
2906 FW_PFVF_CMD_PFN_V(adapter
->pf
) |
2907 FW_PFVF_CMD_VFN_V(0));
2908 cmd
.retval_len16
= cpu_to_be32(FW_LEN16(cmd
));
2909 v
= t4_wr_mbox(adapter
, adapter
->mbox
, &cmd
, sizeof(cmd
), &rpl
);
2910 if (v
!= FW_SUCCESS
)
2913 /* Extract PF resource limits and return success.
2915 word
= be32_to_cpu(rpl
.niqflint_niq
);
2916 pfres
->niqflint
= FW_PFVF_CMD_NIQFLINT_G(word
);
2917 pfres
->niq
= FW_PFVF_CMD_NIQ_G(word
);
2919 word
= be32_to_cpu(rpl
.type_to_neq
);
2920 pfres
->neq
= FW_PFVF_CMD_NEQ_G(word
);
2921 pfres
->pmask
= FW_PFVF_CMD_PMASK_G(word
);
2923 word
= be32_to_cpu(rpl
.tc_to_nexactf
);
2924 pfres
->tc
= FW_PFVF_CMD_TC_G(word
);
2925 pfres
->nvi
= FW_PFVF_CMD_NVI_G(word
);
2926 pfres
->nexactf
= FW_PFVF_CMD_NEXACTF_G(word
);
2928 word
= be32_to_cpu(rpl
.r_caps_to_nethctrl
);
2929 pfres
->r_caps
= FW_PFVF_CMD_R_CAPS_G(word
);
2930 pfres
->wx_caps
= FW_PFVF_CMD_WX_CAPS_G(word
);
2931 pfres
->nethctrl
= FW_PFVF_CMD_NETHCTRL_G(word
);
2936 /* serial flash and firmware constants */
2938 SF_ATTEMPTS
= 10, /* max retries for SF operations */
2940 /* flash command opcodes */
2941 SF_PROG_PAGE
= 2, /* program page */
2942 SF_WR_DISABLE
= 4, /* disable writes */
2943 SF_RD_STATUS
= 5, /* read status register */
2944 SF_WR_ENABLE
= 6, /* enable writes */
2945 SF_RD_DATA_FAST
= 0xb, /* read flash */
2946 SF_RD_ID
= 0x9f, /* read ID */
2947 SF_ERASE_SECTOR
= 0xd8, /* erase sector */
2951 * sf1_read - read data from the serial flash
2952 * @adapter: the adapter
2953 * @byte_cnt: number of bytes to read
2954 * @cont: whether another operation will be chained
2955 * @lock: whether to lock SF for PL access only
2956 * @valp: where to store the read data
2958 * Reads up to 4 bytes of data from the serial flash. The location of
2959 * the read needs to be specified prior to calling this by issuing the
2960 * appropriate commands to the serial flash.
2962 static int sf1_read(struct adapter
*adapter
, unsigned int byte_cnt
, int cont
,
2963 int lock
, u32
*valp
)
2967 if (!byte_cnt
|| byte_cnt
> 4)
2969 if (t4_read_reg(adapter
, SF_OP_A
) & SF_BUSY_F
)
2971 t4_write_reg(adapter
, SF_OP_A
, SF_LOCK_V(lock
) |
2972 SF_CONT_V(cont
) | BYTECNT_V(byte_cnt
- 1));
2973 ret
= t4_wait_op_done(adapter
, SF_OP_A
, SF_BUSY_F
, 0, SF_ATTEMPTS
, 5);
2975 *valp
= t4_read_reg(adapter
, SF_DATA_A
);
2980 * sf1_write - write data to the serial flash
2981 * @adapter: the adapter
2982 * @byte_cnt: number of bytes to write
2983 * @cont: whether another operation will be chained
2984 * @lock: whether to lock SF for PL access only
2985 * @val: value to write
2987 * Writes up to 4 bytes of data to the serial flash. The location of
2988 * the write needs to be specified prior to calling this by issuing the
2989 * appropriate commands to the serial flash.
2991 static int sf1_write(struct adapter
*adapter
, unsigned int byte_cnt
, int cont
,
2994 if (!byte_cnt
|| byte_cnt
> 4)
2996 if (t4_read_reg(adapter
, SF_OP_A
) & SF_BUSY_F
)
2998 t4_write_reg(adapter
, SF_DATA_A
, val
);
2999 t4_write_reg(adapter
, SF_OP_A
, SF_LOCK_V(lock
) |
3000 SF_CONT_V(cont
) | BYTECNT_V(byte_cnt
- 1) | OP_V(1));
3001 return t4_wait_op_done(adapter
, SF_OP_A
, SF_BUSY_F
, 0, SF_ATTEMPTS
, 5);
3005 * flash_wait_op - wait for a flash operation to complete
3006 * @adapter: the adapter
3007 * @attempts: max number of polls of the status register
3008 * @delay: delay between polls in ms
3010 * Wait for a flash operation to complete by polling the status register.
3012 static int flash_wait_op(struct adapter
*adapter
, int attempts
, int delay
)
3018 if ((ret
= sf1_write(adapter
, 1, 1, 1, SF_RD_STATUS
)) != 0 ||
3019 (ret
= sf1_read(adapter
, 1, 0, 1, &status
)) != 0)
3023 if (--attempts
== 0)
3031 * t4_read_flash - read words from serial flash
3032 * @adapter: the adapter
3033 * @addr: the start address for the read
3034 * @nwords: how many 32-bit words to read
3035 * @data: where to store the read data
3036 * @byte_oriented: whether to store data as bytes or as words
3038 * Read the specified number of 32-bit words from the serial flash.
3039 * If @byte_oriented is set the read data is stored as a byte array
3040 * (i.e., big-endian), otherwise as 32-bit words in the platform's
3041 * natural endianness.
3043 int t4_read_flash(struct adapter
*adapter
, unsigned int addr
,
3044 unsigned int nwords
, u32
*data
, int byte_oriented
)
3048 if (addr
+ nwords
* sizeof(u32
) > adapter
->params
.sf_size
|| (addr
& 3))
3051 addr
= swab32(addr
) | SF_RD_DATA_FAST
;
3053 if ((ret
= sf1_write(adapter
, 4, 1, 0, addr
)) != 0 ||
3054 (ret
= sf1_read(adapter
, 1, 1, 0, data
)) != 0)
3057 for ( ; nwords
; nwords
--, data
++) {
3058 ret
= sf1_read(adapter
, 4, nwords
> 1, nwords
== 1, data
);
3060 t4_write_reg(adapter
, SF_OP_A
, 0); /* unlock SF */
3064 *data
= (__force __u32
)(cpu_to_be32(*data
));
3070 * t4_write_flash - write up to a page of data to the serial flash
3071 * @adapter: the adapter
3072 * @addr: the start address to write
3073 * @n: length of data to write in bytes
3074 * @data: the data to write
3076 * Writes up to a page of data (256 bytes) to the serial flash starting
3077 * at the given address. All the data must be written to the same page.
3079 static int t4_write_flash(struct adapter
*adapter
, unsigned int addr
,
3080 unsigned int n
, const u8
*data
)
3084 unsigned int i
, c
, left
, val
, offset
= addr
& 0xff;
3086 if (addr
>= adapter
->params
.sf_size
|| offset
+ n
> SF_PAGE_SIZE
)
3089 val
= swab32(addr
) | SF_PROG_PAGE
;
3091 if ((ret
= sf1_write(adapter
, 1, 0, 1, SF_WR_ENABLE
)) != 0 ||
3092 (ret
= sf1_write(adapter
, 4, 1, 1, val
)) != 0)
3095 for (left
= n
; left
; left
-= c
) {
3097 for (val
= 0, i
= 0; i
< c
; ++i
)
3098 val
= (val
<< 8) + *data
++;
3100 ret
= sf1_write(adapter
, c
, c
!= left
, 1, val
);
3104 ret
= flash_wait_op(adapter
, 8, 1);
3108 t4_write_reg(adapter
, SF_OP_A
, 0); /* unlock SF */
3110 /* Read the page to verify the write succeeded */
3111 ret
= t4_read_flash(adapter
, addr
& ~0xff, ARRAY_SIZE(buf
), buf
, 1);
3115 if (memcmp(data
- n
, (u8
*)buf
+ offset
, n
)) {
3116 dev_err(adapter
->pdev_dev
,
3117 "failed to correctly write the flash page at %#x\n",
3124 t4_write_reg(adapter
, SF_OP_A
, 0); /* unlock SF */
3129 * t4_get_fw_version - read the firmware version
3130 * @adapter: the adapter
3131 * @vers: where to place the version
3133 * Reads the FW version from flash.
3135 int t4_get_fw_version(struct adapter
*adapter
, u32
*vers
)
3137 return t4_read_flash(adapter
, FLASH_FW_START
+
3138 offsetof(struct fw_hdr
, fw_ver
), 1,
3143 * t4_get_bs_version - read the firmware bootstrap version
3144 * @adapter: the adapter
3145 * @vers: where to place the version
3147 * Reads the FW Bootstrap version from flash.
3149 int t4_get_bs_version(struct adapter
*adapter
, u32
*vers
)
3151 return t4_read_flash(adapter
, FLASH_FWBOOTSTRAP_START
+
3152 offsetof(struct fw_hdr
, fw_ver
), 1,
3157 * t4_get_tp_version - read the TP microcode version
3158 * @adapter: the adapter
3159 * @vers: where to place the version
3161 * Reads the TP microcode version from flash.
3163 int t4_get_tp_version(struct adapter
*adapter
, u32
*vers
)
3165 return t4_read_flash(adapter
, FLASH_FW_START
+
3166 offsetof(struct fw_hdr
, tp_microcode_ver
),
3171 * t4_get_exprom_version - return the Expansion ROM version (if any)
3172 * @adapter: the adapter
3173 * @vers: where to place the version
3175 * Reads the Expansion ROM header from FLASH and returns the version
3176 * number (if present) through the @vers return value pointer. We return
3177 * this in the Firmware Version Format since it's convenient. Return
3178 * 0 on success, -ENOENT if no Expansion ROM is present.
3180 int t4_get_exprom_version(struct adapter
*adap
, u32
*vers
)
3182 struct exprom_header
{
3183 unsigned char hdr_arr
[16]; /* must start with 0x55aa */
3184 unsigned char hdr_ver
[4]; /* Expansion ROM version */
3186 u32 exprom_header_buf
[DIV_ROUND_UP(sizeof(struct exprom_header
),
3190 ret
= t4_read_flash(adap
, FLASH_EXP_ROM_START
,
3191 ARRAY_SIZE(exprom_header_buf
), exprom_header_buf
,
3196 hdr
= (struct exprom_header
*)exprom_header_buf
;
3197 if (hdr
->hdr_arr
[0] != 0x55 || hdr
->hdr_arr
[1] != 0xaa)
3200 *vers
= (FW_HDR_FW_VER_MAJOR_V(hdr
->hdr_ver
[0]) |
3201 FW_HDR_FW_VER_MINOR_V(hdr
->hdr_ver
[1]) |
3202 FW_HDR_FW_VER_MICRO_V(hdr
->hdr_ver
[2]) |
3203 FW_HDR_FW_VER_BUILD_V(hdr
->hdr_ver
[3]));
3208 * t4_get_vpd_version - return the VPD version
3209 * @adapter: the adapter
3210 * @vers: where to place the version
3212 * Reads the VPD via the Firmware interface (thus this can only be called
3213 * once we're ready to issue Firmware commands). The format of the
3214 * VPD version is adapter specific. Returns 0 on success, an error on
3217 * Note that early versions of the Firmware didn't include the ability
3218 * to retrieve the VPD version, so we zero-out the return-value parameter
3219 * in that case to avoid leaving it with garbage in it.
3221 * Also note that the Firmware will return its cached copy of the VPD
3222 * Revision ID, not the actual Revision ID as written in the Serial
3223 * EEPROM. This is only an issue if a new VPD has been written and the
3224 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best
3225 * to defer calling this routine till after a FW_RESET_CMD has been issued
3226 * if the Host Driver will be performing a full adapter initialization.
3228 int t4_get_vpd_version(struct adapter
*adapter
, u32
*vers
)
3233 vpdrev_param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
3234 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_VPDREV
));
3235 ret
= t4_query_params(adapter
, adapter
->mbox
, adapter
->pf
, 0,
3236 1, &vpdrev_param
, vers
);
3243 * t4_get_scfg_version - return the Serial Configuration version
3244 * @adapter: the adapter
3245 * @vers: where to place the version
3247 * Reads the Serial Configuration Version via the Firmware interface
3248 * (thus this can only be called once we're ready to issue Firmware
3249 * commands). The format of the Serial Configuration version is
3250 * adapter specific. Returns 0 on success, an error on failure.
3252 * Note that early versions of the Firmware didn't include the ability
3253 * to retrieve the Serial Configuration version, so we zero-out the
3254 * return-value parameter in that case to avoid leaving it with
3257 * Also note that the Firmware will return its cached copy of the Serial
3258 * Initialization Revision ID, not the actual Revision ID as written in
3259 * the Serial EEPROM. This is only an issue if a new VPD has been written
3260 * and the Firmware/Chip haven't yet gone through a RESET sequence. So
3261 * it's best to defer calling this routine till after a FW_RESET_CMD has
3262 * been issued if the Host Driver will be performing a full adapter
3265 int t4_get_scfg_version(struct adapter
*adapter
, u32
*vers
)
3270 scfgrev_param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
3271 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_SCFGREV
));
3272 ret
= t4_query_params(adapter
, adapter
->mbox
, adapter
->pf
, 0,
3273 1, &scfgrev_param
, vers
);
3280 * t4_get_version_info - extract various chip/firmware version information
3281 * @adapter: the adapter
3283 * Reads various chip/firmware version numbers and stores them into the
3284 * adapter Adapter Parameters structure. If any of the efforts fails
3285 * the first failure will be returned, but all of the version numbers
3288 int t4_get_version_info(struct adapter
*adapter
)
3292 #define FIRST_RET(__getvinfo) \
3294 int __ret = __getvinfo; \
3295 if (__ret && !ret) \
3299 FIRST_RET(t4_get_fw_version(adapter
, &adapter
->params
.fw_vers
));
3300 FIRST_RET(t4_get_bs_version(adapter
, &adapter
->params
.bs_vers
));
3301 FIRST_RET(t4_get_tp_version(adapter
, &adapter
->params
.tp_vers
));
3302 FIRST_RET(t4_get_exprom_version(adapter
, &adapter
->params
.er_vers
));
3303 FIRST_RET(t4_get_scfg_version(adapter
, &adapter
->params
.scfg_vers
));
3304 FIRST_RET(t4_get_vpd_version(adapter
, &adapter
->params
.vpd_vers
));
3311 * t4_dump_version_info - dump all of the adapter configuration IDs
3312 * @adapter: the adapter
3314 * Dumps all of the various bits of adapter configuration version/revision
3315 * IDs information. This is typically called at some point after
3316 * t4_get_version_info() has been called.
3318 void t4_dump_version_info(struct adapter
*adapter
)
3320 /* Device information */
3321 dev_info(adapter
->pdev_dev
, "Chelsio %s rev %d\n",
3322 adapter
->params
.vpd
.id
,
3323 CHELSIO_CHIP_RELEASE(adapter
->params
.chip
));
3324 dev_info(adapter
->pdev_dev
, "S/N: %s, P/N: %s\n",
3325 adapter
->params
.vpd
.sn
, adapter
->params
.vpd
.pn
);
3327 /* Firmware Version */
3328 if (!adapter
->params
.fw_vers
)
3329 dev_warn(adapter
->pdev_dev
, "No firmware loaded\n");
3331 dev_info(adapter
->pdev_dev
, "Firmware version: %u.%u.%u.%u\n",
3332 FW_HDR_FW_VER_MAJOR_G(adapter
->params
.fw_vers
),
3333 FW_HDR_FW_VER_MINOR_G(adapter
->params
.fw_vers
),
3334 FW_HDR_FW_VER_MICRO_G(adapter
->params
.fw_vers
),
3335 FW_HDR_FW_VER_BUILD_G(adapter
->params
.fw_vers
));
3337 /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
3338 * Firmware, so dev_info() is more appropriate here.)
3340 if (!adapter
->params
.bs_vers
)
3341 dev_info(adapter
->pdev_dev
, "No bootstrap loaded\n");
3343 dev_info(adapter
->pdev_dev
, "Bootstrap version: %u.%u.%u.%u\n",
3344 FW_HDR_FW_VER_MAJOR_G(adapter
->params
.bs_vers
),
3345 FW_HDR_FW_VER_MINOR_G(adapter
->params
.bs_vers
),
3346 FW_HDR_FW_VER_MICRO_G(adapter
->params
.bs_vers
),
3347 FW_HDR_FW_VER_BUILD_G(adapter
->params
.bs_vers
));
3349 /* TP Microcode Version */
3350 if (!adapter
->params
.tp_vers
)
3351 dev_warn(adapter
->pdev_dev
, "No TP Microcode loaded\n");
3353 dev_info(adapter
->pdev_dev
,
3354 "TP Microcode version: %u.%u.%u.%u\n",
3355 FW_HDR_FW_VER_MAJOR_G(adapter
->params
.tp_vers
),
3356 FW_HDR_FW_VER_MINOR_G(adapter
->params
.tp_vers
),
3357 FW_HDR_FW_VER_MICRO_G(adapter
->params
.tp_vers
),
3358 FW_HDR_FW_VER_BUILD_G(adapter
->params
.tp_vers
));
3360 /* Expansion ROM version */
3361 if (!adapter
->params
.er_vers
)
3362 dev_info(adapter
->pdev_dev
, "No Expansion ROM loaded\n");
3364 dev_info(adapter
->pdev_dev
,
3365 "Expansion ROM version: %u.%u.%u.%u\n",
3366 FW_HDR_FW_VER_MAJOR_G(adapter
->params
.er_vers
),
3367 FW_HDR_FW_VER_MINOR_G(adapter
->params
.er_vers
),
3368 FW_HDR_FW_VER_MICRO_G(adapter
->params
.er_vers
),
3369 FW_HDR_FW_VER_BUILD_G(adapter
->params
.er_vers
));
3371 /* Serial Configuration version */
3372 dev_info(adapter
->pdev_dev
, "Serial Configuration version: %#x\n",
3373 adapter
->params
.scfg_vers
);
3376 dev_info(adapter
->pdev_dev
, "VPD version: %#x\n",
3377 adapter
->params
.vpd_vers
);
3381 * t4_check_fw_version - check if the FW is supported with this driver
3382 * @adap: the adapter
3384 * Checks if an adapter's FW is compatible with the driver. Returns 0
3385 * if there's exact match, a negative error if the version could not be
3386 * read or there's a major version mismatch
3388 int t4_check_fw_version(struct adapter
*adap
)
3390 int i
, ret
, major
, minor
, micro
;
3391 int exp_major
, exp_minor
, exp_micro
;
3392 unsigned int chip_version
= CHELSIO_CHIP_VERSION(adap
->params
.chip
);
3394 ret
= t4_get_fw_version(adap
, &adap
->params
.fw_vers
);
3395 /* Try multiple times before returning error */
3396 for (i
= 0; (ret
== -EBUSY
|| ret
== -EAGAIN
) && i
< 3; i
++)
3397 ret
= t4_get_fw_version(adap
, &adap
->params
.fw_vers
);
3402 major
= FW_HDR_FW_VER_MAJOR_G(adap
->params
.fw_vers
);
3403 minor
= FW_HDR_FW_VER_MINOR_G(adap
->params
.fw_vers
);
3404 micro
= FW_HDR_FW_VER_MICRO_G(adap
->params
.fw_vers
);
3406 switch (chip_version
) {
3408 exp_major
= T4FW_MIN_VERSION_MAJOR
;
3409 exp_minor
= T4FW_MIN_VERSION_MINOR
;
3410 exp_micro
= T4FW_MIN_VERSION_MICRO
;
3413 exp_major
= T5FW_MIN_VERSION_MAJOR
;
3414 exp_minor
= T5FW_MIN_VERSION_MINOR
;
3415 exp_micro
= T5FW_MIN_VERSION_MICRO
;
3418 exp_major
= T6FW_MIN_VERSION_MAJOR
;
3419 exp_minor
= T6FW_MIN_VERSION_MINOR
;
3420 exp_micro
= T6FW_MIN_VERSION_MICRO
;
3423 dev_err(adap
->pdev_dev
, "Unsupported chip type, %x\n",
3428 if (major
< exp_major
|| (major
== exp_major
&& minor
< exp_minor
) ||
3429 (major
== exp_major
&& minor
== exp_minor
&& micro
< exp_micro
)) {
3430 dev_err(adap
->pdev_dev
,
3431 "Card has firmware version %u.%u.%u, minimum "
3432 "supported firmware is %u.%u.%u.\n", major
, minor
,
3433 micro
, exp_major
, exp_minor
, exp_micro
);
3439 /* Is the given firmware API compatible with the one the driver was compiled
3442 static int fw_compatible(const struct fw_hdr
*hdr1
, const struct fw_hdr
*hdr2
)
3445 /* short circuit if it's the exact same firmware version */
3446 if (hdr1
->chip
== hdr2
->chip
&& hdr1
->fw_ver
== hdr2
->fw_ver
)
3449 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3450 if (hdr1
->chip
== hdr2
->chip
&& SAME_INTF(nic
) && SAME_INTF(vnic
) &&
3451 SAME_INTF(ri
) && SAME_INTF(iscsi
) && SAME_INTF(fcoe
))
3458 /* The firmware in the filesystem is usable, but should it be installed?
3459 * This routine explains itself in detail if it indicates the filesystem
3460 * firmware should be installed.
3462 static int should_install_fs_fw(struct adapter
*adap
, int card_fw_usable
,
3467 if (!card_fw_usable
) {
3468 reason
= "incompatible or unusable";
3473 reason
= "older than the version supported with this driver";
3480 dev_err(adap
->pdev_dev
, "firmware on card (%u.%u.%u.%u) is %s, "
3481 "installing firmware %u.%u.%u.%u on card.\n",
3482 FW_HDR_FW_VER_MAJOR_G(c
), FW_HDR_FW_VER_MINOR_G(c
),
3483 FW_HDR_FW_VER_MICRO_G(c
), FW_HDR_FW_VER_BUILD_G(c
), reason
,
3484 FW_HDR_FW_VER_MAJOR_G(k
), FW_HDR_FW_VER_MINOR_G(k
),
3485 FW_HDR_FW_VER_MICRO_G(k
), FW_HDR_FW_VER_BUILD_G(k
));
3490 int t4_prep_fw(struct adapter
*adap
, struct fw_info
*fw_info
,
3491 const u8
*fw_data
, unsigned int fw_size
,
3492 struct fw_hdr
*card_fw
, enum dev_state state
,
3495 int ret
, card_fw_usable
, fs_fw_usable
;
3496 const struct fw_hdr
*fs_fw
;
3497 const struct fw_hdr
*drv_fw
;
3499 drv_fw
= &fw_info
->fw_hdr
;
3501 /* Read the header of the firmware on the card */
3502 ret
= -t4_read_flash(adap
, FLASH_FW_START
,
3503 sizeof(*card_fw
) / sizeof(uint32_t),
3504 (uint32_t *)card_fw
, 1);
3506 card_fw_usable
= fw_compatible(drv_fw
, (const void *)card_fw
);
3508 dev_err(adap
->pdev_dev
,
3509 "Unable to read card's firmware header: %d\n", ret
);
3513 if (fw_data
!= NULL
) {
3514 fs_fw
= (const void *)fw_data
;
3515 fs_fw_usable
= fw_compatible(drv_fw
, fs_fw
);
3521 if (card_fw_usable
&& card_fw
->fw_ver
== drv_fw
->fw_ver
&&
3522 (!fs_fw_usable
|| fs_fw
->fw_ver
== drv_fw
->fw_ver
)) {
3523 /* Common case: the firmware on the card is an exact match and
3524 * the filesystem one is an exact match too, or the filesystem
3525 * one is absent/incompatible.
3527 } else if (fs_fw_usable
&& state
== DEV_STATE_UNINIT
&&
3528 should_install_fs_fw(adap
, card_fw_usable
,
3529 be32_to_cpu(fs_fw
->fw_ver
),
3530 be32_to_cpu(card_fw
->fw_ver
))) {
3531 ret
= -t4_fw_upgrade(adap
, adap
->mbox
, fw_data
,
3534 dev_err(adap
->pdev_dev
,
3535 "failed to install firmware: %d\n", ret
);
3539 /* Installed successfully, update the cached header too. */
3542 *reset
= 0; /* already reset as part of load_fw */
3545 if (!card_fw_usable
) {
3548 d
= be32_to_cpu(drv_fw
->fw_ver
);
3549 c
= be32_to_cpu(card_fw
->fw_ver
);
3550 k
= fs_fw
? be32_to_cpu(fs_fw
->fw_ver
) : 0;
3552 dev_err(adap
->pdev_dev
, "Cannot find a usable firmware: "
3554 "driver compiled with %d.%d.%d.%d, "
3555 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3557 FW_HDR_FW_VER_MAJOR_G(d
), FW_HDR_FW_VER_MINOR_G(d
),
3558 FW_HDR_FW_VER_MICRO_G(d
), FW_HDR_FW_VER_BUILD_G(d
),
3559 FW_HDR_FW_VER_MAJOR_G(c
), FW_HDR_FW_VER_MINOR_G(c
),
3560 FW_HDR_FW_VER_MICRO_G(c
), FW_HDR_FW_VER_BUILD_G(c
),
3561 FW_HDR_FW_VER_MAJOR_G(k
), FW_HDR_FW_VER_MINOR_G(k
),
3562 FW_HDR_FW_VER_MICRO_G(k
), FW_HDR_FW_VER_BUILD_G(k
));
3567 /* We're using whatever's on the card and it's known to be good. */
3568 adap
->params
.fw_vers
= be32_to_cpu(card_fw
->fw_ver
);
3569 adap
->params
.tp_vers
= be32_to_cpu(card_fw
->tp_microcode_ver
);
3576 * t4_flash_erase_sectors - erase a range of flash sectors
3577 * @adapter: the adapter
3578 * @start: the first sector to erase
3579 * @end: the last sector to erase
3581 * Erases the sectors in the given inclusive range.
3583 static int t4_flash_erase_sectors(struct adapter
*adapter
, int start
, int end
)
3587 if (end
>= adapter
->params
.sf_nsec
)
3590 while (start
<= end
) {
3591 if ((ret
= sf1_write(adapter
, 1, 0, 1, SF_WR_ENABLE
)) != 0 ||
3592 (ret
= sf1_write(adapter
, 4, 0, 1,
3593 SF_ERASE_SECTOR
| (start
<< 8))) != 0 ||
3594 (ret
= flash_wait_op(adapter
, 14, 500)) != 0) {
3595 dev_err(adapter
->pdev_dev
,
3596 "erase of flash sector %d failed, error %d\n",
3602 t4_write_reg(adapter
, SF_OP_A
, 0); /* unlock SF */
3607 * t4_flash_cfg_addr - return the address of the flash configuration file
3608 * @adapter: the adapter
3610 * Return the address within the flash where the Firmware Configuration
3613 unsigned int t4_flash_cfg_addr(struct adapter
*adapter
)
3615 if (adapter
->params
.sf_size
== 0x100000)
3616 return FLASH_FPGA_CFG_START
;
3618 return FLASH_CFG_START
;
3621 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3622 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3623 * and emit an error message for mismatched firmware to save our caller the
3626 static bool t4_fw_matches_chip(const struct adapter
*adap
,
3627 const struct fw_hdr
*hdr
)
3629 /* The expression below will return FALSE for any unsupported adapter
3630 * which will keep us "honest" in the future ...
3632 if ((is_t4(adap
->params
.chip
) && hdr
->chip
== FW_HDR_CHIP_T4
) ||
3633 (is_t5(adap
->params
.chip
) && hdr
->chip
== FW_HDR_CHIP_T5
) ||
3634 (is_t6(adap
->params
.chip
) && hdr
->chip
== FW_HDR_CHIP_T6
))
3637 dev_err(adap
->pdev_dev
,
3638 "FW image (%d) is not suitable for this adapter (%d)\n",
3639 hdr
->chip
, CHELSIO_CHIP_VERSION(adap
->params
.chip
));
3644 * t4_load_fw - download firmware
3645 * @adap: the adapter
3646 * @fw_data: the firmware image to write
3649 * Write the supplied firmware image to the card's serial flash.
3651 int t4_load_fw(struct adapter
*adap
, const u8
*fw_data
, unsigned int size
)
3656 u8 first_page
[SF_PAGE_SIZE
];
3657 const __be32
*p
= (const __be32
*)fw_data
;
3658 const struct fw_hdr
*hdr
= (const struct fw_hdr
*)fw_data
;
3659 unsigned int sf_sec_size
= adap
->params
.sf_size
/ adap
->params
.sf_nsec
;
3660 unsigned int fw_start_sec
= FLASH_FW_START_SEC
;
3661 unsigned int fw_size
= FLASH_FW_MAX_SIZE
;
3662 unsigned int fw_start
= FLASH_FW_START
;
3665 dev_err(adap
->pdev_dev
, "FW image has no data\n");
3669 dev_err(adap
->pdev_dev
,
3670 "FW image size not multiple of 512 bytes\n");
3673 if ((unsigned int)be16_to_cpu(hdr
->len512
) * 512 != size
) {
3674 dev_err(adap
->pdev_dev
,
3675 "FW image size differs from size in FW header\n");
3678 if (size
> fw_size
) {
3679 dev_err(adap
->pdev_dev
, "FW image too large, max is %u bytes\n",
3683 if (!t4_fw_matches_chip(adap
, hdr
))
3686 for (csum
= 0, i
= 0; i
< size
/ sizeof(csum
); i
++)
3687 csum
+= be32_to_cpu(p
[i
]);
3689 if (csum
!= 0xffffffff) {
3690 dev_err(adap
->pdev_dev
,
3691 "corrupted firmware image, checksum %#x\n", csum
);
3695 i
= DIV_ROUND_UP(size
, sf_sec_size
); /* # of sectors spanned */
3696 ret
= t4_flash_erase_sectors(adap
, fw_start_sec
, fw_start_sec
+ i
- 1);
3701 * We write the correct version at the end so the driver can see a bad
3702 * version if the FW write fails. Start by writing a copy of the
3703 * first page with a bad version.
3705 memcpy(first_page
, fw_data
, SF_PAGE_SIZE
);
3706 ((struct fw_hdr
*)first_page
)->fw_ver
= cpu_to_be32(0xffffffff);
3707 ret
= t4_write_flash(adap
, fw_start
, SF_PAGE_SIZE
, first_page
);
3712 for (size
-= SF_PAGE_SIZE
; size
; size
-= SF_PAGE_SIZE
) {
3713 addr
+= SF_PAGE_SIZE
;
3714 fw_data
+= SF_PAGE_SIZE
;
3715 ret
= t4_write_flash(adap
, addr
, SF_PAGE_SIZE
, fw_data
);
3720 ret
= t4_write_flash(adap
,
3721 fw_start
+ offsetof(struct fw_hdr
, fw_ver
),
3722 sizeof(hdr
->fw_ver
), (const u8
*)&hdr
->fw_ver
);
3725 dev_err(adap
->pdev_dev
, "firmware download failed, error %d\n",
3728 ret
= t4_get_fw_version(adap
, &adap
->params
.fw_vers
);
3733 * t4_phy_fw_ver - return current PHY firmware version
3734 * @adap: the adapter
3735 * @phy_fw_ver: return value buffer for PHY firmware version
3737 * Returns the current version of external PHY firmware on the
3740 int t4_phy_fw_ver(struct adapter
*adap
, int *phy_fw_ver
)
3745 param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
3746 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW
) |
3747 FW_PARAMS_PARAM_Y_V(adap
->params
.portvec
) |
3748 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION
));
3749 ret
= t4_query_params(adap
, adap
->mbox
, adap
->pf
, 0, 1,
3758 * t4_load_phy_fw - download port PHY firmware
3759 * @adap: the adapter
3760 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3761 * @win_lock: the lock to use to guard the memory copy
3762 * @phy_fw_version: function to check PHY firmware versions
3763 * @phy_fw_data: the PHY firmware image to write
3764 * @phy_fw_size: image size
3766 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3767 * @phy_fw_version is supplied, then it will be used to determine if
3768 * it's necessary to perform the transfer by comparing the version
3769 * of any existing adapter PHY firmware with that of the passed in
3770 * PHY firmware image. If @win_lock is non-NULL then it will be used
3771 * around the call to t4_memory_rw() which transfers the PHY firmware
3774 * A negative error number will be returned if an error occurs. If
3775 * version number support is available and there's no need to upgrade
3776 * the firmware, 0 will be returned. If firmware is successfully
3777 * transferred to the adapter, 1 will be returned.
3779 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3780 * a result, a RESET of the adapter would cause that RAM to lose its
3781 * contents. Thus, loading PHY firmware on such adapters must happen
3782 * after any FW_RESET_CMDs ...
3784 int t4_load_phy_fw(struct adapter
*adap
,
3785 int win
, spinlock_t
*win_lock
,
3786 int (*phy_fw_version
)(const u8
*, size_t),
3787 const u8
*phy_fw_data
, size_t phy_fw_size
)
3789 unsigned long mtype
= 0, maddr
= 0;
3791 int cur_phy_fw_ver
= 0, new_phy_fw_vers
= 0;
3794 /* If we have version number support, then check to see if the adapter
3795 * already has up-to-date PHY firmware loaded.
3797 if (phy_fw_version
) {
3798 new_phy_fw_vers
= phy_fw_version(phy_fw_data
, phy_fw_size
);
3799 ret
= t4_phy_fw_ver(adap
, &cur_phy_fw_ver
);
3803 if (cur_phy_fw_ver
>= new_phy_fw_vers
) {
3804 CH_WARN(adap
, "PHY Firmware already up-to-date, "
3805 "version %#x\n", cur_phy_fw_ver
);
3810 /* Ask the firmware where it wants us to copy the PHY firmware image.
3811 * The size of the file requires a special version of the READ command
3812 * which will pass the file size via the values field in PARAMS_CMD and
3813 * retrieve the return value from firmware and place it in the same
3816 param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
3817 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW
) |
3818 FW_PARAMS_PARAM_Y_V(adap
->params
.portvec
) |
3819 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD
));
3821 ret
= t4_query_params_rw(adap
, adap
->mbox
, adap
->pf
, 0, 1,
3822 ¶m
, &val
, 1, true);
3826 maddr
= (val
& 0xff) << 16;
3828 /* Copy the supplied PHY Firmware image to the adapter memory location
3829 * allocated by the adapter firmware.
3832 spin_lock_bh(win_lock
);
3833 ret
= t4_memory_rw(adap
, win
, mtype
, maddr
,
3834 phy_fw_size
, (__be32
*)phy_fw_data
,
3837 spin_unlock_bh(win_lock
);
3841 /* Tell the firmware that the PHY firmware image has been written to
3842 * RAM and it can now start copying it over to the PHYs. The chip
3843 * firmware will RESET the affected PHYs as part of this operation
3844 * leaving them running the new PHY firmware image.
3846 param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
3847 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW
) |
3848 FW_PARAMS_PARAM_Y_V(adap
->params
.portvec
) |
3849 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD
));
3850 ret
= t4_set_params_timeout(adap
, adap
->mbox
, adap
->pf
, 0, 1,
3851 ¶m
, &val
, 30000);
3853 /* If we have version number support, then check to see that the new
3854 * firmware got loaded properly.
3856 if (phy_fw_version
) {
3857 ret
= t4_phy_fw_ver(adap
, &cur_phy_fw_ver
);
3861 if (cur_phy_fw_ver
!= new_phy_fw_vers
) {
3862 CH_WARN(adap
, "PHY Firmware did not update: "
3863 "version on adapter %#x, "
3864 "version flashed %#x\n",
3865 cur_phy_fw_ver
, new_phy_fw_vers
);
3874 * t4_fwcache - firmware cache operation
3875 * @adap: the adapter
3876 * @op : the operation (flush or flush and invalidate)
3878 int t4_fwcache(struct adapter
*adap
, enum fw_params_param_dev_fwcache op
)
3880 struct fw_params_cmd c
;
3882 memset(&c
, 0, sizeof(c
));
3884 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD
) |
3885 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
3886 FW_PARAMS_CMD_PFN_V(adap
->pf
) |
3887 FW_PARAMS_CMD_VFN_V(0));
3888 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
3890 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
3891 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE
));
3892 c
.param
[0].val
= cpu_to_be32(op
);
3894 return t4_wr_mbox(adap
, adap
->mbox
, &c
, sizeof(c
), NULL
);
3897 void t4_cim_read_pif_la(struct adapter
*adap
, u32
*pif_req
, u32
*pif_rsp
,
3898 unsigned int *pif_req_wrptr
,
3899 unsigned int *pif_rsp_wrptr
)
3902 u32 cfg
, val
, req
, rsp
;
3904 cfg
= t4_read_reg(adap
, CIM_DEBUGCFG_A
);
3905 if (cfg
& LADBGEN_F
)
3906 t4_write_reg(adap
, CIM_DEBUGCFG_A
, cfg
^ LADBGEN_F
);
3908 val
= t4_read_reg(adap
, CIM_DEBUGSTS_A
);
3909 req
= POLADBGWRPTR_G(val
);
3910 rsp
= PILADBGWRPTR_G(val
);
3912 *pif_req_wrptr
= req
;
3914 *pif_rsp_wrptr
= rsp
;
3916 for (i
= 0; i
< CIM_PIFLA_SIZE
; i
++) {
3917 for (j
= 0; j
< 6; j
++) {
3918 t4_write_reg(adap
, CIM_DEBUGCFG_A
, POLADBGRDPTR_V(req
) |
3919 PILADBGRDPTR_V(rsp
));
3920 *pif_req
++ = t4_read_reg(adap
, CIM_PO_LA_DEBUGDATA_A
);
3921 *pif_rsp
++ = t4_read_reg(adap
, CIM_PI_LA_DEBUGDATA_A
);
3925 req
= (req
+ 2) & POLADBGRDPTR_M
;
3926 rsp
= (rsp
+ 2) & PILADBGRDPTR_M
;
3928 t4_write_reg(adap
, CIM_DEBUGCFG_A
, cfg
);
3931 void t4_cim_read_ma_la(struct adapter
*adap
, u32
*ma_req
, u32
*ma_rsp
)
3936 cfg
= t4_read_reg(adap
, CIM_DEBUGCFG_A
);
3937 if (cfg
& LADBGEN_F
)
3938 t4_write_reg(adap
, CIM_DEBUGCFG_A
, cfg
^ LADBGEN_F
);
3940 for (i
= 0; i
< CIM_MALA_SIZE
; i
++) {
3941 for (j
= 0; j
< 5; j
++) {
3943 t4_write_reg(adap
, CIM_DEBUGCFG_A
, POLADBGRDPTR_V(idx
) |
3944 PILADBGRDPTR_V(idx
));
3945 *ma_req
++ = t4_read_reg(adap
, CIM_PO_LA_MADEBUGDATA_A
);
3946 *ma_rsp
++ = t4_read_reg(adap
, CIM_PI_LA_MADEBUGDATA_A
);
3949 t4_write_reg(adap
, CIM_DEBUGCFG_A
, cfg
);
3952 void t4_ulprx_read_la(struct adapter
*adap
, u32
*la_buf
)
3956 for (i
= 0; i
< 8; i
++) {
3957 u32
*p
= la_buf
+ i
;
3959 t4_write_reg(adap
, ULP_RX_LA_CTL_A
, i
);
3960 j
= t4_read_reg(adap
, ULP_RX_LA_WRPTR_A
);
3961 t4_write_reg(adap
, ULP_RX_LA_RDPTR_A
, j
);
3962 for (j
= 0; j
< ULPRX_LA_SIZE
; j
++, p
+= 8)
3963 *p
= t4_read_reg(adap
, ULP_RX_LA_RDDATA_A
);
3967 /* The ADVERT_MASK is used to mask out all of the Advertised Firmware Port
3968 * Capabilities which we control with separate controls -- see, for instance,
3969 * Pause Frames and Forward Error Correction. In order to determine what the
3970 * full set of Advertised Port Capabilities are, the base Advertised Port
3971 * Capabilities (masked by ADVERT_MASK) must be combined with the Advertised
3972 * Port Capabilities associated with those other controls. See
3973 * t4_link_acaps() for how this is done.
3975 #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
3979 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3980 * @caps16: a 16-bit Port Capabilities value
3982 * Returns the equivalent 32-bit Port Capabilities value.
3984 static fw_port_cap32_t
fwcaps16_to_caps32(fw_port_cap16_t caps16
)
3986 fw_port_cap32_t caps32
= 0;
3988 #define CAP16_TO_CAP32(__cap) \
3990 if (caps16 & FW_PORT_CAP_##__cap) \
3991 caps32 |= FW_PORT_CAP32_##__cap; \
3994 CAP16_TO_CAP32(SPEED_100M
);
3995 CAP16_TO_CAP32(SPEED_1G
);
3996 CAP16_TO_CAP32(SPEED_25G
);
3997 CAP16_TO_CAP32(SPEED_10G
);
3998 CAP16_TO_CAP32(SPEED_40G
);
3999 CAP16_TO_CAP32(SPEED_100G
);
4000 CAP16_TO_CAP32(FC_RX
);
4001 CAP16_TO_CAP32(FC_TX
);
4002 CAP16_TO_CAP32(ANEG
);
4003 CAP16_TO_CAP32(FORCE_PAUSE
);
4004 CAP16_TO_CAP32(MDIAUTO
);
4005 CAP16_TO_CAP32(MDISTRAIGHT
);
4006 CAP16_TO_CAP32(FEC_RS
);
4007 CAP16_TO_CAP32(FEC_BASER_RS
);
4008 CAP16_TO_CAP32(802_3_PAUSE
);
4009 CAP16_TO_CAP32(802_3_ASM_DIR
);
4011 #undef CAP16_TO_CAP32
4017 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
4018 * @caps32: a 32-bit Port Capabilities value
4020 * Returns the equivalent 16-bit Port Capabilities value. Note that
4021 * not all 32-bit Port Capabilities can be represented in the 16-bit
4022 * Port Capabilities and some fields/values may not make it.
4024 static fw_port_cap16_t
fwcaps32_to_caps16(fw_port_cap32_t caps32
)
4026 fw_port_cap16_t caps16
= 0;
4028 #define CAP32_TO_CAP16(__cap) \
4030 if (caps32 & FW_PORT_CAP32_##__cap) \
4031 caps16 |= FW_PORT_CAP_##__cap; \
4034 CAP32_TO_CAP16(SPEED_100M
);
4035 CAP32_TO_CAP16(SPEED_1G
);
4036 CAP32_TO_CAP16(SPEED_10G
);
4037 CAP32_TO_CAP16(SPEED_25G
);
4038 CAP32_TO_CAP16(SPEED_40G
);
4039 CAP32_TO_CAP16(SPEED_100G
);
4040 CAP32_TO_CAP16(FC_RX
);
4041 CAP32_TO_CAP16(FC_TX
);
4042 CAP32_TO_CAP16(802_3_PAUSE
);
4043 CAP32_TO_CAP16(802_3_ASM_DIR
);
4044 CAP32_TO_CAP16(ANEG
);
4045 CAP32_TO_CAP16(FORCE_PAUSE
);
4046 CAP32_TO_CAP16(MDIAUTO
);
4047 CAP32_TO_CAP16(MDISTRAIGHT
);
4048 CAP32_TO_CAP16(FEC_RS
);
4049 CAP32_TO_CAP16(FEC_BASER_RS
);
4051 #undef CAP32_TO_CAP16
4056 /* Translate Firmware Port Capabilities Pause specification to Common Code */
4057 static inline enum cc_pause
fwcap_to_cc_pause(fw_port_cap32_t fw_pause
)
4059 enum cc_pause cc_pause
= 0;
4061 if (fw_pause
& FW_PORT_CAP32_FC_RX
)
4062 cc_pause
|= PAUSE_RX
;
4063 if (fw_pause
& FW_PORT_CAP32_FC_TX
)
4064 cc_pause
|= PAUSE_TX
;
4069 /* Translate Common Code Pause specification into Firmware Port Capabilities */
4070 static inline fw_port_cap32_t
cc_to_fwcap_pause(enum cc_pause cc_pause
)
4072 /* Translate orthogonal RX/TX Pause Controls for L1 Configure
4075 fw_port_cap32_t fw_pause
= 0;
4077 if (cc_pause
& PAUSE_RX
)
4078 fw_pause
|= FW_PORT_CAP32_FC_RX
;
4079 if (cc_pause
& PAUSE_TX
)
4080 fw_pause
|= FW_PORT_CAP32_FC_TX
;
4081 if (!(cc_pause
& PAUSE_AUTONEG
))
4082 fw_pause
|= FW_PORT_CAP32_FORCE_PAUSE
;
4084 /* Translate orthogonal Pause controls into IEEE 802.3 Pause,
4085 * Asymmetrical Pause for use in reporting to upper layer OS code, etc.
4086 * Note that these bits are ignored in L1 Configure commands.
4088 if (cc_pause
& PAUSE_RX
) {
4089 if (cc_pause
& PAUSE_TX
)
4090 fw_pause
|= FW_PORT_CAP32_802_3_PAUSE
;
4092 fw_pause
|= FW_PORT_CAP32_802_3_ASM_DIR
;
4093 } else if (cc_pause
& PAUSE_TX
) {
4094 fw_pause
|= FW_PORT_CAP32_802_3_ASM_DIR
;
4100 /* Translate Firmware Forward Error Correction specification to Common Code */
4101 static inline enum cc_fec
fwcap_to_cc_fec(fw_port_cap32_t fw_fec
)
4103 enum cc_fec cc_fec
= 0;
4105 if (fw_fec
& FW_PORT_CAP32_FEC_RS
)
4107 if (fw_fec
& FW_PORT_CAP32_FEC_BASER_RS
)
4108 cc_fec
|= FEC_BASER_RS
;
4113 /* Translate Common Code Forward Error Correction specification to Firmware */
4114 static inline fw_port_cap32_t
cc_to_fwcap_fec(enum cc_fec cc_fec
)
4116 fw_port_cap32_t fw_fec
= 0;
4118 if (cc_fec
& FEC_RS
)
4119 fw_fec
|= FW_PORT_CAP32_FEC_RS
;
4120 if (cc_fec
& FEC_BASER_RS
)
4121 fw_fec
|= FW_PORT_CAP32_FEC_BASER_RS
;
4127 * t4_link_acaps - compute Link Advertised Port Capabilities
4128 * @adapter: the adapter
4129 * @port: the Port ID
4130 * @lc: the Port's Link Configuration
4132 * Synthesize the Advertised Port Capabilities we'll be using based on
4133 * the base Advertised Port Capabilities (which have been filtered by
4134 * ADVERT_MASK) plus the individual controls for things like Pause
4135 * Frames, Forward Error Correction, MDI, etc.
4137 fw_port_cap32_t
t4_link_acaps(struct adapter
*adapter
, unsigned int port
,
4138 struct link_config
*lc
)
4140 fw_port_cap32_t fw_fc
, fw_fec
, acaps
;
4141 unsigned int fw_mdi
;
4144 fw_mdi
= (FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO
) & lc
->pcaps
);
4146 /* Convert driver coding of Pause Frame Flow Control settings into the
4149 fw_fc
= cc_to_fwcap_pause(lc
->requested_fc
);
4151 /* Convert Common Code Forward Error Control settings into the
4152 * Firmware's API. If the current Requested FEC has "Automatic"
4153 * (IEEE 802.3) specified, then we use whatever the Firmware
4154 * sent us as part of its IEEE 802.3-based interpretation of
4155 * the Transceiver Module EPROM FEC parameters. Otherwise we
4156 * use whatever is in the current Requested FEC settings.
4158 if (lc
->requested_fec
& FEC_AUTO
)
4159 cc_fec
= fwcap_to_cc_fec(lc
->def_acaps
);
4161 cc_fec
= lc
->requested_fec
;
4162 fw_fec
= cc_to_fwcap_fec(cc_fec
);
4164 /* Figure out what our Requested Port Capabilities are going to be.
4165 * Note parallel structure in t4_handle_get_port_info() and
4166 * init_link_config().
4168 if (!(lc
->pcaps
& FW_PORT_CAP32_ANEG
)) {
4169 acaps
= lc
->acaps
| fw_fc
| fw_fec
;
4170 lc
->fc
= lc
->requested_fc
& ~PAUSE_AUTONEG
;
4172 } else if (lc
->autoneg
== AUTONEG_DISABLE
) {
4173 acaps
= lc
->speed_caps
| fw_fc
| fw_fec
| fw_mdi
;
4174 lc
->fc
= lc
->requested_fc
& ~PAUSE_AUTONEG
;
4177 acaps
= lc
->acaps
| fw_fc
| fw_fec
| fw_mdi
;
4180 /* Some Requested Port Capabilities are trivially wrong if they exceed
4181 * the Physical Port Capabilities. We can check that here and provide
4182 * moderately useful feedback in the system log.
4184 * Note that older Firmware doesn't have FW_PORT_CAP32_FORCE_PAUSE, so
4185 * we need to exclude this from this check in order to maintain
4188 if ((acaps
& ~lc
->pcaps
) & ~FW_PORT_CAP32_FORCE_PAUSE
) {
4189 dev_err(adapter
->pdev_dev
, "Requested Port Capabilities %#x exceed Physical Port Capabilities %#x\n",
4198 * t4_link_l1cfg_core - apply link configuration to MAC/PHY
4199 * @adapter: the adapter
4200 * @mbox: the Firmware Mailbox to use
4201 * @port: the Port ID
4202 * @lc: the Port's Link Configuration
4203 * @sleep_ok: if true we may sleep while awaiting command completion
4204 * @timeout: time to wait for command to finish before timing out
4205 * (negative implies @sleep_ok=false)
4207 * Set up a port's MAC and PHY according to a desired link configuration.
4208 * - If the PHY can auto-negotiate first decide what to advertise, then
4209 * enable/disable auto-negotiation as desired, and reset.
4210 * - If the PHY does not auto-negotiate just reset it.
4211 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4212 * otherwise do it later based on the outcome of auto-negotiation.
4214 int t4_link_l1cfg_core(struct adapter
*adapter
, unsigned int mbox
,
4215 unsigned int port
, struct link_config
*lc
,
4216 u8 sleep_ok
, int timeout
)
4218 unsigned int fw_caps
= adapter
->params
.fw_caps_support
;
4219 struct fw_port_cmd cmd
;
4220 fw_port_cap32_t rcap
;
4223 if (!(lc
->pcaps
& FW_PORT_CAP32_ANEG
) &&
4224 lc
->autoneg
== AUTONEG_ENABLE
) {
4228 /* Compute our Requested Port Capabilities and send that on to the
4231 rcap
= t4_link_acaps(adapter
, port
, lc
);
4232 memset(&cmd
, 0, sizeof(cmd
));
4233 cmd
.op_to_portid
= cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD
) |
4234 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
4235 FW_PORT_CMD_PORTID_V(port
));
4236 cmd
.action_to_len16
=
4237 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps
== FW_CAPS16
4238 ? FW_PORT_ACTION_L1_CFG
4239 : FW_PORT_ACTION_L1_CFG32
) |
4241 if (fw_caps
== FW_CAPS16
)
4242 cmd
.u
.l1cfg
.rcap
= cpu_to_be32(fwcaps32_to_caps16(rcap
));
4244 cmd
.u
.l1cfg32
.rcap32
= cpu_to_be32(rcap
);
4246 ret
= t4_wr_mbox_meat_timeout(adapter
, mbox
, &cmd
, sizeof(cmd
), NULL
,
4249 /* Unfortunately, even if the Requested Port Capabilities "fit" within
4250 * the Physical Port Capabilities, some combinations of features may
4251 * still not be legal. For example, 40Gb/s and Reed-Solomon Forward
4252 * Error Correction. So if the Firmware rejects the L1 Configure
4253 * request, flag that here.
4256 dev_err(adapter
->pdev_dev
,
4257 "Requested Port Capabilities %#x rejected, error %d\n",
4265 * t4_restart_aneg - restart autonegotiation
4266 * @adap: the adapter
4267 * @mbox: mbox to use for the FW command
4268 * @port: the port id
4270 * Restarts autonegotiation for the selected port.
4272 int t4_restart_aneg(struct adapter
*adap
, unsigned int mbox
, unsigned int port
)
4274 unsigned int fw_caps
= adap
->params
.fw_caps_support
;
4275 struct fw_port_cmd c
;
4277 memset(&c
, 0, sizeof(c
));
4278 c
.op_to_portid
= cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD
) |
4279 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
4280 FW_PORT_CMD_PORTID_V(port
));
4282 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps
== FW_CAPS16
4283 ? FW_PORT_ACTION_L1_CFG
4284 : FW_PORT_ACTION_L1_CFG32
) |
4286 if (fw_caps
== FW_CAPS16
)
4287 c
.u
.l1cfg
.rcap
= cpu_to_be32(FW_PORT_CAP_ANEG
);
4289 c
.u
.l1cfg32
.rcap32
= cpu_to_be32(FW_PORT_CAP32_ANEG
);
4290 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
4293 typedef void (*int_handler_t
)(struct adapter
*adap
);
4296 unsigned int mask
; /* bits to check in interrupt status */
4297 const char *msg
; /* message to print or NULL */
4298 short stat_idx
; /* stat counter to increment or -1 */
4299 unsigned short fatal
; /* whether the condition reported is fatal */
4300 int_handler_t int_handler
; /* platform-specific int handler */
4304 * t4_handle_intr_status - table driven interrupt handler
4305 * @adapter: the adapter that generated the interrupt
4306 * @reg: the interrupt status register to process
4307 * @acts: table of interrupt actions
4309 * A table driven interrupt handler that applies a set of masks to an
4310 * interrupt status word and performs the corresponding actions if the
4311 * interrupts described by the mask have occurred. The actions include
4312 * optionally emitting a warning or alert message. The table is terminated
4313 * by an entry specifying mask 0. Returns the number of fatal interrupt
4316 static int t4_handle_intr_status(struct adapter
*adapter
, unsigned int reg
,
4317 const struct intr_info
*acts
)
4320 unsigned int mask
= 0;
4321 unsigned int status
= t4_read_reg(adapter
, reg
);
4323 for ( ; acts
->mask
; ++acts
) {
4324 if (!(status
& acts
->mask
))
4328 dev_alert(adapter
->pdev_dev
, "%s (0x%x)\n", acts
->msg
,
4329 status
& acts
->mask
);
4330 } else if (acts
->msg
&& printk_ratelimit())
4331 dev_warn(adapter
->pdev_dev
, "%s (0x%x)\n", acts
->msg
,
4332 status
& acts
->mask
);
4333 if (acts
->int_handler
)
4334 acts
->int_handler(adapter
);
4338 if (status
) /* clear processed interrupts */
4339 t4_write_reg(adapter
, reg
, status
);
4344 * Interrupt handler for the PCIE module.
4346 static void pcie_intr_handler(struct adapter
*adapter
)
4348 static const struct intr_info sysbus_intr_info
[] = {
4349 { RNPP_F
, "RXNP array parity error", -1, 1 },
4350 { RPCP_F
, "RXPC array parity error", -1, 1 },
4351 { RCIP_F
, "RXCIF array parity error", -1, 1 },
4352 { RCCP_F
, "Rx completions control array parity error", -1, 1 },
4353 { RFTP_F
, "RXFT array parity error", -1, 1 },
4356 static const struct intr_info pcie_port_intr_info
[] = {
4357 { TPCP_F
, "TXPC array parity error", -1, 1 },
4358 { TNPP_F
, "TXNP array parity error", -1, 1 },
4359 { TFTP_F
, "TXFT array parity error", -1, 1 },
4360 { TCAP_F
, "TXCA array parity error", -1, 1 },
4361 { TCIP_F
, "TXCIF array parity error", -1, 1 },
4362 { RCAP_F
, "RXCA array parity error", -1, 1 },
4363 { OTDD_F
, "outbound request TLP discarded", -1, 1 },
4364 { RDPE_F
, "Rx data parity error", -1, 1 },
4365 { TDUE_F
, "Tx uncorrectable data error", -1, 1 },
4368 static const struct intr_info pcie_intr_info
[] = {
4369 { MSIADDRLPERR_F
, "MSI AddrL parity error", -1, 1 },
4370 { MSIADDRHPERR_F
, "MSI AddrH parity error", -1, 1 },
4371 { MSIDATAPERR_F
, "MSI data parity error", -1, 1 },
4372 { MSIXADDRLPERR_F
, "MSI-X AddrL parity error", -1, 1 },
4373 { MSIXADDRHPERR_F
, "MSI-X AddrH parity error", -1, 1 },
4374 { MSIXDATAPERR_F
, "MSI-X data parity error", -1, 1 },
4375 { MSIXDIPERR_F
, "MSI-X DI parity error", -1, 1 },
4376 { PIOCPLPERR_F
, "PCI PIO completion FIFO parity error", -1, 1 },
4377 { PIOREQPERR_F
, "PCI PIO request FIFO parity error", -1, 1 },
4378 { TARTAGPERR_F
, "PCI PCI target tag FIFO parity error", -1, 1 },
4379 { CCNTPERR_F
, "PCI CMD channel count parity error", -1, 1 },
4380 { CREQPERR_F
, "PCI CMD channel request parity error", -1, 1 },
4381 { CRSPPERR_F
, "PCI CMD channel response parity error", -1, 1 },
4382 { DCNTPERR_F
, "PCI DMA channel count parity error", -1, 1 },
4383 { DREQPERR_F
, "PCI DMA channel request parity error", -1, 1 },
4384 { DRSPPERR_F
, "PCI DMA channel response parity error", -1, 1 },
4385 { HCNTPERR_F
, "PCI HMA channel count parity error", -1, 1 },
4386 { HREQPERR_F
, "PCI HMA channel request parity error", -1, 1 },
4387 { HRSPPERR_F
, "PCI HMA channel response parity error", -1, 1 },
4388 { CFGSNPPERR_F
, "PCI config snoop FIFO parity error", -1, 1 },
4389 { FIDPERR_F
, "PCI FID parity error", -1, 1 },
4390 { INTXCLRPERR_F
, "PCI INTx clear parity error", -1, 1 },
4391 { MATAGPERR_F
, "PCI MA tag parity error", -1, 1 },
4392 { PIOTAGPERR_F
, "PCI PIO tag parity error", -1, 1 },
4393 { RXCPLPERR_F
, "PCI Rx completion parity error", -1, 1 },
4394 { RXWRPERR_F
, "PCI Rx write parity error", -1, 1 },
4395 { RPLPERR_F
, "PCI replay buffer parity error", -1, 1 },
4396 { PCIESINT_F
, "PCI core secondary fault", -1, 1 },
4397 { PCIEPINT_F
, "PCI core primary fault", -1, 1 },
4398 { UNXSPLCPLERR_F
, "PCI unexpected split completion error",
4403 static struct intr_info t5_pcie_intr_info
[] = {
4404 { MSTGRPPERR_F
, "Master Response Read Queue parity error",
4406 { MSTTIMEOUTPERR_F
, "Master Timeout FIFO parity error", -1, 1 },
4407 { MSIXSTIPERR_F
, "MSI-X STI SRAM parity error", -1, 1 },
4408 { MSIXADDRLPERR_F
, "MSI-X AddrL parity error", -1, 1 },
4409 { MSIXADDRHPERR_F
, "MSI-X AddrH parity error", -1, 1 },
4410 { MSIXDATAPERR_F
, "MSI-X data parity error", -1, 1 },
4411 { MSIXDIPERR_F
, "MSI-X DI parity error", -1, 1 },
4412 { PIOCPLGRPPERR_F
, "PCI PIO completion Group FIFO parity error",
4414 { PIOREQGRPPERR_F
, "PCI PIO request Group FIFO parity error",
4416 { TARTAGPERR_F
, "PCI PCI target tag FIFO parity error", -1, 1 },
4417 { MSTTAGQPERR_F
, "PCI master tag queue parity error", -1, 1 },
4418 { CREQPERR_F
, "PCI CMD channel request parity error", -1, 1 },
4419 { CRSPPERR_F
, "PCI CMD channel response parity error", -1, 1 },
4420 { DREQWRPERR_F
, "PCI DMA channel write request parity error",
4422 { DREQPERR_F
, "PCI DMA channel request parity error", -1, 1 },
4423 { DRSPPERR_F
, "PCI DMA channel response parity error", -1, 1 },
4424 { HREQWRPERR_F
, "PCI HMA channel count parity error", -1, 1 },
4425 { HREQPERR_F
, "PCI HMA channel request parity error", -1, 1 },
4426 { HRSPPERR_F
, "PCI HMA channel response parity error", -1, 1 },
4427 { CFGSNPPERR_F
, "PCI config snoop FIFO parity error", -1, 1 },
4428 { FIDPERR_F
, "PCI FID parity error", -1, 1 },
4429 { VFIDPERR_F
, "PCI INTx clear parity error", -1, 1 },
4430 { MAGRPPERR_F
, "PCI MA group FIFO parity error", -1, 1 },
4431 { PIOTAGPERR_F
, "PCI PIO tag parity error", -1, 1 },
4432 { IPRXHDRGRPPERR_F
, "PCI IP Rx header group parity error",
4434 { IPRXDATAGRPPERR_F
, "PCI IP Rx data group parity error",
4436 { RPLPERR_F
, "PCI IP replay buffer parity error", -1, 1 },
4437 { IPSOTPERR_F
, "PCI IP SOT buffer parity error", -1, 1 },
4438 { TRGT1GRPPERR_F
, "PCI TRGT1 group FIFOs parity error", -1, 1 },
4439 { READRSPERR_F
, "Outbound read error", -1, 0 },
4445 if (is_t4(adapter
->params
.chip
))
4446 fat
= t4_handle_intr_status(adapter
,
4447 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A
,
4449 t4_handle_intr_status(adapter
,
4450 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A
,
4451 pcie_port_intr_info
) +
4452 t4_handle_intr_status(adapter
, PCIE_INT_CAUSE_A
,
4455 fat
= t4_handle_intr_status(adapter
, PCIE_INT_CAUSE_A
,
4459 t4_fatal_err(adapter
);
4463 * TP interrupt handler.
4465 static void tp_intr_handler(struct adapter
*adapter
)
4467 static const struct intr_info tp_intr_info
[] = {
4468 { 0x3fffffff, "TP parity error", -1, 1 },
4469 { FLMTXFLSTEMPTY_F
, "TP out of Tx pages", -1, 1 },
4473 if (t4_handle_intr_status(adapter
, TP_INT_CAUSE_A
, tp_intr_info
))
4474 t4_fatal_err(adapter
);
4478 * SGE interrupt handler.
4480 static void sge_intr_handler(struct adapter
*adapter
)
4485 static const struct intr_info sge_intr_info
[] = {
4486 { ERR_CPL_EXCEED_IQE_SIZE_F
,
4487 "SGE received CPL exceeding IQE size", -1, 1 },
4488 { ERR_INVALID_CIDX_INC_F
,
4489 "SGE GTS CIDX increment too large", -1, 0 },
4490 { ERR_CPL_OPCODE_0_F
, "SGE received 0-length CPL", -1, 0 },
4491 { DBFIFO_LP_INT_F
, NULL
, -1, 0, t4_db_full
},
4492 { ERR_DATA_CPL_ON_HIGH_QID1_F
| ERR_DATA_CPL_ON_HIGH_QID0_F
,
4493 "SGE IQID > 1023 received CPL for FL", -1, 0 },
4494 { ERR_BAD_DB_PIDX3_F
, "SGE DBP 3 pidx increment too large", -1,
4496 { ERR_BAD_DB_PIDX2_F
, "SGE DBP 2 pidx increment too large", -1,
4498 { ERR_BAD_DB_PIDX1_F
, "SGE DBP 1 pidx increment too large", -1,
4500 { ERR_BAD_DB_PIDX0_F
, "SGE DBP 0 pidx increment too large", -1,
4502 { ERR_ING_CTXT_PRIO_F
,
4503 "SGE too many priority ingress contexts", -1, 0 },
4504 { INGRESS_SIZE_ERR_F
, "SGE illegal ingress QID", -1, 0 },
4505 { EGRESS_SIZE_ERR_F
, "SGE illegal egress QID", -1, 0 },
4509 static struct intr_info t4t5_sge_intr_info
[] = {
4510 { ERR_DROPPED_DB_F
, NULL
, -1, 0, t4_db_dropped
},
4511 { DBFIFO_HP_INT_F
, NULL
, -1, 0, t4_db_full
},
4512 { ERR_EGR_CTXT_PRIO_F
,
4513 "SGE too many priority egress contexts", -1, 0 },
4517 v
= (u64
)t4_read_reg(adapter
, SGE_INT_CAUSE1_A
) |
4518 ((u64
)t4_read_reg(adapter
, SGE_INT_CAUSE2_A
) << 32);
4520 dev_alert(adapter
->pdev_dev
, "SGE parity error (%#llx)\n",
4521 (unsigned long long)v
);
4522 t4_write_reg(adapter
, SGE_INT_CAUSE1_A
, v
);
4523 t4_write_reg(adapter
, SGE_INT_CAUSE2_A
, v
>> 32);
4526 v
|= t4_handle_intr_status(adapter
, SGE_INT_CAUSE3_A
, sge_intr_info
);
4527 if (CHELSIO_CHIP_VERSION(adapter
->params
.chip
) <= CHELSIO_T5
)
4528 v
|= t4_handle_intr_status(adapter
, SGE_INT_CAUSE3_A
,
4529 t4t5_sge_intr_info
);
4531 err
= t4_read_reg(adapter
, SGE_ERROR_STATS_A
);
4532 if (err
& ERROR_QID_VALID_F
) {
4533 dev_err(adapter
->pdev_dev
, "SGE error for queue %u\n",
4535 if (err
& UNCAPTURED_ERROR_F
)
4536 dev_err(adapter
->pdev_dev
,
4537 "SGE UNCAPTURED_ERROR set (clearing)\n");
4538 t4_write_reg(adapter
, SGE_ERROR_STATS_A
, ERROR_QID_VALID_F
|
4539 UNCAPTURED_ERROR_F
);
4543 t4_fatal_err(adapter
);
4546 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4547 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4548 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4549 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4552 * CIM interrupt handler.
4554 static void cim_intr_handler(struct adapter
*adapter
)
4556 static const struct intr_info cim_intr_info
[] = {
4557 { PREFDROPINT_F
, "CIM control register prefetch drop", -1, 1 },
4558 { CIM_OBQ_INTR
, "CIM OBQ parity error", -1, 1 },
4559 { CIM_IBQ_INTR
, "CIM IBQ parity error", -1, 1 },
4560 { MBUPPARERR_F
, "CIM mailbox uP parity error", -1, 1 },
4561 { MBHOSTPARERR_F
, "CIM mailbox host parity error", -1, 1 },
4562 { TIEQINPARERRINT_F
, "CIM TIEQ outgoing parity error", -1, 1 },
4563 { TIEQOUTPARERRINT_F
, "CIM TIEQ incoming parity error", -1, 1 },
4564 { TIMER0INT_F
, "CIM TIMER0 interrupt", -1, 1 },
4567 static const struct intr_info cim_upintr_info
[] = {
4568 { RSVDSPACEINT_F
, "CIM reserved space access", -1, 1 },
4569 { ILLTRANSINT_F
, "CIM illegal transaction", -1, 1 },
4570 { ILLWRINT_F
, "CIM illegal write", -1, 1 },
4571 { ILLRDINT_F
, "CIM illegal read", -1, 1 },
4572 { ILLRDBEINT_F
, "CIM illegal read BE", -1, 1 },
4573 { ILLWRBEINT_F
, "CIM illegal write BE", -1, 1 },
4574 { SGLRDBOOTINT_F
, "CIM single read from boot space", -1, 1 },
4575 { SGLWRBOOTINT_F
, "CIM single write to boot space", -1, 1 },
4576 { BLKWRBOOTINT_F
, "CIM block write to boot space", -1, 1 },
4577 { SGLRDFLASHINT_F
, "CIM single read from flash space", -1, 1 },
4578 { SGLWRFLASHINT_F
, "CIM single write to flash space", -1, 1 },
4579 { BLKWRFLASHINT_F
, "CIM block write to flash space", -1, 1 },
4580 { SGLRDEEPROMINT_F
, "CIM single EEPROM read", -1, 1 },
4581 { SGLWREEPROMINT_F
, "CIM single EEPROM write", -1, 1 },
4582 { BLKRDEEPROMINT_F
, "CIM block EEPROM read", -1, 1 },
4583 { BLKWREEPROMINT_F
, "CIM block EEPROM write", -1, 1 },
4584 { SGLRDCTLINT_F
, "CIM single read from CTL space", -1, 1 },
4585 { SGLWRCTLINT_F
, "CIM single write to CTL space", -1, 1 },
4586 { BLKRDCTLINT_F
, "CIM block read from CTL space", -1, 1 },
4587 { BLKWRCTLINT_F
, "CIM block write to CTL space", -1, 1 },
4588 { SGLRDPLINT_F
, "CIM single read from PL space", -1, 1 },
4589 { SGLWRPLINT_F
, "CIM single write to PL space", -1, 1 },
4590 { BLKRDPLINT_F
, "CIM block read from PL space", -1, 1 },
4591 { BLKWRPLINT_F
, "CIM block write to PL space", -1, 1 },
4592 { REQOVRLOOKUPINT_F
, "CIM request FIFO overwrite", -1, 1 },
4593 { RSPOVRLOOKUPINT_F
, "CIM response FIFO overwrite", -1, 1 },
4594 { TIMEOUTINT_F
, "CIM PIF timeout", -1, 1 },
4595 { TIMEOUTMAINT_F
, "CIM PIF MA timeout", -1, 1 },
4602 fw_err
= t4_read_reg(adapter
, PCIE_FW_A
);
4603 if (fw_err
& PCIE_FW_ERR_F
)
4604 t4_report_fw_error(adapter
);
4606 /* When the Firmware detects an internal error which normally
4607 * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4608 * in order to make sure the Host sees the Firmware Crash. So
4609 * if we have a Timer0 interrupt and don't see a Firmware Crash,
4610 * ignore the Timer0 interrupt.
4613 val
= t4_read_reg(adapter
, CIM_HOST_INT_CAUSE_A
);
4614 if (val
& TIMER0INT_F
)
4615 if (!(fw_err
& PCIE_FW_ERR_F
) ||
4616 (PCIE_FW_EVAL_G(fw_err
) != PCIE_FW_EVAL_CRASH
))
4617 t4_write_reg(adapter
, CIM_HOST_INT_CAUSE_A
,
4620 fat
= t4_handle_intr_status(adapter
, CIM_HOST_INT_CAUSE_A
,
4622 t4_handle_intr_status(adapter
, CIM_HOST_UPACC_INT_CAUSE_A
,
4625 t4_fatal_err(adapter
);
4629 * ULP RX interrupt handler.
4631 static void ulprx_intr_handler(struct adapter
*adapter
)
4633 static const struct intr_info ulprx_intr_info
[] = {
4634 { 0x1800000, "ULPRX context error", -1, 1 },
4635 { 0x7fffff, "ULPRX parity error", -1, 1 },
4639 if (t4_handle_intr_status(adapter
, ULP_RX_INT_CAUSE_A
, ulprx_intr_info
))
4640 t4_fatal_err(adapter
);
4644 * ULP TX interrupt handler.
4646 static void ulptx_intr_handler(struct adapter
*adapter
)
4648 static const struct intr_info ulptx_intr_info
[] = {
4649 { PBL_BOUND_ERR_CH3_F
, "ULPTX channel 3 PBL out of bounds", -1,
4651 { PBL_BOUND_ERR_CH2_F
, "ULPTX channel 2 PBL out of bounds", -1,
4653 { PBL_BOUND_ERR_CH1_F
, "ULPTX channel 1 PBL out of bounds", -1,
4655 { PBL_BOUND_ERR_CH0_F
, "ULPTX channel 0 PBL out of bounds", -1,
4657 { 0xfffffff, "ULPTX parity error", -1, 1 },
4661 if (t4_handle_intr_status(adapter
, ULP_TX_INT_CAUSE_A
, ulptx_intr_info
))
4662 t4_fatal_err(adapter
);
4666 * PM TX interrupt handler.
4668 static void pmtx_intr_handler(struct adapter
*adapter
)
4670 static const struct intr_info pmtx_intr_info
[] = {
4671 { PCMD_LEN_OVFL0_F
, "PMTX channel 0 pcmd too large", -1, 1 },
4672 { PCMD_LEN_OVFL1_F
, "PMTX channel 1 pcmd too large", -1, 1 },
4673 { PCMD_LEN_OVFL2_F
, "PMTX channel 2 pcmd too large", -1, 1 },
4674 { ZERO_C_CMD_ERROR_F
, "PMTX 0-length pcmd", -1, 1 },
4675 { PMTX_FRAMING_ERROR_F
, "PMTX framing error", -1, 1 },
4676 { OESPI_PAR_ERROR_F
, "PMTX oespi parity error", -1, 1 },
4677 { DB_OPTIONS_PAR_ERROR_F
, "PMTX db_options parity error",
4679 { ICSPI_PAR_ERROR_F
, "PMTX icspi parity error", -1, 1 },
4680 { PMTX_C_PCMD_PAR_ERROR_F
, "PMTX c_pcmd parity error", -1, 1},
4684 if (t4_handle_intr_status(adapter
, PM_TX_INT_CAUSE_A
, pmtx_intr_info
))
4685 t4_fatal_err(adapter
);
4689 * PM RX interrupt handler.
4691 static void pmrx_intr_handler(struct adapter
*adapter
)
4693 static const struct intr_info pmrx_intr_info
[] = {
4694 { ZERO_E_CMD_ERROR_F
, "PMRX 0-length pcmd", -1, 1 },
4695 { PMRX_FRAMING_ERROR_F
, "PMRX framing error", -1, 1 },
4696 { OCSPI_PAR_ERROR_F
, "PMRX ocspi parity error", -1, 1 },
4697 { DB_OPTIONS_PAR_ERROR_F
, "PMRX db_options parity error",
4699 { IESPI_PAR_ERROR_F
, "PMRX iespi parity error", -1, 1 },
4700 { PMRX_E_PCMD_PAR_ERROR_F
, "PMRX e_pcmd parity error", -1, 1},
4704 if (t4_handle_intr_status(adapter
, PM_RX_INT_CAUSE_A
, pmrx_intr_info
))
4705 t4_fatal_err(adapter
);
4709 * CPL switch interrupt handler.
4711 static void cplsw_intr_handler(struct adapter
*adapter
)
4713 static const struct intr_info cplsw_intr_info
[] = {
4714 { CIM_OP_MAP_PERR_F
, "CPLSW CIM op_map parity error", -1, 1 },
4715 { CIM_OVFL_ERROR_F
, "CPLSW CIM overflow", -1, 1 },
4716 { TP_FRAMING_ERROR_F
, "CPLSW TP framing error", -1, 1 },
4717 { SGE_FRAMING_ERROR_F
, "CPLSW SGE framing error", -1, 1 },
4718 { CIM_FRAMING_ERROR_F
, "CPLSW CIM framing error", -1, 1 },
4719 { ZERO_SWITCH_ERROR_F
, "CPLSW no-switch error", -1, 1 },
4723 if (t4_handle_intr_status(adapter
, CPL_INTR_CAUSE_A
, cplsw_intr_info
))
4724 t4_fatal_err(adapter
);
4728 * LE interrupt handler.
4730 static void le_intr_handler(struct adapter
*adap
)
4732 enum chip_type chip
= CHELSIO_CHIP_VERSION(adap
->params
.chip
);
4733 static const struct intr_info le_intr_info
[] = {
4734 { LIPMISS_F
, "LE LIP miss", -1, 0 },
4735 { LIP0_F
, "LE 0 LIP error", -1, 0 },
4736 { PARITYERR_F
, "LE parity error", -1, 1 },
4737 { UNKNOWNCMD_F
, "LE unknown command", -1, 1 },
4738 { REQQPARERR_F
, "LE request queue parity error", -1, 1 },
4742 static struct intr_info t6_le_intr_info
[] = {
4743 { T6_LIPMISS_F
, "LE LIP miss", -1, 0 },
4744 { T6_LIP0_F
, "LE 0 LIP error", -1, 0 },
4745 { TCAMINTPERR_F
, "LE parity error", -1, 1 },
4746 { T6_UNKNOWNCMD_F
, "LE unknown command", -1, 1 },
4747 { SSRAMINTPERR_F
, "LE request queue parity error", -1, 1 },
4751 if (t4_handle_intr_status(adap
, LE_DB_INT_CAUSE_A
,
4752 (chip
<= CHELSIO_T5
) ?
4753 le_intr_info
: t6_le_intr_info
))
4758 * MPS interrupt handler.
4760 static void mps_intr_handler(struct adapter
*adapter
)
4762 static const struct intr_info mps_rx_intr_info
[] = {
4763 { 0xffffff, "MPS Rx parity error", -1, 1 },
4766 static const struct intr_info mps_tx_intr_info
[] = {
4767 { TPFIFO_V(TPFIFO_M
), "MPS Tx TP FIFO parity error", -1, 1 },
4768 { NCSIFIFO_F
, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4769 { TXDATAFIFO_V(TXDATAFIFO_M
), "MPS Tx data FIFO parity error",
4771 { TXDESCFIFO_V(TXDESCFIFO_M
), "MPS Tx desc FIFO parity error",
4773 { BUBBLE_F
, "MPS Tx underflow", -1, 1 },
4774 { SECNTERR_F
, "MPS Tx SOP/EOP error", -1, 1 },
4775 { FRMERR_F
, "MPS Tx framing error", -1, 1 },
4778 static const struct intr_info t6_mps_tx_intr_info
[] = {
4779 { TPFIFO_V(TPFIFO_M
), "MPS Tx TP FIFO parity error", -1, 1 },
4780 { NCSIFIFO_F
, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4781 { TXDATAFIFO_V(TXDATAFIFO_M
), "MPS Tx data FIFO parity error",
4783 { TXDESCFIFO_V(TXDESCFIFO_M
), "MPS Tx desc FIFO parity error",
4785 /* MPS Tx Bubble is normal for T6 */
4786 { SECNTERR_F
, "MPS Tx SOP/EOP error", -1, 1 },
4787 { FRMERR_F
, "MPS Tx framing error", -1, 1 },
4790 static const struct intr_info mps_trc_intr_info
[] = {
4791 { FILTMEM_V(FILTMEM_M
), "MPS TRC filter parity error", -1, 1 },
4792 { PKTFIFO_V(PKTFIFO_M
), "MPS TRC packet FIFO parity error",
4794 { MISCPERR_F
, "MPS TRC misc parity error", -1, 1 },
4797 static const struct intr_info mps_stat_sram_intr_info
[] = {
4798 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4801 static const struct intr_info mps_stat_tx_intr_info
[] = {
4802 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4805 static const struct intr_info mps_stat_rx_intr_info
[] = {
4806 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4809 static const struct intr_info mps_cls_intr_info
[] = {
4810 { MATCHSRAM_F
, "MPS match SRAM parity error", -1, 1 },
4811 { MATCHTCAM_F
, "MPS match TCAM parity error", -1, 1 },
4812 { HASHSRAM_F
, "MPS hash SRAM parity error", -1, 1 },
4818 fat
= t4_handle_intr_status(adapter
, MPS_RX_PERR_INT_CAUSE_A
,
4820 t4_handle_intr_status(adapter
, MPS_TX_INT_CAUSE_A
,
4821 is_t6(adapter
->params
.chip
)
4822 ? t6_mps_tx_intr_info
4823 : mps_tx_intr_info
) +
4824 t4_handle_intr_status(adapter
, MPS_TRC_INT_CAUSE_A
,
4825 mps_trc_intr_info
) +
4826 t4_handle_intr_status(adapter
, MPS_STAT_PERR_INT_CAUSE_SRAM_A
,
4827 mps_stat_sram_intr_info
) +
4828 t4_handle_intr_status(adapter
, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A
,
4829 mps_stat_tx_intr_info
) +
4830 t4_handle_intr_status(adapter
, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A
,
4831 mps_stat_rx_intr_info
) +
4832 t4_handle_intr_status(adapter
, MPS_CLS_INT_CAUSE_A
,
4835 t4_write_reg(adapter
, MPS_INT_CAUSE_A
, 0);
4836 t4_read_reg(adapter
, MPS_INT_CAUSE_A
); /* flush */
4838 t4_fatal_err(adapter
);
4841 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4845 * EDC/MC interrupt handler.
4847 static void mem_intr_handler(struct adapter
*adapter
, int idx
)
4849 static const char name
[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4851 unsigned int addr
, cnt_addr
, v
;
4853 if (idx
<= MEM_EDC1
) {
4854 addr
= EDC_REG(EDC_INT_CAUSE_A
, idx
);
4855 cnt_addr
= EDC_REG(EDC_ECC_STATUS_A
, idx
);
4856 } else if (idx
== MEM_MC
) {
4857 if (is_t4(adapter
->params
.chip
)) {
4858 addr
= MC_INT_CAUSE_A
;
4859 cnt_addr
= MC_ECC_STATUS_A
;
4861 addr
= MC_P_INT_CAUSE_A
;
4862 cnt_addr
= MC_P_ECC_STATUS_A
;
4865 addr
= MC_REG(MC_P_INT_CAUSE_A
, 1);
4866 cnt_addr
= MC_REG(MC_P_ECC_STATUS_A
, 1);
4869 v
= t4_read_reg(adapter
, addr
) & MEM_INT_MASK
;
4870 if (v
& PERR_INT_CAUSE_F
)
4871 dev_alert(adapter
->pdev_dev
, "%s FIFO parity error\n",
4873 if (v
& ECC_CE_INT_CAUSE_F
) {
4874 u32 cnt
= ECC_CECNT_G(t4_read_reg(adapter
, cnt_addr
));
4876 t4_edc_err_read(adapter
, idx
);
4878 t4_write_reg(adapter
, cnt_addr
, ECC_CECNT_V(ECC_CECNT_M
));
4879 if (printk_ratelimit())
4880 dev_warn(adapter
->pdev_dev
,
4881 "%u %s correctable ECC data error%s\n",
4882 cnt
, name
[idx
], cnt
> 1 ? "s" : "");
4884 if (v
& ECC_UE_INT_CAUSE_F
)
4885 dev_alert(adapter
->pdev_dev
,
4886 "%s uncorrectable ECC data error\n", name
[idx
]);
4888 t4_write_reg(adapter
, addr
, v
);
4889 if (v
& (PERR_INT_CAUSE_F
| ECC_UE_INT_CAUSE_F
))
4890 t4_fatal_err(adapter
);
4894 * MA interrupt handler.
4896 static void ma_intr_handler(struct adapter
*adap
)
4898 u32 v
, status
= t4_read_reg(adap
, MA_INT_CAUSE_A
);
4900 if (status
& MEM_PERR_INT_CAUSE_F
) {
4901 dev_alert(adap
->pdev_dev
,
4902 "MA parity error, parity status %#x\n",
4903 t4_read_reg(adap
, MA_PARITY_ERROR_STATUS1_A
));
4904 if (is_t5(adap
->params
.chip
))
4905 dev_alert(adap
->pdev_dev
,
4906 "MA parity error, parity status %#x\n",
4908 MA_PARITY_ERROR_STATUS2_A
));
4910 if (status
& MEM_WRAP_INT_CAUSE_F
) {
4911 v
= t4_read_reg(adap
, MA_INT_WRAP_STATUS_A
);
4912 dev_alert(adap
->pdev_dev
, "MA address wrap-around error by "
4913 "client %u to address %#x\n",
4914 MEM_WRAP_CLIENT_NUM_G(v
),
4915 MEM_WRAP_ADDRESS_G(v
) << 4);
4917 t4_write_reg(adap
, MA_INT_CAUSE_A
, status
);
4922 * SMB interrupt handler.
4924 static void smb_intr_handler(struct adapter
*adap
)
4926 static const struct intr_info smb_intr_info
[] = {
4927 { MSTTXFIFOPARINT_F
, "SMB master Tx FIFO parity error", -1, 1 },
4928 { MSTRXFIFOPARINT_F
, "SMB master Rx FIFO parity error", -1, 1 },
4929 { SLVFIFOPARINT_F
, "SMB slave FIFO parity error", -1, 1 },
4933 if (t4_handle_intr_status(adap
, SMB_INT_CAUSE_A
, smb_intr_info
))
4938 * NC-SI interrupt handler.
4940 static void ncsi_intr_handler(struct adapter
*adap
)
4942 static const struct intr_info ncsi_intr_info
[] = {
4943 { CIM_DM_PRTY_ERR_F
, "NC-SI CIM parity error", -1, 1 },
4944 { MPS_DM_PRTY_ERR_F
, "NC-SI MPS parity error", -1, 1 },
4945 { TXFIFO_PRTY_ERR_F
, "NC-SI Tx FIFO parity error", -1, 1 },
4946 { RXFIFO_PRTY_ERR_F
, "NC-SI Rx FIFO parity error", -1, 1 },
4950 if (t4_handle_intr_status(adap
, NCSI_INT_CAUSE_A
, ncsi_intr_info
))
4955 * XGMAC interrupt handler.
4957 static void xgmac_intr_handler(struct adapter
*adap
, int port
)
4959 u32 v
, int_cause_reg
;
4961 if (is_t4(adap
->params
.chip
))
4962 int_cause_reg
= PORT_REG(port
, XGMAC_PORT_INT_CAUSE_A
);
4964 int_cause_reg
= T5_PORT_REG(port
, MAC_PORT_INT_CAUSE_A
);
4966 v
= t4_read_reg(adap
, int_cause_reg
);
4968 v
&= TXFIFO_PRTY_ERR_F
| RXFIFO_PRTY_ERR_F
;
4972 if (v
& TXFIFO_PRTY_ERR_F
)
4973 dev_alert(adap
->pdev_dev
, "XGMAC %d Tx FIFO parity error\n",
4975 if (v
& RXFIFO_PRTY_ERR_F
)
4976 dev_alert(adap
->pdev_dev
, "XGMAC %d Rx FIFO parity error\n",
4978 t4_write_reg(adap
, PORT_REG(port
, XGMAC_PORT_INT_CAUSE_A
), v
);
4983 * PL interrupt handler.
4985 static void pl_intr_handler(struct adapter
*adap
)
4987 static const struct intr_info pl_intr_info
[] = {
4988 { FATALPERR_F
, "T4 fatal parity error", -1, 1 },
4989 { PERRVFID_F
, "PL VFID_MAP parity error", -1, 1 },
4993 if (t4_handle_intr_status(adap
, PL_PL_INT_CAUSE_A
, pl_intr_info
))
4997 #define PF_INTR_MASK (PFSW_F)
4998 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4999 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
5000 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
5003 * t4_slow_intr_handler - control path interrupt handler
5004 * @adapter: the adapter
5006 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
5007 * The designation 'slow' is because it involves register reads, while
5008 * data interrupts typically don't involve any MMIOs.
5010 int t4_slow_intr_handler(struct adapter
*adapter
)
5012 /* There are rare cases where a PL_INT_CAUSE bit may end up getting
5013 * set when the corresponding PL_INT_ENABLE bit isn't set. It's
5014 * easiest just to mask that case here.
5016 u32 raw_cause
= t4_read_reg(adapter
, PL_INT_CAUSE_A
);
5017 u32 enable
= t4_read_reg(adapter
, PL_INT_ENABLE_A
);
5018 u32 cause
= raw_cause
& enable
;
5020 if (!(cause
& GLBL_INTR_MASK
))
5023 cim_intr_handler(adapter
);
5025 mps_intr_handler(adapter
);
5027 ncsi_intr_handler(adapter
);
5029 pl_intr_handler(adapter
);
5031 smb_intr_handler(adapter
);
5032 if (cause
& XGMAC0_F
)
5033 xgmac_intr_handler(adapter
, 0);
5034 if (cause
& XGMAC1_F
)
5035 xgmac_intr_handler(adapter
, 1);
5036 if (cause
& XGMAC_KR0_F
)
5037 xgmac_intr_handler(adapter
, 2);
5038 if (cause
& XGMAC_KR1_F
)
5039 xgmac_intr_handler(adapter
, 3);
5041 pcie_intr_handler(adapter
);
5043 mem_intr_handler(adapter
, MEM_MC
);
5044 if (is_t5(adapter
->params
.chip
) && (cause
& MC1_F
))
5045 mem_intr_handler(adapter
, MEM_MC1
);
5047 mem_intr_handler(adapter
, MEM_EDC0
);
5049 mem_intr_handler(adapter
, MEM_EDC1
);
5051 le_intr_handler(adapter
);
5053 tp_intr_handler(adapter
);
5055 ma_intr_handler(adapter
);
5056 if (cause
& PM_TX_F
)
5057 pmtx_intr_handler(adapter
);
5058 if (cause
& PM_RX_F
)
5059 pmrx_intr_handler(adapter
);
5060 if (cause
& ULP_RX_F
)
5061 ulprx_intr_handler(adapter
);
5062 if (cause
& CPL_SWITCH_F
)
5063 cplsw_intr_handler(adapter
);
5065 sge_intr_handler(adapter
);
5066 if (cause
& ULP_TX_F
)
5067 ulptx_intr_handler(adapter
);
5069 /* Clear the interrupts just processed for which we are the master. */
5070 t4_write_reg(adapter
, PL_INT_CAUSE_A
, raw_cause
& GLBL_INTR_MASK
);
5071 (void)t4_read_reg(adapter
, PL_INT_CAUSE_A
); /* flush */
5076 * t4_intr_enable - enable interrupts
5077 * @adapter: the adapter whose interrupts should be enabled
5079 * Enable PF-specific interrupts for the calling function and the top-level
5080 * interrupt concentrator for global interrupts. Interrupts are already
5081 * enabled at each module, here we just enable the roots of the interrupt
5084 * Note: this function should be called only when the driver manages
5085 * non PF-specific interrupts from the various HW modules. Only one PCI
5086 * function at a time should be doing this.
5088 void t4_intr_enable(struct adapter
*adapter
)
5091 u32 whoami
= t4_read_reg(adapter
, PL_WHOAMI_A
);
5092 u32 pf
= CHELSIO_CHIP_VERSION(adapter
->params
.chip
) <= CHELSIO_T5
?
5093 SOURCEPF_G(whoami
) : T6_SOURCEPF_G(whoami
);
5095 if (CHELSIO_CHIP_VERSION(adapter
->params
.chip
) <= CHELSIO_T5
)
5096 val
= ERR_DROPPED_DB_F
| ERR_EGR_CTXT_PRIO_F
| DBFIFO_HP_INT_F
;
5097 t4_write_reg(adapter
, SGE_INT_ENABLE3_A
, ERR_CPL_EXCEED_IQE_SIZE_F
|
5098 ERR_INVALID_CIDX_INC_F
| ERR_CPL_OPCODE_0_F
|
5099 ERR_DATA_CPL_ON_HIGH_QID1_F
| INGRESS_SIZE_ERR_F
|
5100 ERR_DATA_CPL_ON_HIGH_QID0_F
| ERR_BAD_DB_PIDX3_F
|
5101 ERR_BAD_DB_PIDX2_F
| ERR_BAD_DB_PIDX1_F
|
5102 ERR_BAD_DB_PIDX0_F
| ERR_ING_CTXT_PRIO_F
|
5103 DBFIFO_LP_INT_F
| EGRESS_SIZE_ERR_F
| val
);
5104 t4_write_reg(adapter
, MYPF_REG(PL_PF_INT_ENABLE_A
), PF_INTR_MASK
);
5105 t4_set_reg_field(adapter
, PL_INT_MAP0_A
, 0, 1 << pf
);
5109 * t4_intr_disable - disable interrupts
5110 * @adapter: the adapter whose interrupts should be disabled
5112 * Disable interrupts. We only disable the top-level interrupt
5113 * concentrators. The caller must be a PCI function managing global
5116 void t4_intr_disable(struct adapter
*adapter
)
5120 if (pci_channel_offline(adapter
->pdev
))
5123 whoami
= t4_read_reg(adapter
, PL_WHOAMI_A
);
5124 pf
= CHELSIO_CHIP_VERSION(adapter
->params
.chip
) <= CHELSIO_T5
?
5125 SOURCEPF_G(whoami
) : T6_SOURCEPF_G(whoami
);
5127 t4_write_reg(adapter
, MYPF_REG(PL_PF_INT_ENABLE_A
), 0);
5128 t4_set_reg_field(adapter
, PL_INT_MAP0_A
, 1 << pf
, 0);
5131 unsigned int t4_chip_rss_size(struct adapter
*adap
)
5133 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) <= CHELSIO_T5
)
5134 return RSS_NENTRIES
;
5136 return T6_RSS_NENTRIES
;
5140 * t4_config_rss_range - configure a portion of the RSS mapping table
5141 * @adapter: the adapter
5142 * @mbox: mbox to use for the FW command
5143 * @viid: virtual interface whose RSS subtable is to be written
5144 * @start: start entry in the table to write
5145 * @n: how many table entries to write
5146 * @rspq: values for the response queue lookup table
5147 * @nrspq: number of values in @rspq
5149 * Programs the selected part of the VI's RSS mapping table with the
5150 * provided values. If @nrspq < @n the supplied values are used repeatedly
5151 * until the full table range is populated.
5153 * The caller must ensure the values in @rspq are in the range allowed for
5156 int t4_config_rss_range(struct adapter
*adapter
, int mbox
, unsigned int viid
,
5157 int start
, int n
, const u16
*rspq
, unsigned int nrspq
)
5160 const u16
*rsp
= rspq
;
5161 const u16
*rsp_end
= rspq
+ nrspq
;
5162 struct fw_rss_ind_tbl_cmd cmd
;
5164 memset(&cmd
, 0, sizeof(cmd
));
5165 cmd
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD
) |
5166 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
5167 FW_RSS_IND_TBL_CMD_VIID_V(viid
));
5168 cmd
.retval_len16
= cpu_to_be32(FW_LEN16(cmd
));
5170 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
5172 int nq
= min(n
, 32);
5173 __be32
*qp
= &cmd
.iq0_to_iq2
;
5175 cmd
.niqid
= cpu_to_be16(nq
);
5176 cmd
.startidx
= cpu_to_be16(start
);
5184 v
= FW_RSS_IND_TBL_CMD_IQ0_V(*rsp
);
5185 if (++rsp
>= rsp_end
)
5187 v
|= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp
);
5188 if (++rsp
>= rsp_end
)
5190 v
|= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp
);
5191 if (++rsp
>= rsp_end
)
5194 *qp
++ = cpu_to_be32(v
);
5198 ret
= t4_wr_mbox(adapter
, mbox
, &cmd
, sizeof(cmd
), NULL
);
5206 * t4_config_glbl_rss - configure the global RSS mode
5207 * @adapter: the adapter
5208 * @mbox: mbox to use for the FW command
5209 * @mode: global RSS mode
5210 * @flags: mode-specific flags
5212 * Sets the global RSS mode.
5214 int t4_config_glbl_rss(struct adapter
*adapter
, int mbox
, unsigned int mode
,
5217 struct fw_rss_glb_config_cmd c
;
5219 memset(&c
, 0, sizeof(c
));
5220 c
.op_to_write
= cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD
) |
5221 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
);
5222 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
5223 if (mode
== FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL
) {
5224 c
.u
.manual
.mode_pkd
=
5225 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode
));
5226 } else if (mode
== FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL
) {
5227 c
.u
.basicvirtual
.mode_pkd
=
5228 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode
));
5229 c
.u
.basicvirtual
.synmapen_to_hashtoeplitz
= cpu_to_be32(flags
);
5232 return t4_wr_mbox(adapter
, mbox
, &c
, sizeof(c
), NULL
);
5236 * t4_config_vi_rss - configure per VI RSS settings
5237 * @adapter: the adapter
5238 * @mbox: mbox to use for the FW command
5241 * @defq: id of the default RSS queue for the VI.
5243 * Configures VI-specific RSS properties.
5245 int t4_config_vi_rss(struct adapter
*adapter
, int mbox
, unsigned int viid
,
5246 unsigned int flags
, unsigned int defq
)
5248 struct fw_rss_vi_config_cmd c
;
5250 memset(&c
, 0, sizeof(c
));
5251 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD
) |
5252 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
5253 FW_RSS_VI_CONFIG_CMD_VIID_V(viid
));
5254 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
5255 c
.u
.basicvirtual
.defaultq_to_udpen
= cpu_to_be32(flags
|
5256 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq
));
5257 return t4_wr_mbox(adapter
, mbox
, &c
, sizeof(c
), NULL
);
5260 /* Read an RSS table row */
5261 static int rd_rss_row(struct adapter
*adap
, int row
, u32
*val
)
5263 t4_write_reg(adap
, TP_RSS_LKP_TABLE_A
, 0xfff00000 | row
);
5264 return t4_wait_op_done_val(adap
, TP_RSS_LKP_TABLE_A
, LKPTBLROWVLD_F
, 1,
5269 * t4_read_rss - read the contents of the RSS mapping table
5270 * @adapter: the adapter
5271 * @map: holds the contents of the RSS mapping table
5273 * Reads the contents of the RSS hash->queue mapping table.
5275 int t4_read_rss(struct adapter
*adapter
, u16
*map
)
5277 int i
, ret
, nentries
;
5280 nentries
= t4_chip_rss_size(adapter
);
5281 for (i
= 0; i
< nentries
/ 2; ++i
) {
5282 ret
= rd_rss_row(adapter
, i
, &val
);
5285 *map
++ = LKPTBLQUEUE0_G(val
);
5286 *map
++ = LKPTBLQUEUE1_G(val
);
5291 static unsigned int t4_use_ldst(struct adapter
*adap
)
5293 return (adap
->flags
& CXGB4_FW_OK
) && !adap
->use_bd
;
5297 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5298 * @adap: the adapter
5299 * @cmd: TP fw ldst address space type
5300 * @vals: where the indirect register values are stored/written
5301 * @nregs: how many indirect registers to read/write
5302 * @start_idx: index of first indirect register to read/write
5303 * @rw: Read (1) or Write (0)
5304 * @sleep_ok: if true we may sleep while awaiting command completion
5306 * Access TP indirect registers through LDST
5308 static int t4_tp_fw_ldst_rw(struct adapter
*adap
, int cmd
, u32
*vals
,
5309 unsigned int nregs
, unsigned int start_index
,
5310 unsigned int rw
, bool sleep_ok
)
5314 struct fw_ldst_cmd c
;
5316 for (i
= 0; i
< nregs
; i
++) {
5317 memset(&c
, 0, sizeof(c
));
5318 c
.op_to_addrspace
= cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
5320 (rw
? FW_CMD_READ_F
:
5322 FW_LDST_CMD_ADDRSPACE_V(cmd
));
5323 c
.cycles_to_len16
= cpu_to_be32(FW_LEN16(c
));
5325 c
.u
.addrval
.addr
= cpu_to_be32(start_index
+ i
);
5326 c
.u
.addrval
.val
= rw
? 0 : cpu_to_be32(vals
[i
]);
5327 ret
= t4_wr_mbox_meat(adap
, adap
->mbox
, &c
, sizeof(c
), &c
,
5333 vals
[i
] = be32_to_cpu(c
.u
.addrval
.val
);
5339 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5340 * @adap: the adapter
5341 * @reg_addr: Address Register
5342 * @reg_data: Data register
5343 * @buff: where the indirect register values are stored/written
5344 * @nregs: how many indirect registers to read/write
5345 * @start_index: index of first indirect register to read/write
5346 * @rw: READ(1) or WRITE(0)
5347 * @sleep_ok: if true we may sleep while awaiting command completion
5349 * Read/Write TP indirect registers through LDST if possible.
5350 * Else, use backdoor access
5352 static void t4_tp_indirect_rw(struct adapter
*adap
, u32 reg_addr
, u32 reg_data
,
5353 u32
*buff
, u32 nregs
, u32 start_index
, int rw
,
5361 cmd
= FW_LDST_ADDRSPC_TP_PIO
;
5363 case TP_TM_PIO_ADDR_A
:
5364 cmd
= FW_LDST_ADDRSPC_TP_TM_PIO
;
5366 case TP_MIB_INDEX_A
:
5367 cmd
= FW_LDST_ADDRSPC_TP_MIB
;
5370 goto indirect_access
;
5373 if (t4_use_ldst(adap
))
5374 rc
= t4_tp_fw_ldst_rw(adap
, cmd
, buff
, nregs
, start_index
, rw
,
5381 t4_read_indirect(adap
, reg_addr
, reg_data
, buff
, nregs
,
5384 t4_write_indirect(adap
, reg_addr
, reg_data
, buff
, nregs
,
5390 * t4_tp_pio_read - Read TP PIO registers
5391 * @adap: the adapter
5392 * @buff: where the indirect register values are written
5393 * @nregs: how many indirect registers to read
5394 * @start_index: index of first indirect register to read
5395 * @sleep_ok: if true we may sleep while awaiting command completion
5397 * Read TP PIO Registers
5399 void t4_tp_pio_read(struct adapter
*adap
, u32
*buff
, u32 nregs
,
5400 u32 start_index
, bool sleep_ok
)
5402 t4_tp_indirect_rw(adap
, TP_PIO_ADDR_A
, TP_PIO_DATA_A
, buff
, nregs
,
5403 start_index
, 1, sleep_ok
);
5407 * t4_tp_pio_write - Write TP PIO registers
5408 * @adap: the adapter
5409 * @buff: where the indirect register values are stored
5410 * @nregs: how many indirect registers to write
5411 * @start_index: index of first indirect register to write
5412 * @sleep_ok: if true we may sleep while awaiting command completion
5414 * Write TP PIO Registers
5416 static void t4_tp_pio_write(struct adapter
*adap
, u32
*buff
, u32 nregs
,
5417 u32 start_index
, bool sleep_ok
)
5419 t4_tp_indirect_rw(adap
, TP_PIO_ADDR_A
, TP_PIO_DATA_A
, buff
, nregs
,
5420 start_index
, 0, sleep_ok
);
5424 * t4_tp_tm_pio_read - Read TP TM PIO registers
5425 * @adap: the adapter
5426 * @buff: where the indirect register values are written
5427 * @nregs: how many indirect registers to read
5428 * @start_index: index of first indirect register to read
5429 * @sleep_ok: if true we may sleep while awaiting command completion
5431 * Read TP TM PIO Registers
5433 void t4_tp_tm_pio_read(struct adapter
*adap
, u32
*buff
, u32 nregs
,
5434 u32 start_index
, bool sleep_ok
)
5436 t4_tp_indirect_rw(adap
, TP_TM_PIO_ADDR_A
, TP_TM_PIO_DATA_A
, buff
,
5437 nregs
, start_index
, 1, sleep_ok
);
5441 * t4_tp_mib_read - Read TP MIB registers
5442 * @adap: the adapter
5443 * @buff: where the indirect register values are written
5444 * @nregs: how many indirect registers to read
5445 * @start_index: index of first indirect register to read
5446 * @sleep_ok: if true we may sleep while awaiting command completion
5448 * Read TP MIB Registers
5450 void t4_tp_mib_read(struct adapter
*adap
, u32
*buff
, u32 nregs
, u32 start_index
,
5453 t4_tp_indirect_rw(adap
, TP_MIB_INDEX_A
, TP_MIB_DATA_A
, buff
, nregs
,
5454 start_index
, 1, sleep_ok
);
5458 * t4_read_rss_key - read the global RSS key
5459 * @adap: the adapter
5460 * @key: 10-entry array holding the 320-bit RSS key
5461 * @sleep_ok: if true we may sleep while awaiting command completion
5463 * Reads the global 320-bit RSS key.
5465 void t4_read_rss_key(struct adapter
*adap
, u32
*key
, bool sleep_ok
)
5467 t4_tp_pio_read(adap
, key
, 10, TP_RSS_SECRET_KEY0_A
, sleep_ok
);
5471 * t4_write_rss_key - program one of the RSS keys
5472 * @adap: the adapter
5473 * @key: 10-entry array holding the 320-bit RSS key
5474 * @idx: which RSS key to write
5475 * @sleep_ok: if true we may sleep while awaiting command completion
5477 * Writes one of the RSS keys with the given 320-bit value. If @idx is
5478 * 0..15 the corresponding entry in the RSS key table is written,
5479 * otherwise the global RSS key is written.
5481 void t4_write_rss_key(struct adapter
*adap
, const u32
*key
, int idx
,
5484 u8 rss_key_addr_cnt
= 16;
5485 u32 vrt
= t4_read_reg(adap
, TP_RSS_CONFIG_VRT_A
);
5487 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5488 * allows access to key addresses 16-63 by using KeyWrAddrX
5489 * as index[5:4](upper 2) into key table
5491 if ((CHELSIO_CHIP_VERSION(adap
->params
.chip
) > CHELSIO_T5
) &&
5492 (vrt
& KEYEXTEND_F
) && (KEYMODE_G(vrt
) == 3))
5493 rss_key_addr_cnt
= 32;
5495 t4_tp_pio_write(adap
, (void *)key
, 10, TP_RSS_SECRET_KEY0_A
, sleep_ok
);
5497 if (idx
>= 0 && idx
< rss_key_addr_cnt
) {
5498 if (rss_key_addr_cnt
> 16)
5499 t4_write_reg(adap
, TP_RSS_CONFIG_VRT_A
,
5500 KEYWRADDRX_V(idx
>> 4) |
5501 T6_VFWRADDR_V(idx
) | KEYWREN_F
);
5503 t4_write_reg(adap
, TP_RSS_CONFIG_VRT_A
,
5504 KEYWRADDR_V(idx
) | KEYWREN_F
);
5509 * t4_read_rss_pf_config - read PF RSS Configuration Table
5510 * @adapter: the adapter
5511 * @index: the entry in the PF RSS table to read
5512 * @valp: where to store the returned value
5513 * @sleep_ok: if true we may sleep while awaiting command completion
5515 * Reads the PF RSS Configuration Table at the specified index and returns
5516 * the value found there.
5518 void t4_read_rss_pf_config(struct adapter
*adapter
, unsigned int index
,
5519 u32
*valp
, bool sleep_ok
)
5521 t4_tp_pio_read(adapter
, valp
, 1, TP_RSS_PF0_CONFIG_A
+ index
, sleep_ok
);
5525 * t4_read_rss_vf_config - read VF RSS Configuration Table
5526 * @adapter: the adapter
5527 * @index: the entry in the VF RSS table to read
5528 * @vfl: where to store the returned VFL
5529 * @vfh: where to store the returned VFH
5530 * @sleep_ok: if true we may sleep while awaiting command completion
5532 * Reads the VF RSS Configuration Table at the specified index and returns
5533 * the (VFL, VFH) values found there.
5535 void t4_read_rss_vf_config(struct adapter
*adapter
, unsigned int index
,
5536 u32
*vfl
, u32
*vfh
, bool sleep_ok
)
5538 u32 vrt
, mask
, data
;
5540 if (CHELSIO_CHIP_VERSION(adapter
->params
.chip
) <= CHELSIO_T5
) {
5541 mask
= VFWRADDR_V(VFWRADDR_M
);
5542 data
= VFWRADDR_V(index
);
5544 mask
= T6_VFWRADDR_V(T6_VFWRADDR_M
);
5545 data
= T6_VFWRADDR_V(index
);
5548 /* Request that the index'th VF Table values be read into VFL/VFH.
5550 vrt
= t4_read_reg(adapter
, TP_RSS_CONFIG_VRT_A
);
5551 vrt
&= ~(VFRDRG_F
| VFWREN_F
| KEYWREN_F
| mask
);
5552 vrt
|= data
| VFRDEN_F
;
5553 t4_write_reg(adapter
, TP_RSS_CONFIG_VRT_A
, vrt
);
5555 /* Grab the VFL/VFH values ...
5557 t4_tp_pio_read(adapter
, vfl
, 1, TP_RSS_VFL_CONFIG_A
, sleep_ok
);
5558 t4_tp_pio_read(adapter
, vfh
, 1, TP_RSS_VFH_CONFIG_A
, sleep_ok
);
5562 * t4_read_rss_pf_map - read PF RSS Map
5563 * @adapter: the adapter
5564 * @sleep_ok: if true we may sleep while awaiting command completion
5566 * Reads the PF RSS Map register and returns its value.
5568 u32
t4_read_rss_pf_map(struct adapter
*adapter
, bool sleep_ok
)
5572 t4_tp_pio_read(adapter
, &pfmap
, 1, TP_RSS_PF_MAP_A
, sleep_ok
);
5577 * t4_read_rss_pf_mask - read PF RSS Mask
5578 * @adapter: the adapter
5579 * @sleep_ok: if true we may sleep while awaiting command completion
5581 * Reads the PF RSS Mask register and returns its value.
5583 u32
t4_read_rss_pf_mask(struct adapter
*adapter
, bool sleep_ok
)
5587 t4_tp_pio_read(adapter
, &pfmask
, 1, TP_RSS_PF_MSK_A
, sleep_ok
);
5592 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
5593 * @adap: the adapter
5594 * @v4: holds the TCP/IP counter values
5595 * @v6: holds the TCP/IPv6 counter values
5596 * @sleep_ok: if true we may sleep while awaiting command completion
5598 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5599 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5601 void t4_tp_get_tcp_stats(struct adapter
*adap
, struct tp_tcp_stats
*v4
,
5602 struct tp_tcp_stats
*v6
, bool sleep_ok
)
5604 u32 val
[TP_MIB_TCP_RXT_SEG_LO_A
- TP_MIB_TCP_OUT_RST_A
+ 1];
5606 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
5607 #define STAT(x) val[STAT_IDX(x)]
5608 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5611 t4_tp_mib_read(adap
, val
, ARRAY_SIZE(val
),
5612 TP_MIB_TCP_OUT_RST_A
, sleep_ok
);
5613 v4
->tcp_out_rsts
= STAT(OUT_RST
);
5614 v4
->tcp_in_segs
= STAT64(IN_SEG
);
5615 v4
->tcp_out_segs
= STAT64(OUT_SEG
);
5616 v4
->tcp_retrans_segs
= STAT64(RXT_SEG
);
5619 t4_tp_mib_read(adap
, val
, ARRAY_SIZE(val
),
5620 TP_MIB_TCP_V6OUT_RST_A
, sleep_ok
);
5621 v6
->tcp_out_rsts
= STAT(OUT_RST
);
5622 v6
->tcp_in_segs
= STAT64(IN_SEG
);
5623 v6
->tcp_out_segs
= STAT64(OUT_SEG
);
5624 v6
->tcp_retrans_segs
= STAT64(RXT_SEG
);
5632 * t4_tp_get_err_stats - read TP's error MIB counters
5633 * @adap: the adapter
5634 * @st: holds the counter values
5635 * @sleep_ok: if true we may sleep while awaiting command completion
5637 * Returns the values of TP's error counters.
5639 void t4_tp_get_err_stats(struct adapter
*adap
, struct tp_err_stats
*st
,
5642 int nchan
= adap
->params
.arch
.nchan
;
5644 t4_tp_mib_read(adap
, st
->mac_in_errs
, nchan
, TP_MIB_MAC_IN_ERR_0_A
,
5646 t4_tp_mib_read(adap
, st
->hdr_in_errs
, nchan
, TP_MIB_HDR_IN_ERR_0_A
,
5648 t4_tp_mib_read(adap
, st
->tcp_in_errs
, nchan
, TP_MIB_TCP_IN_ERR_0_A
,
5650 t4_tp_mib_read(adap
, st
->tnl_cong_drops
, nchan
,
5651 TP_MIB_TNL_CNG_DROP_0_A
, sleep_ok
);
5652 t4_tp_mib_read(adap
, st
->ofld_chan_drops
, nchan
,
5653 TP_MIB_OFD_CHN_DROP_0_A
, sleep_ok
);
5654 t4_tp_mib_read(adap
, st
->tnl_tx_drops
, nchan
, TP_MIB_TNL_DROP_0_A
,
5656 t4_tp_mib_read(adap
, st
->ofld_vlan_drops
, nchan
,
5657 TP_MIB_OFD_VLN_DROP_0_A
, sleep_ok
);
5658 t4_tp_mib_read(adap
, st
->tcp6_in_errs
, nchan
,
5659 TP_MIB_TCP_V6IN_ERR_0_A
, sleep_ok
);
5660 t4_tp_mib_read(adap
, &st
->ofld_no_neigh
, 2, TP_MIB_OFD_ARP_DROP_A
,
5665 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
5666 * @adap: the adapter
5667 * @st: holds the counter values
5668 * @sleep_ok: if true we may sleep while awaiting command completion
5670 * Returns the values of TP's CPL counters.
5672 void t4_tp_get_cpl_stats(struct adapter
*adap
, struct tp_cpl_stats
*st
,
5675 int nchan
= adap
->params
.arch
.nchan
;
5677 t4_tp_mib_read(adap
, st
->req
, nchan
, TP_MIB_CPL_IN_REQ_0_A
, sleep_ok
);
5679 t4_tp_mib_read(adap
, st
->rsp
, nchan
, TP_MIB_CPL_OUT_RSP_0_A
, sleep_ok
);
5683 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5684 * @adap: the adapter
5685 * @st: holds the counter values
5686 * @sleep_ok: if true we may sleep while awaiting command completion
5688 * Returns the values of TP's RDMA counters.
5690 void t4_tp_get_rdma_stats(struct adapter
*adap
, struct tp_rdma_stats
*st
,
5693 t4_tp_mib_read(adap
, &st
->rqe_dfr_pkt
, 2, TP_MIB_RQE_DFR_PKT_A
,
5698 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5699 * @adap: the adapter
5700 * @idx: the port index
5701 * @st: holds the counter values
5702 * @sleep_ok: if true we may sleep while awaiting command completion
5704 * Returns the values of TP's FCoE counters for the selected port.
5706 void t4_get_fcoe_stats(struct adapter
*adap
, unsigned int idx
,
5707 struct tp_fcoe_stats
*st
, bool sleep_ok
)
5711 t4_tp_mib_read(adap
, &st
->frames_ddp
, 1, TP_MIB_FCOE_DDP_0_A
+ idx
,
5714 t4_tp_mib_read(adap
, &st
->frames_drop
, 1,
5715 TP_MIB_FCOE_DROP_0_A
+ idx
, sleep_ok
);
5717 t4_tp_mib_read(adap
, val
, 2, TP_MIB_FCOE_BYTE_0_HI_A
+ 2 * idx
,
5720 st
->octets_ddp
= ((u64
)val
[0] << 32) | val
[1];
5724 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5725 * @adap: the adapter
5726 * @st: holds the counter values
5727 * @sleep_ok: if true we may sleep while awaiting command completion
5729 * Returns the values of TP's counters for non-TCP directly-placed packets.
5731 void t4_get_usm_stats(struct adapter
*adap
, struct tp_usm_stats
*st
,
5736 t4_tp_mib_read(adap
, val
, 4, TP_MIB_USM_PKTS_A
, sleep_ok
);
5737 st
->frames
= val
[0];
5739 st
->octets
= ((u64
)val
[2] << 32) | val
[3];
5743 * t4_read_mtu_tbl - returns the values in the HW path MTU table
5744 * @adap: the adapter
5745 * @mtus: where to store the MTU values
5746 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
5748 * Reads the HW path MTU table.
5750 void t4_read_mtu_tbl(struct adapter
*adap
, u16
*mtus
, u8
*mtu_log
)
5755 for (i
= 0; i
< NMTUS
; ++i
) {
5756 t4_write_reg(adap
, TP_MTU_TABLE_A
,
5757 MTUINDEX_V(0xff) | MTUVALUE_V(i
));
5758 v
= t4_read_reg(adap
, TP_MTU_TABLE_A
);
5759 mtus
[i
] = MTUVALUE_G(v
);
5761 mtu_log
[i
] = MTUWIDTH_G(v
);
5766 * t4_read_cong_tbl - reads the congestion control table
5767 * @adap: the adapter
5768 * @incr: where to store the alpha values
5770 * Reads the additive increments programmed into the HW congestion
5773 void t4_read_cong_tbl(struct adapter
*adap
, u16 incr
[NMTUS
][NCCTRL_WIN
])
5775 unsigned int mtu
, w
;
5777 for (mtu
= 0; mtu
< NMTUS
; ++mtu
)
5778 for (w
= 0; w
< NCCTRL_WIN
; ++w
) {
5779 t4_write_reg(adap
, TP_CCTRL_TABLE_A
,
5780 ROWINDEX_V(0xffff) | (mtu
<< 5) | w
);
5781 incr
[mtu
][w
] = (u16
)t4_read_reg(adap
,
5782 TP_CCTRL_TABLE_A
) & 0x1fff;
5787 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5788 * @adap: the adapter
5789 * @addr: the indirect TP register address
5790 * @mask: specifies the field within the register to modify
5791 * @val: new value for the field
5793 * Sets a field of an indirect TP register to the given value.
5795 void t4_tp_wr_bits_indirect(struct adapter
*adap
, unsigned int addr
,
5796 unsigned int mask
, unsigned int val
)
5798 t4_write_reg(adap
, TP_PIO_ADDR_A
, addr
);
5799 val
|= t4_read_reg(adap
, TP_PIO_DATA_A
) & ~mask
;
5800 t4_write_reg(adap
, TP_PIO_DATA_A
, val
);
5804 * init_cong_ctrl - initialize congestion control parameters
5805 * @a: the alpha values for congestion control
5806 * @b: the beta values for congestion control
5808 * Initialize the congestion control parameters.
5810 static void init_cong_ctrl(unsigned short *a
, unsigned short *b
)
5812 a
[0] = a
[1] = a
[2] = a
[3] = a
[4] = a
[5] = a
[6] = a
[7] = a
[8] = 1;
5837 b
[0] = b
[1] = b
[2] = b
[3] = b
[4] = b
[5] = b
[6] = b
[7] = b
[8] = 0;
5840 b
[13] = b
[14] = b
[15] = b
[16] = 3;
5841 b
[17] = b
[18] = b
[19] = b
[20] = b
[21] = 4;
5842 b
[22] = b
[23] = b
[24] = b
[25] = b
[26] = b
[27] = 5;
5847 /* The minimum additive increment value for the congestion control table */
5848 #define CC_MIN_INCR 2U
5851 * t4_load_mtus - write the MTU and congestion control HW tables
5852 * @adap: the adapter
5853 * @mtus: the values for the MTU table
5854 * @alpha: the values for the congestion control alpha parameter
5855 * @beta: the values for the congestion control beta parameter
5857 * Write the HW MTU table with the supplied MTUs and the high-speed
5858 * congestion control table with the supplied alpha, beta, and MTUs.
5859 * We write the two tables together because the additive increments
5860 * depend on the MTUs.
5862 void t4_load_mtus(struct adapter
*adap
, const unsigned short *mtus
,
5863 const unsigned short *alpha
, const unsigned short *beta
)
5865 static const unsigned int avg_pkts
[NCCTRL_WIN
] = {
5866 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5867 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5868 28672, 40960, 57344, 81920, 114688, 163840, 229376
5873 for (i
= 0; i
< NMTUS
; ++i
) {
5874 unsigned int mtu
= mtus
[i
];
5875 unsigned int log2
= fls(mtu
);
5877 if (!(mtu
& ((1 << log2
) >> 2))) /* round */
5879 t4_write_reg(adap
, TP_MTU_TABLE_A
, MTUINDEX_V(i
) |
5880 MTUWIDTH_V(log2
) | MTUVALUE_V(mtu
));
5882 for (w
= 0; w
< NCCTRL_WIN
; ++w
) {
5885 inc
= max(((mtu
- 40) * alpha
[w
]) / avg_pkts
[w
],
5888 t4_write_reg(adap
, TP_CCTRL_TABLE_A
, (i
<< 21) |
5889 (w
<< 16) | (beta
[w
] << 13) | inc
);
5894 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5895 * clocks. The formula is
5897 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5899 * which is equivalent to
5901 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5903 static u64
chan_rate(struct adapter
*adap
, unsigned int bytes256
)
5905 u64 v
= bytes256
* adap
->params
.vpd
.cclk
;
5907 return v
* 62 + v
/ 2;
5911 * t4_get_chan_txrate - get the current per channel Tx rates
5912 * @adap: the adapter
5913 * @nic_rate: rates for NIC traffic
5914 * @ofld_rate: rates for offloaded traffic
5916 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5919 void t4_get_chan_txrate(struct adapter
*adap
, u64
*nic_rate
, u64
*ofld_rate
)
5923 v
= t4_read_reg(adap
, TP_TX_TRATE_A
);
5924 nic_rate
[0] = chan_rate(adap
, TNLRATE0_G(v
));
5925 nic_rate
[1] = chan_rate(adap
, TNLRATE1_G(v
));
5926 if (adap
->params
.arch
.nchan
== NCHAN
) {
5927 nic_rate
[2] = chan_rate(adap
, TNLRATE2_G(v
));
5928 nic_rate
[3] = chan_rate(adap
, TNLRATE3_G(v
));
5931 v
= t4_read_reg(adap
, TP_TX_ORATE_A
);
5932 ofld_rate
[0] = chan_rate(adap
, OFDRATE0_G(v
));
5933 ofld_rate
[1] = chan_rate(adap
, OFDRATE1_G(v
));
5934 if (adap
->params
.arch
.nchan
== NCHAN
) {
5935 ofld_rate
[2] = chan_rate(adap
, OFDRATE2_G(v
));
5936 ofld_rate
[3] = chan_rate(adap
, OFDRATE3_G(v
));
5941 * t4_set_trace_filter - configure one of the tracing filters
5942 * @adap: the adapter
5943 * @tp: the desired trace filter parameters
5944 * @idx: which filter to configure
5945 * @enable: whether to enable or disable the filter
5947 * Configures one of the tracing filters available in HW. If @enable is
5948 * %0 @tp is not examined and may be %NULL. The user is responsible to
5949 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5951 int t4_set_trace_filter(struct adapter
*adap
, const struct trace_params
*tp
,
5952 int idx
, int enable
)
5954 int i
, ofst
= idx
* 4;
5955 u32 data_reg
, mask_reg
, cfg
;
5958 t4_write_reg(adap
, MPS_TRC_FILTER_MATCH_CTL_A_A
+ ofst
, 0);
5962 cfg
= t4_read_reg(adap
, MPS_TRC_CFG_A
);
5963 if (cfg
& TRCMULTIFILTER_F
) {
5964 /* If multiple tracers are enabled, then maximum
5965 * capture size is 2.5KB (FIFO size of a single channel)
5966 * minus 2 flits for CPL_TRACE_PKT header.
5968 if (tp
->snap_len
> ((10 * 1024 / 4) - (2 * 8)))
5971 /* If multiple tracers are disabled, to avoid deadlocks
5972 * maximum packet capture size of 9600 bytes is recommended.
5973 * Also in this mode, only trace0 can be enabled and running.
5975 if (tp
->snap_len
> 9600 || idx
)
5979 if (tp
->port
> (is_t4(adap
->params
.chip
) ? 11 : 19) || tp
->invert
> 1 ||
5980 tp
->skip_len
> TFLENGTH_M
|| tp
->skip_ofst
> TFOFFSET_M
||
5981 tp
->min_len
> TFMINPKTSIZE_M
)
5984 /* stop the tracer we'll be changing */
5985 t4_write_reg(adap
, MPS_TRC_FILTER_MATCH_CTL_A_A
+ ofst
, 0);
5987 idx
*= (MPS_TRC_FILTER1_MATCH_A
- MPS_TRC_FILTER0_MATCH_A
);
5988 data_reg
= MPS_TRC_FILTER0_MATCH_A
+ idx
;
5989 mask_reg
= MPS_TRC_FILTER0_DONT_CARE_A
+ idx
;
5991 for (i
= 0; i
< TRACE_LEN
/ 4; i
++, data_reg
+= 4, mask_reg
+= 4) {
5992 t4_write_reg(adap
, data_reg
, tp
->data
[i
]);
5993 t4_write_reg(adap
, mask_reg
, ~tp
->mask
[i
]);
5995 t4_write_reg(adap
, MPS_TRC_FILTER_MATCH_CTL_B_A
+ ofst
,
5996 TFCAPTUREMAX_V(tp
->snap_len
) |
5997 TFMINPKTSIZE_V(tp
->min_len
));
5998 t4_write_reg(adap
, MPS_TRC_FILTER_MATCH_CTL_A_A
+ ofst
,
5999 TFOFFSET_V(tp
->skip_ofst
) | TFLENGTH_V(tp
->skip_len
) |
6000 (is_t4(adap
->params
.chip
) ?
6001 TFPORT_V(tp
->port
) | TFEN_F
| TFINVERTMATCH_V(tp
->invert
) :
6002 T5_TFPORT_V(tp
->port
) | T5_TFEN_F
|
6003 T5_TFINVERTMATCH_V(tp
->invert
)));
6009 * t4_get_trace_filter - query one of the tracing filters
6010 * @adap: the adapter
6011 * @tp: the current trace filter parameters
6012 * @idx: which trace filter to query
6013 * @enabled: non-zero if the filter is enabled
6015 * Returns the current settings of one of the HW tracing filters.
6017 void t4_get_trace_filter(struct adapter
*adap
, struct trace_params
*tp
, int idx
,
6021 int i
, ofst
= idx
* 4;
6022 u32 data_reg
, mask_reg
;
6024 ctla
= t4_read_reg(adap
, MPS_TRC_FILTER_MATCH_CTL_A_A
+ ofst
);
6025 ctlb
= t4_read_reg(adap
, MPS_TRC_FILTER_MATCH_CTL_B_A
+ ofst
);
6027 if (is_t4(adap
->params
.chip
)) {
6028 *enabled
= !!(ctla
& TFEN_F
);
6029 tp
->port
= TFPORT_G(ctla
);
6030 tp
->invert
= !!(ctla
& TFINVERTMATCH_F
);
6032 *enabled
= !!(ctla
& T5_TFEN_F
);
6033 tp
->port
= T5_TFPORT_G(ctla
);
6034 tp
->invert
= !!(ctla
& T5_TFINVERTMATCH_F
);
6036 tp
->snap_len
= TFCAPTUREMAX_G(ctlb
);
6037 tp
->min_len
= TFMINPKTSIZE_G(ctlb
);
6038 tp
->skip_ofst
= TFOFFSET_G(ctla
);
6039 tp
->skip_len
= TFLENGTH_G(ctla
);
6041 ofst
= (MPS_TRC_FILTER1_MATCH_A
- MPS_TRC_FILTER0_MATCH_A
) * idx
;
6042 data_reg
= MPS_TRC_FILTER0_MATCH_A
+ ofst
;
6043 mask_reg
= MPS_TRC_FILTER0_DONT_CARE_A
+ ofst
;
6045 for (i
= 0; i
< TRACE_LEN
/ 4; i
++, data_reg
+= 4, mask_reg
+= 4) {
6046 tp
->mask
[i
] = ~t4_read_reg(adap
, mask_reg
);
6047 tp
->data
[i
] = t4_read_reg(adap
, data_reg
) & tp
->mask
[i
];
6052 * t4_pmtx_get_stats - returns the HW stats from PMTX
6053 * @adap: the adapter
6054 * @cnt: where to store the count statistics
6055 * @cycles: where to store the cycle statistics
6057 * Returns performance statistics from PMTX.
6059 void t4_pmtx_get_stats(struct adapter
*adap
, u32 cnt
[], u64 cycles
[])
6064 for (i
= 0; i
< adap
->params
.arch
.pm_stats_cnt
; i
++) {
6065 t4_write_reg(adap
, PM_TX_STAT_CONFIG_A
, i
+ 1);
6066 cnt
[i
] = t4_read_reg(adap
, PM_TX_STAT_COUNT_A
);
6067 if (is_t4(adap
->params
.chip
)) {
6068 cycles
[i
] = t4_read_reg64(adap
, PM_TX_STAT_LSB_A
);
6070 t4_read_indirect(adap
, PM_TX_DBG_CTRL_A
,
6071 PM_TX_DBG_DATA_A
, data
, 2,
6072 PM_TX_DBG_STAT_MSB_A
);
6073 cycles
[i
] = (((u64
)data
[0] << 32) | data
[1]);
6079 * t4_pmrx_get_stats - returns the HW stats from PMRX
6080 * @adap: the adapter
6081 * @cnt: where to store the count statistics
6082 * @cycles: where to store the cycle statistics
6084 * Returns performance statistics from PMRX.
6086 void t4_pmrx_get_stats(struct adapter
*adap
, u32 cnt
[], u64 cycles
[])
6091 for (i
= 0; i
< adap
->params
.arch
.pm_stats_cnt
; i
++) {
6092 t4_write_reg(adap
, PM_RX_STAT_CONFIG_A
, i
+ 1);
6093 cnt
[i
] = t4_read_reg(adap
, PM_RX_STAT_COUNT_A
);
6094 if (is_t4(adap
->params
.chip
)) {
6095 cycles
[i
] = t4_read_reg64(adap
, PM_RX_STAT_LSB_A
);
6097 t4_read_indirect(adap
, PM_RX_DBG_CTRL_A
,
6098 PM_RX_DBG_DATA_A
, data
, 2,
6099 PM_RX_DBG_STAT_MSB_A
);
6100 cycles
[i
] = (((u64
)data
[0] << 32) | data
[1]);
6106 * compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
6107 * @adap: the adapter
6108 * @pidx: the port index
6110 * Computes and returns a bitmap indicating which MPS buffer groups are
6111 * associated with the given Port. Bit i is set if buffer group i is
6114 static inline unsigned int compute_mps_bg_map(struct adapter
*adapter
,
6117 unsigned int chip_version
, nports
;
6119 chip_version
= CHELSIO_CHIP_VERSION(adapter
->params
.chip
);
6120 nports
= 1 << NUMPORTS_G(t4_read_reg(adapter
, MPS_CMN_CTL_A
));
6122 switch (chip_version
) {
6127 case 2: return 3 << (2 * pidx
);
6128 case 4: return 1 << pidx
;
6134 case 2: return 1 << (2 * pidx
);
6139 dev_err(adapter
->pdev_dev
, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
6140 chip_version
, nports
);
6146 * t4_get_mps_bg_map - return the buffer groups associated with a port
6147 * @adapter: the adapter
6148 * @pidx: the port index
6150 * Returns a bitmap indicating which MPS buffer groups are associated
6151 * with the given Port. Bit i is set if buffer group i is used by the
6154 unsigned int t4_get_mps_bg_map(struct adapter
*adapter
, int pidx
)
6157 unsigned int nports
;
6159 nports
= 1 << NUMPORTS_G(t4_read_reg(adapter
, MPS_CMN_CTL_A
));
6160 if (pidx
>= nports
) {
6161 CH_WARN(adapter
, "MPS Port Index %d >= Nports %d\n",
6166 /* If we've already retrieved/computed this, just return the result.
6168 mps_bg_map
= adapter
->params
.mps_bg_map
;
6169 if (mps_bg_map
[pidx
])
6170 return mps_bg_map
[pidx
];
6172 /* Newer Firmware can tell us what the MPS Buffer Group Map is.
6173 * If we're talking to such Firmware, let it tell us. If the new
6174 * API isn't supported, revert back to old hardcoded way. The value
6175 * obtained from Firmware is encoded in below format:
6177 * val = (( MPSBGMAP[Port 3] << 24 ) |
6178 * ( MPSBGMAP[Port 2] << 16 ) |
6179 * ( MPSBGMAP[Port 1] << 8 ) |
6180 * ( MPSBGMAP[Port 0] << 0 ))
6182 if (adapter
->flags
& CXGB4_FW_OK
) {
6186 param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
6187 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_MPSBGMAP
));
6188 ret
= t4_query_params_ns(adapter
, adapter
->mbox
, adapter
->pf
,
6189 0, 1, ¶m
, &val
);
6193 /* Store the BG Map for all of the Ports in order to
6194 * avoid more calls to the Firmware in the future.
6196 for (p
= 0; p
< MAX_NPORTS
; p
++, val
>>= 8)
6197 mps_bg_map
[p
] = val
& 0xff;
6199 return mps_bg_map
[pidx
];
6203 /* Either we're not talking to the Firmware or we're dealing with
6204 * older Firmware which doesn't support the new API to get the MPS
6205 * Buffer Group Map. Fall back to computing it ourselves.
6207 mps_bg_map
[pidx
] = compute_mps_bg_map(adapter
, pidx
);
6208 return mps_bg_map
[pidx
];
6212 * t4_get_tp_e2c_map - return the E2C channel map associated with a port
6213 * @adapter: the adapter
6214 * @pidx: the port index
6216 static unsigned int t4_get_tp_e2c_map(struct adapter
*adapter
, int pidx
)
6218 unsigned int nports
;
6222 nports
= 1 << NUMPORTS_G(t4_read_reg(adapter
, MPS_CMN_CTL_A
));
6223 if (pidx
>= nports
) {
6224 CH_WARN(adapter
, "TP E2C Channel Port Index %d >= Nports %d\n",
6229 /* FW version >= 1.16.44.0 can determine E2C channel map using
6230 * FW_PARAMS_PARAM_DEV_TPCHMAP API.
6232 param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
6233 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_TPCHMAP
));
6234 ret
= t4_query_params_ns(adapter
, adapter
->mbox
, adapter
->pf
,
6235 0, 1, ¶m
, &val
);
6237 return (val
>> (8 * pidx
)) & 0xff;
6243 * t4_get_tp_ch_map - return TP ingress channels associated with a port
6244 * @adapter: the adapter
6245 * @pidx: the port index
6247 * Returns a bitmap indicating which TP Ingress Channels are associated
6248 * with a given Port. Bit i is set if TP Ingress Channel i is used by
6251 unsigned int t4_get_tp_ch_map(struct adapter
*adap
, int pidx
)
6253 unsigned int chip_version
= CHELSIO_CHIP_VERSION(adap
->params
.chip
);
6254 unsigned int nports
= 1 << NUMPORTS_G(t4_read_reg(adap
, MPS_CMN_CTL_A
));
6256 if (pidx
>= nports
) {
6257 dev_warn(adap
->pdev_dev
, "TP Port Index %d >= Nports %d\n",
6262 switch (chip_version
) {
6265 /* Note that this happens to be the same values as the MPS
6266 * Buffer Group Map for these Chips. But we replicate the code
6267 * here because they're really separate concepts.
6271 case 2: return 3 << (2 * pidx
);
6272 case 4: return 1 << pidx
;
6279 case 2: return 1 << pidx
;
6284 dev_err(adap
->pdev_dev
, "Need TP Channel Map for Chip %0x, Nports %d\n",
6285 chip_version
, nports
);
6290 * t4_get_port_type_description - return Port Type string description
6291 * @port_type: firmware Port Type enumeration
6293 const char *t4_get_port_type_description(enum fw_port_type port_type
)
6295 static const char *const port_type_description
[] = {
6321 if (port_type
< ARRAY_SIZE(port_type_description
))
6322 return port_type_description
[port_type
];
6327 * t4_get_port_stats_offset - collect port stats relative to a previous
6329 * @adap: The adapter
6331 * @stats: Current stats to fill
6332 * @offset: Previous stats snapshot
6334 void t4_get_port_stats_offset(struct adapter
*adap
, int idx
,
6335 struct port_stats
*stats
,
6336 struct port_stats
*offset
)
6341 t4_get_port_stats(adap
, idx
, stats
);
6342 for (i
= 0, s
= (u64
*)stats
, o
= (u64
*)offset
;
6343 i
< (sizeof(struct port_stats
) / sizeof(u64
));
6349 * t4_get_port_stats - collect port statistics
6350 * @adap: the adapter
6351 * @idx: the port index
6352 * @p: the stats structure to fill
6354 * Collect statistics related to the given port from HW.
6356 void t4_get_port_stats(struct adapter
*adap
, int idx
, struct port_stats
*p
)
6358 u32 bgmap
= t4_get_mps_bg_map(adap
, idx
);
6359 u32 stat_ctl
= t4_read_reg(adap
, MPS_STAT_CTL_A
);
6361 #define GET_STAT(name) \
6362 t4_read_reg64(adap, \
6363 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
6364 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
6365 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6367 p
->tx_octets
= GET_STAT(TX_PORT_BYTES
);
6368 p
->tx_frames
= GET_STAT(TX_PORT_FRAMES
);
6369 p
->tx_bcast_frames
= GET_STAT(TX_PORT_BCAST
);
6370 p
->tx_mcast_frames
= GET_STAT(TX_PORT_MCAST
);
6371 p
->tx_ucast_frames
= GET_STAT(TX_PORT_UCAST
);
6372 p
->tx_error_frames
= GET_STAT(TX_PORT_ERROR
);
6373 p
->tx_frames_64
= GET_STAT(TX_PORT_64B
);
6374 p
->tx_frames_65_127
= GET_STAT(TX_PORT_65B_127B
);
6375 p
->tx_frames_128_255
= GET_STAT(TX_PORT_128B_255B
);
6376 p
->tx_frames_256_511
= GET_STAT(TX_PORT_256B_511B
);
6377 p
->tx_frames_512_1023
= GET_STAT(TX_PORT_512B_1023B
);
6378 p
->tx_frames_1024_1518
= GET_STAT(TX_PORT_1024B_1518B
);
6379 p
->tx_frames_1519_max
= GET_STAT(TX_PORT_1519B_MAX
);
6380 p
->tx_drop
= GET_STAT(TX_PORT_DROP
);
6381 p
->tx_pause
= GET_STAT(TX_PORT_PAUSE
);
6382 p
->tx_ppp0
= GET_STAT(TX_PORT_PPP0
);
6383 p
->tx_ppp1
= GET_STAT(TX_PORT_PPP1
);
6384 p
->tx_ppp2
= GET_STAT(TX_PORT_PPP2
);
6385 p
->tx_ppp3
= GET_STAT(TX_PORT_PPP3
);
6386 p
->tx_ppp4
= GET_STAT(TX_PORT_PPP4
);
6387 p
->tx_ppp5
= GET_STAT(TX_PORT_PPP5
);
6388 p
->tx_ppp6
= GET_STAT(TX_PORT_PPP6
);
6389 p
->tx_ppp7
= GET_STAT(TX_PORT_PPP7
);
6391 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) >= CHELSIO_T5
) {
6392 if (stat_ctl
& COUNTPAUSESTATTX_F
)
6393 p
->tx_frames_64
-= p
->tx_pause
;
6394 if (stat_ctl
& COUNTPAUSEMCTX_F
)
6395 p
->tx_mcast_frames
-= p
->tx_pause
;
6397 p
->rx_octets
= GET_STAT(RX_PORT_BYTES
);
6398 p
->rx_frames
= GET_STAT(RX_PORT_FRAMES
);
6399 p
->rx_bcast_frames
= GET_STAT(RX_PORT_BCAST
);
6400 p
->rx_mcast_frames
= GET_STAT(RX_PORT_MCAST
);
6401 p
->rx_ucast_frames
= GET_STAT(RX_PORT_UCAST
);
6402 p
->rx_too_long
= GET_STAT(RX_PORT_MTU_ERROR
);
6403 p
->rx_jabber
= GET_STAT(RX_PORT_MTU_CRC_ERROR
);
6404 p
->rx_fcs_err
= GET_STAT(RX_PORT_CRC_ERROR
);
6405 p
->rx_len_err
= GET_STAT(RX_PORT_LEN_ERROR
);
6406 p
->rx_symbol_err
= GET_STAT(RX_PORT_SYM_ERROR
);
6407 p
->rx_runt
= GET_STAT(RX_PORT_LESS_64B
);
6408 p
->rx_frames_64
= GET_STAT(RX_PORT_64B
);
6409 p
->rx_frames_65_127
= GET_STAT(RX_PORT_65B_127B
);
6410 p
->rx_frames_128_255
= GET_STAT(RX_PORT_128B_255B
);
6411 p
->rx_frames_256_511
= GET_STAT(RX_PORT_256B_511B
);
6412 p
->rx_frames_512_1023
= GET_STAT(RX_PORT_512B_1023B
);
6413 p
->rx_frames_1024_1518
= GET_STAT(RX_PORT_1024B_1518B
);
6414 p
->rx_frames_1519_max
= GET_STAT(RX_PORT_1519B_MAX
);
6415 p
->rx_pause
= GET_STAT(RX_PORT_PAUSE
);
6416 p
->rx_ppp0
= GET_STAT(RX_PORT_PPP0
);
6417 p
->rx_ppp1
= GET_STAT(RX_PORT_PPP1
);
6418 p
->rx_ppp2
= GET_STAT(RX_PORT_PPP2
);
6419 p
->rx_ppp3
= GET_STAT(RX_PORT_PPP3
);
6420 p
->rx_ppp4
= GET_STAT(RX_PORT_PPP4
);
6421 p
->rx_ppp5
= GET_STAT(RX_PORT_PPP5
);
6422 p
->rx_ppp6
= GET_STAT(RX_PORT_PPP6
);
6423 p
->rx_ppp7
= GET_STAT(RX_PORT_PPP7
);
6425 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) >= CHELSIO_T5
) {
6426 if (stat_ctl
& COUNTPAUSESTATRX_F
)
6427 p
->rx_frames_64
-= p
->rx_pause
;
6428 if (stat_ctl
& COUNTPAUSEMCRX_F
)
6429 p
->rx_mcast_frames
-= p
->rx_pause
;
6432 p
->rx_ovflow0
= (bgmap
& 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME
) : 0;
6433 p
->rx_ovflow1
= (bgmap
& 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME
) : 0;
6434 p
->rx_ovflow2
= (bgmap
& 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME
) : 0;
6435 p
->rx_ovflow3
= (bgmap
& 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME
) : 0;
6436 p
->rx_trunc0
= (bgmap
& 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME
) : 0;
6437 p
->rx_trunc1
= (bgmap
& 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME
) : 0;
6438 p
->rx_trunc2
= (bgmap
& 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME
) : 0;
6439 p
->rx_trunc3
= (bgmap
& 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME
) : 0;
6446 * t4_get_lb_stats - collect loopback port statistics
6447 * @adap: the adapter
6448 * @idx: the loopback port index
6449 * @p: the stats structure to fill
6451 * Return HW statistics for the given loopback port.
6453 void t4_get_lb_stats(struct adapter
*adap
, int idx
, struct lb_port_stats
*p
)
6455 u32 bgmap
= t4_get_mps_bg_map(adap
, idx
);
6457 #define GET_STAT(name) \
6458 t4_read_reg64(adap, \
6459 (is_t4(adap->params.chip) ? \
6460 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
6461 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
6462 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6464 p
->octets
= GET_STAT(BYTES
);
6465 p
->frames
= GET_STAT(FRAMES
);
6466 p
->bcast_frames
= GET_STAT(BCAST
);
6467 p
->mcast_frames
= GET_STAT(MCAST
);
6468 p
->ucast_frames
= GET_STAT(UCAST
);
6469 p
->error_frames
= GET_STAT(ERROR
);
6471 p
->frames_64
= GET_STAT(64B
);
6472 p
->frames_65_127
= GET_STAT(65B_127B
);
6473 p
->frames_128_255
= GET_STAT(128B_255B
);
6474 p
->frames_256_511
= GET_STAT(256B_511B
);
6475 p
->frames_512_1023
= GET_STAT(512B_1023B
);
6476 p
->frames_1024_1518
= GET_STAT(1024B_1518B
);
6477 p
->frames_1519_max
= GET_STAT(1519B_MAX
);
6478 p
->drop
= GET_STAT(DROP_FRAMES
);
6480 p
->ovflow0
= (bgmap
& 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME
) : 0;
6481 p
->ovflow1
= (bgmap
& 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME
) : 0;
6482 p
->ovflow2
= (bgmap
& 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME
) : 0;
6483 p
->ovflow3
= (bgmap
& 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME
) : 0;
6484 p
->trunc0
= (bgmap
& 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME
) : 0;
6485 p
->trunc1
= (bgmap
& 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME
) : 0;
6486 p
->trunc2
= (bgmap
& 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME
) : 0;
6487 p
->trunc3
= (bgmap
& 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME
) : 0;
6493 /* t4_mk_filtdelwr - create a delete filter WR
6494 * @ftid: the filter ID
6495 * @wr: the filter work request to populate
6496 * @qid: ingress queue to receive the delete notification
6498 * Creates a filter work request to delete the supplied filter. If @qid is
6499 * negative the delete notification is suppressed.
6501 void t4_mk_filtdelwr(unsigned int ftid
, struct fw_filter_wr
*wr
, int qid
)
6503 memset(wr
, 0, sizeof(*wr
));
6504 wr
->op_pkd
= cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR
));
6505 wr
->len16_pkd
= cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr
) / 16));
6506 wr
->tid_to_iq
= cpu_to_be32(FW_FILTER_WR_TID_V(ftid
) |
6507 FW_FILTER_WR_NOREPLY_V(qid
< 0));
6508 wr
->del_filter_to_l2tix
= cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F
);
6510 wr
->rx_chan_rx_rpl_iq
=
6511 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid
));
6514 #define INIT_CMD(var, cmd, rd_wr) do { \
6515 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
6516 FW_CMD_REQUEST_F | \
6517 FW_CMD_##rd_wr##_F); \
6518 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6521 int t4_fwaddrspace_write(struct adapter
*adap
, unsigned int mbox
,
6525 struct fw_ldst_cmd c
;
6527 memset(&c
, 0, sizeof(c
));
6528 ldst_addrspace
= FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE
);
6529 c
.op_to_addrspace
= cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
6533 c
.cycles_to_len16
= cpu_to_be32(FW_LEN16(c
));
6534 c
.u
.addrval
.addr
= cpu_to_be32(addr
);
6535 c
.u
.addrval
.val
= cpu_to_be32(val
);
6537 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
6541 * t4_mdio_rd - read a PHY register through MDIO
6542 * @adap: the adapter
6543 * @mbox: mailbox to use for the FW command
6544 * @phy_addr: the PHY address
6545 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6546 * @reg: the register to read
6547 * @valp: where to store the value
6549 * Issues a FW command through the given mailbox to read a PHY register.
6551 int t4_mdio_rd(struct adapter
*adap
, unsigned int mbox
, unsigned int phy_addr
,
6552 unsigned int mmd
, unsigned int reg
, u16
*valp
)
6556 struct fw_ldst_cmd c
;
6558 memset(&c
, 0, sizeof(c
));
6559 ldst_addrspace
= FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO
);
6560 c
.op_to_addrspace
= cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
6561 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
6563 c
.cycles_to_len16
= cpu_to_be32(FW_LEN16(c
));
6564 c
.u
.mdio
.paddr_mmd
= cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr
) |
6565 FW_LDST_CMD_MMD_V(mmd
));
6566 c
.u
.mdio
.raddr
= cpu_to_be16(reg
);
6568 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
6570 *valp
= be16_to_cpu(c
.u
.mdio
.rval
);
6575 * t4_mdio_wr - write a PHY register through MDIO
6576 * @adap: the adapter
6577 * @mbox: mailbox to use for the FW command
6578 * @phy_addr: the PHY address
6579 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6580 * @reg: the register to write
6581 * @valp: value to write
6583 * Issues a FW command through the given mailbox to write a PHY register.
6585 int t4_mdio_wr(struct adapter
*adap
, unsigned int mbox
, unsigned int phy_addr
,
6586 unsigned int mmd
, unsigned int reg
, u16 val
)
6589 struct fw_ldst_cmd c
;
6591 memset(&c
, 0, sizeof(c
));
6592 ldst_addrspace
= FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO
);
6593 c
.op_to_addrspace
= cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
6594 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
6596 c
.cycles_to_len16
= cpu_to_be32(FW_LEN16(c
));
6597 c
.u
.mdio
.paddr_mmd
= cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr
) |
6598 FW_LDST_CMD_MMD_V(mmd
));
6599 c
.u
.mdio
.raddr
= cpu_to_be16(reg
);
6600 c
.u
.mdio
.rval
= cpu_to_be16(val
);
6602 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
6606 * t4_sge_decode_idma_state - decode the idma state
6607 * @adap: the adapter
6608 * @state: the state idma is stuck in
6610 void t4_sge_decode_idma_state(struct adapter
*adapter
, int state
)
6612 static const char * const t4_decode
[] = {
6614 "IDMA_PUSH_MORE_CPL_FIFO",
6615 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6617 "IDMA_PHYSADDR_SEND_PCIEHDR",
6618 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6619 "IDMA_PHYSADDR_SEND_PAYLOAD",
6620 "IDMA_SEND_FIFO_TO_IMSG",
6621 "IDMA_FL_REQ_DATA_FL_PREP",
6622 "IDMA_FL_REQ_DATA_FL",
6624 "IDMA_FL_H_REQ_HEADER_FL",
6625 "IDMA_FL_H_SEND_PCIEHDR",
6626 "IDMA_FL_H_PUSH_CPL_FIFO",
6627 "IDMA_FL_H_SEND_CPL",
6628 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6629 "IDMA_FL_H_SEND_IP_HDR",
6630 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6631 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6632 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6633 "IDMA_FL_D_SEND_PCIEHDR",
6634 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6635 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6636 "IDMA_FL_SEND_PCIEHDR",
6637 "IDMA_FL_PUSH_CPL_FIFO",
6639 "IDMA_FL_SEND_PAYLOAD_FIRST",
6640 "IDMA_FL_SEND_PAYLOAD",
6641 "IDMA_FL_REQ_NEXT_DATA_FL",
6642 "IDMA_FL_SEND_NEXT_PCIEHDR",
6643 "IDMA_FL_SEND_PADDING",
6644 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6645 "IDMA_FL_SEND_FIFO_TO_IMSG",
6646 "IDMA_FL_REQ_DATAFL_DONE",
6647 "IDMA_FL_REQ_HEADERFL_DONE",
6649 static const char * const t5_decode
[] = {
6652 "IDMA_PUSH_MORE_CPL_FIFO",
6653 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6654 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6655 "IDMA_PHYSADDR_SEND_PCIEHDR",
6656 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6657 "IDMA_PHYSADDR_SEND_PAYLOAD",
6658 "IDMA_SEND_FIFO_TO_IMSG",
6659 "IDMA_FL_REQ_DATA_FL",
6661 "IDMA_FL_DROP_SEND_INC",
6662 "IDMA_FL_H_REQ_HEADER_FL",
6663 "IDMA_FL_H_SEND_PCIEHDR",
6664 "IDMA_FL_H_PUSH_CPL_FIFO",
6665 "IDMA_FL_H_SEND_CPL",
6666 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6667 "IDMA_FL_H_SEND_IP_HDR",
6668 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6669 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6670 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6671 "IDMA_FL_D_SEND_PCIEHDR",
6672 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6673 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6674 "IDMA_FL_SEND_PCIEHDR",
6675 "IDMA_FL_PUSH_CPL_FIFO",
6677 "IDMA_FL_SEND_PAYLOAD_FIRST",
6678 "IDMA_FL_SEND_PAYLOAD",
6679 "IDMA_FL_REQ_NEXT_DATA_FL",
6680 "IDMA_FL_SEND_NEXT_PCIEHDR",
6681 "IDMA_FL_SEND_PADDING",
6682 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6684 static const char * const t6_decode
[] = {
6686 "IDMA_PUSH_MORE_CPL_FIFO",
6687 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6688 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6689 "IDMA_PHYSADDR_SEND_PCIEHDR",
6690 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6691 "IDMA_PHYSADDR_SEND_PAYLOAD",
6692 "IDMA_FL_REQ_DATA_FL",
6694 "IDMA_FL_DROP_SEND_INC",
6695 "IDMA_FL_H_REQ_HEADER_FL",
6696 "IDMA_FL_H_SEND_PCIEHDR",
6697 "IDMA_FL_H_PUSH_CPL_FIFO",
6698 "IDMA_FL_H_SEND_CPL",
6699 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6700 "IDMA_FL_H_SEND_IP_HDR",
6701 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6702 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6703 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6704 "IDMA_FL_D_SEND_PCIEHDR",
6705 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6706 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6707 "IDMA_FL_SEND_PCIEHDR",
6708 "IDMA_FL_PUSH_CPL_FIFO",
6710 "IDMA_FL_SEND_PAYLOAD_FIRST",
6711 "IDMA_FL_SEND_PAYLOAD",
6712 "IDMA_FL_REQ_NEXT_DATA_FL",
6713 "IDMA_FL_SEND_NEXT_PCIEHDR",
6714 "IDMA_FL_SEND_PADDING",
6715 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6717 static const u32 sge_regs
[] = {
6718 SGE_DEBUG_DATA_LOW_INDEX_2_A
,
6719 SGE_DEBUG_DATA_LOW_INDEX_3_A
,
6720 SGE_DEBUG_DATA_HIGH_INDEX_10_A
,
6722 const char **sge_idma_decode
;
6723 int sge_idma_decode_nstates
;
6725 unsigned int chip_version
= CHELSIO_CHIP_VERSION(adapter
->params
.chip
);
6727 /* Select the right set of decode strings to dump depending on the
6728 * adapter chip type.
6730 switch (chip_version
) {
6732 sge_idma_decode
= (const char **)t4_decode
;
6733 sge_idma_decode_nstates
= ARRAY_SIZE(t4_decode
);
6737 sge_idma_decode
= (const char **)t5_decode
;
6738 sge_idma_decode_nstates
= ARRAY_SIZE(t5_decode
);
6742 sge_idma_decode
= (const char **)t6_decode
;
6743 sge_idma_decode_nstates
= ARRAY_SIZE(t6_decode
);
6747 dev_err(adapter
->pdev_dev
,
6748 "Unsupported chip version %d\n", chip_version
);
6752 if (is_t4(adapter
->params
.chip
)) {
6753 sge_idma_decode
= (const char **)t4_decode
;
6754 sge_idma_decode_nstates
= ARRAY_SIZE(t4_decode
);
6756 sge_idma_decode
= (const char **)t5_decode
;
6757 sge_idma_decode_nstates
= ARRAY_SIZE(t5_decode
);
6760 if (state
< sge_idma_decode_nstates
)
6761 CH_WARN(adapter
, "idma state %s\n", sge_idma_decode
[state
]);
6763 CH_WARN(adapter
, "idma state %d unknown\n", state
);
6765 for (i
= 0; i
< ARRAY_SIZE(sge_regs
); i
++)
6766 CH_WARN(adapter
, "SGE register %#x value %#x\n",
6767 sge_regs
[i
], t4_read_reg(adapter
, sge_regs
[i
]));
6771 * t4_sge_ctxt_flush - flush the SGE context cache
6772 * @adap: the adapter
6773 * @mbox: mailbox to use for the FW command
6774 * @ctx_type: Egress or Ingress
6776 * Issues a FW command through the given mailbox to flush the
6777 * SGE context cache.
6779 int t4_sge_ctxt_flush(struct adapter
*adap
, unsigned int mbox
, int ctxt_type
)
6783 struct fw_ldst_cmd c
;
6785 memset(&c
, 0, sizeof(c
));
6786 ldst_addrspace
= FW_LDST_CMD_ADDRSPACE_V(ctxt_type
== CTXT_EGRESS
?
6787 FW_LDST_ADDRSPC_SGE_EGRC
:
6788 FW_LDST_ADDRSPC_SGE_INGC
);
6789 c
.op_to_addrspace
= cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
6790 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
6792 c
.cycles_to_len16
= cpu_to_be32(FW_LEN16(c
));
6793 c
.u
.idctxt
.msg_ctxtflush
= cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F
);
6795 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
6800 * t4_read_sge_dbqtimers - read SGE Doorbell Queue Timer values
6801 * @adap - the adapter
6802 * @ndbqtimers: size of the provided SGE Doorbell Queue Timer table
6803 * @dbqtimers: SGE Doorbell Queue Timer table
6805 * Reads the SGE Doorbell Queue Timer values into the provided table.
6806 * Returns 0 on success (Firmware and Hardware support this feature),
6807 * an error on failure.
6809 int t4_read_sge_dbqtimers(struct adapter
*adap
, unsigned int ndbqtimers
,
6812 int ret
, dbqtimerix
;
6816 while (dbqtimerix
< ndbqtimers
) {
6818 u32 params
[7], vals
[7];
6820 nparams
= ndbqtimers
- dbqtimerix
;
6821 if (nparams
> ARRAY_SIZE(params
))
6822 nparams
= ARRAY_SIZE(params
);
6824 for (param
= 0; param
< nparams
; param
++)
6826 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
6827 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DBQ_TIMER
) |
6828 FW_PARAMS_PARAM_Y_V(dbqtimerix
+ param
));
6829 ret
= t4_query_params(adap
, adap
->mbox
, adap
->pf
, 0,
6830 nparams
, params
, vals
);
6834 for (param
= 0; param
< nparams
; param
++)
6835 dbqtimers
[dbqtimerix
++] = vals
[param
];
6841 * t4_fw_hello - establish communication with FW
6842 * @adap: the adapter
6843 * @mbox: mailbox to use for the FW command
6844 * @evt_mbox: mailbox to receive async FW events
6845 * @master: specifies the caller's willingness to be the device master
6846 * @state: returns the current device state (if non-NULL)
6848 * Issues a command to establish communication with FW. Returns either
6849 * an error (negative integer) or the mailbox of the Master PF.
6851 int t4_fw_hello(struct adapter
*adap
, unsigned int mbox
, unsigned int evt_mbox
,
6852 enum dev_master master
, enum dev_state
*state
)
6855 struct fw_hello_cmd c
;
6857 unsigned int master_mbox
;
6858 int retries
= FW_CMD_HELLO_RETRIES
;
6861 memset(&c
, 0, sizeof(c
));
6862 INIT_CMD(c
, HELLO
, WRITE
);
6863 c
.err_to_clearinit
= cpu_to_be32(
6864 FW_HELLO_CMD_MASTERDIS_V(master
== MASTER_CANT
) |
6865 FW_HELLO_CMD_MASTERFORCE_V(master
== MASTER_MUST
) |
6866 FW_HELLO_CMD_MBMASTER_V(master
== MASTER_MUST
?
6867 mbox
: FW_HELLO_CMD_MBMASTER_M
) |
6868 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox
) |
6869 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os
) |
6870 FW_HELLO_CMD_CLEARINIT_F
);
6873 * Issue the HELLO command to the firmware. If it's not successful
6874 * but indicates that we got a "busy" or "timeout" condition, retry
6875 * the HELLO until we exhaust our retry limit. If we do exceed our
6876 * retry limit, check to see if the firmware left us any error
6877 * information and report that if so.
6879 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
6881 if ((ret
== -EBUSY
|| ret
== -ETIMEDOUT
) && retries
-- > 0)
6883 if (t4_read_reg(adap
, PCIE_FW_A
) & PCIE_FW_ERR_F
)
6884 t4_report_fw_error(adap
);
6888 v
= be32_to_cpu(c
.err_to_clearinit
);
6889 master_mbox
= FW_HELLO_CMD_MBMASTER_G(v
);
6891 if (v
& FW_HELLO_CMD_ERR_F
)
6892 *state
= DEV_STATE_ERR
;
6893 else if (v
& FW_HELLO_CMD_INIT_F
)
6894 *state
= DEV_STATE_INIT
;
6896 *state
= DEV_STATE_UNINIT
;
6900 * If we're not the Master PF then we need to wait around for the
6901 * Master PF Driver to finish setting up the adapter.
6903 * Note that we also do this wait if we're a non-Master-capable PF and
6904 * there is no current Master PF; a Master PF may show up momentarily
6905 * and we wouldn't want to fail pointlessly. (This can happen when an
6906 * OS loads lots of different drivers rapidly at the same time). In
6907 * this case, the Master PF returned by the firmware will be
6908 * PCIE_FW_MASTER_M so the test below will work ...
6910 if ((v
& (FW_HELLO_CMD_ERR_F
|FW_HELLO_CMD_INIT_F
)) == 0 &&
6911 master_mbox
!= mbox
) {
6912 int waiting
= FW_CMD_HELLO_TIMEOUT
;
6915 * Wait for the firmware to either indicate an error or
6916 * initialized state. If we see either of these we bail out
6917 * and report the issue to the caller. If we exhaust the
6918 * "hello timeout" and we haven't exhausted our retries, try
6919 * again. Otherwise bail with a timeout error.
6928 * If neither Error nor Initialized are indicated
6929 * by the firmware keep waiting till we exhaust our
6930 * timeout ... and then retry if we haven't exhausted
6933 pcie_fw
= t4_read_reg(adap
, PCIE_FW_A
);
6934 if (!(pcie_fw
& (PCIE_FW_ERR_F
|PCIE_FW_INIT_F
))) {
6945 * We either have an Error or Initialized condition
6946 * report errors preferentially.
6949 if (pcie_fw
& PCIE_FW_ERR_F
)
6950 *state
= DEV_STATE_ERR
;
6951 else if (pcie_fw
& PCIE_FW_INIT_F
)
6952 *state
= DEV_STATE_INIT
;
6956 * If we arrived before a Master PF was selected and
6957 * there's not a valid Master PF, grab its identity
6960 if (master_mbox
== PCIE_FW_MASTER_M
&&
6961 (pcie_fw
& PCIE_FW_MASTER_VLD_F
))
6962 master_mbox
= PCIE_FW_MASTER_G(pcie_fw
);
6971 * t4_fw_bye - end communication with FW
6972 * @adap: the adapter
6973 * @mbox: mailbox to use for the FW command
6975 * Issues a command to terminate communication with FW.
6977 int t4_fw_bye(struct adapter
*adap
, unsigned int mbox
)
6979 struct fw_bye_cmd c
;
6981 memset(&c
, 0, sizeof(c
));
6982 INIT_CMD(c
, BYE
, WRITE
);
6983 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
6987 * t4_init_cmd - ask FW to initialize the device
6988 * @adap: the adapter
6989 * @mbox: mailbox to use for the FW command
6991 * Issues a command to FW to partially initialize the device. This
6992 * performs initialization that generally doesn't depend on user input.
6994 int t4_early_init(struct adapter
*adap
, unsigned int mbox
)
6996 struct fw_initialize_cmd c
;
6998 memset(&c
, 0, sizeof(c
));
6999 INIT_CMD(c
, INITIALIZE
, WRITE
);
7000 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
7004 * t4_fw_reset - issue a reset to FW
7005 * @adap: the adapter
7006 * @mbox: mailbox to use for the FW command
7007 * @reset: specifies the type of reset to perform
7009 * Issues a reset command of the specified type to FW.
7011 int t4_fw_reset(struct adapter
*adap
, unsigned int mbox
, int reset
)
7013 struct fw_reset_cmd c
;
7015 memset(&c
, 0, sizeof(c
));
7016 INIT_CMD(c
, RESET
, WRITE
);
7017 c
.val
= cpu_to_be32(reset
);
7018 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
7022 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
7023 * @adap: the adapter
7024 * @mbox: mailbox to use for the FW RESET command (if desired)
7025 * @force: force uP into RESET even if FW RESET command fails
7027 * Issues a RESET command to firmware (if desired) with a HALT indication
7028 * and then puts the microprocessor into RESET state. The RESET command
7029 * will only be issued if a legitimate mailbox is provided (mbox <=
7030 * PCIE_FW_MASTER_M).
7032 * This is generally used in order for the host to safely manipulate the
7033 * adapter without fear of conflicting with whatever the firmware might
7034 * be doing. The only way out of this state is to RESTART the firmware
7037 static int t4_fw_halt(struct adapter
*adap
, unsigned int mbox
, int force
)
7042 * If a legitimate mailbox is provided, issue a RESET command
7043 * with a HALT indication.
7045 if (mbox
<= PCIE_FW_MASTER_M
) {
7046 struct fw_reset_cmd c
;
7048 memset(&c
, 0, sizeof(c
));
7049 INIT_CMD(c
, RESET
, WRITE
);
7050 c
.val
= cpu_to_be32(PIORST_F
| PIORSTMODE_F
);
7051 c
.halt_pkd
= cpu_to_be32(FW_RESET_CMD_HALT_F
);
7052 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
7056 * Normally we won't complete the operation if the firmware RESET
7057 * command fails but if our caller insists we'll go ahead and put the
7058 * uP into RESET. This can be useful if the firmware is hung or even
7059 * missing ... We'll have to take the risk of putting the uP into
7060 * RESET without the cooperation of firmware in that case.
7062 * We also force the firmware's HALT flag to be on in case we bypassed
7063 * the firmware RESET command above or we're dealing with old firmware
7064 * which doesn't have the HALT capability. This will serve as a flag
7065 * for the incoming firmware to know that it's coming out of a HALT
7066 * rather than a RESET ... if it's new enough to understand that ...
7068 if (ret
== 0 || force
) {
7069 t4_set_reg_field(adap
, CIM_BOOT_CFG_A
, UPCRST_F
, UPCRST_F
);
7070 t4_set_reg_field(adap
, PCIE_FW_A
, PCIE_FW_HALT_F
,
7075 * And we always return the result of the firmware RESET command
7076 * even when we force the uP into RESET ...
7082 * t4_fw_restart - restart the firmware by taking the uP out of RESET
7083 * @adap: the adapter
7084 * @reset: if we want to do a RESET to restart things
7086 * Restart firmware previously halted by t4_fw_halt(). On successful
7087 * return the previous PF Master remains as the new PF Master and there
7088 * is no need to issue a new HELLO command, etc.
7090 * We do this in two ways:
7092 * 1. If we're dealing with newer firmware we'll simply want to take
7093 * the chip's microprocessor out of RESET. This will cause the
7094 * firmware to start up from its start vector. And then we'll loop
7095 * until the firmware indicates it's started again (PCIE_FW.HALT
7096 * reset to 0) or we timeout.
7098 * 2. If we're dealing with older firmware then we'll need to RESET
7099 * the chip since older firmware won't recognize the PCIE_FW.HALT
7100 * flag and automatically RESET itself on startup.
7102 static int t4_fw_restart(struct adapter
*adap
, unsigned int mbox
, int reset
)
7106 * Since we're directing the RESET instead of the firmware
7107 * doing it automatically, we need to clear the PCIE_FW.HALT
7110 t4_set_reg_field(adap
, PCIE_FW_A
, PCIE_FW_HALT_F
, 0);
7113 * If we've been given a valid mailbox, first try to get the
7114 * firmware to do the RESET. If that works, great and we can
7115 * return success. Otherwise, if we haven't been given a
7116 * valid mailbox or the RESET command failed, fall back to
7117 * hitting the chip with a hammer.
7119 if (mbox
<= PCIE_FW_MASTER_M
) {
7120 t4_set_reg_field(adap
, CIM_BOOT_CFG_A
, UPCRST_F
, 0);
7122 if (t4_fw_reset(adap
, mbox
,
7123 PIORST_F
| PIORSTMODE_F
) == 0)
7127 t4_write_reg(adap
, PL_RST_A
, PIORST_F
| PIORSTMODE_F
);
7132 t4_set_reg_field(adap
, CIM_BOOT_CFG_A
, UPCRST_F
, 0);
7133 for (ms
= 0; ms
< FW_CMD_MAX_TIMEOUT
; ) {
7134 if (!(t4_read_reg(adap
, PCIE_FW_A
) & PCIE_FW_HALT_F
))
7145 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
7146 * @adap: the adapter
7147 * @mbox: mailbox to use for the FW RESET command (if desired)
7148 * @fw_data: the firmware image to write
7150 * @force: force upgrade even if firmware doesn't cooperate
7152 * Perform all of the steps necessary for upgrading an adapter's
7153 * firmware image. Normally this requires the cooperation of the
7154 * existing firmware in order to halt all existing activities
7155 * but if an invalid mailbox token is passed in we skip that step
7156 * (though we'll still put the adapter microprocessor into RESET in
7159 * On successful return the new firmware will have been loaded and
7160 * the adapter will have been fully RESET losing all previous setup
7161 * state. On unsuccessful return the adapter may be completely hosed ...
7162 * positive errno indicates that the adapter is ~probably~ intact, a
7163 * negative errno indicates that things are looking bad ...
7165 int t4_fw_upgrade(struct adapter
*adap
, unsigned int mbox
,
7166 const u8
*fw_data
, unsigned int size
, int force
)
7168 const struct fw_hdr
*fw_hdr
= (const struct fw_hdr
*)fw_data
;
7171 if (!t4_fw_matches_chip(adap
, fw_hdr
))
7174 /* Disable CXGB4_FW_OK flag so that mbox commands with CXGB4_FW_OK flag
7175 * set wont be sent when we are flashing FW.
7177 adap
->flags
&= ~CXGB4_FW_OK
;
7179 ret
= t4_fw_halt(adap
, mbox
, force
);
7180 if (ret
< 0 && !force
)
7183 ret
= t4_load_fw(adap
, fw_data
, size
);
7188 * If there was a Firmware Configuration File stored in FLASH,
7189 * there's a good chance that it won't be compatible with the new
7190 * Firmware. In order to prevent difficult to diagnose adapter
7191 * initialization issues, we clear out the Firmware Configuration File
7192 * portion of the FLASH . The user will need to re-FLASH a new
7193 * Firmware Configuration File which is compatible with the new
7194 * Firmware if that's desired.
7196 (void)t4_load_cfg(adap
, NULL
, 0);
7199 * Older versions of the firmware don't understand the new
7200 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
7201 * restart. So for newly loaded older firmware we'll have to do the
7202 * RESET for it so it starts up on a clean slate. We can tell if
7203 * the newly loaded firmware will handle this right by checking
7204 * its header flags to see if it advertises the capability.
7206 reset
= ((be32_to_cpu(fw_hdr
->flags
) & FW_HDR_FLAGS_RESET_HALT
) == 0);
7207 ret
= t4_fw_restart(adap
, mbox
, reset
);
7209 /* Grab potentially new Firmware Device Log parameters so we can see
7210 * how healthy the new Firmware is. It's okay to contact the new
7211 * Firmware for these parameters even though, as far as it's
7212 * concerned, we've never said "HELLO" to it ...
7214 (void)t4_init_devlog_params(adap
);
7216 adap
->flags
|= CXGB4_FW_OK
;
7221 * t4_fl_pkt_align - return the fl packet alignment
7222 * @adap: the adapter
7224 * T4 has a single field to specify the packing and padding boundary.
7225 * T5 onwards has separate fields for this and hence the alignment for
7226 * next packet offset is maximum of these two.
7229 int t4_fl_pkt_align(struct adapter
*adap
)
7231 u32 sge_control
, sge_control2
;
7232 unsigned int ingpadboundary
, ingpackboundary
, fl_align
, ingpad_shift
;
7234 sge_control
= t4_read_reg(adap
, SGE_CONTROL_A
);
7236 /* T4 uses a single control field to specify both the PCIe Padding and
7237 * Packing Boundary. T5 introduced the ability to specify these
7238 * separately. The actual Ingress Packet Data alignment boundary
7239 * within Packed Buffer Mode is the maximum of these two
7240 * specifications. (Note that it makes no real practical sense to
7241 * have the Padding Boundary be larger than the Packing Boundary but you
7242 * could set the chip up that way and, in fact, legacy T4 code would
7243 * end doing this because it would initialize the Padding Boundary and
7244 * leave the Packing Boundary initialized to 0 (16 bytes).)
7245 * Padding Boundary values in T6 starts from 8B,
7246 * where as it is 32B for T4 and T5.
7248 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) <= CHELSIO_T5
)
7249 ingpad_shift
= INGPADBOUNDARY_SHIFT_X
;
7251 ingpad_shift
= T6_INGPADBOUNDARY_SHIFT_X
;
7253 ingpadboundary
= 1 << (INGPADBOUNDARY_G(sge_control
) + ingpad_shift
);
7255 fl_align
= ingpadboundary
;
7256 if (!is_t4(adap
->params
.chip
)) {
7257 /* T5 has a weird interpretation of one of the PCIe Packing
7258 * Boundary values. No idea why ...
7260 sge_control2
= t4_read_reg(adap
, SGE_CONTROL2_A
);
7261 ingpackboundary
= INGPACKBOUNDARY_G(sge_control2
);
7262 if (ingpackboundary
== INGPACKBOUNDARY_16B_X
)
7263 ingpackboundary
= 16;
7265 ingpackboundary
= 1 << (ingpackboundary
+
7266 INGPACKBOUNDARY_SHIFT_X
);
7268 fl_align
= max(ingpadboundary
, ingpackboundary
);
7274 * t4_fixup_host_params - fix up host-dependent parameters
7275 * @adap: the adapter
7276 * @page_size: the host's Base Page Size
7277 * @cache_line_size: the host's Cache Line Size
7279 * Various registers in T4 contain values which are dependent on the
7280 * host's Base Page and Cache Line Sizes. This function will fix all of
7281 * those registers with the appropriate values as passed in ...
7283 int t4_fixup_host_params(struct adapter
*adap
, unsigned int page_size
,
7284 unsigned int cache_line_size
)
7286 unsigned int page_shift
= fls(page_size
) - 1;
7287 unsigned int sge_hps
= page_shift
- 10;
7288 unsigned int stat_len
= cache_line_size
> 64 ? 128 : 64;
7289 unsigned int fl_align
= cache_line_size
< 32 ? 32 : cache_line_size
;
7290 unsigned int fl_align_log
= fls(fl_align
) - 1;
7292 t4_write_reg(adap
, SGE_HOST_PAGE_SIZE_A
,
7293 HOSTPAGESIZEPF0_V(sge_hps
) |
7294 HOSTPAGESIZEPF1_V(sge_hps
) |
7295 HOSTPAGESIZEPF2_V(sge_hps
) |
7296 HOSTPAGESIZEPF3_V(sge_hps
) |
7297 HOSTPAGESIZEPF4_V(sge_hps
) |
7298 HOSTPAGESIZEPF5_V(sge_hps
) |
7299 HOSTPAGESIZEPF6_V(sge_hps
) |
7300 HOSTPAGESIZEPF7_V(sge_hps
));
7302 if (is_t4(adap
->params
.chip
)) {
7303 t4_set_reg_field(adap
, SGE_CONTROL_A
,
7304 INGPADBOUNDARY_V(INGPADBOUNDARY_M
) |
7305 EGRSTATUSPAGESIZE_F
,
7306 INGPADBOUNDARY_V(fl_align_log
-
7307 INGPADBOUNDARY_SHIFT_X
) |
7308 EGRSTATUSPAGESIZE_V(stat_len
!= 64));
7310 unsigned int pack_align
;
7311 unsigned int ingpad
, ingpack
;
7313 /* T5 introduced the separation of the Free List Padding and
7314 * Packing Boundaries. Thus, we can select a smaller Padding
7315 * Boundary to avoid uselessly chewing up PCIe Link and Memory
7316 * Bandwidth, and use a Packing Boundary which is large enough
7317 * to avoid false sharing between CPUs, etc.
7319 * For the PCI Link, the smaller the Padding Boundary the
7320 * better. For the Memory Controller, a smaller Padding
7321 * Boundary is better until we cross under the Memory Line
7322 * Size (the minimum unit of transfer to/from Memory). If we
7323 * have a Padding Boundary which is smaller than the Memory
7324 * Line Size, that'll involve a Read-Modify-Write cycle on the
7325 * Memory Controller which is never good.
7328 /* We want the Packing Boundary to be based on the Cache Line
7329 * Size in order to help avoid False Sharing performance
7330 * issues between CPUs, etc. We also want the Packing
7331 * Boundary to incorporate the PCI-E Maximum Payload Size. We
7332 * get best performance when the Packing Boundary is a
7333 * multiple of the Maximum Payload Size.
7335 pack_align
= fl_align
;
7336 if (pci_is_pcie(adap
->pdev
)) {
7337 unsigned int mps
, mps_log
;
7340 /* The PCIe Device Control Maximum Payload Size field
7341 * [bits 7:5] encodes sizes as powers of 2 starting at
7344 pcie_capability_read_word(adap
->pdev
, PCI_EXP_DEVCTL
,
7346 mps_log
= ((devctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5) + 7;
7348 if (mps
> pack_align
)
7352 /* N.B. T5/T6 have a crazy special interpretation of the "0"
7353 * value for the Packing Boundary. This corresponds to 16
7354 * bytes instead of the expected 32 bytes. So if we want 32
7355 * bytes, the best we can really do is 64 bytes ...
7357 if (pack_align
<= 16) {
7358 ingpack
= INGPACKBOUNDARY_16B_X
;
7360 } else if (pack_align
== 32) {
7361 ingpack
= INGPACKBOUNDARY_64B_X
;
7364 unsigned int pack_align_log
= fls(pack_align
) - 1;
7366 ingpack
= pack_align_log
- INGPACKBOUNDARY_SHIFT_X
;
7367 fl_align
= pack_align
;
7370 /* Use the smallest Ingress Padding which isn't smaller than
7371 * the Memory Controller Read/Write Size. We'll take that as
7372 * being 8 bytes since we don't know of any system with a
7373 * wider Memory Controller Bus Width.
7375 if (is_t5(adap
->params
.chip
))
7376 ingpad
= INGPADBOUNDARY_32B_X
;
7378 ingpad
= T6_INGPADBOUNDARY_8B_X
;
7380 t4_set_reg_field(adap
, SGE_CONTROL_A
,
7381 INGPADBOUNDARY_V(INGPADBOUNDARY_M
) |
7382 EGRSTATUSPAGESIZE_F
,
7383 INGPADBOUNDARY_V(ingpad
) |
7384 EGRSTATUSPAGESIZE_V(stat_len
!= 64));
7385 t4_set_reg_field(adap
, SGE_CONTROL2_A
,
7386 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M
),
7387 INGPACKBOUNDARY_V(ingpack
));
7390 * Adjust various SGE Free List Host Buffer Sizes.
7392 * This is something of a crock since we're using fixed indices into
7393 * the array which are also known by the sge.c code and the T4
7394 * Firmware Configuration File. We need to come up with a much better
7395 * approach to managing this array. For now, the first four entries
7400 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
7401 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
7403 * For the single-MTU buffers in unpacked mode we need to include
7404 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
7405 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
7406 * Padding boundary. All of these are accommodated in the Factory
7407 * Default Firmware Configuration File but we need to adjust it for
7408 * this host's cache line size.
7410 t4_write_reg(adap
, SGE_FL_BUFFER_SIZE0_A
, page_size
);
7411 t4_write_reg(adap
, SGE_FL_BUFFER_SIZE2_A
,
7412 (t4_read_reg(adap
, SGE_FL_BUFFER_SIZE2_A
) + fl_align
-1)
7414 t4_write_reg(adap
, SGE_FL_BUFFER_SIZE3_A
,
7415 (t4_read_reg(adap
, SGE_FL_BUFFER_SIZE3_A
) + fl_align
-1)
7418 t4_write_reg(adap
, ULP_RX_TDDP_PSZ_A
, HPZ0_V(page_shift
- 12));
7424 * t4_fw_initialize - ask FW to initialize the device
7425 * @adap: the adapter
7426 * @mbox: mailbox to use for the FW command
7428 * Issues a command to FW to partially initialize the device. This
7429 * performs initialization that generally doesn't depend on user input.
7431 int t4_fw_initialize(struct adapter
*adap
, unsigned int mbox
)
7433 struct fw_initialize_cmd c
;
7435 memset(&c
, 0, sizeof(c
));
7436 INIT_CMD(c
, INITIALIZE
, WRITE
);
7437 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
7441 * t4_query_params_rw - query FW or device parameters
7442 * @adap: the adapter
7443 * @mbox: mailbox to use for the FW command
7446 * @nparams: the number of parameters
7447 * @params: the parameter names
7448 * @val: the parameter values
7449 * @rw: Write and read flag
7450 * @sleep_ok: if true, we may sleep awaiting mbox cmd completion
7452 * Reads the value of FW or device parameters. Up to 7 parameters can be
7455 int t4_query_params_rw(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
7456 unsigned int vf
, unsigned int nparams
, const u32
*params
,
7457 u32
*val
, int rw
, bool sleep_ok
)
7460 struct fw_params_cmd c
;
7461 __be32
*p
= &c
.param
[0].mnem
;
7466 memset(&c
, 0, sizeof(c
));
7467 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD
) |
7468 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
7469 FW_PARAMS_CMD_PFN_V(pf
) |
7470 FW_PARAMS_CMD_VFN_V(vf
));
7471 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
7473 for (i
= 0; i
< nparams
; i
++) {
7474 *p
++ = cpu_to_be32(*params
++);
7476 *p
= cpu_to_be32(*(val
+ i
));
7480 ret
= t4_wr_mbox_meat(adap
, mbox
, &c
, sizeof(c
), &c
, sleep_ok
);
7482 for (i
= 0, p
= &c
.param
[0].val
; i
< nparams
; i
++, p
+= 2)
7483 *val
++ = be32_to_cpu(*p
);
7487 int t4_query_params(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
7488 unsigned int vf
, unsigned int nparams
, const u32
*params
,
7491 return t4_query_params_rw(adap
, mbox
, pf
, vf
, nparams
, params
, val
, 0,
7495 int t4_query_params_ns(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
7496 unsigned int vf
, unsigned int nparams
, const u32
*params
,
7499 return t4_query_params_rw(adap
, mbox
, pf
, vf
, nparams
, params
, val
, 0,
7504 * t4_set_params_timeout - sets FW or device parameters
7505 * @adap: the adapter
7506 * @mbox: mailbox to use for the FW command
7509 * @nparams: the number of parameters
7510 * @params: the parameter names
7511 * @val: the parameter values
7512 * @timeout: the timeout time
7514 * Sets the value of FW or device parameters. Up to 7 parameters can be
7515 * specified at once.
7517 int t4_set_params_timeout(struct adapter
*adap
, unsigned int mbox
,
7518 unsigned int pf
, unsigned int vf
,
7519 unsigned int nparams
, const u32
*params
,
7520 const u32
*val
, int timeout
)
7522 struct fw_params_cmd c
;
7523 __be32
*p
= &c
.param
[0].mnem
;
7528 memset(&c
, 0, sizeof(c
));
7529 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD
) |
7530 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
7531 FW_PARAMS_CMD_PFN_V(pf
) |
7532 FW_PARAMS_CMD_VFN_V(vf
));
7533 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
7536 *p
++ = cpu_to_be32(*params
++);
7537 *p
++ = cpu_to_be32(*val
++);
7540 return t4_wr_mbox_timeout(adap
, mbox
, &c
, sizeof(c
), NULL
, timeout
);
7544 * t4_set_params - sets FW or device parameters
7545 * @adap: the adapter
7546 * @mbox: mailbox to use for the FW command
7549 * @nparams: the number of parameters
7550 * @params: the parameter names
7551 * @val: the parameter values
7553 * Sets the value of FW or device parameters. Up to 7 parameters can be
7554 * specified at once.
7556 int t4_set_params(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
7557 unsigned int vf
, unsigned int nparams
, const u32
*params
,
7560 return t4_set_params_timeout(adap
, mbox
, pf
, vf
, nparams
, params
, val
,
7561 FW_CMD_MAX_TIMEOUT
);
7565 * t4_cfg_pfvf - configure PF/VF resource limits
7566 * @adap: the adapter
7567 * @mbox: mailbox to use for the FW command
7568 * @pf: the PF being configured
7569 * @vf: the VF being configured
7570 * @txq: the max number of egress queues
7571 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
7572 * @rxqi: the max number of interrupt-capable ingress queues
7573 * @rxq: the max number of interruptless ingress queues
7574 * @tc: the PCI traffic class
7575 * @vi: the max number of virtual interfaces
7576 * @cmask: the channel access rights mask for the PF/VF
7577 * @pmask: the port access rights mask for the PF/VF
7578 * @nexact: the maximum number of exact MPS filters
7579 * @rcaps: read capabilities
7580 * @wxcaps: write/execute capabilities
7582 * Configures resource limits and capabilities for a physical or virtual
7585 int t4_cfg_pfvf(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
7586 unsigned int vf
, unsigned int txq
, unsigned int txq_eth_ctrl
,
7587 unsigned int rxqi
, unsigned int rxq
, unsigned int tc
,
7588 unsigned int vi
, unsigned int cmask
, unsigned int pmask
,
7589 unsigned int nexact
, unsigned int rcaps
, unsigned int wxcaps
)
7591 struct fw_pfvf_cmd c
;
7593 memset(&c
, 0, sizeof(c
));
7594 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD
) | FW_CMD_REQUEST_F
|
7595 FW_CMD_WRITE_F
| FW_PFVF_CMD_PFN_V(pf
) |
7596 FW_PFVF_CMD_VFN_V(vf
));
7597 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
7598 c
.niqflint_niq
= cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi
) |
7599 FW_PFVF_CMD_NIQ_V(rxq
));
7600 c
.type_to_neq
= cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask
) |
7601 FW_PFVF_CMD_PMASK_V(pmask
) |
7602 FW_PFVF_CMD_NEQ_V(txq
));
7603 c
.tc_to_nexactf
= cpu_to_be32(FW_PFVF_CMD_TC_V(tc
) |
7604 FW_PFVF_CMD_NVI_V(vi
) |
7605 FW_PFVF_CMD_NEXACTF_V(nexact
));
7606 c
.r_caps_to_nethctrl
= cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps
) |
7607 FW_PFVF_CMD_WX_CAPS_V(wxcaps
) |
7608 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl
));
7609 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
7613 * t4_alloc_vi - allocate a virtual interface
7614 * @adap: the adapter
7615 * @mbox: mailbox to use for the FW command
7616 * @port: physical port associated with the VI
7617 * @pf: the PF owning the VI
7618 * @vf: the VF owning the VI
7619 * @nmac: number of MAC addresses needed (1 to 5)
7620 * @mac: the MAC addresses of the VI
7621 * @rss_size: size of RSS table slice associated with this VI
7623 * Allocates a virtual interface for the given physical port. If @mac is
7624 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
7625 * @mac should be large enough to hold @nmac Ethernet addresses, they are
7626 * stored consecutively so the space needed is @nmac * 6 bytes.
7627 * Returns a negative error number or the non-negative VI id.
7629 int t4_alloc_vi(struct adapter
*adap
, unsigned int mbox
, unsigned int port
,
7630 unsigned int pf
, unsigned int vf
, unsigned int nmac
, u8
*mac
,
7631 unsigned int *rss_size
, u8
*vivld
, u8
*vin
)
7636 memset(&c
, 0, sizeof(c
));
7637 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD
) | FW_CMD_REQUEST_F
|
7638 FW_CMD_WRITE_F
| FW_CMD_EXEC_F
|
7639 FW_VI_CMD_PFN_V(pf
) | FW_VI_CMD_VFN_V(vf
));
7640 c
.alloc_to_len16
= cpu_to_be32(FW_VI_CMD_ALLOC_F
| FW_LEN16(c
));
7641 c
.portid_pkd
= FW_VI_CMD_PORTID_V(port
);
7644 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
7649 memcpy(mac
, c
.mac
, sizeof(c
.mac
));
7652 memcpy(mac
+ 24, c
.nmac3
, sizeof(c
.nmac3
));
7655 memcpy(mac
+ 18, c
.nmac2
, sizeof(c
.nmac2
));
7658 memcpy(mac
+ 12, c
.nmac1
, sizeof(c
.nmac1
));
7661 memcpy(mac
+ 6, c
.nmac0
, sizeof(c
.nmac0
));
7665 *rss_size
= FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c
.rsssize_pkd
));
7668 *vivld
= FW_VI_CMD_VFVLD_G(be32_to_cpu(c
.alloc_to_len16
));
7671 *vin
= FW_VI_CMD_VIN_G(be32_to_cpu(c
.alloc_to_len16
));
7673 return FW_VI_CMD_VIID_G(be16_to_cpu(c
.type_viid
));
7677 * t4_free_vi - free a virtual interface
7678 * @adap: the adapter
7679 * @mbox: mailbox to use for the FW command
7680 * @pf: the PF owning the VI
7681 * @vf: the VF owning the VI
7682 * @viid: virtual interface identifiler
7684 * Free a previously allocated virtual interface.
7686 int t4_free_vi(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
7687 unsigned int vf
, unsigned int viid
)
7691 memset(&c
, 0, sizeof(c
));
7692 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD
) |
7695 FW_VI_CMD_PFN_V(pf
) |
7696 FW_VI_CMD_VFN_V(vf
));
7697 c
.alloc_to_len16
= cpu_to_be32(FW_VI_CMD_FREE_F
| FW_LEN16(c
));
7698 c
.type_viid
= cpu_to_be16(FW_VI_CMD_VIID_V(viid
));
7700 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
7704 * t4_set_rxmode - set Rx properties of a virtual interface
7705 * @adap: the adapter
7706 * @mbox: mailbox to use for the FW command
7708 * @mtu: the new MTU or -1
7709 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7710 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7711 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7712 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7713 * @sleep_ok: if true we may sleep while awaiting command completion
7715 * Sets Rx properties of a virtual interface.
7717 int t4_set_rxmode(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
7718 int mtu
, int promisc
, int all_multi
, int bcast
, int vlanex
,
7721 struct fw_vi_rxmode_cmd c
;
7723 /* convert to FW values */
7725 mtu
= FW_RXMODE_MTU_NO_CHG
;
7727 promisc
= FW_VI_RXMODE_CMD_PROMISCEN_M
;
7729 all_multi
= FW_VI_RXMODE_CMD_ALLMULTIEN_M
;
7731 bcast
= FW_VI_RXMODE_CMD_BROADCASTEN_M
;
7733 vlanex
= FW_VI_RXMODE_CMD_VLANEXEN_M
;
7735 memset(&c
, 0, sizeof(c
));
7736 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD
) |
7737 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
7738 FW_VI_RXMODE_CMD_VIID_V(viid
));
7739 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
7741 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu
) |
7742 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc
) |
7743 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi
) |
7744 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast
) |
7745 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex
));
7746 return t4_wr_mbox_meat(adap
, mbox
, &c
, sizeof(c
), NULL
, sleep_ok
);
7750 * t4_free_encap_mac_filt - frees MPS entry at given index
7751 * @adap: the adapter
7753 * @idx: index of MPS entry to be freed
7754 * @sleep_ok: call is allowed to sleep
7756 * Frees the MPS entry at supplied index
7758 * Returns a negative error number or zero on success
7760 int t4_free_encap_mac_filt(struct adapter
*adap
, unsigned int viid
,
7761 int idx
, bool sleep_ok
)
7763 struct fw_vi_mac_exact
*p
;
7764 u8 addr
[] = {0, 0, 0, 0, 0, 0};
7765 struct fw_vi_mac_cmd c
;
7769 memset(&c
, 0, sizeof(c
));
7770 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
7771 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
7773 FW_VI_MAC_CMD_VIID_V(viid
));
7774 exact
= FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC
);
7775 c
.freemacs_to_len16
= cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7779 p
->valid_to_idx
= cpu_to_be16(FW_VI_MAC_CMD_VALID_F
|
7780 FW_VI_MAC_CMD_IDX_V(idx
));
7781 memcpy(p
->macaddr
, addr
, sizeof(p
->macaddr
));
7782 ret
= t4_wr_mbox_meat(adap
, adap
->mbox
, &c
, sizeof(c
), &c
, sleep_ok
);
7787 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
7788 * @adap: the adapter
7790 * @addr: the MAC address
7792 * @idx: index of the entry in mps tcam
7793 * @lookup_type: MAC address for inner (1) or outer (0) header
7794 * @port_id: the port index
7795 * @sleep_ok: call is allowed to sleep
7797 * Removes the mac entry at the specified index using raw mac interface.
7799 * Returns a negative error number on failure.
7801 int t4_free_raw_mac_filt(struct adapter
*adap
, unsigned int viid
,
7802 const u8
*addr
, const u8
*mask
, unsigned int idx
,
7803 u8 lookup_type
, u8 port_id
, bool sleep_ok
)
7805 struct fw_vi_mac_cmd c
;
7806 struct fw_vi_mac_raw
*p
= &c
.u
.raw
;
7809 memset(&c
, 0, sizeof(c
));
7810 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
7811 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
7813 FW_VI_MAC_CMD_VIID_V(viid
));
7814 val
= FW_CMD_LEN16_V(1) |
7815 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW
);
7816 c
.freemacs_to_len16
= cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7817 FW_CMD_LEN16_V(val
));
7819 p
->raw_idx_pkd
= cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx
) |
7820 FW_VI_MAC_ID_BASED_FREE
);
7822 /* Lookup Type. Outer header: 0, Inner header: 1 */
7823 p
->data0_pkd
= cpu_to_be32(DATALKPTYPE_V(lookup_type
) |
7824 DATAPORTNUM_V(port_id
));
7825 /* Lookup mask and port mask */
7826 p
->data0m_pkd
= cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M
) |
7827 DATAPORTNUM_V(DATAPORTNUM_M
));
7829 /* Copy the address and the mask */
7830 memcpy((u8
*)&p
->data1
[0] + 2, addr
, ETH_ALEN
);
7831 memcpy((u8
*)&p
->data1m
[0] + 2, mask
, ETH_ALEN
);
7833 return t4_wr_mbox_meat(adap
, adap
->mbox
, &c
, sizeof(c
), &c
, sleep_ok
);
7837 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support
7838 * @adap: the adapter
7840 * @mac: the MAC address
7842 * @vni: the VNI id for the tunnel protocol
7843 * @vni_mask: mask for the VNI id
7844 * @dip_hit: to enable DIP match for the MPS entry
7845 * @lookup_type: MAC address for inner (1) or outer (0) header
7846 * @sleep_ok: call is allowed to sleep
7848 * Allocates an MPS entry with specified MAC address and VNI value.
7850 * Returns a negative error number or the allocated index for this mac.
7852 int t4_alloc_encap_mac_filt(struct adapter
*adap
, unsigned int viid
,
7853 const u8
*addr
, const u8
*mask
, unsigned int vni
,
7854 unsigned int vni_mask
, u8 dip_hit
, u8 lookup_type
,
7857 struct fw_vi_mac_cmd c
;
7858 struct fw_vi_mac_vni
*p
= c
.u
.exact_vni
;
7862 memset(&c
, 0, sizeof(c
));
7863 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
7864 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
7865 FW_VI_MAC_CMD_VIID_V(viid
));
7866 val
= FW_CMD_LEN16_V(1) |
7867 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC_VNI
);
7868 c
.freemacs_to_len16
= cpu_to_be32(val
);
7869 p
->valid_to_idx
= cpu_to_be16(FW_VI_MAC_CMD_VALID_F
|
7870 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC
));
7871 memcpy(p
->macaddr
, addr
, sizeof(p
->macaddr
));
7872 memcpy(p
->macaddr_mask
, mask
, sizeof(p
->macaddr_mask
));
7874 p
->lookup_type_to_vni
=
7875 cpu_to_be32(FW_VI_MAC_CMD_VNI_V(vni
) |
7876 FW_VI_MAC_CMD_DIP_HIT_V(dip_hit
) |
7877 FW_VI_MAC_CMD_LOOKUP_TYPE_V(lookup_type
));
7878 p
->vni_mask_pkd
= cpu_to_be32(FW_VI_MAC_CMD_VNI_MASK_V(vni_mask
));
7879 ret
= t4_wr_mbox_meat(adap
, adap
->mbox
, &c
, sizeof(c
), &c
, sleep_ok
);
7881 ret
= FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p
->valid_to_idx
));
7886 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
7887 * @adap: the adapter
7889 * @mac: the MAC address
7891 * @idx: index at which to add this entry
7892 * @port_id: the port index
7893 * @lookup_type: MAC address for inner (1) or outer (0) header
7894 * @sleep_ok: call is allowed to sleep
7896 * Adds the mac entry at the specified index using raw mac interface.
7898 * Returns a negative error number or the allocated index for this mac.
7900 int t4_alloc_raw_mac_filt(struct adapter
*adap
, unsigned int viid
,
7901 const u8
*addr
, const u8
*mask
, unsigned int idx
,
7902 u8 lookup_type
, u8 port_id
, bool sleep_ok
)
7905 struct fw_vi_mac_cmd c
;
7906 struct fw_vi_mac_raw
*p
= &c
.u
.raw
;
7909 memset(&c
, 0, sizeof(c
));
7910 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
7911 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
7912 FW_VI_MAC_CMD_VIID_V(viid
));
7913 val
= FW_CMD_LEN16_V(1) |
7914 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW
);
7915 c
.freemacs_to_len16
= cpu_to_be32(val
);
7917 /* Specify that this is an inner mac address */
7918 p
->raw_idx_pkd
= cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx
));
7920 /* Lookup Type. Outer header: 0, Inner header: 1 */
7921 p
->data0_pkd
= cpu_to_be32(DATALKPTYPE_V(lookup_type
) |
7922 DATAPORTNUM_V(port_id
));
7923 /* Lookup mask and port mask */
7924 p
->data0m_pkd
= cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M
) |
7925 DATAPORTNUM_V(DATAPORTNUM_M
));
7927 /* Copy the address and the mask */
7928 memcpy((u8
*)&p
->data1
[0] + 2, addr
, ETH_ALEN
);
7929 memcpy((u8
*)&p
->data1m
[0] + 2, mask
, ETH_ALEN
);
7931 ret
= t4_wr_mbox_meat(adap
, adap
->mbox
, &c
, sizeof(c
), &c
, sleep_ok
);
7933 ret
= FW_VI_MAC_CMD_RAW_IDX_G(be32_to_cpu(p
->raw_idx_pkd
));
7942 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7943 * @adap: the adapter
7944 * @mbox: mailbox to use for the FW command
7946 * @free: if true any existing filters for this VI id are first removed
7947 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
7948 * @addr: the MAC address(es)
7949 * @idx: where to store the index of each allocated filter
7950 * @hash: pointer to hash address filter bitmap
7951 * @sleep_ok: call is allowed to sleep
7953 * Allocates an exact-match filter for each of the supplied addresses and
7954 * sets it to the corresponding address. If @idx is not %NULL it should
7955 * have at least @naddr entries, each of which will be set to the index of
7956 * the filter allocated for the corresponding MAC address. If a filter
7957 * could not be allocated for an address its index is set to 0xffff.
7958 * If @hash is not %NULL addresses that fail to allocate an exact filter
7959 * are hashed and update the hash filter bitmap pointed at by @hash.
7961 * Returns a negative error number or the number of filters allocated.
7963 int t4_alloc_mac_filt(struct adapter
*adap
, unsigned int mbox
,
7964 unsigned int viid
, bool free
, unsigned int naddr
,
7965 const u8
**addr
, u16
*idx
, u64
*hash
, bool sleep_ok
)
7967 int offset
, ret
= 0;
7968 struct fw_vi_mac_cmd c
;
7969 unsigned int nfilters
= 0;
7970 unsigned int max_naddr
= adap
->params
.arch
.mps_tcam_size
;
7971 unsigned int rem
= naddr
;
7973 if (naddr
> max_naddr
)
7976 for (offset
= 0; offset
< naddr
; /**/) {
7977 unsigned int fw_naddr
= (rem
< ARRAY_SIZE(c
.u
.exact
) ?
7978 rem
: ARRAY_SIZE(c
.u
.exact
));
7979 size_t len16
= DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd
,
7980 u
.exact
[fw_naddr
]), 16);
7981 struct fw_vi_mac_exact
*p
;
7984 memset(&c
, 0, sizeof(c
));
7985 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
7988 FW_CMD_EXEC_V(free
) |
7989 FW_VI_MAC_CMD_VIID_V(viid
));
7990 c
.freemacs_to_len16
=
7991 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free
) |
7992 FW_CMD_LEN16_V(len16
));
7994 for (i
= 0, p
= c
.u
.exact
; i
< fw_naddr
; i
++, p
++) {
7996 cpu_to_be16(FW_VI_MAC_CMD_VALID_F
|
7997 FW_VI_MAC_CMD_IDX_V(
7998 FW_VI_MAC_ADD_MAC
));
7999 memcpy(p
->macaddr
, addr
[offset
+ i
],
8000 sizeof(p
->macaddr
));
8003 /* It's okay if we run out of space in our MAC address arena.
8004 * Some of the addresses we submit may get stored so we need
8005 * to run through the reply to see what the results were ...
8007 ret
= t4_wr_mbox_meat(adap
, mbox
, &c
, sizeof(c
), &c
, sleep_ok
);
8008 if (ret
&& ret
!= -FW_ENOMEM
)
8011 for (i
= 0, p
= c
.u
.exact
; i
< fw_naddr
; i
++, p
++) {
8012 u16 index
= FW_VI_MAC_CMD_IDX_G(
8013 be16_to_cpu(p
->valid_to_idx
));
8016 idx
[offset
+ i
] = (index
>= max_naddr
?
8018 if (index
< max_naddr
)
8022 hash_mac_addr(addr
[offset
+ i
]));
8030 if (ret
== 0 || ret
== -FW_ENOMEM
)
8036 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
8037 * @adap: the adapter
8038 * @mbox: mailbox to use for the FW command
8040 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
8041 * @addr: the MAC address(es)
8042 * @sleep_ok: call is allowed to sleep
8044 * Frees the exact-match filter for each of the supplied addresses
8046 * Returns a negative error number or the number of filters freed.
8048 int t4_free_mac_filt(struct adapter
*adap
, unsigned int mbox
,
8049 unsigned int viid
, unsigned int naddr
,
8050 const u8
**addr
, bool sleep_ok
)
8052 int offset
, ret
= 0;
8053 struct fw_vi_mac_cmd c
;
8054 unsigned int nfilters
= 0;
8055 unsigned int max_naddr
= is_t4(adap
->params
.chip
) ?
8056 NUM_MPS_CLS_SRAM_L_INSTANCES
:
8057 NUM_MPS_T5_CLS_SRAM_L_INSTANCES
;
8058 unsigned int rem
= naddr
;
8060 if (naddr
> max_naddr
)
8063 for (offset
= 0; offset
< (int)naddr
; /**/) {
8064 unsigned int fw_naddr
= (rem
< ARRAY_SIZE(c
.u
.exact
)
8066 : ARRAY_SIZE(c
.u
.exact
));
8067 size_t len16
= DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd
,
8068 u
.exact
[fw_naddr
]), 16);
8069 struct fw_vi_mac_exact
*p
;
8072 memset(&c
, 0, sizeof(c
));
8073 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
8077 FW_VI_MAC_CMD_VIID_V(viid
));
8078 c
.freemacs_to_len16
=
8079 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
8080 FW_CMD_LEN16_V(len16
));
8082 for (i
= 0, p
= c
.u
.exact
; i
< (int)fw_naddr
; i
++, p
++) {
8083 p
->valid_to_idx
= cpu_to_be16(
8084 FW_VI_MAC_CMD_VALID_F
|
8085 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE
));
8086 memcpy(p
->macaddr
, addr
[offset
+i
], sizeof(p
->macaddr
));
8089 ret
= t4_wr_mbox_meat(adap
, mbox
, &c
, sizeof(c
), &c
, sleep_ok
);
8093 for (i
= 0, p
= c
.u
.exact
; i
< fw_naddr
; i
++, p
++) {
8094 u16 index
= FW_VI_MAC_CMD_IDX_G(
8095 be16_to_cpu(p
->valid_to_idx
));
8097 if (index
< max_naddr
)
8111 * t4_change_mac - modifies the exact-match filter for a MAC address
8112 * @adap: the adapter
8113 * @mbox: mailbox to use for the FW command
8115 * @idx: index of existing filter for old value of MAC address, or -1
8116 * @addr: the new MAC address value
8117 * @persist: whether a new MAC allocation should be persistent
8118 * @add_smt: if true also add the address to the HW SMT
8120 * Modifies an exact-match filter and sets it to the new MAC address.
8121 * Note that in general it is not possible to modify the value of a given
8122 * filter so the generic way to modify an address filter is to free the one
8123 * being used by the old address value and allocate a new filter for the
8124 * new address value. @idx can be -1 if the address is a new addition.
8126 * Returns a negative error number or the index of the filter with the new
8129 int t4_change_mac(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
8130 int idx
, const u8
*addr
, bool persist
, u8
*smt_idx
)
8133 struct fw_vi_mac_cmd c
;
8134 struct fw_vi_mac_exact
*p
= c
.u
.exact
;
8135 unsigned int max_mac_addr
= adap
->params
.arch
.mps_tcam_size
;
8137 if (idx
< 0) /* new allocation */
8138 idx
= persist
? FW_VI_MAC_ADD_PERSIST_MAC
: FW_VI_MAC_ADD_MAC
;
8139 mode
= smt_idx
? FW_VI_MAC_SMT_AND_MPSTCAM
: FW_VI_MAC_MPS_TCAM_ENTRY
;
8141 memset(&c
, 0, sizeof(c
));
8142 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
8143 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
8144 FW_VI_MAC_CMD_VIID_V(viid
));
8145 c
.freemacs_to_len16
= cpu_to_be32(FW_CMD_LEN16_V(1));
8146 p
->valid_to_idx
= cpu_to_be16(FW_VI_MAC_CMD_VALID_F
|
8147 FW_VI_MAC_CMD_SMAC_RESULT_V(mode
) |
8148 FW_VI_MAC_CMD_IDX_V(idx
));
8149 memcpy(p
->macaddr
, addr
, sizeof(p
->macaddr
));
8151 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
8153 ret
= FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p
->valid_to_idx
));
8154 if (ret
>= max_mac_addr
)
8157 if (adap
->params
.viid_smt_extn_support
) {
8158 *smt_idx
= FW_VI_MAC_CMD_SMTID_G
8159 (be32_to_cpu(c
.op_to_viid
));
8161 /* In T4/T5, SMT contains 256 SMAC entries
8162 * organized in 128 rows of 2 entries each.
8163 * In T6, SMT contains 256 SMAC entries in
8166 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) <=
8168 *smt_idx
= (viid
& FW_VIID_VIN_M
) << 1;
8170 *smt_idx
= (viid
& FW_VIID_VIN_M
);
8178 * t4_set_addr_hash - program the MAC inexact-match hash filter
8179 * @adap: the adapter
8180 * @mbox: mailbox to use for the FW command
8182 * @ucast: whether the hash filter should also match unicast addresses
8183 * @vec: the value to be written to the hash filter
8184 * @sleep_ok: call is allowed to sleep
8186 * Sets the 64-bit inexact-match hash filter for a virtual interface.
8188 int t4_set_addr_hash(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
8189 bool ucast
, u64 vec
, bool sleep_ok
)
8191 struct fw_vi_mac_cmd c
;
8193 memset(&c
, 0, sizeof(c
));
8194 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
8195 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
8196 FW_VI_ENABLE_CMD_VIID_V(viid
));
8197 c
.freemacs_to_len16
= cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F
|
8198 FW_VI_MAC_CMD_HASHUNIEN_V(ucast
) |
8200 c
.u
.hash
.hashvec
= cpu_to_be64(vec
);
8201 return t4_wr_mbox_meat(adap
, mbox
, &c
, sizeof(c
), NULL
, sleep_ok
);
8205 * t4_enable_vi_params - enable/disable a virtual interface
8206 * @adap: the adapter
8207 * @mbox: mailbox to use for the FW command
8209 * @rx_en: 1=enable Rx, 0=disable Rx
8210 * @tx_en: 1=enable Tx, 0=disable Tx
8211 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
8213 * Enables/disables a virtual interface. Note that setting DCB Enable
8214 * only makes sense when enabling a Virtual Interface ...
8216 int t4_enable_vi_params(struct adapter
*adap
, unsigned int mbox
,
8217 unsigned int viid
, bool rx_en
, bool tx_en
, bool dcb_en
)
8219 struct fw_vi_enable_cmd c
;
8221 memset(&c
, 0, sizeof(c
));
8222 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD
) |
8223 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
8224 FW_VI_ENABLE_CMD_VIID_V(viid
));
8225 c
.ien_to_len16
= cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en
) |
8226 FW_VI_ENABLE_CMD_EEN_V(tx_en
) |
8227 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en
) |
8229 return t4_wr_mbox_ns(adap
, mbox
, &c
, sizeof(c
), NULL
);
8233 * t4_enable_vi - enable/disable a virtual interface
8234 * @adap: the adapter
8235 * @mbox: mailbox to use for the FW command
8237 * @rx_en: 1=enable Rx, 0=disable Rx
8238 * @tx_en: 1=enable Tx, 0=disable Tx
8240 * Enables/disables a virtual interface.
8242 int t4_enable_vi(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
8243 bool rx_en
, bool tx_en
)
8245 return t4_enable_vi_params(adap
, mbox
, viid
, rx_en
, tx_en
, 0);
8249 * t4_enable_pi_params - enable/disable a Port's Virtual Interface
8250 * @adap: the adapter
8251 * @mbox: mailbox to use for the FW command
8252 * @pi: the Port Information structure
8253 * @rx_en: 1=enable Rx, 0=disable Rx
8254 * @tx_en: 1=enable Tx, 0=disable Tx
8255 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
8257 * Enables/disables a Port's Virtual Interface. Note that setting DCB
8258 * Enable only makes sense when enabling a Virtual Interface ...
8259 * If the Virtual Interface enable/disable operation is successful,
8260 * we notify the OS-specific code of a potential Link Status change
8261 * via the OS Contract API t4_os_link_changed().
8263 int t4_enable_pi_params(struct adapter
*adap
, unsigned int mbox
,
8264 struct port_info
*pi
,
8265 bool rx_en
, bool tx_en
, bool dcb_en
)
8267 int ret
= t4_enable_vi_params(adap
, mbox
, pi
->viid
,
8268 rx_en
, tx_en
, dcb_en
);
8271 t4_os_link_changed(adap
, pi
->port_id
,
8272 rx_en
&& tx_en
&& pi
->link_cfg
.link_ok
);
8277 * t4_identify_port - identify a VI's port by blinking its LED
8278 * @adap: the adapter
8279 * @mbox: mailbox to use for the FW command
8281 * @nblinks: how many times to blink LED at 2.5 Hz
8283 * Identifies a VI's port by blinking its LED.
8285 int t4_identify_port(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
8286 unsigned int nblinks
)
8288 struct fw_vi_enable_cmd c
;
8290 memset(&c
, 0, sizeof(c
));
8291 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD
) |
8292 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
8293 FW_VI_ENABLE_CMD_VIID_V(viid
));
8294 c
.ien_to_len16
= cpu_to_be32(FW_VI_ENABLE_CMD_LED_F
| FW_LEN16(c
));
8295 c
.blinkdur
= cpu_to_be16(nblinks
);
8296 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
8300 * t4_iq_stop - stop an ingress queue and its FLs
8301 * @adap: the adapter
8302 * @mbox: mailbox to use for the FW command
8303 * @pf: the PF owning the queues
8304 * @vf: the VF owning the queues
8305 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8306 * @iqid: ingress queue id
8307 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8308 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8310 * Stops an ingress queue and its associated FLs, if any. This causes
8311 * any current or future data/messages destined for these queues to be
8314 int t4_iq_stop(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
8315 unsigned int vf
, unsigned int iqtype
, unsigned int iqid
,
8316 unsigned int fl0id
, unsigned int fl1id
)
8320 memset(&c
, 0, sizeof(c
));
8321 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD
) | FW_CMD_REQUEST_F
|
8322 FW_CMD_EXEC_F
| FW_IQ_CMD_PFN_V(pf
) |
8323 FW_IQ_CMD_VFN_V(vf
));
8324 c
.alloc_to_len16
= cpu_to_be32(FW_IQ_CMD_IQSTOP_F
| FW_LEN16(c
));
8325 c
.type_to_iqandstindex
= cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype
));
8326 c
.iqid
= cpu_to_be16(iqid
);
8327 c
.fl0id
= cpu_to_be16(fl0id
);
8328 c
.fl1id
= cpu_to_be16(fl1id
);
8329 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
8333 * t4_iq_free - free an ingress queue and its FLs
8334 * @adap: the adapter
8335 * @mbox: mailbox to use for the FW command
8336 * @pf: the PF owning the queues
8337 * @vf: the VF owning the queues
8338 * @iqtype: the ingress queue type
8339 * @iqid: ingress queue id
8340 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8341 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8343 * Frees an ingress queue and its associated FLs, if any.
8345 int t4_iq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
8346 unsigned int vf
, unsigned int iqtype
, unsigned int iqid
,
8347 unsigned int fl0id
, unsigned int fl1id
)
8351 memset(&c
, 0, sizeof(c
));
8352 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD
) | FW_CMD_REQUEST_F
|
8353 FW_CMD_EXEC_F
| FW_IQ_CMD_PFN_V(pf
) |
8354 FW_IQ_CMD_VFN_V(vf
));
8355 c
.alloc_to_len16
= cpu_to_be32(FW_IQ_CMD_FREE_F
| FW_LEN16(c
));
8356 c
.type_to_iqandstindex
= cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype
));
8357 c
.iqid
= cpu_to_be16(iqid
);
8358 c
.fl0id
= cpu_to_be16(fl0id
);
8359 c
.fl1id
= cpu_to_be16(fl1id
);
8360 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
8364 * t4_eth_eq_free - free an Ethernet egress queue
8365 * @adap: the adapter
8366 * @mbox: mailbox to use for the FW command
8367 * @pf: the PF owning the queue
8368 * @vf: the VF owning the queue
8369 * @eqid: egress queue id
8371 * Frees an Ethernet egress queue.
8373 int t4_eth_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
8374 unsigned int vf
, unsigned int eqid
)
8376 struct fw_eq_eth_cmd c
;
8378 memset(&c
, 0, sizeof(c
));
8379 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD
) |
8380 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
8381 FW_EQ_ETH_CMD_PFN_V(pf
) |
8382 FW_EQ_ETH_CMD_VFN_V(vf
));
8383 c
.alloc_to_len16
= cpu_to_be32(FW_EQ_ETH_CMD_FREE_F
| FW_LEN16(c
));
8384 c
.eqid_pkd
= cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid
));
8385 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
8389 * t4_ctrl_eq_free - free a control egress queue
8390 * @adap: the adapter
8391 * @mbox: mailbox to use for the FW command
8392 * @pf: the PF owning the queue
8393 * @vf: the VF owning the queue
8394 * @eqid: egress queue id
8396 * Frees a control egress queue.
8398 int t4_ctrl_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
8399 unsigned int vf
, unsigned int eqid
)
8401 struct fw_eq_ctrl_cmd c
;
8403 memset(&c
, 0, sizeof(c
));
8404 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD
) |
8405 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
8406 FW_EQ_CTRL_CMD_PFN_V(pf
) |
8407 FW_EQ_CTRL_CMD_VFN_V(vf
));
8408 c
.alloc_to_len16
= cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F
| FW_LEN16(c
));
8409 c
.cmpliqid_eqid
= cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid
));
8410 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
8414 * t4_ofld_eq_free - free an offload egress queue
8415 * @adap: the adapter
8416 * @mbox: mailbox to use for the FW command
8417 * @pf: the PF owning the queue
8418 * @vf: the VF owning the queue
8419 * @eqid: egress queue id
8421 * Frees a control egress queue.
8423 int t4_ofld_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
8424 unsigned int vf
, unsigned int eqid
)
8426 struct fw_eq_ofld_cmd c
;
8428 memset(&c
, 0, sizeof(c
));
8429 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD
) |
8430 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
8431 FW_EQ_OFLD_CMD_PFN_V(pf
) |
8432 FW_EQ_OFLD_CMD_VFN_V(vf
));
8433 c
.alloc_to_len16
= cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F
| FW_LEN16(c
));
8434 c
.eqid_pkd
= cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid
));
8435 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
8439 * t4_link_down_rc_str - return a string for a Link Down Reason Code
8440 * @adap: the adapter
8441 * @link_down_rc: Link Down Reason Code
8443 * Returns a string representation of the Link Down Reason Code.
8445 static const char *t4_link_down_rc_str(unsigned char link_down_rc
)
8447 static const char * const reason
[] = {
8450 "Auto-negotiation Failure",
8452 "Insufficient Airflow",
8453 "Unable To Determine Reason",
8454 "No RX Signal Detected",
8458 if (link_down_rc
>= ARRAY_SIZE(reason
))
8459 return "Bad Reason Code";
8461 return reason
[link_down_rc
];
8465 * Return the highest speed set in the port capabilities, in Mb/s.
8467 static unsigned int fwcap_to_speed(fw_port_cap32_t caps
)
8469 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8471 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8475 TEST_SPEED_RETURN(400G
, 400000);
8476 TEST_SPEED_RETURN(200G
, 200000);
8477 TEST_SPEED_RETURN(100G
, 100000);
8478 TEST_SPEED_RETURN(50G
, 50000);
8479 TEST_SPEED_RETURN(40G
, 40000);
8480 TEST_SPEED_RETURN(25G
, 25000);
8481 TEST_SPEED_RETURN(10G
, 10000);
8482 TEST_SPEED_RETURN(1G
, 1000);
8483 TEST_SPEED_RETURN(100M
, 100);
8485 #undef TEST_SPEED_RETURN
8491 * fwcap_to_fwspeed - return highest speed in Port Capabilities
8492 * @acaps: advertised Port Capabilities
8494 * Get the highest speed for the port from the advertised Port
8495 * Capabilities. It will be either the highest speed from the list of
8496 * speeds or whatever user has set using ethtool.
8498 static fw_port_cap32_t
fwcap_to_fwspeed(fw_port_cap32_t acaps
)
8500 #define TEST_SPEED_RETURN(__caps_speed) \
8502 if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8503 return FW_PORT_CAP32_SPEED_##__caps_speed; \
8506 TEST_SPEED_RETURN(400G
);
8507 TEST_SPEED_RETURN(200G
);
8508 TEST_SPEED_RETURN(100G
);
8509 TEST_SPEED_RETURN(50G
);
8510 TEST_SPEED_RETURN(40G
);
8511 TEST_SPEED_RETURN(25G
);
8512 TEST_SPEED_RETURN(10G
);
8513 TEST_SPEED_RETURN(1G
);
8514 TEST_SPEED_RETURN(100M
);
8516 #undef TEST_SPEED_RETURN
8522 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8523 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
8525 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
8526 * 32-bit Port Capabilities value.
8528 static fw_port_cap32_t
lstatus_to_fwcap(u32 lstatus
)
8530 fw_port_cap32_t linkattr
= 0;
8532 /* Unfortunately the format of the Link Status in the old
8533 * 16-bit Port Information message isn't the same as the
8534 * 16-bit Port Capabilities bitfield used everywhere else ...
8536 if (lstatus
& FW_PORT_CMD_RXPAUSE_F
)
8537 linkattr
|= FW_PORT_CAP32_FC_RX
;
8538 if (lstatus
& FW_PORT_CMD_TXPAUSE_F
)
8539 linkattr
|= FW_PORT_CAP32_FC_TX
;
8540 if (lstatus
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M
))
8541 linkattr
|= FW_PORT_CAP32_SPEED_100M
;
8542 if (lstatus
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G
))
8543 linkattr
|= FW_PORT_CAP32_SPEED_1G
;
8544 if (lstatus
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G
))
8545 linkattr
|= FW_PORT_CAP32_SPEED_10G
;
8546 if (lstatus
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G
))
8547 linkattr
|= FW_PORT_CAP32_SPEED_25G
;
8548 if (lstatus
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G
))
8549 linkattr
|= FW_PORT_CAP32_SPEED_40G
;
8550 if (lstatus
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G
))
8551 linkattr
|= FW_PORT_CAP32_SPEED_100G
;
8557 * t4_handle_get_port_info - process a FW reply message
8558 * @pi: the port info
8559 * @rpl: start of the FW message
8561 * Processes a GET_PORT_INFO FW reply message.
8563 void t4_handle_get_port_info(struct port_info
*pi
, const __be64
*rpl
)
8565 const struct fw_port_cmd
*cmd
= (const void *)rpl
;
8566 int action
= FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd
->action_to_len16
));
8567 struct adapter
*adapter
= pi
->adapter
;
8568 struct link_config
*lc
= &pi
->link_cfg
;
8569 int link_ok
, linkdnrc
;
8570 enum fw_port_type port_type
;
8571 enum fw_port_module_type mod_type
;
8572 unsigned int speed
, fc
, fec
;
8573 fw_port_cap32_t pcaps
, acaps
, lpacaps
, linkattr
;
8575 /* Extract the various fields from the Port Information message.
8578 case FW_PORT_ACTION_GET_PORT_INFO
: {
8579 u32 lstatus
= be32_to_cpu(cmd
->u
.info
.lstatus_to_modtype
);
8581 link_ok
= (lstatus
& FW_PORT_CMD_LSTATUS_F
) != 0;
8582 linkdnrc
= FW_PORT_CMD_LINKDNRC_G(lstatus
);
8583 port_type
= FW_PORT_CMD_PTYPE_G(lstatus
);
8584 mod_type
= FW_PORT_CMD_MODTYPE_G(lstatus
);
8585 pcaps
= fwcaps16_to_caps32(be16_to_cpu(cmd
->u
.info
.pcap
));
8586 acaps
= fwcaps16_to_caps32(be16_to_cpu(cmd
->u
.info
.acap
));
8587 lpacaps
= fwcaps16_to_caps32(be16_to_cpu(cmd
->u
.info
.lpacap
));
8588 linkattr
= lstatus_to_fwcap(lstatus
);
8592 case FW_PORT_ACTION_GET_PORT_INFO32
: {
8595 lstatus32
= be32_to_cpu(cmd
->u
.info32
.lstatus32_to_cbllen32
);
8596 link_ok
= (lstatus32
& FW_PORT_CMD_LSTATUS32_F
) != 0;
8597 linkdnrc
= FW_PORT_CMD_LINKDNRC32_G(lstatus32
);
8598 port_type
= FW_PORT_CMD_PORTTYPE32_G(lstatus32
);
8599 mod_type
= FW_PORT_CMD_MODTYPE32_G(lstatus32
);
8600 pcaps
= be32_to_cpu(cmd
->u
.info32
.pcaps32
);
8601 acaps
= be32_to_cpu(cmd
->u
.info32
.acaps32
);
8602 lpacaps
= be32_to_cpu(cmd
->u
.info32
.lpacaps32
);
8603 linkattr
= be32_to_cpu(cmd
->u
.info32
.linkattr32
);
8608 dev_err(adapter
->pdev_dev
, "Handle Port Information: Bad Command/Action %#x\n",
8609 be32_to_cpu(cmd
->action_to_len16
));
8613 fec
= fwcap_to_cc_fec(acaps
);
8614 fc
= fwcap_to_cc_pause(linkattr
);
8615 speed
= fwcap_to_speed(linkattr
);
8617 /* Reset state for communicating new Transceiver Module status and
8618 * whether the OS-dependent layer wants us to redo the current
8619 * "sticky" L1 Configure Link Parameters.
8621 lc
->new_module
= false;
8622 lc
->redo_l1cfg
= false;
8624 if (mod_type
!= pi
->mod_type
) {
8625 /* With the newer SFP28 and QSFP28 Transceiver Module Types,
8626 * various fundamental Port Capabilities which used to be
8627 * immutable can now change radically. We can now have
8628 * Speeds, Auto-Negotiation, Forward Error Correction, etc.
8629 * all change based on what Transceiver Module is inserted.
8630 * So we need to record the Physical "Port" Capabilities on
8631 * every Transceiver Module change.
8635 /* When a new Transceiver Module is inserted, the Firmware
8636 * will examine its i2c EPROM to determine its type and
8637 * general operating parameters including things like Forward
8638 * Error Control, etc. Various IEEE 802.3 standards dictate
8639 * how to interpret these i2c values to determine default
8640 * "sutomatic" settings. We record these for future use when
8641 * the user explicitly requests these standards-based values.
8643 lc
->def_acaps
= acaps
;
8645 /* Some versions of the early T6 Firmware "cheated" when
8646 * handling different Transceiver Modules by changing the
8647 * underlaying Port Type reported to the Host Drivers. As
8648 * such we need to capture whatever Port Type the Firmware
8649 * sends us and record it in case it's different from what we
8650 * were told earlier. Unfortunately, since Firmware is
8651 * forever, we'll need to keep this code here forever, but in
8652 * later T6 Firmware it should just be an assignment of the
8653 * same value already recorded.
8655 pi
->port_type
= port_type
;
8657 /* Record new Module Type information.
8659 pi
->mod_type
= mod_type
;
8661 /* Let the OS-dependent layer know if we have a new
8662 * Transceiver Module inserted.
8664 lc
->new_module
= t4_is_inserted_mod_type(mod_type
);
8666 t4_os_portmod_changed(adapter
, pi
->port_id
);
8669 if (link_ok
!= lc
->link_ok
|| speed
!= lc
->speed
||
8670 fc
!= lc
->fc
|| fec
!= lc
->fec
) { /* something changed */
8671 if (!link_ok
&& lc
->link_ok
) {
8672 lc
->link_down_rc
= linkdnrc
;
8673 dev_warn_ratelimited(adapter
->pdev_dev
,
8674 "Port %d link down, reason: %s\n",
8676 t4_link_down_rc_str(linkdnrc
));
8678 lc
->link_ok
= link_ok
;
8683 lc
->lpacaps
= lpacaps
;
8684 lc
->acaps
= acaps
& ADVERT_MASK
;
8686 /* If we're not physically capable of Auto-Negotiation, note
8687 * this as Auto-Negotiation disabled. Otherwise, we track
8688 * what Auto-Negotiation settings we have. Note parallel
8689 * structure in t4_link_l1cfg_core() and init_link_config().
8691 if (!(lc
->acaps
& FW_PORT_CAP32_ANEG
)) {
8692 lc
->autoneg
= AUTONEG_DISABLE
;
8693 } else if (lc
->acaps
& FW_PORT_CAP32_ANEG
) {
8694 lc
->autoneg
= AUTONEG_ENABLE
;
8696 /* When Autoneg is disabled, user needs to set
8698 * Similar to cxgb4_ethtool.c: set_link_ksettings
8701 lc
->speed_caps
= fwcap_to_fwspeed(acaps
);
8702 lc
->autoneg
= AUTONEG_DISABLE
;
8705 t4_os_link_changed(adapter
, pi
->port_id
, link_ok
);
8708 /* If we have a new Transceiver Module and the OS-dependent code has
8709 * told us that it wants us to redo whatever "sticky" L1 Configuration
8710 * Link Parameters are set, do that now.
8712 if (lc
->new_module
&& lc
->redo_l1cfg
) {
8713 struct link_config old_lc
;
8716 /* Save the current L1 Configuration and restore it if an
8717 * error occurs. We probably should fix the l1_cfg*()
8718 * routines not to change the link_config when an error
8722 ret
= t4_link_l1cfg_ns(adapter
, adapter
->mbox
, pi
->lport
, lc
);
8725 dev_warn(adapter
->pdev_dev
,
8726 "Attempt to update new Transceiver Module settings failed\n");
8729 lc
->new_module
= false;
8730 lc
->redo_l1cfg
= false;
8734 * t4_update_port_info - retrieve and update port information if changed
8735 * @pi: the port_info
8737 * We issue a Get Port Information Command to the Firmware and, if
8738 * successful, we check to see if anything is different from what we
8739 * last recorded and update things accordingly.
8741 int t4_update_port_info(struct port_info
*pi
)
8743 unsigned int fw_caps
= pi
->adapter
->params
.fw_caps_support
;
8744 struct fw_port_cmd port_cmd
;
8747 memset(&port_cmd
, 0, sizeof(port_cmd
));
8748 port_cmd
.op_to_portid
= cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD
) |
8749 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
8750 FW_PORT_CMD_PORTID_V(pi
->tx_chan
));
8751 port_cmd
.action_to_len16
= cpu_to_be32(
8752 FW_PORT_CMD_ACTION_V(fw_caps
== FW_CAPS16
8753 ? FW_PORT_ACTION_GET_PORT_INFO
8754 : FW_PORT_ACTION_GET_PORT_INFO32
) |
8755 FW_LEN16(port_cmd
));
8756 ret
= t4_wr_mbox(pi
->adapter
, pi
->adapter
->mbox
,
8757 &port_cmd
, sizeof(port_cmd
), &port_cmd
);
8761 t4_handle_get_port_info(pi
, (__be64
*)&port_cmd
);
8766 * t4_get_link_params - retrieve basic link parameters for given port
8768 * @link_okp: value return pointer for link up/down
8769 * @speedp: value return pointer for speed (Mb/s)
8770 * @mtup: value return pointer for mtu
8772 * Retrieves basic link parameters for a port: link up/down, speed (Mb/s),
8773 * and MTU for a specified port. A negative error is returned on
8774 * failure; 0 on success.
8776 int t4_get_link_params(struct port_info
*pi
, unsigned int *link_okp
,
8777 unsigned int *speedp
, unsigned int *mtup
)
8779 unsigned int fw_caps
= pi
->adapter
->params
.fw_caps_support
;
8780 unsigned int action
, link_ok
, mtu
;
8781 struct fw_port_cmd port_cmd
;
8782 fw_port_cap32_t linkattr
;
8785 memset(&port_cmd
, 0, sizeof(port_cmd
));
8786 port_cmd
.op_to_portid
= cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD
) |
8787 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
8788 FW_PORT_CMD_PORTID_V(pi
->tx_chan
));
8789 action
= (fw_caps
== FW_CAPS16
8790 ? FW_PORT_ACTION_GET_PORT_INFO
8791 : FW_PORT_ACTION_GET_PORT_INFO32
);
8792 port_cmd
.action_to_len16
= cpu_to_be32(
8793 FW_PORT_CMD_ACTION_V(action
) |
8794 FW_LEN16(port_cmd
));
8795 ret
= t4_wr_mbox(pi
->adapter
, pi
->adapter
->mbox
,
8796 &port_cmd
, sizeof(port_cmd
), &port_cmd
);
8800 if (action
== FW_PORT_ACTION_GET_PORT_INFO
) {
8801 u32 lstatus
= be32_to_cpu(port_cmd
.u
.info
.lstatus_to_modtype
);
8803 link_ok
= !!(lstatus
& FW_PORT_CMD_LSTATUS_F
);
8804 linkattr
= lstatus_to_fwcap(lstatus
);
8805 mtu
= be16_to_cpu(port_cmd
.u
.info
.mtu
);
8808 be32_to_cpu(port_cmd
.u
.info32
.lstatus32_to_cbllen32
);
8810 link_ok
= !!(lstatus32
& FW_PORT_CMD_LSTATUS32_F
);
8811 linkattr
= be32_to_cpu(port_cmd
.u
.info32
.linkattr32
);
8812 mtu
= FW_PORT_CMD_MTU32_G(
8813 be32_to_cpu(port_cmd
.u
.info32
.auxlinfo32_mtu32
));
8817 *link_okp
= link_ok
;
8819 *speedp
= fwcap_to_speed(linkattr
);
8827 * t4_handle_fw_rpl - process a FW reply message
8828 * @adap: the adapter
8829 * @rpl: start of the FW message
8831 * Processes a FW message, such as link state change messages.
8833 int t4_handle_fw_rpl(struct adapter
*adap
, const __be64
*rpl
)
8835 u8 opcode
= *(const u8
*)rpl
;
8837 /* This might be a port command ... this simplifies the following
8838 * conditionals ... We can get away with pre-dereferencing
8839 * action_to_len16 because it's in the first 16 bytes and all messages
8840 * will be at least that long.
8842 const struct fw_port_cmd
*p
= (const void *)rpl
;
8843 unsigned int action
=
8844 FW_PORT_CMD_ACTION_G(be32_to_cpu(p
->action_to_len16
));
8846 if (opcode
== FW_PORT_CMD
&&
8847 (action
== FW_PORT_ACTION_GET_PORT_INFO
||
8848 action
== FW_PORT_ACTION_GET_PORT_INFO32
)) {
8850 int chan
= FW_PORT_CMD_PORTID_G(be32_to_cpu(p
->op_to_portid
));
8851 struct port_info
*pi
= NULL
;
8853 for_each_port(adap
, i
) {
8854 pi
= adap2pinfo(adap
, i
);
8855 if (pi
->tx_chan
== chan
)
8859 t4_handle_get_port_info(pi
, rpl
);
8861 dev_warn(adap
->pdev_dev
, "Unknown firmware reply %d\n",
8868 static void get_pci_mode(struct adapter
*adapter
, struct pci_params
*p
)
8872 if (pci_is_pcie(adapter
->pdev
)) {
8873 pcie_capability_read_word(adapter
->pdev
, PCI_EXP_LNKSTA
, &val
);
8874 p
->speed
= val
& PCI_EXP_LNKSTA_CLS
;
8875 p
->width
= (val
& PCI_EXP_LNKSTA_NLW
) >> 4;
8880 * init_link_config - initialize a link's SW state
8881 * @lc: pointer to structure holding the link state
8882 * @pcaps: link Port Capabilities
8883 * @acaps: link current Advertised Port Capabilities
8885 * Initializes the SW state maintained for each link, including the link's
8886 * capabilities and default speed/flow-control/autonegotiation settings.
8888 static void init_link_config(struct link_config
*lc
, fw_port_cap32_t pcaps
,
8889 fw_port_cap32_t acaps
)
8892 lc
->def_acaps
= acaps
;
8896 lc
->requested_fc
= lc
->fc
= PAUSE_RX
| PAUSE_TX
;
8898 /* For Forward Error Control, we default to whatever the Firmware
8899 * tells us the Link is currently advertising.
8901 lc
->requested_fec
= FEC_AUTO
;
8902 lc
->fec
= fwcap_to_cc_fec(lc
->def_acaps
);
8904 /* If the Port is capable of Auto-Negtotiation, initialize it as
8905 * "enabled" and copy over all of the Physical Port Capabilities
8906 * to the Advertised Port Capabilities. Otherwise mark it as
8907 * Auto-Negotiate disabled and select the highest supported speed
8908 * for the link. Note parallel structure in t4_link_l1cfg_core()
8909 * and t4_handle_get_port_info().
8911 if (lc
->pcaps
& FW_PORT_CAP32_ANEG
) {
8912 lc
->acaps
= lc
->pcaps
& ADVERT_MASK
;
8913 lc
->autoneg
= AUTONEG_ENABLE
;
8914 lc
->requested_fc
|= PAUSE_AUTONEG
;
8917 lc
->autoneg
= AUTONEG_DISABLE
;
8918 lc
->speed_caps
= fwcap_to_fwspeed(acaps
);
8922 #define CIM_PF_NOACCESS 0xeeeeeeee
8924 int t4_wait_dev_ready(void __iomem
*regs
)
8928 whoami
= readl(regs
+ PL_WHOAMI_A
);
8929 if (whoami
!= 0xffffffff && whoami
!= CIM_PF_NOACCESS
)
8933 whoami
= readl(regs
+ PL_WHOAMI_A
);
8934 return (whoami
!= 0xffffffff && whoami
!= CIM_PF_NOACCESS
? 0 : -EIO
);
8938 u32 vendor_and_model_id
;
8942 static int t4_get_flash_params(struct adapter
*adap
)
8944 /* Table for non-Numonix supported flash parts. Numonix parts are left
8945 * to the preexisting code. All flash parts have 64KB sectors.
8947 static struct flash_desc supported_flash
[] = {
8948 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
8951 unsigned int part
, manufacturer
;
8952 unsigned int density
, size
= 0;
8956 /* Issue a Read ID Command to the Flash part. We decode supported
8957 * Flash parts and their sizes from this. There's a newer Query
8958 * Command which can retrieve detailed geometry information but many
8959 * Flash parts don't support it.
8962 ret
= sf1_write(adap
, 1, 1, 0, SF_RD_ID
);
8964 ret
= sf1_read(adap
, 3, 0, 1, &flashid
);
8965 t4_write_reg(adap
, SF_OP_A
, 0); /* unlock SF */
8969 /* Check to see if it's one of our non-standard supported Flash parts.
8971 for (part
= 0; part
< ARRAY_SIZE(supported_flash
); part
++)
8972 if (supported_flash
[part
].vendor_and_model_id
== flashid
) {
8973 adap
->params
.sf_size
= supported_flash
[part
].size_mb
;
8974 adap
->params
.sf_nsec
=
8975 adap
->params
.sf_size
/ SF_SEC_SIZE
;
8979 /* Decode Flash part size. The code below looks repetitive with
8980 * common encodings, but that's not guaranteed in the JEDEC
8981 * specification for the Read JEDEC ID command. The only thing that
8982 * we're guaranteed by the JEDEC specification is where the
8983 * Manufacturer ID is in the returned result. After that each
8984 * Manufacturer ~could~ encode things completely differently.
8985 * Note, all Flash parts must have 64KB sectors.
8987 manufacturer
= flashid
& 0xff;
8988 switch (manufacturer
) {
8989 case 0x20: { /* Micron/Numonix */
8990 /* This Density -> Size decoding table is taken from Micron
8993 density
= (flashid
>> 16) & 0xff;
8995 case 0x14: /* 1MB */
8998 case 0x15: /* 2MB */
9001 case 0x16: /* 4MB */
9004 case 0x17: /* 8MB */
9007 case 0x18: /* 16MB */
9010 case 0x19: /* 32MB */
9013 case 0x20: /* 64MB */
9016 case 0x21: /* 128MB */
9019 case 0x22: /* 256MB */
9025 case 0x9d: { /* ISSI -- Integrated Silicon Solution, Inc. */
9026 /* This Density -> Size decoding table is taken from ISSI
9029 density
= (flashid
>> 16) & 0xff;
9031 case 0x16: /* 32 MB */
9034 case 0x17: /* 64MB */
9040 case 0xc2: { /* Macronix */
9041 /* This Density -> Size decoding table is taken from Macronix
9044 density
= (flashid
>> 16) & 0xff;
9046 case 0x17: /* 8MB */
9049 case 0x18: /* 16MB */
9055 case 0xef: { /* Winbond */
9056 /* This Density -> Size decoding table is taken from Winbond
9059 density
= (flashid
>> 16) & 0xff;
9061 case 0x17: /* 8MB */
9064 case 0x18: /* 16MB */
9072 /* If we didn't recognize the FLASH part, that's no real issue: the
9073 * Hardware/Software contract says that Hardware will _*ALWAYS*_
9074 * use a FLASH part which is at least 4MB in size and has 64KB
9075 * sectors. The unrecognized FLASH part is likely to be much larger
9076 * than 4MB, but that's all we really need.
9079 dev_warn(adap
->pdev_dev
, "Unknown Flash Part, ID = %#x, assuming 4MB\n",
9084 /* Store decoded Flash size and fall through into vetting code. */
9085 adap
->params
.sf_size
= size
;
9086 adap
->params
.sf_nsec
= size
/ SF_SEC_SIZE
;
9089 if (adap
->params
.sf_size
< FLASH_MIN_SIZE
)
9090 dev_warn(adap
->pdev_dev
, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
9091 flashid
, adap
->params
.sf_size
, FLASH_MIN_SIZE
);
9096 * t4_prep_adapter - prepare SW and HW for operation
9097 * @adapter: the adapter
9098 * @reset: if true perform a HW reset
9100 * Initialize adapter SW state for the various HW modules, set initial
9101 * values for some adapter tunables, take PHYs out of reset, and
9102 * initialize the MDIO interface.
9104 int t4_prep_adapter(struct adapter
*adapter
)
9110 get_pci_mode(adapter
, &adapter
->params
.pci
);
9111 pl_rev
= REV_G(t4_read_reg(adapter
, PL_REV_A
));
9113 ret
= t4_get_flash_params(adapter
);
9115 dev_err(adapter
->pdev_dev
, "error %d identifying flash\n", ret
);
9119 /* Retrieve adapter's device ID
9121 pci_read_config_word(adapter
->pdev
, PCI_DEVICE_ID
, &device_id
);
9122 ver
= device_id
>> 12;
9123 adapter
->params
.chip
= 0;
9126 adapter
->params
.chip
|= CHELSIO_CHIP_CODE(CHELSIO_T4
, pl_rev
);
9127 adapter
->params
.arch
.sge_fl_db
= DBPRIO_F
;
9128 adapter
->params
.arch
.mps_tcam_size
=
9129 NUM_MPS_CLS_SRAM_L_INSTANCES
;
9130 adapter
->params
.arch
.mps_rplc_size
= 128;
9131 adapter
->params
.arch
.nchan
= NCHAN
;
9132 adapter
->params
.arch
.pm_stats_cnt
= PM_NSTATS
;
9133 adapter
->params
.arch
.vfcount
= 128;
9134 /* Congestion map is for 4 channels so that
9135 * MPS can have 4 priority per port.
9137 adapter
->params
.arch
.cng_ch_bits_log
= 2;
9140 adapter
->params
.chip
|= CHELSIO_CHIP_CODE(CHELSIO_T5
, pl_rev
);
9141 adapter
->params
.arch
.sge_fl_db
= DBPRIO_F
| DBTYPE_F
;
9142 adapter
->params
.arch
.mps_tcam_size
=
9143 NUM_MPS_T5_CLS_SRAM_L_INSTANCES
;
9144 adapter
->params
.arch
.mps_rplc_size
= 128;
9145 adapter
->params
.arch
.nchan
= NCHAN
;
9146 adapter
->params
.arch
.pm_stats_cnt
= PM_NSTATS
;
9147 adapter
->params
.arch
.vfcount
= 128;
9148 adapter
->params
.arch
.cng_ch_bits_log
= 2;
9151 adapter
->params
.chip
|= CHELSIO_CHIP_CODE(CHELSIO_T6
, pl_rev
);
9152 adapter
->params
.arch
.sge_fl_db
= 0;
9153 adapter
->params
.arch
.mps_tcam_size
=
9154 NUM_MPS_T5_CLS_SRAM_L_INSTANCES
;
9155 adapter
->params
.arch
.mps_rplc_size
= 256;
9156 adapter
->params
.arch
.nchan
= 2;
9157 adapter
->params
.arch
.pm_stats_cnt
= T6_PM_NSTATS
;
9158 adapter
->params
.arch
.vfcount
= 256;
9159 /* Congestion map will be for 2 channels so that
9160 * MPS can have 8 priority per port.
9162 adapter
->params
.arch
.cng_ch_bits_log
= 3;
9165 dev_err(adapter
->pdev_dev
, "Device %d is not supported\n",
9170 adapter
->params
.cim_la_size
= CIMLA_SIZE
;
9171 init_cong_ctrl(adapter
->params
.a_wnd
, adapter
->params
.b_wnd
);
9174 * Default port for debugging in case we can't reach FW.
9176 adapter
->params
.nports
= 1;
9177 adapter
->params
.portvec
= 1;
9178 adapter
->params
.vpd
.cclk
= 50000;
9180 /* Set PCIe completion timeout to 4 seconds. */
9181 pcie_capability_clear_and_set_word(adapter
->pdev
, PCI_EXP_DEVCTL2
,
9182 PCI_EXP_DEVCTL2_COMP_TIMEOUT
, 0xd);
9187 * t4_shutdown_adapter - shut down adapter, host & wire
9188 * @adapter: the adapter
9190 * Perform an emergency shutdown of the adapter and stop it from
9191 * continuing any further communication on the ports or DMA to the
9192 * host. This is typically used when the adapter and/or firmware
9193 * have crashed and we want to prevent any further accidental
9194 * communication with the rest of the world. This will also force
9195 * the port Link Status to go down -- if register writes work --
9196 * which should help our peers figure out that we're down.
9198 int t4_shutdown_adapter(struct adapter
*adapter
)
9202 t4_intr_disable(adapter
);
9203 t4_write_reg(adapter
, DBG_GPIO_EN_A
, 0);
9204 for_each_port(adapter
, port
) {
9205 u32 a_port_cfg
= is_t4(adapter
->params
.chip
) ?
9206 PORT_REG(port
, XGMAC_PORT_CFG_A
) :
9207 T5_PORT_REG(port
, MAC_PORT_CFG_A
);
9209 t4_write_reg(adapter
, a_port_cfg
,
9210 t4_read_reg(adapter
, a_port_cfg
)
9211 & ~SIGNAL_DET_V(1));
9213 t4_set_reg_field(adapter
, SGE_CONTROL_A
, GLOBALENABLE_F
, 0);
9219 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
9220 * @adapter: the adapter
9221 * @qid: the Queue ID
9222 * @qtype: the Ingress or Egress type for @qid
9223 * @user: true if this request is for a user mode queue
9224 * @pbar2_qoffset: BAR2 Queue Offset
9225 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
9227 * Returns the BAR2 SGE Queue Registers information associated with the
9228 * indicated Absolute Queue ID. These are passed back in return value
9229 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
9230 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
9232 * This may return an error which indicates that BAR2 SGE Queue
9233 * registers aren't available. If an error is not returned, then the
9234 * following values are returned:
9236 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
9237 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
9239 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
9240 * require the "Inferred Queue ID" ability may be used. E.g. the
9241 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
9242 * then these "Inferred Queue ID" register may not be used.
9244 int t4_bar2_sge_qregs(struct adapter
*adapter
,
9246 enum t4_bar2_qtype qtype
,
9249 unsigned int *pbar2_qid
)
9251 unsigned int page_shift
, page_size
, qpp_shift
, qpp_mask
;
9252 u64 bar2_page_offset
, bar2_qoffset
;
9253 unsigned int bar2_qid
, bar2_qid_offset
, bar2_qinferred
;
9255 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
9256 if (!user
&& is_t4(adapter
->params
.chip
))
9259 /* Get our SGE Page Size parameters.
9261 page_shift
= adapter
->params
.sge
.hps
+ 10;
9262 page_size
= 1 << page_shift
;
9264 /* Get the right Queues per Page parameters for our Queue.
9266 qpp_shift
= (qtype
== T4_BAR2_QTYPE_EGRESS
9267 ? adapter
->params
.sge
.eq_qpp
9268 : adapter
->params
.sge
.iq_qpp
);
9269 qpp_mask
= (1 << qpp_shift
) - 1;
9271 /* Calculate the basics of the BAR2 SGE Queue register area:
9272 * o The BAR2 page the Queue registers will be in.
9273 * o The BAR2 Queue ID.
9274 * o The BAR2 Queue ID Offset into the BAR2 page.
9276 bar2_page_offset
= ((u64
)(qid
>> qpp_shift
) << page_shift
);
9277 bar2_qid
= qid
& qpp_mask
;
9278 bar2_qid_offset
= bar2_qid
* SGE_UDB_SIZE
;
9280 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
9281 * hardware will infer the Absolute Queue ID simply from the writes to
9282 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
9283 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
9284 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
9285 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
9286 * from the BAR2 Page and BAR2 Queue ID.
9288 * One important censequence of this is that some BAR2 SGE registers
9289 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
9290 * there. But other registers synthesize the SGE Queue ID purely
9291 * from the writes to the registers -- the Write Combined Doorbell
9292 * Buffer is a good example. These BAR2 SGE Registers are only
9293 * available for those BAR2 SGE Register areas where the SGE Absolute
9294 * Queue ID can be inferred from simple writes.
9296 bar2_qoffset
= bar2_page_offset
;
9297 bar2_qinferred
= (bar2_qid_offset
< page_size
);
9298 if (bar2_qinferred
) {
9299 bar2_qoffset
+= bar2_qid_offset
;
9303 *pbar2_qoffset
= bar2_qoffset
;
9304 *pbar2_qid
= bar2_qid
;
9309 * t4_init_devlog_params - initialize adapter->params.devlog
9310 * @adap: the adapter
9312 * Initialize various fields of the adapter's Firmware Device Log
9313 * Parameters structure.
9315 int t4_init_devlog_params(struct adapter
*adap
)
9317 struct devlog_params
*dparams
= &adap
->params
.devlog
;
9319 unsigned int devlog_meminfo
;
9320 struct fw_devlog_cmd devlog_cmd
;
9323 /* If we're dealing with newer firmware, the Device Log Parameters
9324 * are stored in a designated register which allows us to access the
9325 * Device Log even if we can't talk to the firmware.
9328 t4_read_reg(adap
, PCIE_FW_REG(PCIE_FW_PF_A
, PCIE_FW_PF_DEVLOG
));
9330 unsigned int nentries
, nentries128
;
9332 dparams
->memtype
= PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams
);
9333 dparams
->start
= PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams
) << 4;
9335 nentries128
= PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams
);
9336 nentries
= (nentries128
+ 1) * 128;
9337 dparams
->size
= nentries
* sizeof(struct fw_devlog_e
);
9342 /* Otherwise, ask the firmware for it's Device Log Parameters.
9344 memset(&devlog_cmd
, 0, sizeof(devlog_cmd
));
9345 devlog_cmd
.op_to_write
= cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD
) |
9346 FW_CMD_REQUEST_F
| FW_CMD_READ_F
);
9347 devlog_cmd
.retval_len16
= cpu_to_be32(FW_LEN16(devlog_cmd
));
9348 ret
= t4_wr_mbox(adap
, adap
->mbox
, &devlog_cmd
, sizeof(devlog_cmd
),
9354 be32_to_cpu(devlog_cmd
.memtype_devlog_memaddr16_devlog
);
9355 dparams
->memtype
= FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo
);
9356 dparams
->start
= FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo
) << 4;
9357 dparams
->size
= be32_to_cpu(devlog_cmd
.memsize_devlog
);
9363 * t4_init_sge_params - initialize adap->params.sge
9364 * @adapter: the adapter
9366 * Initialize various fields of the adapter's SGE Parameters structure.
9368 int t4_init_sge_params(struct adapter
*adapter
)
9370 struct sge_params
*sge_params
= &adapter
->params
.sge
;
9372 unsigned int s_hps
, s_qpp
;
9374 /* Extract the SGE Page Size for our PF.
9376 hps
= t4_read_reg(adapter
, SGE_HOST_PAGE_SIZE_A
);
9377 s_hps
= (HOSTPAGESIZEPF0_S
+
9378 (HOSTPAGESIZEPF1_S
- HOSTPAGESIZEPF0_S
) * adapter
->pf
);
9379 sge_params
->hps
= ((hps
>> s_hps
) & HOSTPAGESIZEPF0_M
);
9381 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
9383 s_qpp
= (QUEUESPERPAGEPF0_S
+
9384 (QUEUESPERPAGEPF1_S
- QUEUESPERPAGEPF0_S
) * adapter
->pf
);
9385 qpp
= t4_read_reg(adapter
, SGE_EGRESS_QUEUES_PER_PAGE_PF_A
);
9386 sge_params
->eq_qpp
= ((qpp
>> s_qpp
) & QUEUESPERPAGEPF0_M
);
9387 qpp
= t4_read_reg(adapter
, SGE_INGRESS_QUEUES_PER_PAGE_PF_A
);
9388 sge_params
->iq_qpp
= ((qpp
>> s_qpp
) & QUEUESPERPAGEPF0_M
);
9394 * t4_init_tp_params - initialize adap->params.tp
9395 * @adap: the adapter
9396 * @sleep_ok: if true we may sleep while awaiting command completion
9398 * Initialize various fields of the adapter's TP Parameters structure.
9400 int t4_init_tp_params(struct adapter
*adap
, bool sleep_ok
)
9406 v
= t4_read_reg(adap
, TP_TIMER_RESOLUTION_A
);
9407 adap
->params
.tp
.tre
= TIMERRESOLUTION_G(v
);
9408 adap
->params
.tp
.dack_re
= DELAYEDACKRESOLUTION_G(v
);
9410 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
9411 for (chan
= 0; chan
< NCHAN
; chan
++)
9412 adap
->params
.tp
.tx_modq
[chan
] = chan
;
9414 /* Cache the adapter's Compressed Filter Mode/Mask and global Ingress
9417 param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
9418 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FILTER
) |
9419 FW_PARAMS_PARAM_Y_V(FW_PARAM_DEV_FILTER_MODE_MASK
));
9421 /* Read current value */
9422 ret
= t4_query_params(adap
, adap
->mbox
, adap
->pf
, 0, 1,
9425 dev_info(adap
->pdev_dev
,
9426 "Current filter mode/mask 0x%x:0x%x\n",
9427 FW_PARAMS_PARAM_FILTER_MODE_G(val
),
9428 FW_PARAMS_PARAM_FILTER_MASK_G(val
));
9429 adap
->params
.tp
.vlan_pri_map
=
9430 FW_PARAMS_PARAM_FILTER_MODE_G(val
);
9431 adap
->params
.tp
.filter_mask
=
9432 FW_PARAMS_PARAM_FILTER_MASK_G(val
);
9434 dev_info(adap
->pdev_dev
,
9435 "Failed to read filter mode/mask via fw api, using indirect-reg-read\n");
9437 /* Incase of older-fw (which doesn't expose the api
9438 * FW_PARAM_DEV_FILTER_MODE_MASK) and newer-driver (which uses
9439 * the fw api) combination, fall-back to older method of reading
9440 * the filter mode from indirect-register
9442 t4_tp_pio_read(adap
, &adap
->params
.tp
.vlan_pri_map
, 1,
9443 TP_VLAN_PRI_MAP_A
, sleep_ok
);
9445 /* With the older-fw and newer-driver combination we might run
9446 * into an issue when user wants to use hash filter region but
9447 * the filter_mask is zero, in this case filter_mask validation
9448 * is tough. To avoid that we set the filter_mask same as filter
9449 * mode, which will behave exactly as the older way of ignoring
9450 * the filter mask validation.
9452 adap
->params
.tp
.filter_mask
= adap
->params
.tp
.vlan_pri_map
;
9455 t4_tp_pio_read(adap
, &adap
->params
.tp
.ingress_config
, 1,
9456 TP_INGRESS_CONFIG_A
, sleep_ok
);
9458 /* For T6, cache the adapter's compressed error vector
9459 * and passing outer header info for encapsulated packets.
9461 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) > CHELSIO_T5
) {
9462 v
= t4_read_reg(adap
, TP_OUT_CONFIG_A
);
9463 adap
->params
.tp
.rx_pkt_encap
= (v
& CRXPKTENC_F
) ? 1 : 0;
9466 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
9467 * shift positions of several elements of the Compressed Filter Tuple
9468 * for this adapter which we need frequently ...
9470 adap
->params
.tp
.fcoe_shift
= t4_filter_field_shift(adap
, FCOE_F
);
9471 adap
->params
.tp
.port_shift
= t4_filter_field_shift(adap
, PORT_F
);
9472 adap
->params
.tp
.vnic_shift
= t4_filter_field_shift(adap
, VNIC_ID_F
);
9473 adap
->params
.tp
.vlan_shift
= t4_filter_field_shift(adap
, VLAN_F
);
9474 adap
->params
.tp
.tos_shift
= t4_filter_field_shift(adap
, TOS_F
);
9475 adap
->params
.tp
.protocol_shift
= t4_filter_field_shift(adap
,
9477 adap
->params
.tp
.ethertype_shift
= t4_filter_field_shift(adap
,
9479 adap
->params
.tp
.macmatch_shift
= t4_filter_field_shift(adap
,
9481 adap
->params
.tp
.matchtype_shift
= t4_filter_field_shift(adap
,
9483 adap
->params
.tp
.frag_shift
= t4_filter_field_shift(adap
,
9486 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
9487 * represents the presence of an Outer VLAN instead of a VNIC ID.
9489 if ((adap
->params
.tp
.ingress_config
& VNIC_F
) == 0)
9490 adap
->params
.tp
.vnic_shift
= -1;
9492 v
= t4_read_reg(adap
, LE_3_DB_HASH_MASK_GEN_IPV4_T6_A
);
9493 adap
->params
.tp
.hash_filter_mask
= v
;
9494 v
= t4_read_reg(adap
, LE_4_DB_HASH_MASK_GEN_IPV4_T6_A
);
9495 adap
->params
.tp
.hash_filter_mask
|= ((u64
)v
<< 32);
9500 * t4_filter_field_shift - calculate filter field shift
9501 * @adap: the adapter
9502 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
9504 * Return the shift position of a filter field within the Compressed
9505 * Filter Tuple. The filter field is specified via its selection bit
9506 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
9508 int t4_filter_field_shift(const struct adapter
*adap
, int filter_sel
)
9510 unsigned int filter_mode
= adap
->params
.tp
.vlan_pri_map
;
9514 if ((filter_mode
& filter_sel
) == 0)
9517 for (sel
= 1, field_shift
= 0; sel
< filter_sel
; sel
<<= 1) {
9518 switch (filter_mode
& sel
) {
9520 field_shift
+= FT_FCOE_W
;
9523 field_shift
+= FT_PORT_W
;
9526 field_shift
+= FT_VNIC_ID_W
;
9529 field_shift
+= FT_VLAN_W
;
9532 field_shift
+= FT_TOS_W
;
9535 field_shift
+= FT_PROTOCOL_W
;
9538 field_shift
+= FT_ETHERTYPE_W
;
9541 field_shift
+= FT_MACMATCH_W
;
9544 field_shift
+= FT_MPSHITTYPE_W
;
9546 case FRAGMENTATION_F
:
9547 field_shift
+= FT_FRAGMENTATION_W
;
9554 int t4_init_rss_mode(struct adapter
*adap
, int mbox
)
9557 struct fw_rss_vi_config_cmd rvc
;
9559 memset(&rvc
, 0, sizeof(rvc
));
9561 for_each_port(adap
, i
) {
9562 struct port_info
*p
= adap2pinfo(adap
, i
);
9565 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD
) |
9566 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
9567 FW_RSS_VI_CONFIG_CMD_VIID_V(p
->viid
));
9568 rvc
.retval_len16
= cpu_to_be32(FW_LEN16(rvc
));
9569 ret
= t4_wr_mbox(adap
, mbox
, &rvc
, sizeof(rvc
), &rvc
);
9572 p
->rss_mode
= be32_to_cpu(rvc
.u
.basicvirtual
.defaultq_to_udpen
);
9578 * t4_init_portinfo - allocate a virtual interface and initialize port_info
9579 * @pi: the port_info
9580 * @mbox: mailbox to use for the FW command
9581 * @port: physical port associated with the VI
9582 * @pf: the PF owning the VI
9583 * @vf: the VF owning the VI
9584 * @mac: the MAC address of the VI
9586 * Allocates a virtual interface for the given physical port. If @mac is
9587 * not %NULL it contains the MAC address of the VI as assigned by FW.
9588 * @mac should be large enough to hold an Ethernet address.
9589 * Returns < 0 on error.
9591 int t4_init_portinfo(struct port_info
*pi
, int mbox
,
9592 int port
, int pf
, int vf
, u8 mac
[])
9594 struct adapter
*adapter
= pi
->adapter
;
9595 unsigned int fw_caps
= adapter
->params
.fw_caps_support
;
9596 struct fw_port_cmd cmd
;
9597 unsigned int rss_size
;
9598 enum fw_port_type port_type
;
9600 fw_port_cap32_t pcaps
, acaps
;
9601 u8 vivld
= 0, vin
= 0;
9604 /* If we haven't yet determined whether we're talking to Firmware
9605 * which knows the new 32-bit Port Capabilities, it's time to find
9606 * out now. This will also tell new Firmware to send us Port Status
9607 * Updates using the new 32-bit Port Capabilities version of the
9608 * Port Information message.
9610 if (fw_caps
== FW_CAPS_UNKNOWN
) {
9613 param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF
) |
9614 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_PORT_CAPS32
));
9616 ret
= t4_set_params(adapter
, mbox
, pf
, vf
, 1, ¶m
, &val
);
9617 fw_caps
= (ret
== 0 ? FW_CAPS32
: FW_CAPS16
);
9618 adapter
->params
.fw_caps_support
= fw_caps
;
9621 memset(&cmd
, 0, sizeof(cmd
));
9622 cmd
.op_to_portid
= cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD
) |
9623 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
9624 FW_PORT_CMD_PORTID_V(port
));
9625 cmd
.action_to_len16
= cpu_to_be32(
9626 FW_PORT_CMD_ACTION_V(fw_caps
== FW_CAPS16
9627 ? FW_PORT_ACTION_GET_PORT_INFO
9628 : FW_PORT_ACTION_GET_PORT_INFO32
) |
9630 ret
= t4_wr_mbox(pi
->adapter
, mbox
, &cmd
, sizeof(cmd
), &cmd
);
9634 /* Extract the various fields from the Port Information message.
9636 if (fw_caps
== FW_CAPS16
) {
9637 u32 lstatus
= be32_to_cpu(cmd
.u
.info
.lstatus_to_modtype
);
9639 port_type
= FW_PORT_CMD_PTYPE_G(lstatus
);
9640 mdio_addr
= ((lstatus
& FW_PORT_CMD_MDIOCAP_F
)
9641 ? FW_PORT_CMD_MDIOADDR_G(lstatus
)
9643 pcaps
= fwcaps16_to_caps32(be16_to_cpu(cmd
.u
.info
.pcap
));
9644 acaps
= fwcaps16_to_caps32(be16_to_cpu(cmd
.u
.info
.acap
));
9646 u32 lstatus32
= be32_to_cpu(cmd
.u
.info32
.lstatus32_to_cbllen32
);
9648 port_type
= FW_PORT_CMD_PORTTYPE32_G(lstatus32
);
9649 mdio_addr
= ((lstatus32
& FW_PORT_CMD_MDIOCAP32_F
)
9650 ? FW_PORT_CMD_MDIOADDR32_G(lstatus32
)
9652 pcaps
= be32_to_cpu(cmd
.u
.info32
.pcaps32
);
9653 acaps
= be32_to_cpu(cmd
.u
.info32
.acaps32
);
9656 ret
= t4_alloc_vi(pi
->adapter
, mbox
, port
, pf
, vf
, 1, mac
, &rss_size
,
9664 pi
->rss_size
= rss_size
;
9665 pi
->rx_cchan
= t4_get_tp_e2c_map(pi
->adapter
, port
);
9667 /* If fw supports returning the VIN as part of FW_VI_CMD,
9668 * save the returned values.
9670 if (adapter
->params
.viid_smt_extn_support
) {
9674 /* Retrieve the values from VIID */
9675 pi
->vivld
= FW_VIID_VIVLD_G(pi
->viid
);
9676 pi
->vin
= FW_VIID_VIN_G(pi
->viid
);
9679 pi
->port_type
= port_type
;
9680 pi
->mdio_addr
= mdio_addr
;
9681 pi
->mod_type
= FW_PORT_MOD_TYPE_NA
;
9683 init_link_config(&pi
->link_cfg
, pcaps
, acaps
);
9687 int t4_port_init(struct adapter
*adap
, int mbox
, int pf
, int vf
)
9692 for_each_port(adap
, i
) {
9693 struct port_info
*pi
= adap2pinfo(adap
, i
);
9695 while ((adap
->params
.portvec
& (1 << j
)) == 0)
9698 ret
= t4_init_portinfo(pi
, mbox
, j
, pf
, vf
, addr
);
9702 memcpy(adap
->port
[i
]->dev_addr
, addr
, ETH_ALEN
);
9709 * t4_read_cimq_cfg - read CIM queue configuration
9710 * @adap: the adapter
9711 * @base: holds the queue base addresses in bytes
9712 * @size: holds the queue sizes in bytes
9713 * @thres: holds the queue full thresholds in bytes
9715 * Returns the current configuration of the CIM queues, starting with
9716 * the IBQs, then the OBQs.
9718 void t4_read_cimq_cfg(struct adapter
*adap
, u16
*base
, u16
*size
, u16
*thres
)
9721 int cim_num_obq
= is_t4(adap
->params
.chip
) ?
9722 CIM_NUM_OBQ
: CIM_NUM_OBQ_T5
;
9724 for (i
= 0; i
< CIM_NUM_IBQ
; i
++) {
9725 t4_write_reg(adap
, CIM_QUEUE_CONFIG_REF_A
, IBQSELECT_F
|
9727 v
= t4_read_reg(adap
, CIM_QUEUE_CONFIG_CTRL_A
);
9728 /* value is in 256-byte units */
9729 *base
++ = CIMQBASE_G(v
) * 256;
9730 *size
++ = CIMQSIZE_G(v
) * 256;
9731 *thres
++ = QUEFULLTHRSH_G(v
) * 8; /* 8-byte unit */
9733 for (i
= 0; i
< cim_num_obq
; i
++) {
9734 t4_write_reg(adap
, CIM_QUEUE_CONFIG_REF_A
, OBQSELECT_F
|
9736 v
= t4_read_reg(adap
, CIM_QUEUE_CONFIG_CTRL_A
);
9737 /* value is in 256-byte units */
9738 *base
++ = CIMQBASE_G(v
) * 256;
9739 *size
++ = CIMQSIZE_G(v
) * 256;
9744 * t4_read_cim_ibq - read the contents of a CIM inbound queue
9745 * @adap: the adapter
9746 * @qid: the queue index
9747 * @data: where to store the queue contents
9748 * @n: capacity of @data in 32-bit words
9750 * Reads the contents of the selected CIM queue starting at address 0 up
9751 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9752 * error and the number of 32-bit words actually read on success.
9754 int t4_read_cim_ibq(struct adapter
*adap
, unsigned int qid
, u32
*data
, size_t n
)
9756 int i
, err
, attempts
;
9758 const unsigned int nwords
= CIM_IBQ_SIZE
* 4;
9760 if (qid
> 5 || (n
& 3))
9763 addr
= qid
* nwords
;
9767 /* It might take 3-10ms before the IBQ debug read access is allowed.
9768 * Wait for 1 Sec with a delay of 1 usec.
9772 for (i
= 0; i
< n
; i
++, addr
++) {
9773 t4_write_reg(adap
, CIM_IBQ_DBG_CFG_A
, IBQDBGADDR_V(addr
) |
9775 err
= t4_wait_op_done(adap
, CIM_IBQ_DBG_CFG_A
, IBQDBGBUSY_F
, 0,
9779 *data
++ = t4_read_reg(adap
, CIM_IBQ_DBG_DATA_A
);
9781 t4_write_reg(adap
, CIM_IBQ_DBG_CFG_A
, 0);
9786 * t4_read_cim_obq - read the contents of a CIM outbound queue
9787 * @adap: the adapter
9788 * @qid: the queue index
9789 * @data: where to store the queue contents
9790 * @n: capacity of @data in 32-bit words
9792 * Reads the contents of the selected CIM queue starting at address 0 up
9793 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9794 * error and the number of 32-bit words actually read on success.
9796 int t4_read_cim_obq(struct adapter
*adap
, unsigned int qid
, u32
*data
, size_t n
)
9799 unsigned int addr
, v
, nwords
;
9800 int cim_num_obq
= is_t4(adap
->params
.chip
) ?
9801 CIM_NUM_OBQ
: CIM_NUM_OBQ_T5
;
9803 if ((qid
> (cim_num_obq
- 1)) || (n
& 3))
9806 t4_write_reg(adap
, CIM_QUEUE_CONFIG_REF_A
, OBQSELECT_F
|
9807 QUENUMSELECT_V(qid
));
9808 v
= t4_read_reg(adap
, CIM_QUEUE_CONFIG_CTRL_A
);
9810 addr
= CIMQBASE_G(v
) * 64; /* muliple of 256 -> muliple of 4 */
9811 nwords
= CIMQSIZE_G(v
) * 64; /* same */
9815 for (i
= 0; i
< n
; i
++, addr
++) {
9816 t4_write_reg(adap
, CIM_OBQ_DBG_CFG_A
, OBQDBGADDR_V(addr
) |
9818 err
= t4_wait_op_done(adap
, CIM_OBQ_DBG_CFG_A
, OBQDBGBUSY_F
, 0,
9822 *data
++ = t4_read_reg(adap
, CIM_OBQ_DBG_DATA_A
);
9824 t4_write_reg(adap
, CIM_OBQ_DBG_CFG_A
, 0);
9829 * t4_cim_read - read a block from CIM internal address space
9830 * @adap: the adapter
9831 * @addr: the start address within the CIM address space
9832 * @n: number of words to read
9833 * @valp: where to store the result
9835 * Reads a block of 4-byte words from the CIM intenal address space.
9837 int t4_cim_read(struct adapter
*adap
, unsigned int addr
, unsigned int n
,
9842 if (t4_read_reg(adap
, CIM_HOST_ACC_CTRL_A
) & HOSTBUSY_F
)
9845 for ( ; !ret
&& n
--; addr
+= 4) {
9846 t4_write_reg(adap
, CIM_HOST_ACC_CTRL_A
, addr
);
9847 ret
= t4_wait_op_done(adap
, CIM_HOST_ACC_CTRL_A
, HOSTBUSY_F
,
9850 *valp
++ = t4_read_reg(adap
, CIM_HOST_ACC_DATA_A
);
9856 * t4_cim_write - write a block into CIM internal address space
9857 * @adap: the adapter
9858 * @addr: the start address within the CIM address space
9859 * @n: number of words to write
9860 * @valp: set of values to write
9862 * Writes a block of 4-byte words into the CIM intenal address space.
9864 int t4_cim_write(struct adapter
*adap
, unsigned int addr
, unsigned int n
,
9865 const unsigned int *valp
)
9869 if (t4_read_reg(adap
, CIM_HOST_ACC_CTRL_A
) & HOSTBUSY_F
)
9872 for ( ; !ret
&& n
--; addr
+= 4) {
9873 t4_write_reg(adap
, CIM_HOST_ACC_DATA_A
, *valp
++);
9874 t4_write_reg(adap
, CIM_HOST_ACC_CTRL_A
, addr
| HOSTWRITE_F
);
9875 ret
= t4_wait_op_done(adap
, CIM_HOST_ACC_CTRL_A
, HOSTBUSY_F
,
9881 static int t4_cim_write1(struct adapter
*adap
, unsigned int addr
,
9884 return t4_cim_write(adap
, addr
, 1, &val
);
9888 * t4_cim_read_la - read CIM LA capture buffer
9889 * @adap: the adapter
9890 * @la_buf: where to store the LA data
9891 * @wrptr: the HW write pointer within the capture buffer
9893 * Reads the contents of the CIM LA buffer with the most recent entry at
9894 * the end of the returned data and with the entry at @wrptr first.
9895 * We try to leave the LA in the running state we find it in.
9897 int t4_cim_read_la(struct adapter
*adap
, u32
*la_buf
, unsigned int *wrptr
)
9900 unsigned int cfg
, val
, idx
;
9902 ret
= t4_cim_read(adap
, UP_UP_DBG_LA_CFG_A
, 1, &cfg
);
9906 if (cfg
& UPDBGLAEN_F
) { /* LA is running, freeze it */
9907 ret
= t4_cim_write1(adap
, UP_UP_DBG_LA_CFG_A
, 0);
9912 ret
= t4_cim_read(adap
, UP_UP_DBG_LA_CFG_A
, 1, &val
);
9916 idx
= UPDBGLAWRPTR_G(val
);
9920 for (i
= 0; i
< adap
->params
.cim_la_size
; i
++) {
9921 ret
= t4_cim_write1(adap
, UP_UP_DBG_LA_CFG_A
,
9922 UPDBGLARDPTR_V(idx
) | UPDBGLARDEN_F
);
9925 ret
= t4_cim_read(adap
, UP_UP_DBG_LA_CFG_A
, 1, &val
);
9928 if (val
& UPDBGLARDEN_F
) {
9932 ret
= t4_cim_read(adap
, UP_UP_DBG_LA_DATA_A
, 1, &la_buf
[i
]);
9936 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9937 * identify the 32-bit portion of the full 312-bit data
9939 if (is_t6(adap
->params
.chip
) && (idx
& 0xf) >= 9)
9940 idx
= (idx
& 0xff0) + 0x10;
9943 /* address can't exceed 0xfff */
9944 idx
&= UPDBGLARDPTR_M
;
9947 if (cfg
& UPDBGLAEN_F
) {
9948 int r
= t4_cim_write1(adap
, UP_UP_DBG_LA_CFG_A
,
9949 cfg
& ~UPDBGLARDEN_F
);
9957 * t4_tp_read_la - read TP LA capture buffer
9958 * @adap: the adapter
9959 * @la_buf: where to store the LA data
9960 * @wrptr: the HW write pointer within the capture buffer
9962 * Reads the contents of the TP LA buffer with the most recent entry at
9963 * the end of the returned data and with the entry at @wrptr first.
9964 * We leave the LA in the running state we find it in.
9966 void t4_tp_read_la(struct adapter
*adap
, u64
*la_buf
, unsigned int *wrptr
)
9968 bool last_incomplete
;
9969 unsigned int i
, cfg
, val
, idx
;
9971 cfg
= t4_read_reg(adap
, TP_DBG_LA_CONFIG_A
) & 0xffff;
9972 if (cfg
& DBGLAENABLE_F
) /* freeze LA */
9973 t4_write_reg(adap
, TP_DBG_LA_CONFIG_A
,
9974 adap
->params
.tp
.la_mask
| (cfg
^ DBGLAENABLE_F
));
9976 val
= t4_read_reg(adap
, TP_DBG_LA_CONFIG_A
);
9977 idx
= DBGLAWPTR_G(val
);
9978 last_incomplete
= DBGLAMODE_G(val
) >= 2 && (val
& DBGLAWHLF_F
) == 0;
9979 if (last_incomplete
)
9980 idx
= (idx
+ 1) & DBGLARPTR_M
;
9985 val
&= ~DBGLARPTR_V(DBGLARPTR_M
);
9986 val
|= adap
->params
.tp
.la_mask
;
9988 for (i
= 0; i
< TPLA_SIZE
; i
++) {
9989 t4_write_reg(adap
, TP_DBG_LA_CONFIG_A
, DBGLARPTR_V(idx
) | val
);
9990 la_buf
[i
] = t4_read_reg64(adap
, TP_DBG_LA_DATAL_A
);
9991 idx
= (idx
+ 1) & DBGLARPTR_M
;
9994 /* Wipe out last entry if it isn't valid */
9995 if (last_incomplete
)
9996 la_buf
[TPLA_SIZE
- 1] = ~0ULL;
9998 if (cfg
& DBGLAENABLE_F
) /* restore running state */
9999 t4_write_reg(adap
, TP_DBG_LA_CONFIG_A
,
10000 cfg
| adap
->params
.tp
.la_mask
);
10003 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
10004 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
10005 * state for more than the Warning Threshold then we'll issue a warning about
10006 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
10007 * appears to be hung every Warning Repeat second till the situation clears.
10008 * If the situation clears, we'll note that as well.
10010 #define SGE_IDMA_WARN_THRESH 1
10011 #define SGE_IDMA_WARN_REPEAT 300
10014 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
10015 * @adapter: the adapter
10016 * @idma: the adapter IDMA Monitor state
10018 * Initialize the state of an SGE Ingress DMA Monitor.
10020 void t4_idma_monitor_init(struct adapter
*adapter
,
10021 struct sge_idma_monitor_state
*idma
)
10023 /* Initialize the state variables for detecting an SGE Ingress DMA
10024 * hang. The SGE has internal counters which count up on each clock
10025 * tick whenever the SGE finds its Ingress DMA State Engines in the
10026 * same state they were on the previous clock tick. The clock used is
10027 * the Core Clock so we have a limit on the maximum "time" they can
10028 * record; typically a very small number of seconds. For instance,
10029 * with a 600MHz Core Clock, we can only count up to a bit more than
10030 * 7s. So we'll synthesize a larger counter in order to not run the
10031 * risk of having the "timers" overflow and give us the flexibility to
10032 * maintain a Hung SGE State Machine of our own which operates across
10033 * a longer time frame.
10035 idma
->idma_1s_thresh
= core_ticks_per_usec(adapter
) * 1000000; /* 1s */
10036 idma
->idma_stalled
[0] = 0;
10037 idma
->idma_stalled
[1] = 0;
10041 * t4_idma_monitor - monitor SGE Ingress DMA state
10042 * @adapter: the adapter
10043 * @idma: the adapter IDMA Monitor state
10044 * @hz: number of ticks/second
10045 * @ticks: number of ticks since the last IDMA Monitor call
10047 void t4_idma_monitor(struct adapter
*adapter
,
10048 struct sge_idma_monitor_state
*idma
,
10051 int i
, idma_same_state_cnt
[2];
10053 /* Read the SGE Debug Ingress DMA Same State Count registers. These
10054 * are counters inside the SGE which count up on each clock when the
10055 * SGE finds its Ingress DMA State Engines in the same states they
10056 * were in the previous clock. The counters will peg out at
10057 * 0xffffffff without wrapping around so once they pass the 1s
10058 * threshold they'll stay above that till the IDMA state changes.
10060 t4_write_reg(adapter
, SGE_DEBUG_INDEX_A
, 13);
10061 idma_same_state_cnt
[0] = t4_read_reg(adapter
, SGE_DEBUG_DATA_HIGH_A
);
10062 idma_same_state_cnt
[1] = t4_read_reg(adapter
, SGE_DEBUG_DATA_LOW_A
);
10064 for (i
= 0; i
< 2; i
++) {
10065 u32 debug0
, debug11
;
10067 /* If the Ingress DMA Same State Counter ("timer") is less
10068 * than 1s, then we can reset our synthesized Stall Timer and
10069 * continue. If we have previously emitted warnings about a
10070 * potential stalled Ingress Queue, issue a note indicating
10071 * that the Ingress Queue has resumed forward progress.
10073 if (idma_same_state_cnt
[i
] < idma
->idma_1s_thresh
) {
10074 if (idma
->idma_stalled
[i
] >= SGE_IDMA_WARN_THRESH
* hz
)
10075 dev_warn(adapter
->pdev_dev
, "SGE idma%d, queue %u, "
10076 "resumed after %d seconds\n",
10077 i
, idma
->idma_qid
[i
],
10078 idma
->idma_stalled
[i
] / hz
);
10079 idma
->idma_stalled
[i
] = 0;
10083 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
10084 * domain. The first time we get here it'll be because we
10085 * passed the 1s Threshold; each additional time it'll be
10086 * because the RX Timer Callback is being fired on its regular
10089 * If the stall is below our Potential Hung Ingress Queue
10090 * Warning Threshold, continue.
10092 if (idma
->idma_stalled
[i
] == 0) {
10093 idma
->idma_stalled
[i
] = hz
;
10094 idma
->idma_warn
[i
] = 0;
10096 idma
->idma_stalled
[i
] += ticks
;
10097 idma
->idma_warn
[i
] -= ticks
;
10100 if (idma
->idma_stalled
[i
] < SGE_IDMA_WARN_THRESH
* hz
)
10103 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
10105 if (idma
->idma_warn
[i
] > 0)
10107 idma
->idma_warn
[i
] = SGE_IDMA_WARN_REPEAT
* hz
;
10109 /* Read and save the SGE IDMA State and Queue ID information.
10110 * We do this every time in case it changes across time ...
10111 * can't be too careful ...
10113 t4_write_reg(adapter
, SGE_DEBUG_INDEX_A
, 0);
10114 debug0
= t4_read_reg(adapter
, SGE_DEBUG_DATA_LOW_A
);
10115 idma
->idma_state
[i
] = (debug0
>> (i
* 9)) & 0x3f;
10117 t4_write_reg(adapter
, SGE_DEBUG_INDEX_A
, 11);
10118 debug11
= t4_read_reg(adapter
, SGE_DEBUG_DATA_LOW_A
);
10119 idma
->idma_qid
[i
] = (debug11
>> (i
* 16)) & 0xffff;
10121 dev_warn(adapter
->pdev_dev
, "SGE idma%u, queue %u, potentially stuck in "
10122 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
10123 i
, idma
->idma_qid
[i
], idma
->idma_state
[i
],
10124 idma
->idma_stalled
[i
] / hz
,
10126 t4_sge_decode_idma_state(adapter
, idma
->idma_state
[i
]);
10131 * t4_load_cfg - download config file
10132 * @adap: the adapter
10133 * @cfg_data: the cfg text file to write
10134 * @size: text file size
10136 * Write the supplied config text file to the card's serial flash.
10138 int t4_load_cfg(struct adapter
*adap
, const u8
*cfg_data
, unsigned int size
)
10140 int ret
, i
, n
, cfg_addr
;
10142 unsigned int flash_cfg_start_sec
;
10143 unsigned int sf_sec_size
= adap
->params
.sf_size
/ adap
->params
.sf_nsec
;
10145 cfg_addr
= t4_flash_cfg_addr(adap
);
10150 flash_cfg_start_sec
= addr
/ SF_SEC_SIZE
;
10152 if (size
> FLASH_CFG_MAX_SIZE
) {
10153 dev_err(adap
->pdev_dev
, "cfg file too large, max is %u bytes\n",
10154 FLASH_CFG_MAX_SIZE
);
10158 i
= DIV_ROUND_UP(FLASH_CFG_MAX_SIZE
, /* # of sectors spanned */
10160 ret
= t4_flash_erase_sectors(adap
, flash_cfg_start_sec
,
10161 flash_cfg_start_sec
+ i
- 1);
10162 /* If size == 0 then we're simply erasing the FLASH sectors associated
10163 * with the on-adapter Firmware Configuration File.
10165 if (ret
|| size
== 0)
10168 /* this will write to the flash up to SF_PAGE_SIZE at a time */
10169 for (i
= 0; i
< size
; i
+= SF_PAGE_SIZE
) {
10170 if ((size
- i
) < SF_PAGE_SIZE
)
10174 ret
= t4_write_flash(adap
, addr
, n
, cfg_data
);
10178 addr
+= SF_PAGE_SIZE
;
10179 cfg_data
+= SF_PAGE_SIZE
;
10184 dev_err(adap
->pdev_dev
, "config file %s failed %d\n",
10185 (size
== 0 ? "clear" : "download"), ret
);
10190 * t4_set_vf_mac - Set MAC address for the specified VF
10191 * @adapter: The adapter
10192 * @vf: one of the VFs instantiated by the specified PF
10193 * @naddr: the number of MAC addresses
10194 * @addr: the MAC address(es) to be set to the specified VF
10196 int t4_set_vf_mac_acl(struct adapter
*adapter
, unsigned int vf
,
10197 unsigned int naddr
, u8
*addr
)
10199 struct fw_acl_mac_cmd cmd
;
10201 memset(&cmd
, 0, sizeof(cmd
));
10202 cmd
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD
) |
10205 FW_ACL_MAC_CMD_PFN_V(adapter
->pf
) |
10206 FW_ACL_MAC_CMD_VFN_V(vf
));
10208 /* Note: Do not enable the ACL */
10209 cmd
.en_to_len16
= cpu_to_be32((unsigned int)FW_LEN16(cmd
));
10212 switch (adapter
->pf
) {
10214 memcpy(cmd
.macaddr3
, addr
, sizeof(cmd
.macaddr3
));
10217 memcpy(cmd
.macaddr2
, addr
, sizeof(cmd
.macaddr2
));
10220 memcpy(cmd
.macaddr1
, addr
, sizeof(cmd
.macaddr1
));
10223 memcpy(cmd
.macaddr0
, addr
, sizeof(cmd
.macaddr0
));
10227 return t4_wr_mbox(adapter
, adapter
->mbox
, &cmd
, sizeof(cmd
), &cmd
);
10231 * t4_read_pace_tbl - read the pace table
10232 * @adap: the adapter
10233 * @pace_vals: holds the returned values
10235 * Returns the values of TP's pace table in microseconds.
10237 void t4_read_pace_tbl(struct adapter
*adap
, unsigned int pace_vals
[NTX_SCHED
])
10241 for (i
= 0; i
< NTX_SCHED
; i
++) {
10242 t4_write_reg(adap
, TP_PACE_TABLE_A
, 0xffff0000 + i
);
10243 v
= t4_read_reg(adap
, TP_PACE_TABLE_A
);
10244 pace_vals
[i
] = dack_ticks_to_usec(adap
, v
);
10249 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
10250 * @adap: the adapter
10251 * @sched: the scheduler index
10252 * @kbps: the byte rate in Kbps
10253 * @ipg: the interpacket delay in tenths of nanoseconds
10254 * @sleep_ok: if true we may sleep while awaiting command completion
10256 * Return the current configuration of a HW Tx scheduler.
10258 void t4_get_tx_sched(struct adapter
*adap
, unsigned int sched
,
10259 unsigned int *kbps
, unsigned int *ipg
, bool sleep_ok
)
10261 unsigned int v
, addr
, bpt
, cpt
;
10264 addr
= TP_TX_MOD_Q1_Q0_RATE_LIMIT_A
- sched
/ 2;
10265 t4_tp_tm_pio_read(adap
, &v
, 1, addr
, sleep_ok
);
10268 bpt
= (v
>> 8) & 0xff;
10271 *kbps
= 0; /* scheduler disabled */
10273 v
= (adap
->params
.vpd
.cclk
* 1000) / cpt
; /* ticks/s */
10274 *kbps
= (v
* bpt
) / 125;
10278 addr
= TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A
- sched
/ 2;
10279 t4_tp_tm_pio_read(adap
, &v
, 1, addr
, sleep_ok
);
10283 *ipg
= (10000 * v
) / core_ticks_per_usec(adap
);
10287 /* t4_sge_ctxt_rd - read an SGE context through FW
10288 * @adap: the adapter
10289 * @mbox: mailbox to use for the FW command
10290 * @cid: the context id
10291 * @ctype: the context type
10292 * @data: where to store the context data
10294 * Issues a FW command through the given mailbox to read an SGE context.
10296 int t4_sge_ctxt_rd(struct adapter
*adap
, unsigned int mbox
, unsigned int cid
,
10297 enum ctxt_type ctype
, u32
*data
)
10299 struct fw_ldst_cmd c
;
10302 if (ctype
== CTXT_FLM
)
10303 ret
= FW_LDST_ADDRSPC_SGE_FLMC
;
10305 ret
= FW_LDST_ADDRSPC_SGE_CONMC
;
10307 memset(&c
, 0, sizeof(c
));
10308 c
.op_to_addrspace
= cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
10309 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
10310 FW_LDST_CMD_ADDRSPACE_V(ret
));
10311 c
.cycles_to_len16
= cpu_to_be32(FW_LEN16(c
));
10312 c
.u
.idctxt
.physid
= cpu_to_be32(cid
);
10314 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
10316 data
[0] = be32_to_cpu(c
.u
.idctxt
.ctxt_data0
);
10317 data
[1] = be32_to_cpu(c
.u
.idctxt
.ctxt_data1
);
10318 data
[2] = be32_to_cpu(c
.u
.idctxt
.ctxt_data2
);
10319 data
[3] = be32_to_cpu(c
.u
.idctxt
.ctxt_data3
);
10320 data
[4] = be32_to_cpu(c
.u
.idctxt
.ctxt_data4
);
10321 data
[5] = be32_to_cpu(c
.u
.idctxt
.ctxt_data5
);
10327 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
10328 * @adap: the adapter
10329 * @cid: the context id
10330 * @ctype: the context type
10331 * @data: where to store the context data
10333 * Reads an SGE context directly, bypassing FW. This is only for
10334 * debugging when FW is unavailable.
10336 int t4_sge_ctxt_rd_bd(struct adapter
*adap
, unsigned int cid
,
10337 enum ctxt_type ctype
, u32
*data
)
10341 t4_write_reg(adap
, SGE_CTXT_CMD_A
, CTXTQID_V(cid
) | CTXTTYPE_V(ctype
));
10342 ret
= t4_wait_op_done(adap
, SGE_CTXT_CMD_A
, BUSY_F
, 0, 3, 1);
10344 for (i
= SGE_CTXT_DATA0_A
; i
<= SGE_CTXT_DATA5_A
; i
+= 4)
10345 *data
++ = t4_read_reg(adap
, i
);
10349 int t4_sched_params(struct adapter
*adapter
, int type
, int level
, int mode
,
10350 int rateunit
, int ratemode
, int channel
, int class,
10351 int minrate
, int maxrate
, int weight
, int pktsize
)
10353 struct fw_sched_cmd cmd
;
10355 memset(&cmd
, 0, sizeof(cmd
));
10356 cmd
.op_to_write
= cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD
) |
10359 cmd
.retval_len16
= cpu_to_be32(FW_LEN16(cmd
));
10361 cmd
.u
.params
.sc
= FW_SCHED_SC_PARAMS
;
10362 cmd
.u
.params
.type
= type
;
10363 cmd
.u
.params
.level
= level
;
10364 cmd
.u
.params
.mode
= mode
;
10365 cmd
.u
.params
.ch
= channel
;
10366 cmd
.u
.params
.cl
= class;
10367 cmd
.u
.params
.unit
= rateunit
;
10368 cmd
.u
.params
.rate
= ratemode
;
10369 cmd
.u
.params
.min
= cpu_to_be32(minrate
);
10370 cmd
.u
.params
.max
= cpu_to_be32(maxrate
);
10371 cmd
.u
.params
.weight
= cpu_to_be16(weight
);
10372 cmd
.u
.params
.pktsize
= cpu_to_be16(pktsize
);
10374 return t4_wr_mbox_meat(adapter
, adapter
->mbox
, &cmd
, sizeof(cmd
),
10379 * t4_i2c_rd - read I2C data from adapter
10380 * @adap: the adapter
10381 * @port: Port number if per-port device; <0 if not
10382 * @devid: per-port device ID or absolute device ID
10383 * @offset: byte offset into device I2C space
10384 * @len: byte length of I2C space data
10385 * @buf: buffer in which to return I2C data
10387 * Reads the I2C data from the indicated device and location.
10389 int t4_i2c_rd(struct adapter
*adap
, unsigned int mbox
, int port
,
10390 unsigned int devid
, unsigned int offset
,
10391 unsigned int len
, u8
*buf
)
10393 struct fw_ldst_cmd ldst_cmd
, ldst_rpl
;
10394 unsigned int i2c_max
= sizeof(ldst_cmd
.u
.i2c
.data
);
10397 if (len
> I2C_PAGE_SIZE
)
10400 /* Dont allow reads that spans multiple pages */
10401 if (offset
< I2C_PAGE_SIZE
&& offset
+ len
> I2C_PAGE_SIZE
)
10404 memset(&ldst_cmd
, 0, sizeof(ldst_cmd
));
10405 ldst_cmd
.op_to_addrspace
=
10406 cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
10409 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_I2C
));
10410 ldst_cmd
.cycles_to_len16
= cpu_to_be32(FW_LEN16(ldst_cmd
));
10411 ldst_cmd
.u
.i2c
.pid
= (port
< 0 ? 0xff : port
);
10412 ldst_cmd
.u
.i2c
.did
= devid
;
10415 unsigned int i2c_len
= (len
< i2c_max
) ? len
: i2c_max
;
10417 ldst_cmd
.u
.i2c
.boffset
= offset
;
10418 ldst_cmd
.u
.i2c
.blen
= i2c_len
;
10420 ret
= t4_wr_mbox(adap
, mbox
, &ldst_cmd
, sizeof(ldst_cmd
),
10425 memcpy(buf
, ldst_rpl
.u
.i2c
.data
, i2c_len
);
10435 * t4_set_vlan_acl - Set a VLAN id for the specified VF
10436 * @adapter: the adapter
10437 * @mbox: mailbox to use for the FW command
10438 * @vf: one of the VFs instantiated by the specified PF
10439 * @vlan: The vlanid to be set
10441 int t4_set_vlan_acl(struct adapter
*adap
, unsigned int mbox
, unsigned int vf
,
10444 struct fw_acl_vlan_cmd vlan_cmd
;
10445 unsigned int enable
;
10447 enable
= (vlan
? FW_ACL_VLAN_CMD_EN_F
: 0);
10448 memset(&vlan_cmd
, 0, sizeof(vlan_cmd
));
10449 vlan_cmd
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_ACL_VLAN_CMD
) |
10453 FW_ACL_VLAN_CMD_PFN_V(adap
->pf
) |
10454 FW_ACL_VLAN_CMD_VFN_V(vf
));
10455 vlan_cmd
.en_to_len16
= cpu_to_be32(enable
| FW_LEN16(vlan_cmd
));
10456 /* Drop all packets that donot match vlan id */
10457 vlan_cmd
.dropnovlan_fm
= (enable
10458 ? (FW_ACL_VLAN_CMD_DROPNOVLAN_F
|
10459 FW_ACL_VLAN_CMD_FM_F
) : 0);
10461 vlan_cmd
.nvlan
= 1;
10462 vlan_cmd
.vlanid
[0] = cpu_to_be16(vlan
);
10465 return t4_wr_mbox(adap
, adap
->mbox
, &vlan_cmd
, sizeof(vlan_cmd
), NULL
);