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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / chelsio / cxgb4 / t4_hw.c
1 /*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/delay.h>
36 #include "cxgb4.h"
37 #include "t4_regs.h"
38 #include "t4_values.h"
39 #include "t4fw_api.h"
40 #include "t4fw_version.h"
41
42 /**
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
51 *
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
56 */
57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
58 int polarity, int attempts, int delay, u32 *valp)
59 {
60 while (1) {
61 u32 val = t4_read_reg(adapter, reg);
62
63 if (!!(val & mask) == polarity) {
64 if (valp)
65 *valp = val;
66 return 0;
67 }
68 if (--attempts == 0)
69 return -EAGAIN;
70 if (delay)
71 udelay(delay);
72 }
73 }
74
75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
76 int polarity, int attempts, int delay)
77 {
78 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
79 delay, NULL);
80 }
81
82 /**
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
88 *
89 * Sets a register field specified by the supplied mask to the
90 * given value.
91 */
92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
93 u32 val)
94 {
95 u32 v = t4_read_reg(adapter, addr) & ~mask;
96
97 t4_write_reg(adapter, addr, v | val);
98 (void) t4_read_reg(adapter, addr); /* flush */
99 }
100
101 /**
102 * t4_read_indirect - read indirectly addressed registers
103 * @adap: the adapter
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
109 *
110 * Reads registers that are accessed indirectly through an address/data
111 * register pair.
112 */
113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
114 unsigned int data_reg, u32 *vals,
115 unsigned int nregs, unsigned int start_idx)
116 {
117 while (nregs--) {
118 t4_write_reg(adap, addr_reg, start_idx);
119 *vals++ = t4_read_reg(adap, data_reg);
120 start_idx++;
121 }
122 }
123
124 /**
125 * t4_write_indirect - write indirectly addressed registers
126 * @adap: the adapter
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
132 *
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
135 */
136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
137 unsigned int data_reg, const u32 *vals,
138 unsigned int nregs, unsigned int start_idx)
139 {
140 while (nregs--) {
141 t4_write_reg(adap, addr_reg, start_idx++);
142 t4_write_reg(adap, data_reg, *vals++);
143 }
144 }
145
146 /*
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
151 */
152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
153 {
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
155
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
157 req |= ENABLE_F;
158 else
159 req |= T6_ENABLE_F;
160
161 if (is_t4(adap->params.chip))
162 req |= LOCALCFG_F;
163
164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
166
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
171 */
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
173 }
174
175 /*
176 * t4_report_fw_error - report firmware error
177 * @adap: the adapter
178 *
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
182 */
183 static void t4_report_fw_error(struct adapter *adap)
184 {
185 static const char *const reason[] = {
186 "Crash", /* PCIE_FW_EVAL_CRASH */
187 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
188 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
189 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
190 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
191 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
192 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
193 "Reserved", /* reserved */
194 };
195 u32 pcie_fw;
196
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
198 if (pcie_fw & PCIE_FW_ERR_F)
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
200 reason[PCIE_FW_EVAL_G(pcie_fw)]);
201 }
202
203 /*
204 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
205 */
206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
207 u32 mbox_addr)
208 {
209 for ( ; nflit; nflit--, mbox_addr += 8)
210 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
211 }
212
213 /*
214 * Handle a FW assertion reported in a mailbox.
215 */
216 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
217 {
218 struct fw_debug_cmd asrt;
219
220 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
221 dev_alert(adap->pdev_dev,
222 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
223 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
224 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
225 }
226
227 /**
228 * t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
229 * @adapter: the adapter
230 * @cmd: the Firmware Mailbox Command or Reply
231 * @size: command length in bytes
232 * @access: the time (ms) needed to access the Firmware Mailbox
233 * @execute: the time (ms) the command spent being executed
234 */
235 static void t4_record_mbox(struct adapter *adapter,
236 const __be64 *cmd, unsigned int size,
237 int access, int execute)
238 {
239 struct mbox_cmd_log *log = adapter->mbox_log;
240 struct mbox_cmd *entry;
241 int i;
242
243 entry = mbox_cmd_log_entry(log, log->cursor++);
244 if (log->cursor == log->size)
245 log->cursor = 0;
246
247 for (i = 0; i < size / 8; i++)
248 entry->cmd[i] = be64_to_cpu(cmd[i]);
249 while (i < MBOX_LEN / 8)
250 entry->cmd[i++] = 0;
251 entry->timestamp = jiffies;
252 entry->seqno = log->seqno++;
253 entry->access = access;
254 entry->execute = execute;
255 }
256
257 /**
258 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
259 * @adap: the adapter
260 * @mbox: index of the mailbox to use
261 * @cmd: the command to write
262 * @size: command length in bytes
263 * @rpl: where to optionally store the reply
264 * @sleep_ok: if true we may sleep while awaiting command completion
265 * @timeout: time to wait for command to finish before timing out
266 *
267 * Sends the given command to FW through the selected mailbox and waits
268 * for the FW to execute the command. If @rpl is not %NULL it is used to
269 * store the FW's reply to the command. The command and its optional
270 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
271 * to respond. @sleep_ok determines whether we may sleep while awaiting
272 * the response. If sleeping is allowed we use progressive backoff
273 * otherwise we spin.
274 *
275 * The return value is 0 on success or a negative errno on failure. A
276 * failure can happen either because we are not able to execute the
277 * command or FW executes it but signals an error. In the latter case
278 * the return value is the error code indicated by FW (negated).
279 */
280 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
281 int size, void *rpl, bool sleep_ok, int timeout)
282 {
283 static const int delay[] = {
284 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
285 };
286
287 struct mbox_list entry;
288 u16 access = 0;
289 u16 execute = 0;
290 u32 v;
291 u64 res;
292 int i, ms, delay_idx, ret;
293 const __be64 *p = cmd;
294 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
295 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
296 __be64 cmd_rpl[MBOX_LEN / 8];
297 u32 pcie_fw;
298
299 if ((size & 15) || size > MBOX_LEN)
300 return -EINVAL;
301
302 /*
303 * If the device is off-line, as in EEH, commands will time out.
304 * Fail them early so we don't waste time waiting.
305 */
306 if (adap->pdev->error_state != pci_channel_io_normal)
307 return -EIO;
308
309 /* If we have a negative timeout, that implies that we can't sleep. */
310 if (timeout < 0) {
311 sleep_ok = false;
312 timeout = -timeout;
313 }
314
315 /* Queue ourselves onto the mailbox access list. When our entry is at
316 * the front of the list, we have rights to access the mailbox. So we
317 * wait [for a while] till we're at the front [or bail out with an
318 * EBUSY] ...
319 */
320 spin_lock(&adap->mbox_lock);
321 list_add_tail(&entry.list, &adap->mlist.list);
322 spin_unlock(&adap->mbox_lock);
323
324 delay_idx = 0;
325 ms = delay[0];
326
327 for (i = 0; ; i += ms) {
328 /* If we've waited too long, return a busy indication. This
329 * really ought to be based on our initial position in the
330 * mailbox access list but this is a start. We very rearely
331 * contend on access to the mailbox ...
332 */
333 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
334 if (i > FW_CMD_MAX_TIMEOUT || (pcie_fw & PCIE_FW_ERR_F)) {
335 spin_lock(&adap->mbox_lock);
336 list_del(&entry.list);
337 spin_unlock(&adap->mbox_lock);
338 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY;
339 t4_record_mbox(adap, cmd, size, access, ret);
340 return ret;
341 }
342
343 /* If we're at the head, break out and start the mailbox
344 * protocol.
345 */
346 if (list_first_entry(&adap->mlist.list, struct mbox_list,
347 list) == &entry)
348 break;
349
350 /* Delay for a bit before checking again ... */
351 if (sleep_ok) {
352 ms = delay[delay_idx]; /* last element may repeat */
353 if (delay_idx < ARRAY_SIZE(delay) - 1)
354 delay_idx++;
355 msleep(ms);
356 } else {
357 mdelay(ms);
358 }
359 }
360
361 /* Loop trying to get ownership of the mailbox. Return an error
362 * if we can't gain ownership.
363 */
364 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
365 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
366 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
367 if (v != MBOX_OWNER_DRV) {
368 spin_lock(&adap->mbox_lock);
369 list_del(&entry.list);
370 spin_unlock(&adap->mbox_lock);
371 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
372 t4_record_mbox(adap, cmd, MBOX_LEN, access, ret);
373 return ret;
374 }
375
376 /* Copy in the new mailbox command and send it on its way ... */
377 t4_record_mbox(adap, cmd, MBOX_LEN, access, 0);
378 for (i = 0; i < size; i += 8)
379 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
380
381 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
382 t4_read_reg(adap, ctl_reg); /* flush write */
383
384 delay_idx = 0;
385 ms = delay[0];
386
387 for (i = 0;
388 !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
389 i < timeout;
390 i += ms) {
391 if (sleep_ok) {
392 ms = delay[delay_idx]; /* last element may repeat */
393 if (delay_idx < ARRAY_SIZE(delay) - 1)
394 delay_idx++;
395 msleep(ms);
396 } else
397 mdelay(ms);
398
399 v = t4_read_reg(adap, ctl_reg);
400 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
401 if (!(v & MBMSGVALID_F)) {
402 t4_write_reg(adap, ctl_reg, 0);
403 continue;
404 }
405
406 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
407 res = be64_to_cpu(cmd_rpl[0]);
408
409 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
410 fw_asrt(adap, data_reg);
411 res = FW_CMD_RETVAL_V(EIO);
412 } else if (rpl) {
413 memcpy(rpl, cmd_rpl, size);
414 }
415
416 t4_write_reg(adap, ctl_reg, 0);
417
418 execute = i + ms;
419 t4_record_mbox(adap, cmd_rpl,
420 MBOX_LEN, access, execute);
421 spin_lock(&adap->mbox_lock);
422 list_del(&entry.list);
423 spin_unlock(&adap->mbox_lock);
424 return -FW_CMD_RETVAL_G((int)res);
425 }
426 }
427
428 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
429 t4_record_mbox(adap, cmd, MBOX_LEN, access, ret);
430 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
431 *(const u8 *)cmd, mbox);
432 t4_report_fw_error(adap);
433 spin_lock(&adap->mbox_lock);
434 list_del(&entry.list);
435 spin_unlock(&adap->mbox_lock);
436 t4_fatal_err(adap);
437 return ret;
438 }
439
440 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
441 void *rpl, bool sleep_ok)
442 {
443 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
444 FW_CMD_MAX_TIMEOUT);
445 }
446
447 static int t4_edc_err_read(struct adapter *adap, int idx)
448 {
449 u32 edc_ecc_err_addr_reg;
450 u32 rdata_reg;
451
452 if (is_t4(adap->params.chip)) {
453 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
454 return 0;
455 }
456 if (idx != 0 && idx != 1) {
457 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
458 return 0;
459 }
460
461 edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
462 rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
463
464 CH_WARN(adap,
465 "edc%d err addr 0x%x: 0x%x.\n",
466 idx, edc_ecc_err_addr_reg,
467 t4_read_reg(adap, edc_ecc_err_addr_reg));
468 CH_WARN(adap,
469 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
470 rdata_reg,
471 (unsigned long long)t4_read_reg64(adap, rdata_reg),
472 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
473 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
474 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
475 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
476 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
477 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
478 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
479 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
480
481 return 0;
482 }
483
484 /**
485 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
486 * @adap: the adapter
487 * @win: PCI-E Memory Window to use
488 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
489 * @addr: address within indicated memory type
490 * @len: amount of memory to transfer
491 * @hbuf: host memory buffer
492 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
493 *
494 * Reads/writes an [almost] arbitrary memory region in the firmware: the
495 * firmware memory address and host buffer must be aligned on 32-bit
496 * boudaries; the length may be arbitrary. The memory is transferred as
497 * a raw byte sequence from/to the firmware's memory. If this memory
498 * contains data structures which contain multi-byte integers, it's the
499 * caller's responsibility to perform appropriate byte order conversions.
500 */
501 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
502 u32 len, void *hbuf, int dir)
503 {
504 u32 pos, offset, resid, memoffset;
505 u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
506 u32 *buf;
507
508 /* Argument sanity checks ...
509 */
510 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
511 return -EINVAL;
512 buf = (u32 *)hbuf;
513
514 /* It's convenient to be able to handle lengths which aren't a
515 * multiple of 32-bits because we often end up transferring files to
516 * the firmware. So we'll handle that by normalizing the length here
517 * and then handling any residual transfer at the end.
518 */
519 resid = len & 0x3;
520 len -= resid;
521
522 /* Offset into the region of memory which is being accessed
523 * MEM_EDC0 = 0
524 * MEM_EDC1 = 1
525 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
526 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
527 */
528 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
529 if (mtype != MEM_MC1)
530 memoffset = (mtype * (edc_size * 1024 * 1024));
531 else {
532 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
533 MA_EXT_MEMORY0_BAR_A));
534 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
535 }
536
537 /* Determine the PCIE_MEM_ACCESS_OFFSET */
538 addr = addr + memoffset;
539
540 /* Each PCI-E Memory Window is programmed with a window size -- or
541 * "aperture" -- which controls the granularity of its mapping onto
542 * adapter memory. We need to grab that aperture in order to know
543 * how to use the specified window. The window is also programmed
544 * with the base address of the Memory Window in BAR0's address
545 * space. For T4 this is an absolute PCI-E Bus Address. For T5
546 * the address is relative to BAR0.
547 */
548 mem_reg = t4_read_reg(adap,
549 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
550 win));
551 mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
552 mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
553 if (is_t4(adap->params.chip))
554 mem_base -= adap->t4_bar0;
555 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
556
557 /* Calculate our initial PCI-E Memory Window Position and Offset into
558 * that Window.
559 */
560 pos = addr & ~(mem_aperture-1);
561 offset = addr - pos;
562
563 /* Set up initial PCI-E Memory Window to cover the start of our
564 * transfer. (Read it back to ensure that changes propagate before we
565 * attempt to use the new value.)
566 */
567 t4_write_reg(adap,
568 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
569 pos | win_pf);
570 t4_read_reg(adap,
571 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
572
573 /* Transfer data to/from the adapter as long as there's an integral
574 * number of 32-bit transfers to complete.
575 *
576 * A note on Endianness issues:
577 *
578 * The "register" reads and writes below from/to the PCI-E Memory
579 * Window invoke the standard adapter Big-Endian to PCI-E Link
580 * Little-Endian "swizzel." As a result, if we have the following
581 * data in adapter memory:
582 *
583 * Memory: ... | b0 | b1 | b2 | b3 | ...
584 * Address: i+0 i+1 i+2 i+3
585 *
586 * Then a read of the adapter memory via the PCI-E Memory Window
587 * will yield:
588 *
589 * x = readl(i)
590 * 31 0
591 * [ b3 | b2 | b1 | b0 ]
592 *
593 * If this value is stored into local memory on a Little-Endian system
594 * it will show up correctly in local memory as:
595 *
596 * ( ..., b0, b1, b2, b3, ... )
597 *
598 * But on a Big-Endian system, the store will show up in memory
599 * incorrectly swizzled as:
600 *
601 * ( ..., b3, b2, b1, b0, ... )
602 *
603 * So we need to account for this in the reads and writes to the
604 * PCI-E Memory Window below by undoing the register read/write
605 * swizzels.
606 */
607 while (len > 0) {
608 if (dir == T4_MEMORY_READ)
609 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
610 mem_base + offset));
611 else
612 t4_write_reg(adap, mem_base + offset,
613 (__force u32)cpu_to_le32(*buf++));
614 offset += sizeof(__be32);
615 len -= sizeof(__be32);
616
617 /* If we've reached the end of our current window aperture,
618 * move the PCI-E Memory Window on to the next. Note that
619 * doing this here after "len" may be 0 allows us to set up
620 * the PCI-E Memory Window for a possible final residual
621 * transfer below ...
622 */
623 if (offset == mem_aperture) {
624 pos += mem_aperture;
625 offset = 0;
626 t4_write_reg(adap,
627 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
628 win), pos | win_pf);
629 t4_read_reg(adap,
630 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
631 win));
632 }
633 }
634
635 /* If the original transfer had a length which wasn't a multiple of
636 * 32-bits, now's where we need to finish off the transfer of the
637 * residual amount. The PCI-E Memory Window has already been moved
638 * above (if necessary) to cover this final transfer.
639 */
640 if (resid) {
641 union {
642 u32 word;
643 char byte[4];
644 } last;
645 unsigned char *bp;
646 int i;
647
648 if (dir == T4_MEMORY_READ) {
649 last.word = le32_to_cpu(
650 (__force __le32)t4_read_reg(adap,
651 mem_base + offset));
652 for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
653 bp[i] = last.byte[i];
654 } else {
655 last.word = *buf;
656 for (i = resid; i < 4; i++)
657 last.byte[i] = 0;
658 t4_write_reg(adap, mem_base + offset,
659 (__force u32)cpu_to_le32(last.word));
660 }
661 }
662
663 return 0;
664 }
665
666 /* Return the specified PCI-E Configuration Space register from our Physical
667 * Function. We try first via a Firmware LDST Command since we prefer to let
668 * the firmware own all of these registers, but if that fails we go for it
669 * directly ourselves.
670 */
671 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
672 {
673 u32 val, ldst_addrspace;
674
675 /* If fw_attach != 0, construct and send the Firmware LDST Command to
676 * retrieve the specified PCI-E Configuration Space register.
677 */
678 struct fw_ldst_cmd ldst_cmd;
679 int ret;
680
681 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
682 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
683 ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
684 FW_CMD_REQUEST_F |
685 FW_CMD_READ_F |
686 ldst_addrspace);
687 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
688 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
689 ldst_cmd.u.pcie.ctrl_to_fn =
690 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
691 ldst_cmd.u.pcie.r = reg;
692
693 /* If the LDST Command succeeds, return the result, otherwise
694 * fall through to reading it directly ourselves ...
695 */
696 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
697 &ldst_cmd);
698 if (ret == 0)
699 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
700 else
701 /* Read the desired Configuration Space register via the PCI-E
702 * Backdoor mechanism.
703 */
704 t4_hw_pci_read_cfg4(adap, reg, &val);
705 return val;
706 }
707
708 /* Get the window based on base passed to it.
709 * Window aperture is currently unhandled, but there is no use case for it
710 * right now
711 */
712 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
713 u32 memwin_base)
714 {
715 u32 ret;
716
717 if (is_t4(adap->params.chip)) {
718 u32 bar0;
719
720 /* Truncation intentional: we only read the bottom 32-bits of
721 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
722 * mechanism to read BAR0 instead of using
723 * pci_resource_start() because we could be operating from
724 * within a Virtual Machine which is trapping our accesses to
725 * our Configuration Space and we need to set up the PCI-E
726 * Memory Window decoders with the actual addresses which will
727 * be coming across the PCI-E link.
728 */
729 bar0 = t4_read_pcie_cfg4(adap, pci_base);
730 bar0 &= pci_mask;
731 adap->t4_bar0 = bar0;
732
733 ret = bar0 + memwin_base;
734 } else {
735 /* For T5, only relative offset inside the PCIe BAR is passed */
736 ret = memwin_base;
737 }
738 return ret;
739 }
740
741 /* Get the default utility window (win0) used by everyone */
742 u32 t4_get_util_window(struct adapter *adap)
743 {
744 return t4_get_window(adap, PCI_BASE_ADDRESS_0,
745 PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
746 }
747
748 /* Set up memory window for accessing adapter memory ranges. (Read
749 * back MA register to ensure that changes propagate before we attempt
750 * to use the new values.)
751 */
752 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
753 {
754 t4_write_reg(adap,
755 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
756 memwin_base | BIR_V(0) |
757 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
758 t4_read_reg(adap,
759 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
760 }
761
762 /**
763 * t4_get_regs_len - return the size of the chips register set
764 * @adapter: the adapter
765 *
766 * Returns the size of the chip's BAR0 register space.
767 */
768 unsigned int t4_get_regs_len(struct adapter *adapter)
769 {
770 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
771
772 switch (chip_version) {
773 case CHELSIO_T4:
774 return T4_REGMAP_SIZE;
775
776 case CHELSIO_T5:
777 case CHELSIO_T6:
778 return T5_REGMAP_SIZE;
779 }
780
781 dev_err(adapter->pdev_dev,
782 "Unsupported chip version %d\n", chip_version);
783 return 0;
784 }
785
786 /**
787 * t4_get_regs - read chip registers into provided buffer
788 * @adap: the adapter
789 * @buf: register buffer
790 * @buf_size: size (in bytes) of register buffer
791 *
792 * If the provided register buffer isn't large enough for the chip's
793 * full register range, the register dump will be truncated to the
794 * register buffer's size.
795 */
796 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
797 {
798 static const unsigned int t4_reg_ranges[] = {
799 0x1008, 0x1108,
800 0x1180, 0x1184,
801 0x1190, 0x1194,
802 0x11a0, 0x11a4,
803 0x11b0, 0x11b4,
804 0x11fc, 0x123c,
805 0x1300, 0x173c,
806 0x1800, 0x18fc,
807 0x3000, 0x30d8,
808 0x30e0, 0x30e4,
809 0x30ec, 0x5910,
810 0x5920, 0x5924,
811 0x5960, 0x5960,
812 0x5968, 0x5968,
813 0x5970, 0x5970,
814 0x5978, 0x5978,
815 0x5980, 0x5980,
816 0x5988, 0x5988,
817 0x5990, 0x5990,
818 0x5998, 0x5998,
819 0x59a0, 0x59d4,
820 0x5a00, 0x5ae0,
821 0x5ae8, 0x5ae8,
822 0x5af0, 0x5af0,
823 0x5af8, 0x5af8,
824 0x6000, 0x6098,
825 0x6100, 0x6150,
826 0x6200, 0x6208,
827 0x6240, 0x6248,
828 0x6280, 0x62b0,
829 0x62c0, 0x6338,
830 0x6370, 0x638c,
831 0x6400, 0x643c,
832 0x6500, 0x6524,
833 0x6a00, 0x6a04,
834 0x6a14, 0x6a38,
835 0x6a60, 0x6a70,
836 0x6a78, 0x6a78,
837 0x6b00, 0x6b0c,
838 0x6b1c, 0x6b84,
839 0x6bf0, 0x6bf8,
840 0x6c00, 0x6c0c,
841 0x6c1c, 0x6c84,
842 0x6cf0, 0x6cf8,
843 0x6d00, 0x6d0c,
844 0x6d1c, 0x6d84,
845 0x6df0, 0x6df8,
846 0x6e00, 0x6e0c,
847 0x6e1c, 0x6e84,
848 0x6ef0, 0x6ef8,
849 0x6f00, 0x6f0c,
850 0x6f1c, 0x6f84,
851 0x6ff0, 0x6ff8,
852 0x7000, 0x700c,
853 0x701c, 0x7084,
854 0x70f0, 0x70f8,
855 0x7100, 0x710c,
856 0x711c, 0x7184,
857 0x71f0, 0x71f8,
858 0x7200, 0x720c,
859 0x721c, 0x7284,
860 0x72f0, 0x72f8,
861 0x7300, 0x730c,
862 0x731c, 0x7384,
863 0x73f0, 0x73f8,
864 0x7400, 0x7450,
865 0x7500, 0x7530,
866 0x7600, 0x760c,
867 0x7614, 0x761c,
868 0x7680, 0x76cc,
869 0x7700, 0x7798,
870 0x77c0, 0x77fc,
871 0x7900, 0x79fc,
872 0x7b00, 0x7b58,
873 0x7b60, 0x7b84,
874 0x7b8c, 0x7c38,
875 0x7d00, 0x7d38,
876 0x7d40, 0x7d80,
877 0x7d8c, 0x7ddc,
878 0x7de4, 0x7e04,
879 0x7e10, 0x7e1c,
880 0x7e24, 0x7e38,
881 0x7e40, 0x7e44,
882 0x7e4c, 0x7e78,
883 0x7e80, 0x7ea4,
884 0x7eac, 0x7edc,
885 0x7ee8, 0x7efc,
886 0x8dc0, 0x8e04,
887 0x8e10, 0x8e1c,
888 0x8e30, 0x8e78,
889 0x8ea0, 0x8eb8,
890 0x8ec0, 0x8f6c,
891 0x8fc0, 0x9008,
892 0x9010, 0x9058,
893 0x9060, 0x9060,
894 0x9068, 0x9074,
895 0x90fc, 0x90fc,
896 0x9400, 0x9408,
897 0x9410, 0x9458,
898 0x9600, 0x9600,
899 0x9608, 0x9638,
900 0x9640, 0x96bc,
901 0x9800, 0x9808,
902 0x9820, 0x983c,
903 0x9850, 0x9864,
904 0x9c00, 0x9c6c,
905 0x9c80, 0x9cec,
906 0x9d00, 0x9d6c,
907 0x9d80, 0x9dec,
908 0x9e00, 0x9e6c,
909 0x9e80, 0x9eec,
910 0x9f00, 0x9f6c,
911 0x9f80, 0x9fec,
912 0xd004, 0xd004,
913 0xd010, 0xd03c,
914 0xdfc0, 0xdfe0,
915 0xe000, 0xea7c,
916 0xf000, 0x11190,
917 0x19040, 0x1906c,
918 0x19078, 0x19080,
919 0x1908c, 0x190e4,
920 0x190f0, 0x190f8,
921 0x19100, 0x19110,
922 0x19120, 0x19124,
923 0x19150, 0x19194,
924 0x1919c, 0x191b0,
925 0x191d0, 0x191e8,
926 0x19238, 0x1924c,
927 0x193f8, 0x1943c,
928 0x1944c, 0x19474,
929 0x19490, 0x194e0,
930 0x194f0, 0x194f8,
931 0x19800, 0x19c08,
932 0x19c10, 0x19c90,
933 0x19ca0, 0x19ce4,
934 0x19cf0, 0x19d40,
935 0x19d50, 0x19d94,
936 0x19da0, 0x19de8,
937 0x19df0, 0x19e40,
938 0x19e50, 0x19e90,
939 0x19ea0, 0x19f4c,
940 0x1a000, 0x1a004,
941 0x1a010, 0x1a06c,
942 0x1a0b0, 0x1a0e4,
943 0x1a0ec, 0x1a0f4,
944 0x1a100, 0x1a108,
945 0x1a114, 0x1a120,
946 0x1a128, 0x1a130,
947 0x1a138, 0x1a138,
948 0x1a190, 0x1a1c4,
949 0x1a1fc, 0x1a1fc,
950 0x1e040, 0x1e04c,
951 0x1e284, 0x1e28c,
952 0x1e2c0, 0x1e2c0,
953 0x1e2e0, 0x1e2e0,
954 0x1e300, 0x1e384,
955 0x1e3c0, 0x1e3c8,
956 0x1e440, 0x1e44c,
957 0x1e684, 0x1e68c,
958 0x1e6c0, 0x1e6c0,
959 0x1e6e0, 0x1e6e0,
960 0x1e700, 0x1e784,
961 0x1e7c0, 0x1e7c8,
962 0x1e840, 0x1e84c,
963 0x1ea84, 0x1ea8c,
964 0x1eac0, 0x1eac0,
965 0x1eae0, 0x1eae0,
966 0x1eb00, 0x1eb84,
967 0x1ebc0, 0x1ebc8,
968 0x1ec40, 0x1ec4c,
969 0x1ee84, 0x1ee8c,
970 0x1eec0, 0x1eec0,
971 0x1eee0, 0x1eee0,
972 0x1ef00, 0x1ef84,
973 0x1efc0, 0x1efc8,
974 0x1f040, 0x1f04c,
975 0x1f284, 0x1f28c,
976 0x1f2c0, 0x1f2c0,
977 0x1f2e0, 0x1f2e0,
978 0x1f300, 0x1f384,
979 0x1f3c0, 0x1f3c8,
980 0x1f440, 0x1f44c,
981 0x1f684, 0x1f68c,
982 0x1f6c0, 0x1f6c0,
983 0x1f6e0, 0x1f6e0,
984 0x1f700, 0x1f784,
985 0x1f7c0, 0x1f7c8,
986 0x1f840, 0x1f84c,
987 0x1fa84, 0x1fa8c,
988 0x1fac0, 0x1fac0,
989 0x1fae0, 0x1fae0,
990 0x1fb00, 0x1fb84,
991 0x1fbc0, 0x1fbc8,
992 0x1fc40, 0x1fc4c,
993 0x1fe84, 0x1fe8c,
994 0x1fec0, 0x1fec0,
995 0x1fee0, 0x1fee0,
996 0x1ff00, 0x1ff84,
997 0x1ffc0, 0x1ffc8,
998 0x20000, 0x2002c,
999 0x20100, 0x2013c,
1000 0x20190, 0x201a0,
1001 0x201a8, 0x201b8,
1002 0x201c4, 0x201c8,
1003 0x20200, 0x20318,
1004 0x20400, 0x204b4,
1005 0x204c0, 0x20528,
1006 0x20540, 0x20614,
1007 0x21000, 0x21040,
1008 0x2104c, 0x21060,
1009 0x210c0, 0x210ec,
1010 0x21200, 0x21268,
1011 0x21270, 0x21284,
1012 0x212fc, 0x21388,
1013 0x21400, 0x21404,
1014 0x21500, 0x21500,
1015 0x21510, 0x21518,
1016 0x2152c, 0x21530,
1017 0x2153c, 0x2153c,
1018 0x21550, 0x21554,
1019 0x21600, 0x21600,
1020 0x21608, 0x2161c,
1021 0x21624, 0x21628,
1022 0x21630, 0x21634,
1023 0x2163c, 0x2163c,
1024 0x21700, 0x2171c,
1025 0x21780, 0x2178c,
1026 0x21800, 0x21818,
1027 0x21820, 0x21828,
1028 0x21830, 0x21848,
1029 0x21850, 0x21854,
1030 0x21860, 0x21868,
1031 0x21870, 0x21870,
1032 0x21878, 0x21898,
1033 0x218a0, 0x218a8,
1034 0x218b0, 0x218c8,
1035 0x218d0, 0x218d4,
1036 0x218e0, 0x218e8,
1037 0x218f0, 0x218f0,
1038 0x218f8, 0x21a18,
1039 0x21a20, 0x21a28,
1040 0x21a30, 0x21a48,
1041 0x21a50, 0x21a54,
1042 0x21a60, 0x21a68,
1043 0x21a70, 0x21a70,
1044 0x21a78, 0x21a98,
1045 0x21aa0, 0x21aa8,
1046 0x21ab0, 0x21ac8,
1047 0x21ad0, 0x21ad4,
1048 0x21ae0, 0x21ae8,
1049 0x21af0, 0x21af0,
1050 0x21af8, 0x21c18,
1051 0x21c20, 0x21c20,
1052 0x21c28, 0x21c30,
1053 0x21c38, 0x21c38,
1054 0x21c80, 0x21c98,
1055 0x21ca0, 0x21ca8,
1056 0x21cb0, 0x21cc8,
1057 0x21cd0, 0x21cd4,
1058 0x21ce0, 0x21ce8,
1059 0x21cf0, 0x21cf0,
1060 0x21cf8, 0x21d7c,
1061 0x21e00, 0x21e04,
1062 0x22000, 0x2202c,
1063 0x22100, 0x2213c,
1064 0x22190, 0x221a0,
1065 0x221a8, 0x221b8,
1066 0x221c4, 0x221c8,
1067 0x22200, 0x22318,
1068 0x22400, 0x224b4,
1069 0x224c0, 0x22528,
1070 0x22540, 0x22614,
1071 0x23000, 0x23040,
1072 0x2304c, 0x23060,
1073 0x230c0, 0x230ec,
1074 0x23200, 0x23268,
1075 0x23270, 0x23284,
1076 0x232fc, 0x23388,
1077 0x23400, 0x23404,
1078 0x23500, 0x23500,
1079 0x23510, 0x23518,
1080 0x2352c, 0x23530,
1081 0x2353c, 0x2353c,
1082 0x23550, 0x23554,
1083 0x23600, 0x23600,
1084 0x23608, 0x2361c,
1085 0x23624, 0x23628,
1086 0x23630, 0x23634,
1087 0x2363c, 0x2363c,
1088 0x23700, 0x2371c,
1089 0x23780, 0x2378c,
1090 0x23800, 0x23818,
1091 0x23820, 0x23828,
1092 0x23830, 0x23848,
1093 0x23850, 0x23854,
1094 0x23860, 0x23868,
1095 0x23870, 0x23870,
1096 0x23878, 0x23898,
1097 0x238a0, 0x238a8,
1098 0x238b0, 0x238c8,
1099 0x238d0, 0x238d4,
1100 0x238e0, 0x238e8,
1101 0x238f0, 0x238f0,
1102 0x238f8, 0x23a18,
1103 0x23a20, 0x23a28,
1104 0x23a30, 0x23a48,
1105 0x23a50, 0x23a54,
1106 0x23a60, 0x23a68,
1107 0x23a70, 0x23a70,
1108 0x23a78, 0x23a98,
1109 0x23aa0, 0x23aa8,
1110 0x23ab0, 0x23ac8,
1111 0x23ad0, 0x23ad4,
1112 0x23ae0, 0x23ae8,
1113 0x23af0, 0x23af0,
1114 0x23af8, 0x23c18,
1115 0x23c20, 0x23c20,
1116 0x23c28, 0x23c30,
1117 0x23c38, 0x23c38,
1118 0x23c80, 0x23c98,
1119 0x23ca0, 0x23ca8,
1120 0x23cb0, 0x23cc8,
1121 0x23cd0, 0x23cd4,
1122 0x23ce0, 0x23ce8,
1123 0x23cf0, 0x23cf0,
1124 0x23cf8, 0x23d7c,
1125 0x23e00, 0x23e04,
1126 0x24000, 0x2402c,
1127 0x24100, 0x2413c,
1128 0x24190, 0x241a0,
1129 0x241a8, 0x241b8,
1130 0x241c4, 0x241c8,
1131 0x24200, 0x24318,
1132 0x24400, 0x244b4,
1133 0x244c0, 0x24528,
1134 0x24540, 0x24614,
1135 0x25000, 0x25040,
1136 0x2504c, 0x25060,
1137 0x250c0, 0x250ec,
1138 0x25200, 0x25268,
1139 0x25270, 0x25284,
1140 0x252fc, 0x25388,
1141 0x25400, 0x25404,
1142 0x25500, 0x25500,
1143 0x25510, 0x25518,
1144 0x2552c, 0x25530,
1145 0x2553c, 0x2553c,
1146 0x25550, 0x25554,
1147 0x25600, 0x25600,
1148 0x25608, 0x2561c,
1149 0x25624, 0x25628,
1150 0x25630, 0x25634,
1151 0x2563c, 0x2563c,
1152 0x25700, 0x2571c,
1153 0x25780, 0x2578c,
1154 0x25800, 0x25818,
1155 0x25820, 0x25828,
1156 0x25830, 0x25848,
1157 0x25850, 0x25854,
1158 0x25860, 0x25868,
1159 0x25870, 0x25870,
1160 0x25878, 0x25898,
1161 0x258a0, 0x258a8,
1162 0x258b0, 0x258c8,
1163 0x258d0, 0x258d4,
1164 0x258e0, 0x258e8,
1165 0x258f0, 0x258f0,
1166 0x258f8, 0x25a18,
1167 0x25a20, 0x25a28,
1168 0x25a30, 0x25a48,
1169 0x25a50, 0x25a54,
1170 0x25a60, 0x25a68,
1171 0x25a70, 0x25a70,
1172 0x25a78, 0x25a98,
1173 0x25aa0, 0x25aa8,
1174 0x25ab0, 0x25ac8,
1175 0x25ad0, 0x25ad4,
1176 0x25ae0, 0x25ae8,
1177 0x25af0, 0x25af0,
1178 0x25af8, 0x25c18,
1179 0x25c20, 0x25c20,
1180 0x25c28, 0x25c30,
1181 0x25c38, 0x25c38,
1182 0x25c80, 0x25c98,
1183 0x25ca0, 0x25ca8,
1184 0x25cb0, 0x25cc8,
1185 0x25cd0, 0x25cd4,
1186 0x25ce0, 0x25ce8,
1187 0x25cf0, 0x25cf0,
1188 0x25cf8, 0x25d7c,
1189 0x25e00, 0x25e04,
1190 0x26000, 0x2602c,
1191 0x26100, 0x2613c,
1192 0x26190, 0x261a0,
1193 0x261a8, 0x261b8,
1194 0x261c4, 0x261c8,
1195 0x26200, 0x26318,
1196 0x26400, 0x264b4,
1197 0x264c0, 0x26528,
1198 0x26540, 0x26614,
1199 0x27000, 0x27040,
1200 0x2704c, 0x27060,
1201 0x270c0, 0x270ec,
1202 0x27200, 0x27268,
1203 0x27270, 0x27284,
1204 0x272fc, 0x27388,
1205 0x27400, 0x27404,
1206 0x27500, 0x27500,
1207 0x27510, 0x27518,
1208 0x2752c, 0x27530,
1209 0x2753c, 0x2753c,
1210 0x27550, 0x27554,
1211 0x27600, 0x27600,
1212 0x27608, 0x2761c,
1213 0x27624, 0x27628,
1214 0x27630, 0x27634,
1215 0x2763c, 0x2763c,
1216 0x27700, 0x2771c,
1217 0x27780, 0x2778c,
1218 0x27800, 0x27818,
1219 0x27820, 0x27828,
1220 0x27830, 0x27848,
1221 0x27850, 0x27854,
1222 0x27860, 0x27868,
1223 0x27870, 0x27870,
1224 0x27878, 0x27898,
1225 0x278a0, 0x278a8,
1226 0x278b0, 0x278c8,
1227 0x278d0, 0x278d4,
1228 0x278e0, 0x278e8,
1229 0x278f0, 0x278f0,
1230 0x278f8, 0x27a18,
1231 0x27a20, 0x27a28,
1232 0x27a30, 0x27a48,
1233 0x27a50, 0x27a54,
1234 0x27a60, 0x27a68,
1235 0x27a70, 0x27a70,
1236 0x27a78, 0x27a98,
1237 0x27aa0, 0x27aa8,
1238 0x27ab0, 0x27ac8,
1239 0x27ad0, 0x27ad4,
1240 0x27ae0, 0x27ae8,
1241 0x27af0, 0x27af0,
1242 0x27af8, 0x27c18,
1243 0x27c20, 0x27c20,
1244 0x27c28, 0x27c30,
1245 0x27c38, 0x27c38,
1246 0x27c80, 0x27c98,
1247 0x27ca0, 0x27ca8,
1248 0x27cb0, 0x27cc8,
1249 0x27cd0, 0x27cd4,
1250 0x27ce0, 0x27ce8,
1251 0x27cf0, 0x27cf0,
1252 0x27cf8, 0x27d7c,
1253 0x27e00, 0x27e04,
1254 };
1255
1256 static const unsigned int t5_reg_ranges[] = {
1257 0x1008, 0x10c0,
1258 0x10cc, 0x10f8,
1259 0x1100, 0x1100,
1260 0x110c, 0x1148,
1261 0x1180, 0x1184,
1262 0x1190, 0x1194,
1263 0x11a0, 0x11a4,
1264 0x11b0, 0x11b4,
1265 0x11fc, 0x123c,
1266 0x1280, 0x173c,
1267 0x1800, 0x18fc,
1268 0x3000, 0x3028,
1269 0x3060, 0x30b0,
1270 0x30b8, 0x30d8,
1271 0x30e0, 0x30fc,
1272 0x3140, 0x357c,
1273 0x35a8, 0x35cc,
1274 0x35ec, 0x35ec,
1275 0x3600, 0x5624,
1276 0x56cc, 0x56ec,
1277 0x56f4, 0x5720,
1278 0x5728, 0x575c,
1279 0x580c, 0x5814,
1280 0x5890, 0x589c,
1281 0x58a4, 0x58ac,
1282 0x58b8, 0x58bc,
1283 0x5940, 0x59c8,
1284 0x59d0, 0x59dc,
1285 0x59fc, 0x5a18,
1286 0x5a60, 0x5a70,
1287 0x5a80, 0x5a9c,
1288 0x5b94, 0x5bfc,
1289 0x6000, 0x6020,
1290 0x6028, 0x6040,
1291 0x6058, 0x609c,
1292 0x60a8, 0x614c,
1293 0x7700, 0x7798,
1294 0x77c0, 0x78fc,
1295 0x7b00, 0x7b58,
1296 0x7b60, 0x7b84,
1297 0x7b8c, 0x7c54,
1298 0x7d00, 0x7d38,
1299 0x7d40, 0x7d80,
1300 0x7d8c, 0x7ddc,
1301 0x7de4, 0x7e04,
1302 0x7e10, 0x7e1c,
1303 0x7e24, 0x7e38,
1304 0x7e40, 0x7e44,
1305 0x7e4c, 0x7e78,
1306 0x7e80, 0x7edc,
1307 0x7ee8, 0x7efc,
1308 0x8dc0, 0x8de0,
1309 0x8df8, 0x8e04,
1310 0x8e10, 0x8e84,
1311 0x8ea0, 0x8f84,
1312 0x8fc0, 0x9058,
1313 0x9060, 0x9060,
1314 0x9068, 0x90f8,
1315 0x9400, 0x9408,
1316 0x9410, 0x9470,
1317 0x9600, 0x9600,
1318 0x9608, 0x9638,
1319 0x9640, 0x96f4,
1320 0x9800, 0x9808,
1321 0x9820, 0x983c,
1322 0x9850, 0x9864,
1323 0x9c00, 0x9c6c,
1324 0x9c80, 0x9cec,
1325 0x9d00, 0x9d6c,
1326 0x9d80, 0x9dec,
1327 0x9e00, 0x9e6c,
1328 0x9e80, 0x9eec,
1329 0x9f00, 0x9f6c,
1330 0x9f80, 0xa020,
1331 0xd004, 0xd004,
1332 0xd010, 0xd03c,
1333 0xdfc0, 0xdfe0,
1334 0xe000, 0x1106c,
1335 0x11074, 0x11088,
1336 0x1109c, 0x1117c,
1337 0x11190, 0x11204,
1338 0x19040, 0x1906c,
1339 0x19078, 0x19080,
1340 0x1908c, 0x190e8,
1341 0x190f0, 0x190f8,
1342 0x19100, 0x19110,
1343 0x19120, 0x19124,
1344 0x19150, 0x19194,
1345 0x1919c, 0x191b0,
1346 0x191d0, 0x191e8,
1347 0x19238, 0x19290,
1348 0x193f8, 0x19428,
1349 0x19430, 0x19444,
1350 0x1944c, 0x1946c,
1351 0x19474, 0x19474,
1352 0x19490, 0x194cc,
1353 0x194f0, 0x194f8,
1354 0x19c00, 0x19c08,
1355 0x19c10, 0x19c60,
1356 0x19c94, 0x19ce4,
1357 0x19cf0, 0x19d40,
1358 0x19d50, 0x19d94,
1359 0x19da0, 0x19de8,
1360 0x19df0, 0x19e10,
1361 0x19e50, 0x19e90,
1362 0x19ea0, 0x19f24,
1363 0x19f34, 0x19f34,
1364 0x19f40, 0x19f50,
1365 0x19f90, 0x19fb4,
1366 0x19fc4, 0x19fe4,
1367 0x1a000, 0x1a004,
1368 0x1a010, 0x1a06c,
1369 0x1a0b0, 0x1a0e4,
1370 0x1a0ec, 0x1a0f8,
1371 0x1a100, 0x1a108,
1372 0x1a114, 0x1a120,
1373 0x1a128, 0x1a130,
1374 0x1a138, 0x1a138,
1375 0x1a190, 0x1a1c4,
1376 0x1a1fc, 0x1a1fc,
1377 0x1e008, 0x1e00c,
1378 0x1e040, 0x1e044,
1379 0x1e04c, 0x1e04c,
1380 0x1e284, 0x1e290,
1381 0x1e2c0, 0x1e2c0,
1382 0x1e2e0, 0x1e2e0,
1383 0x1e300, 0x1e384,
1384 0x1e3c0, 0x1e3c8,
1385 0x1e408, 0x1e40c,
1386 0x1e440, 0x1e444,
1387 0x1e44c, 0x1e44c,
1388 0x1e684, 0x1e690,
1389 0x1e6c0, 0x1e6c0,
1390 0x1e6e0, 0x1e6e0,
1391 0x1e700, 0x1e784,
1392 0x1e7c0, 0x1e7c8,
1393 0x1e808, 0x1e80c,
1394 0x1e840, 0x1e844,
1395 0x1e84c, 0x1e84c,
1396 0x1ea84, 0x1ea90,
1397 0x1eac0, 0x1eac0,
1398 0x1eae0, 0x1eae0,
1399 0x1eb00, 0x1eb84,
1400 0x1ebc0, 0x1ebc8,
1401 0x1ec08, 0x1ec0c,
1402 0x1ec40, 0x1ec44,
1403 0x1ec4c, 0x1ec4c,
1404 0x1ee84, 0x1ee90,
1405 0x1eec0, 0x1eec0,
1406 0x1eee0, 0x1eee0,
1407 0x1ef00, 0x1ef84,
1408 0x1efc0, 0x1efc8,
1409 0x1f008, 0x1f00c,
1410 0x1f040, 0x1f044,
1411 0x1f04c, 0x1f04c,
1412 0x1f284, 0x1f290,
1413 0x1f2c0, 0x1f2c0,
1414 0x1f2e0, 0x1f2e0,
1415 0x1f300, 0x1f384,
1416 0x1f3c0, 0x1f3c8,
1417 0x1f408, 0x1f40c,
1418 0x1f440, 0x1f444,
1419 0x1f44c, 0x1f44c,
1420 0x1f684, 0x1f690,
1421 0x1f6c0, 0x1f6c0,
1422 0x1f6e0, 0x1f6e0,
1423 0x1f700, 0x1f784,
1424 0x1f7c0, 0x1f7c8,
1425 0x1f808, 0x1f80c,
1426 0x1f840, 0x1f844,
1427 0x1f84c, 0x1f84c,
1428 0x1fa84, 0x1fa90,
1429 0x1fac0, 0x1fac0,
1430 0x1fae0, 0x1fae0,
1431 0x1fb00, 0x1fb84,
1432 0x1fbc0, 0x1fbc8,
1433 0x1fc08, 0x1fc0c,
1434 0x1fc40, 0x1fc44,
1435 0x1fc4c, 0x1fc4c,
1436 0x1fe84, 0x1fe90,
1437 0x1fec0, 0x1fec0,
1438 0x1fee0, 0x1fee0,
1439 0x1ff00, 0x1ff84,
1440 0x1ffc0, 0x1ffc8,
1441 0x30000, 0x30030,
1442 0x30038, 0x30038,
1443 0x30040, 0x30040,
1444 0x30100, 0x30144,
1445 0x30190, 0x301a0,
1446 0x301a8, 0x301b8,
1447 0x301c4, 0x301c8,
1448 0x301d0, 0x301d0,
1449 0x30200, 0x30318,
1450 0x30400, 0x304b4,
1451 0x304c0, 0x3052c,
1452 0x30540, 0x3061c,
1453 0x30800, 0x30828,
1454 0x30834, 0x30834,
1455 0x308c0, 0x30908,
1456 0x30910, 0x309ac,
1457 0x30a00, 0x30a14,
1458 0x30a1c, 0x30a2c,
1459 0x30a44, 0x30a50,
1460 0x30a74, 0x30a74,
1461 0x30a7c, 0x30afc,
1462 0x30b08, 0x30c24,
1463 0x30d00, 0x30d00,
1464 0x30d08, 0x30d14,
1465 0x30d1c, 0x30d20,
1466 0x30d3c, 0x30d3c,
1467 0x30d48, 0x30d50,
1468 0x31200, 0x3120c,
1469 0x31220, 0x31220,
1470 0x31240, 0x31240,
1471 0x31600, 0x3160c,
1472 0x31a00, 0x31a1c,
1473 0x31e00, 0x31e20,
1474 0x31e38, 0x31e3c,
1475 0x31e80, 0x31e80,
1476 0x31e88, 0x31ea8,
1477 0x31eb0, 0x31eb4,
1478 0x31ec8, 0x31ed4,
1479 0x31fb8, 0x32004,
1480 0x32200, 0x32200,
1481 0x32208, 0x32240,
1482 0x32248, 0x32280,
1483 0x32288, 0x322c0,
1484 0x322c8, 0x322fc,
1485 0x32600, 0x32630,
1486 0x32a00, 0x32abc,
1487 0x32b00, 0x32b10,
1488 0x32b20, 0x32b30,
1489 0x32b40, 0x32b50,
1490 0x32b60, 0x32b70,
1491 0x33000, 0x33028,
1492 0x33030, 0x33048,
1493 0x33060, 0x33068,
1494 0x33070, 0x3309c,
1495 0x330f0, 0x33128,
1496 0x33130, 0x33148,
1497 0x33160, 0x33168,
1498 0x33170, 0x3319c,
1499 0x331f0, 0x33238,
1500 0x33240, 0x33240,
1501 0x33248, 0x33250,
1502 0x3325c, 0x33264,
1503 0x33270, 0x332b8,
1504 0x332c0, 0x332e4,
1505 0x332f8, 0x33338,
1506 0x33340, 0x33340,
1507 0x33348, 0x33350,
1508 0x3335c, 0x33364,
1509 0x33370, 0x333b8,
1510 0x333c0, 0x333e4,
1511 0x333f8, 0x33428,
1512 0x33430, 0x33448,
1513 0x33460, 0x33468,
1514 0x33470, 0x3349c,
1515 0x334f0, 0x33528,
1516 0x33530, 0x33548,
1517 0x33560, 0x33568,
1518 0x33570, 0x3359c,
1519 0x335f0, 0x33638,
1520 0x33640, 0x33640,
1521 0x33648, 0x33650,
1522 0x3365c, 0x33664,
1523 0x33670, 0x336b8,
1524 0x336c0, 0x336e4,
1525 0x336f8, 0x33738,
1526 0x33740, 0x33740,
1527 0x33748, 0x33750,
1528 0x3375c, 0x33764,
1529 0x33770, 0x337b8,
1530 0x337c0, 0x337e4,
1531 0x337f8, 0x337fc,
1532 0x33814, 0x33814,
1533 0x3382c, 0x3382c,
1534 0x33880, 0x3388c,
1535 0x338e8, 0x338ec,
1536 0x33900, 0x33928,
1537 0x33930, 0x33948,
1538 0x33960, 0x33968,
1539 0x33970, 0x3399c,
1540 0x339f0, 0x33a38,
1541 0x33a40, 0x33a40,
1542 0x33a48, 0x33a50,
1543 0x33a5c, 0x33a64,
1544 0x33a70, 0x33ab8,
1545 0x33ac0, 0x33ae4,
1546 0x33af8, 0x33b10,
1547 0x33b28, 0x33b28,
1548 0x33b3c, 0x33b50,
1549 0x33bf0, 0x33c10,
1550 0x33c28, 0x33c28,
1551 0x33c3c, 0x33c50,
1552 0x33cf0, 0x33cfc,
1553 0x34000, 0x34030,
1554 0x34038, 0x34038,
1555 0x34040, 0x34040,
1556 0x34100, 0x34144,
1557 0x34190, 0x341a0,
1558 0x341a8, 0x341b8,
1559 0x341c4, 0x341c8,
1560 0x341d0, 0x341d0,
1561 0x34200, 0x34318,
1562 0x34400, 0x344b4,
1563 0x344c0, 0x3452c,
1564 0x34540, 0x3461c,
1565 0x34800, 0x34828,
1566 0x34834, 0x34834,
1567 0x348c0, 0x34908,
1568 0x34910, 0x349ac,
1569 0x34a00, 0x34a14,
1570 0x34a1c, 0x34a2c,
1571 0x34a44, 0x34a50,
1572 0x34a74, 0x34a74,
1573 0x34a7c, 0x34afc,
1574 0x34b08, 0x34c24,
1575 0x34d00, 0x34d00,
1576 0x34d08, 0x34d14,
1577 0x34d1c, 0x34d20,
1578 0x34d3c, 0x34d3c,
1579 0x34d48, 0x34d50,
1580 0x35200, 0x3520c,
1581 0x35220, 0x35220,
1582 0x35240, 0x35240,
1583 0x35600, 0x3560c,
1584 0x35a00, 0x35a1c,
1585 0x35e00, 0x35e20,
1586 0x35e38, 0x35e3c,
1587 0x35e80, 0x35e80,
1588 0x35e88, 0x35ea8,
1589 0x35eb0, 0x35eb4,
1590 0x35ec8, 0x35ed4,
1591 0x35fb8, 0x36004,
1592 0x36200, 0x36200,
1593 0x36208, 0x36240,
1594 0x36248, 0x36280,
1595 0x36288, 0x362c0,
1596 0x362c8, 0x362fc,
1597 0x36600, 0x36630,
1598 0x36a00, 0x36abc,
1599 0x36b00, 0x36b10,
1600 0x36b20, 0x36b30,
1601 0x36b40, 0x36b50,
1602 0x36b60, 0x36b70,
1603 0x37000, 0x37028,
1604 0x37030, 0x37048,
1605 0x37060, 0x37068,
1606 0x37070, 0x3709c,
1607 0x370f0, 0x37128,
1608 0x37130, 0x37148,
1609 0x37160, 0x37168,
1610 0x37170, 0x3719c,
1611 0x371f0, 0x37238,
1612 0x37240, 0x37240,
1613 0x37248, 0x37250,
1614 0x3725c, 0x37264,
1615 0x37270, 0x372b8,
1616 0x372c0, 0x372e4,
1617 0x372f8, 0x37338,
1618 0x37340, 0x37340,
1619 0x37348, 0x37350,
1620 0x3735c, 0x37364,
1621 0x37370, 0x373b8,
1622 0x373c0, 0x373e4,
1623 0x373f8, 0x37428,
1624 0x37430, 0x37448,
1625 0x37460, 0x37468,
1626 0x37470, 0x3749c,
1627 0x374f0, 0x37528,
1628 0x37530, 0x37548,
1629 0x37560, 0x37568,
1630 0x37570, 0x3759c,
1631 0x375f0, 0x37638,
1632 0x37640, 0x37640,
1633 0x37648, 0x37650,
1634 0x3765c, 0x37664,
1635 0x37670, 0x376b8,
1636 0x376c0, 0x376e4,
1637 0x376f8, 0x37738,
1638 0x37740, 0x37740,
1639 0x37748, 0x37750,
1640 0x3775c, 0x37764,
1641 0x37770, 0x377b8,
1642 0x377c0, 0x377e4,
1643 0x377f8, 0x377fc,
1644 0x37814, 0x37814,
1645 0x3782c, 0x3782c,
1646 0x37880, 0x3788c,
1647 0x378e8, 0x378ec,
1648 0x37900, 0x37928,
1649 0x37930, 0x37948,
1650 0x37960, 0x37968,
1651 0x37970, 0x3799c,
1652 0x379f0, 0x37a38,
1653 0x37a40, 0x37a40,
1654 0x37a48, 0x37a50,
1655 0x37a5c, 0x37a64,
1656 0x37a70, 0x37ab8,
1657 0x37ac0, 0x37ae4,
1658 0x37af8, 0x37b10,
1659 0x37b28, 0x37b28,
1660 0x37b3c, 0x37b50,
1661 0x37bf0, 0x37c10,
1662 0x37c28, 0x37c28,
1663 0x37c3c, 0x37c50,
1664 0x37cf0, 0x37cfc,
1665 0x38000, 0x38030,
1666 0x38038, 0x38038,
1667 0x38040, 0x38040,
1668 0x38100, 0x38144,
1669 0x38190, 0x381a0,
1670 0x381a8, 0x381b8,
1671 0x381c4, 0x381c8,
1672 0x381d0, 0x381d0,
1673 0x38200, 0x38318,
1674 0x38400, 0x384b4,
1675 0x384c0, 0x3852c,
1676 0x38540, 0x3861c,
1677 0x38800, 0x38828,
1678 0x38834, 0x38834,
1679 0x388c0, 0x38908,
1680 0x38910, 0x389ac,
1681 0x38a00, 0x38a14,
1682 0x38a1c, 0x38a2c,
1683 0x38a44, 0x38a50,
1684 0x38a74, 0x38a74,
1685 0x38a7c, 0x38afc,
1686 0x38b08, 0x38c24,
1687 0x38d00, 0x38d00,
1688 0x38d08, 0x38d14,
1689 0x38d1c, 0x38d20,
1690 0x38d3c, 0x38d3c,
1691 0x38d48, 0x38d50,
1692 0x39200, 0x3920c,
1693 0x39220, 0x39220,
1694 0x39240, 0x39240,
1695 0x39600, 0x3960c,
1696 0x39a00, 0x39a1c,
1697 0x39e00, 0x39e20,
1698 0x39e38, 0x39e3c,
1699 0x39e80, 0x39e80,
1700 0x39e88, 0x39ea8,
1701 0x39eb0, 0x39eb4,
1702 0x39ec8, 0x39ed4,
1703 0x39fb8, 0x3a004,
1704 0x3a200, 0x3a200,
1705 0x3a208, 0x3a240,
1706 0x3a248, 0x3a280,
1707 0x3a288, 0x3a2c0,
1708 0x3a2c8, 0x3a2fc,
1709 0x3a600, 0x3a630,
1710 0x3aa00, 0x3aabc,
1711 0x3ab00, 0x3ab10,
1712 0x3ab20, 0x3ab30,
1713 0x3ab40, 0x3ab50,
1714 0x3ab60, 0x3ab70,
1715 0x3b000, 0x3b028,
1716 0x3b030, 0x3b048,
1717 0x3b060, 0x3b068,
1718 0x3b070, 0x3b09c,
1719 0x3b0f0, 0x3b128,
1720 0x3b130, 0x3b148,
1721 0x3b160, 0x3b168,
1722 0x3b170, 0x3b19c,
1723 0x3b1f0, 0x3b238,
1724 0x3b240, 0x3b240,
1725 0x3b248, 0x3b250,
1726 0x3b25c, 0x3b264,
1727 0x3b270, 0x3b2b8,
1728 0x3b2c0, 0x3b2e4,
1729 0x3b2f8, 0x3b338,
1730 0x3b340, 0x3b340,
1731 0x3b348, 0x3b350,
1732 0x3b35c, 0x3b364,
1733 0x3b370, 0x3b3b8,
1734 0x3b3c0, 0x3b3e4,
1735 0x3b3f8, 0x3b428,
1736 0x3b430, 0x3b448,
1737 0x3b460, 0x3b468,
1738 0x3b470, 0x3b49c,
1739 0x3b4f0, 0x3b528,
1740 0x3b530, 0x3b548,
1741 0x3b560, 0x3b568,
1742 0x3b570, 0x3b59c,
1743 0x3b5f0, 0x3b638,
1744 0x3b640, 0x3b640,
1745 0x3b648, 0x3b650,
1746 0x3b65c, 0x3b664,
1747 0x3b670, 0x3b6b8,
1748 0x3b6c0, 0x3b6e4,
1749 0x3b6f8, 0x3b738,
1750 0x3b740, 0x3b740,
1751 0x3b748, 0x3b750,
1752 0x3b75c, 0x3b764,
1753 0x3b770, 0x3b7b8,
1754 0x3b7c0, 0x3b7e4,
1755 0x3b7f8, 0x3b7fc,
1756 0x3b814, 0x3b814,
1757 0x3b82c, 0x3b82c,
1758 0x3b880, 0x3b88c,
1759 0x3b8e8, 0x3b8ec,
1760 0x3b900, 0x3b928,
1761 0x3b930, 0x3b948,
1762 0x3b960, 0x3b968,
1763 0x3b970, 0x3b99c,
1764 0x3b9f0, 0x3ba38,
1765 0x3ba40, 0x3ba40,
1766 0x3ba48, 0x3ba50,
1767 0x3ba5c, 0x3ba64,
1768 0x3ba70, 0x3bab8,
1769 0x3bac0, 0x3bae4,
1770 0x3baf8, 0x3bb10,
1771 0x3bb28, 0x3bb28,
1772 0x3bb3c, 0x3bb50,
1773 0x3bbf0, 0x3bc10,
1774 0x3bc28, 0x3bc28,
1775 0x3bc3c, 0x3bc50,
1776 0x3bcf0, 0x3bcfc,
1777 0x3c000, 0x3c030,
1778 0x3c038, 0x3c038,
1779 0x3c040, 0x3c040,
1780 0x3c100, 0x3c144,
1781 0x3c190, 0x3c1a0,
1782 0x3c1a8, 0x3c1b8,
1783 0x3c1c4, 0x3c1c8,
1784 0x3c1d0, 0x3c1d0,
1785 0x3c200, 0x3c318,
1786 0x3c400, 0x3c4b4,
1787 0x3c4c0, 0x3c52c,
1788 0x3c540, 0x3c61c,
1789 0x3c800, 0x3c828,
1790 0x3c834, 0x3c834,
1791 0x3c8c0, 0x3c908,
1792 0x3c910, 0x3c9ac,
1793 0x3ca00, 0x3ca14,
1794 0x3ca1c, 0x3ca2c,
1795 0x3ca44, 0x3ca50,
1796 0x3ca74, 0x3ca74,
1797 0x3ca7c, 0x3cafc,
1798 0x3cb08, 0x3cc24,
1799 0x3cd00, 0x3cd00,
1800 0x3cd08, 0x3cd14,
1801 0x3cd1c, 0x3cd20,
1802 0x3cd3c, 0x3cd3c,
1803 0x3cd48, 0x3cd50,
1804 0x3d200, 0x3d20c,
1805 0x3d220, 0x3d220,
1806 0x3d240, 0x3d240,
1807 0x3d600, 0x3d60c,
1808 0x3da00, 0x3da1c,
1809 0x3de00, 0x3de20,
1810 0x3de38, 0x3de3c,
1811 0x3de80, 0x3de80,
1812 0x3de88, 0x3dea8,
1813 0x3deb0, 0x3deb4,
1814 0x3dec8, 0x3ded4,
1815 0x3dfb8, 0x3e004,
1816 0x3e200, 0x3e200,
1817 0x3e208, 0x3e240,
1818 0x3e248, 0x3e280,
1819 0x3e288, 0x3e2c0,
1820 0x3e2c8, 0x3e2fc,
1821 0x3e600, 0x3e630,
1822 0x3ea00, 0x3eabc,
1823 0x3eb00, 0x3eb10,
1824 0x3eb20, 0x3eb30,
1825 0x3eb40, 0x3eb50,
1826 0x3eb60, 0x3eb70,
1827 0x3f000, 0x3f028,
1828 0x3f030, 0x3f048,
1829 0x3f060, 0x3f068,
1830 0x3f070, 0x3f09c,
1831 0x3f0f0, 0x3f128,
1832 0x3f130, 0x3f148,
1833 0x3f160, 0x3f168,
1834 0x3f170, 0x3f19c,
1835 0x3f1f0, 0x3f238,
1836 0x3f240, 0x3f240,
1837 0x3f248, 0x3f250,
1838 0x3f25c, 0x3f264,
1839 0x3f270, 0x3f2b8,
1840 0x3f2c0, 0x3f2e4,
1841 0x3f2f8, 0x3f338,
1842 0x3f340, 0x3f340,
1843 0x3f348, 0x3f350,
1844 0x3f35c, 0x3f364,
1845 0x3f370, 0x3f3b8,
1846 0x3f3c0, 0x3f3e4,
1847 0x3f3f8, 0x3f428,
1848 0x3f430, 0x3f448,
1849 0x3f460, 0x3f468,
1850 0x3f470, 0x3f49c,
1851 0x3f4f0, 0x3f528,
1852 0x3f530, 0x3f548,
1853 0x3f560, 0x3f568,
1854 0x3f570, 0x3f59c,
1855 0x3f5f0, 0x3f638,
1856 0x3f640, 0x3f640,
1857 0x3f648, 0x3f650,
1858 0x3f65c, 0x3f664,
1859 0x3f670, 0x3f6b8,
1860 0x3f6c0, 0x3f6e4,
1861 0x3f6f8, 0x3f738,
1862 0x3f740, 0x3f740,
1863 0x3f748, 0x3f750,
1864 0x3f75c, 0x3f764,
1865 0x3f770, 0x3f7b8,
1866 0x3f7c0, 0x3f7e4,
1867 0x3f7f8, 0x3f7fc,
1868 0x3f814, 0x3f814,
1869 0x3f82c, 0x3f82c,
1870 0x3f880, 0x3f88c,
1871 0x3f8e8, 0x3f8ec,
1872 0x3f900, 0x3f928,
1873 0x3f930, 0x3f948,
1874 0x3f960, 0x3f968,
1875 0x3f970, 0x3f99c,
1876 0x3f9f0, 0x3fa38,
1877 0x3fa40, 0x3fa40,
1878 0x3fa48, 0x3fa50,
1879 0x3fa5c, 0x3fa64,
1880 0x3fa70, 0x3fab8,
1881 0x3fac0, 0x3fae4,
1882 0x3faf8, 0x3fb10,
1883 0x3fb28, 0x3fb28,
1884 0x3fb3c, 0x3fb50,
1885 0x3fbf0, 0x3fc10,
1886 0x3fc28, 0x3fc28,
1887 0x3fc3c, 0x3fc50,
1888 0x3fcf0, 0x3fcfc,
1889 0x40000, 0x4000c,
1890 0x40040, 0x40050,
1891 0x40060, 0x40068,
1892 0x4007c, 0x4008c,
1893 0x40094, 0x400b0,
1894 0x400c0, 0x40144,
1895 0x40180, 0x4018c,
1896 0x40200, 0x40254,
1897 0x40260, 0x40264,
1898 0x40270, 0x40288,
1899 0x40290, 0x40298,
1900 0x402ac, 0x402c8,
1901 0x402d0, 0x402e0,
1902 0x402f0, 0x402f0,
1903 0x40300, 0x4033c,
1904 0x403f8, 0x403fc,
1905 0x41304, 0x413c4,
1906 0x41400, 0x4140c,
1907 0x41414, 0x4141c,
1908 0x41480, 0x414d0,
1909 0x44000, 0x44054,
1910 0x4405c, 0x44078,
1911 0x440c0, 0x44174,
1912 0x44180, 0x441ac,
1913 0x441b4, 0x441b8,
1914 0x441c0, 0x44254,
1915 0x4425c, 0x44278,
1916 0x442c0, 0x44374,
1917 0x44380, 0x443ac,
1918 0x443b4, 0x443b8,
1919 0x443c0, 0x44454,
1920 0x4445c, 0x44478,
1921 0x444c0, 0x44574,
1922 0x44580, 0x445ac,
1923 0x445b4, 0x445b8,
1924 0x445c0, 0x44654,
1925 0x4465c, 0x44678,
1926 0x446c0, 0x44774,
1927 0x44780, 0x447ac,
1928 0x447b4, 0x447b8,
1929 0x447c0, 0x44854,
1930 0x4485c, 0x44878,
1931 0x448c0, 0x44974,
1932 0x44980, 0x449ac,
1933 0x449b4, 0x449b8,
1934 0x449c0, 0x449fc,
1935 0x45000, 0x45004,
1936 0x45010, 0x45030,
1937 0x45040, 0x45060,
1938 0x45068, 0x45068,
1939 0x45080, 0x45084,
1940 0x450a0, 0x450b0,
1941 0x45200, 0x45204,
1942 0x45210, 0x45230,
1943 0x45240, 0x45260,
1944 0x45268, 0x45268,
1945 0x45280, 0x45284,
1946 0x452a0, 0x452b0,
1947 0x460c0, 0x460e4,
1948 0x47000, 0x4703c,
1949 0x47044, 0x4708c,
1950 0x47200, 0x47250,
1951 0x47400, 0x47408,
1952 0x47414, 0x47420,
1953 0x47600, 0x47618,
1954 0x47800, 0x47814,
1955 0x48000, 0x4800c,
1956 0x48040, 0x48050,
1957 0x48060, 0x48068,
1958 0x4807c, 0x4808c,
1959 0x48094, 0x480b0,
1960 0x480c0, 0x48144,
1961 0x48180, 0x4818c,
1962 0x48200, 0x48254,
1963 0x48260, 0x48264,
1964 0x48270, 0x48288,
1965 0x48290, 0x48298,
1966 0x482ac, 0x482c8,
1967 0x482d0, 0x482e0,
1968 0x482f0, 0x482f0,
1969 0x48300, 0x4833c,
1970 0x483f8, 0x483fc,
1971 0x49304, 0x493c4,
1972 0x49400, 0x4940c,
1973 0x49414, 0x4941c,
1974 0x49480, 0x494d0,
1975 0x4c000, 0x4c054,
1976 0x4c05c, 0x4c078,
1977 0x4c0c0, 0x4c174,
1978 0x4c180, 0x4c1ac,
1979 0x4c1b4, 0x4c1b8,
1980 0x4c1c0, 0x4c254,
1981 0x4c25c, 0x4c278,
1982 0x4c2c0, 0x4c374,
1983 0x4c380, 0x4c3ac,
1984 0x4c3b4, 0x4c3b8,
1985 0x4c3c0, 0x4c454,
1986 0x4c45c, 0x4c478,
1987 0x4c4c0, 0x4c574,
1988 0x4c580, 0x4c5ac,
1989 0x4c5b4, 0x4c5b8,
1990 0x4c5c0, 0x4c654,
1991 0x4c65c, 0x4c678,
1992 0x4c6c0, 0x4c774,
1993 0x4c780, 0x4c7ac,
1994 0x4c7b4, 0x4c7b8,
1995 0x4c7c0, 0x4c854,
1996 0x4c85c, 0x4c878,
1997 0x4c8c0, 0x4c974,
1998 0x4c980, 0x4c9ac,
1999 0x4c9b4, 0x4c9b8,
2000 0x4c9c0, 0x4c9fc,
2001 0x4d000, 0x4d004,
2002 0x4d010, 0x4d030,
2003 0x4d040, 0x4d060,
2004 0x4d068, 0x4d068,
2005 0x4d080, 0x4d084,
2006 0x4d0a0, 0x4d0b0,
2007 0x4d200, 0x4d204,
2008 0x4d210, 0x4d230,
2009 0x4d240, 0x4d260,
2010 0x4d268, 0x4d268,
2011 0x4d280, 0x4d284,
2012 0x4d2a0, 0x4d2b0,
2013 0x4e0c0, 0x4e0e4,
2014 0x4f000, 0x4f03c,
2015 0x4f044, 0x4f08c,
2016 0x4f200, 0x4f250,
2017 0x4f400, 0x4f408,
2018 0x4f414, 0x4f420,
2019 0x4f600, 0x4f618,
2020 0x4f800, 0x4f814,
2021 0x50000, 0x50084,
2022 0x50090, 0x500cc,
2023 0x50400, 0x50400,
2024 0x50800, 0x50884,
2025 0x50890, 0x508cc,
2026 0x50c00, 0x50c00,
2027 0x51000, 0x5101c,
2028 0x51300, 0x51308,
2029 };
2030
2031 static const unsigned int t6_reg_ranges[] = {
2032 0x1008, 0x101c,
2033 0x1024, 0x10a8,
2034 0x10b4, 0x10f8,
2035 0x1100, 0x1114,
2036 0x111c, 0x112c,
2037 0x1138, 0x113c,
2038 0x1144, 0x114c,
2039 0x1180, 0x1184,
2040 0x1190, 0x1194,
2041 0x11a0, 0x11a4,
2042 0x11b0, 0x11b4,
2043 0x11fc, 0x1258,
2044 0x1280, 0x12d4,
2045 0x12d9, 0x12d9,
2046 0x12de, 0x12de,
2047 0x12e3, 0x12e3,
2048 0x12e8, 0x133c,
2049 0x1800, 0x18fc,
2050 0x3000, 0x302c,
2051 0x3060, 0x30b0,
2052 0x30b8, 0x30d8,
2053 0x30e0, 0x30fc,
2054 0x3140, 0x357c,
2055 0x35a8, 0x35cc,
2056 0x35ec, 0x35ec,
2057 0x3600, 0x5624,
2058 0x56cc, 0x56ec,
2059 0x56f4, 0x5720,
2060 0x5728, 0x575c,
2061 0x580c, 0x5814,
2062 0x5890, 0x589c,
2063 0x58a4, 0x58ac,
2064 0x58b8, 0x58bc,
2065 0x5940, 0x595c,
2066 0x5980, 0x598c,
2067 0x59b0, 0x59c8,
2068 0x59d0, 0x59dc,
2069 0x59fc, 0x5a18,
2070 0x5a60, 0x5a6c,
2071 0x5a80, 0x5a8c,
2072 0x5a94, 0x5a9c,
2073 0x5b94, 0x5bfc,
2074 0x5c10, 0x5e48,
2075 0x5e50, 0x5e94,
2076 0x5ea0, 0x5eb0,
2077 0x5ec0, 0x5ec0,
2078 0x5ec8, 0x5ed0,
2079 0x6000, 0x6020,
2080 0x6028, 0x6040,
2081 0x6058, 0x609c,
2082 0x60a8, 0x619c,
2083 0x7700, 0x7798,
2084 0x77c0, 0x7880,
2085 0x78cc, 0x78fc,
2086 0x7b00, 0x7b58,
2087 0x7b60, 0x7b84,
2088 0x7b8c, 0x7c54,
2089 0x7d00, 0x7d38,
2090 0x7d40, 0x7d84,
2091 0x7d8c, 0x7ddc,
2092 0x7de4, 0x7e04,
2093 0x7e10, 0x7e1c,
2094 0x7e24, 0x7e38,
2095 0x7e40, 0x7e44,
2096 0x7e4c, 0x7e78,
2097 0x7e80, 0x7edc,
2098 0x7ee8, 0x7efc,
2099 0x8dc0, 0x8de4,
2100 0x8df8, 0x8e04,
2101 0x8e10, 0x8e84,
2102 0x8ea0, 0x8f88,
2103 0x8fb8, 0x9058,
2104 0x9060, 0x9060,
2105 0x9068, 0x90f8,
2106 0x9100, 0x9124,
2107 0x9400, 0x9470,
2108 0x9600, 0x9600,
2109 0x9608, 0x9638,
2110 0x9640, 0x9704,
2111 0x9710, 0x971c,
2112 0x9800, 0x9808,
2113 0x9820, 0x983c,
2114 0x9850, 0x9864,
2115 0x9c00, 0x9c6c,
2116 0x9c80, 0x9cec,
2117 0x9d00, 0x9d6c,
2118 0x9d80, 0x9dec,
2119 0x9e00, 0x9e6c,
2120 0x9e80, 0x9eec,
2121 0x9f00, 0x9f6c,
2122 0x9f80, 0xa020,
2123 0xd004, 0xd03c,
2124 0xd100, 0xd118,
2125 0xd200, 0xd214,
2126 0xd220, 0xd234,
2127 0xd240, 0xd254,
2128 0xd260, 0xd274,
2129 0xd280, 0xd294,
2130 0xd2a0, 0xd2b4,
2131 0xd2c0, 0xd2d4,
2132 0xd2e0, 0xd2f4,
2133 0xd300, 0xd31c,
2134 0xdfc0, 0xdfe0,
2135 0xe000, 0xf008,
2136 0x11000, 0x11014,
2137 0x11048, 0x1106c,
2138 0x11074, 0x11088,
2139 0x11098, 0x11120,
2140 0x1112c, 0x1117c,
2141 0x11190, 0x112e0,
2142 0x11300, 0x1130c,
2143 0x12000, 0x1206c,
2144 0x19040, 0x1906c,
2145 0x19078, 0x19080,
2146 0x1908c, 0x190e8,
2147 0x190f0, 0x190f8,
2148 0x19100, 0x19110,
2149 0x19120, 0x19124,
2150 0x19150, 0x19194,
2151 0x1919c, 0x191b0,
2152 0x191d0, 0x191e8,
2153 0x19238, 0x19290,
2154 0x192a4, 0x192b0,
2155 0x192bc, 0x192bc,
2156 0x19348, 0x1934c,
2157 0x193f8, 0x19418,
2158 0x19420, 0x19428,
2159 0x19430, 0x19444,
2160 0x1944c, 0x1946c,
2161 0x19474, 0x19474,
2162 0x19490, 0x194cc,
2163 0x194f0, 0x194f8,
2164 0x19c00, 0x19c48,
2165 0x19c50, 0x19c80,
2166 0x19c94, 0x19c98,
2167 0x19ca0, 0x19cbc,
2168 0x19ce4, 0x19ce4,
2169 0x19cf0, 0x19cf8,
2170 0x19d00, 0x19d28,
2171 0x19d50, 0x19d78,
2172 0x19d94, 0x19d98,
2173 0x19da0, 0x19dc8,
2174 0x19df0, 0x19e10,
2175 0x19e50, 0x19e6c,
2176 0x19ea0, 0x19ebc,
2177 0x19ec4, 0x19ef4,
2178 0x19f04, 0x19f2c,
2179 0x19f34, 0x19f34,
2180 0x19f40, 0x19f50,
2181 0x19f90, 0x19fac,
2182 0x19fc4, 0x19fc8,
2183 0x19fd0, 0x19fe4,
2184 0x1a000, 0x1a004,
2185 0x1a010, 0x1a06c,
2186 0x1a0b0, 0x1a0e4,
2187 0x1a0ec, 0x1a0f8,
2188 0x1a100, 0x1a108,
2189 0x1a114, 0x1a120,
2190 0x1a128, 0x1a130,
2191 0x1a138, 0x1a138,
2192 0x1a190, 0x1a1c4,
2193 0x1a1fc, 0x1a1fc,
2194 0x1e008, 0x1e00c,
2195 0x1e040, 0x1e044,
2196 0x1e04c, 0x1e04c,
2197 0x1e284, 0x1e290,
2198 0x1e2c0, 0x1e2c0,
2199 0x1e2e0, 0x1e2e0,
2200 0x1e300, 0x1e384,
2201 0x1e3c0, 0x1e3c8,
2202 0x1e408, 0x1e40c,
2203 0x1e440, 0x1e444,
2204 0x1e44c, 0x1e44c,
2205 0x1e684, 0x1e690,
2206 0x1e6c0, 0x1e6c0,
2207 0x1e6e0, 0x1e6e0,
2208 0x1e700, 0x1e784,
2209 0x1e7c0, 0x1e7c8,
2210 0x1e808, 0x1e80c,
2211 0x1e840, 0x1e844,
2212 0x1e84c, 0x1e84c,
2213 0x1ea84, 0x1ea90,
2214 0x1eac0, 0x1eac0,
2215 0x1eae0, 0x1eae0,
2216 0x1eb00, 0x1eb84,
2217 0x1ebc0, 0x1ebc8,
2218 0x1ec08, 0x1ec0c,
2219 0x1ec40, 0x1ec44,
2220 0x1ec4c, 0x1ec4c,
2221 0x1ee84, 0x1ee90,
2222 0x1eec0, 0x1eec0,
2223 0x1eee0, 0x1eee0,
2224 0x1ef00, 0x1ef84,
2225 0x1efc0, 0x1efc8,
2226 0x1f008, 0x1f00c,
2227 0x1f040, 0x1f044,
2228 0x1f04c, 0x1f04c,
2229 0x1f284, 0x1f290,
2230 0x1f2c0, 0x1f2c0,
2231 0x1f2e0, 0x1f2e0,
2232 0x1f300, 0x1f384,
2233 0x1f3c0, 0x1f3c8,
2234 0x1f408, 0x1f40c,
2235 0x1f440, 0x1f444,
2236 0x1f44c, 0x1f44c,
2237 0x1f684, 0x1f690,
2238 0x1f6c0, 0x1f6c0,
2239 0x1f6e0, 0x1f6e0,
2240 0x1f700, 0x1f784,
2241 0x1f7c0, 0x1f7c8,
2242 0x1f808, 0x1f80c,
2243 0x1f840, 0x1f844,
2244 0x1f84c, 0x1f84c,
2245 0x1fa84, 0x1fa90,
2246 0x1fac0, 0x1fac0,
2247 0x1fae0, 0x1fae0,
2248 0x1fb00, 0x1fb84,
2249 0x1fbc0, 0x1fbc8,
2250 0x1fc08, 0x1fc0c,
2251 0x1fc40, 0x1fc44,
2252 0x1fc4c, 0x1fc4c,
2253 0x1fe84, 0x1fe90,
2254 0x1fec0, 0x1fec0,
2255 0x1fee0, 0x1fee0,
2256 0x1ff00, 0x1ff84,
2257 0x1ffc0, 0x1ffc8,
2258 0x30000, 0x30030,
2259 0x30038, 0x30038,
2260 0x30040, 0x30040,
2261 0x30048, 0x30048,
2262 0x30050, 0x30050,
2263 0x3005c, 0x30060,
2264 0x30068, 0x30068,
2265 0x30070, 0x30070,
2266 0x30100, 0x30168,
2267 0x30190, 0x301a0,
2268 0x301a8, 0x301b8,
2269 0x301c4, 0x301c8,
2270 0x301d0, 0x301d0,
2271 0x30200, 0x30320,
2272 0x30400, 0x304b4,
2273 0x304c0, 0x3052c,
2274 0x30540, 0x3061c,
2275 0x30800, 0x308a0,
2276 0x308c0, 0x30908,
2277 0x30910, 0x309b8,
2278 0x30a00, 0x30a04,
2279 0x30a0c, 0x30a14,
2280 0x30a1c, 0x30a2c,
2281 0x30a44, 0x30a50,
2282 0x30a74, 0x30a74,
2283 0x30a7c, 0x30afc,
2284 0x30b08, 0x30c24,
2285 0x30d00, 0x30d14,
2286 0x30d1c, 0x30d3c,
2287 0x30d44, 0x30d4c,
2288 0x30d54, 0x30d74,
2289 0x30d7c, 0x30d7c,
2290 0x30de0, 0x30de0,
2291 0x30e00, 0x30ed4,
2292 0x30f00, 0x30fa4,
2293 0x30fc0, 0x30fc4,
2294 0x31000, 0x31004,
2295 0x31080, 0x310fc,
2296 0x31208, 0x31220,
2297 0x3123c, 0x31254,
2298 0x31300, 0x31300,
2299 0x31308, 0x3131c,
2300 0x31338, 0x3133c,
2301 0x31380, 0x31380,
2302 0x31388, 0x313a8,
2303 0x313b4, 0x313b4,
2304 0x31400, 0x31420,
2305 0x31438, 0x3143c,
2306 0x31480, 0x31480,
2307 0x314a8, 0x314a8,
2308 0x314b0, 0x314b4,
2309 0x314c8, 0x314d4,
2310 0x31a40, 0x31a4c,
2311 0x31af0, 0x31b20,
2312 0x31b38, 0x31b3c,
2313 0x31b80, 0x31b80,
2314 0x31ba8, 0x31ba8,
2315 0x31bb0, 0x31bb4,
2316 0x31bc8, 0x31bd4,
2317 0x32140, 0x3218c,
2318 0x321f0, 0x321f4,
2319 0x32200, 0x32200,
2320 0x32218, 0x32218,
2321 0x32400, 0x32400,
2322 0x32408, 0x3241c,
2323 0x32618, 0x32620,
2324 0x32664, 0x32664,
2325 0x326a8, 0x326a8,
2326 0x326ec, 0x326ec,
2327 0x32a00, 0x32abc,
2328 0x32b00, 0x32b38,
2329 0x32b40, 0x32b58,
2330 0x32b60, 0x32b78,
2331 0x32c00, 0x32c00,
2332 0x32c08, 0x32c3c,
2333 0x32e00, 0x32e2c,
2334 0x32f00, 0x32f2c,
2335 0x33000, 0x3302c,
2336 0x33034, 0x33050,
2337 0x33058, 0x33058,
2338 0x33060, 0x3308c,
2339 0x3309c, 0x330ac,
2340 0x330c0, 0x330c0,
2341 0x330c8, 0x330d0,
2342 0x330d8, 0x330e0,
2343 0x330ec, 0x3312c,
2344 0x33134, 0x33150,
2345 0x33158, 0x33158,
2346 0x33160, 0x3318c,
2347 0x3319c, 0x331ac,
2348 0x331c0, 0x331c0,
2349 0x331c8, 0x331d0,
2350 0x331d8, 0x331e0,
2351 0x331ec, 0x33290,
2352 0x33298, 0x332c4,
2353 0x332e4, 0x33390,
2354 0x33398, 0x333c4,
2355 0x333e4, 0x3342c,
2356 0x33434, 0x33450,
2357 0x33458, 0x33458,
2358 0x33460, 0x3348c,
2359 0x3349c, 0x334ac,
2360 0x334c0, 0x334c0,
2361 0x334c8, 0x334d0,
2362 0x334d8, 0x334e0,
2363 0x334ec, 0x3352c,
2364 0x33534, 0x33550,
2365 0x33558, 0x33558,
2366 0x33560, 0x3358c,
2367 0x3359c, 0x335ac,
2368 0x335c0, 0x335c0,
2369 0x335c8, 0x335d0,
2370 0x335d8, 0x335e0,
2371 0x335ec, 0x33690,
2372 0x33698, 0x336c4,
2373 0x336e4, 0x33790,
2374 0x33798, 0x337c4,
2375 0x337e4, 0x337fc,
2376 0x33814, 0x33814,
2377 0x33854, 0x33868,
2378 0x33880, 0x3388c,
2379 0x338c0, 0x338d0,
2380 0x338e8, 0x338ec,
2381 0x33900, 0x3392c,
2382 0x33934, 0x33950,
2383 0x33958, 0x33958,
2384 0x33960, 0x3398c,
2385 0x3399c, 0x339ac,
2386 0x339c0, 0x339c0,
2387 0x339c8, 0x339d0,
2388 0x339d8, 0x339e0,
2389 0x339ec, 0x33a90,
2390 0x33a98, 0x33ac4,
2391 0x33ae4, 0x33b10,
2392 0x33b24, 0x33b28,
2393 0x33b38, 0x33b50,
2394 0x33bf0, 0x33c10,
2395 0x33c24, 0x33c28,
2396 0x33c38, 0x33c50,
2397 0x33cf0, 0x33cfc,
2398 0x34000, 0x34030,
2399 0x34038, 0x34038,
2400 0x34040, 0x34040,
2401 0x34048, 0x34048,
2402 0x34050, 0x34050,
2403 0x3405c, 0x34060,
2404 0x34068, 0x34068,
2405 0x34070, 0x34070,
2406 0x34100, 0x34168,
2407 0x34190, 0x341a0,
2408 0x341a8, 0x341b8,
2409 0x341c4, 0x341c8,
2410 0x341d0, 0x341d0,
2411 0x34200, 0x34320,
2412 0x34400, 0x344b4,
2413 0x344c0, 0x3452c,
2414 0x34540, 0x3461c,
2415 0x34800, 0x348a0,
2416 0x348c0, 0x34908,
2417 0x34910, 0x349b8,
2418 0x34a00, 0x34a04,
2419 0x34a0c, 0x34a14,
2420 0x34a1c, 0x34a2c,
2421 0x34a44, 0x34a50,
2422 0x34a74, 0x34a74,
2423 0x34a7c, 0x34afc,
2424 0x34b08, 0x34c24,
2425 0x34d00, 0x34d14,
2426 0x34d1c, 0x34d3c,
2427 0x34d44, 0x34d4c,
2428 0x34d54, 0x34d74,
2429 0x34d7c, 0x34d7c,
2430 0x34de0, 0x34de0,
2431 0x34e00, 0x34ed4,
2432 0x34f00, 0x34fa4,
2433 0x34fc0, 0x34fc4,
2434 0x35000, 0x35004,
2435 0x35080, 0x350fc,
2436 0x35208, 0x35220,
2437 0x3523c, 0x35254,
2438 0x35300, 0x35300,
2439 0x35308, 0x3531c,
2440 0x35338, 0x3533c,
2441 0x35380, 0x35380,
2442 0x35388, 0x353a8,
2443 0x353b4, 0x353b4,
2444 0x35400, 0x35420,
2445 0x35438, 0x3543c,
2446 0x35480, 0x35480,
2447 0x354a8, 0x354a8,
2448 0x354b0, 0x354b4,
2449 0x354c8, 0x354d4,
2450 0x35a40, 0x35a4c,
2451 0x35af0, 0x35b20,
2452 0x35b38, 0x35b3c,
2453 0x35b80, 0x35b80,
2454 0x35ba8, 0x35ba8,
2455 0x35bb0, 0x35bb4,
2456 0x35bc8, 0x35bd4,
2457 0x36140, 0x3618c,
2458 0x361f0, 0x361f4,
2459 0x36200, 0x36200,
2460 0x36218, 0x36218,
2461 0x36400, 0x36400,
2462 0x36408, 0x3641c,
2463 0x36618, 0x36620,
2464 0x36664, 0x36664,
2465 0x366a8, 0x366a8,
2466 0x366ec, 0x366ec,
2467 0x36a00, 0x36abc,
2468 0x36b00, 0x36b38,
2469 0x36b40, 0x36b58,
2470 0x36b60, 0x36b78,
2471 0x36c00, 0x36c00,
2472 0x36c08, 0x36c3c,
2473 0x36e00, 0x36e2c,
2474 0x36f00, 0x36f2c,
2475 0x37000, 0x3702c,
2476 0x37034, 0x37050,
2477 0x37058, 0x37058,
2478 0x37060, 0x3708c,
2479 0x3709c, 0x370ac,
2480 0x370c0, 0x370c0,
2481 0x370c8, 0x370d0,
2482 0x370d8, 0x370e0,
2483 0x370ec, 0x3712c,
2484 0x37134, 0x37150,
2485 0x37158, 0x37158,
2486 0x37160, 0x3718c,
2487 0x3719c, 0x371ac,
2488 0x371c0, 0x371c0,
2489 0x371c8, 0x371d0,
2490 0x371d8, 0x371e0,
2491 0x371ec, 0x37290,
2492 0x37298, 0x372c4,
2493 0x372e4, 0x37390,
2494 0x37398, 0x373c4,
2495 0x373e4, 0x3742c,
2496 0x37434, 0x37450,
2497 0x37458, 0x37458,
2498 0x37460, 0x3748c,
2499 0x3749c, 0x374ac,
2500 0x374c0, 0x374c0,
2501 0x374c8, 0x374d0,
2502 0x374d8, 0x374e0,
2503 0x374ec, 0x3752c,
2504 0x37534, 0x37550,
2505 0x37558, 0x37558,
2506 0x37560, 0x3758c,
2507 0x3759c, 0x375ac,
2508 0x375c0, 0x375c0,
2509 0x375c8, 0x375d0,
2510 0x375d8, 0x375e0,
2511 0x375ec, 0x37690,
2512 0x37698, 0x376c4,
2513 0x376e4, 0x37790,
2514 0x37798, 0x377c4,
2515 0x377e4, 0x377fc,
2516 0x37814, 0x37814,
2517 0x37854, 0x37868,
2518 0x37880, 0x3788c,
2519 0x378c0, 0x378d0,
2520 0x378e8, 0x378ec,
2521 0x37900, 0x3792c,
2522 0x37934, 0x37950,
2523 0x37958, 0x37958,
2524 0x37960, 0x3798c,
2525 0x3799c, 0x379ac,
2526 0x379c0, 0x379c0,
2527 0x379c8, 0x379d0,
2528 0x379d8, 0x379e0,
2529 0x379ec, 0x37a90,
2530 0x37a98, 0x37ac4,
2531 0x37ae4, 0x37b10,
2532 0x37b24, 0x37b28,
2533 0x37b38, 0x37b50,
2534 0x37bf0, 0x37c10,
2535 0x37c24, 0x37c28,
2536 0x37c38, 0x37c50,
2537 0x37cf0, 0x37cfc,
2538 0x40040, 0x40040,
2539 0x40080, 0x40084,
2540 0x40100, 0x40100,
2541 0x40140, 0x401bc,
2542 0x40200, 0x40214,
2543 0x40228, 0x40228,
2544 0x40240, 0x40258,
2545 0x40280, 0x40280,
2546 0x40304, 0x40304,
2547 0x40330, 0x4033c,
2548 0x41304, 0x413b8,
2549 0x413c0, 0x413c8,
2550 0x413d0, 0x413dc,
2551 0x413f0, 0x413f0,
2552 0x41400, 0x4140c,
2553 0x41414, 0x4141c,
2554 0x41480, 0x414d0,
2555 0x44000, 0x4407c,
2556 0x440c0, 0x441ac,
2557 0x441b4, 0x4427c,
2558 0x442c0, 0x443ac,
2559 0x443b4, 0x4447c,
2560 0x444c0, 0x445ac,
2561 0x445b4, 0x4467c,
2562 0x446c0, 0x447ac,
2563 0x447b4, 0x4487c,
2564 0x448c0, 0x449ac,
2565 0x449b4, 0x44a7c,
2566 0x44ac0, 0x44bac,
2567 0x44bb4, 0x44c7c,
2568 0x44cc0, 0x44dac,
2569 0x44db4, 0x44e7c,
2570 0x44ec0, 0x44fac,
2571 0x44fb4, 0x4507c,
2572 0x450c0, 0x451ac,
2573 0x451b4, 0x451fc,
2574 0x45800, 0x45804,
2575 0x45810, 0x45830,
2576 0x45840, 0x45860,
2577 0x45868, 0x45868,
2578 0x45880, 0x45884,
2579 0x458a0, 0x458b0,
2580 0x45a00, 0x45a04,
2581 0x45a10, 0x45a30,
2582 0x45a40, 0x45a60,
2583 0x45a68, 0x45a68,
2584 0x45a80, 0x45a84,
2585 0x45aa0, 0x45ab0,
2586 0x460c0, 0x460e4,
2587 0x47000, 0x4703c,
2588 0x47044, 0x4708c,
2589 0x47200, 0x47250,
2590 0x47400, 0x47408,
2591 0x47414, 0x47420,
2592 0x47600, 0x47618,
2593 0x47800, 0x47814,
2594 0x47820, 0x4782c,
2595 0x50000, 0x50084,
2596 0x50090, 0x500cc,
2597 0x50300, 0x50384,
2598 0x50400, 0x50400,
2599 0x50800, 0x50884,
2600 0x50890, 0x508cc,
2601 0x50b00, 0x50b84,
2602 0x50c00, 0x50c00,
2603 0x51000, 0x51020,
2604 0x51028, 0x510b0,
2605 0x51300, 0x51324,
2606 };
2607
2608 u32 *buf_end = (u32 *)((char *)buf + buf_size);
2609 const unsigned int *reg_ranges;
2610 int reg_ranges_size, range;
2611 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2612
2613 /* Select the right set of register ranges to dump depending on the
2614 * adapter chip type.
2615 */
2616 switch (chip_version) {
2617 case CHELSIO_T4:
2618 reg_ranges = t4_reg_ranges;
2619 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2620 break;
2621
2622 case CHELSIO_T5:
2623 reg_ranges = t5_reg_ranges;
2624 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2625 break;
2626
2627 case CHELSIO_T6:
2628 reg_ranges = t6_reg_ranges;
2629 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2630 break;
2631
2632 default:
2633 dev_err(adap->pdev_dev,
2634 "Unsupported chip version %d\n", chip_version);
2635 return;
2636 }
2637
2638 /* Clear the register buffer and insert the appropriate register
2639 * values selected by the above register ranges.
2640 */
2641 memset(buf, 0, buf_size);
2642 for (range = 0; range < reg_ranges_size; range += 2) {
2643 unsigned int reg = reg_ranges[range];
2644 unsigned int last_reg = reg_ranges[range + 1];
2645 u32 *bufp = (u32 *)((char *)buf + reg);
2646
2647 /* Iterate across the register range filling in the register
2648 * buffer but don't write past the end of the register buffer.
2649 */
2650 while (reg <= last_reg && bufp < buf_end) {
2651 *bufp++ = t4_read_reg(adap, reg);
2652 reg += sizeof(u32);
2653 }
2654 }
2655 }
2656
2657 #define EEPROM_STAT_ADDR 0x7bfc
2658 #define VPD_SIZE 0x800
2659 #define VPD_BASE 0x400
2660 #define VPD_BASE_OLD 0
2661 #define VPD_LEN 1024
2662 #define CHELSIO_VPD_UNIQUE_ID 0x82
2663
2664 /**
2665 * t4_seeprom_wp - enable/disable EEPROM write protection
2666 * @adapter: the adapter
2667 * @enable: whether to enable or disable write protection
2668 *
2669 * Enables or disables write protection on the serial EEPROM.
2670 */
2671 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2672 {
2673 unsigned int v = enable ? 0xc : 0;
2674 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2675 return ret < 0 ? ret : 0;
2676 }
2677
2678 /**
2679 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2680 * @adapter: adapter to read
2681 * @p: where to store the parameters
2682 *
2683 * Reads card parameters stored in VPD EEPROM.
2684 */
2685 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2686 {
2687 int i, ret = 0, addr;
2688 int ec, sn, pn, na;
2689 u8 *vpd, csum;
2690 unsigned int vpdr_len, kw_offset, id_len;
2691
2692 vpd = vmalloc(VPD_LEN);
2693 if (!vpd)
2694 return -ENOMEM;
2695
2696 /* We have two VPD data structures stored in the adapter VPD area.
2697 * By default, Linux calculates the size of the VPD area by traversing
2698 * the first VPD area at offset 0x0, so we need to tell the OS what
2699 * our real VPD size is.
2700 */
2701 ret = pci_set_vpd_size(adapter->pdev, VPD_SIZE);
2702 if (ret < 0)
2703 goto out;
2704
2705 /* Card information normally starts at VPD_BASE but early cards had
2706 * it at 0.
2707 */
2708 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2709 if (ret < 0)
2710 goto out;
2711
2712 /* The VPD shall have a unique identifier specified by the PCI SIG.
2713 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2714 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2715 * is expected to automatically put this entry at the
2716 * beginning of the VPD.
2717 */
2718 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2719
2720 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2721 if (ret < 0)
2722 goto out;
2723
2724 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2725 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2726 ret = -EINVAL;
2727 goto out;
2728 }
2729
2730 id_len = pci_vpd_lrdt_size(vpd);
2731 if (id_len > ID_LEN)
2732 id_len = ID_LEN;
2733
2734 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2735 if (i < 0) {
2736 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2737 ret = -EINVAL;
2738 goto out;
2739 }
2740
2741 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2742 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2743 if (vpdr_len + kw_offset > VPD_LEN) {
2744 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2745 ret = -EINVAL;
2746 goto out;
2747 }
2748
2749 #define FIND_VPD_KW(var, name) do { \
2750 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2751 if (var < 0) { \
2752 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2753 ret = -EINVAL; \
2754 goto out; \
2755 } \
2756 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2757 } while (0)
2758
2759 FIND_VPD_KW(i, "RV");
2760 for (csum = 0; i >= 0; i--)
2761 csum += vpd[i];
2762
2763 if (csum) {
2764 dev_err(adapter->pdev_dev,
2765 "corrupted VPD EEPROM, actual csum %u\n", csum);
2766 ret = -EINVAL;
2767 goto out;
2768 }
2769
2770 FIND_VPD_KW(ec, "EC");
2771 FIND_VPD_KW(sn, "SN");
2772 FIND_VPD_KW(pn, "PN");
2773 FIND_VPD_KW(na, "NA");
2774 #undef FIND_VPD_KW
2775
2776 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2777 strim(p->id);
2778 memcpy(p->ec, vpd + ec, EC_LEN);
2779 strim(p->ec);
2780 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2781 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2782 strim(p->sn);
2783 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2784 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2785 strim(p->pn);
2786 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2787 strim((char *)p->na);
2788
2789 out:
2790 vfree(vpd);
2791 return ret < 0 ? ret : 0;
2792 }
2793
2794 /**
2795 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2796 * @adapter: adapter to read
2797 * @p: where to store the parameters
2798 *
2799 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2800 * Clock. This can only be called after a connection to the firmware
2801 * is established.
2802 */
2803 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2804 {
2805 u32 cclk_param, cclk_val;
2806 int ret;
2807
2808 /* Grab the raw VPD parameters.
2809 */
2810 ret = t4_get_raw_vpd_params(adapter, p);
2811 if (ret)
2812 return ret;
2813
2814 /* Ask firmware for the Core Clock since it knows how to translate the
2815 * Reference Clock ('V2') VPD field into a Core Clock value ...
2816 */
2817 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2818 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2819 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2820 1, &cclk_param, &cclk_val);
2821
2822 if (ret)
2823 return ret;
2824 p->cclk = cclk_val;
2825
2826 return 0;
2827 }
2828
2829 /* serial flash and firmware constants */
2830 enum {
2831 SF_ATTEMPTS = 10, /* max retries for SF operations */
2832
2833 /* flash command opcodes */
2834 SF_PROG_PAGE = 2, /* program page */
2835 SF_WR_DISABLE = 4, /* disable writes */
2836 SF_RD_STATUS = 5, /* read status register */
2837 SF_WR_ENABLE = 6, /* enable writes */
2838 SF_RD_DATA_FAST = 0xb, /* read flash */
2839 SF_RD_ID = 0x9f, /* read ID */
2840 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2841
2842 FW_MAX_SIZE = 16 * SF_SEC_SIZE,
2843 };
2844
2845 /**
2846 * sf1_read - read data from the serial flash
2847 * @adapter: the adapter
2848 * @byte_cnt: number of bytes to read
2849 * @cont: whether another operation will be chained
2850 * @lock: whether to lock SF for PL access only
2851 * @valp: where to store the read data
2852 *
2853 * Reads up to 4 bytes of data from the serial flash. The location of
2854 * the read needs to be specified prior to calling this by issuing the
2855 * appropriate commands to the serial flash.
2856 */
2857 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2858 int lock, u32 *valp)
2859 {
2860 int ret;
2861
2862 if (!byte_cnt || byte_cnt > 4)
2863 return -EINVAL;
2864 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2865 return -EBUSY;
2866 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2867 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2868 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2869 if (!ret)
2870 *valp = t4_read_reg(adapter, SF_DATA_A);
2871 return ret;
2872 }
2873
2874 /**
2875 * sf1_write - write data to the serial flash
2876 * @adapter: the adapter
2877 * @byte_cnt: number of bytes to write
2878 * @cont: whether another operation will be chained
2879 * @lock: whether to lock SF for PL access only
2880 * @val: value to write
2881 *
2882 * Writes up to 4 bytes of data to the serial flash. The location of
2883 * the write needs to be specified prior to calling this by issuing the
2884 * appropriate commands to the serial flash.
2885 */
2886 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2887 int lock, u32 val)
2888 {
2889 if (!byte_cnt || byte_cnt > 4)
2890 return -EINVAL;
2891 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2892 return -EBUSY;
2893 t4_write_reg(adapter, SF_DATA_A, val);
2894 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2895 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2896 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2897 }
2898
2899 /**
2900 * flash_wait_op - wait for a flash operation to complete
2901 * @adapter: the adapter
2902 * @attempts: max number of polls of the status register
2903 * @delay: delay between polls in ms
2904 *
2905 * Wait for a flash operation to complete by polling the status register.
2906 */
2907 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2908 {
2909 int ret;
2910 u32 status;
2911
2912 while (1) {
2913 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2914 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2915 return ret;
2916 if (!(status & 1))
2917 return 0;
2918 if (--attempts == 0)
2919 return -EAGAIN;
2920 if (delay)
2921 msleep(delay);
2922 }
2923 }
2924
2925 /**
2926 * t4_read_flash - read words from serial flash
2927 * @adapter: the adapter
2928 * @addr: the start address for the read
2929 * @nwords: how many 32-bit words to read
2930 * @data: where to store the read data
2931 * @byte_oriented: whether to store data as bytes or as words
2932 *
2933 * Read the specified number of 32-bit words from the serial flash.
2934 * If @byte_oriented is set the read data is stored as a byte array
2935 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2936 * natural endianness.
2937 */
2938 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2939 unsigned int nwords, u32 *data, int byte_oriented)
2940 {
2941 int ret;
2942
2943 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
2944 return -EINVAL;
2945
2946 addr = swab32(addr) | SF_RD_DATA_FAST;
2947
2948 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
2949 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
2950 return ret;
2951
2952 for ( ; nwords; nwords--, data++) {
2953 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2954 if (nwords == 1)
2955 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2956 if (ret)
2957 return ret;
2958 if (byte_oriented)
2959 *data = (__force __u32)(cpu_to_be32(*data));
2960 }
2961 return 0;
2962 }
2963
2964 /**
2965 * t4_write_flash - write up to a page of data to the serial flash
2966 * @adapter: the adapter
2967 * @addr: the start address to write
2968 * @n: length of data to write in bytes
2969 * @data: the data to write
2970 *
2971 * Writes up to a page of data (256 bytes) to the serial flash starting
2972 * at the given address. All the data must be written to the same page.
2973 */
2974 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
2975 unsigned int n, const u8 *data)
2976 {
2977 int ret;
2978 u32 buf[64];
2979 unsigned int i, c, left, val, offset = addr & 0xff;
2980
2981 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
2982 return -EINVAL;
2983
2984 val = swab32(addr) | SF_PROG_PAGE;
2985
2986 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2987 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
2988 goto unlock;
2989
2990 for (left = n; left; left -= c) {
2991 c = min(left, 4U);
2992 for (val = 0, i = 0; i < c; ++i)
2993 val = (val << 8) + *data++;
2994
2995 ret = sf1_write(adapter, c, c != left, 1, val);
2996 if (ret)
2997 goto unlock;
2998 }
2999 ret = flash_wait_op(adapter, 8, 1);
3000 if (ret)
3001 goto unlock;
3002
3003 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3004
3005 /* Read the page to verify the write succeeded */
3006 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
3007 if (ret)
3008 return ret;
3009
3010 if (memcmp(data - n, (u8 *)buf + offset, n)) {
3011 dev_err(adapter->pdev_dev,
3012 "failed to correctly write the flash page at %#x\n",
3013 addr);
3014 return -EIO;
3015 }
3016 return 0;
3017
3018 unlock:
3019 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3020 return ret;
3021 }
3022
3023 /**
3024 * t4_get_fw_version - read the firmware version
3025 * @adapter: the adapter
3026 * @vers: where to place the version
3027 *
3028 * Reads the FW version from flash.
3029 */
3030 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3031 {
3032 return t4_read_flash(adapter, FLASH_FW_START +
3033 offsetof(struct fw_hdr, fw_ver), 1,
3034 vers, 0);
3035 }
3036
3037 /**
3038 * t4_get_bs_version - read the firmware bootstrap version
3039 * @adapter: the adapter
3040 * @vers: where to place the version
3041 *
3042 * Reads the FW Bootstrap version from flash.
3043 */
3044 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3045 {
3046 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3047 offsetof(struct fw_hdr, fw_ver), 1,
3048 vers, 0);
3049 }
3050
3051 /**
3052 * t4_get_tp_version - read the TP microcode version
3053 * @adapter: the adapter
3054 * @vers: where to place the version
3055 *
3056 * Reads the TP microcode version from flash.
3057 */
3058 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3059 {
3060 return t4_read_flash(adapter, FLASH_FW_START +
3061 offsetof(struct fw_hdr, tp_microcode_ver),
3062 1, vers, 0);
3063 }
3064
3065 /**
3066 * t4_get_exprom_version - return the Expansion ROM version (if any)
3067 * @adapter: the adapter
3068 * @vers: where to place the version
3069 *
3070 * Reads the Expansion ROM header from FLASH and returns the version
3071 * number (if present) through the @vers return value pointer. We return
3072 * this in the Firmware Version Format since it's convenient. Return
3073 * 0 on success, -ENOENT if no Expansion ROM is present.
3074 */
3075 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3076 {
3077 struct exprom_header {
3078 unsigned char hdr_arr[16]; /* must start with 0x55aa */
3079 unsigned char hdr_ver[4]; /* Expansion ROM version */
3080 } *hdr;
3081 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3082 sizeof(u32))];
3083 int ret;
3084
3085 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3086 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3087 0);
3088 if (ret)
3089 return ret;
3090
3091 hdr = (struct exprom_header *)exprom_header_buf;
3092 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3093 return -ENOENT;
3094
3095 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3096 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3097 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3098 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3099 return 0;
3100 }
3101
3102 /**
3103 * t4_check_fw_version - check if the FW is supported with this driver
3104 * @adap: the adapter
3105 *
3106 * Checks if an adapter's FW is compatible with the driver. Returns 0
3107 * if there's exact match, a negative error if the version could not be
3108 * read or there's a major version mismatch
3109 */
3110 int t4_check_fw_version(struct adapter *adap)
3111 {
3112 int i, ret, major, minor, micro;
3113 int exp_major, exp_minor, exp_micro;
3114 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3115
3116 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3117 /* Try multiple times before returning error */
3118 for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3119 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3120
3121 if (ret)
3122 return ret;
3123
3124 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3125 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3126 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3127
3128 switch (chip_version) {
3129 case CHELSIO_T4:
3130 exp_major = T4FW_MIN_VERSION_MAJOR;
3131 exp_minor = T4FW_MIN_VERSION_MINOR;
3132 exp_micro = T4FW_MIN_VERSION_MICRO;
3133 break;
3134 case CHELSIO_T5:
3135 exp_major = T5FW_MIN_VERSION_MAJOR;
3136 exp_minor = T5FW_MIN_VERSION_MINOR;
3137 exp_micro = T5FW_MIN_VERSION_MICRO;
3138 break;
3139 case CHELSIO_T6:
3140 exp_major = T6FW_MIN_VERSION_MAJOR;
3141 exp_minor = T6FW_MIN_VERSION_MINOR;
3142 exp_micro = T6FW_MIN_VERSION_MICRO;
3143 break;
3144 default:
3145 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3146 adap->chip);
3147 return -EINVAL;
3148 }
3149
3150 if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3151 (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3152 dev_err(adap->pdev_dev,
3153 "Card has firmware version %u.%u.%u, minimum "
3154 "supported firmware is %u.%u.%u.\n", major, minor,
3155 micro, exp_major, exp_minor, exp_micro);
3156 return -EFAULT;
3157 }
3158 return 0;
3159 }
3160
3161 /* Is the given firmware API compatible with the one the driver was compiled
3162 * with?
3163 */
3164 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3165 {
3166
3167 /* short circuit if it's the exact same firmware version */
3168 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3169 return 1;
3170
3171 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3172 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3173 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3174 return 1;
3175 #undef SAME_INTF
3176
3177 return 0;
3178 }
3179
3180 /* The firmware in the filesystem is usable, but should it be installed?
3181 * This routine explains itself in detail if it indicates the filesystem
3182 * firmware should be installed.
3183 */
3184 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3185 int k, int c)
3186 {
3187 const char *reason;
3188
3189 if (!card_fw_usable) {
3190 reason = "incompatible or unusable";
3191 goto install;
3192 }
3193
3194 if (k > c) {
3195 reason = "older than the version supported with this driver";
3196 goto install;
3197 }
3198
3199 return 0;
3200
3201 install:
3202 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3203 "installing firmware %u.%u.%u.%u on card.\n",
3204 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3205 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3206 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3207 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3208
3209 return 1;
3210 }
3211
3212 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3213 const u8 *fw_data, unsigned int fw_size,
3214 struct fw_hdr *card_fw, enum dev_state state,
3215 int *reset)
3216 {
3217 int ret, card_fw_usable, fs_fw_usable;
3218 const struct fw_hdr *fs_fw;
3219 const struct fw_hdr *drv_fw;
3220
3221 drv_fw = &fw_info->fw_hdr;
3222
3223 /* Read the header of the firmware on the card */
3224 ret = -t4_read_flash(adap, FLASH_FW_START,
3225 sizeof(*card_fw) / sizeof(uint32_t),
3226 (uint32_t *)card_fw, 1);
3227 if (ret == 0) {
3228 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3229 } else {
3230 dev_err(adap->pdev_dev,
3231 "Unable to read card's firmware header: %d\n", ret);
3232 card_fw_usable = 0;
3233 }
3234
3235 if (fw_data != NULL) {
3236 fs_fw = (const void *)fw_data;
3237 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3238 } else {
3239 fs_fw = NULL;
3240 fs_fw_usable = 0;
3241 }
3242
3243 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3244 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3245 /* Common case: the firmware on the card is an exact match and
3246 * the filesystem one is an exact match too, or the filesystem
3247 * one is absent/incompatible.
3248 */
3249 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3250 should_install_fs_fw(adap, card_fw_usable,
3251 be32_to_cpu(fs_fw->fw_ver),
3252 be32_to_cpu(card_fw->fw_ver))) {
3253 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3254 fw_size, 0);
3255 if (ret != 0) {
3256 dev_err(adap->pdev_dev,
3257 "failed to install firmware: %d\n", ret);
3258 goto bye;
3259 }
3260
3261 /* Installed successfully, update the cached header too. */
3262 *card_fw = *fs_fw;
3263 card_fw_usable = 1;
3264 *reset = 0; /* already reset as part of load_fw */
3265 }
3266
3267 if (!card_fw_usable) {
3268 uint32_t d, c, k;
3269
3270 d = be32_to_cpu(drv_fw->fw_ver);
3271 c = be32_to_cpu(card_fw->fw_ver);
3272 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3273
3274 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3275 "chip state %d, "
3276 "driver compiled with %d.%d.%d.%d, "
3277 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3278 state,
3279 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3280 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3281 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3282 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3283 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3284 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3285 ret = EINVAL;
3286 goto bye;
3287 }
3288
3289 /* We're using whatever's on the card and it's known to be good. */
3290 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3291 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3292
3293 bye:
3294 return ret;
3295 }
3296
3297 /**
3298 * t4_flash_erase_sectors - erase a range of flash sectors
3299 * @adapter: the adapter
3300 * @start: the first sector to erase
3301 * @end: the last sector to erase
3302 *
3303 * Erases the sectors in the given inclusive range.
3304 */
3305 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3306 {
3307 int ret = 0;
3308
3309 if (end >= adapter->params.sf_nsec)
3310 return -EINVAL;
3311
3312 while (start <= end) {
3313 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3314 (ret = sf1_write(adapter, 4, 0, 1,
3315 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3316 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3317 dev_err(adapter->pdev_dev,
3318 "erase of flash sector %d failed, error %d\n",
3319 start, ret);
3320 break;
3321 }
3322 start++;
3323 }
3324 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3325 return ret;
3326 }
3327
3328 /**
3329 * t4_flash_cfg_addr - return the address of the flash configuration file
3330 * @adapter: the adapter
3331 *
3332 * Return the address within the flash where the Firmware Configuration
3333 * File is stored.
3334 */
3335 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3336 {
3337 if (adapter->params.sf_size == 0x100000)
3338 return FLASH_FPGA_CFG_START;
3339 else
3340 return FLASH_CFG_START;
3341 }
3342
3343 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3344 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3345 * and emit an error message for mismatched firmware to save our caller the
3346 * effort ...
3347 */
3348 static bool t4_fw_matches_chip(const struct adapter *adap,
3349 const struct fw_hdr *hdr)
3350 {
3351 /* The expression below will return FALSE for any unsupported adapter
3352 * which will keep us "honest" in the future ...
3353 */
3354 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3355 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3356 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3357 return true;
3358
3359 dev_err(adap->pdev_dev,
3360 "FW image (%d) is not suitable for this adapter (%d)\n",
3361 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3362 return false;
3363 }
3364
3365 /**
3366 * t4_load_fw - download firmware
3367 * @adap: the adapter
3368 * @fw_data: the firmware image to write
3369 * @size: image size
3370 *
3371 * Write the supplied firmware image to the card's serial flash.
3372 */
3373 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3374 {
3375 u32 csum;
3376 int ret, addr;
3377 unsigned int i;
3378 u8 first_page[SF_PAGE_SIZE];
3379 const __be32 *p = (const __be32 *)fw_data;
3380 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3381 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3382 unsigned int fw_img_start = adap->params.sf_fw_start;
3383 unsigned int fw_start_sec = fw_img_start / sf_sec_size;
3384
3385 if (!size) {
3386 dev_err(adap->pdev_dev, "FW image has no data\n");
3387 return -EINVAL;
3388 }
3389 if (size & 511) {
3390 dev_err(adap->pdev_dev,
3391 "FW image size not multiple of 512 bytes\n");
3392 return -EINVAL;
3393 }
3394 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3395 dev_err(adap->pdev_dev,
3396 "FW image size differs from size in FW header\n");
3397 return -EINVAL;
3398 }
3399 if (size > FW_MAX_SIZE) {
3400 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3401 FW_MAX_SIZE);
3402 return -EFBIG;
3403 }
3404 if (!t4_fw_matches_chip(adap, hdr))
3405 return -EINVAL;
3406
3407 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3408 csum += be32_to_cpu(p[i]);
3409
3410 if (csum != 0xffffffff) {
3411 dev_err(adap->pdev_dev,
3412 "corrupted firmware image, checksum %#x\n", csum);
3413 return -EINVAL;
3414 }
3415
3416 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3417 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3418 if (ret)
3419 goto out;
3420
3421 /*
3422 * We write the correct version at the end so the driver can see a bad
3423 * version if the FW write fails. Start by writing a copy of the
3424 * first page with a bad version.
3425 */
3426 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3427 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3428 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
3429 if (ret)
3430 goto out;
3431
3432 addr = fw_img_start;
3433 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3434 addr += SF_PAGE_SIZE;
3435 fw_data += SF_PAGE_SIZE;
3436 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3437 if (ret)
3438 goto out;
3439 }
3440
3441 ret = t4_write_flash(adap,
3442 fw_img_start + offsetof(struct fw_hdr, fw_ver),
3443 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3444 out:
3445 if (ret)
3446 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3447 ret);
3448 else
3449 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3450 return ret;
3451 }
3452
3453 /**
3454 * t4_phy_fw_ver - return current PHY firmware version
3455 * @adap: the adapter
3456 * @phy_fw_ver: return value buffer for PHY firmware version
3457 *
3458 * Returns the current version of external PHY firmware on the
3459 * adapter.
3460 */
3461 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3462 {
3463 u32 param, val;
3464 int ret;
3465
3466 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3467 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3468 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3469 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3470 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3471 &param, &val);
3472 if (ret < 0)
3473 return ret;
3474 *phy_fw_ver = val;
3475 return 0;
3476 }
3477
3478 /**
3479 * t4_load_phy_fw - download port PHY firmware
3480 * @adap: the adapter
3481 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3482 * @win_lock: the lock to use to guard the memory copy
3483 * @phy_fw_version: function to check PHY firmware versions
3484 * @phy_fw_data: the PHY firmware image to write
3485 * @phy_fw_size: image size
3486 *
3487 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3488 * @phy_fw_version is supplied, then it will be used to determine if
3489 * it's necessary to perform the transfer by comparing the version
3490 * of any existing adapter PHY firmware with that of the passed in
3491 * PHY firmware image. If @win_lock is non-NULL then it will be used
3492 * around the call to t4_memory_rw() which transfers the PHY firmware
3493 * to the adapter.
3494 *
3495 * A negative error number will be returned if an error occurs. If
3496 * version number support is available and there's no need to upgrade
3497 * the firmware, 0 will be returned. If firmware is successfully
3498 * transferred to the adapter, 1 will be retured.
3499 *
3500 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3501 * a result, a RESET of the adapter would cause that RAM to lose its
3502 * contents. Thus, loading PHY firmware on such adapters must happen
3503 * after any FW_RESET_CMDs ...
3504 */
3505 int t4_load_phy_fw(struct adapter *adap,
3506 int win, spinlock_t *win_lock,
3507 int (*phy_fw_version)(const u8 *, size_t),
3508 const u8 *phy_fw_data, size_t phy_fw_size)
3509 {
3510 unsigned long mtype = 0, maddr = 0;
3511 u32 param, val;
3512 int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3513 int ret;
3514
3515 /* If we have version number support, then check to see if the adapter
3516 * already has up-to-date PHY firmware loaded.
3517 */
3518 if (phy_fw_version) {
3519 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3520 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3521 if (ret < 0)
3522 return ret;
3523
3524 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3525 CH_WARN(adap, "PHY Firmware already up-to-date, "
3526 "version %#x\n", cur_phy_fw_ver);
3527 return 0;
3528 }
3529 }
3530
3531 /* Ask the firmware where it wants us to copy the PHY firmware image.
3532 * The size of the file requires a special version of the READ coommand
3533 * which will pass the file size via the values field in PARAMS_CMD and
3534 * retrieve the return value from firmware and place it in the same
3535 * buffer values
3536 */
3537 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3538 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3539 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3540 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3541 val = phy_fw_size;
3542 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3543 &param, &val, 1);
3544 if (ret < 0)
3545 return ret;
3546 mtype = val >> 8;
3547 maddr = (val & 0xff) << 16;
3548
3549 /* Copy the supplied PHY Firmware image to the adapter memory location
3550 * allocated by the adapter firmware.
3551 */
3552 if (win_lock)
3553 spin_lock_bh(win_lock);
3554 ret = t4_memory_rw(adap, win, mtype, maddr,
3555 phy_fw_size, (__be32 *)phy_fw_data,
3556 T4_MEMORY_WRITE);
3557 if (win_lock)
3558 spin_unlock_bh(win_lock);
3559 if (ret)
3560 return ret;
3561
3562 /* Tell the firmware that the PHY firmware image has been written to
3563 * RAM and it can now start copying it over to the PHYs. The chip
3564 * firmware will RESET the affected PHYs as part of this operation
3565 * leaving them running the new PHY firmware image.
3566 */
3567 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3568 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3569 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3570 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3571 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3572 &param, &val, 30000);
3573
3574 /* If we have version number support, then check to see that the new
3575 * firmware got loaded properly.
3576 */
3577 if (phy_fw_version) {
3578 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3579 if (ret < 0)
3580 return ret;
3581
3582 if (cur_phy_fw_ver != new_phy_fw_vers) {
3583 CH_WARN(adap, "PHY Firmware did not update: "
3584 "version on adapter %#x, "
3585 "version flashed %#x\n",
3586 cur_phy_fw_ver, new_phy_fw_vers);
3587 return -ENXIO;
3588 }
3589 }
3590
3591 return 1;
3592 }
3593
3594 /**
3595 * t4_fwcache - firmware cache operation
3596 * @adap: the adapter
3597 * @op : the operation (flush or flush and invalidate)
3598 */
3599 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3600 {
3601 struct fw_params_cmd c;
3602
3603 memset(&c, 0, sizeof(c));
3604 c.op_to_vfn =
3605 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3606 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3607 FW_PARAMS_CMD_PFN_V(adap->pf) |
3608 FW_PARAMS_CMD_VFN_V(0));
3609 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3610 c.param[0].mnem =
3611 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3612 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3613 c.param[0].val = (__force __be32)op;
3614
3615 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3616 }
3617
3618 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3619 unsigned int *pif_req_wrptr,
3620 unsigned int *pif_rsp_wrptr)
3621 {
3622 int i, j;
3623 u32 cfg, val, req, rsp;
3624
3625 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3626 if (cfg & LADBGEN_F)
3627 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3628
3629 val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3630 req = POLADBGWRPTR_G(val);
3631 rsp = PILADBGWRPTR_G(val);
3632 if (pif_req_wrptr)
3633 *pif_req_wrptr = req;
3634 if (pif_rsp_wrptr)
3635 *pif_rsp_wrptr = rsp;
3636
3637 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3638 for (j = 0; j < 6; j++) {
3639 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3640 PILADBGRDPTR_V(rsp));
3641 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3642 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3643 req++;
3644 rsp++;
3645 }
3646 req = (req + 2) & POLADBGRDPTR_M;
3647 rsp = (rsp + 2) & PILADBGRDPTR_M;
3648 }
3649 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3650 }
3651
3652 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3653 {
3654 u32 cfg;
3655 int i, j, idx;
3656
3657 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3658 if (cfg & LADBGEN_F)
3659 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3660
3661 for (i = 0; i < CIM_MALA_SIZE; i++) {
3662 for (j = 0; j < 5; j++) {
3663 idx = 8 * i + j;
3664 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3665 PILADBGRDPTR_V(idx));
3666 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3667 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3668 }
3669 }
3670 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3671 }
3672
3673 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3674 {
3675 unsigned int i, j;
3676
3677 for (i = 0; i < 8; i++) {
3678 u32 *p = la_buf + i;
3679
3680 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3681 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3682 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3683 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3684 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3685 }
3686 }
3687
3688 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
3689 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_25G | \
3690 FW_PORT_CAP_SPEED_40G | FW_PORT_CAP_SPEED_100G | \
3691 FW_PORT_CAP_ANEG)
3692
3693 /**
3694 * t4_link_l1cfg - apply link configuration to MAC/PHY
3695 * @phy: the PHY to setup
3696 * @mac: the MAC to setup
3697 * @lc: the requested link configuration
3698 *
3699 * Set up a port's MAC and PHY according to a desired link configuration.
3700 * - If the PHY can auto-negotiate first decide what to advertise, then
3701 * enable/disable auto-negotiation as desired, and reset.
3702 * - If the PHY does not auto-negotiate just reset it.
3703 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3704 * otherwise do it later based on the outcome of auto-negotiation.
3705 */
3706 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3707 struct link_config *lc)
3708 {
3709 struct fw_port_cmd c;
3710 unsigned int mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO);
3711 unsigned int fc = 0, fec = 0, fw_fec = 0;
3712
3713 lc->link_ok = 0;
3714 if (lc->requested_fc & PAUSE_RX)
3715 fc |= FW_PORT_CAP_FC_RX;
3716 if (lc->requested_fc & PAUSE_TX)
3717 fc |= FW_PORT_CAP_FC_TX;
3718
3719 fec = lc->requested_fec & FEC_AUTO ? lc->auto_fec : lc->requested_fec;
3720
3721 if (fec & FEC_RS)
3722 fw_fec |= FW_PORT_CAP_FEC_RS;
3723 if (fec & FEC_BASER_RS)
3724 fw_fec |= FW_PORT_CAP_FEC_BASER_RS;
3725
3726 memset(&c, 0, sizeof(c));
3727 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3728 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3729 FW_PORT_CMD_PORTID_V(port));
3730 c.action_to_len16 =
3731 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3732 FW_LEN16(c));
3733
3734 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
3735 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
3736 fc | fw_fec);
3737 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3738 } else if (lc->autoneg == AUTONEG_DISABLE) {
3739 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc |
3740 fw_fec | mdi);
3741 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3742 } else
3743 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc |
3744 fw_fec | mdi);
3745
3746 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3747 }
3748
3749 /**
3750 * t4_restart_aneg - restart autonegotiation
3751 * @adap: the adapter
3752 * @mbox: mbox to use for the FW command
3753 * @port: the port id
3754 *
3755 * Restarts autonegotiation for the selected port.
3756 */
3757 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3758 {
3759 struct fw_port_cmd c;
3760
3761 memset(&c, 0, sizeof(c));
3762 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3763 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3764 FW_PORT_CMD_PORTID_V(port));
3765 c.action_to_len16 =
3766 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3767 FW_LEN16(c));
3768 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3769 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3770 }
3771
3772 typedef void (*int_handler_t)(struct adapter *adap);
3773
3774 struct intr_info {
3775 unsigned int mask; /* bits to check in interrupt status */
3776 const char *msg; /* message to print or NULL */
3777 short stat_idx; /* stat counter to increment or -1 */
3778 unsigned short fatal; /* whether the condition reported is fatal */
3779 int_handler_t int_handler; /* platform-specific int handler */
3780 };
3781
3782 /**
3783 * t4_handle_intr_status - table driven interrupt handler
3784 * @adapter: the adapter that generated the interrupt
3785 * @reg: the interrupt status register to process
3786 * @acts: table of interrupt actions
3787 *
3788 * A table driven interrupt handler that applies a set of masks to an
3789 * interrupt status word and performs the corresponding actions if the
3790 * interrupts described by the mask have occurred. The actions include
3791 * optionally emitting a warning or alert message. The table is terminated
3792 * by an entry specifying mask 0. Returns the number of fatal interrupt
3793 * conditions.
3794 */
3795 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
3796 const struct intr_info *acts)
3797 {
3798 int fatal = 0;
3799 unsigned int mask = 0;
3800 unsigned int status = t4_read_reg(adapter, reg);
3801
3802 for ( ; acts->mask; ++acts) {
3803 if (!(status & acts->mask))
3804 continue;
3805 if (acts->fatal) {
3806 fatal++;
3807 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3808 status & acts->mask);
3809 } else if (acts->msg && printk_ratelimit())
3810 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3811 status & acts->mask);
3812 if (acts->int_handler)
3813 acts->int_handler(adapter);
3814 mask |= acts->mask;
3815 }
3816 status &= mask;
3817 if (status) /* clear processed interrupts */
3818 t4_write_reg(adapter, reg, status);
3819 return fatal;
3820 }
3821
3822 /*
3823 * Interrupt handler for the PCIE module.
3824 */
3825 static void pcie_intr_handler(struct adapter *adapter)
3826 {
3827 static const struct intr_info sysbus_intr_info[] = {
3828 { RNPP_F, "RXNP array parity error", -1, 1 },
3829 { RPCP_F, "RXPC array parity error", -1, 1 },
3830 { RCIP_F, "RXCIF array parity error", -1, 1 },
3831 { RCCP_F, "Rx completions control array parity error", -1, 1 },
3832 { RFTP_F, "RXFT array parity error", -1, 1 },
3833 { 0 }
3834 };
3835 static const struct intr_info pcie_port_intr_info[] = {
3836 { TPCP_F, "TXPC array parity error", -1, 1 },
3837 { TNPP_F, "TXNP array parity error", -1, 1 },
3838 { TFTP_F, "TXFT array parity error", -1, 1 },
3839 { TCAP_F, "TXCA array parity error", -1, 1 },
3840 { TCIP_F, "TXCIF array parity error", -1, 1 },
3841 { RCAP_F, "RXCA array parity error", -1, 1 },
3842 { OTDD_F, "outbound request TLP discarded", -1, 1 },
3843 { RDPE_F, "Rx data parity error", -1, 1 },
3844 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
3845 { 0 }
3846 };
3847 static const struct intr_info pcie_intr_info[] = {
3848 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
3849 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
3850 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
3851 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3852 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3853 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3854 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3855 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
3856 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
3857 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3858 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
3859 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3860 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3861 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
3862 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3863 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3864 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
3865 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3866 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3867 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3868 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3869 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
3870 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
3871 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3872 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
3873 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
3874 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
3875 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
3876 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
3877 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
3878 -1, 0 },
3879 { 0 }
3880 };
3881
3882 static struct intr_info t5_pcie_intr_info[] = {
3883 { MSTGRPPERR_F, "Master Response Read Queue parity error",
3884 -1, 1 },
3885 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
3886 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
3887 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3888 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3889 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3890 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3891 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
3892 -1, 1 },
3893 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
3894 -1, 1 },
3895 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3896 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
3897 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3898 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3899 { DREQWRPERR_F, "PCI DMA channel write request parity error",
3900 -1, 1 },
3901 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3902 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3903 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
3904 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3905 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3906 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3907 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3908 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
3909 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
3910 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3911 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
3912 -1, 1 },
3913 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
3914 -1, 1 },
3915 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
3916 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
3917 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
3918 { READRSPERR_F, "Outbound read error", -1, 0 },
3919 { 0 }
3920 };
3921
3922 int fat;
3923
3924 if (is_t4(adapter->params.chip))
3925 fat = t4_handle_intr_status(adapter,
3926 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
3927 sysbus_intr_info) +
3928 t4_handle_intr_status(adapter,
3929 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
3930 pcie_port_intr_info) +
3931 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3932 pcie_intr_info);
3933 else
3934 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3935 t5_pcie_intr_info);
3936
3937 if (fat)
3938 t4_fatal_err(adapter);
3939 }
3940
3941 /*
3942 * TP interrupt handler.
3943 */
3944 static void tp_intr_handler(struct adapter *adapter)
3945 {
3946 static const struct intr_info tp_intr_info[] = {
3947 { 0x3fffffff, "TP parity error", -1, 1 },
3948 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
3949 { 0 }
3950 };
3951
3952 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
3953 t4_fatal_err(adapter);
3954 }
3955
3956 /*
3957 * SGE interrupt handler.
3958 */
3959 static void sge_intr_handler(struct adapter *adapter)
3960 {
3961 u64 v;
3962 u32 err;
3963
3964 static const struct intr_info sge_intr_info[] = {
3965 { ERR_CPL_EXCEED_IQE_SIZE_F,
3966 "SGE received CPL exceeding IQE size", -1, 1 },
3967 { ERR_INVALID_CIDX_INC_F,
3968 "SGE GTS CIDX increment too large", -1, 0 },
3969 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
3970 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
3971 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
3972 "SGE IQID > 1023 received CPL for FL", -1, 0 },
3973 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
3974 0 },
3975 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
3976 0 },
3977 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
3978 0 },
3979 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
3980 0 },
3981 { ERR_ING_CTXT_PRIO_F,
3982 "SGE too many priority ingress contexts", -1, 0 },
3983 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
3984 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
3985 { 0 }
3986 };
3987
3988 static struct intr_info t4t5_sge_intr_info[] = {
3989 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
3990 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
3991 { ERR_EGR_CTXT_PRIO_F,
3992 "SGE too many priority egress contexts", -1, 0 },
3993 { 0 }
3994 };
3995
3996 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
3997 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
3998 if (v) {
3999 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
4000 (unsigned long long)v);
4001 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
4002 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
4003 }
4004
4005 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
4006 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4007 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
4008 t4t5_sge_intr_info);
4009
4010 err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4011 if (err & ERROR_QID_VALID_F) {
4012 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
4013 ERROR_QID_G(err));
4014 if (err & UNCAPTURED_ERROR_F)
4015 dev_err(adapter->pdev_dev,
4016 "SGE UNCAPTURED_ERROR set (clearing)\n");
4017 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
4018 UNCAPTURED_ERROR_F);
4019 }
4020
4021 if (v != 0)
4022 t4_fatal_err(adapter);
4023 }
4024
4025 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4026 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4027 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4028 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4029
4030 /*
4031 * CIM interrupt handler.
4032 */
4033 static void cim_intr_handler(struct adapter *adapter)
4034 {
4035 static const struct intr_info cim_intr_info[] = {
4036 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
4037 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4038 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4039 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
4040 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
4041 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
4042 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
4043 { 0 }
4044 };
4045 static const struct intr_info cim_upintr_info[] = {
4046 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
4047 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
4048 { ILLWRINT_F, "CIM illegal write", -1, 1 },
4049 { ILLRDINT_F, "CIM illegal read", -1, 1 },
4050 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
4051 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
4052 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
4053 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
4054 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
4055 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
4056 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
4057 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
4058 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
4059 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
4060 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
4061 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
4062 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
4063 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
4064 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
4065 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
4066 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
4067 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
4068 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4069 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4070 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4071 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4072 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4073 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4074 { 0 }
4075 };
4076
4077 int fat;
4078
4079 if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F)
4080 t4_report_fw_error(adapter);
4081
4082 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4083 cim_intr_info) +
4084 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4085 cim_upintr_info);
4086 if (fat)
4087 t4_fatal_err(adapter);
4088 }
4089
4090 /*
4091 * ULP RX interrupt handler.
4092 */
4093 static void ulprx_intr_handler(struct adapter *adapter)
4094 {
4095 static const struct intr_info ulprx_intr_info[] = {
4096 { 0x1800000, "ULPRX context error", -1, 1 },
4097 { 0x7fffff, "ULPRX parity error", -1, 1 },
4098 { 0 }
4099 };
4100
4101 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4102 t4_fatal_err(adapter);
4103 }
4104
4105 /*
4106 * ULP TX interrupt handler.
4107 */
4108 static void ulptx_intr_handler(struct adapter *adapter)
4109 {
4110 static const struct intr_info ulptx_intr_info[] = {
4111 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4112 0 },
4113 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4114 0 },
4115 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4116 0 },
4117 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4118 0 },
4119 { 0xfffffff, "ULPTX parity error", -1, 1 },
4120 { 0 }
4121 };
4122
4123 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4124 t4_fatal_err(adapter);
4125 }
4126
4127 /*
4128 * PM TX interrupt handler.
4129 */
4130 static void pmtx_intr_handler(struct adapter *adapter)
4131 {
4132 static const struct intr_info pmtx_intr_info[] = {
4133 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4134 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4135 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4136 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4137 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4138 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4139 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4140 -1, 1 },
4141 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4142 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4143 { 0 }
4144 };
4145
4146 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4147 t4_fatal_err(adapter);
4148 }
4149
4150 /*
4151 * PM RX interrupt handler.
4152 */
4153 static void pmrx_intr_handler(struct adapter *adapter)
4154 {
4155 static const struct intr_info pmrx_intr_info[] = {
4156 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4157 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4158 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4159 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4160 -1, 1 },
4161 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4162 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4163 { 0 }
4164 };
4165
4166 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4167 t4_fatal_err(adapter);
4168 }
4169
4170 /*
4171 * CPL switch interrupt handler.
4172 */
4173 static void cplsw_intr_handler(struct adapter *adapter)
4174 {
4175 static const struct intr_info cplsw_intr_info[] = {
4176 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4177 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4178 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4179 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4180 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4181 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4182 { 0 }
4183 };
4184
4185 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4186 t4_fatal_err(adapter);
4187 }
4188
4189 /*
4190 * LE interrupt handler.
4191 */
4192 static void le_intr_handler(struct adapter *adap)
4193 {
4194 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4195 static const struct intr_info le_intr_info[] = {
4196 { LIPMISS_F, "LE LIP miss", -1, 0 },
4197 { LIP0_F, "LE 0 LIP error", -1, 0 },
4198 { PARITYERR_F, "LE parity error", -1, 1 },
4199 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4200 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4201 { 0 }
4202 };
4203
4204 static struct intr_info t6_le_intr_info[] = {
4205 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4206 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4207 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4208 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4209 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4210 { 0 }
4211 };
4212
4213 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4214 (chip <= CHELSIO_T5) ?
4215 le_intr_info : t6_le_intr_info))
4216 t4_fatal_err(adap);
4217 }
4218
4219 /*
4220 * MPS interrupt handler.
4221 */
4222 static void mps_intr_handler(struct adapter *adapter)
4223 {
4224 static const struct intr_info mps_rx_intr_info[] = {
4225 { 0xffffff, "MPS Rx parity error", -1, 1 },
4226 { 0 }
4227 };
4228 static const struct intr_info mps_tx_intr_info[] = {
4229 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4230 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4231 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4232 -1, 1 },
4233 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4234 -1, 1 },
4235 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4236 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4237 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4238 { 0 }
4239 };
4240 static const struct intr_info mps_trc_intr_info[] = {
4241 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4242 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4243 -1, 1 },
4244 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4245 { 0 }
4246 };
4247 static const struct intr_info mps_stat_sram_intr_info[] = {
4248 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4249 { 0 }
4250 };
4251 static const struct intr_info mps_stat_tx_intr_info[] = {
4252 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4253 { 0 }
4254 };
4255 static const struct intr_info mps_stat_rx_intr_info[] = {
4256 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4257 { 0 }
4258 };
4259 static const struct intr_info mps_cls_intr_info[] = {
4260 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4261 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4262 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4263 { 0 }
4264 };
4265
4266 int fat;
4267
4268 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4269 mps_rx_intr_info) +
4270 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4271 mps_tx_intr_info) +
4272 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4273 mps_trc_intr_info) +
4274 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4275 mps_stat_sram_intr_info) +
4276 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4277 mps_stat_tx_intr_info) +
4278 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4279 mps_stat_rx_intr_info) +
4280 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4281 mps_cls_intr_info);
4282
4283 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4284 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
4285 if (fat)
4286 t4_fatal_err(adapter);
4287 }
4288
4289 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4290 ECC_UE_INT_CAUSE_F)
4291
4292 /*
4293 * EDC/MC interrupt handler.
4294 */
4295 static void mem_intr_handler(struct adapter *adapter, int idx)
4296 {
4297 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4298
4299 unsigned int addr, cnt_addr, v;
4300
4301 if (idx <= MEM_EDC1) {
4302 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4303 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4304 } else if (idx == MEM_MC) {
4305 if (is_t4(adapter->params.chip)) {
4306 addr = MC_INT_CAUSE_A;
4307 cnt_addr = MC_ECC_STATUS_A;
4308 } else {
4309 addr = MC_P_INT_CAUSE_A;
4310 cnt_addr = MC_P_ECC_STATUS_A;
4311 }
4312 } else {
4313 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4314 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4315 }
4316
4317 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4318 if (v & PERR_INT_CAUSE_F)
4319 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4320 name[idx]);
4321 if (v & ECC_CE_INT_CAUSE_F) {
4322 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4323
4324 t4_edc_err_read(adapter, idx);
4325
4326 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4327 if (printk_ratelimit())
4328 dev_warn(adapter->pdev_dev,
4329 "%u %s correctable ECC data error%s\n",
4330 cnt, name[idx], cnt > 1 ? "s" : "");
4331 }
4332 if (v & ECC_UE_INT_CAUSE_F)
4333 dev_alert(adapter->pdev_dev,
4334 "%s uncorrectable ECC data error\n", name[idx]);
4335
4336 t4_write_reg(adapter, addr, v);
4337 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4338 t4_fatal_err(adapter);
4339 }
4340
4341 /*
4342 * MA interrupt handler.
4343 */
4344 static void ma_intr_handler(struct adapter *adap)
4345 {
4346 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4347
4348 if (status & MEM_PERR_INT_CAUSE_F) {
4349 dev_alert(adap->pdev_dev,
4350 "MA parity error, parity status %#x\n",
4351 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4352 if (is_t5(adap->params.chip))
4353 dev_alert(adap->pdev_dev,
4354 "MA parity error, parity status %#x\n",
4355 t4_read_reg(adap,
4356 MA_PARITY_ERROR_STATUS2_A));
4357 }
4358 if (status & MEM_WRAP_INT_CAUSE_F) {
4359 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4360 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4361 "client %u to address %#x\n",
4362 MEM_WRAP_CLIENT_NUM_G(v),
4363 MEM_WRAP_ADDRESS_G(v) << 4);
4364 }
4365 t4_write_reg(adap, MA_INT_CAUSE_A, status);
4366 t4_fatal_err(adap);
4367 }
4368
4369 /*
4370 * SMB interrupt handler.
4371 */
4372 static void smb_intr_handler(struct adapter *adap)
4373 {
4374 static const struct intr_info smb_intr_info[] = {
4375 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4376 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4377 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4378 { 0 }
4379 };
4380
4381 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4382 t4_fatal_err(adap);
4383 }
4384
4385 /*
4386 * NC-SI interrupt handler.
4387 */
4388 static void ncsi_intr_handler(struct adapter *adap)
4389 {
4390 static const struct intr_info ncsi_intr_info[] = {
4391 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4392 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4393 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4394 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4395 { 0 }
4396 };
4397
4398 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4399 t4_fatal_err(adap);
4400 }
4401
4402 /*
4403 * XGMAC interrupt handler.
4404 */
4405 static void xgmac_intr_handler(struct adapter *adap, int port)
4406 {
4407 u32 v, int_cause_reg;
4408
4409 if (is_t4(adap->params.chip))
4410 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4411 else
4412 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4413
4414 v = t4_read_reg(adap, int_cause_reg);
4415
4416 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4417 if (!v)
4418 return;
4419
4420 if (v & TXFIFO_PRTY_ERR_F)
4421 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4422 port);
4423 if (v & RXFIFO_PRTY_ERR_F)
4424 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4425 port);
4426 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4427 t4_fatal_err(adap);
4428 }
4429
4430 /*
4431 * PL interrupt handler.
4432 */
4433 static void pl_intr_handler(struct adapter *adap)
4434 {
4435 static const struct intr_info pl_intr_info[] = {
4436 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4437 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4438 { 0 }
4439 };
4440
4441 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4442 t4_fatal_err(adap);
4443 }
4444
4445 #define PF_INTR_MASK (PFSW_F)
4446 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4447 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4448 CPL_SWITCH_F | SGE_F | ULP_TX_F)
4449
4450 /**
4451 * t4_slow_intr_handler - control path interrupt handler
4452 * @adapter: the adapter
4453 *
4454 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
4455 * The designation 'slow' is because it involves register reads, while
4456 * data interrupts typically don't involve any MMIOs.
4457 */
4458 int t4_slow_intr_handler(struct adapter *adapter)
4459 {
4460 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4461
4462 if (!(cause & GLBL_INTR_MASK))
4463 return 0;
4464 if (cause & CIM_F)
4465 cim_intr_handler(adapter);
4466 if (cause & MPS_F)
4467 mps_intr_handler(adapter);
4468 if (cause & NCSI_F)
4469 ncsi_intr_handler(adapter);
4470 if (cause & PL_F)
4471 pl_intr_handler(adapter);
4472 if (cause & SMB_F)
4473 smb_intr_handler(adapter);
4474 if (cause & XGMAC0_F)
4475 xgmac_intr_handler(adapter, 0);
4476 if (cause & XGMAC1_F)
4477 xgmac_intr_handler(adapter, 1);
4478 if (cause & XGMAC_KR0_F)
4479 xgmac_intr_handler(adapter, 2);
4480 if (cause & XGMAC_KR1_F)
4481 xgmac_intr_handler(adapter, 3);
4482 if (cause & PCIE_F)
4483 pcie_intr_handler(adapter);
4484 if (cause & MC_F)
4485 mem_intr_handler(adapter, MEM_MC);
4486 if (is_t5(adapter->params.chip) && (cause & MC1_F))
4487 mem_intr_handler(adapter, MEM_MC1);
4488 if (cause & EDC0_F)
4489 mem_intr_handler(adapter, MEM_EDC0);
4490 if (cause & EDC1_F)
4491 mem_intr_handler(adapter, MEM_EDC1);
4492 if (cause & LE_F)
4493 le_intr_handler(adapter);
4494 if (cause & TP_F)
4495 tp_intr_handler(adapter);
4496 if (cause & MA_F)
4497 ma_intr_handler(adapter);
4498 if (cause & PM_TX_F)
4499 pmtx_intr_handler(adapter);
4500 if (cause & PM_RX_F)
4501 pmrx_intr_handler(adapter);
4502 if (cause & ULP_RX_F)
4503 ulprx_intr_handler(adapter);
4504 if (cause & CPL_SWITCH_F)
4505 cplsw_intr_handler(adapter);
4506 if (cause & SGE_F)
4507 sge_intr_handler(adapter);
4508 if (cause & ULP_TX_F)
4509 ulptx_intr_handler(adapter);
4510
4511 /* Clear the interrupts just processed for which we are the master. */
4512 t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4513 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4514 return 1;
4515 }
4516
4517 /**
4518 * t4_intr_enable - enable interrupts
4519 * @adapter: the adapter whose interrupts should be enabled
4520 *
4521 * Enable PF-specific interrupts for the calling function and the top-level
4522 * interrupt concentrator for global interrupts. Interrupts are already
4523 * enabled at each module, here we just enable the roots of the interrupt
4524 * hierarchies.
4525 *
4526 * Note: this function should be called only when the driver manages
4527 * non PF-specific interrupts from the various HW modules. Only one PCI
4528 * function at a time should be doing this.
4529 */
4530 void t4_intr_enable(struct adapter *adapter)
4531 {
4532 u32 val = 0;
4533 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4534 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4535 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4536
4537 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4538 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4539 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4540 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4541 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4542 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4543 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4544 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4545 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4546 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4547 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4548 }
4549
4550 /**
4551 * t4_intr_disable - disable interrupts
4552 * @adapter: the adapter whose interrupts should be disabled
4553 *
4554 * Disable interrupts. We only disable the top-level interrupt
4555 * concentrators. The caller must be a PCI function managing global
4556 * interrupts.
4557 */
4558 void t4_intr_disable(struct adapter *adapter)
4559 {
4560 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4561 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4562 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4563
4564 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4565 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
4566 }
4567
4568 /**
4569 * t4_config_rss_range - configure a portion of the RSS mapping table
4570 * @adapter: the adapter
4571 * @mbox: mbox to use for the FW command
4572 * @viid: virtual interface whose RSS subtable is to be written
4573 * @start: start entry in the table to write
4574 * @n: how many table entries to write
4575 * @rspq: values for the response queue lookup table
4576 * @nrspq: number of values in @rspq
4577 *
4578 * Programs the selected part of the VI's RSS mapping table with the
4579 * provided values. If @nrspq < @n the supplied values are used repeatedly
4580 * until the full table range is populated.
4581 *
4582 * The caller must ensure the values in @rspq are in the range allowed for
4583 * @viid.
4584 */
4585 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4586 int start, int n, const u16 *rspq, unsigned int nrspq)
4587 {
4588 int ret;
4589 const u16 *rsp = rspq;
4590 const u16 *rsp_end = rspq + nrspq;
4591 struct fw_rss_ind_tbl_cmd cmd;
4592
4593 memset(&cmd, 0, sizeof(cmd));
4594 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
4595 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4596 FW_RSS_IND_TBL_CMD_VIID_V(viid));
4597 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4598
4599 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
4600 while (n > 0) {
4601 int nq = min(n, 32);
4602 __be32 *qp = &cmd.iq0_to_iq2;
4603
4604 cmd.niqid = cpu_to_be16(nq);
4605 cmd.startidx = cpu_to_be16(start);
4606
4607 start += nq;
4608 n -= nq;
4609
4610 while (nq > 0) {
4611 unsigned int v;
4612
4613 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
4614 if (++rsp >= rsp_end)
4615 rsp = rspq;
4616 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
4617 if (++rsp >= rsp_end)
4618 rsp = rspq;
4619 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
4620 if (++rsp >= rsp_end)
4621 rsp = rspq;
4622
4623 *qp++ = cpu_to_be32(v);
4624 nq -= 3;
4625 }
4626
4627 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4628 if (ret)
4629 return ret;
4630 }
4631 return 0;
4632 }
4633
4634 /**
4635 * t4_config_glbl_rss - configure the global RSS mode
4636 * @adapter: the adapter
4637 * @mbox: mbox to use for the FW command
4638 * @mode: global RSS mode
4639 * @flags: mode-specific flags
4640 *
4641 * Sets the global RSS mode.
4642 */
4643 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4644 unsigned int flags)
4645 {
4646 struct fw_rss_glb_config_cmd c;
4647
4648 memset(&c, 0, sizeof(c));
4649 c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
4650 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
4651 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4652 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4653 c.u.manual.mode_pkd =
4654 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4655 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4656 c.u.basicvirtual.mode_pkd =
4657 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4658 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4659 } else
4660 return -EINVAL;
4661 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4662 }
4663
4664 /**
4665 * t4_config_vi_rss - configure per VI RSS settings
4666 * @adapter: the adapter
4667 * @mbox: mbox to use for the FW command
4668 * @viid: the VI id
4669 * @flags: RSS flags
4670 * @defq: id of the default RSS queue for the VI.
4671 *
4672 * Configures VI-specific RSS properties.
4673 */
4674 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
4675 unsigned int flags, unsigned int defq)
4676 {
4677 struct fw_rss_vi_config_cmd c;
4678
4679 memset(&c, 0, sizeof(c));
4680 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
4681 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4682 FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
4683 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4684 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
4685 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
4686 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4687 }
4688
4689 /* Read an RSS table row */
4690 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
4691 {
4692 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
4693 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
4694 5, 0, val);
4695 }
4696
4697 /**
4698 * t4_read_rss - read the contents of the RSS mapping table
4699 * @adapter: the adapter
4700 * @map: holds the contents of the RSS mapping table
4701 *
4702 * Reads the contents of the RSS hash->queue mapping table.
4703 */
4704 int t4_read_rss(struct adapter *adapter, u16 *map)
4705 {
4706 u32 val;
4707 int i, ret;
4708
4709 for (i = 0; i < RSS_NENTRIES / 2; ++i) {
4710 ret = rd_rss_row(adapter, i, &val);
4711 if (ret)
4712 return ret;
4713 *map++ = LKPTBLQUEUE0_G(val);
4714 *map++ = LKPTBLQUEUE1_G(val);
4715 }
4716 return 0;
4717 }
4718
4719 static unsigned int t4_use_ldst(struct adapter *adap)
4720 {
4721 return (adap->flags & FW_OK) || !adap->use_bd;
4722 }
4723
4724 /**
4725 * t4_fw_tp_pio_rw - Access TP PIO through LDST
4726 * @adap: the adapter
4727 * @vals: where the indirect register values are stored/written
4728 * @nregs: how many indirect registers to read/write
4729 * @start_idx: index of first indirect register to read/write
4730 * @rw: Read (1) or Write (0)
4731 *
4732 * Access TP PIO registers through LDST
4733 */
4734 static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
4735 unsigned int start_index, unsigned int rw)
4736 {
4737 int ret, i;
4738 int cmd = FW_LDST_ADDRSPC_TP_PIO;
4739 struct fw_ldst_cmd c;
4740
4741 for (i = 0 ; i < nregs; i++) {
4742 memset(&c, 0, sizeof(c));
4743 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
4744 FW_CMD_REQUEST_F |
4745 (rw ? FW_CMD_READ_F :
4746 FW_CMD_WRITE_F) |
4747 FW_LDST_CMD_ADDRSPACE_V(cmd));
4748 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4749
4750 c.u.addrval.addr = cpu_to_be32(start_index + i);
4751 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
4752 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4753 if (!ret && rw)
4754 vals[i] = be32_to_cpu(c.u.addrval.val);
4755 }
4756 }
4757
4758 /**
4759 * t4_read_rss_key - read the global RSS key
4760 * @adap: the adapter
4761 * @key: 10-entry array holding the 320-bit RSS key
4762 *
4763 * Reads the global 320-bit RSS key.
4764 */
4765 void t4_read_rss_key(struct adapter *adap, u32 *key)
4766 {
4767 if (t4_use_ldst(adap))
4768 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1);
4769 else
4770 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4771 TP_RSS_SECRET_KEY0_A);
4772 }
4773
4774 /**
4775 * t4_write_rss_key - program one of the RSS keys
4776 * @adap: the adapter
4777 * @key: 10-entry array holding the 320-bit RSS key
4778 * @idx: which RSS key to write
4779 *
4780 * Writes one of the RSS keys with the given 320-bit value. If @idx is
4781 * 0..15 the corresponding entry in the RSS key table is written,
4782 * otherwise the global RSS key is written.
4783 */
4784 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx)
4785 {
4786 u8 rss_key_addr_cnt = 16;
4787 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
4788
4789 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
4790 * allows access to key addresses 16-63 by using KeyWrAddrX
4791 * as index[5:4](upper 2) into key table
4792 */
4793 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
4794 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
4795 rss_key_addr_cnt = 32;
4796
4797 if (t4_use_ldst(adap))
4798 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0);
4799 else
4800 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4801 TP_RSS_SECRET_KEY0_A);
4802
4803 if (idx >= 0 && idx < rss_key_addr_cnt) {
4804 if (rss_key_addr_cnt > 16)
4805 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4806 KEYWRADDRX_V(idx >> 4) |
4807 T6_VFWRADDR_V(idx) | KEYWREN_F);
4808 else
4809 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4810 KEYWRADDR_V(idx) | KEYWREN_F);
4811 }
4812 }
4813
4814 /**
4815 * t4_read_rss_pf_config - read PF RSS Configuration Table
4816 * @adapter: the adapter
4817 * @index: the entry in the PF RSS table to read
4818 * @valp: where to store the returned value
4819 *
4820 * Reads the PF RSS Configuration Table at the specified index and returns
4821 * the value found there.
4822 */
4823 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
4824 u32 *valp)
4825 {
4826 if (t4_use_ldst(adapter))
4827 t4_fw_tp_pio_rw(adapter, valp, 1,
4828 TP_RSS_PF0_CONFIG_A + index, 1);
4829 else
4830 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4831 valp, 1, TP_RSS_PF0_CONFIG_A + index);
4832 }
4833
4834 /**
4835 * t4_read_rss_vf_config - read VF RSS Configuration Table
4836 * @adapter: the adapter
4837 * @index: the entry in the VF RSS table to read
4838 * @vfl: where to store the returned VFL
4839 * @vfh: where to store the returned VFH
4840 *
4841 * Reads the VF RSS Configuration Table at the specified index and returns
4842 * the (VFL, VFH) values found there.
4843 */
4844 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
4845 u32 *vfl, u32 *vfh)
4846 {
4847 u32 vrt, mask, data;
4848
4849 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
4850 mask = VFWRADDR_V(VFWRADDR_M);
4851 data = VFWRADDR_V(index);
4852 } else {
4853 mask = T6_VFWRADDR_V(T6_VFWRADDR_M);
4854 data = T6_VFWRADDR_V(index);
4855 }
4856
4857 /* Request that the index'th VF Table values be read into VFL/VFH.
4858 */
4859 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
4860 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
4861 vrt |= data | VFRDEN_F;
4862 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
4863
4864 /* Grab the VFL/VFH values ...
4865 */
4866 if (t4_use_ldst(adapter)) {
4867 t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1);
4868 t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1);
4869 } else {
4870 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4871 vfl, 1, TP_RSS_VFL_CONFIG_A);
4872 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4873 vfh, 1, TP_RSS_VFH_CONFIG_A);
4874 }
4875 }
4876
4877 /**
4878 * t4_read_rss_pf_map - read PF RSS Map
4879 * @adapter: the adapter
4880 *
4881 * Reads the PF RSS Map register and returns its value.
4882 */
4883 u32 t4_read_rss_pf_map(struct adapter *adapter)
4884 {
4885 u32 pfmap;
4886
4887 if (t4_use_ldst(adapter))
4888 t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1);
4889 else
4890 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4891 &pfmap, 1, TP_RSS_PF_MAP_A);
4892 return pfmap;
4893 }
4894
4895 /**
4896 * t4_read_rss_pf_mask - read PF RSS Mask
4897 * @adapter: the adapter
4898 *
4899 * Reads the PF RSS Mask register and returns its value.
4900 */
4901 u32 t4_read_rss_pf_mask(struct adapter *adapter)
4902 {
4903 u32 pfmask;
4904
4905 if (t4_use_ldst(adapter))
4906 t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1);
4907 else
4908 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4909 &pfmask, 1, TP_RSS_PF_MSK_A);
4910 return pfmask;
4911 }
4912
4913 /**
4914 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
4915 * @adap: the adapter
4916 * @v4: holds the TCP/IP counter values
4917 * @v6: holds the TCP/IPv6 counter values
4918 *
4919 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
4920 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
4921 */
4922 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
4923 struct tp_tcp_stats *v6)
4924 {
4925 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
4926
4927 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
4928 #define STAT(x) val[STAT_IDX(x)]
4929 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
4930
4931 if (v4) {
4932 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4933 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A);
4934 v4->tcp_out_rsts = STAT(OUT_RST);
4935 v4->tcp_in_segs = STAT64(IN_SEG);
4936 v4->tcp_out_segs = STAT64(OUT_SEG);
4937 v4->tcp_retrans_segs = STAT64(RXT_SEG);
4938 }
4939 if (v6) {
4940 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4941 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A);
4942 v6->tcp_out_rsts = STAT(OUT_RST);
4943 v6->tcp_in_segs = STAT64(IN_SEG);
4944 v6->tcp_out_segs = STAT64(OUT_SEG);
4945 v6->tcp_retrans_segs = STAT64(RXT_SEG);
4946 }
4947 #undef STAT64
4948 #undef STAT
4949 #undef STAT_IDX
4950 }
4951
4952 /**
4953 * t4_tp_get_err_stats - read TP's error MIB counters
4954 * @adap: the adapter
4955 * @st: holds the counter values
4956 *
4957 * Returns the values of TP's error counters.
4958 */
4959 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
4960 {
4961 int nchan = adap->params.arch.nchan;
4962
4963 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4964 st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A);
4965 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4966 st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A);
4967 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4968 st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A);
4969 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4970 st->tnl_cong_drops, nchan, TP_MIB_TNL_CNG_DROP_0_A);
4971 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4972 st->ofld_chan_drops, nchan, TP_MIB_OFD_CHN_DROP_0_A);
4973 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4974 st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A);
4975 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4976 st->ofld_vlan_drops, nchan, TP_MIB_OFD_VLN_DROP_0_A);
4977 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4978 st->tcp6_in_errs, nchan, TP_MIB_TCP_V6IN_ERR_0_A);
4979
4980 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4981 &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A);
4982 }
4983
4984 /**
4985 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
4986 * @adap: the adapter
4987 * @st: holds the counter values
4988 *
4989 * Returns the values of TP's CPL counters.
4990 */
4991 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
4992 {
4993 int nchan = adap->params.arch.nchan;
4994
4995 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req,
4996 nchan, TP_MIB_CPL_IN_REQ_0_A);
4997 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp,
4998 nchan, TP_MIB_CPL_OUT_RSP_0_A);
4999
5000 }
5001
5002 /**
5003 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5004 * @adap: the adapter
5005 * @st: holds the counter values
5006 *
5007 * Returns the values of TP's RDMA counters.
5008 */
5009 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
5010 {
5011 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt,
5012 2, TP_MIB_RQE_DFR_PKT_A);
5013 }
5014
5015 /**
5016 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5017 * @adap: the adapter
5018 * @idx: the port index
5019 * @st: holds the counter values
5020 *
5021 * Returns the values of TP's FCoE counters for the selected port.
5022 */
5023 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5024 struct tp_fcoe_stats *st)
5025 {
5026 u32 val[2];
5027
5028 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp,
5029 1, TP_MIB_FCOE_DDP_0_A + idx);
5030 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop,
5031 1, TP_MIB_FCOE_DROP_0_A + idx);
5032 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
5033 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx);
5034 st->octets_ddp = ((u64)val[0] << 32) | val[1];
5035 }
5036
5037 /**
5038 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5039 * @adap: the adapter
5040 * @st: holds the counter values
5041 *
5042 * Returns the values of TP's counters for non-TCP directly-placed packets.
5043 */
5044 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
5045 {
5046 u32 val[4];
5047
5048 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4,
5049 TP_MIB_USM_PKTS_A);
5050 st->frames = val[0];
5051 st->drops = val[1];
5052 st->octets = ((u64)val[2] << 32) | val[3];
5053 }
5054
5055 /**
5056 * t4_read_mtu_tbl - returns the values in the HW path MTU table
5057 * @adap: the adapter
5058 * @mtus: where to store the MTU values
5059 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
5060 *
5061 * Reads the HW path MTU table.
5062 */
5063 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5064 {
5065 u32 v;
5066 int i;
5067
5068 for (i = 0; i < NMTUS; ++i) {
5069 t4_write_reg(adap, TP_MTU_TABLE_A,
5070 MTUINDEX_V(0xff) | MTUVALUE_V(i));
5071 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5072 mtus[i] = MTUVALUE_G(v);
5073 if (mtu_log)
5074 mtu_log[i] = MTUWIDTH_G(v);
5075 }
5076 }
5077
5078 /**
5079 * t4_read_cong_tbl - reads the congestion control table
5080 * @adap: the adapter
5081 * @incr: where to store the alpha values
5082 *
5083 * Reads the additive increments programmed into the HW congestion
5084 * control table.
5085 */
5086 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5087 {
5088 unsigned int mtu, w;
5089
5090 for (mtu = 0; mtu < NMTUS; ++mtu)
5091 for (w = 0; w < NCCTRL_WIN; ++w) {
5092 t4_write_reg(adap, TP_CCTRL_TABLE_A,
5093 ROWINDEX_V(0xffff) | (mtu << 5) | w);
5094 incr[mtu][w] = (u16)t4_read_reg(adap,
5095 TP_CCTRL_TABLE_A) & 0x1fff;
5096 }
5097 }
5098
5099 /**
5100 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5101 * @adap: the adapter
5102 * @addr: the indirect TP register address
5103 * @mask: specifies the field within the register to modify
5104 * @val: new value for the field
5105 *
5106 * Sets a field of an indirect TP register to the given value.
5107 */
5108 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5109 unsigned int mask, unsigned int val)
5110 {
5111 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5112 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5113 t4_write_reg(adap, TP_PIO_DATA_A, val);
5114 }
5115
5116 /**
5117 * init_cong_ctrl - initialize congestion control parameters
5118 * @a: the alpha values for congestion control
5119 * @b: the beta values for congestion control
5120 *
5121 * Initialize the congestion control parameters.
5122 */
5123 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5124 {
5125 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5126 a[9] = 2;
5127 a[10] = 3;
5128 a[11] = 4;
5129 a[12] = 5;
5130 a[13] = 6;
5131 a[14] = 7;
5132 a[15] = 8;
5133 a[16] = 9;
5134 a[17] = 10;
5135 a[18] = 14;
5136 a[19] = 17;
5137 a[20] = 21;
5138 a[21] = 25;
5139 a[22] = 30;
5140 a[23] = 35;
5141 a[24] = 45;
5142 a[25] = 60;
5143 a[26] = 80;
5144 a[27] = 100;
5145 a[28] = 200;
5146 a[29] = 300;
5147 a[30] = 400;
5148 a[31] = 500;
5149
5150 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5151 b[9] = b[10] = 1;
5152 b[11] = b[12] = 2;
5153 b[13] = b[14] = b[15] = b[16] = 3;
5154 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5155 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5156 b[28] = b[29] = 6;
5157 b[30] = b[31] = 7;
5158 }
5159
5160 /* The minimum additive increment value for the congestion control table */
5161 #define CC_MIN_INCR 2U
5162
5163 /**
5164 * t4_load_mtus - write the MTU and congestion control HW tables
5165 * @adap: the adapter
5166 * @mtus: the values for the MTU table
5167 * @alpha: the values for the congestion control alpha parameter
5168 * @beta: the values for the congestion control beta parameter
5169 *
5170 * Write the HW MTU table with the supplied MTUs and the high-speed
5171 * congestion control table with the supplied alpha, beta, and MTUs.
5172 * We write the two tables together because the additive increments
5173 * depend on the MTUs.
5174 */
5175 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5176 const unsigned short *alpha, const unsigned short *beta)
5177 {
5178 static const unsigned int avg_pkts[NCCTRL_WIN] = {
5179 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5180 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5181 28672, 40960, 57344, 81920, 114688, 163840, 229376
5182 };
5183
5184 unsigned int i, w;
5185
5186 for (i = 0; i < NMTUS; ++i) {
5187 unsigned int mtu = mtus[i];
5188 unsigned int log2 = fls(mtu);
5189
5190 if (!(mtu & ((1 << log2) >> 2))) /* round */
5191 log2--;
5192 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5193 MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5194
5195 for (w = 0; w < NCCTRL_WIN; ++w) {
5196 unsigned int inc;
5197
5198 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5199 CC_MIN_INCR);
5200
5201 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5202 (w << 16) | (beta[w] << 13) | inc);
5203 }
5204 }
5205 }
5206
5207 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5208 * clocks. The formula is
5209 *
5210 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5211 *
5212 * which is equivalent to
5213 *
5214 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5215 */
5216 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5217 {
5218 u64 v = bytes256 * adap->params.vpd.cclk;
5219
5220 return v * 62 + v / 2;
5221 }
5222
5223 /**
5224 * t4_get_chan_txrate - get the current per channel Tx rates
5225 * @adap: the adapter
5226 * @nic_rate: rates for NIC traffic
5227 * @ofld_rate: rates for offloaded traffic
5228 *
5229 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5230 * for each channel.
5231 */
5232 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5233 {
5234 u32 v;
5235
5236 v = t4_read_reg(adap, TP_TX_TRATE_A);
5237 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5238 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5239 if (adap->params.arch.nchan == NCHAN) {
5240 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5241 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5242 }
5243
5244 v = t4_read_reg(adap, TP_TX_ORATE_A);
5245 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5246 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5247 if (adap->params.arch.nchan == NCHAN) {
5248 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5249 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5250 }
5251 }
5252
5253 /**
5254 * t4_set_trace_filter - configure one of the tracing filters
5255 * @adap: the adapter
5256 * @tp: the desired trace filter parameters
5257 * @idx: which filter to configure
5258 * @enable: whether to enable or disable the filter
5259 *
5260 * Configures one of the tracing filters available in HW. If @enable is
5261 * %0 @tp is not examined and may be %NULL. The user is responsible to
5262 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5263 */
5264 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5265 int idx, int enable)
5266 {
5267 int i, ofst = idx * 4;
5268 u32 data_reg, mask_reg, cfg;
5269 u32 multitrc = TRCMULTIFILTER_F;
5270
5271 if (!enable) {
5272 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5273 return 0;
5274 }
5275
5276 cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5277 if (cfg & TRCMULTIFILTER_F) {
5278 /* If multiple tracers are enabled, then maximum
5279 * capture size is 2.5KB (FIFO size of a single channel)
5280 * minus 2 flits for CPL_TRACE_PKT header.
5281 */
5282 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5283 return -EINVAL;
5284 } else {
5285 /* If multiple tracers are disabled, to avoid deadlocks
5286 * maximum packet capture size of 9600 bytes is recommended.
5287 * Also in this mode, only trace0 can be enabled and running.
5288 */
5289 multitrc = 0;
5290 if (tp->snap_len > 9600 || idx)
5291 return -EINVAL;
5292 }
5293
5294 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5295 tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5296 tp->min_len > TFMINPKTSIZE_M)
5297 return -EINVAL;
5298
5299 /* stop the tracer we'll be changing */
5300 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5301
5302 idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5303 data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5304 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5305
5306 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5307 t4_write_reg(adap, data_reg, tp->data[i]);
5308 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5309 }
5310 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5311 TFCAPTUREMAX_V(tp->snap_len) |
5312 TFMINPKTSIZE_V(tp->min_len));
5313 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5314 TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5315 (is_t4(adap->params.chip) ?
5316 TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5317 T5_TFPORT_V(tp->port) | T5_TFEN_F |
5318 T5_TFINVERTMATCH_V(tp->invert)));
5319
5320 return 0;
5321 }
5322
5323 /**
5324 * t4_get_trace_filter - query one of the tracing filters
5325 * @adap: the adapter
5326 * @tp: the current trace filter parameters
5327 * @idx: which trace filter to query
5328 * @enabled: non-zero if the filter is enabled
5329 *
5330 * Returns the current settings of one of the HW tracing filters.
5331 */
5332 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5333 int *enabled)
5334 {
5335 u32 ctla, ctlb;
5336 int i, ofst = idx * 4;
5337 u32 data_reg, mask_reg;
5338
5339 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5340 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5341
5342 if (is_t4(adap->params.chip)) {
5343 *enabled = !!(ctla & TFEN_F);
5344 tp->port = TFPORT_G(ctla);
5345 tp->invert = !!(ctla & TFINVERTMATCH_F);
5346 } else {
5347 *enabled = !!(ctla & T5_TFEN_F);
5348 tp->port = T5_TFPORT_G(ctla);
5349 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5350 }
5351 tp->snap_len = TFCAPTUREMAX_G(ctlb);
5352 tp->min_len = TFMINPKTSIZE_G(ctlb);
5353 tp->skip_ofst = TFOFFSET_G(ctla);
5354 tp->skip_len = TFLENGTH_G(ctla);
5355
5356 ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5357 data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5358 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5359
5360 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5361 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5362 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5363 }
5364 }
5365
5366 /**
5367 * t4_pmtx_get_stats - returns the HW stats from PMTX
5368 * @adap: the adapter
5369 * @cnt: where to store the count statistics
5370 * @cycles: where to store the cycle statistics
5371 *
5372 * Returns performance statistics from PMTX.
5373 */
5374 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5375 {
5376 int i;
5377 u32 data[2];
5378
5379 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5380 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5381 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5382 if (is_t4(adap->params.chip)) {
5383 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5384 } else {
5385 t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5386 PM_TX_DBG_DATA_A, data, 2,
5387 PM_TX_DBG_STAT_MSB_A);
5388 cycles[i] = (((u64)data[0] << 32) | data[1]);
5389 }
5390 }
5391 }
5392
5393 /**
5394 * t4_pmrx_get_stats - returns the HW stats from PMRX
5395 * @adap: the adapter
5396 * @cnt: where to store the count statistics
5397 * @cycles: where to store the cycle statistics
5398 *
5399 * Returns performance statistics from PMRX.
5400 */
5401 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5402 {
5403 int i;
5404 u32 data[2];
5405
5406 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5407 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5408 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5409 if (is_t4(adap->params.chip)) {
5410 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5411 } else {
5412 t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5413 PM_RX_DBG_DATA_A, data, 2,
5414 PM_RX_DBG_STAT_MSB_A);
5415 cycles[i] = (((u64)data[0] << 32) | data[1]);
5416 }
5417 }
5418 }
5419
5420 /**
5421 * t4_get_mps_bg_map - return the buffer groups associated with a port
5422 * @adap: the adapter
5423 * @idx: the port index
5424 *
5425 * Returns a bitmap indicating which MPS buffer groups are associated
5426 * with the given port. Bit i is set if buffer group i is used by the
5427 * port.
5428 */
5429 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
5430 {
5431 u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
5432
5433 if (n == 0)
5434 return idx == 0 ? 0xf : 0;
5435 /* In T6 (which is a 2 port card),
5436 * port 0 is mapped to channel 0 and port 1 is mapped to channel 1.
5437 * For 2 port T4/T5 adapter,
5438 * port 0 is mapped to channel 0 and 1,
5439 * port 1 is mapped to channel 2 and 3.
5440 */
5441 if ((n == 1) &&
5442 (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
5443 return idx < 2 ? (3 << (2 * idx)) : 0;
5444 return 1 << idx;
5445 }
5446
5447 /**
5448 * t4_get_port_type_description - return Port Type string description
5449 * @port_type: firmware Port Type enumeration
5450 */
5451 const char *t4_get_port_type_description(enum fw_port_type port_type)
5452 {
5453 static const char *const port_type_description[] = {
5454 "Fiber_XFI",
5455 "Fiber_XAUI",
5456 "BT_SGMII",
5457 "BT_XFI",
5458 "BT_XAUI",
5459 "KX4",
5460 "CX4",
5461 "KX",
5462 "KR",
5463 "SFP",
5464 "BP_AP",
5465 "BP4_AP",
5466 "QSFP_10G",
5467 "QSA",
5468 "QSFP",
5469 "BP40_BA",
5470 "KR4_100G",
5471 "CR4_QSFP",
5472 "CR_QSFP",
5473 "CR2_QSFP",
5474 "SFP28",
5475 "KR_SFP28",
5476 };
5477
5478 if (port_type < ARRAY_SIZE(port_type_description))
5479 return port_type_description[port_type];
5480 return "UNKNOWN";
5481 }
5482
5483 /**
5484 * t4_get_port_stats_offset - collect port stats relative to a previous
5485 * snapshot
5486 * @adap: The adapter
5487 * @idx: The port
5488 * @stats: Current stats to fill
5489 * @offset: Previous stats snapshot
5490 */
5491 void t4_get_port_stats_offset(struct adapter *adap, int idx,
5492 struct port_stats *stats,
5493 struct port_stats *offset)
5494 {
5495 u64 *s, *o;
5496 int i;
5497
5498 t4_get_port_stats(adap, idx, stats);
5499 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
5500 i < (sizeof(struct port_stats) / sizeof(u64));
5501 i++, s++, o++)
5502 *s -= *o;
5503 }
5504
5505 /**
5506 * t4_get_port_stats - collect port statistics
5507 * @adap: the adapter
5508 * @idx: the port index
5509 * @p: the stats structure to fill
5510 *
5511 * Collect statistics related to the given port from HW.
5512 */
5513 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5514 {
5515 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5516 u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
5517
5518 #define GET_STAT(name) \
5519 t4_read_reg64(adap, \
5520 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
5521 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
5522 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5523
5524 p->tx_octets = GET_STAT(TX_PORT_BYTES);
5525 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
5526 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
5527 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
5528 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
5529 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
5530 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
5531 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
5532 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
5533 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
5534 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
5535 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
5536 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
5537 p->tx_drop = GET_STAT(TX_PORT_DROP);
5538 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
5539 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
5540 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
5541 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
5542 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
5543 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
5544 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
5545 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
5546 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
5547
5548 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
5549 if (stat_ctl & COUNTPAUSESTATTX_F) {
5550 p->tx_frames -= p->tx_pause;
5551 p->tx_octets -= p->tx_pause * 64;
5552 }
5553 if (stat_ctl & COUNTPAUSEMCTX_F)
5554 p->tx_mcast_frames -= p->tx_pause;
5555 }
5556 p->rx_octets = GET_STAT(RX_PORT_BYTES);
5557 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
5558 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
5559 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
5560 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
5561 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
5562 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
5563 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
5564 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
5565 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
5566 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
5567 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
5568 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
5569 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
5570 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
5571 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
5572 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
5573 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
5574 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
5575 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
5576 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
5577 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
5578 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
5579 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
5580 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
5581 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
5582 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
5583
5584 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
5585 if (stat_ctl & COUNTPAUSESTATRX_F) {
5586 p->rx_frames -= p->rx_pause;
5587 p->rx_octets -= p->rx_pause * 64;
5588 }
5589 if (stat_ctl & COUNTPAUSEMCRX_F)
5590 p->rx_mcast_frames -= p->rx_pause;
5591 }
5592
5593 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
5594 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
5595 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
5596 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
5597 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
5598 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
5599 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
5600 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
5601
5602 #undef GET_STAT
5603 #undef GET_STAT_COM
5604 }
5605
5606 /**
5607 * t4_get_lb_stats - collect loopback port statistics
5608 * @adap: the adapter
5609 * @idx: the loopback port index
5610 * @p: the stats structure to fill
5611 *
5612 * Return HW statistics for the given loopback port.
5613 */
5614 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
5615 {
5616 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5617
5618 #define GET_STAT(name) \
5619 t4_read_reg64(adap, \
5620 (is_t4(adap->params.chip) ? \
5621 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
5622 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
5623 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5624
5625 p->octets = GET_STAT(BYTES);
5626 p->frames = GET_STAT(FRAMES);
5627 p->bcast_frames = GET_STAT(BCAST);
5628 p->mcast_frames = GET_STAT(MCAST);
5629 p->ucast_frames = GET_STAT(UCAST);
5630 p->error_frames = GET_STAT(ERROR);
5631
5632 p->frames_64 = GET_STAT(64B);
5633 p->frames_65_127 = GET_STAT(65B_127B);
5634 p->frames_128_255 = GET_STAT(128B_255B);
5635 p->frames_256_511 = GET_STAT(256B_511B);
5636 p->frames_512_1023 = GET_STAT(512B_1023B);
5637 p->frames_1024_1518 = GET_STAT(1024B_1518B);
5638 p->frames_1519_max = GET_STAT(1519B_MAX);
5639 p->drop = GET_STAT(DROP_FRAMES);
5640
5641 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
5642 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
5643 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
5644 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
5645 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
5646 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
5647 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
5648 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
5649
5650 #undef GET_STAT
5651 #undef GET_STAT_COM
5652 }
5653
5654 /* t4_mk_filtdelwr - create a delete filter WR
5655 * @ftid: the filter ID
5656 * @wr: the filter work request to populate
5657 * @qid: ingress queue to receive the delete notification
5658 *
5659 * Creates a filter work request to delete the supplied filter. If @qid is
5660 * negative the delete notification is suppressed.
5661 */
5662 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
5663 {
5664 memset(wr, 0, sizeof(*wr));
5665 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
5666 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
5667 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
5668 FW_FILTER_WR_NOREPLY_V(qid < 0));
5669 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
5670 if (qid >= 0)
5671 wr->rx_chan_rx_rpl_iq =
5672 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
5673 }
5674
5675 #define INIT_CMD(var, cmd, rd_wr) do { \
5676 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
5677 FW_CMD_REQUEST_F | \
5678 FW_CMD_##rd_wr##_F); \
5679 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
5680 } while (0)
5681
5682 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
5683 u32 addr, u32 val)
5684 {
5685 u32 ldst_addrspace;
5686 struct fw_ldst_cmd c;
5687
5688 memset(&c, 0, sizeof(c));
5689 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
5690 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5691 FW_CMD_REQUEST_F |
5692 FW_CMD_WRITE_F |
5693 ldst_addrspace);
5694 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5695 c.u.addrval.addr = cpu_to_be32(addr);
5696 c.u.addrval.val = cpu_to_be32(val);
5697
5698 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5699 }
5700
5701 /**
5702 * t4_mdio_rd - read a PHY register through MDIO
5703 * @adap: the adapter
5704 * @mbox: mailbox to use for the FW command
5705 * @phy_addr: the PHY address
5706 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5707 * @reg: the register to read
5708 * @valp: where to store the value
5709 *
5710 * Issues a FW command through the given mailbox to read a PHY register.
5711 */
5712 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5713 unsigned int mmd, unsigned int reg, u16 *valp)
5714 {
5715 int ret;
5716 u32 ldst_addrspace;
5717 struct fw_ldst_cmd c;
5718
5719 memset(&c, 0, sizeof(c));
5720 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5721 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5722 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5723 ldst_addrspace);
5724 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5725 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5726 FW_LDST_CMD_MMD_V(mmd));
5727 c.u.mdio.raddr = cpu_to_be16(reg);
5728
5729 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5730 if (ret == 0)
5731 *valp = be16_to_cpu(c.u.mdio.rval);
5732 return ret;
5733 }
5734
5735 /**
5736 * t4_mdio_wr - write a PHY register through MDIO
5737 * @adap: the adapter
5738 * @mbox: mailbox to use for the FW command
5739 * @phy_addr: the PHY address
5740 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5741 * @reg: the register to write
5742 * @valp: value to write
5743 *
5744 * Issues a FW command through the given mailbox to write a PHY register.
5745 */
5746 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5747 unsigned int mmd, unsigned int reg, u16 val)
5748 {
5749 u32 ldst_addrspace;
5750 struct fw_ldst_cmd c;
5751
5752 memset(&c, 0, sizeof(c));
5753 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5754 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5755 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5756 ldst_addrspace);
5757 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5758 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5759 FW_LDST_CMD_MMD_V(mmd));
5760 c.u.mdio.raddr = cpu_to_be16(reg);
5761 c.u.mdio.rval = cpu_to_be16(val);
5762
5763 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5764 }
5765
5766 /**
5767 * t4_sge_decode_idma_state - decode the idma state
5768 * @adap: the adapter
5769 * @state: the state idma is stuck in
5770 */
5771 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
5772 {
5773 static const char * const t4_decode[] = {
5774 "IDMA_IDLE",
5775 "IDMA_PUSH_MORE_CPL_FIFO",
5776 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5777 "Not used",
5778 "IDMA_PHYSADDR_SEND_PCIEHDR",
5779 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5780 "IDMA_PHYSADDR_SEND_PAYLOAD",
5781 "IDMA_SEND_FIFO_TO_IMSG",
5782 "IDMA_FL_REQ_DATA_FL_PREP",
5783 "IDMA_FL_REQ_DATA_FL",
5784 "IDMA_FL_DROP",
5785 "IDMA_FL_H_REQ_HEADER_FL",
5786 "IDMA_FL_H_SEND_PCIEHDR",
5787 "IDMA_FL_H_PUSH_CPL_FIFO",
5788 "IDMA_FL_H_SEND_CPL",
5789 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5790 "IDMA_FL_H_SEND_IP_HDR",
5791 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5792 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5793 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5794 "IDMA_FL_D_SEND_PCIEHDR",
5795 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5796 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5797 "IDMA_FL_SEND_PCIEHDR",
5798 "IDMA_FL_PUSH_CPL_FIFO",
5799 "IDMA_FL_SEND_CPL",
5800 "IDMA_FL_SEND_PAYLOAD_FIRST",
5801 "IDMA_FL_SEND_PAYLOAD",
5802 "IDMA_FL_REQ_NEXT_DATA_FL",
5803 "IDMA_FL_SEND_NEXT_PCIEHDR",
5804 "IDMA_FL_SEND_PADDING",
5805 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5806 "IDMA_FL_SEND_FIFO_TO_IMSG",
5807 "IDMA_FL_REQ_DATAFL_DONE",
5808 "IDMA_FL_REQ_HEADERFL_DONE",
5809 };
5810 static const char * const t5_decode[] = {
5811 "IDMA_IDLE",
5812 "IDMA_ALMOST_IDLE",
5813 "IDMA_PUSH_MORE_CPL_FIFO",
5814 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5815 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5816 "IDMA_PHYSADDR_SEND_PCIEHDR",
5817 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5818 "IDMA_PHYSADDR_SEND_PAYLOAD",
5819 "IDMA_SEND_FIFO_TO_IMSG",
5820 "IDMA_FL_REQ_DATA_FL",
5821 "IDMA_FL_DROP",
5822 "IDMA_FL_DROP_SEND_INC",
5823 "IDMA_FL_H_REQ_HEADER_FL",
5824 "IDMA_FL_H_SEND_PCIEHDR",
5825 "IDMA_FL_H_PUSH_CPL_FIFO",
5826 "IDMA_FL_H_SEND_CPL",
5827 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5828 "IDMA_FL_H_SEND_IP_HDR",
5829 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5830 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5831 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5832 "IDMA_FL_D_SEND_PCIEHDR",
5833 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5834 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5835 "IDMA_FL_SEND_PCIEHDR",
5836 "IDMA_FL_PUSH_CPL_FIFO",
5837 "IDMA_FL_SEND_CPL",
5838 "IDMA_FL_SEND_PAYLOAD_FIRST",
5839 "IDMA_FL_SEND_PAYLOAD",
5840 "IDMA_FL_REQ_NEXT_DATA_FL",
5841 "IDMA_FL_SEND_NEXT_PCIEHDR",
5842 "IDMA_FL_SEND_PADDING",
5843 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5844 };
5845 static const char * const t6_decode[] = {
5846 "IDMA_IDLE",
5847 "IDMA_PUSH_MORE_CPL_FIFO",
5848 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5849 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5850 "IDMA_PHYSADDR_SEND_PCIEHDR",
5851 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5852 "IDMA_PHYSADDR_SEND_PAYLOAD",
5853 "IDMA_FL_REQ_DATA_FL",
5854 "IDMA_FL_DROP",
5855 "IDMA_FL_DROP_SEND_INC",
5856 "IDMA_FL_H_REQ_HEADER_FL",
5857 "IDMA_FL_H_SEND_PCIEHDR",
5858 "IDMA_FL_H_PUSH_CPL_FIFO",
5859 "IDMA_FL_H_SEND_CPL",
5860 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5861 "IDMA_FL_H_SEND_IP_HDR",
5862 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5863 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5864 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5865 "IDMA_FL_D_SEND_PCIEHDR",
5866 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5867 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5868 "IDMA_FL_SEND_PCIEHDR",
5869 "IDMA_FL_PUSH_CPL_FIFO",
5870 "IDMA_FL_SEND_CPL",
5871 "IDMA_FL_SEND_PAYLOAD_FIRST",
5872 "IDMA_FL_SEND_PAYLOAD",
5873 "IDMA_FL_REQ_NEXT_DATA_FL",
5874 "IDMA_FL_SEND_NEXT_PCIEHDR",
5875 "IDMA_FL_SEND_PADDING",
5876 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5877 };
5878 static const u32 sge_regs[] = {
5879 SGE_DEBUG_DATA_LOW_INDEX_2_A,
5880 SGE_DEBUG_DATA_LOW_INDEX_3_A,
5881 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
5882 };
5883 const char **sge_idma_decode;
5884 int sge_idma_decode_nstates;
5885 int i;
5886 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
5887
5888 /* Select the right set of decode strings to dump depending on the
5889 * adapter chip type.
5890 */
5891 switch (chip_version) {
5892 case CHELSIO_T4:
5893 sge_idma_decode = (const char **)t4_decode;
5894 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5895 break;
5896
5897 case CHELSIO_T5:
5898 sge_idma_decode = (const char **)t5_decode;
5899 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5900 break;
5901
5902 case CHELSIO_T6:
5903 sge_idma_decode = (const char **)t6_decode;
5904 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
5905 break;
5906
5907 default:
5908 dev_err(adapter->pdev_dev,
5909 "Unsupported chip version %d\n", chip_version);
5910 return;
5911 }
5912
5913 if (is_t4(adapter->params.chip)) {
5914 sge_idma_decode = (const char **)t4_decode;
5915 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5916 } else {
5917 sge_idma_decode = (const char **)t5_decode;
5918 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5919 }
5920
5921 if (state < sge_idma_decode_nstates)
5922 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
5923 else
5924 CH_WARN(adapter, "idma state %d unknown\n", state);
5925
5926 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
5927 CH_WARN(adapter, "SGE register %#x value %#x\n",
5928 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
5929 }
5930
5931 /**
5932 * t4_sge_ctxt_flush - flush the SGE context cache
5933 * @adap: the adapter
5934 * @mbox: mailbox to use for the FW command
5935 *
5936 * Issues a FW command through the given mailbox to flush the
5937 * SGE context cache.
5938 */
5939 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
5940 {
5941 int ret;
5942 u32 ldst_addrspace;
5943 struct fw_ldst_cmd c;
5944
5945 memset(&c, 0, sizeof(c));
5946 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC);
5947 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5948 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5949 ldst_addrspace);
5950 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5951 c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
5952
5953 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5954 return ret;
5955 }
5956
5957 /**
5958 * t4_fw_hello - establish communication with FW
5959 * @adap: the adapter
5960 * @mbox: mailbox to use for the FW command
5961 * @evt_mbox: mailbox to receive async FW events
5962 * @master: specifies the caller's willingness to be the device master
5963 * @state: returns the current device state (if non-NULL)
5964 *
5965 * Issues a command to establish communication with FW. Returns either
5966 * an error (negative integer) or the mailbox of the Master PF.
5967 */
5968 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
5969 enum dev_master master, enum dev_state *state)
5970 {
5971 int ret;
5972 struct fw_hello_cmd c;
5973 u32 v;
5974 unsigned int master_mbox;
5975 int retries = FW_CMD_HELLO_RETRIES;
5976
5977 retry:
5978 memset(&c, 0, sizeof(c));
5979 INIT_CMD(c, HELLO, WRITE);
5980 c.err_to_clearinit = cpu_to_be32(
5981 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
5982 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
5983 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
5984 mbox : FW_HELLO_CMD_MBMASTER_M) |
5985 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
5986 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
5987 FW_HELLO_CMD_CLEARINIT_F);
5988
5989 /*
5990 * Issue the HELLO command to the firmware. If it's not successful
5991 * but indicates that we got a "busy" or "timeout" condition, retry
5992 * the HELLO until we exhaust our retry limit. If we do exceed our
5993 * retry limit, check to see if the firmware left us any error
5994 * information and report that if so.
5995 */
5996 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5997 if (ret < 0) {
5998 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
5999 goto retry;
6000 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
6001 t4_report_fw_error(adap);
6002 return ret;
6003 }
6004
6005 v = be32_to_cpu(c.err_to_clearinit);
6006 master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
6007 if (state) {
6008 if (v & FW_HELLO_CMD_ERR_F)
6009 *state = DEV_STATE_ERR;
6010 else if (v & FW_HELLO_CMD_INIT_F)
6011 *state = DEV_STATE_INIT;
6012 else
6013 *state = DEV_STATE_UNINIT;
6014 }
6015
6016 /*
6017 * If we're not the Master PF then we need to wait around for the
6018 * Master PF Driver to finish setting up the adapter.
6019 *
6020 * Note that we also do this wait if we're a non-Master-capable PF and
6021 * there is no current Master PF; a Master PF may show up momentarily
6022 * and we wouldn't want to fail pointlessly. (This can happen when an
6023 * OS loads lots of different drivers rapidly at the same time). In
6024 * this case, the Master PF returned by the firmware will be
6025 * PCIE_FW_MASTER_M so the test below will work ...
6026 */
6027 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
6028 master_mbox != mbox) {
6029 int waiting = FW_CMD_HELLO_TIMEOUT;
6030
6031 /*
6032 * Wait for the firmware to either indicate an error or
6033 * initialized state. If we see either of these we bail out
6034 * and report the issue to the caller. If we exhaust the
6035 * "hello timeout" and we haven't exhausted our retries, try
6036 * again. Otherwise bail with a timeout error.
6037 */
6038 for (;;) {
6039 u32 pcie_fw;
6040
6041 msleep(50);
6042 waiting -= 50;
6043
6044 /*
6045 * If neither Error nor Initialialized are indicated
6046 * by the firmware keep waiting till we exaust our
6047 * timeout ... and then retry if we haven't exhausted
6048 * our retries ...
6049 */
6050 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
6051 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
6052 if (waiting <= 0) {
6053 if (retries-- > 0)
6054 goto retry;
6055
6056 return -ETIMEDOUT;
6057 }
6058 continue;
6059 }
6060
6061 /*
6062 * We either have an Error or Initialized condition
6063 * report errors preferentially.
6064 */
6065 if (state) {
6066 if (pcie_fw & PCIE_FW_ERR_F)
6067 *state = DEV_STATE_ERR;
6068 else if (pcie_fw & PCIE_FW_INIT_F)
6069 *state = DEV_STATE_INIT;
6070 }
6071
6072 /*
6073 * If we arrived before a Master PF was selected and
6074 * there's not a valid Master PF, grab its identity
6075 * for our caller.
6076 */
6077 if (master_mbox == PCIE_FW_MASTER_M &&
6078 (pcie_fw & PCIE_FW_MASTER_VLD_F))
6079 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
6080 break;
6081 }
6082 }
6083
6084 return master_mbox;
6085 }
6086
6087 /**
6088 * t4_fw_bye - end communication with FW
6089 * @adap: the adapter
6090 * @mbox: mailbox to use for the FW command
6091 *
6092 * Issues a command to terminate communication with FW.
6093 */
6094 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6095 {
6096 struct fw_bye_cmd c;
6097
6098 memset(&c, 0, sizeof(c));
6099 INIT_CMD(c, BYE, WRITE);
6100 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6101 }
6102
6103 /**
6104 * t4_init_cmd - ask FW to initialize the device
6105 * @adap: the adapter
6106 * @mbox: mailbox to use for the FW command
6107 *
6108 * Issues a command to FW to partially initialize the device. This
6109 * performs initialization that generally doesn't depend on user input.
6110 */
6111 int t4_early_init(struct adapter *adap, unsigned int mbox)
6112 {
6113 struct fw_initialize_cmd c;
6114
6115 memset(&c, 0, sizeof(c));
6116 INIT_CMD(c, INITIALIZE, WRITE);
6117 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6118 }
6119
6120 /**
6121 * t4_fw_reset - issue a reset to FW
6122 * @adap: the adapter
6123 * @mbox: mailbox to use for the FW command
6124 * @reset: specifies the type of reset to perform
6125 *
6126 * Issues a reset command of the specified type to FW.
6127 */
6128 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6129 {
6130 struct fw_reset_cmd c;
6131
6132 memset(&c, 0, sizeof(c));
6133 INIT_CMD(c, RESET, WRITE);
6134 c.val = cpu_to_be32(reset);
6135 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6136 }
6137
6138 /**
6139 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6140 * @adap: the adapter
6141 * @mbox: mailbox to use for the FW RESET command (if desired)
6142 * @force: force uP into RESET even if FW RESET command fails
6143 *
6144 * Issues a RESET command to firmware (if desired) with a HALT indication
6145 * and then puts the microprocessor into RESET state. The RESET command
6146 * will only be issued if a legitimate mailbox is provided (mbox <=
6147 * PCIE_FW_MASTER_M).
6148 *
6149 * This is generally used in order for the host to safely manipulate the
6150 * adapter without fear of conflicting with whatever the firmware might
6151 * be doing. The only way out of this state is to RESTART the firmware
6152 * ...
6153 */
6154 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6155 {
6156 int ret = 0;
6157
6158 /*
6159 * If a legitimate mailbox is provided, issue a RESET command
6160 * with a HALT indication.
6161 */
6162 if (mbox <= PCIE_FW_MASTER_M) {
6163 struct fw_reset_cmd c;
6164
6165 memset(&c, 0, sizeof(c));
6166 INIT_CMD(c, RESET, WRITE);
6167 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
6168 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
6169 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6170 }
6171
6172 /*
6173 * Normally we won't complete the operation if the firmware RESET
6174 * command fails but if our caller insists we'll go ahead and put the
6175 * uP into RESET. This can be useful if the firmware is hung or even
6176 * missing ... We'll have to take the risk of putting the uP into
6177 * RESET without the cooperation of firmware in that case.
6178 *
6179 * We also force the firmware's HALT flag to be on in case we bypassed
6180 * the firmware RESET command above or we're dealing with old firmware
6181 * which doesn't have the HALT capability. This will serve as a flag
6182 * for the incoming firmware to know that it's coming out of a HALT
6183 * rather than a RESET ... if it's new enough to understand that ...
6184 */
6185 if (ret == 0 || force) {
6186 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
6187 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
6188 PCIE_FW_HALT_F);
6189 }
6190
6191 /*
6192 * And we always return the result of the firmware RESET command
6193 * even when we force the uP into RESET ...
6194 */
6195 return ret;
6196 }
6197
6198 /**
6199 * t4_fw_restart - restart the firmware by taking the uP out of RESET
6200 * @adap: the adapter
6201 * @reset: if we want to do a RESET to restart things
6202 *
6203 * Restart firmware previously halted by t4_fw_halt(). On successful
6204 * return the previous PF Master remains as the new PF Master and there
6205 * is no need to issue a new HELLO command, etc.
6206 *
6207 * We do this in two ways:
6208 *
6209 * 1. If we're dealing with newer firmware we'll simply want to take
6210 * the chip's microprocessor out of RESET. This will cause the
6211 * firmware to start up from its start vector. And then we'll loop
6212 * until the firmware indicates it's started again (PCIE_FW.HALT
6213 * reset to 0) or we timeout.
6214 *
6215 * 2. If we're dealing with older firmware then we'll need to RESET
6216 * the chip since older firmware won't recognize the PCIE_FW.HALT
6217 * flag and automatically RESET itself on startup.
6218 */
6219 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6220 {
6221 if (reset) {
6222 /*
6223 * Since we're directing the RESET instead of the firmware
6224 * doing it automatically, we need to clear the PCIE_FW.HALT
6225 * bit.
6226 */
6227 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6228
6229 /*
6230 * If we've been given a valid mailbox, first try to get the
6231 * firmware to do the RESET. If that works, great and we can
6232 * return success. Otherwise, if we haven't been given a
6233 * valid mailbox or the RESET command failed, fall back to
6234 * hitting the chip with a hammer.
6235 */
6236 if (mbox <= PCIE_FW_MASTER_M) {
6237 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6238 msleep(100);
6239 if (t4_fw_reset(adap, mbox,
6240 PIORST_F | PIORSTMODE_F) == 0)
6241 return 0;
6242 }
6243
6244 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6245 msleep(2000);
6246 } else {
6247 int ms;
6248
6249 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6250 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6251 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6252 return 0;
6253 msleep(100);
6254 ms += 100;
6255 }
6256 return -ETIMEDOUT;
6257 }
6258 return 0;
6259 }
6260
6261 /**
6262 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6263 * @adap: the adapter
6264 * @mbox: mailbox to use for the FW RESET command (if desired)
6265 * @fw_data: the firmware image to write
6266 * @size: image size
6267 * @force: force upgrade even if firmware doesn't cooperate
6268 *
6269 * Perform all of the steps necessary for upgrading an adapter's
6270 * firmware image. Normally this requires the cooperation of the
6271 * existing firmware in order to halt all existing activities
6272 * but if an invalid mailbox token is passed in we skip that step
6273 * (though we'll still put the adapter microprocessor into RESET in
6274 * that case).
6275 *
6276 * On successful return the new firmware will have been loaded and
6277 * the adapter will have been fully RESET losing all previous setup
6278 * state. On unsuccessful return the adapter may be completely hosed ...
6279 * positive errno indicates that the adapter is ~probably~ intact, a
6280 * negative errno indicates that things are looking bad ...
6281 */
6282 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6283 const u8 *fw_data, unsigned int size, int force)
6284 {
6285 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6286 int reset, ret;
6287
6288 if (!t4_fw_matches_chip(adap, fw_hdr))
6289 return -EINVAL;
6290
6291 ret = t4_fw_halt(adap, mbox, force);
6292 if (ret < 0 && !force)
6293 return ret;
6294
6295 ret = t4_load_fw(adap, fw_data, size);
6296 if (ret < 0)
6297 return ret;
6298
6299 /*
6300 * Older versions of the firmware don't understand the new
6301 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6302 * restart. So for newly loaded older firmware we'll have to do the
6303 * RESET for it so it starts up on a clean slate. We can tell if
6304 * the newly loaded firmware will handle this right by checking
6305 * its header flags to see if it advertises the capability.
6306 */
6307 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6308 return t4_fw_restart(adap, mbox, reset);
6309 }
6310
6311 /**
6312 * t4_fl_pkt_align - return the fl packet alignment
6313 * @adap: the adapter
6314 *
6315 * T4 has a single field to specify the packing and padding boundary.
6316 * T5 onwards has separate fields for this and hence the alignment for
6317 * next packet offset is maximum of these two.
6318 *
6319 */
6320 int t4_fl_pkt_align(struct adapter *adap)
6321 {
6322 u32 sge_control, sge_control2;
6323 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
6324
6325 sge_control = t4_read_reg(adap, SGE_CONTROL_A);
6326
6327 /* T4 uses a single control field to specify both the PCIe Padding and
6328 * Packing Boundary. T5 introduced the ability to specify these
6329 * separately. The actual Ingress Packet Data alignment boundary
6330 * within Packed Buffer Mode is the maximum of these two
6331 * specifications. (Note that it makes no real practical sense to
6332 * have the Pading Boudary be larger than the Packing Boundary but you
6333 * could set the chip up that way and, in fact, legacy T4 code would
6334 * end doing this because it would initialize the Padding Boundary and
6335 * leave the Packing Boundary initialized to 0 (16 bytes).)
6336 * Padding Boundary values in T6 starts from 8B,
6337 * where as it is 32B for T4 and T5.
6338 */
6339 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
6340 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
6341 else
6342 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
6343
6344 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
6345
6346 fl_align = ingpadboundary;
6347 if (!is_t4(adap->params.chip)) {
6348 /* T5 has a weird interpretation of one of the PCIe Packing
6349 * Boundary values. No idea why ...
6350 */
6351 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
6352 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
6353 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
6354 ingpackboundary = 16;
6355 else
6356 ingpackboundary = 1 << (ingpackboundary +
6357 INGPACKBOUNDARY_SHIFT_X);
6358
6359 fl_align = max(ingpadboundary, ingpackboundary);
6360 }
6361 return fl_align;
6362 }
6363
6364 /**
6365 * t4_fixup_host_params - fix up host-dependent parameters
6366 * @adap: the adapter
6367 * @page_size: the host's Base Page Size
6368 * @cache_line_size: the host's Cache Line Size
6369 *
6370 * Various registers in T4 contain values which are dependent on the
6371 * host's Base Page and Cache Line Sizes. This function will fix all of
6372 * those registers with the appropriate values as passed in ...
6373 */
6374 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
6375 unsigned int cache_line_size)
6376 {
6377 unsigned int page_shift = fls(page_size) - 1;
6378 unsigned int sge_hps = page_shift - 10;
6379 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
6380 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
6381 unsigned int fl_align_log = fls(fl_align) - 1;
6382
6383 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
6384 HOSTPAGESIZEPF0_V(sge_hps) |
6385 HOSTPAGESIZEPF1_V(sge_hps) |
6386 HOSTPAGESIZEPF2_V(sge_hps) |
6387 HOSTPAGESIZEPF3_V(sge_hps) |
6388 HOSTPAGESIZEPF4_V(sge_hps) |
6389 HOSTPAGESIZEPF5_V(sge_hps) |
6390 HOSTPAGESIZEPF6_V(sge_hps) |
6391 HOSTPAGESIZEPF7_V(sge_hps));
6392
6393 if (is_t4(adap->params.chip)) {
6394 t4_set_reg_field(adap, SGE_CONTROL_A,
6395 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6396 EGRSTATUSPAGESIZE_F,
6397 INGPADBOUNDARY_V(fl_align_log -
6398 INGPADBOUNDARY_SHIFT_X) |
6399 EGRSTATUSPAGESIZE_V(stat_len != 64));
6400 } else {
6401 unsigned int pack_align;
6402 unsigned int ingpad, ingpack;
6403 unsigned int pcie_cap;
6404
6405 /* T5 introduced the separation of the Free List Padding and
6406 * Packing Boundaries. Thus, we can select a smaller Padding
6407 * Boundary to avoid uselessly chewing up PCIe Link and Memory
6408 * Bandwidth, and use a Packing Boundary which is large enough
6409 * to avoid false sharing between CPUs, etc.
6410 *
6411 * For the PCI Link, the smaller the Padding Boundary the
6412 * better. For the Memory Controller, a smaller Padding
6413 * Boundary is better until we cross under the Memory Line
6414 * Size (the minimum unit of transfer to/from Memory). If we
6415 * have a Padding Boundary which is smaller than the Memory
6416 * Line Size, that'll involve a Read-Modify-Write cycle on the
6417 * Memory Controller which is never good.
6418 */
6419
6420 /* We want the Packing Boundary to be based on the Cache Line
6421 * Size in order to help avoid False Sharing performance
6422 * issues between CPUs, etc. We also want the Packing
6423 * Boundary to incorporate the PCI-E Maximum Payload Size. We
6424 * get best performance when the Packing Boundary is a
6425 * multiple of the Maximum Payload Size.
6426 */
6427 pack_align = fl_align;
6428 pcie_cap = pci_find_capability(adap->pdev, PCI_CAP_ID_EXP);
6429 if (pcie_cap) {
6430 unsigned int mps, mps_log;
6431 u16 devctl;
6432
6433 /* The PCIe Device Control Maximum Payload Size field
6434 * [bits 7:5] encodes sizes as powers of 2 starting at
6435 * 128 bytes.
6436 */
6437 pci_read_config_word(adap->pdev,
6438 pcie_cap + PCI_EXP_DEVCTL,
6439 &devctl);
6440 mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
6441 mps = 1 << mps_log;
6442 if (mps > pack_align)
6443 pack_align = mps;
6444 }
6445
6446 /* N.B. T5/T6 have a crazy special interpretation of the "0"
6447 * value for the Packing Boundary. This corresponds to 16
6448 * bytes instead of the expected 32 bytes. So if we want 32
6449 * bytes, the best we can really do is 64 bytes ...
6450 */
6451 if (pack_align <= 16) {
6452 ingpack = INGPACKBOUNDARY_16B_X;
6453 fl_align = 16;
6454 } else if (pack_align == 32) {
6455 ingpack = INGPACKBOUNDARY_64B_X;
6456 fl_align = 64;
6457 } else {
6458 unsigned int pack_align_log = fls(pack_align) - 1;
6459
6460 ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X;
6461 fl_align = pack_align;
6462 }
6463
6464 /* Use the smallest Ingress Padding which isn't smaller than
6465 * the Memory Controller Read/Write Size. We'll take that as
6466 * being 8 bytes since we don't know of any system with a
6467 * wider Memory Controller Bus Width.
6468 */
6469 if (is_t5(adap->params.chip))
6470 ingpad = INGPADBOUNDARY_32B_X;
6471 else
6472 ingpad = T6_INGPADBOUNDARY_8B_X;
6473
6474 t4_set_reg_field(adap, SGE_CONTROL_A,
6475 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6476 EGRSTATUSPAGESIZE_F,
6477 INGPADBOUNDARY_V(ingpad) |
6478 EGRSTATUSPAGESIZE_V(stat_len != 64));
6479 t4_set_reg_field(adap, SGE_CONTROL2_A,
6480 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
6481 INGPACKBOUNDARY_V(ingpack));
6482 }
6483 /*
6484 * Adjust various SGE Free List Host Buffer Sizes.
6485 *
6486 * This is something of a crock since we're using fixed indices into
6487 * the array which are also known by the sge.c code and the T4
6488 * Firmware Configuration File. We need to come up with a much better
6489 * approach to managing this array. For now, the first four entries
6490 * are:
6491 *
6492 * 0: Host Page Size
6493 * 1: 64KB
6494 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
6495 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
6496 *
6497 * For the single-MTU buffers in unpacked mode we need to include
6498 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
6499 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
6500 * Padding boundary. All of these are accommodated in the Factory
6501 * Default Firmware Configuration File but we need to adjust it for
6502 * this host's cache line size.
6503 */
6504 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
6505 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
6506 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
6507 & ~(fl_align-1));
6508 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
6509 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
6510 & ~(fl_align-1));
6511
6512 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
6513
6514 return 0;
6515 }
6516
6517 /**
6518 * t4_fw_initialize - ask FW to initialize the device
6519 * @adap: the adapter
6520 * @mbox: mailbox to use for the FW command
6521 *
6522 * Issues a command to FW to partially initialize the device. This
6523 * performs initialization that generally doesn't depend on user input.
6524 */
6525 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
6526 {
6527 struct fw_initialize_cmd c;
6528
6529 memset(&c, 0, sizeof(c));
6530 INIT_CMD(c, INITIALIZE, WRITE);
6531 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6532 }
6533
6534 /**
6535 * t4_query_params_rw - query FW or device parameters
6536 * @adap: the adapter
6537 * @mbox: mailbox to use for the FW command
6538 * @pf: the PF
6539 * @vf: the VF
6540 * @nparams: the number of parameters
6541 * @params: the parameter names
6542 * @val: the parameter values
6543 * @rw: Write and read flag
6544 *
6545 * Reads the value of FW or device parameters. Up to 7 parameters can be
6546 * queried at once.
6547 */
6548 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
6549 unsigned int vf, unsigned int nparams, const u32 *params,
6550 u32 *val, int rw)
6551 {
6552 int i, ret;
6553 struct fw_params_cmd c;
6554 __be32 *p = &c.param[0].mnem;
6555
6556 if (nparams > 7)
6557 return -EINVAL;
6558
6559 memset(&c, 0, sizeof(c));
6560 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6561 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6562 FW_PARAMS_CMD_PFN_V(pf) |
6563 FW_PARAMS_CMD_VFN_V(vf));
6564 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6565
6566 for (i = 0; i < nparams; i++) {
6567 *p++ = cpu_to_be32(*params++);
6568 if (rw)
6569 *p = cpu_to_be32(*(val + i));
6570 p++;
6571 }
6572
6573 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6574 if (ret == 0)
6575 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
6576 *val++ = be32_to_cpu(*p);
6577 return ret;
6578 }
6579
6580 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6581 unsigned int vf, unsigned int nparams, const u32 *params,
6582 u32 *val)
6583 {
6584 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
6585 }
6586
6587 /**
6588 * t4_set_params_timeout - sets FW or device parameters
6589 * @adap: the adapter
6590 * @mbox: mailbox to use for the FW command
6591 * @pf: the PF
6592 * @vf: the VF
6593 * @nparams: the number of parameters
6594 * @params: the parameter names
6595 * @val: the parameter values
6596 * @timeout: the timeout time
6597 *
6598 * Sets the value of FW or device parameters. Up to 7 parameters can be
6599 * specified at once.
6600 */
6601 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
6602 unsigned int pf, unsigned int vf,
6603 unsigned int nparams, const u32 *params,
6604 const u32 *val, int timeout)
6605 {
6606 struct fw_params_cmd c;
6607 __be32 *p = &c.param[0].mnem;
6608
6609 if (nparams > 7)
6610 return -EINVAL;
6611
6612 memset(&c, 0, sizeof(c));
6613 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6614 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6615 FW_PARAMS_CMD_PFN_V(pf) |
6616 FW_PARAMS_CMD_VFN_V(vf));
6617 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6618
6619 while (nparams--) {
6620 *p++ = cpu_to_be32(*params++);
6621 *p++ = cpu_to_be32(*val++);
6622 }
6623
6624 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
6625 }
6626
6627 /**
6628 * t4_set_params - sets FW or device parameters
6629 * @adap: the adapter
6630 * @mbox: mailbox to use for the FW command
6631 * @pf: the PF
6632 * @vf: the VF
6633 * @nparams: the number of parameters
6634 * @params: the parameter names
6635 * @val: the parameter values
6636 *
6637 * Sets the value of FW or device parameters. Up to 7 parameters can be
6638 * specified at once.
6639 */
6640 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6641 unsigned int vf, unsigned int nparams, const u32 *params,
6642 const u32 *val)
6643 {
6644 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
6645 FW_CMD_MAX_TIMEOUT);
6646 }
6647
6648 /**
6649 * t4_cfg_pfvf - configure PF/VF resource limits
6650 * @adap: the adapter
6651 * @mbox: mailbox to use for the FW command
6652 * @pf: the PF being configured
6653 * @vf: the VF being configured
6654 * @txq: the max number of egress queues
6655 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
6656 * @rxqi: the max number of interrupt-capable ingress queues
6657 * @rxq: the max number of interruptless ingress queues
6658 * @tc: the PCI traffic class
6659 * @vi: the max number of virtual interfaces
6660 * @cmask: the channel access rights mask for the PF/VF
6661 * @pmask: the port access rights mask for the PF/VF
6662 * @nexact: the maximum number of exact MPS filters
6663 * @rcaps: read capabilities
6664 * @wxcaps: write/execute capabilities
6665 *
6666 * Configures resource limits and capabilities for a physical or virtual
6667 * function.
6668 */
6669 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
6670 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
6671 unsigned int rxqi, unsigned int rxq, unsigned int tc,
6672 unsigned int vi, unsigned int cmask, unsigned int pmask,
6673 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
6674 {
6675 struct fw_pfvf_cmd c;
6676
6677 memset(&c, 0, sizeof(c));
6678 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
6679 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
6680 FW_PFVF_CMD_VFN_V(vf));
6681 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6682 c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
6683 FW_PFVF_CMD_NIQ_V(rxq));
6684 c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
6685 FW_PFVF_CMD_PMASK_V(pmask) |
6686 FW_PFVF_CMD_NEQ_V(txq));
6687 c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
6688 FW_PFVF_CMD_NVI_V(vi) |
6689 FW_PFVF_CMD_NEXACTF_V(nexact));
6690 c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
6691 FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
6692 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
6693 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6694 }
6695
6696 /**
6697 * t4_alloc_vi - allocate a virtual interface
6698 * @adap: the adapter
6699 * @mbox: mailbox to use for the FW command
6700 * @port: physical port associated with the VI
6701 * @pf: the PF owning the VI
6702 * @vf: the VF owning the VI
6703 * @nmac: number of MAC addresses needed (1 to 5)
6704 * @mac: the MAC addresses of the VI
6705 * @rss_size: size of RSS table slice associated with this VI
6706 *
6707 * Allocates a virtual interface for the given physical port. If @mac is
6708 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
6709 * @mac should be large enough to hold @nmac Ethernet addresses, they are
6710 * stored consecutively so the space needed is @nmac * 6 bytes.
6711 * Returns a negative error number or the non-negative VI id.
6712 */
6713 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
6714 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
6715 unsigned int *rss_size)
6716 {
6717 int ret;
6718 struct fw_vi_cmd c;
6719
6720 memset(&c, 0, sizeof(c));
6721 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
6722 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
6723 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
6724 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
6725 c.portid_pkd = FW_VI_CMD_PORTID_V(port);
6726 c.nmac = nmac - 1;
6727
6728 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6729 if (ret)
6730 return ret;
6731
6732 if (mac) {
6733 memcpy(mac, c.mac, sizeof(c.mac));
6734 switch (nmac) {
6735 case 5:
6736 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
6737 case 4:
6738 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
6739 case 3:
6740 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
6741 case 2:
6742 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
6743 }
6744 }
6745 if (rss_size)
6746 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
6747 return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
6748 }
6749
6750 /**
6751 * t4_free_vi - free a virtual interface
6752 * @adap: the adapter
6753 * @mbox: mailbox to use for the FW command
6754 * @pf: the PF owning the VI
6755 * @vf: the VF owning the VI
6756 * @viid: virtual interface identifiler
6757 *
6758 * Free a previously allocated virtual interface.
6759 */
6760 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
6761 unsigned int vf, unsigned int viid)
6762 {
6763 struct fw_vi_cmd c;
6764
6765 memset(&c, 0, sizeof(c));
6766 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
6767 FW_CMD_REQUEST_F |
6768 FW_CMD_EXEC_F |
6769 FW_VI_CMD_PFN_V(pf) |
6770 FW_VI_CMD_VFN_V(vf));
6771 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
6772 c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
6773
6774 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6775 }
6776
6777 /**
6778 * t4_set_rxmode - set Rx properties of a virtual interface
6779 * @adap: the adapter
6780 * @mbox: mailbox to use for the FW command
6781 * @viid: the VI id
6782 * @mtu: the new MTU or -1
6783 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
6784 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
6785 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
6786 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
6787 * @sleep_ok: if true we may sleep while awaiting command completion
6788 *
6789 * Sets Rx properties of a virtual interface.
6790 */
6791 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
6792 int mtu, int promisc, int all_multi, int bcast, int vlanex,
6793 bool sleep_ok)
6794 {
6795 struct fw_vi_rxmode_cmd c;
6796
6797 /* convert to FW values */
6798 if (mtu < 0)
6799 mtu = FW_RXMODE_MTU_NO_CHG;
6800 if (promisc < 0)
6801 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
6802 if (all_multi < 0)
6803 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
6804 if (bcast < 0)
6805 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
6806 if (vlanex < 0)
6807 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
6808
6809 memset(&c, 0, sizeof(c));
6810 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
6811 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6812 FW_VI_RXMODE_CMD_VIID_V(viid));
6813 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6814 c.mtu_to_vlanexen =
6815 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
6816 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
6817 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
6818 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
6819 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
6820 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6821 }
6822
6823 /**
6824 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
6825 * @adap: the adapter
6826 * @mbox: mailbox to use for the FW command
6827 * @viid: the VI id
6828 * @free: if true any existing filters for this VI id are first removed
6829 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
6830 * @addr: the MAC address(es)
6831 * @idx: where to store the index of each allocated filter
6832 * @hash: pointer to hash address filter bitmap
6833 * @sleep_ok: call is allowed to sleep
6834 *
6835 * Allocates an exact-match filter for each of the supplied addresses and
6836 * sets it to the corresponding address. If @idx is not %NULL it should
6837 * have at least @naddr entries, each of which will be set to the index of
6838 * the filter allocated for the corresponding MAC address. If a filter
6839 * could not be allocated for an address its index is set to 0xffff.
6840 * If @hash is not %NULL addresses that fail to allocate an exact filter
6841 * are hashed and update the hash filter bitmap pointed at by @hash.
6842 *
6843 * Returns a negative error number or the number of filters allocated.
6844 */
6845 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
6846 unsigned int viid, bool free, unsigned int naddr,
6847 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
6848 {
6849 int offset, ret = 0;
6850 struct fw_vi_mac_cmd c;
6851 unsigned int nfilters = 0;
6852 unsigned int max_naddr = adap->params.arch.mps_tcam_size;
6853 unsigned int rem = naddr;
6854
6855 if (naddr > max_naddr)
6856 return -EINVAL;
6857
6858 for (offset = 0; offset < naddr ; /**/) {
6859 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
6860 rem : ARRAY_SIZE(c.u.exact));
6861 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6862 u.exact[fw_naddr]), 16);
6863 struct fw_vi_mac_exact *p;
6864 int i;
6865
6866 memset(&c, 0, sizeof(c));
6867 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6868 FW_CMD_REQUEST_F |
6869 FW_CMD_WRITE_F |
6870 FW_CMD_EXEC_V(free) |
6871 FW_VI_MAC_CMD_VIID_V(viid));
6872 c.freemacs_to_len16 =
6873 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
6874 FW_CMD_LEN16_V(len16));
6875
6876 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6877 p->valid_to_idx =
6878 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6879 FW_VI_MAC_CMD_IDX_V(
6880 FW_VI_MAC_ADD_MAC));
6881 memcpy(p->macaddr, addr[offset + i],
6882 sizeof(p->macaddr));
6883 }
6884
6885 /* It's okay if we run out of space in our MAC address arena.
6886 * Some of the addresses we submit may get stored so we need
6887 * to run through the reply to see what the results were ...
6888 */
6889 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6890 if (ret && ret != -FW_ENOMEM)
6891 break;
6892
6893 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6894 u16 index = FW_VI_MAC_CMD_IDX_G(
6895 be16_to_cpu(p->valid_to_idx));
6896
6897 if (idx)
6898 idx[offset + i] = (index >= max_naddr ?
6899 0xffff : index);
6900 if (index < max_naddr)
6901 nfilters++;
6902 else if (hash)
6903 *hash |= (1ULL <<
6904 hash_mac_addr(addr[offset + i]));
6905 }
6906
6907 free = false;
6908 offset += fw_naddr;
6909 rem -= fw_naddr;
6910 }
6911
6912 if (ret == 0 || ret == -FW_ENOMEM)
6913 ret = nfilters;
6914 return ret;
6915 }
6916
6917 /**
6918 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
6919 * @adap: the adapter
6920 * @mbox: mailbox to use for the FW command
6921 * @viid: the VI id
6922 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
6923 * @addr: the MAC address(es)
6924 * @sleep_ok: call is allowed to sleep
6925 *
6926 * Frees the exact-match filter for each of the supplied addresses
6927 *
6928 * Returns a negative error number or the number of filters freed.
6929 */
6930 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
6931 unsigned int viid, unsigned int naddr,
6932 const u8 **addr, bool sleep_ok)
6933 {
6934 int offset, ret = 0;
6935 struct fw_vi_mac_cmd c;
6936 unsigned int nfilters = 0;
6937 unsigned int max_naddr = is_t4(adap->params.chip) ?
6938 NUM_MPS_CLS_SRAM_L_INSTANCES :
6939 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
6940 unsigned int rem = naddr;
6941
6942 if (naddr > max_naddr)
6943 return -EINVAL;
6944
6945 for (offset = 0; offset < (int)naddr ; /**/) {
6946 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
6947 ? rem
6948 : ARRAY_SIZE(c.u.exact));
6949 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6950 u.exact[fw_naddr]), 16);
6951 struct fw_vi_mac_exact *p;
6952 int i;
6953
6954 memset(&c, 0, sizeof(c));
6955 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6956 FW_CMD_REQUEST_F |
6957 FW_CMD_WRITE_F |
6958 FW_CMD_EXEC_V(0) |
6959 FW_VI_MAC_CMD_VIID_V(viid));
6960 c.freemacs_to_len16 =
6961 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
6962 FW_CMD_LEN16_V(len16));
6963
6964 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
6965 p->valid_to_idx = cpu_to_be16(
6966 FW_VI_MAC_CMD_VALID_F |
6967 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
6968 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
6969 }
6970
6971 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6972 if (ret)
6973 break;
6974
6975 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6976 u16 index = FW_VI_MAC_CMD_IDX_G(
6977 be16_to_cpu(p->valid_to_idx));
6978
6979 if (index < max_naddr)
6980 nfilters++;
6981 }
6982
6983 offset += fw_naddr;
6984 rem -= fw_naddr;
6985 }
6986
6987 if (ret == 0)
6988 ret = nfilters;
6989 return ret;
6990 }
6991
6992 /**
6993 * t4_change_mac - modifies the exact-match filter for a MAC address
6994 * @adap: the adapter
6995 * @mbox: mailbox to use for the FW command
6996 * @viid: the VI id
6997 * @idx: index of existing filter for old value of MAC address, or -1
6998 * @addr: the new MAC address value
6999 * @persist: whether a new MAC allocation should be persistent
7000 * @add_smt: if true also add the address to the HW SMT
7001 *
7002 * Modifies an exact-match filter and sets it to the new MAC address.
7003 * Note that in general it is not possible to modify the value of a given
7004 * filter so the generic way to modify an address filter is to free the one
7005 * being used by the old address value and allocate a new filter for the
7006 * new address value. @idx can be -1 if the address is a new addition.
7007 *
7008 * Returns a negative error number or the index of the filter with the new
7009 * MAC value.
7010 */
7011 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
7012 int idx, const u8 *addr, bool persist, bool add_smt)
7013 {
7014 int ret, mode;
7015 struct fw_vi_mac_cmd c;
7016 struct fw_vi_mac_exact *p = c.u.exact;
7017 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
7018
7019 if (idx < 0) /* new allocation */
7020 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
7021 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
7022
7023 memset(&c, 0, sizeof(c));
7024 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7025 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7026 FW_VI_MAC_CMD_VIID_V(viid));
7027 c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
7028 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7029 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
7030 FW_VI_MAC_CMD_IDX_V(idx));
7031 memcpy(p->macaddr, addr, sizeof(p->macaddr));
7032
7033 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7034 if (ret == 0) {
7035 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7036 if (ret >= max_mac_addr)
7037 ret = -ENOMEM;
7038 }
7039 return ret;
7040 }
7041
7042 /**
7043 * t4_set_addr_hash - program the MAC inexact-match hash filter
7044 * @adap: the adapter
7045 * @mbox: mailbox to use for the FW command
7046 * @viid: the VI id
7047 * @ucast: whether the hash filter should also match unicast addresses
7048 * @vec: the value to be written to the hash filter
7049 * @sleep_ok: call is allowed to sleep
7050 *
7051 * Sets the 64-bit inexact-match hash filter for a virtual interface.
7052 */
7053 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
7054 bool ucast, u64 vec, bool sleep_ok)
7055 {
7056 struct fw_vi_mac_cmd c;
7057
7058 memset(&c, 0, sizeof(c));
7059 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7060 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7061 FW_VI_ENABLE_CMD_VIID_V(viid));
7062 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
7063 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
7064 FW_CMD_LEN16_V(1));
7065 c.u.hash.hashvec = cpu_to_be64(vec);
7066 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7067 }
7068
7069 /**
7070 * t4_enable_vi_params - enable/disable a virtual interface
7071 * @adap: the adapter
7072 * @mbox: mailbox to use for the FW command
7073 * @viid: the VI id
7074 * @rx_en: 1=enable Rx, 0=disable Rx
7075 * @tx_en: 1=enable Tx, 0=disable Tx
7076 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
7077 *
7078 * Enables/disables a virtual interface. Note that setting DCB Enable
7079 * only makes sense when enabling a Virtual Interface ...
7080 */
7081 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
7082 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
7083 {
7084 struct fw_vi_enable_cmd c;
7085
7086 memset(&c, 0, sizeof(c));
7087 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7088 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7089 FW_VI_ENABLE_CMD_VIID_V(viid));
7090 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
7091 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
7092 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
7093 FW_LEN16(c));
7094 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
7095 }
7096
7097 /**
7098 * t4_enable_vi - enable/disable a virtual interface
7099 * @adap: the adapter
7100 * @mbox: mailbox to use for the FW command
7101 * @viid: the VI id
7102 * @rx_en: 1=enable Rx, 0=disable Rx
7103 * @tx_en: 1=enable Tx, 0=disable Tx
7104 *
7105 * Enables/disables a virtual interface.
7106 */
7107 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
7108 bool rx_en, bool tx_en)
7109 {
7110 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
7111 }
7112
7113 /**
7114 * t4_identify_port - identify a VI's port by blinking its LED
7115 * @adap: the adapter
7116 * @mbox: mailbox to use for the FW command
7117 * @viid: the VI id
7118 * @nblinks: how many times to blink LED at 2.5 Hz
7119 *
7120 * Identifies a VI's port by blinking its LED.
7121 */
7122 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
7123 unsigned int nblinks)
7124 {
7125 struct fw_vi_enable_cmd c;
7126
7127 memset(&c, 0, sizeof(c));
7128 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7129 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7130 FW_VI_ENABLE_CMD_VIID_V(viid));
7131 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
7132 c.blinkdur = cpu_to_be16(nblinks);
7133 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7134 }
7135
7136 /**
7137 * t4_iq_stop - stop an ingress queue and its FLs
7138 * @adap: the adapter
7139 * @mbox: mailbox to use for the FW command
7140 * @pf: the PF owning the queues
7141 * @vf: the VF owning the queues
7142 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7143 * @iqid: ingress queue id
7144 * @fl0id: FL0 queue id or 0xffff if no attached FL0
7145 * @fl1id: FL1 queue id or 0xffff if no attached FL1
7146 *
7147 * Stops an ingress queue and its associated FLs, if any. This causes
7148 * any current or future data/messages destined for these queues to be
7149 * tossed.
7150 */
7151 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
7152 unsigned int vf, unsigned int iqtype, unsigned int iqid,
7153 unsigned int fl0id, unsigned int fl1id)
7154 {
7155 struct fw_iq_cmd c;
7156
7157 memset(&c, 0, sizeof(c));
7158 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7159 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7160 FW_IQ_CMD_VFN_V(vf));
7161 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
7162 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7163 c.iqid = cpu_to_be16(iqid);
7164 c.fl0id = cpu_to_be16(fl0id);
7165 c.fl1id = cpu_to_be16(fl1id);
7166 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7167 }
7168
7169 /**
7170 * t4_iq_free - free an ingress queue and its FLs
7171 * @adap: the adapter
7172 * @mbox: mailbox to use for the FW command
7173 * @pf: the PF owning the queues
7174 * @vf: the VF owning the queues
7175 * @iqtype: the ingress queue type
7176 * @iqid: ingress queue id
7177 * @fl0id: FL0 queue id or 0xffff if no attached FL0
7178 * @fl1id: FL1 queue id or 0xffff if no attached FL1
7179 *
7180 * Frees an ingress queue and its associated FLs, if any.
7181 */
7182 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7183 unsigned int vf, unsigned int iqtype, unsigned int iqid,
7184 unsigned int fl0id, unsigned int fl1id)
7185 {
7186 struct fw_iq_cmd c;
7187
7188 memset(&c, 0, sizeof(c));
7189 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7190 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7191 FW_IQ_CMD_VFN_V(vf));
7192 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
7193 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7194 c.iqid = cpu_to_be16(iqid);
7195 c.fl0id = cpu_to_be16(fl0id);
7196 c.fl1id = cpu_to_be16(fl1id);
7197 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7198 }
7199
7200 /**
7201 * t4_eth_eq_free - free an Ethernet egress queue
7202 * @adap: the adapter
7203 * @mbox: mailbox to use for the FW command
7204 * @pf: the PF owning the queue
7205 * @vf: the VF owning the queue
7206 * @eqid: egress queue id
7207 *
7208 * Frees an Ethernet egress queue.
7209 */
7210 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7211 unsigned int vf, unsigned int eqid)
7212 {
7213 struct fw_eq_eth_cmd c;
7214
7215 memset(&c, 0, sizeof(c));
7216 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
7217 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7218 FW_EQ_ETH_CMD_PFN_V(pf) |
7219 FW_EQ_ETH_CMD_VFN_V(vf));
7220 c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
7221 c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
7222 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7223 }
7224
7225 /**
7226 * t4_ctrl_eq_free - free a control egress queue
7227 * @adap: the adapter
7228 * @mbox: mailbox to use for the FW command
7229 * @pf: the PF owning the queue
7230 * @vf: the VF owning the queue
7231 * @eqid: egress queue id
7232 *
7233 * Frees a control egress queue.
7234 */
7235 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7236 unsigned int vf, unsigned int eqid)
7237 {
7238 struct fw_eq_ctrl_cmd c;
7239
7240 memset(&c, 0, sizeof(c));
7241 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
7242 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7243 FW_EQ_CTRL_CMD_PFN_V(pf) |
7244 FW_EQ_CTRL_CMD_VFN_V(vf));
7245 c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
7246 c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
7247 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7248 }
7249
7250 /**
7251 * t4_ofld_eq_free - free an offload egress queue
7252 * @adap: the adapter
7253 * @mbox: mailbox to use for the FW command
7254 * @pf: the PF owning the queue
7255 * @vf: the VF owning the queue
7256 * @eqid: egress queue id
7257 *
7258 * Frees a control egress queue.
7259 */
7260 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7261 unsigned int vf, unsigned int eqid)
7262 {
7263 struct fw_eq_ofld_cmd c;
7264
7265 memset(&c, 0, sizeof(c));
7266 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
7267 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7268 FW_EQ_OFLD_CMD_PFN_V(pf) |
7269 FW_EQ_OFLD_CMD_VFN_V(vf));
7270 c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
7271 c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
7272 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7273 }
7274
7275 /**
7276 * t4_link_down_rc_str - return a string for a Link Down Reason Code
7277 * @adap: the adapter
7278 * @link_down_rc: Link Down Reason Code
7279 *
7280 * Returns a string representation of the Link Down Reason Code.
7281 */
7282 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
7283 {
7284 static const char * const reason[] = {
7285 "Link Down",
7286 "Remote Fault",
7287 "Auto-negotiation Failure",
7288 "Reserved",
7289 "Insufficient Airflow",
7290 "Unable To Determine Reason",
7291 "No RX Signal Detected",
7292 "Reserved",
7293 };
7294
7295 if (link_down_rc >= ARRAY_SIZE(reason))
7296 return "Bad Reason Code";
7297
7298 return reason[link_down_rc];
7299 }
7300
7301 /**
7302 * t4_handle_get_port_info - process a FW reply message
7303 * @pi: the port info
7304 * @rpl: start of the FW message
7305 *
7306 * Processes a GET_PORT_INFO FW reply message.
7307 */
7308 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
7309 {
7310 const struct fw_port_cmd *p = (const void *)rpl;
7311 struct adapter *adap = pi->adapter;
7312
7313 /* link/module state change message */
7314 int speed = 0, fc = 0;
7315 struct link_config *lc;
7316 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
7317 int link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0;
7318 u32 mod = FW_PORT_CMD_MODTYPE_G(stat);
7319
7320 if (stat & FW_PORT_CMD_RXPAUSE_F)
7321 fc |= PAUSE_RX;
7322 if (stat & FW_PORT_CMD_TXPAUSE_F)
7323 fc |= PAUSE_TX;
7324 if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
7325 speed = 100;
7326 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
7327 speed = 1000;
7328 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
7329 speed = 10000;
7330 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
7331 speed = 25000;
7332 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
7333 speed = 40000;
7334 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
7335 speed = 100000;
7336
7337 lc = &pi->link_cfg;
7338
7339 if (mod != pi->mod_type) {
7340 pi->mod_type = mod;
7341 t4_os_portmod_changed(adap, pi->port_id);
7342 }
7343 if (link_ok != lc->link_ok || speed != lc->speed ||
7344 fc != lc->fc) { /* something changed */
7345 if (!link_ok && lc->link_ok) {
7346 unsigned char rc = FW_PORT_CMD_LINKDNRC_G(stat);
7347
7348 lc->link_down_rc = rc;
7349 dev_warn(adap->pdev_dev,
7350 "Port %d link down, reason: %s\n",
7351 pi->port_id, t4_link_down_rc_str(rc));
7352 }
7353 lc->link_ok = link_ok;
7354 lc->speed = speed;
7355 lc->fc = fc;
7356 lc->supported = be16_to_cpu(p->u.info.pcap);
7357 lc->lp_advertising = be16_to_cpu(p->u.info.lpacap);
7358 t4_os_link_changed(adap, pi->port_id, link_ok);
7359 }
7360 }
7361
7362 /**
7363 * t4_handle_fw_rpl - process a FW reply message
7364 * @adap: the adapter
7365 * @rpl: start of the FW message
7366 *
7367 * Processes a FW message, such as link state change messages.
7368 */
7369 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
7370 {
7371 u8 opcode = *(const u8 *)rpl;
7372
7373 /* This might be a port command ... this simplifies the following
7374 * conditionals ... We can get away with pre-dereferencing
7375 * action_to_len16 because it's in the first 16 bytes and all messages
7376 * will be at least that long.
7377 */
7378 const struct fw_port_cmd *p = (const void *)rpl;
7379 unsigned int action =
7380 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
7381
7382 if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
7383 int i;
7384 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
7385 struct port_info *pi = NULL;
7386
7387 for_each_port(adap, i) {
7388 pi = adap2pinfo(adap, i);
7389 if (pi->tx_chan == chan)
7390 break;
7391 }
7392
7393 t4_handle_get_port_info(pi, rpl);
7394 } else {
7395 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n", opcode);
7396 return -EINVAL;
7397 }
7398 return 0;
7399 }
7400
7401 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
7402 {
7403 u16 val;
7404
7405 if (pci_is_pcie(adapter->pdev)) {
7406 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
7407 p->speed = val & PCI_EXP_LNKSTA_CLS;
7408 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
7409 }
7410 }
7411
7412 /**
7413 * init_link_config - initialize a link's SW state
7414 * @lc: structure holding the link state
7415 * @caps: link capabilities
7416 *
7417 * Initializes the SW state maintained for each link, including the link's
7418 * capabilities and default speed/flow-control/autonegotiation settings.
7419 */
7420 static void init_link_config(struct link_config *lc, unsigned int pcaps,
7421 unsigned int acaps)
7422 {
7423 lc->supported = pcaps;
7424 lc->lp_advertising = 0;
7425 lc->requested_speed = 0;
7426 lc->speed = 0;
7427 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
7428 lc->auto_fec = 0;
7429
7430 /* For Forward Error Control, we default to whatever the Firmware
7431 * tells us the Link is currently advertising.
7432 */
7433 if (acaps & FW_PORT_CAP_FEC_RS)
7434 lc->auto_fec |= FEC_RS;
7435 if (acaps & FW_PORT_CAP_FEC_BASER_RS)
7436 lc->auto_fec |= FEC_BASER_RS;
7437 lc->requested_fec = FEC_AUTO;
7438 lc->fec = lc->auto_fec;
7439
7440 if (lc->supported & FW_PORT_CAP_ANEG) {
7441 lc->advertising = lc->supported & ADVERT_MASK;
7442 lc->autoneg = AUTONEG_ENABLE;
7443 lc->requested_fc |= PAUSE_AUTONEG;
7444 } else {
7445 lc->advertising = 0;
7446 lc->autoneg = AUTONEG_DISABLE;
7447 }
7448 }
7449
7450 #define CIM_PF_NOACCESS 0xeeeeeeee
7451
7452 int t4_wait_dev_ready(void __iomem *regs)
7453 {
7454 u32 whoami;
7455
7456 whoami = readl(regs + PL_WHOAMI_A);
7457 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
7458 return 0;
7459
7460 msleep(500);
7461 whoami = readl(regs + PL_WHOAMI_A);
7462 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
7463 }
7464
7465 struct flash_desc {
7466 u32 vendor_and_model_id;
7467 u32 size_mb;
7468 };
7469
7470 static int get_flash_params(struct adapter *adap)
7471 {
7472 /* Table for non-Numonix supported flash parts. Numonix parts are left
7473 * to the preexisting code. All flash parts have 64KB sectors.
7474 */
7475 static struct flash_desc supported_flash[] = {
7476 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
7477 };
7478
7479 int ret;
7480 u32 info;
7481
7482 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
7483 if (!ret)
7484 ret = sf1_read(adap, 3, 0, 1, &info);
7485 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
7486 if (ret)
7487 return ret;
7488
7489 for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
7490 if (supported_flash[ret].vendor_and_model_id == info) {
7491 adap->params.sf_size = supported_flash[ret].size_mb;
7492 adap->params.sf_nsec =
7493 adap->params.sf_size / SF_SEC_SIZE;
7494 return 0;
7495 }
7496
7497 if ((info & 0xff) != 0x20) /* not a Numonix flash */
7498 return -EINVAL;
7499 info >>= 16; /* log2 of size */
7500 if (info >= 0x14 && info < 0x18)
7501 adap->params.sf_nsec = 1 << (info - 16);
7502 else if (info == 0x18)
7503 adap->params.sf_nsec = 64;
7504 else
7505 return -EINVAL;
7506 adap->params.sf_size = 1 << info;
7507 adap->params.sf_fw_start =
7508 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M;
7509
7510 if (adap->params.sf_size < FLASH_MIN_SIZE)
7511 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n",
7512 adap->params.sf_size, FLASH_MIN_SIZE);
7513 return 0;
7514 }
7515
7516 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
7517 {
7518 u16 val;
7519 u32 pcie_cap;
7520
7521 pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
7522 if (pcie_cap) {
7523 pci_read_config_word(adapter->pdev,
7524 pcie_cap + PCI_EXP_DEVCTL2, &val);
7525 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
7526 val |= range;
7527 pci_write_config_word(adapter->pdev,
7528 pcie_cap + PCI_EXP_DEVCTL2, val);
7529 }
7530 }
7531
7532 /**
7533 * t4_prep_adapter - prepare SW and HW for operation
7534 * @adapter: the adapter
7535 * @reset: if true perform a HW reset
7536 *
7537 * Initialize adapter SW state for the various HW modules, set initial
7538 * values for some adapter tunables, take PHYs out of reset, and
7539 * initialize the MDIO interface.
7540 */
7541 int t4_prep_adapter(struct adapter *adapter)
7542 {
7543 int ret, ver;
7544 uint16_t device_id;
7545 u32 pl_rev;
7546
7547 get_pci_mode(adapter, &adapter->params.pci);
7548 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
7549
7550 ret = get_flash_params(adapter);
7551 if (ret < 0) {
7552 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
7553 return ret;
7554 }
7555
7556 /* Retrieve adapter's device ID
7557 */
7558 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
7559 ver = device_id >> 12;
7560 adapter->params.chip = 0;
7561 switch (ver) {
7562 case CHELSIO_T4:
7563 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
7564 adapter->params.arch.sge_fl_db = DBPRIO_F;
7565 adapter->params.arch.mps_tcam_size =
7566 NUM_MPS_CLS_SRAM_L_INSTANCES;
7567 adapter->params.arch.mps_rplc_size = 128;
7568 adapter->params.arch.nchan = NCHAN;
7569 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7570 adapter->params.arch.vfcount = 128;
7571 /* Congestion map is for 4 channels so that
7572 * MPS can have 4 priority per port.
7573 */
7574 adapter->params.arch.cng_ch_bits_log = 2;
7575 break;
7576 case CHELSIO_T5:
7577 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
7578 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
7579 adapter->params.arch.mps_tcam_size =
7580 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7581 adapter->params.arch.mps_rplc_size = 128;
7582 adapter->params.arch.nchan = NCHAN;
7583 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7584 adapter->params.arch.vfcount = 128;
7585 adapter->params.arch.cng_ch_bits_log = 2;
7586 break;
7587 case CHELSIO_T6:
7588 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
7589 adapter->params.arch.sge_fl_db = 0;
7590 adapter->params.arch.mps_tcam_size =
7591 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7592 adapter->params.arch.mps_rplc_size = 256;
7593 adapter->params.arch.nchan = 2;
7594 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
7595 adapter->params.arch.vfcount = 256;
7596 /* Congestion map will be for 2 channels so that
7597 * MPS can have 8 priority per port.
7598 */
7599 adapter->params.arch.cng_ch_bits_log = 3;
7600 break;
7601 default:
7602 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
7603 device_id);
7604 return -EINVAL;
7605 }
7606
7607 adapter->params.cim_la_size = CIMLA_SIZE;
7608 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
7609
7610 /*
7611 * Default port for debugging in case we can't reach FW.
7612 */
7613 adapter->params.nports = 1;
7614 adapter->params.portvec = 1;
7615 adapter->params.vpd.cclk = 50000;
7616
7617 /* Set pci completion timeout value to 4 seconds. */
7618 set_pcie_completion_timeout(adapter, 0xd);
7619 return 0;
7620 }
7621
7622 /**
7623 * t4_shutdown_adapter - shut down adapter, host & wire
7624 * @adapter: the adapter
7625 *
7626 * Perform an emergency shutdown of the adapter and stop it from
7627 * continuing any further communication on the ports or DMA to the
7628 * host. This is typically used when the adapter and/or firmware
7629 * have crashed and we want to prevent any further accidental
7630 * communication with the rest of the world. This will also force
7631 * the port Link Status to go down -- if register writes work --
7632 * which should help our peers figure out that we're down.
7633 */
7634 int t4_shutdown_adapter(struct adapter *adapter)
7635 {
7636 int port;
7637
7638 t4_intr_disable(adapter);
7639 t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
7640 for_each_port(adapter, port) {
7641 u32 a_port_cfg = PORT_REG(port,
7642 is_t4(adapter->params.chip)
7643 ? XGMAC_PORT_CFG_A
7644 : MAC_PORT_CFG_A);
7645
7646 t4_write_reg(adapter, a_port_cfg,
7647 t4_read_reg(adapter, a_port_cfg)
7648 & ~SIGNAL_DET_V(1));
7649 }
7650 t4_set_reg_field(adapter, SGE_CONTROL_A, GLOBALENABLE_F, 0);
7651
7652 return 0;
7653 }
7654
7655 /**
7656 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
7657 * @adapter: the adapter
7658 * @qid: the Queue ID
7659 * @qtype: the Ingress or Egress type for @qid
7660 * @user: true if this request is for a user mode queue
7661 * @pbar2_qoffset: BAR2 Queue Offset
7662 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
7663 *
7664 * Returns the BAR2 SGE Queue Registers information associated with the
7665 * indicated Absolute Queue ID. These are passed back in return value
7666 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
7667 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
7668 *
7669 * This may return an error which indicates that BAR2 SGE Queue
7670 * registers aren't available. If an error is not returned, then the
7671 * following values are returned:
7672 *
7673 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
7674 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
7675 *
7676 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
7677 * require the "Inferred Queue ID" ability may be used. E.g. the
7678 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
7679 * then these "Inferred Queue ID" register may not be used.
7680 */
7681 int t4_bar2_sge_qregs(struct adapter *adapter,
7682 unsigned int qid,
7683 enum t4_bar2_qtype qtype,
7684 int user,
7685 u64 *pbar2_qoffset,
7686 unsigned int *pbar2_qid)
7687 {
7688 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
7689 u64 bar2_page_offset, bar2_qoffset;
7690 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
7691
7692 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
7693 if (!user && is_t4(adapter->params.chip))
7694 return -EINVAL;
7695
7696 /* Get our SGE Page Size parameters.
7697 */
7698 page_shift = adapter->params.sge.hps + 10;
7699 page_size = 1 << page_shift;
7700
7701 /* Get the right Queues per Page parameters for our Queue.
7702 */
7703 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
7704 ? adapter->params.sge.eq_qpp
7705 : adapter->params.sge.iq_qpp);
7706 qpp_mask = (1 << qpp_shift) - 1;
7707
7708 /* Calculate the basics of the BAR2 SGE Queue register area:
7709 * o The BAR2 page the Queue registers will be in.
7710 * o The BAR2 Queue ID.
7711 * o The BAR2 Queue ID Offset into the BAR2 page.
7712 */
7713 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
7714 bar2_qid = qid & qpp_mask;
7715 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
7716
7717 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
7718 * hardware will infer the Absolute Queue ID simply from the writes to
7719 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
7720 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
7721 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
7722 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
7723 * from the BAR2 Page and BAR2 Queue ID.
7724 *
7725 * One important censequence of this is that some BAR2 SGE registers
7726 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
7727 * there. But other registers synthesize the SGE Queue ID purely
7728 * from the writes to the registers -- the Write Combined Doorbell
7729 * Buffer is a good example. These BAR2 SGE Registers are only
7730 * available for those BAR2 SGE Register areas where the SGE Absolute
7731 * Queue ID can be inferred from simple writes.
7732 */
7733 bar2_qoffset = bar2_page_offset;
7734 bar2_qinferred = (bar2_qid_offset < page_size);
7735 if (bar2_qinferred) {
7736 bar2_qoffset += bar2_qid_offset;
7737 bar2_qid = 0;
7738 }
7739
7740 *pbar2_qoffset = bar2_qoffset;
7741 *pbar2_qid = bar2_qid;
7742 return 0;
7743 }
7744
7745 /**
7746 * t4_init_devlog_params - initialize adapter->params.devlog
7747 * @adap: the adapter
7748 *
7749 * Initialize various fields of the adapter's Firmware Device Log
7750 * Parameters structure.
7751 */
7752 int t4_init_devlog_params(struct adapter *adap)
7753 {
7754 struct devlog_params *dparams = &adap->params.devlog;
7755 u32 pf_dparams;
7756 unsigned int devlog_meminfo;
7757 struct fw_devlog_cmd devlog_cmd;
7758 int ret;
7759
7760 /* If we're dealing with newer firmware, the Device Log Paramerters
7761 * are stored in a designated register which allows us to access the
7762 * Device Log even if we can't talk to the firmware.
7763 */
7764 pf_dparams =
7765 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
7766 if (pf_dparams) {
7767 unsigned int nentries, nentries128;
7768
7769 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
7770 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
7771
7772 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
7773 nentries = (nentries128 + 1) * 128;
7774 dparams->size = nentries * sizeof(struct fw_devlog_e);
7775
7776 return 0;
7777 }
7778
7779 /* Otherwise, ask the firmware for it's Device Log Parameters.
7780 */
7781 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
7782 devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
7783 FW_CMD_REQUEST_F | FW_CMD_READ_F);
7784 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
7785 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
7786 &devlog_cmd);
7787 if (ret)
7788 return ret;
7789
7790 devlog_meminfo =
7791 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
7792 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
7793 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
7794 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
7795
7796 return 0;
7797 }
7798
7799 /**
7800 * t4_init_sge_params - initialize adap->params.sge
7801 * @adapter: the adapter
7802 *
7803 * Initialize various fields of the adapter's SGE Parameters structure.
7804 */
7805 int t4_init_sge_params(struct adapter *adapter)
7806 {
7807 struct sge_params *sge_params = &adapter->params.sge;
7808 u32 hps, qpp;
7809 unsigned int s_hps, s_qpp;
7810
7811 /* Extract the SGE Page Size for our PF.
7812 */
7813 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
7814 s_hps = (HOSTPAGESIZEPF0_S +
7815 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
7816 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
7817
7818 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
7819 */
7820 s_qpp = (QUEUESPERPAGEPF0_S +
7821 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
7822 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
7823 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7824 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
7825 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7826
7827 return 0;
7828 }
7829
7830 /**
7831 * t4_init_tp_params - initialize adap->params.tp
7832 * @adap: the adapter
7833 *
7834 * Initialize various fields of the adapter's TP Parameters structure.
7835 */
7836 int t4_init_tp_params(struct adapter *adap)
7837 {
7838 int chan;
7839 u32 v;
7840
7841 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
7842 adap->params.tp.tre = TIMERRESOLUTION_G(v);
7843 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
7844
7845 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
7846 for (chan = 0; chan < NCHAN; chan++)
7847 adap->params.tp.tx_modq[chan] = chan;
7848
7849 /* Cache the adapter's Compressed Filter Mode and global Incress
7850 * Configuration.
7851 */
7852 if (t4_use_ldst(adap)) {
7853 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1,
7854 TP_VLAN_PRI_MAP_A, 1);
7855 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1,
7856 TP_INGRESS_CONFIG_A, 1);
7857 } else {
7858 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7859 &adap->params.tp.vlan_pri_map, 1,
7860 TP_VLAN_PRI_MAP_A);
7861 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7862 &adap->params.tp.ingress_config, 1,
7863 TP_INGRESS_CONFIG_A);
7864 }
7865 /* For T6, cache the adapter's compressed error vector
7866 * and passing outer header info for encapsulated packets.
7867 */
7868 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
7869 v = t4_read_reg(adap, TP_OUT_CONFIG_A);
7870 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
7871 }
7872
7873 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
7874 * shift positions of several elements of the Compressed Filter Tuple
7875 * for this adapter which we need frequently ...
7876 */
7877 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
7878 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
7879 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
7880 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
7881 PROTOCOL_F);
7882
7883 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
7884 * represents the presence of an Outer VLAN instead of a VNIC ID.
7885 */
7886 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
7887 adap->params.tp.vnic_shift = -1;
7888
7889 return 0;
7890 }
7891
7892 /**
7893 * t4_filter_field_shift - calculate filter field shift
7894 * @adap: the adapter
7895 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
7896 *
7897 * Return the shift position of a filter field within the Compressed
7898 * Filter Tuple. The filter field is specified via its selection bit
7899 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
7900 */
7901 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
7902 {
7903 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
7904 unsigned int sel;
7905 int field_shift;
7906
7907 if ((filter_mode & filter_sel) == 0)
7908 return -1;
7909
7910 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
7911 switch (filter_mode & sel) {
7912 case FCOE_F:
7913 field_shift += FT_FCOE_W;
7914 break;
7915 case PORT_F:
7916 field_shift += FT_PORT_W;
7917 break;
7918 case VNIC_ID_F:
7919 field_shift += FT_VNIC_ID_W;
7920 break;
7921 case VLAN_F:
7922 field_shift += FT_VLAN_W;
7923 break;
7924 case TOS_F:
7925 field_shift += FT_TOS_W;
7926 break;
7927 case PROTOCOL_F:
7928 field_shift += FT_PROTOCOL_W;
7929 break;
7930 case ETHERTYPE_F:
7931 field_shift += FT_ETHERTYPE_W;
7932 break;
7933 case MACMATCH_F:
7934 field_shift += FT_MACMATCH_W;
7935 break;
7936 case MPSHITTYPE_F:
7937 field_shift += FT_MPSHITTYPE_W;
7938 break;
7939 case FRAGMENTATION_F:
7940 field_shift += FT_FRAGMENTATION_W;
7941 break;
7942 }
7943 }
7944 return field_shift;
7945 }
7946
7947 int t4_init_rss_mode(struct adapter *adap, int mbox)
7948 {
7949 int i, ret;
7950 struct fw_rss_vi_config_cmd rvc;
7951
7952 memset(&rvc, 0, sizeof(rvc));
7953
7954 for_each_port(adap, i) {
7955 struct port_info *p = adap2pinfo(adap, i);
7956
7957 rvc.op_to_viid =
7958 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
7959 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7960 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
7961 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
7962 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
7963 if (ret)
7964 return ret;
7965 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
7966 }
7967 return 0;
7968 }
7969
7970 /**
7971 * t4_init_portinfo - allocate a virtual interface amd initialize port_info
7972 * @pi: the port_info
7973 * @mbox: mailbox to use for the FW command
7974 * @port: physical port associated with the VI
7975 * @pf: the PF owning the VI
7976 * @vf: the VF owning the VI
7977 * @mac: the MAC address of the VI
7978 *
7979 * Allocates a virtual interface for the given physical port. If @mac is
7980 * not %NULL it contains the MAC address of the VI as assigned by FW.
7981 * @mac should be large enough to hold an Ethernet address.
7982 * Returns < 0 on error.
7983 */
7984 int t4_init_portinfo(struct port_info *pi, int mbox,
7985 int port, int pf, int vf, u8 mac[])
7986 {
7987 int ret;
7988 struct fw_port_cmd c;
7989 unsigned int rss_size;
7990
7991 memset(&c, 0, sizeof(c));
7992 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
7993 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7994 FW_PORT_CMD_PORTID_V(port));
7995 c.action_to_len16 = cpu_to_be32(
7996 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
7997 FW_LEN16(c));
7998 ret = t4_wr_mbox(pi->adapter, mbox, &c, sizeof(c), &c);
7999 if (ret)
8000 return ret;
8001
8002 ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size);
8003 if (ret < 0)
8004 return ret;
8005
8006 pi->viid = ret;
8007 pi->tx_chan = port;
8008 pi->lport = port;
8009 pi->rss_size = rss_size;
8010
8011 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
8012 pi->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP_F) ?
8013 FW_PORT_CMD_MDIOADDR_G(ret) : -1;
8014 pi->port_type = FW_PORT_CMD_PTYPE_G(ret);
8015 pi->mod_type = FW_PORT_MOD_TYPE_NA;
8016
8017 init_link_config(&pi->link_cfg, be16_to_cpu(c.u.info.pcap),
8018 be16_to_cpu(c.u.info.acap));
8019 return 0;
8020 }
8021
8022 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
8023 {
8024 u8 addr[6];
8025 int ret, i, j = 0;
8026
8027 for_each_port(adap, i) {
8028 struct port_info *pi = adap2pinfo(adap, i);
8029
8030 while ((adap->params.portvec & (1 << j)) == 0)
8031 j++;
8032
8033 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
8034 if (ret)
8035 return ret;
8036
8037 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
8038 j++;
8039 }
8040 return 0;
8041 }
8042
8043 /**
8044 * t4_read_cimq_cfg - read CIM queue configuration
8045 * @adap: the adapter
8046 * @base: holds the queue base addresses in bytes
8047 * @size: holds the queue sizes in bytes
8048 * @thres: holds the queue full thresholds in bytes
8049 *
8050 * Returns the current configuration of the CIM queues, starting with
8051 * the IBQs, then the OBQs.
8052 */
8053 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
8054 {
8055 unsigned int i, v;
8056 int cim_num_obq = is_t4(adap->params.chip) ?
8057 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
8058
8059 for (i = 0; i < CIM_NUM_IBQ; i++) {
8060 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
8061 QUENUMSELECT_V(i));
8062 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
8063 /* value is in 256-byte units */
8064 *base++ = CIMQBASE_G(v) * 256;
8065 *size++ = CIMQSIZE_G(v) * 256;
8066 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
8067 }
8068 for (i = 0; i < cim_num_obq; i++) {
8069 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
8070 QUENUMSELECT_V(i));
8071 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
8072 /* value is in 256-byte units */
8073 *base++ = CIMQBASE_G(v) * 256;
8074 *size++ = CIMQSIZE_G(v) * 256;
8075 }
8076 }
8077
8078 /**
8079 * t4_read_cim_ibq - read the contents of a CIM inbound queue
8080 * @adap: the adapter
8081 * @qid: the queue index
8082 * @data: where to store the queue contents
8083 * @n: capacity of @data in 32-bit words
8084 *
8085 * Reads the contents of the selected CIM queue starting at address 0 up
8086 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
8087 * error and the number of 32-bit words actually read on success.
8088 */
8089 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
8090 {
8091 int i, err, attempts;
8092 unsigned int addr;
8093 const unsigned int nwords = CIM_IBQ_SIZE * 4;
8094
8095 if (qid > 5 || (n & 3))
8096 return -EINVAL;
8097
8098 addr = qid * nwords;
8099 if (n > nwords)
8100 n = nwords;
8101
8102 /* It might take 3-10ms before the IBQ debug read access is allowed.
8103 * Wait for 1 Sec with a delay of 1 usec.
8104 */
8105 attempts = 1000000;
8106
8107 for (i = 0; i < n; i++, addr++) {
8108 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
8109 IBQDBGEN_F);
8110 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
8111 attempts, 1);
8112 if (err)
8113 return err;
8114 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
8115 }
8116 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
8117 return i;
8118 }
8119
8120 /**
8121 * t4_read_cim_obq - read the contents of a CIM outbound queue
8122 * @adap: the adapter
8123 * @qid: the queue index
8124 * @data: where to store the queue contents
8125 * @n: capacity of @data in 32-bit words
8126 *
8127 * Reads the contents of the selected CIM queue starting at address 0 up
8128 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
8129 * error and the number of 32-bit words actually read on success.
8130 */
8131 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
8132 {
8133 int i, err;
8134 unsigned int addr, v, nwords;
8135 int cim_num_obq = is_t4(adap->params.chip) ?
8136 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
8137
8138 if ((qid > (cim_num_obq - 1)) || (n & 3))
8139 return -EINVAL;
8140
8141 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
8142 QUENUMSELECT_V(qid));
8143 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
8144
8145 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
8146 nwords = CIMQSIZE_G(v) * 64; /* same */
8147 if (n > nwords)
8148 n = nwords;
8149
8150 for (i = 0; i < n; i++, addr++) {
8151 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
8152 OBQDBGEN_F);
8153 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
8154 2, 1);
8155 if (err)
8156 return err;
8157 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
8158 }
8159 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
8160 return i;
8161 }
8162
8163 /**
8164 * t4_cim_read - read a block from CIM internal address space
8165 * @adap: the adapter
8166 * @addr: the start address within the CIM address space
8167 * @n: number of words to read
8168 * @valp: where to store the result
8169 *
8170 * Reads a block of 4-byte words from the CIM intenal address space.
8171 */
8172 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
8173 unsigned int *valp)
8174 {
8175 int ret = 0;
8176
8177 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
8178 return -EBUSY;
8179
8180 for ( ; !ret && n--; addr += 4) {
8181 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
8182 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
8183 0, 5, 2);
8184 if (!ret)
8185 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
8186 }
8187 return ret;
8188 }
8189
8190 /**
8191 * t4_cim_write - write a block into CIM internal address space
8192 * @adap: the adapter
8193 * @addr: the start address within the CIM address space
8194 * @n: number of words to write
8195 * @valp: set of values to write
8196 *
8197 * Writes a block of 4-byte words into the CIM intenal address space.
8198 */
8199 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
8200 const unsigned int *valp)
8201 {
8202 int ret = 0;
8203
8204 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
8205 return -EBUSY;
8206
8207 for ( ; !ret && n--; addr += 4) {
8208 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
8209 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
8210 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
8211 0, 5, 2);
8212 }
8213 return ret;
8214 }
8215
8216 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
8217 unsigned int val)
8218 {
8219 return t4_cim_write(adap, addr, 1, &val);
8220 }
8221
8222 /**
8223 * t4_cim_read_la - read CIM LA capture buffer
8224 * @adap: the adapter
8225 * @la_buf: where to store the LA data
8226 * @wrptr: the HW write pointer within the capture buffer
8227 *
8228 * Reads the contents of the CIM LA buffer with the most recent entry at
8229 * the end of the returned data and with the entry at @wrptr first.
8230 * We try to leave the LA in the running state we find it in.
8231 */
8232 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
8233 {
8234 int i, ret;
8235 unsigned int cfg, val, idx;
8236
8237 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
8238 if (ret)
8239 return ret;
8240
8241 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
8242 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
8243 if (ret)
8244 return ret;
8245 }
8246
8247 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
8248 if (ret)
8249 goto restart;
8250
8251 idx = UPDBGLAWRPTR_G(val);
8252 if (wrptr)
8253 *wrptr = idx;
8254
8255 for (i = 0; i < adap->params.cim_la_size; i++) {
8256 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
8257 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
8258 if (ret)
8259 break;
8260 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
8261 if (ret)
8262 break;
8263 if (val & UPDBGLARDEN_F) {
8264 ret = -ETIMEDOUT;
8265 break;
8266 }
8267 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
8268 if (ret)
8269 break;
8270 idx = (idx + 1) & UPDBGLARDPTR_M;
8271 }
8272 restart:
8273 if (cfg & UPDBGLAEN_F) {
8274 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
8275 cfg & ~UPDBGLARDEN_F);
8276 if (!ret)
8277 ret = r;
8278 }
8279 return ret;
8280 }
8281
8282 /**
8283 * t4_tp_read_la - read TP LA capture buffer
8284 * @adap: the adapter
8285 * @la_buf: where to store the LA data
8286 * @wrptr: the HW write pointer within the capture buffer
8287 *
8288 * Reads the contents of the TP LA buffer with the most recent entry at
8289 * the end of the returned data and with the entry at @wrptr first.
8290 * We leave the LA in the running state we find it in.
8291 */
8292 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
8293 {
8294 bool last_incomplete;
8295 unsigned int i, cfg, val, idx;
8296
8297 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
8298 if (cfg & DBGLAENABLE_F) /* freeze LA */
8299 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8300 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
8301
8302 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
8303 idx = DBGLAWPTR_G(val);
8304 last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
8305 if (last_incomplete)
8306 idx = (idx + 1) & DBGLARPTR_M;
8307 if (wrptr)
8308 *wrptr = idx;
8309
8310 val &= 0xffff;
8311 val &= ~DBGLARPTR_V(DBGLARPTR_M);
8312 val |= adap->params.tp.la_mask;
8313
8314 for (i = 0; i < TPLA_SIZE; i++) {
8315 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
8316 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
8317 idx = (idx + 1) & DBGLARPTR_M;
8318 }
8319
8320 /* Wipe out last entry if it isn't valid */
8321 if (last_incomplete)
8322 la_buf[TPLA_SIZE - 1] = ~0ULL;
8323
8324 if (cfg & DBGLAENABLE_F) /* restore running state */
8325 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8326 cfg | adap->params.tp.la_mask);
8327 }
8328
8329 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
8330 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
8331 * state for more than the Warning Threshold then we'll issue a warning about
8332 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
8333 * appears to be hung every Warning Repeat second till the situation clears.
8334 * If the situation clears, we'll note that as well.
8335 */
8336 #define SGE_IDMA_WARN_THRESH 1
8337 #define SGE_IDMA_WARN_REPEAT 300
8338
8339 /**
8340 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
8341 * @adapter: the adapter
8342 * @idma: the adapter IDMA Monitor state
8343 *
8344 * Initialize the state of an SGE Ingress DMA Monitor.
8345 */
8346 void t4_idma_monitor_init(struct adapter *adapter,
8347 struct sge_idma_monitor_state *idma)
8348 {
8349 /* Initialize the state variables for detecting an SGE Ingress DMA
8350 * hang. The SGE has internal counters which count up on each clock
8351 * tick whenever the SGE finds its Ingress DMA State Engines in the
8352 * same state they were on the previous clock tick. The clock used is
8353 * the Core Clock so we have a limit on the maximum "time" they can
8354 * record; typically a very small number of seconds. For instance,
8355 * with a 600MHz Core Clock, we can only count up to a bit more than
8356 * 7s. So we'll synthesize a larger counter in order to not run the
8357 * risk of having the "timers" overflow and give us the flexibility to
8358 * maintain a Hung SGE State Machine of our own which operates across
8359 * a longer time frame.
8360 */
8361 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
8362 idma->idma_stalled[0] = 0;
8363 idma->idma_stalled[1] = 0;
8364 }
8365
8366 /**
8367 * t4_idma_monitor - monitor SGE Ingress DMA state
8368 * @adapter: the adapter
8369 * @idma: the adapter IDMA Monitor state
8370 * @hz: number of ticks/second
8371 * @ticks: number of ticks since the last IDMA Monitor call
8372 */
8373 void t4_idma_monitor(struct adapter *adapter,
8374 struct sge_idma_monitor_state *idma,
8375 int hz, int ticks)
8376 {
8377 int i, idma_same_state_cnt[2];
8378
8379 /* Read the SGE Debug Ingress DMA Same State Count registers. These
8380 * are counters inside the SGE which count up on each clock when the
8381 * SGE finds its Ingress DMA State Engines in the same states they
8382 * were in the previous clock. The counters will peg out at
8383 * 0xffffffff without wrapping around so once they pass the 1s
8384 * threshold they'll stay above that till the IDMA state changes.
8385 */
8386 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
8387 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
8388 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8389
8390 for (i = 0; i < 2; i++) {
8391 u32 debug0, debug11;
8392
8393 /* If the Ingress DMA Same State Counter ("timer") is less
8394 * than 1s, then we can reset our synthesized Stall Timer and
8395 * continue. If we have previously emitted warnings about a
8396 * potential stalled Ingress Queue, issue a note indicating
8397 * that the Ingress Queue has resumed forward progress.
8398 */
8399 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
8400 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
8401 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
8402 "resumed after %d seconds\n",
8403 i, idma->idma_qid[i],
8404 idma->idma_stalled[i] / hz);
8405 idma->idma_stalled[i] = 0;
8406 continue;
8407 }
8408
8409 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
8410 * domain. The first time we get here it'll be because we
8411 * passed the 1s Threshold; each additional time it'll be
8412 * because the RX Timer Callback is being fired on its regular
8413 * schedule.
8414 *
8415 * If the stall is below our Potential Hung Ingress Queue
8416 * Warning Threshold, continue.
8417 */
8418 if (idma->idma_stalled[i] == 0) {
8419 idma->idma_stalled[i] = hz;
8420 idma->idma_warn[i] = 0;
8421 } else {
8422 idma->idma_stalled[i] += ticks;
8423 idma->idma_warn[i] -= ticks;
8424 }
8425
8426 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
8427 continue;
8428
8429 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
8430 */
8431 if (idma->idma_warn[i] > 0)
8432 continue;
8433 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
8434
8435 /* Read and save the SGE IDMA State and Queue ID information.
8436 * We do this every time in case it changes across time ...
8437 * can't be too careful ...
8438 */
8439 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
8440 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8441 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
8442
8443 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
8444 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8445 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
8446
8447 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
8448 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
8449 i, idma->idma_qid[i], idma->idma_state[i],
8450 idma->idma_stalled[i] / hz,
8451 debug0, debug11);
8452 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
8453 }
8454 }
8455
8456 /**
8457 * t4_set_vf_mac - Set MAC address for the specified VF
8458 * @adapter: The adapter
8459 * @vf: one of the VFs instantiated by the specified PF
8460 * @naddr: the number of MAC addresses
8461 * @addr: the MAC address(es) to be set to the specified VF
8462 */
8463 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
8464 unsigned int naddr, u8 *addr)
8465 {
8466 struct fw_acl_mac_cmd cmd;
8467
8468 memset(&cmd, 0, sizeof(cmd));
8469 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
8470 FW_CMD_REQUEST_F |
8471 FW_CMD_WRITE_F |
8472 FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
8473 FW_ACL_MAC_CMD_VFN_V(vf));
8474
8475 /* Note: Do not enable the ACL */
8476 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
8477 cmd.nmac = naddr;
8478
8479 switch (adapter->pf) {
8480 case 3:
8481 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
8482 break;
8483 case 2:
8484 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
8485 break;
8486 case 1:
8487 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
8488 break;
8489 case 0:
8490 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
8491 break;
8492 }
8493
8494 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
8495 }
8496
8497 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
8498 int rateunit, int ratemode, int channel, int class,
8499 int minrate, int maxrate, int weight, int pktsize)
8500 {
8501 struct fw_sched_cmd cmd;
8502
8503 memset(&cmd, 0, sizeof(cmd));
8504 cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
8505 FW_CMD_REQUEST_F |
8506 FW_CMD_WRITE_F);
8507 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
8508
8509 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
8510 cmd.u.params.type = type;
8511 cmd.u.params.level = level;
8512 cmd.u.params.mode = mode;
8513 cmd.u.params.ch = channel;
8514 cmd.u.params.cl = class;
8515 cmd.u.params.unit = rateunit;
8516 cmd.u.params.rate = ratemode;
8517 cmd.u.params.min = cpu_to_be32(minrate);
8518 cmd.u.params.max = cpu_to_be32(maxrate);
8519 cmd.u.params.weight = cpu_to_be16(weight);
8520 cmd.u.params.pktsize = cpu_to_be16(pktsize);
8521
8522 return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),
8523 NULL, 1);
8524 }
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