2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
38 #include "t4_values.h"
42 * t4_wait_op_done_val - wait until an operation is completed
43 * @adapter: the adapter performing the operation
44 * @reg: the register to check for completion
45 * @mask: a single-bit field within @reg that indicates completion
46 * @polarity: the value of the field when the operation is completed
47 * @attempts: number of check iterations
48 * @delay: delay in usecs between iterations
49 * @valp: where to store the value of the register at completion time
51 * Wait until an operation is completed by checking a bit in a register
52 * up to @attempts times. If @valp is not NULL the value of the register
53 * at the time it indicated completion is stored there. Returns 0 if the
54 * operation completes and -EAGAIN otherwise.
56 static int t4_wait_op_done_val(struct adapter
*adapter
, int reg
, u32 mask
,
57 int polarity
, int attempts
, int delay
, u32
*valp
)
60 u32 val
= t4_read_reg(adapter
, reg
);
62 if (!!(val
& mask
) == polarity
) {
74 static inline int t4_wait_op_done(struct adapter
*adapter
, int reg
, u32 mask
,
75 int polarity
, int attempts
, int delay
)
77 return t4_wait_op_done_val(adapter
, reg
, mask
, polarity
, attempts
,
82 * t4_set_reg_field - set a register field to a value
83 * @adapter: the adapter to program
84 * @addr: the register address
85 * @mask: specifies the portion of the register to modify
86 * @val: the new value for the register field
88 * Sets a register field specified by the supplied mask to the
91 void t4_set_reg_field(struct adapter
*adapter
, unsigned int addr
, u32 mask
,
94 u32 v
= t4_read_reg(adapter
, addr
) & ~mask
;
96 t4_write_reg(adapter
, addr
, v
| val
);
97 (void) t4_read_reg(adapter
, addr
); /* flush */
101 * t4_read_indirect - read indirectly addressed registers
103 * @addr_reg: register holding the indirect address
104 * @data_reg: register holding the value of the indirect register
105 * @vals: where the read register values are stored
106 * @nregs: how many indirect registers to read
107 * @start_idx: index of first indirect register to read
109 * Reads registers that are accessed indirectly through an address/data
112 void t4_read_indirect(struct adapter
*adap
, unsigned int addr_reg
,
113 unsigned int data_reg
, u32
*vals
,
114 unsigned int nregs
, unsigned int start_idx
)
117 t4_write_reg(adap
, addr_reg
, start_idx
);
118 *vals
++ = t4_read_reg(adap
, data_reg
);
124 * t4_write_indirect - write indirectly addressed registers
126 * @addr_reg: register holding the indirect addresses
127 * @data_reg: register holding the value for the indirect registers
128 * @vals: values to write
129 * @nregs: how many indirect registers to write
130 * @start_idx: address of first indirect register to write
132 * Writes a sequential block of registers that are accessed indirectly
133 * through an address/data register pair.
135 void t4_write_indirect(struct adapter
*adap
, unsigned int addr_reg
,
136 unsigned int data_reg
, const u32
*vals
,
137 unsigned int nregs
, unsigned int start_idx
)
140 t4_write_reg(adap
, addr_reg
, start_idx
++);
141 t4_write_reg(adap
, data_reg
, *vals
++);
146 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
147 * mechanism. This guarantees that we get the real value even if we're
148 * operating within a Virtual Machine and the Hypervisor is trapping our
149 * Configuration Space accesses.
151 void t4_hw_pci_read_cfg4(struct adapter
*adap
, int reg
, u32
*val
)
153 u32 req
= ENABLE_F
| FUNCTION_V(adap
->fn
) | REGISTER_V(reg
);
155 if (is_t4(adap
->params
.chip
))
158 t4_write_reg(adap
, PCIE_CFG_SPACE_REQ_A
, req
);
159 *val
= t4_read_reg(adap
, PCIE_CFG_SPACE_DATA_A
);
161 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
162 * Configuration Space read. (None of the other fields matter when
163 * ENABLE is 0 so a simple register write is easier than a
164 * read-modify-write via t4_set_reg_field().)
166 t4_write_reg(adap
, PCIE_CFG_SPACE_REQ_A
, 0);
170 * t4_report_fw_error - report firmware error
173 * The adapter firmware can indicate error conditions to the host.
174 * If the firmware has indicated an error, print out the reason for
175 * the firmware error.
177 static void t4_report_fw_error(struct adapter
*adap
)
179 static const char *const reason
[] = {
180 "Crash", /* PCIE_FW_EVAL_CRASH */
181 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
182 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
183 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
184 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
185 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
186 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
187 "Reserved", /* reserved */
191 pcie_fw
= t4_read_reg(adap
, PCIE_FW_A
);
192 if (pcie_fw
& PCIE_FW_ERR_F
)
193 dev_err(adap
->pdev_dev
, "Firmware reports adapter error: %s\n",
194 reason
[PCIE_FW_EVAL_G(pcie_fw
)]);
198 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
200 static void get_mbox_rpl(struct adapter
*adap
, __be64
*rpl
, int nflit
,
203 for ( ; nflit
; nflit
--, mbox_addr
+= 8)
204 *rpl
++ = cpu_to_be64(t4_read_reg64(adap
, mbox_addr
));
208 * Handle a FW assertion reported in a mailbox.
210 static void fw_asrt(struct adapter
*adap
, u32 mbox_addr
)
212 struct fw_debug_cmd asrt
;
214 get_mbox_rpl(adap
, (__be64
*)&asrt
, sizeof(asrt
) / 8, mbox_addr
);
215 dev_alert(adap
->pdev_dev
,
216 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
217 asrt
.u
.assert.filename_0_7
, ntohl(asrt
.u
.assert.line
),
218 ntohl(asrt
.u
.assert.x
), ntohl(asrt
.u
.assert.y
));
221 static void dump_mbox(struct adapter
*adap
, int mbox
, u32 data_reg
)
223 dev_err(adap
->pdev_dev
,
224 "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox
,
225 (unsigned long long)t4_read_reg64(adap
, data_reg
),
226 (unsigned long long)t4_read_reg64(adap
, data_reg
+ 8),
227 (unsigned long long)t4_read_reg64(adap
, data_reg
+ 16),
228 (unsigned long long)t4_read_reg64(adap
, data_reg
+ 24),
229 (unsigned long long)t4_read_reg64(adap
, data_reg
+ 32),
230 (unsigned long long)t4_read_reg64(adap
, data_reg
+ 40),
231 (unsigned long long)t4_read_reg64(adap
, data_reg
+ 48),
232 (unsigned long long)t4_read_reg64(adap
, data_reg
+ 56));
236 * t4_wr_mbox_meat - send a command to FW through the given mailbox
238 * @mbox: index of the mailbox to use
239 * @cmd: the command to write
240 * @size: command length in bytes
241 * @rpl: where to optionally store the reply
242 * @sleep_ok: if true we may sleep while awaiting command completion
244 * Sends the given command to FW through the selected mailbox and waits
245 * for the FW to execute the command. If @rpl is not %NULL it is used to
246 * store the FW's reply to the command. The command and its optional
247 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
248 * to respond. @sleep_ok determines whether we may sleep while awaiting
249 * the response. If sleeping is allowed we use progressive backoff
252 * The return value is 0 on success or a negative errno on failure. A
253 * failure can happen either because we are not able to execute the
254 * command or FW executes it but signals an error. In the latter case
255 * the return value is the error code indicated by FW (negated).
257 int t4_wr_mbox_meat(struct adapter
*adap
, int mbox
, const void *cmd
, int size
,
258 void *rpl
, bool sleep_ok
)
260 static const int delay
[] = {
261 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
266 int i
, ms
, delay_idx
;
267 const __be64
*p
= cmd
;
268 u32 data_reg
= PF_REG(mbox
, CIM_PF_MAILBOX_DATA_A
);
269 u32 ctl_reg
= PF_REG(mbox
, CIM_PF_MAILBOX_CTRL_A
);
271 if ((size
& 15) || size
> MBOX_LEN
)
275 * If the device is off-line, as in EEH, commands will time out.
276 * Fail them early so we don't waste time waiting.
278 if (adap
->pdev
->error_state
!= pci_channel_io_normal
)
281 v
= MBOWNER_G(t4_read_reg(adap
, ctl_reg
));
282 for (i
= 0; v
== MBOX_OWNER_NONE
&& i
< 3; i
++)
283 v
= MBOWNER_G(t4_read_reg(adap
, ctl_reg
));
285 if (v
!= MBOX_OWNER_DRV
)
286 return v
? -EBUSY
: -ETIMEDOUT
;
288 for (i
= 0; i
< size
; i
+= 8)
289 t4_write_reg64(adap
, data_reg
+ i
, be64_to_cpu(*p
++));
291 t4_write_reg(adap
, ctl_reg
, MBMSGVALID_F
| MBOWNER_V(MBOX_OWNER_FW
));
292 t4_read_reg(adap
, ctl_reg
); /* flush write */
297 for (i
= 0; i
< FW_CMD_MAX_TIMEOUT
; i
+= ms
) {
299 ms
= delay
[delay_idx
]; /* last element may repeat */
300 if (delay_idx
< ARRAY_SIZE(delay
) - 1)
306 v
= t4_read_reg(adap
, ctl_reg
);
307 if (MBOWNER_G(v
) == MBOX_OWNER_DRV
) {
308 if (!(v
& MBMSGVALID_F
)) {
309 t4_write_reg(adap
, ctl_reg
, 0);
313 res
= t4_read_reg64(adap
, data_reg
);
314 if (FW_CMD_OP_G(res
>> 32) == FW_DEBUG_CMD
) {
315 fw_asrt(adap
, data_reg
);
316 res
= FW_CMD_RETVAL_V(EIO
);
318 get_mbox_rpl(adap
, rpl
, size
/ 8, data_reg
);
321 if (FW_CMD_RETVAL_G((int)res
))
322 dump_mbox(adap
, mbox
, data_reg
);
323 t4_write_reg(adap
, ctl_reg
, 0);
324 return -FW_CMD_RETVAL_G((int)res
);
328 dump_mbox(adap
, mbox
, data_reg
);
329 dev_err(adap
->pdev_dev
, "command %#x in mailbox %d timed out\n",
330 *(const u8
*)cmd
, mbox
);
331 t4_report_fw_error(adap
);
336 * t4_mc_read - read from MC through backdoor accesses
338 * @addr: address of first byte requested
339 * @idx: which MC to access
340 * @data: 64 bytes of data containing the requested address
341 * @ecc: where to store the corresponding 64-bit ECC word
343 * Read 64 bytes of data from MC starting at a 64-byte-aligned address
344 * that covers the requested address @addr. If @parity is not %NULL it
345 * is assigned the 64-bit ECC word for the read data.
347 int t4_mc_read(struct adapter
*adap
, int idx
, u32 addr
, __be32
*data
, u64
*ecc
)
350 u32 mc_bist_cmd
, mc_bist_cmd_addr
, mc_bist_cmd_len
;
351 u32 mc_bist_status_rdata
, mc_bist_data_pattern
;
353 if (is_t4(adap
->params
.chip
)) {
354 mc_bist_cmd
= MC_BIST_CMD_A
;
355 mc_bist_cmd_addr
= MC_BIST_CMD_ADDR_A
;
356 mc_bist_cmd_len
= MC_BIST_CMD_LEN_A
;
357 mc_bist_status_rdata
= MC_BIST_STATUS_RDATA_A
;
358 mc_bist_data_pattern
= MC_BIST_DATA_PATTERN_A
;
360 mc_bist_cmd
= MC_REG(MC_P_BIST_CMD_A
, idx
);
361 mc_bist_cmd_addr
= MC_REG(MC_P_BIST_CMD_ADDR_A
, idx
);
362 mc_bist_cmd_len
= MC_REG(MC_P_BIST_CMD_LEN_A
, idx
);
363 mc_bist_status_rdata
= MC_REG(MC_P_BIST_STATUS_RDATA_A
, idx
);
364 mc_bist_data_pattern
= MC_REG(MC_P_BIST_DATA_PATTERN_A
, idx
);
367 if (t4_read_reg(adap
, mc_bist_cmd
) & START_BIST_F
)
369 t4_write_reg(adap
, mc_bist_cmd_addr
, addr
& ~0x3fU
);
370 t4_write_reg(adap
, mc_bist_cmd_len
, 64);
371 t4_write_reg(adap
, mc_bist_data_pattern
, 0xc);
372 t4_write_reg(adap
, mc_bist_cmd
, BIST_OPCODE_V(1) | START_BIST_F
|
374 i
= t4_wait_op_done(adap
, mc_bist_cmd
, START_BIST_F
, 0, 10, 1);
378 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata, i)
380 for (i
= 15; i
>= 0; i
--)
381 *data
++ = htonl(t4_read_reg(adap
, MC_DATA(i
)));
383 *ecc
= t4_read_reg64(adap
, MC_DATA(16));
389 * t4_edc_read - read from EDC through backdoor accesses
391 * @idx: which EDC to access
392 * @addr: address of first byte requested
393 * @data: 64 bytes of data containing the requested address
394 * @ecc: where to store the corresponding 64-bit ECC word
396 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address
397 * that covers the requested address @addr. If @parity is not %NULL it
398 * is assigned the 64-bit ECC word for the read data.
400 int t4_edc_read(struct adapter
*adap
, int idx
, u32 addr
, __be32
*data
, u64
*ecc
)
403 u32 edc_bist_cmd
, edc_bist_cmd_addr
, edc_bist_cmd_len
;
404 u32 edc_bist_cmd_data_pattern
, edc_bist_status_rdata
;
406 if (is_t4(adap
->params
.chip
)) {
407 edc_bist_cmd
= EDC_REG(EDC_BIST_CMD_A
, idx
);
408 edc_bist_cmd_addr
= EDC_REG(EDC_BIST_CMD_ADDR_A
, idx
);
409 edc_bist_cmd_len
= EDC_REG(EDC_BIST_CMD_LEN_A
, idx
);
410 edc_bist_cmd_data_pattern
= EDC_REG(EDC_BIST_DATA_PATTERN_A
,
412 edc_bist_status_rdata
= EDC_REG(EDC_BIST_STATUS_RDATA_A
,
415 edc_bist_cmd
= EDC_REG_T5(EDC_H_BIST_CMD_A
, idx
);
416 edc_bist_cmd_addr
= EDC_REG_T5(EDC_H_BIST_CMD_ADDR_A
, idx
);
417 edc_bist_cmd_len
= EDC_REG_T5(EDC_H_BIST_CMD_LEN_A
, idx
);
418 edc_bist_cmd_data_pattern
=
419 EDC_REG_T5(EDC_H_BIST_DATA_PATTERN_A
, idx
);
420 edc_bist_status_rdata
=
421 EDC_REG_T5(EDC_H_BIST_STATUS_RDATA_A
, idx
);
424 if (t4_read_reg(adap
, edc_bist_cmd
) & START_BIST_F
)
426 t4_write_reg(adap
, edc_bist_cmd_addr
, addr
& ~0x3fU
);
427 t4_write_reg(adap
, edc_bist_cmd_len
, 64);
428 t4_write_reg(adap
, edc_bist_cmd_data_pattern
, 0xc);
429 t4_write_reg(adap
, edc_bist_cmd
,
430 BIST_OPCODE_V(1) | BIST_CMD_GAP_V(1) | START_BIST_F
);
431 i
= t4_wait_op_done(adap
, edc_bist_cmd
, START_BIST_F
, 0, 10, 1);
435 #define EDC_DATA(i) (EDC_BIST_STATUS_REG(edc_bist_status_rdata, i))
437 for (i
= 15; i
>= 0; i
--)
438 *data
++ = htonl(t4_read_reg(adap
, EDC_DATA(i
)));
440 *ecc
= t4_read_reg64(adap
, EDC_DATA(16));
446 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
448 * @win: PCI-E Memory Window to use
449 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
450 * @addr: address within indicated memory type
451 * @len: amount of memory to transfer
452 * @hbuf: host memory buffer
453 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
455 * Reads/writes an [almost] arbitrary memory region in the firmware: the
456 * firmware memory address and host buffer must be aligned on 32-bit
457 * boudaries; the length may be arbitrary. The memory is transferred as
458 * a raw byte sequence from/to the firmware's memory. If this memory
459 * contains data structures which contain multi-byte integers, it's the
460 * caller's responsibility to perform appropriate byte order conversions.
462 int t4_memory_rw(struct adapter
*adap
, int win
, int mtype
, u32 addr
,
463 u32 len
, void *hbuf
, int dir
)
465 u32 pos
, offset
, resid
, memoffset
;
466 u32 edc_size
, mc_size
, win_pf
, mem_reg
, mem_aperture
, mem_base
;
469 /* Argument sanity checks ...
471 if (addr
& 0x3 || (uintptr_t)hbuf
& 0x3)
475 /* It's convenient to be able to handle lengths which aren't a
476 * multiple of 32-bits because we often end up transferring files to
477 * the firmware. So we'll handle that by normalizing the length here
478 * and then handling any residual transfer at the end.
483 /* Offset into the region of memory which is being accessed
487 * MEM_MC0 = 2 -- For T5
488 * MEM_MC1 = 3 -- For T5
490 edc_size
= EDRAM0_SIZE_G(t4_read_reg(adap
, MA_EDRAM0_BAR_A
));
491 if (mtype
!= MEM_MC1
)
492 memoffset
= (mtype
* (edc_size
* 1024 * 1024));
494 mc_size
= EXT_MEM0_SIZE_G(t4_read_reg(adap
,
495 MA_EXT_MEMORY0_BAR_A
));
496 memoffset
= (MEM_MC0
* edc_size
+ mc_size
) * 1024 * 1024;
499 /* Determine the PCIE_MEM_ACCESS_OFFSET */
500 addr
= addr
+ memoffset
;
502 /* Each PCI-E Memory Window is programmed with a window size -- or
503 * "aperture" -- which controls the granularity of its mapping onto
504 * adapter memory. We need to grab that aperture in order to know
505 * how to use the specified window. The window is also programmed
506 * with the base address of the Memory Window in BAR0's address
507 * space. For T4 this is an absolute PCI-E Bus Address. For T5
508 * the address is relative to BAR0.
510 mem_reg
= t4_read_reg(adap
,
511 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A
,
513 mem_aperture
= 1 << (WINDOW_G(mem_reg
) + WINDOW_SHIFT_X
);
514 mem_base
= PCIEOFST_G(mem_reg
) << PCIEOFST_SHIFT_X
;
515 if (is_t4(adap
->params
.chip
))
516 mem_base
-= adap
->t4_bar0
;
517 win_pf
= is_t4(adap
->params
.chip
) ? 0 : PFNUM_V(adap
->fn
);
519 /* Calculate our initial PCI-E Memory Window Position and Offset into
522 pos
= addr
& ~(mem_aperture
-1);
525 /* Set up initial PCI-E Memory Window to cover the start of our
526 * transfer. (Read it back to ensure that changes propagate before we
527 * attempt to use the new value.)
530 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A
, win
),
533 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A
, win
));
535 /* Transfer data to/from the adapter as long as there's an integral
536 * number of 32-bit transfers to complete.
538 * A note on Endianness issues:
540 * The "register" reads and writes below from/to the PCI-E Memory
541 * Window invoke the standard adapter Big-Endian to PCI-E Link
542 * Little-Endian "swizzel." As a result, if we have the following
543 * data in adapter memory:
545 * Memory: ... | b0 | b1 | b2 | b3 | ...
546 * Address: i+0 i+1 i+2 i+3
548 * Then a read of the adapter memory via the PCI-E Memory Window
553 * [ b3 | b2 | b1 | b0 ]
555 * If this value is stored into local memory on a Little-Endian system
556 * it will show up correctly in local memory as:
558 * ( ..., b0, b1, b2, b3, ... )
560 * But on a Big-Endian system, the store will show up in memory
561 * incorrectly swizzled as:
563 * ( ..., b3, b2, b1, b0, ... )
565 * So we need to account for this in the reads and writes to the
566 * PCI-E Memory Window below by undoing the register read/write
570 if (dir
== T4_MEMORY_READ
)
571 *buf
++ = le32_to_cpu((__force __le32
)t4_read_reg(adap
,
574 t4_write_reg(adap
, mem_base
+ offset
,
575 (__force u32
)cpu_to_le32(*buf
++));
576 offset
+= sizeof(__be32
);
577 len
-= sizeof(__be32
);
579 /* If we've reached the end of our current window aperture,
580 * move the PCI-E Memory Window on to the next. Note that
581 * doing this here after "len" may be 0 allows us to set up
582 * the PCI-E Memory Window for a possible final residual
585 if (offset
== mem_aperture
) {
589 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A
,
592 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A
,
597 /* If the original transfer had a length which wasn't a multiple of
598 * 32-bits, now's where we need to finish off the transfer of the
599 * residual amount. The PCI-E Memory Window has already been moved
600 * above (if necessary) to cover this final transfer.
610 if (dir
== T4_MEMORY_READ
) {
611 last
.word
= le32_to_cpu(
612 (__force __le32
)t4_read_reg(adap
,
614 for (bp
= (unsigned char *)buf
, i
= resid
; i
< 4; i
++)
615 bp
[i
] = last
.byte
[i
];
618 for (i
= resid
; i
< 4; i
++)
620 t4_write_reg(adap
, mem_base
+ offset
,
621 (__force u32
)cpu_to_le32(last
.word
));
629 * t4_get_regs_len - return the size of the chips register set
630 * @adapter: the adapter
632 * Returns the size of the chip's BAR0 register space.
634 unsigned int t4_get_regs_len(struct adapter
*adapter
)
636 unsigned int chip_version
= CHELSIO_CHIP_VERSION(adapter
->params
.chip
);
638 switch (chip_version
) {
640 return T4_REGMAP_SIZE
;
643 return T5_REGMAP_SIZE
;
646 dev_err(adapter
->pdev_dev
,
647 "Unsupported chip version %d\n", chip_version
);
652 * t4_get_regs - read chip registers into provided buffer
654 * @buf: register buffer
655 * @buf_size: size (in bytes) of register buffer
657 * If the provided register buffer isn't large enough for the chip's
658 * full register range, the register dump will be truncated to the
659 * register buffer's size.
661 void t4_get_regs(struct adapter
*adap
, void *buf
, size_t buf_size
)
663 static const unsigned int t4_reg_ranges
[] = {
884 static const unsigned int t5_reg_ranges
[] = {
1312 u32
*buf_end
= (u32
*)((char *)buf
+ buf_size
);
1313 const unsigned int *reg_ranges
;
1314 int reg_ranges_size
, range
;
1315 unsigned int chip_version
= CHELSIO_CHIP_VERSION(adap
->params
.chip
);
1317 /* Select the right set of register ranges to dump depending on the
1318 * adapter chip type.
1320 switch (chip_version
) {
1322 reg_ranges
= t4_reg_ranges
;
1323 reg_ranges_size
= ARRAY_SIZE(t4_reg_ranges
);
1327 reg_ranges
= t5_reg_ranges
;
1328 reg_ranges_size
= ARRAY_SIZE(t5_reg_ranges
);
1332 dev_err(adap
->pdev_dev
,
1333 "Unsupported chip version %d\n", chip_version
);
1337 /* Clear the register buffer and insert the appropriate register
1338 * values selected by the above register ranges.
1340 memset(buf
, 0, buf_size
);
1341 for (range
= 0; range
< reg_ranges_size
; range
+= 2) {
1342 unsigned int reg
= reg_ranges
[range
];
1343 unsigned int last_reg
= reg_ranges
[range
+ 1];
1344 u32
*bufp
= (u32
*)((char *)buf
+ reg
);
1346 /* Iterate across the register range filling in the register
1347 * buffer but don't write past the end of the register buffer.
1349 while (reg
<= last_reg
&& bufp
< buf_end
) {
1350 *bufp
++ = t4_read_reg(adap
, reg
);
1356 #define EEPROM_STAT_ADDR 0x7bfc
1357 #define VPD_BASE 0x400
1358 #define VPD_BASE_OLD 0
1359 #define VPD_LEN 1024
1360 #define CHELSIO_VPD_UNIQUE_ID 0x82
1363 * t4_seeprom_wp - enable/disable EEPROM write protection
1364 * @adapter: the adapter
1365 * @enable: whether to enable or disable write protection
1367 * Enables or disables write protection on the serial EEPROM.
1369 int t4_seeprom_wp(struct adapter
*adapter
, bool enable
)
1371 unsigned int v
= enable
? 0xc : 0;
1372 int ret
= pci_write_vpd(adapter
->pdev
, EEPROM_STAT_ADDR
, 4, &v
);
1373 return ret
< 0 ? ret
: 0;
1377 * get_vpd_params - read VPD parameters from VPD EEPROM
1378 * @adapter: adapter to read
1379 * @p: where to store the parameters
1381 * Reads card parameters stored in VPD EEPROM.
1383 int get_vpd_params(struct adapter
*adapter
, struct vpd_params
*p
)
1385 u32 cclk_param
, cclk_val
;
1389 unsigned int vpdr_len
, kw_offset
, id_len
;
1391 vpd
= vmalloc(VPD_LEN
);
1395 ret
= pci_read_vpd(adapter
->pdev
, VPD_BASE
, sizeof(u32
), vpd
);
1399 /* The VPD shall have a unique identifier specified by the PCI SIG.
1400 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
1401 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
1402 * is expected to automatically put this entry at the
1403 * beginning of the VPD.
1405 addr
= *vpd
== CHELSIO_VPD_UNIQUE_ID
? VPD_BASE
: VPD_BASE_OLD
;
1407 ret
= pci_read_vpd(adapter
->pdev
, addr
, VPD_LEN
, vpd
);
1411 if (vpd
[0] != PCI_VPD_LRDT_ID_STRING
) {
1412 dev_err(adapter
->pdev_dev
, "missing VPD ID string\n");
1417 id_len
= pci_vpd_lrdt_size(vpd
);
1418 if (id_len
> ID_LEN
)
1421 i
= pci_vpd_find_tag(vpd
, 0, VPD_LEN
, PCI_VPD_LRDT_RO_DATA
);
1423 dev_err(adapter
->pdev_dev
, "missing VPD-R section\n");
1428 vpdr_len
= pci_vpd_lrdt_size(&vpd
[i
]);
1429 kw_offset
= i
+ PCI_VPD_LRDT_TAG_SIZE
;
1430 if (vpdr_len
+ kw_offset
> VPD_LEN
) {
1431 dev_err(adapter
->pdev_dev
, "bad VPD-R length %u\n", vpdr_len
);
1436 #define FIND_VPD_KW(var, name) do { \
1437 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
1439 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
1443 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
1446 FIND_VPD_KW(i
, "RV");
1447 for (csum
= 0; i
>= 0; i
--)
1451 dev_err(adapter
->pdev_dev
,
1452 "corrupted VPD EEPROM, actual csum %u\n", csum
);
1457 FIND_VPD_KW(ec
, "EC");
1458 FIND_VPD_KW(sn
, "SN");
1459 FIND_VPD_KW(pn
, "PN");
1462 memcpy(p
->id
, vpd
+ PCI_VPD_LRDT_TAG_SIZE
, id_len
);
1464 memcpy(p
->ec
, vpd
+ ec
, EC_LEN
);
1466 i
= pci_vpd_info_field_size(vpd
+ sn
- PCI_VPD_INFO_FLD_HDR_SIZE
);
1467 memcpy(p
->sn
, vpd
+ sn
, min(i
, SERNUM_LEN
));
1469 i
= pci_vpd_info_field_size(vpd
+ pn
- PCI_VPD_INFO_FLD_HDR_SIZE
);
1470 memcpy(p
->pn
, vpd
+ pn
, min(i
, PN_LEN
));
1474 * Ask firmware for the Core Clock since it knows how to translate the
1475 * Reference Clock ('V2') VPD field into a Core Clock value ...
1477 cclk_param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
1478 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK
));
1479 ret
= t4_query_params(adapter
, adapter
->mbox
, 0, 0,
1480 1, &cclk_param
, &cclk_val
);
1491 /* serial flash and firmware constants */
1493 SF_ATTEMPTS
= 10, /* max retries for SF operations */
1495 /* flash command opcodes */
1496 SF_PROG_PAGE
= 2, /* program page */
1497 SF_WR_DISABLE
= 4, /* disable writes */
1498 SF_RD_STATUS
= 5, /* read status register */
1499 SF_WR_ENABLE
= 6, /* enable writes */
1500 SF_RD_DATA_FAST
= 0xb, /* read flash */
1501 SF_RD_ID
= 0x9f, /* read ID */
1502 SF_ERASE_SECTOR
= 0xd8, /* erase sector */
1504 FW_MAX_SIZE
= 16 * SF_SEC_SIZE
,
1508 * sf1_read - read data from the serial flash
1509 * @adapter: the adapter
1510 * @byte_cnt: number of bytes to read
1511 * @cont: whether another operation will be chained
1512 * @lock: whether to lock SF for PL access only
1513 * @valp: where to store the read data
1515 * Reads up to 4 bytes of data from the serial flash. The location of
1516 * the read needs to be specified prior to calling this by issuing the
1517 * appropriate commands to the serial flash.
1519 static int sf1_read(struct adapter
*adapter
, unsigned int byte_cnt
, int cont
,
1520 int lock
, u32
*valp
)
1524 if (!byte_cnt
|| byte_cnt
> 4)
1526 if (t4_read_reg(adapter
, SF_OP_A
) & SF_BUSY_F
)
1528 t4_write_reg(adapter
, SF_OP_A
, SF_LOCK_V(lock
) |
1529 SF_CONT_V(cont
) | BYTECNT_V(byte_cnt
- 1));
1530 ret
= t4_wait_op_done(adapter
, SF_OP_A
, SF_BUSY_F
, 0, SF_ATTEMPTS
, 5);
1532 *valp
= t4_read_reg(adapter
, SF_DATA_A
);
1537 * sf1_write - write data to the serial flash
1538 * @adapter: the adapter
1539 * @byte_cnt: number of bytes to write
1540 * @cont: whether another operation will be chained
1541 * @lock: whether to lock SF for PL access only
1542 * @val: value to write
1544 * Writes up to 4 bytes of data to the serial flash. The location of
1545 * the write needs to be specified prior to calling this by issuing the
1546 * appropriate commands to the serial flash.
1548 static int sf1_write(struct adapter
*adapter
, unsigned int byte_cnt
, int cont
,
1551 if (!byte_cnt
|| byte_cnt
> 4)
1553 if (t4_read_reg(adapter
, SF_OP_A
) & SF_BUSY_F
)
1555 t4_write_reg(adapter
, SF_DATA_A
, val
);
1556 t4_write_reg(adapter
, SF_OP_A
, SF_LOCK_V(lock
) |
1557 SF_CONT_V(cont
) | BYTECNT_V(byte_cnt
- 1) | OP_V(1));
1558 return t4_wait_op_done(adapter
, SF_OP_A
, SF_BUSY_F
, 0, SF_ATTEMPTS
, 5);
1562 * flash_wait_op - wait for a flash operation to complete
1563 * @adapter: the adapter
1564 * @attempts: max number of polls of the status register
1565 * @delay: delay between polls in ms
1567 * Wait for a flash operation to complete by polling the status register.
1569 static int flash_wait_op(struct adapter
*adapter
, int attempts
, int delay
)
1575 if ((ret
= sf1_write(adapter
, 1, 1, 1, SF_RD_STATUS
)) != 0 ||
1576 (ret
= sf1_read(adapter
, 1, 0, 1, &status
)) != 0)
1580 if (--attempts
== 0)
1588 * t4_read_flash - read words from serial flash
1589 * @adapter: the adapter
1590 * @addr: the start address for the read
1591 * @nwords: how many 32-bit words to read
1592 * @data: where to store the read data
1593 * @byte_oriented: whether to store data as bytes or as words
1595 * Read the specified number of 32-bit words from the serial flash.
1596 * If @byte_oriented is set the read data is stored as a byte array
1597 * (i.e., big-endian), otherwise as 32-bit words in the platform's
1598 * natural endianness.
1600 int t4_read_flash(struct adapter
*adapter
, unsigned int addr
,
1601 unsigned int nwords
, u32
*data
, int byte_oriented
)
1605 if (addr
+ nwords
* sizeof(u32
) > adapter
->params
.sf_size
|| (addr
& 3))
1608 addr
= swab32(addr
) | SF_RD_DATA_FAST
;
1610 if ((ret
= sf1_write(adapter
, 4, 1, 0, addr
)) != 0 ||
1611 (ret
= sf1_read(adapter
, 1, 1, 0, data
)) != 0)
1614 for ( ; nwords
; nwords
--, data
++) {
1615 ret
= sf1_read(adapter
, 4, nwords
> 1, nwords
== 1, data
);
1617 t4_write_reg(adapter
, SF_OP_A
, 0); /* unlock SF */
1621 *data
= (__force __u32
) (htonl(*data
));
1627 * t4_write_flash - write up to a page of data to the serial flash
1628 * @adapter: the adapter
1629 * @addr: the start address to write
1630 * @n: length of data to write in bytes
1631 * @data: the data to write
1633 * Writes up to a page of data (256 bytes) to the serial flash starting
1634 * at the given address. All the data must be written to the same page.
1636 static int t4_write_flash(struct adapter
*adapter
, unsigned int addr
,
1637 unsigned int n
, const u8
*data
)
1641 unsigned int i
, c
, left
, val
, offset
= addr
& 0xff;
1643 if (addr
>= adapter
->params
.sf_size
|| offset
+ n
> SF_PAGE_SIZE
)
1646 val
= swab32(addr
) | SF_PROG_PAGE
;
1648 if ((ret
= sf1_write(adapter
, 1, 0, 1, SF_WR_ENABLE
)) != 0 ||
1649 (ret
= sf1_write(adapter
, 4, 1, 1, val
)) != 0)
1652 for (left
= n
; left
; left
-= c
) {
1654 for (val
= 0, i
= 0; i
< c
; ++i
)
1655 val
= (val
<< 8) + *data
++;
1657 ret
= sf1_write(adapter
, c
, c
!= left
, 1, val
);
1661 ret
= flash_wait_op(adapter
, 8, 1);
1665 t4_write_reg(adapter
, SF_OP_A
, 0); /* unlock SF */
1667 /* Read the page to verify the write succeeded */
1668 ret
= t4_read_flash(adapter
, addr
& ~0xff, ARRAY_SIZE(buf
), buf
, 1);
1672 if (memcmp(data
- n
, (u8
*)buf
+ offset
, n
)) {
1673 dev_err(adapter
->pdev_dev
,
1674 "failed to correctly write the flash page at %#x\n",
1681 t4_write_reg(adapter
, SF_OP_A
, 0); /* unlock SF */
1686 * t4_get_fw_version - read the firmware version
1687 * @adapter: the adapter
1688 * @vers: where to place the version
1690 * Reads the FW version from flash.
1692 int t4_get_fw_version(struct adapter
*adapter
, u32
*vers
)
1694 return t4_read_flash(adapter
, FLASH_FW_START
+
1695 offsetof(struct fw_hdr
, fw_ver
), 1,
1700 * t4_get_tp_version - read the TP microcode version
1701 * @adapter: the adapter
1702 * @vers: where to place the version
1704 * Reads the TP microcode version from flash.
1706 int t4_get_tp_version(struct adapter
*adapter
, u32
*vers
)
1708 return t4_read_flash(adapter
, FLASH_FW_START
+
1709 offsetof(struct fw_hdr
, tp_microcode_ver
),
1714 * t4_get_exprom_version - return the Expansion ROM version (if any)
1715 * @adapter: the adapter
1716 * @vers: where to place the version
1718 * Reads the Expansion ROM header from FLASH and returns the version
1719 * number (if present) through the @vers return value pointer. We return
1720 * this in the Firmware Version Format since it's convenient. Return
1721 * 0 on success, -ENOENT if no Expansion ROM is present.
1723 int t4_get_exprom_version(struct adapter
*adap
, u32
*vers
)
1725 struct exprom_header
{
1726 unsigned char hdr_arr
[16]; /* must start with 0x55aa */
1727 unsigned char hdr_ver
[4]; /* Expansion ROM version */
1729 u32 exprom_header_buf
[DIV_ROUND_UP(sizeof(struct exprom_header
),
1733 ret
= t4_read_flash(adap
, FLASH_EXP_ROM_START
,
1734 ARRAY_SIZE(exprom_header_buf
), exprom_header_buf
,
1739 hdr
= (struct exprom_header
*)exprom_header_buf
;
1740 if (hdr
->hdr_arr
[0] != 0x55 || hdr
->hdr_arr
[1] != 0xaa)
1743 *vers
= (FW_HDR_FW_VER_MAJOR_V(hdr
->hdr_ver
[0]) |
1744 FW_HDR_FW_VER_MINOR_V(hdr
->hdr_ver
[1]) |
1745 FW_HDR_FW_VER_MICRO_V(hdr
->hdr_ver
[2]) |
1746 FW_HDR_FW_VER_BUILD_V(hdr
->hdr_ver
[3]));
1750 /* Is the given firmware API compatible with the one the driver was compiled
1753 static int fw_compatible(const struct fw_hdr
*hdr1
, const struct fw_hdr
*hdr2
)
1756 /* short circuit if it's the exact same firmware version */
1757 if (hdr1
->chip
== hdr2
->chip
&& hdr1
->fw_ver
== hdr2
->fw_ver
)
1760 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
1761 if (hdr1
->chip
== hdr2
->chip
&& SAME_INTF(nic
) && SAME_INTF(vnic
) &&
1762 SAME_INTF(ri
) && SAME_INTF(iscsi
) && SAME_INTF(fcoe
))
1769 /* The firmware in the filesystem is usable, but should it be installed?
1770 * This routine explains itself in detail if it indicates the filesystem
1771 * firmware should be installed.
1773 static int should_install_fs_fw(struct adapter
*adap
, int card_fw_usable
,
1778 if (!card_fw_usable
) {
1779 reason
= "incompatible or unusable";
1784 reason
= "older than the version supported with this driver";
1791 dev_err(adap
->pdev_dev
, "firmware on card (%u.%u.%u.%u) is %s, "
1792 "installing firmware %u.%u.%u.%u on card.\n",
1793 FW_HDR_FW_VER_MAJOR_G(c
), FW_HDR_FW_VER_MINOR_G(c
),
1794 FW_HDR_FW_VER_MICRO_G(c
), FW_HDR_FW_VER_BUILD_G(c
), reason
,
1795 FW_HDR_FW_VER_MAJOR_G(k
), FW_HDR_FW_VER_MINOR_G(k
),
1796 FW_HDR_FW_VER_MICRO_G(k
), FW_HDR_FW_VER_BUILD_G(k
));
1801 int t4_prep_fw(struct adapter
*adap
, struct fw_info
*fw_info
,
1802 const u8
*fw_data
, unsigned int fw_size
,
1803 struct fw_hdr
*card_fw
, enum dev_state state
,
1806 int ret
, card_fw_usable
, fs_fw_usable
;
1807 const struct fw_hdr
*fs_fw
;
1808 const struct fw_hdr
*drv_fw
;
1810 drv_fw
= &fw_info
->fw_hdr
;
1812 /* Read the header of the firmware on the card */
1813 ret
= -t4_read_flash(adap
, FLASH_FW_START
,
1814 sizeof(*card_fw
) / sizeof(uint32_t),
1815 (uint32_t *)card_fw
, 1);
1817 card_fw_usable
= fw_compatible(drv_fw
, (const void *)card_fw
);
1819 dev_err(adap
->pdev_dev
,
1820 "Unable to read card's firmware header: %d\n", ret
);
1824 if (fw_data
!= NULL
) {
1825 fs_fw
= (const void *)fw_data
;
1826 fs_fw_usable
= fw_compatible(drv_fw
, fs_fw
);
1832 if (card_fw_usable
&& card_fw
->fw_ver
== drv_fw
->fw_ver
&&
1833 (!fs_fw_usable
|| fs_fw
->fw_ver
== drv_fw
->fw_ver
)) {
1834 /* Common case: the firmware on the card is an exact match and
1835 * the filesystem one is an exact match too, or the filesystem
1836 * one is absent/incompatible.
1838 } else if (fs_fw_usable
&& state
== DEV_STATE_UNINIT
&&
1839 should_install_fs_fw(adap
, card_fw_usable
,
1840 be32_to_cpu(fs_fw
->fw_ver
),
1841 be32_to_cpu(card_fw
->fw_ver
))) {
1842 ret
= -t4_fw_upgrade(adap
, adap
->mbox
, fw_data
,
1845 dev_err(adap
->pdev_dev
,
1846 "failed to install firmware: %d\n", ret
);
1850 /* Installed successfully, update the cached header too. */
1853 *reset
= 0; /* already reset as part of load_fw */
1856 if (!card_fw_usable
) {
1859 d
= be32_to_cpu(drv_fw
->fw_ver
);
1860 c
= be32_to_cpu(card_fw
->fw_ver
);
1861 k
= fs_fw
? be32_to_cpu(fs_fw
->fw_ver
) : 0;
1863 dev_err(adap
->pdev_dev
, "Cannot find a usable firmware: "
1865 "driver compiled with %d.%d.%d.%d, "
1866 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
1868 FW_HDR_FW_VER_MAJOR_G(d
), FW_HDR_FW_VER_MINOR_G(d
),
1869 FW_HDR_FW_VER_MICRO_G(d
), FW_HDR_FW_VER_BUILD_G(d
),
1870 FW_HDR_FW_VER_MAJOR_G(c
), FW_HDR_FW_VER_MINOR_G(c
),
1871 FW_HDR_FW_VER_MICRO_G(c
), FW_HDR_FW_VER_BUILD_G(c
),
1872 FW_HDR_FW_VER_MAJOR_G(k
), FW_HDR_FW_VER_MINOR_G(k
),
1873 FW_HDR_FW_VER_MICRO_G(k
), FW_HDR_FW_VER_BUILD_G(k
));
1878 /* We're using whatever's on the card and it's known to be good. */
1879 adap
->params
.fw_vers
= be32_to_cpu(card_fw
->fw_ver
);
1880 adap
->params
.tp_vers
= be32_to_cpu(card_fw
->tp_microcode_ver
);
1887 * t4_flash_erase_sectors - erase a range of flash sectors
1888 * @adapter: the adapter
1889 * @start: the first sector to erase
1890 * @end: the last sector to erase
1892 * Erases the sectors in the given inclusive range.
1894 static int t4_flash_erase_sectors(struct adapter
*adapter
, int start
, int end
)
1898 if (end
>= adapter
->params
.sf_nsec
)
1901 while (start
<= end
) {
1902 if ((ret
= sf1_write(adapter
, 1, 0, 1, SF_WR_ENABLE
)) != 0 ||
1903 (ret
= sf1_write(adapter
, 4, 0, 1,
1904 SF_ERASE_SECTOR
| (start
<< 8))) != 0 ||
1905 (ret
= flash_wait_op(adapter
, 14, 500)) != 0) {
1906 dev_err(adapter
->pdev_dev
,
1907 "erase of flash sector %d failed, error %d\n",
1913 t4_write_reg(adapter
, SF_OP_A
, 0); /* unlock SF */
1918 * t4_flash_cfg_addr - return the address of the flash configuration file
1919 * @adapter: the adapter
1921 * Return the address within the flash where the Firmware Configuration
1924 unsigned int t4_flash_cfg_addr(struct adapter
*adapter
)
1926 if (adapter
->params
.sf_size
== 0x100000)
1927 return FLASH_FPGA_CFG_START
;
1929 return FLASH_CFG_START
;
1932 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
1933 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
1934 * and emit an error message for mismatched firmware to save our caller the
1937 static bool t4_fw_matches_chip(const struct adapter
*adap
,
1938 const struct fw_hdr
*hdr
)
1940 /* The expression below will return FALSE for any unsupported adapter
1941 * which will keep us "honest" in the future ...
1943 if ((is_t4(adap
->params
.chip
) && hdr
->chip
== FW_HDR_CHIP_T4
) ||
1944 (is_t5(adap
->params
.chip
) && hdr
->chip
== FW_HDR_CHIP_T5
))
1947 dev_err(adap
->pdev_dev
,
1948 "FW image (%d) is not suitable for this adapter (%d)\n",
1949 hdr
->chip
, CHELSIO_CHIP_VERSION(adap
->params
.chip
));
1954 * t4_load_fw - download firmware
1955 * @adap: the adapter
1956 * @fw_data: the firmware image to write
1959 * Write the supplied firmware image to the card's serial flash.
1961 int t4_load_fw(struct adapter
*adap
, const u8
*fw_data
, unsigned int size
)
1966 u8 first_page
[SF_PAGE_SIZE
];
1967 const __be32
*p
= (const __be32
*)fw_data
;
1968 const struct fw_hdr
*hdr
= (const struct fw_hdr
*)fw_data
;
1969 unsigned int sf_sec_size
= adap
->params
.sf_size
/ adap
->params
.sf_nsec
;
1970 unsigned int fw_img_start
= adap
->params
.sf_fw_start
;
1971 unsigned int fw_start_sec
= fw_img_start
/ sf_sec_size
;
1974 dev_err(adap
->pdev_dev
, "FW image has no data\n");
1978 dev_err(adap
->pdev_dev
,
1979 "FW image size not multiple of 512 bytes\n");
1982 if (ntohs(hdr
->len512
) * 512 != size
) {
1983 dev_err(adap
->pdev_dev
,
1984 "FW image size differs from size in FW header\n");
1987 if (size
> FW_MAX_SIZE
) {
1988 dev_err(adap
->pdev_dev
, "FW image too large, max is %u bytes\n",
1992 if (!t4_fw_matches_chip(adap
, hdr
))
1995 for (csum
= 0, i
= 0; i
< size
/ sizeof(csum
); i
++)
1996 csum
+= ntohl(p
[i
]);
1998 if (csum
!= 0xffffffff) {
1999 dev_err(adap
->pdev_dev
,
2000 "corrupted firmware image, checksum %#x\n", csum
);
2004 i
= DIV_ROUND_UP(size
, sf_sec_size
); /* # of sectors spanned */
2005 ret
= t4_flash_erase_sectors(adap
, fw_start_sec
, fw_start_sec
+ i
- 1);
2010 * We write the correct version at the end so the driver can see a bad
2011 * version if the FW write fails. Start by writing a copy of the
2012 * first page with a bad version.
2014 memcpy(first_page
, fw_data
, SF_PAGE_SIZE
);
2015 ((struct fw_hdr
*)first_page
)->fw_ver
= htonl(0xffffffff);
2016 ret
= t4_write_flash(adap
, fw_img_start
, SF_PAGE_SIZE
, first_page
);
2020 addr
= fw_img_start
;
2021 for (size
-= SF_PAGE_SIZE
; size
; size
-= SF_PAGE_SIZE
) {
2022 addr
+= SF_PAGE_SIZE
;
2023 fw_data
+= SF_PAGE_SIZE
;
2024 ret
= t4_write_flash(adap
, addr
, SF_PAGE_SIZE
, fw_data
);
2029 ret
= t4_write_flash(adap
,
2030 fw_img_start
+ offsetof(struct fw_hdr
, fw_ver
),
2031 sizeof(hdr
->fw_ver
), (const u8
*)&hdr
->fw_ver
);
2034 dev_err(adap
->pdev_dev
, "firmware download failed, error %d\n",
2037 ret
= t4_get_fw_version(adap
, &adap
->params
.fw_vers
);
2042 * t4_fwcache - firmware cache operation
2043 * @adap: the adapter
2044 * @op : the operation (flush or flush and invalidate)
2046 int t4_fwcache(struct adapter
*adap
, enum fw_params_param_dev_fwcache op
)
2048 struct fw_params_cmd c
;
2050 memset(&c
, 0, sizeof(c
));
2052 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD
) |
2053 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
2054 FW_PARAMS_CMD_PFN_V(adap
->fn
) |
2055 FW_PARAMS_CMD_VFN_V(0));
2056 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
2058 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
2059 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE
));
2060 c
.param
[0].val
= (__force __be32
)op
;
2062 return t4_wr_mbox(adap
, adap
->mbox
, &c
, sizeof(c
), NULL
);
2065 void t4_ulprx_read_la(struct adapter
*adap
, u32
*la_buf
)
2069 for (i
= 0; i
< 8; i
++) {
2070 u32
*p
= la_buf
+ i
;
2072 t4_write_reg(adap
, ULP_RX_LA_CTL_A
, i
);
2073 j
= t4_read_reg(adap
, ULP_RX_LA_WRPTR_A
);
2074 t4_write_reg(adap
, ULP_RX_LA_RDPTR_A
, j
);
2075 for (j
= 0; j
< ULPRX_LA_SIZE
; j
++, p
+= 8)
2076 *p
= t4_read_reg(adap
, ULP_RX_LA_RDDATA_A
);
2080 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
2081 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
2085 * t4_link_start - apply link configuration to MAC/PHY
2086 * @phy: the PHY to setup
2087 * @mac: the MAC to setup
2088 * @lc: the requested link configuration
2090 * Set up a port's MAC and PHY according to a desired link configuration.
2091 * - If the PHY can auto-negotiate first decide what to advertise, then
2092 * enable/disable auto-negotiation as desired, and reset.
2093 * - If the PHY does not auto-negotiate just reset it.
2094 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
2095 * otherwise do it later based on the outcome of auto-negotiation.
2097 int t4_link_start(struct adapter
*adap
, unsigned int mbox
, unsigned int port
,
2098 struct link_config
*lc
)
2100 struct fw_port_cmd c
;
2101 unsigned int fc
= 0, mdi
= FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO
);
2104 if (lc
->requested_fc
& PAUSE_RX
)
2105 fc
|= FW_PORT_CAP_FC_RX
;
2106 if (lc
->requested_fc
& PAUSE_TX
)
2107 fc
|= FW_PORT_CAP_FC_TX
;
2109 memset(&c
, 0, sizeof(c
));
2110 c
.op_to_portid
= htonl(FW_CMD_OP_V(FW_PORT_CMD
) | FW_CMD_REQUEST_F
|
2111 FW_CMD_EXEC_F
| FW_PORT_CMD_PORTID_V(port
));
2112 c
.action_to_len16
= htonl(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG
) |
2115 if (!(lc
->supported
& FW_PORT_CAP_ANEG
)) {
2116 c
.u
.l1cfg
.rcap
= htonl((lc
->supported
& ADVERT_MASK
) | fc
);
2117 lc
->fc
= lc
->requested_fc
& (PAUSE_RX
| PAUSE_TX
);
2118 } else if (lc
->autoneg
== AUTONEG_DISABLE
) {
2119 c
.u
.l1cfg
.rcap
= htonl(lc
->requested_speed
| fc
| mdi
);
2120 lc
->fc
= lc
->requested_fc
& (PAUSE_RX
| PAUSE_TX
);
2122 c
.u
.l1cfg
.rcap
= htonl(lc
->advertising
| fc
| mdi
);
2124 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
2128 * t4_restart_aneg - restart autonegotiation
2129 * @adap: the adapter
2130 * @mbox: mbox to use for the FW command
2131 * @port: the port id
2133 * Restarts autonegotiation for the selected port.
2135 int t4_restart_aneg(struct adapter
*adap
, unsigned int mbox
, unsigned int port
)
2137 struct fw_port_cmd c
;
2139 memset(&c
, 0, sizeof(c
));
2140 c
.op_to_portid
= htonl(FW_CMD_OP_V(FW_PORT_CMD
) | FW_CMD_REQUEST_F
|
2141 FW_CMD_EXEC_F
| FW_PORT_CMD_PORTID_V(port
));
2142 c
.action_to_len16
= htonl(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG
) |
2144 c
.u
.l1cfg
.rcap
= htonl(FW_PORT_CAP_ANEG
);
2145 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
2148 typedef void (*int_handler_t
)(struct adapter
*adap
);
2151 unsigned int mask
; /* bits to check in interrupt status */
2152 const char *msg
; /* message to print or NULL */
2153 short stat_idx
; /* stat counter to increment or -1 */
2154 unsigned short fatal
; /* whether the condition reported is fatal */
2155 int_handler_t int_handler
; /* platform-specific int handler */
2159 * t4_handle_intr_status - table driven interrupt handler
2160 * @adapter: the adapter that generated the interrupt
2161 * @reg: the interrupt status register to process
2162 * @acts: table of interrupt actions
2164 * A table driven interrupt handler that applies a set of masks to an
2165 * interrupt status word and performs the corresponding actions if the
2166 * interrupts described by the mask have occurred. The actions include
2167 * optionally emitting a warning or alert message. The table is terminated
2168 * by an entry specifying mask 0. Returns the number of fatal interrupt
2171 static int t4_handle_intr_status(struct adapter
*adapter
, unsigned int reg
,
2172 const struct intr_info
*acts
)
2175 unsigned int mask
= 0;
2176 unsigned int status
= t4_read_reg(adapter
, reg
);
2178 for ( ; acts
->mask
; ++acts
) {
2179 if (!(status
& acts
->mask
))
2183 dev_alert(adapter
->pdev_dev
, "%s (0x%x)\n", acts
->msg
,
2184 status
& acts
->mask
);
2185 } else if (acts
->msg
&& printk_ratelimit())
2186 dev_warn(adapter
->pdev_dev
, "%s (0x%x)\n", acts
->msg
,
2187 status
& acts
->mask
);
2188 if (acts
->int_handler
)
2189 acts
->int_handler(adapter
);
2193 if (status
) /* clear processed interrupts */
2194 t4_write_reg(adapter
, reg
, status
);
2199 * Interrupt handler for the PCIE module.
2201 static void pcie_intr_handler(struct adapter
*adapter
)
2203 static const struct intr_info sysbus_intr_info
[] = {
2204 { RNPP_F
, "RXNP array parity error", -1, 1 },
2205 { RPCP_F
, "RXPC array parity error", -1, 1 },
2206 { RCIP_F
, "RXCIF array parity error", -1, 1 },
2207 { RCCP_F
, "Rx completions control array parity error", -1, 1 },
2208 { RFTP_F
, "RXFT array parity error", -1, 1 },
2211 static const struct intr_info pcie_port_intr_info
[] = {
2212 { TPCP_F
, "TXPC array parity error", -1, 1 },
2213 { TNPP_F
, "TXNP array parity error", -1, 1 },
2214 { TFTP_F
, "TXFT array parity error", -1, 1 },
2215 { TCAP_F
, "TXCA array parity error", -1, 1 },
2216 { TCIP_F
, "TXCIF array parity error", -1, 1 },
2217 { RCAP_F
, "RXCA array parity error", -1, 1 },
2218 { OTDD_F
, "outbound request TLP discarded", -1, 1 },
2219 { RDPE_F
, "Rx data parity error", -1, 1 },
2220 { TDUE_F
, "Tx uncorrectable data error", -1, 1 },
2223 static const struct intr_info pcie_intr_info
[] = {
2224 { MSIADDRLPERR_F
, "MSI AddrL parity error", -1, 1 },
2225 { MSIADDRHPERR_F
, "MSI AddrH parity error", -1, 1 },
2226 { MSIDATAPERR_F
, "MSI data parity error", -1, 1 },
2227 { MSIXADDRLPERR_F
, "MSI-X AddrL parity error", -1, 1 },
2228 { MSIXADDRHPERR_F
, "MSI-X AddrH parity error", -1, 1 },
2229 { MSIXDATAPERR_F
, "MSI-X data parity error", -1, 1 },
2230 { MSIXDIPERR_F
, "MSI-X DI parity error", -1, 1 },
2231 { PIOCPLPERR_F
, "PCI PIO completion FIFO parity error", -1, 1 },
2232 { PIOREQPERR_F
, "PCI PIO request FIFO parity error", -1, 1 },
2233 { TARTAGPERR_F
, "PCI PCI target tag FIFO parity error", -1, 1 },
2234 { CCNTPERR_F
, "PCI CMD channel count parity error", -1, 1 },
2235 { CREQPERR_F
, "PCI CMD channel request parity error", -1, 1 },
2236 { CRSPPERR_F
, "PCI CMD channel response parity error", -1, 1 },
2237 { DCNTPERR_F
, "PCI DMA channel count parity error", -1, 1 },
2238 { DREQPERR_F
, "PCI DMA channel request parity error", -1, 1 },
2239 { DRSPPERR_F
, "PCI DMA channel response parity error", -1, 1 },
2240 { HCNTPERR_F
, "PCI HMA channel count parity error", -1, 1 },
2241 { HREQPERR_F
, "PCI HMA channel request parity error", -1, 1 },
2242 { HRSPPERR_F
, "PCI HMA channel response parity error", -1, 1 },
2243 { CFGSNPPERR_F
, "PCI config snoop FIFO parity error", -1, 1 },
2244 { FIDPERR_F
, "PCI FID parity error", -1, 1 },
2245 { INTXCLRPERR_F
, "PCI INTx clear parity error", -1, 1 },
2246 { MATAGPERR_F
, "PCI MA tag parity error", -1, 1 },
2247 { PIOTAGPERR_F
, "PCI PIO tag parity error", -1, 1 },
2248 { RXCPLPERR_F
, "PCI Rx completion parity error", -1, 1 },
2249 { RXWRPERR_F
, "PCI Rx write parity error", -1, 1 },
2250 { RPLPERR_F
, "PCI replay buffer parity error", -1, 1 },
2251 { PCIESINT_F
, "PCI core secondary fault", -1, 1 },
2252 { PCIEPINT_F
, "PCI core primary fault", -1, 1 },
2253 { UNXSPLCPLERR_F
, "PCI unexpected split completion error",
2258 static struct intr_info t5_pcie_intr_info
[] = {
2259 { MSTGRPPERR_F
, "Master Response Read Queue parity error",
2261 { MSTTIMEOUTPERR_F
, "Master Timeout FIFO parity error", -1, 1 },
2262 { MSIXSTIPERR_F
, "MSI-X STI SRAM parity error", -1, 1 },
2263 { MSIXADDRLPERR_F
, "MSI-X AddrL parity error", -1, 1 },
2264 { MSIXADDRHPERR_F
, "MSI-X AddrH parity error", -1, 1 },
2265 { MSIXDATAPERR_F
, "MSI-X data parity error", -1, 1 },
2266 { MSIXDIPERR_F
, "MSI-X DI parity error", -1, 1 },
2267 { PIOCPLGRPPERR_F
, "PCI PIO completion Group FIFO parity error",
2269 { PIOREQGRPPERR_F
, "PCI PIO request Group FIFO parity error",
2271 { TARTAGPERR_F
, "PCI PCI target tag FIFO parity error", -1, 1 },
2272 { MSTTAGQPERR_F
, "PCI master tag queue parity error", -1, 1 },
2273 { CREQPERR_F
, "PCI CMD channel request parity error", -1, 1 },
2274 { CRSPPERR_F
, "PCI CMD channel response parity error", -1, 1 },
2275 { DREQWRPERR_F
, "PCI DMA channel write request parity error",
2277 { DREQPERR_F
, "PCI DMA channel request parity error", -1, 1 },
2278 { DRSPPERR_F
, "PCI DMA channel response parity error", -1, 1 },
2279 { HREQWRPERR_F
, "PCI HMA channel count parity error", -1, 1 },
2280 { HREQPERR_F
, "PCI HMA channel request parity error", -1, 1 },
2281 { HRSPPERR_F
, "PCI HMA channel response parity error", -1, 1 },
2282 { CFGSNPPERR_F
, "PCI config snoop FIFO parity error", -1, 1 },
2283 { FIDPERR_F
, "PCI FID parity error", -1, 1 },
2284 { VFIDPERR_F
, "PCI INTx clear parity error", -1, 1 },
2285 { MAGRPPERR_F
, "PCI MA group FIFO parity error", -1, 1 },
2286 { PIOTAGPERR_F
, "PCI PIO tag parity error", -1, 1 },
2287 { IPRXHDRGRPPERR_F
, "PCI IP Rx header group parity error",
2289 { IPRXDATAGRPPERR_F
, "PCI IP Rx data group parity error",
2291 { RPLPERR_F
, "PCI IP replay buffer parity error", -1, 1 },
2292 { IPSOTPERR_F
, "PCI IP SOT buffer parity error", -1, 1 },
2293 { TRGT1GRPPERR_F
, "PCI TRGT1 group FIFOs parity error", -1, 1 },
2294 { READRSPERR_F
, "Outbound read error", -1, 0 },
2300 if (is_t4(adapter
->params
.chip
))
2301 fat
= t4_handle_intr_status(adapter
,
2302 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A
,
2304 t4_handle_intr_status(adapter
,
2305 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A
,
2306 pcie_port_intr_info
) +
2307 t4_handle_intr_status(adapter
, PCIE_INT_CAUSE_A
,
2310 fat
= t4_handle_intr_status(adapter
, PCIE_INT_CAUSE_A
,
2314 t4_fatal_err(adapter
);
2318 * TP interrupt handler.
2320 static void tp_intr_handler(struct adapter
*adapter
)
2322 static const struct intr_info tp_intr_info
[] = {
2323 { 0x3fffffff, "TP parity error", -1, 1 },
2324 { FLMTXFLSTEMPTY_F
, "TP out of Tx pages", -1, 1 },
2328 if (t4_handle_intr_status(adapter
, TP_INT_CAUSE_A
, tp_intr_info
))
2329 t4_fatal_err(adapter
);
2333 * SGE interrupt handler.
2335 static void sge_intr_handler(struct adapter
*adapter
)
2339 static const struct intr_info sge_intr_info
[] = {
2340 { ERR_CPL_EXCEED_IQE_SIZE_F
,
2341 "SGE received CPL exceeding IQE size", -1, 1 },
2342 { ERR_INVALID_CIDX_INC_F
,
2343 "SGE GTS CIDX increment too large", -1, 0 },
2344 { ERR_CPL_OPCODE_0_F
, "SGE received 0-length CPL", -1, 0 },
2345 { DBFIFO_LP_INT_F
, NULL
, -1, 0, t4_db_full
},
2346 { DBFIFO_HP_INT_F
, NULL
, -1, 0, t4_db_full
},
2347 { ERR_DROPPED_DB_F
, NULL
, -1, 0, t4_db_dropped
},
2348 { ERR_DATA_CPL_ON_HIGH_QID1_F
| ERR_DATA_CPL_ON_HIGH_QID0_F
,
2349 "SGE IQID > 1023 received CPL for FL", -1, 0 },
2350 { ERR_BAD_DB_PIDX3_F
, "SGE DBP 3 pidx increment too large", -1,
2352 { ERR_BAD_DB_PIDX2_F
, "SGE DBP 2 pidx increment too large", -1,
2354 { ERR_BAD_DB_PIDX1_F
, "SGE DBP 1 pidx increment too large", -1,
2356 { ERR_BAD_DB_PIDX0_F
, "SGE DBP 0 pidx increment too large", -1,
2358 { ERR_ING_CTXT_PRIO_F
,
2359 "SGE too many priority ingress contexts", -1, 0 },
2360 { ERR_EGR_CTXT_PRIO_F
,
2361 "SGE too many priority egress contexts", -1, 0 },
2362 { INGRESS_SIZE_ERR_F
, "SGE illegal ingress QID", -1, 0 },
2363 { EGRESS_SIZE_ERR_F
, "SGE illegal egress QID", -1, 0 },
2367 v
= (u64
)t4_read_reg(adapter
, SGE_INT_CAUSE1_A
) |
2368 ((u64
)t4_read_reg(adapter
, SGE_INT_CAUSE2_A
) << 32);
2370 dev_alert(adapter
->pdev_dev
, "SGE parity error (%#llx)\n",
2371 (unsigned long long)v
);
2372 t4_write_reg(adapter
, SGE_INT_CAUSE1_A
, v
);
2373 t4_write_reg(adapter
, SGE_INT_CAUSE2_A
, v
>> 32);
2376 if (t4_handle_intr_status(adapter
, SGE_INT_CAUSE3_A
, sge_intr_info
) ||
2378 t4_fatal_err(adapter
);
2381 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
2382 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
2383 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
2384 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
2387 * CIM interrupt handler.
2389 static void cim_intr_handler(struct adapter
*adapter
)
2391 static const struct intr_info cim_intr_info
[] = {
2392 { PREFDROPINT_F
, "CIM control register prefetch drop", -1, 1 },
2393 { CIM_OBQ_INTR
, "CIM OBQ parity error", -1, 1 },
2394 { CIM_IBQ_INTR
, "CIM IBQ parity error", -1, 1 },
2395 { MBUPPARERR_F
, "CIM mailbox uP parity error", -1, 1 },
2396 { MBHOSTPARERR_F
, "CIM mailbox host parity error", -1, 1 },
2397 { TIEQINPARERRINT_F
, "CIM TIEQ outgoing parity error", -1, 1 },
2398 { TIEQOUTPARERRINT_F
, "CIM TIEQ incoming parity error", -1, 1 },
2401 static const struct intr_info cim_upintr_info
[] = {
2402 { RSVDSPACEINT_F
, "CIM reserved space access", -1, 1 },
2403 { ILLTRANSINT_F
, "CIM illegal transaction", -1, 1 },
2404 { ILLWRINT_F
, "CIM illegal write", -1, 1 },
2405 { ILLRDINT_F
, "CIM illegal read", -1, 1 },
2406 { ILLRDBEINT_F
, "CIM illegal read BE", -1, 1 },
2407 { ILLWRBEINT_F
, "CIM illegal write BE", -1, 1 },
2408 { SGLRDBOOTINT_F
, "CIM single read from boot space", -1, 1 },
2409 { SGLWRBOOTINT_F
, "CIM single write to boot space", -1, 1 },
2410 { BLKWRBOOTINT_F
, "CIM block write to boot space", -1, 1 },
2411 { SGLRDFLASHINT_F
, "CIM single read from flash space", -1, 1 },
2412 { SGLWRFLASHINT_F
, "CIM single write to flash space", -1, 1 },
2413 { BLKWRFLASHINT_F
, "CIM block write to flash space", -1, 1 },
2414 { SGLRDEEPROMINT_F
, "CIM single EEPROM read", -1, 1 },
2415 { SGLWREEPROMINT_F
, "CIM single EEPROM write", -1, 1 },
2416 { BLKRDEEPROMINT_F
, "CIM block EEPROM read", -1, 1 },
2417 { BLKWREEPROMINT_F
, "CIM block EEPROM write", -1, 1 },
2418 { SGLRDCTLINT_F
, "CIM single read from CTL space", -1, 1 },
2419 { SGLWRCTLINT_F
, "CIM single write to CTL space", -1, 1 },
2420 { BLKRDCTLINT_F
, "CIM block read from CTL space", -1, 1 },
2421 { BLKWRCTLINT_F
, "CIM block write to CTL space", -1, 1 },
2422 { SGLRDPLINT_F
, "CIM single read from PL space", -1, 1 },
2423 { SGLWRPLINT_F
, "CIM single write to PL space", -1, 1 },
2424 { BLKRDPLINT_F
, "CIM block read from PL space", -1, 1 },
2425 { BLKWRPLINT_F
, "CIM block write to PL space", -1, 1 },
2426 { REQOVRLOOKUPINT_F
, "CIM request FIFO overwrite", -1, 1 },
2427 { RSPOVRLOOKUPINT_F
, "CIM response FIFO overwrite", -1, 1 },
2428 { TIMEOUTINT_F
, "CIM PIF timeout", -1, 1 },
2429 { TIMEOUTMAINT_F
, "CIM PIF MA timeout", -1, 1 },
2435 if (t4_read_reg(adapter
, PCIE_FW_A
) & PCIE_FW_ERR_F
)
2436 t4_report_fw_error(adapter
);
2438 fat
= t4_handle_intr_status(adapter
, CIM_HOST_INT_CAUSE_A
,
2440 t4_handle_intr_status(adapter
, CIM_HOST_UPACC_INT_CAUSE_A
,
2443 t4_fatal_err(adapter
);
2447 * ULP RX interrupt handler.
2449 static void ulprx_intr_handler(struct adapter
*adapter
)
2451 static const struct intr_info ulprx_intr_info
[] = {
2452 { 0x1800000, "ULPRX context error", -1, 1 },
2453 { 0x7fffff, "ULPRX parity error", -1, 1 },
2457 if (t4_handle_intr_status(adapter
, ULP_RX_INT_CAUSE_A
, ulprx_intr_info
))
2458 t4_fatal_err(adapter
);
2462 * ULP TX interrupt handler.
2464 static void ulptx_intr_handler(struct adapter
*adapter
)
2466 static const struct intr_info ulptx_intr_info
[] = {
2467 { PBL_BOUND_ERR_CH3_F
, "ULPTX channel 3 PBL out of bounds", -1,
2469 { PBL_BOUND_ERR_CH2_F
, "ULPTX channel 2 PBL out of bounds", -1,
2471 { PBL_BOUND_ERR_CH1_F
, "ULPTX channel 1 PBL out of bounds", -1,
2473 { PBL_BOUND_ERR_CH0_F
, "ULPTX channel 0 PBL out of bounds", -1,
2475 { 0xfffffff, "ULPTX parity error", -1, 1 },
2479 if (t4_handle_intr_status(adapter
, ULP_TX_INT_CAUSE_A
, ulptx_intr_info
))
2480 t4_fatal_err(adapter
);
2484 * PM TX interrupt handler.
2486 static void pmtx_intr_handler(struct adapter
*adapter
)
2488 static const struct intr_info pmtx_intr_info
[] = {
2489 { PCMD_LEN_OVFL0_F
, "PMTX channel 0 pcmd too large", -1, 1 },
2490 { PCMD_LEN_OVFL1_F
, "PMTX channel 1 pcmd too large", -1, 1 },
2491 { PCMD_LEN_OVFL2_F
, "PMTX channel 2 pcmd too large", -1, 1 },
2492 { ZERO_C_CMD_ERROR_F
, "PMTX 0-length pcmd", -1, 1 },
2493 { PMTX_FRAMING_ERROR_F
, "PMTX framing error", -1, 1 },
2494 { OESPI_PAR_ERROR_F
, "PMTX oespi parity error", -1, 1 },
2495 { DB_OPTIONS_PAR_ERROR_F
, "PMTX db_options parity error",
2497 { ICSPI_PAR_ERROR_F
, "PMTX icspi parity error", -1, 1 },
2498 { PMTX_C_PCMD_PAR_ERROR_F
, "PMTX c_pcmd parity error", -1, 1},
2502 if (t4_handle_intr_status(adapter
, PM_TX_INT_CAUSE_A
, pmtx_intr_info
))
2503 t4_fatal_err(adapter
);
2507 * PM RX interrupt handler.
2509 static void pmrx_intr_handler(struct adapter
*adapter
)
2511 static const struct intr_info pmrx_intr_info
[] = {
2512 { ZERO_E_CMD_ERROR_F
, "PMRX 0-length pcmd", -1, 1 },
2513 { PMRX_FRAMING_ERROR_F
, "PMRX framing error", -1, 1 },
2514 { OCSPI_PAR_ERROR_F
, "PMRX ocspi parity error", -1, 1 },
2515 { DB_OPTIONS_PAR_ERROR_F
, "PMRX db_options parity error",
2517 { IESPI_PAR_ERROR_F
, "PMRX iespi parity error", -1, 1 },
2518 { PMRX_E_PCMD_PAR_ERROR_F
, "PMRX e_pcmd parity error", -1, 1},
2522 if (t4_handle_intr_status(adapter
, PM_RX_INT_CAUSE_A
, pmrx_intr_info
))
2523 t4_fatal_err(adapter
);
2527 * CPL switch interrupt handler.
2529 static void cplsw_intr_handler(struct adapter
*adapter
)
2531 static const struct intr_info cplsw_intr_info
[] = {
2532 { CIM_OP_MAP_PERR_F
, "CPLSW CIM op_map parity error", -1, 1 },
2533 { CIM_OVFL_ERROR_F
, "CPLSW CIM overflow", -1, 1 },
2534 { TP_FRAMING_ERROR_F
, "CPLSW TP framing error", -1, 1 },
2535 { SGE_FRAMING_ERROR_F
, "CPLSW SGE framing error", -1, 1 },
2536 { CIM_FRAMING_ERROR_F
, "CPLSW CIM framing error", -1, 1 },
2537 { ZERO_SWITCH_ERROR_F
, "CPLSW no-switch error", -1, 1 },
2541 if (t4_handle_intr_status(adapter
, CPL_INTR_CAUSE_A
, cplsw_intr_info
))
2542 t4_fatal_err(adapter
);
2546 * LE interrupt handler.
2548 static void le_intr_handler(struct adapter
*adap
)
2550 static const struct intr_info le_intr_info
[] = {
2551 { LIPMISS_F
, "LE LIP miss", -1, 0 },
2552 { LIP0_F
, "LE 0 LIP error", -1, 0 },
2553 { PARITYERR_F
, "LE parity error", -1, 1 },
2554 { UNKNOWNCMD_F
, "LE unknown command", -1, 1 },
2555 { REQQPARERR_F
, "LE request queue parity error", -1, 1 },
2559 if (t4_handle_intr_status(adap
, LE_DB_INT_CAUSE_A
, le_intr_info
))
2564 * MPS interrupt handler.
2566 static void mps_intr_handler(struct adapter
*adapter
)
2568 static const struct intr_info mps_rx_intr_info
[] = {
2569 { 0xffffff, "MPS Rx parity error", -1, 1 },
2572 static const struct intr_info mps_tx_intr_info
[] = {
2573 { TPFIFO_V(TPFIFO_M
), "MPS Tx TP FIFO parity error", -1, 1 },
2574 { NCSIFIFO_F
, "MPS Tx NC-SI FIFO parity error", -1, 1 },
2575 { TXDATAFIFO_V(TXDATAFIFO_M
), "MPS Tx data FIFO parity error",
2577 { TXDESCFIFO_V(TXDESCFIFO_M
), "MPS Tx desc FIFO parity error",
2579 { BUBBLE_F
, "MPS Tx underflow", -1, 1 },
2580 { SECNTERR_F
, "MPS Tx SOP/EOP error", -1, 1 },
2581 { FRMERR_F
, "MPS Tx framing error", -1, 1 },
2584 static const struct intr_info mps_trc_intr_info
[] = {
2585 { FILTMEM_V(FILTMEM_M
), "MPS TRC filter parity error", -1, 1 },
2586 { PKTFIFO_V(PKTFIFO_M
), "MPS TRC packet FIFO parity error",
2588 { MISCPERR_F
, "MPS TRC misc parity error", -1, 1 },
2591 static const struct intr_info mps_stat_sram_intr_info
[] = {
2592 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
2595 static const struct intr_info mps_stat_tx_intr_info
[] = {
2596 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
2599 static const struct intr_info mps_stat_rx_intr_info
[] = {
2600 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
2603 static const struct intr_info mps_cls_intr_info
[] = {
2604 { MATCHSRAM_F
, "MPS match SRAM parity error", -1, 1 },
2605 { MATCHTCAM_F
, "MPS match TCAM parity error", -1, 1 },
2606 { HASHSRAM_F
, "MPS hash SRAM parity error", -1, 1 },
2612 fat
= t4_handle_intr_status(adapter
, MPS_RX_PERR_INT_CAUSE_A
,
2614 t4_handle_intr_status(adapter
, MPS_TX_INT_CAUSE_A
,
2616 t4_handle_intr_status(adapter
, MPS_TRC_INT_CAUSE_A
,
2617 mps_trc_intr_info
) +
2618 t4_handle_intr_status(adapter
, MPS_STAT_PERR_INT_CAUSE_SRAM_A
,
2619 mps_stat_sram_intr_info
) +
2620 t4_handle_intr_status(adapter
, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A
,
2621 mps_stat_tx_intr_info
) +
2622 t4_handle_intr_status(adapter
, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A
,
2623 mps_stat_rx_intr_info
) +
2624 t4_handle_intr_status(adapter
, MPS_CLS_INT_CAUSE_A
,
2627 t4_write_reg(adapter
, MPS_INT_CAUSE_A
, 0);
2628 t4_read_reg(adapter
, MPS_INT_CAUSE_A
); /* flush */
2630 t4_fatal_err(adapter
);
2633 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
2637 * EDC/MC interrupt handler.
2639 static void mem_intr_handler(struct adapter
*adapter
, int idx
)
2641 static const char name
[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
2643 unsigned int addr
, cnt_addr
, v
;
2645 if (idx
<= MEM_EDC1
) {
2646 addr
= EDC_REG(EDC_INT_CAUSE_A
, idx
);
2647 cnt_addr
= EDC_REG(EDC_ECC_STATUS_A
, idx
);
2648 } else if (idx
== MEM_MC
) {
2649 if (is_t4(adapter
->params
.chip
)) {
2650 addr
= MC_INT_CAUSE_A
;
2651 cnt_addr
= MC_ECC_STATUS_A
;
2653 addr
= MC_P_INT_CAUSE_A
;
2654 cnt_addr
= MC_P_ECC_STATUS_A
;
2657 addr
= MC_REG(MC_P_INT_CAUSE_A
, 1);
2658 cnt_addr
= MC_REG(MC_P_ECC_STATUS_A
, 1);
2661 v
= t4_read_reg(adapter
, addr
) & MEM_INT_MASK
;
2662 if (v
& PERR_INT_CAUSE_F
)
2663 dev_alert(adapter
->pdev_dev
, "%s FIFO parity error\n",
2665 if (v
& ECC_CE_INT_CAUSE_F
) {
2666 u32 cnt
= ECC_CECNT_G(t4_read_reg(adapter
, cnt_addr
));
2668 t4_write_reg(adapter
, cnt_addr
, ECC_CECNT_V(ECC_CECNT_M
));
2669 if (printk_ratelimit())
2670 dev_warn(adapter
->pdev_dev
,
2671 "%u %s correctable ECC data error%s\n",
2672 cnt
, name
[idx
], cnt
> 1 ? "s" : "");
2674 if (v
& ECC_UE_INT_CAUSE_F
)
2675 dev_alert(adapter
->pdev_dev
,
2676 "%s uncorrectable ECC data error\n", name
[idx
]);
2678 t4_write_reg(adapter
, addr
, v
);
2679 if (v
& (PERR_INT_CAUSE_F
| ECC_UE_INT_CAUSE_F
))
2680 t4_fatal_err(adapter
);
2684 * MA interrupt handler.
2686 static void ma_intr_handler(struct adapter
*adap
)
2688 u32 v
, status
= t4_read_reg(adap
, MA_INT_CAUSE_A
);
2690 if (status
& MEM_PERR_INT_CAUSE_F
) {
2691 dev_alert(adap
->pdev_dev
,
2692 "MA parity error, parity status %#x\n",
2693 t4_read_reg(adap
, MA_PARITY_ERROR_STATUS1_A
));
2694 if (is_t5(adap
->params
.chip
))
2695 dev_alert(adap
->pdev_dev
,
2696 "MA parity error, parity status %#x\n",
2698 MA_PARITY_ERROR_STATUS2_A
));
2700 if (status
& MEM_WRAP_INT_CAUSE_F
) {
2701 v
= t4_read_reg(adap
, MA_INT_WRAP_STATUS_A
);
2702 dev_alert(adap
->pdev_dev
, "MA address wrap-around error by "
2703 "client %u to address %#x\n",
2704 MEM_WRAP_CLIENT_NUM_G(v
),
2705 MEM_WRAP_ADDRESS_G(v
) << 4);
2707 t4_write_reg(adap
, MA_INT_CAUSE_A
, status
);
2712 * SMB interrupt handler.
2714 static void smb_intr_handler(struct adapter
*adap
)
2716 static const struct intr_info smb_intr_info
[] = {
2717 { MSTTXFIFOPARINT_F
, "SMB master Tx FIFO parity error", -1, 1 },
2718 { MSTRXFIFOPARINT_F
, "SMB master Rx FIFO parity error", -1, 1 },
2719 { SLVFIFOPARINT_F
, "SMB slave FIFO parity error", -1, 1 },
2723 if (t4_handle_intr_status(adap
, SMB_INT_CAUSE_A
, smb_intr_info
))
2728 * NC-SI interrupt handler.
2730 static void ncsi_intr_handler(struct adapter
*adap
)
2732 static const struct intr_info ncsi_intr_info
[] = {
2733 { CIM_DM_PRTY_ERR_F
, "NC-SI CIM parity error", -1, 1 },
2734 { MPS_DM_PRTY_ERR_F
, "NC-SI MPS parity error", -1, 1 },
2735 { TXFIFO_PRTY_ERR_F
, "NC-SI Tx FIFO parity error", -1, 1 },
2736 { RXFIFO_PRTY_ERR_F
, "NC-SI Rx FIFO parity error", -1, 1 },
2740 if (t4_handle_intr_status(adap
, NCSI_INT_CAUSE_A
, ncsi_intr_info
))
2745 * XGMAC interrupt handler.
2747 static void xgmac_intr_handler(struct adapter
*adap
, int port
)
2749 u32 v
, int_cause_reg
;
2751 if (is_t4(adap
->params
.chip
))
2752 int_cause_reg
= PORT_REG(port
, XGMAC_PORT_INT_CAUSE_A
);
2754 int_cause_reg
= T5_PORT_REG(port
, MAC_PORT_INT_CAUSE_A
);
2756 v
= t4_read_reg(adap
, int_cause_reg
);
2758 v
&= TXFIFO_PRTY_ERR_F
| RXFIFO_PRTY_ERR_F
;
2762 if (v
& TXFIFO_PRTY_ERR_F
)
2763 dev_alert(adap
->pdev_dev
, "XGMAC %d Tx FIFO parity error\n",
2765 if (v
& RXFIFO_PRTY_ERR_F
)
2766 dev_alert(adap
->pdev_dev
, "XGMAC %d Rx FIFO parity error\n",
2768 t4_write_reg(adap
, PORT_REG(port
, XGMAC_PORT_INT_CAUSE_A
), v
);
2773 * PL interrupt handler.
2775 static void pl_intr_handler(struct adapter
*adap
)
2777 static const struct intr_info pl_intr_info
[] = {
2778 { FATALPERR_F
, "T4 fatal parity error", -1, 1 },
2779 { PERRVFID_F
, "PL VFID_MAP parity error", -1, 1 },
2783 if (t4_handle_intr_status(adap
, PL_PL_INT_CAUSE_A
, pl_intr_info
))
2787 #define PF_INTR_MASK (PFSW_F)
2788 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
2789 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
2790 CPL_SWITCH_F | SGE_F | ULP_TX_F)
2793 * t4_slow_intr_handler - control path interrupt handler
2794 * @adapter: the adapter
2796 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
2797 * The designation 'slow' is because it involves register reads, while
2798 * data interrupts typically don't involve any MMIOs.
2800 int t4_slow_intr_handler(struct adapter
*adapter
)
2802 u32 cause
= t4_read_reg(adapter
, PL_INT_CAUSE_A
);
2804 if (!(cause
& GLBL_INTR_MASK
))
2807 cim_intr_handler(adapter
);
2809 mps_intr_handler(adapter
);
2811 ncsi_intr_handler(adapter
);
2813 pl_intr_handler(adapter
);
2815 smb_intr_handler(adapter
);
2816 if (cause
& XGMAC0_F
)
2817 xgmac_intr_handler(adapter
, 0);
2818 if (cause
& XGMAC1_F
)
2819 xgmac_intr_handler(adapter
, 1);
2820 if (cause
& XGMAC_KR0_F
)
2821 xgmac_intr_handler(adapter
, 2);
2822 if (cause
& XGMAC_KR1_F
)
2823 xgmac_intr_handler(adapter
, 3);
2825 pcie_intr_handler(adapter
);
2827 mem_intr_handler(adapter
, MEM_MC
);
2828 if (!is_t4(adapter
->params
.chip
) && (cause
& MC1_S
))
2829 mem_intr_handler(adapter
, MEM_MC1
);
2831 mem_intr_handler(adapter
, MEM_EDC0
);
2833 mem_intr_handler(adapter
, MEM_EDC1
);
2835 le_intr_handler(adapter
);
2837 tp_intr_handler(adapter
);
2839 ma_intr_handler(adapter
);
2840 if (cause
& PM_TX_F
)
2841 pmtx_intr_handler(adapter
);
2842 if (cause
& PM_RX_F
)
2843 pmrx_intr_handler(adapter
);
2844 if (cause
& ULP_RX_F
)
2845 ulprx_intr_handler(adapter
);
2846 if (cause
& CPL_SWITCH_F
)
2847 cplsw_intr_handler(adapter
);
2849 sge_intr_handler(adapter
);
2850 if (cause
& ULP_TX_F
)
2851 ulptx_intr_handler(adapter
);
2853 /* Clear the interrupts just processed for which we are the master. */
2854 t4_write_reg(adapter
, PL_INT_CAUSE_A
, cause
& GLBL_INTR_MASK
);
2855 (void)t4_read_reg(adapter
, PL_INT_CAUSE_A
); /* flush */
2860 * t4_intr_enable - enable interrupts
2861 * @adapter: the adapter whose interrupts should be enabled
2863 * Enable PF-specific interrupts for the calling function and the top-level
2864 * interrupt concentrator for global interrupts. Interrupts are already
2865 * enabled at each module, here we just enable the roots of the interrupt
2868 * Note: this function should be called only when the driver manages
2869 * non PF-specific interrupts from the various HW modules. Only one PCI
2870 * function at a time should be doing this.
2872 void t4_intr_enable(struct adapter
*adapter
)
2874 u32 pf
= SOURCEPF_G(t4_read_reg(adapter
, PL_WHOAMI_A
));
2876 t4_write_reg(adapter
, SGE_INT_ENABLE3_A
, ERR_CPL_EXCEED_IQE_SIZE_F
|
2877 ERR_INVALID_CIDX_INC_F
| ERR_CPL_OPCODE_0_F
|
2878 ERR_DROPPED_DB_F
| ERR_DATA_CPL_ON_HIGH_QID1_F
|
2879 ERR_DATA_CPL_ON_HIGH_QID0_F
| ERR_BAD_DB_PIDX3_F
|
2880 ERR_BAD_DB_PIDX2_F
| ERR_BAD_DB_PIDX1_F
|
2881 ERR_BAD_DB_PIDX0_F
| ERR_ING_CTXT_PRIO_F
|
2882 ERR_EGR_CTXT_PRIO_F
| INGRESS_SIZE_ERR_F
|
2883 DBFIFO_HP_INT_F
| DBFIFO_LP_INT_F
|
2885 t4_write_reg(adapter
, MYPF_REG(PL_PF_INT_ENABLE_A
), PF_INTR_MASK
);
2886 t4_set_reg_field(adapter
, PL_INT_MAP0_A
, 0, 1 << pf
);
2890 * t4_intr_disable - disable interrupts
2891 * @adapter: the adapter whose interrupts should be disabled
2893 * Disable interrupts. We only disable the top-level interrupt
2894 * concentrators. The caller must be a PCI function managing global
2897 void t4_intr_disable(struct adapter
*adapter
)
2899 u32 pf
= SOURCEPF_G(t4_read_reg(adapter
, PL_WHOAMI_A
));
2901 t4_write_reg(adapter
, MYPF_REG(PL_PF_INT_ENABLE_A
), 0);
2902 t4_set_reg_field(adapter
, PL_INT_MAP0_A
, 1 << pf
, 0);
2906 * hash_mac_addr - return the hash value of a MAC address
2907 * @addr: the 48-bit Ethernet MAC address
2909 * Hashes a MAC address according to the hash function used by HW inexact
2910 * (hash) address matching.
2912 static int hash_mac_addr(const u8
*addr
)
2914 u32 a
= ((u32
)addr
[0] << 16) | ((u32
)addr
[1] << 8) | addr
[2];
2915 u32 b
= ((u32
)addr
[3] << 16) | ((u32
)addr
[4] << 8) | addr
[5];
2923 * t4_config_rss_range - configure a portion of the RSS mapping table
2924 * @adapter: the adapter
2925 * @mbox: mbox to use for the FW command
2926 * @viid: virtual interface whose RSS subtable is to be written
2927 * @start: start entry in the table to write
2928 * @n: how many table entries to write
2929 * @rspq: values for the response queue lookup table
2930 * @nrspq: number of values in @rspq
2932 * Programs the selected part of the VI's RSS mapping table with the
2933 * provided values. If @nrspq < @n the supplied values are used repeatedly
2934 * until the full table range is populated.
2936 * The caller must ensure the values in @rspq are in the range allowed for
2939 int t4_config_rss_range(struct adapter
*adapter
, int mbox
, unsigned int viid
,
2940 int start
, int n
, const u16
*rspq
, unsigned int nrspq
)
2943 const u16
*rsp
= rspq
;
2944 const u16
*rsp_end
= rspq
+ nrspq
;
2945 struct fw_rss_ind_tbl_cmd cmd
;
2947 memset(&cmd
, 0, sizeof(cmd
));
2948 cmd
.op_to_viid
= htonl(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD
) |
2949 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
2950 FW_RSS_IND_TBL_CMD_VIID_V(viid
));
2951 cmd
.retval_len16
= htonl(FW_LEN16(cmd
));
2953 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
2955 int nq
= min(n
, 32);
2956 __be32
*qp
= &cmd
.iq0_to_iq2
;
2958 cmd
.niqid
= htons(nq
);
2959 cmd
.startidx
= htons(start
);
2967 v
= FW_RSS_IND_TBL_CMD_IQ0_V(*rsp
);
2968 if (++rsp
>= rsp_end
)
2970 v
|= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp
);
2971 if (++rsp
>= rsp_end
)
2973 v
|= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp
);
2974 if (++rsp
>= rsp_end
)
2981 ret
= t4_wr_mbox(adapter
, mbox
, &cmd
, sizeof(cmd
), NULL
);
2989 * t4_config_glbl_rss - configure the global RSS mode
2990 * @adapter: the adapter
2991 * @mbox: mbox to use for the FW command
2992 * @mode: global RSS mode
2993 * @flags: mode-specific flags
2995 * Sets the global RSS mode.
2997 int t4_config_glbl_rss(struct adapter
*adapter
, int mbox
, unsigned int mode
,
3000 struct fw_rss_glb_config_cmd c
;
3002 memset(&c
, 0, sizeof(c
));
3003 c
.op_to_write
= htonl(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD
) |
3004 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
);
3005 c
.retval_len16
= htonl(FW_LEN16(c
));
3006 if (mode
== FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL
) {
3007 c
.u
.manual
.mode_pkd
= htonl(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode
));
3008 } else if (mode
== FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL
) {
3009 c
.u
.basicvirtual
.mode_pkd
=
3010 htonl(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode
));
3011 c
.u
.basicvirtual
.synmapen_to_hashtoeplitz
= htonl(flags
);
3014 return t4_wr_mbox(adapter
, mbox
, &c
, sizeof(c
), NULL
);
3017 /* Read an RSS table row */
3018 static int rd_rss_row(struct adapter
*adap
, int row
, u32
*val
)
3020 t4_write_reg(adap
, TP_RSS_LKP_TABLE_A
, 0xfff00000 | row
);
3021 return t4_wait_op_done_val(adap
, TP_RSS_LKP_TABLE_A
, LKPTBLROWVLD_F
, 1,
3026 * t4_read_rss - read the contents of the RSS mapping table
3027 * @adapter: the adapter
3028 * @map: holds the contents of the RSS mapping table
3030 * Reads the contents of the RSS hash->queue mapping table.
3032 int t4_read_rss(struct adapter
*adapter
, u16
*map
)
3037 for (i
= 0; i
< RSS_NENTRIES
/ 2; ++i
) {
3038 ret
= rd_rss_row(adapter
, i
, &val
);
3041 *map
++ = LKPTBLQUEUE0_G(val
);
3042 *map
++ = LKPTBLQUEUE1_G(val
);
3048 * t4_read_rss_key - read the global RSS key
3049 * @adap: the adapter
3050 * @key: 10-entry array holding the 320-bit RSS key
3052 * Reads the global 320-bit RSS key.
3054 void t4_read_rss_key(struct adapter
*adap
, u32
*key
)
3056 t4_read_indirect(adap
, TP_PIO_ADDR_A
, TP_PIO_DATA_A
, key
, 10,
3057 TP_RSS_SECRET_KEY0_A
);
3061 * t4_write_rss_key - program one of the RSS keys
3062 * @adap: the adapter
3063 * @key: 10-entry array holding the 320-bit RSS key
3064 * @idx: which RSS key to write
3066 * Writes one of the RSS keys with the given 320-bit value. If @idx is
3067 * 0..15 the corresponding entry in the RSS key table is written,
3068 * otherwise the global RSS key is written.
3070 void t4_write_rss_key(struct adapter
*adap
, const u32
*key
, int idx
)
3072 t4_write_indirect(adap
, TP_PIO_ADDR_A
, TP_PIO_DATA_A
, key
, 10,
3073 TP_RSS_SECRET_KEY0_A
);
3074 if (idx
>= 0 && idx
< 16)
3075 t4_write_reg(adap
, TP_RSS_CONFIG_VRT_A
,
3076 KEYWRADDR_V(idx
) | KEYWREN_F
);
3080 * t4_read_rss_pf_config - read PF RSS Configuration Table
3081 * @adapter: the adapter
3082 * @index: the entry in the PF RSS table to read
3083 * @valp: where to store the returned value
3085 * Reads the PF RSS Configuration Table at the specified index and returns
3086 * the value found there.
3088 void t4_read_rss_pf_config(struct adapter
*adapter
, unsigned int index
,
3091 t4_read_indirect(adapter
, TP_PIO_ADDR_A
, TP_PIO_DATA_A
,
3092 valp
, 1, TP_RSS_PF0_CONFIG_A
+ index
);
3096 * t4_read_rss_vf_config - read VF RSS Configuration Table
3097 * @adapter: the adapter
3098 * @index: the entry in the VF RSS table to read
3099 * @vfl: where to store the returned VFL
3100 * @vfh: where to store the returned VFH
3102 * Reads the VF RSS Configuration Table at the specified index and returns
3103 * the (VFL, VFH) values found there.
3105 void t4_read_rss_vf_config(struct adapter
*adapter
, unsigned int index
,
3108 u32 vrt
, mask
, data
;
3110 mask
= VFWRADDR_V(VFWRADDR_M
);
3111 data
= VFWRADDR_V(index
);
3113 /* Request that the index'th VF Table values be read into VFL/VFH.
3115 vrt
= t4_read_reg(adapter
, TP_RSS_CONFIG_VRT_A
);
3116 vrt
&= ~(VFRDRG_F
| VFWREN_F
| KEYWREN_F
| mask
);
3117 vrt
|= data
| VFRDEN_F
;
3118 t4_write_reg(adapter
, TP_RSS_CONFIG_VRT_A
, vrt
);
3120 /* Grab the VFL/VFH values ...
3122 t4_read_indirect(adapter
, TP_PIO_ADDR_A
, TP_PIO_DATA_A
,
3123 vfl
, 1, TP_RSS_VFL_CONFIG_A
);
3124 t4_read_indirect(adapter
, TP_PIO_ADDR_A
, TP_PIO_DATA_A
,
3125 vfh
, 1, TP_RSS_VFH_CONFIG_A
);
3129 * t4_read_rss_pf_map - read PF RSS Map
3130 * @adapter: the adapter
3132 * Reads the PF RSS Map register and returns its value.
3134 u32
t4_read_rss_pf_map(struct adapter
*adapter
)
3138 t4_read_indirect(adapter
, TP_PIO_ADDR_A
, TP_PIO_DATA_A
,
3139 &pfmap
, 1, TP_RSS_PF_MAP_A
);
3144 * t4_read_rss_pf_mask - read PF RSS Mask
3145 * @adapter: the adapter
3147 * Reads the PF RSS Mask register and returns its value.
3149 u32
t4_read_rss_pf_mask(struct adapter
*adapter
)
3153 t4_read_indirect(adapter
, TP_PIO_ADDR_A
, TP_PIO_DATA_A
,
3154 &pfmask
, 1, TP_RSS_PF_MSK_A
);
3159 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
3160 * @adap: the adapter
3161 * @v4: holds the TCP/IP counter values
3162 * @v6: holds the TCP/IPv6 counter values
3164 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
3165 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
3167 void t4_tp_get_tcp_stats(struct adapter
*adap
, struct tp_tcp_stats
*v4
,
3168 struct tp_tcp_stats
*v6
)
3170 u32 val
[TP_MIB_TCP_RXT_SEG_LO_A
- TP_MIB_TCP_OUT_RST_A
+ 1];
3172 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
3173 #define STAT(x) val[STAT_IDX(x)]
3174 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
3177 t4_read_indirect(adap
, TP_MIB_INDEX_A
, TP_MIB_DATA_A
, val
,
3178 ARRAY_SIZE(val
), TP_MIB_TCP_OUT_RST_A
);
3179 v4
->tcpOutRsts
= STAT(OUT_RST
);
3180 v4
->tcpInSegs
= STAT64(IN_SEG
);
3181 v4
->tcpOutSegs
= STAT64(OUT_SEG
);
3182 v4
->tcpRetransSegs
= STAT64(RXT_SEG
);
3185 t4_read_indirect(adap
, TP_MIB_INDEX_A
, TP_MIB_DATA_A
, val
,
3186 ARRAY_SIZE(val
), TP_MIB_TCP_V6OUT_RST_A
);
3187 v6
->tcpOutRsts
= STAT(OUT_RST
);
3188 v6
->tcpInSegs
= STAT64(IN_SEG
);
3189 v6
->tcpOutSegs
= STAT64(OUT_SEG
);
3190 v6
->tcpRetransSegs
= STAT64(RXT_SEG
);
3198 * t4_read_mtu_tbl - returns the values in the HW path MTU table
3199 * @adap: the adapter
3200 * @mtus: where to store the MTU values
3201 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
3203 * Reads the HW path MTU table.
3205 void t4_read_mtu_tbl(struct adapter
*adap
, u16
*mtus
, u8
*mtu_log
)
3210 for (i
= 0; i
< NMTUS
; ++i
) {
3211 t4_write_reg(adap
, TP_MTU_TABLE_A
,
3212 MTUINDEX_V(0xff) | MTUVALUE_V(i
));
3213 v
= t4_read_reg(adap
, TP_MTU_TABLE_A
);
3214 mtus
[i
] = MTUVALUE_G(v
);
3216 mtu_log
[i
] = MTUWIDTH_G(v
);
3221 * t4_read_cong_tbl - reads the congestion control table
3222 * @adap: the adapter
3223 * @incr: where to store the alpha values
3225 * Reads the additive increments programmed into the HW congestion
3228 void t4_read_cong_tbl(struct adapter
*adap
, u16 incr
[NMTUS
][NCCTRL_WIN
])
3230 unsigned int mtu
, w
;
3232 for (mtu
= 0; mtu
< NMTUS
; ++mtu
)
3233 for (w
= 0; w
< NCCTRL_WIN
; ++w
) {
3234 t4_write_reg(adap
, TP_CCTRL_TABLE_A
,
3235 ROWINDEX_V(0xffff) | (mtu
<< 5) | w
);
3236 incr
[mtu
][w
] = (u16
)t4_read_reg(adap
,
3237 TP_CCTRL_TABLE_A
) & 0x1fff;
3242 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
3243 * @adap: the adapter
3244 * @addr: the indirect TP register address
3245 * @mask: specifies the field within the register to modify
3246 * @val: new value for the field
3248 * Sets a field of an indirect TP register to the given value.
3250 void t4_tp_wr_bits_indirect(struct adapter
*adap
, unsigned int addr
,
3251 unsigned int mask
, unsigned int val
)
3253 t4_write_reg(adap
, TP_PIO_ADDR_A
, addr
);
3254 val
|= t4_read_reg(adap
, TP_PIO_DATA_A
) & ~mask
;
3255 t4_write_reg(adap
, TP_PIO_DATA_A
, val
);
3259 * init_cong_ctrl - initialize congestion control parameters
3260 * @a: the alpha values for congestion control
3261 * @b: the beta values for congestion control
3263 * Initialize the congestion control parameters.
3265 static void init_cong_ctrl(unsigned short *a
, unsigned short *b
)
3267 a
[0] = a
[1] = a
[2] = a
[3] = a
[4] = a
[5] = a
[6] = a
[7] = a
[8] = 1;
3292 b
[0] = b
[1] = b
[2] = b
[3] = b
[4] = b
[5] = b
[6] = b
[7] = b
[8] = 0;
3295 b
[13] = b
[14] = b
[15] = b
[16] = 3;
3296 b
[17] = b
[18] = b
[19] = b
[20] = b
[21] = 4;
3297 b
[22] = b
[23] = b
[24] = b
[25] = b
[26] = b
[27] = 5;
3302 /* The minimum additive increment value for the congestion control table */
3303 #define CC_MIN_INCR 2U
3306 * t4_load_mtus - write the MTU and congestion control HW tables
3307 * @adap: the adapter
3308 * @mtus: the values for the MTU table
3309 * @alpha: the values for the congestion control alpha parameter
3310 * @beta: the values for the congestion control beta parameter
3312 * Write the HW MTU table with the supplied MTUs and the high-speed
3313 * congestion control table with the supplied alpha, beta, and MTUs.
3314 * We write the two tables together because the additive increments
3315 * depend on the MTUs.
3317 void t4_load_mtus(struct adapter
*adap
, const unsigned short *mtus
,
3318 const unsigned short *alpha
, const unsigned short *beta
)
3320 static const unsigned int avg_pkts
[NCCTRL_WIN
] = {
3321 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
3322 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
3323 28672, 40960, 57344, 81920, 114688, 163840, 229376
3328 for (i
= 0; i
< NMTUS
; ++i
) {
3329 unsigned int mtu
= mtus
[i
];
3330 unsigned int log2
= fls(mtu
);
3332 if (!(mtu
& ((1 << log2
) >> 2))) /* round */
3334 t4_write_reg(adap
, TP_MTU_TABLE_A
, MTUINDEX_V(i
) |
3335 MTUWIDTH_V(log2
) | MTUVALUE_V(mtu
));
3337 for (w
= 0; w
< NCCTRL_WIN
; ++w
) {
3340 inc
= max(((mtu
- 40) * alpha
[w
]) / avg_pkts
[w
],
3343 t4_write_reg(adap
, TP_CCTRL_TABLE_A
, (i
<< 21) |
3344 (w
<< 16) | (beta
[w
] << 13) | inc
);
3350 * t4_pmtx_get_stats - returns the HW stats from PMTX
3351 * @adap: the adapter
3352 * @cnt: where to store the count statistics
3353 * @cycles: where to store the cycle statistics
3355 * Returns performance statistics from PMTX.
3357 void t4_pmtx_get_stats(struct adapter
*adap
, u32 cnt
[], u64 cycles
[])
3362 for (i
= 0; i
< PM_NSTATS
; i
++) {
3363 t4_write_reg(adap
, PM_TX_STAT_CONFIG_A
, i
+ 1);
3364 cnt
[i
] = t4_read_reg(adap
, PM_TX_STAT_COUNT_A
);
3365 if (is_t4(adap
->params
.chip
)) {
3366 cycles
[i
] = t4_read_reg64(adap
, PM_TX_STAT_LSB_A
);
3368 t4_read_indirect(adap
, PM_TX_DBG_CTRL_A
,
3369 PM_TX_DBG_DATA_A
, data
, 2,
3370 PM_TX_DBG_STAT_MSB_A
);
3371 cycles
[i
] = (((u64
)data
[0] << 32) | data
[1]);
3377 * t4_pmrx_get_stats - returns the HW stats from PMRX
3378 * @adap: the adapter
3379 * @cnt: where to store the count statistics
3380 * @cycles: where to store the cycle statistics
3382 * Returns performance statistics from PMRX.
3384 void t4_pmrx_get_stats(struct adapter
*adap
, u32 cnt
[], u64 cycles
[])
3389 for (i
= 0; i
< PM_NSTATS
; i
++) {
3390 t4_write_reg(adap
, PM_RX_STAT_CONFIG_A
, i
+ 1);
3391 cnt
[i
] = t4_read_reg(adap
, PM_RX_STAT_COUNT_A
);
3392 if (is_t4(adap
->params
.chip
)) {
3393 cycles
[i
] = t4_read_reg64(adap
, PM_RX_STAT_LSB_A
);
3395 t4_read_indirect(adap
, PM_RX_DBG_CTRL_A
,
3396 PM_RX_DBG_DATA_A
, data
, 2,
3397 PM_RX_DBG_STAT_MSB_A
);
3398 cycles
[i
] = (((u64
)data
[0] << 32) | data
[1]);
3404 * get_mps_bg_map - return the buffer groups associated with a port
3405 * @adap: the adapter
3406 * @idx: the port index
3408 * Returns a bitmap indicating which MPS buffer groups are associated
3409 * with the given port. Bit i is set if buffer group i is used by the
3412 static unsigned int get_mps_bg_map(struct adapter
*adap
, int idx
)
3414 u32 n
= NUMPORTS_G(t4_read_reg(adap
, MPS_CMN_CTL_A
));
3417 return idx
== 0 ? 0xf : 0;
3419 return idx
< 2 ? (3 << (2 * idx
)) : 0;
3424 * t4_get_port_type_description - return Port Type string description
3425 * @port_type: firmware Port Type enumeration
3427 const char *t4_get_port_type_description(enum fw_port_type port_type
)
3429 static const char *const port_type_description
[] = {
3448 if (port_type
< ARRAY_SIZE(port_type_description
))
3449 return port_type_description
[port_type
];
3454 * t4_get_port_stats - collect port statistics
3455 * @adap: the adapter
3456 * @idx: the port index
3457 * @p: the stats structure to fill
3459 * Collect statistics related to the given port from HW.
3461 void t4_get_port_stats(struct adapter
*adap
, int idx
, struct port_stats
*p
)
3463 u32 bgmap
= get_mps_bg_map(adap
, idx
);
3465 #define GET_STAT(name) \
3466 t4_read_reg64(adap, \
3467 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
3468 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
3469 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
3471 p
->tx_octets
= GET_STAT(TX_PORT_BYTES
);
3472 p
->tx_frames
= GET_STAT(TX_PORT_FRAMES
);
3473 p
->tx_bcast_frames
= GET_STAT(TX_PORT_BCAST
);
3474 p
->tx_mcast_frames
= GET_STAT(TX_PORT_MCAST
);
3475 p
->tx_ucast_frames
= GET_STAT(TX_PORT_UCAST
);
3476 p
->tx_error_frames
= GET_STAT(TX_PORT_ERROR
);
3477 p
->tx_frames_64
= GET_STAT(TX_PORT_64B
);
3478 p
->tx_frames_65_127
= GET_STAT(TX_PORT_65B_127B
);
3479 p
->tx_frames_128_255
= GET_STAT(TX_PORT_128B_255B
);
3480 p
->tx_frames_256_511
= GET_STAT(TX_PORT_256B_511B
);
3481 p
->tx_frames_512_1023
= GET_STAT(TX_PORT_512B_1023B
);
3482 p
->tx_frames_1024_1518
= GET_STAT(TX_PORT_1024B_1518B
);
3483 p
->tx_frames_1519_max
= GET_STAT(TX_PORT_1519B_MAX
);
3484 p
->tx_drop
= GET_STAT(TX_PORT_DROP
);
3485 p
->tx_pause
= GET_STAT(TX_PORT_PAUSE
);
3486 p
->tx_ppp0
= GET_STAT(TX_PORT_PPP0
);
3487 p
->tx_ppp1
= GET_STAT(TX_PORT_PPP1
);
3488 p
->tx_ppp2
= GET_STAT(TX_PORT_PPP2
);
3489 p
->tx_ppp3
= GET_STAT(TX_PORT_PPP3
);
3490 p
->tx_ppp4
= GET_STAT(TX_PORT_PPP4
);
3491 p
->tx_ppp5
= GET_STAT(TX_PORT_PPP5
);
3492 p
->tx_ppp6
= GET_STAT(TX_PORT_PPP6
);
3493 p
->tx_ppp7
= GET_STAT(TX_PORT_PPP7
);
3495 p
->rx_octets
= GET_STAT(RX_PORT_BYTES
);
3496 p
->rx_frames
= GET_STAT(RX_PORT_FRAMES
);
3497 p
->rx_bcast_frames
= GET_STAT(RX_PORT_BCAST
);
3498 p
->rx_mcast_frames
= GET_STAT(RX_PORT_MCAST
);
3499 p
->rx_ucast_frames
= GET_STAT(RX_PORT_UCAST
);
3500 p
->rx_too_long
= GET_STAT(RX_PORT_MTU_ERROR
);
3501 p
->rx_jabber
= GET_STAT(RX_PORT_MTU_CRC_ERROR
);
3502 p
->rx_fcs_err
= GET_STAT(RX_PORT_CRC_ERROR
);
3503 p
->rx_len_err
= GET_STAT(RX_PORT_LEN_ERROR
);
3504 p
->rx_symbol_err
= GET_STAT(RX_PORT_SYM_ERROR
);
3505 p
->rx_runt
= GET_STAT(RX_PORT_LESS_64B
);
3506 p
->rx_frames_64
= GET_STAT(RX_PORT_64B
);
3507 p
->rx_frames_65_127
= GET_STAT(RX_PORT_65B_127B
);
3508 p
->rx_frames_128_255
= GET_STAT(RX_PORT_128B_255B
);
3509 p
->rx_frames_256_511
= GET_STAT(RX_PORT_256B_511B
);
3510 p
->rx_frames_512_1023
= GET_STAT(RX_PORT_512B_1023B
);
3511 p
->rx_frames_1024_1518
= GET_STAT(RX_PORT_1024B_1518B
);
3512 p
->rx_frames_1519_max
= GET_STAT(RX_PORT_1519B_MAX
);
3513 p
->rx_pause
= GET_STAT(RX_PORT_PAUSE
);
3514 p
->rx_ppp0
= GET_STAT(RX_PORT_PPP0
);
3515 p
->rx_ppp1
= GET_STAT(RX_PORT_PPP1
);
3516 p
->rx_ppp2
= GET_STAT(RX_PORT_PPP2
);
3517 p
->rx_ppp3
= GET_STAT(RX_PORT_PPP3
);
3518 p
->rx_ppp4
= GET_STAT(RX_PORT_PPP4
);
3519 p
->rx_ppp5
= GET_STAT(RX_PORT_PPP5
);
3520 p
->rx_ppp6
= GET_STAT(RX_PORT_PPP6
);
3521 p
->rx_ppp7
= GET_STAT(RX_PORT_PPP7
);
3523 p
->rx_ovflow0
= (bgmap
& 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME
) : 0;
3524 p
->rx_ovflow1
= (bgmap
& 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME
) : 0;
3525 p
->rx_ovflow2
= (bgmap
& 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME
) : 0;
3526 p
->rx_ovflow3
= (bgmap
& 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME
) : 0;
3527 p
->rx_trunc0
= (bgmap
& 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME
) : 0;
3528 p
->rx_trunc1
= (bgmap
& 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME
) : 0;
3529 p
->rx_trunc2
= (bgmap
& 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME
) : 0;
3530 p
->rx_trunc3
= (bgmap
& 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME
) : 0;
3537 * t4_wol_magic_enable - enable/disable magic packet WoL
3538 * @adap: the adapter
3539 * @port: the physical port index
3540 * @addr: MAC address expected in magic packets, %NULL to disable
3542 * Enables/disables magic packet wake-on-LAN for the selected port.
3544 void t4_wol_magic_enable(struct adapter
*adap
, unsigned int port
,
3547 u32 mag_id_reg_l
, mag_id_reg_h
, port_cfg_reg
;
3549 if (is_t4(adap
->params
.chip
)) {
3550 mag_id_reg_l
= PORT_REG(port
, XGMAC_PORT_MAGIC_MACID_LO
);
3551 mag_id_reg_h
= PORT_REG(port
, XGMAC_PORT_MAGIC_MACID_HI
);
3552 port_cfg_reg
= PORT_REG(port
, XGMAC_PORT_CFG2_A
);
3554 mag_id_reg_l
= T5_PORT_REG(port
, MAC_PORT_MAGIC_MACID_LO
);
3555 mag_id_reg_h
= T5_PORT_REG(port
, MAC_PORT_MAGIC_MACID_HI
);
3556 port_cfg_reg
= T5_PORT_REG(port
, MAC_PORT_CFG2_A
);
3560 t4_write_reg(adap
, mag_id_reg_l
,
3561 (addr
[2] << 24) | (addr
[3] << 16) |
3562 (addr
[4] << 8) | addr
[5]);
3563 t4_write_reg(adap
, mag_id_reg_h
,
3564 (addr
[0] << 8) | addr
[1]);
3566 t4_set_reg_field(adap
, port_cfg_reg
, MAGICEN_F
,
3567 addr
? MAGICEN_F
: 0);
3571 * t4_wol_pat_enable - enable/disable pattern-based WoL
3572 * @adap: the adapter
3573 * @port: the physical port index
3574 * @map: bitmap of which HW pattern filters to set
3575 * @mask0: byte mask for bytes 0-63 of a packet
3576 * @mask1: byte mask for bytes 64-127 of a packet
3577 * @crc: Ethernet CRC for selected bytes
3578 * @enable: enable/disable switch
3580 * Sets the pattern filters indicated in @map to mask out the bytes
3581 * specified in @mask0/@mask1 in received packets and compare the CRC of
3582 * the resulting packet against @crc. If @enable is %true pattern-based
3583 * WoL is enabled, otherwise disabled.
3585 int t4_wol_pat_enable(struct adapter
*adap
, unsigned int port
, unsigned int map
,
3586 u64 mask0
, u64 mask1
, unsigned int crc
, bool enable
)
3591 if (is_t4(adap
->params
.chip
))
3592 port_cfg_reg
= PORT_REG(port
, XGMAC_PORT_CFG2_A
);
3594 port_cfg_reg
= T5_PORT_REG(port
, MAC_PORT_CFG2_A
);
3597 t4_set_reg_field(adap
, port_cfg_reg
, PATEN_F
, 0);
3603 #define EPIO_REG(name) \
3604 (is_t4(adap->params.chip) ? \
3605 PORT_REG(port, XGMAC_PORT_EPIO_##name##_A) : \
3606 T5_PORT_REG(port, MAC_PORT_EPIO_##name##_A))
3608 t4_write_reg(adap
, EPIO_REG(DATA1
), mask0
>> 32);
3609 t4_write_reg(adap
, EPIO_REG(DATA2
), mask1
);
3610 t4_write_reg(adap
, EPIO_REG(DATA3
), mask1
>> 32);
3612 for (i
= 0; i
< NWOL_PAT
; i
++, map
>>= 1) {
3616 /* write byte masks */
3617 t4_write_reg(adap
, EPIO_REG(DATA0
), mask0
);
3618 t4_write_reg(adap
, EPIO_REG(OP
), ADDRESS_V(i
) | EPIOWR_F
);
3619 t4_read_reg(adap
, EPIO_REG(OP
)); /* flush */
3620 if (t4_read_reg(adap
, EPIO_REG(OP
)) & SF_BUSY_F
)
3624 t4_write_reg(adap
, EPIO_REG(DATA0
), crc
);
3625 t4_write_reg(adap
, EPIO_REG(OP
), ADDRESS_V(i
+ 32) | EPIOWR_F
);
3626 t4_read_reg(adap
, EPIO_REG(OP
)); /* flush */
3627 if (t4_read_reg(adap
, EPIO_REG(OP
)) & SF_BUSY_F
)
3632 t4_set_reg_field(adap
, PORT_REG(port
, XGMAC_PORT_CFG2_A
), 0, PATEN_F
);
3636 /* t4_mk_filtdelwr - create a delete filter WR
3637 * @ftid: the filter ID
3638 * @wr: the filter work request to populate
3639 * @qid: ingress queue to receive the delete notification
3641 * Creates a filter work request to delete the supplied filter. If @qid is
3642 * negative the delete notification is suppressed.
3644 void t4_mk_filtdelwr(unsigned int ftid
, struct fw_filter_wr
*wr
, int qid
)
3646 memset(wr
, 0, sizeof(*wr
));
3647 wr
->op_pkd
= htonl(FW_WR_OP_V(FW_FILTER_WR
));
3648 wr
->len16_pkd
= htonl(FW_WR_LEN16_V(sizeof(*wr
) / 16));
3649 wr
->tid_to_iq
= htonl(FW_FILTER_WR_TID_V(ftid
) |
3650 FW_FILTER_WR_NOREPLY_V(qid
< 0));
3651 wr
->del_filter_to_l2tix
= htonl(FW_FILTER_WR_DEL_FILTER_F
);
3653 wr
->rx_chan_rx_rpl_iq
= htons(FW_FILTER_WR_RX_RPL_IQ_V(qid
));
3656 #define INIT_CMD(var, cmd, rd_wr) do { \
3657 (var).op_to_write = htonl(FW_CMD_OP_V(FW_##cmd##_CMD) | \
3658 FW_CMD_REQUEST_F | FW_CMD_##rd_wr##_F); \
3659 (var).retval_len16 = htonl(FW_LEN16(var)); \
3662 int t4_fwaddrspace_write(struct adapter
*adap
, unsigned int mbox
,
3665 struct fw_ldst_cmd c
;
3667 memset(&c
, 0, sizeof(c
));
3668 c
.op_to_addrspace
= htonl(FW_CMD_OP_V(FW_LDST_CMD
) | FW_CMD_REQUEST_F
|
3670 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE
));
3671 c
.cycles_to_len16
= htonl(FW_LEN16(c
));
3672 c
.u
.addrval
.addr
= htonl(addr
);
3673 c
.u
.addrval
.val
= htonl(val
);
3675 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
3679 * t4_mdio_rd - read a PHY register through MDIO
3680 * @adap: the adapter
3681 * @mbox: mailbox to use for the FW command
3682 * @phy_addr: the PHY address
3683 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
3684 * @reg: the register to read
3685 * @valp: where to store the value
3687 * Issues a FW command through the given mailbox to read a PHY register.
3689 int t4_mdio_rd(struct adapter
*adap
, unsigned int mbox
, unsigned int phy_addr
,
3690 unsigned int mmd
, unsigned int reg
, u16
*valp
)
3693 struct fw_ldst_cmd c
;
3695 memset(&c
, 0, sizeof(c
));
3696 c
.op_to_addrspace
= htonl(FW_CMD_OP_V(FW_LDST_CMD
) | FW_CMD_REQUEST_F
|
3697 FW_CMD_READ_F
| FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO
));
3698 c
.cycles_to_len16
= htonl(FW_LEN16(c
));
3699 c
.u
.mdio
.paddr_mmd
= htons(FW_LDST_CMD_PADDR_V(phy_addr
) |
3700 FW_LDST_CMD_MMD_V(mmd
));
3701 c
.u
.mdio
.raddr
= htons(reg
);
3703 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
3705 *valp
= ntohs(c
.u
.mdio
.rval
);
3710 * t4_mdio_wr - write a PHY register through MDIO
3711 * @adap: the adapter
3712 * @mbox: mailbox to use for the FW command
3713 * @phy_addr: the PHY address
3714 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
3715 * @reg: the register to write
3716 * @valp: value to write
3718 * Issues a FW command through the given mailbox to write a PHY register.
3720 int t4_mdio_wr(struct adapter
*adap
, unsigned int mbox
, unsigned int phy_addr
,
3721 unsigned int mmd
, unsigned int reg
, u16 val
)
3723 struct fw_ldst_cmd c
;
3725 memset(&c
, 0, sizeof(c
));
3726 c
.op_to_addrspace
= htonl(FW_CMD_OP_V(FW_LDST_CMD
) | FW_CMD_REQUEST_F
|
3727 FW_CMD_WRITE_F
| FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO
));
3728 c
.cycles_to_len16
= htonl(FW_LEN16(c
));
3729 c
.u
.mdio
.paddr_mmd
= htons(FW_LDST_CMD_PADDR_V(phy_addr
) |
3730 FW_LDST_CMD_MMD_V(mmd
));
3731 c
.u
.mdio
.raddr
= htons(reg
);
3732 c
.u
.mdio
.rval
= htons(val
);
3734 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
3738 * t4_sge_decode_idma_state - decode the idma state
3739 * @adap: the adapter
3740 * @state: the state idma is stuck in
3742 void t4_sge_decode_idma_state(struct adapter
*adapter
, int state
)
3744 static const char * const t4_decode
[] = {
3746 "IDMA_PUSH_MORE_CPL_FIFO",
3747 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
3749 "IDMA_PHYSADDR_SEND_PCIEHDR",
3750 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
3751 "IDMA_PHYSADDR_SEND_PAYLOAD",
3752 "IDMA_SEND_FIFO_TO_IMSG",
3753 "IDMA_FL_REQ_DATA_FL_PREP",
3754 "IDMA_FL_REQ_DATA_FL",
3756 "IDMA_FL_H_REQ_HEADER_FL",
3757 "IDMA_FL_H_SEND_PCIEHDR",
3758 "IDMA_FL_H_PUSH_CPL_FIFO",
3759 "IDMA_FL_H_SEND_CPL",
3760 "IDMA_FL_H_SEND_IP_HDR_FIRST",
3761 "IDMA_FL_H_SEND_IP_HDR",
3762 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
3763 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
3764 "IDMA_FL_H_SEND_IP_HDR_PADDING",
3765 "IDMA_FL_D_SEND_PCIEHDR",
3766 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
3767 "IDMA_FL_D_REQ_NEXT_DATA_FL",
3768 "IDMA_FL_SEND_PCIEHDR",
3769 "IDMA_FL_PUSH_CPL_FIFO",
3771 "IDMA_FL_SEND_PAYLOAD_FIRST",
3772 "IDMA_FL_SEND_PAYLOAD",
3773 "IDMA_FL_REQ_NEXT_DATA_FL",
3774 "IDMA_FL_SEND_NEXT_PCIEHDR",
3775 "IDMA_FL_SEND_PADDING",
3776 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
3777 "IDMA_FL_SEND_FIFO_TO_IMSG",
3778 "IDMA_FL_REQ_DATAFL_DONE",
3779 "IDMA_FL_REQ_HEADERFL_DONE",
3781 static const char * const t5_decode
[] = {
3784 "IDMA_PUSH_MORE_CPL_FIFO",
3785 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
3786 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
3787 "IDMA_PHYSADDR_SEND_PCIEHDR",
3788 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
3789 "IDMA_PHYSADDR_SEND_PAYLOAD",
3790 "IDMA_SEND_FIFO_TO_IMSG",
3791 "IDMA_FL_REQ_DATA_FL",
3793 "IDMA_FL_DROP_SEND_INC",
3794 "IDMA_FL_H_REQ_HEADER_FL",
3795 "IDMA_FL_H_SEND_PCIEHDR",
3796 "IDMA_FL_H_PUSH_CPL_FIFO",
3797 "IDMA_FL_H_SEND_CPL",
3798 "IDMA_FL_H_SEND_IP_HDR_FIRST",
3799 "IDMA_FL_H_SEND_IP_HDR",
3800 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
3801 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
3802 "IDMA_FL_H_SEND_IP_HDR_PADDING",
3803 "IDMA_FL_D_SEND_PCIEHDR",
3804 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
3805 "IDMA_FL_D_REQ_NEXT_DATA_FL",
3806 "IDMA_FL_SEND_PCIEHDR",
3807 "IDMA_FL_PUSH_CPL_FIFO",
3809 "IDMA_FL_SEND_PAYLOAD_FIRST",
3810 "IDMA_FL_SEND_PAYLOAD",
3811 "IDMA_FL_REQ_NEXT_DATA_FL",
3812 "IDMA_FL_SEND_NEXT_PCIEHDR",
3813 "IDMA_FL_SEND_PADDING",
3814 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
3816 static const u32 sge_regs
[] = {
3817 SGE_DEBUG_DATA_LOW_INDEX_2_A
,
3818 SGE_DEBUG_DATA_LOW_INDEX_3_A
,
3819 SGE_DEBUG_DATA_HIGH_INDEX_10_A
,
3821 const char **sge_idma_decode
;
3822 int sge_idma_decode_nstates
;
3825 if (is_t4(adapter
->params
.chip
)) {
3826 sge_idma_decode
= (const char **)t4_decode
;
3827 sge_idma_decode_nstates
= ARRAY_SIZE(t4_decode
);
3829 sge_idma_decode
= (const char **)t5_decode
;
3830 sge_idma_decode_nstates
= ARRAY_SIZE(t5_decode
);
3833 if (state
< sge_idma_decode_nstates
)
3834 CH_WARN(adapter
, "idma state %s\n", sge_idma_decode
[state
]);
3836 CH_WARN(adapter
, "idma state %d unknown\n", state
);
3838 for (i
= 0; i
< ARRAY_SIZE(sge_regs
); i
++)
3839 CH_WARN(adapter
, "SGE register %#x value %#x\n",
3840 sge_regs
[i
], t4_read_reg(adapter
, sge_regs
[i
]));
3844 * t4_fw_hello - establish communication with FW
3845 * @adap: the adapter
3846 * @mbox: mailbox to use for the FW command
3847 * @evt_mbox: mailbox to receive async FW events
3848 * @master: specifies the caller's willingness to be the device master
3849 * @state: returns the current device state (if non-NULL)
3851 * Issues a command to establish communication with FW. Returns either
3852 * an error (negative integer) or the mailbox of the Master PF.
3854 int t4_fw_hello(struct adapter
*adap
, unsigned int mbox
, unsigned int evt_mbox
,
3855 enum dev_master master
, enum dev_state
*state
)
3858 struct fw_hello_cmd c
;
3860 unsigned int master_mbox
;
3861 int retries
= FW_CMD_HELLO_RETRIES
;
3864 memset(&c
, 0, sizeof(c
));
3865 INIT_CMD(c
, HELLO
, WRITE
);
3866 c
.err_to_clearinit
= htonl(
3867 FW_HELLO_CMD_MASTERDIS_V(master
== MASTER_CANT
) |
3868 FW_HELLO_CMD_MASTERFORCE_V(master
== MASTER_MUST
) |
3869 FW_HELLO_CMD_MBMASTER_V(master
== MASTER_MUST
? mbox
:
3870 FW_HELLO_CMD_MBMASTER_M
) |
3871 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox
) |
3872 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os
) |
3873 FW_HELLO_CMD_CLEARINIT_F
);
3876 * Issue the HELLO command to the firmware. If it's not successful
3877 * but indicates that we got a "busy" or "timeout" condition, retry
3878 * the HELLO until we exhaust our retry limit. If we do exceed our
3879 * retry limit, check to see if the firmware left us any error
3880 * information and report that if so.
3882 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
3884 if ((ret
== -EBUSY
|| ret
== -ETIMEDOUT
) && retries
-- > 0)
3886 if (t4_read_reg(adap
, PCIE_FW_A
) & PCIE_FW_ERR_F
)
3887 t4_report_fw_error(adap
);
3891 v
= ntohl(c
.err_to_clearinit
);
3892 master_mbox
= FW_HELLO_CMD_MBMASTER_G(v
);
3894 if (v
& FW_HELLO_CMD_ERR_F
)
3895 *state
= DEV_STATE_ERR
;
3896 else if (v
& FW_HELLO_CMD_INIT_F
)
3897 *state
= DEV_STATE_INIT
;
3899 *state
= DEV_STATE_UNINIT
;
3903 * If we're not the Master PF then we need to wait around for the
3904 * Master PF Driver to finish setting up the adapter.
3906 * Note that we also do this wait if we're a non-Master-capable PF and
3907 * there is no current Master PF; a Master PF may show up momentarily
3908 * and we wouldn't want to fail pointlessly. (This can happen when an
3909 * OS loads lots of different drivers rapidly at the same time). In
3910 * this case, the Master PF returned by the firmware will be
3911 * PCIE_FW_MASTER_M so the test below will work ...
3913 if ((v
& (FW_HELLO_CMD_ERR_F
|FW_HELLO_CMD_INIT_F
)) == 0 &&
3914 master_mbox
!= mbox
) {
3915 int waiting
= FW_CMD_HELLO_TIMEOUT
;
3918 * Wait for the firmware to either indicate an error or
3919 * initialized state. If we see either of these we bail out
3920 * and report the issue to the caller. If we exhaust the
3921 * "hello timeout" and we haven't exhausted our retries, try
3922 * again. Otherwise bail with a timeout error.
3931 * If neither Error nor Initialialized are indicated
3932 * by the firmware keep waiting till we exaust our
3933 * timeout ... and then retry if we haven't exhausted
3936 pcie_fw
= t4_read_reg(adap
, PCIE_FW_A
);
3937 if (!(pcie_fw
& (PCIE_FW_ERR_F
|PCIE_FW_INIT_F
))) {
3948 * We either have an Error or Initialized condition
3949 * report errors preferentially.
3952 if (pcie_fw
& PCIE_FW_ERR_F
)
3953 *state
= DEV_STATE_ERR
;
3954 else if (pcie_fw
& PCIE_FW_INIT_F
)
3955 *state
= DEV_STATE_INIT
;
3959 * If we arrived before a Master PF was selected and
3960 * there's not a valid Master PF, grab its identity
3963 if (master_mbox
== PCIE_FW_MASTER_M
&&
3964 (pcie_fw
& PCIE_FW_MASTER_VLD_F
))
3965 master_mbox
= PCIE_FW_MASTER_G(pcie_fw
);
3974 * t4_fw_bye - end communication with FW
3975 * @adap: the adapter
3976 * @mbox: mailbox to use for the FW command
3978 * Issues a command to terminate communication with FW.
3980 int t4_fw_bye(struct adapter
*adap
, unsigned int mbox
)
3982 struct fw_bye_cmd c
;
3984 memset(&c
, 0, sizeof(c
));
3985 INIT_CMD(c
, BYE
, WRITE
);
3986 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
3990 * t4_init_cmd - ask FW to initialize the device
3991 * @adap: the adapter
3992 * @mbox: mailbox to use for the FW command
3994 * Issues a command to FW to partially initialize the device. This
3995 * performs initialization that generally doesn't depend on user input.
3997 int t4_early_init(struct adapter
*adap
, unsigned int mbox
)
3999 struct fw_initialize_cmd c
;
4001 memset(&c
, 0, sizeof(c
));
4002 INIT_CMD(c
, INITIALIZE
, WRITE
);
4003 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
4007 * t4_fw_reset - issue a reset to FW
4008 * @adap: the adapter
4009 * @mbox: mailbox to use for the FW command
4010 * @reset: specifies the type of reset to perform
4012 * Issues a reset command of the specified type to FW.
4014 int t4_fw_reset(struct adapter
*adap
, unsigned int mbox
, int reset
)
4016 struct fw_reset_cmd c
;
4018 memset(&c
, 0, sizeof(c
));
4019 INIT_CMD(c
, RESET
, WRITE
);
4020 c
.val
= htonl(reset
);
4021 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
4025 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
4026 * @adap: the adapter
4027 * @mbox: mailbox to use for the FW RESET command (if desired)
4028 * @force: force uP into RESET even if FW RESET command fails
4030 * Issues a RESET command to firmware (if desired) with a HALT indication
4031 * and then puts the microprocessor into RESET state. The RESET command
4032 * will only be issued if a legitimate mailbox is provided (mbox <=
4033 * PCIE_FW_MASTER_M).
4035 * This is generally used in order for the host to safely manipulate the
4036 * adapter without fear of conflicting with whatever the firmware might
4037 * be doing. The only way out of this state is to RESTART the firmware
4040 static int t4_fw_halt(struct adapter
*adap
, unsigned int mbox
, int force
)
4045 * If a legitimate mailbox is provided, issue a RESET command
4046 * with a HALT indication.
4048 if (mbox
<= PCIE_FW_MASTER_M
) {
4049 struct fw_reset_cmd c
;
4051 memset(&c
, 0, sizeof(c
));
4052 INIT_CMD(c
, RESET
, WRITE
);
4053 c
.val
= htonl(PIORST_F
| PIORSTMODE_F
);
4054 c
.halt_pkd
= htonl(FW_RESET_CMD_HALT_F
);
4055 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
4059 * Normally we won't complete the operation if the firmware RESET
4060 * command fails but if our caller insists we'll go ahead and put the
4061 * uP into RESET. This can be useful if the firmware is hung or even
4062 * missing ... We'll have to take the risk of putting the uP into
4063 * RESET without the cooperation of firmware in that case.
4065 * We also force the firmware's HALT flag to be on in case we bypassed
4066 * the firmware RESET command above or we're dealing with old firmware
4067 * which doesn't have the HALT capability. This will serve as a flag
4068 * for the incoming firmware to know that it's coming out of a HALT
4069 * rather than a RESET ... if it's new enough to understand that ...
4071 if (ret
== 0 || force
) {
4072 t4_set_reg_field(adap
, CIM_BOOT_CFG_A
, UPCRST_F
, UPCRST_F
);
4073 t4_set_reg_field(adap
, PCIE_FW_A
, PCIE_FW_HALT_F
,
4078 * And we always return the result of the firmware RESET command
4079 * even when we force the uP into RESET ...
4085 * t4_fw_restart - restart the firmware by taking the uP out of RESET
4086 * @adap: the adapter
4087 * @reset: if we want to do a RESET to restart things
4089 * Restart firmware previously halted by t4_fw_halt(). On successful
4090 * return the previous PF Master remains as the new PF Master and there
4091 * is no need to issue a new HELLO command, etc.
4093 * We do this in two ways:
4095 * 1. If we're dealing with newer firmware we'll simply want to take
4096 * the chip's microprocessor out of RESET. This will cause the
4097 * firmware to start up from its start vector. And then we'll loop
4098 * until the firmware indicates it's started again (PCIE_FW.HALT
4099 * reset to 0) or we timeout.
4101 * 2. If we're dealing with older firmware then we'll need to RESET
4102 * the chip since older firmware won't recognize the PCIE_FW.HALT
4103 * flag and automatically RESET itself on startup.
4105 static int t4_fw_restart(struct adapter
*adap
, unsigned int mbox
, int reset
)
4109 * Since we're directing the RESET instead of the firmware
4110 * doing it automatically, we need to clear the PCIE_FW.HALT
4113 t4_set_reg_field(adap
, PCIE_FW_A
, PCIE_FW_HALT_F
, 0);
4116 * If we've been given a valid mailbox, first try to get the
4117 * firmware to do the RESET. If that works, great and we can
4118 * return success. Otherwise, if we haven't been given a
4119 * valid mailbox or the RESET command failed, fall back to
4120 * hitting the chip with a hammer.
4122 if (mbox
<= PCIE_FW_MASTER_M
) {
4123 t4_set_reg_field(adap
, CIM_BOOT_CFG_A
, UPCRST_F
, 0);
4125 if (t4_fw_reset(adap
, mbox
,
4126 PIORST_F
| PIORSTMODE_F
) == 0)
4130 t4_write_reg(adap
, PL_RST_A
, PIORST_F
| PIORSTMODE_F
);
4135 t4_set_reg_field(adap
, CIM_BOOT_CFG_A
, UPCRST_F
, 0);
4136 for (ms
= 0; ms
< FW_CMD_MAX_TIMEOUT
; ) {
4137 if (!(t4_read_reg(adap
, PCIE_FW_A
) & PCIE_FW_HALT_F
))
4148 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
4149 * @adap: the adapter
4150 * @mbox: mailbox to use for the FW RESET command (if desired)
4151 * @fw_data: the firmware image to write
4153 * @force: force upgrade even if firmware doesn't cooperate
4155 * Perform all of the steps necessary for upgrading an adapter's
4156 * firmware image. Normally this requires the cooperation of the
4157 * existing firmware in order to halt all existing activities
4158 * but if an invalid mailbox token is passed in we skip that step
4159 * (though we'll still put the adapter microprocessor into RESET in
4162 * On successful return the new firmware will have been loaded and
4163 * the adapter will have been fully RESET losing all previous setup
4164 * state. On unsuccessful return the adapter may be completely hosed ...
4165 * positive errno indicates that the adapter is ~probably~ intact, a
4166 * negative errno indicates that things are looking bad ...
4168 int t4_fw_upgrade(struct adapter
*adap
, unsigned int mbox
,
4169 const u8
*fw_data
, unsigned int size
, int force
)
4171 const struct fw_hdr
*fw_hdr
= (const struct fw_hdr
*)fw_data
;
4174 if (!t4_fw_matches_chip(adap
, fw_hdr
))
4177 ret
= t4_fw_halt(adap
, mbox
, force
);
4178 if (ret
< 0 && !force
)
4181 ret
= t4_load_fw(adap
, fw_data
, size
);
4186 * Older versions of the firmware don't understand the new
4187 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
4188 * restart. So for newly loaded older firmware we'll have to do the
4189 * RESET for it so it starts up on a clean slate. We can tell if
4190 * the newly loaded firmware will handle this right by checking
4191 * its header flags to see if it advertises the capability.
4193 reset
= ((ntohl(fw_hdr
->flags
) & FW_HDR_FLAGS_RESET_HALT
) == 0);
4194 return t4_fw_restart(adap
, mbox
, reset
);
4198 * t4_fixup_host_params - fix up host-dependent parameters
4199 * @adap: the adapter
4200 * @page_size: the host's Base Page Size
4201 * @cache_line_size: the host's Cache Line Size
4203 * Various registers in T4 contain values which are dependent on the
4204 * host's Base Page and Cache Line Sizes. This function will fix all of
4205 * those registers with the appropriate values as passed in ...
4207 int t4_fixup_host_params(struct adapter
*adap
, unsigned int page_size
,
4208 unsigned int cache_line_size
)
4210 unsigned int page_shift
= fls(page_size
) - 1;
4211 unsigned int sge_hps
= page_shift
- 10;
4212 unsigned int stat_len
= cache_line_size
> 64 ? 128 : 64;
4213 unsigned int fl_align
= cache_line_size
< 32 ? 32 : cache_line_size
;
4214 unsigned int fl_align_log
= fls(fl_align
) - 1;
4216 t4_write_reg(adap
, SGE_HOST_PAGE_SIZE_A
,
4217 HOSTPAGESIZEPF0_V(sge_hps
) |
4218 HOSTPAGESIZEPF1_V(sge_hps
) |
4219 HOSTPAGESIZEPF2_V(sge_hps
) |
4220 HOSTPAGESIZEPF3_V(sge_hps
) |
4221 HOSTPAGESIZEPF4_V(sge_hps
) |
4222 HOSTPAGESIZEPF5_V(sge_hps
) |
4223 HOSTPAGESIZEPF6_V(sge_hps
) |
4224 HOSTPAGESIZEPF7_V(sge_hps
));
4226 if (is_t4(adap
->params
.chip
)) {
4227 t4_set_reg_field(adap
, SGE_CONTROL_A
,
4228 INGPADBOUNDARY_V(INGPADBOUNDARY_M
) |
4229 EGRSTATUSPAGESIZE_F
,
4230 INGPADBOUNDARY_V(fl_align_log
-
4231 INGPADBOUNDARY_SHIFT_X
) |
4232 EGRSTATUSPAGESIZE_V(stat_len
!= 64));
4234 /* T5 introduced the separation of the Free List Padding and
4235 * Packing Boundaries. Thus, we can select a smaller Padding
4236 * Boundary to avoid uselessly chewing up PCIe Link and Memory
4237 * Bandwidth, and use a Packing Boundary which is large enough
4238 * to avoid false sharing between CPUs, etc.
4240 * For the PCI Link, the smaller the Padding Boundary the
4241 * better. For the Memory Controller, a smaller Padding
4242 * Boundary is better until we cross under the Memory Line
4243 * Size (the minimum unit of transfer to/from Memory). If we
4244 * have a Padding Boundary which is smaller than the Memory
4245 * Line Size, that'll involve a Read-Modify-Write cycle on the
4246 * Memory Controller which is never good. For T5 the smallest
4247 * Padding Boundary which we can select is 32 bytes which is
4248 * larger than any known Memory Controller Line Size so we'll
4251 * T5 has a different interpretation of the "0" value for the
4252 * Packing Boundary. This corresponds to 16 bytes instead of
4253 * the expected 32 bytes. We never have a Packing Boundary
4254 * less than 32 bytes so we can't use that special value but
4255 * on the other hand, if we wanted 32 bytes, the best we can
4256 * really do is 64 bytes.
4258 if (fl_align
<= 32) {
4262 t4_set_reg_field(adap
, SGE_CONTROL_A
,
4263 INGPADBOUNDARY_V(INGPADBOUNDARY_M
) |
4264 EGRSTATUSPAGESIZE_F
,
4265 INGPADBOUNDARY_V(INGPCIEBOUNDARY_32B_X
) |
4266 EGRSTATUSPAGESIZE_V(stat_len
!= 64));
4267 t4_set_reg_field(adap
, SGE_CONTROL2_A
,
4268 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M
),
4269 INGPACKBOUNDARY_V(fl_align_log
-
4270 INGPACKBOUNDARY_SHIFT_X
));
4273 * Adjust various SGE Free List Host Buffer Sizes.
4275 * This is something of a crock since we're using fixed indices into
4276 * the array which are also known by the sge.c code and the T4
4277 * Firmware Configuration File. We need to come up with a much better
4278 * approach to managing this array. For now, the first four entries
4283 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
4284 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
4286 * For the single-MTU buffers in unpacked mode we need to include
4287 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
4288 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
4289 * Padding boundary. All of these are accommodated in the Factory
4290 * Default Firmware Configuration File but we need to adjust it for
4291 * this host's cache line size.
4293 t4_write_reg(adap
, SGE_FL_BUFFER_SIZE0_A
, page_size
);
4294 t4_write_reg(adap
, SGE_FL_BUFFER_SIZE2_A
,
4295 (t4_read_reg(adap
, SGE_FL_BUFFER_SIZE2_A
) + fl_align
-1)
4297 t4_write_reg(adap
, SGE_FL_BUFFER_SIZE3_A
,
4298 (t4_read_reg(adap
, SGE_FL_BUFFER_SIZE3_A
) + fl_align
-1)
4301 t4_write_reg(adap
, ULP_RX_TDDP_PSZ_A
, HPZ0_V(page_shift
- 12));
4307 * t4_fw_initialize - ask FW to initialize the device
4308 * @adap: the adapter
4309 * @mbox: mailbox to use for the FW command
4311 * Issues a command to FW to partially initialize the device. This
4312 * performs initialization that generally doesn't depend on user input.
4314 int t4_fw_initialize(struct adapter
*adap
, unsigned int mbox
)
4316 struct fw_initialize_cmd c
;
4318 memset(&c
, 0, sizeof(c
));
4319 INIT_CMD(c
, INITIALIZE
, WRITE
);
4320 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
4324 * t4_query_params - query FW or device parameters
4325 * @adap: the adapter
4326 * @mbox: mailbox to use for the FW command
4329 * @nparams: the number of parameters
4330 * @params: the parameter names
4331 * @val: the parameter values
4333 * Reads the value of FW or device parameters. Up to 7 parameters can be
4336 int t4_query_params(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
4337 unsigned int vf
, unsigned int nparams
, const u32
*params
,
4341 struct fw_params_cmd c
;
4342 __be32
*p
= &c
.param
[0].mnem
;
4347 memset(&c
, 0, sizeof(c
));
4348 c
.op_to_vfn
= htonl(FW_CMD_OP_V(FW_PARAMS_CMD
) | FW_CMD_REQUEST_F
|
4349 FW_CMD_READ_F
| FW_PARAMS_CMD_PFN_V(pf
) |
4350 FW_PARAMS_CMD_VFN_V(vf
));
4351 c
.retval_len16
= htonl(FW_LEN16(c
));
4352 for (i
= 0; i
< nparams
; i
++, p
+= 2)
4353 *p
= htonl(*params
++);
4355 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
4357 for (i
= 0, p
= &c
.param
[0].val
; i
< nparams
; i
++, p
+= 2)
4363 * t4_set_params_nosleep - sets FW or device parameters
4364 * @adap: the adapter
4365 * @mbox: mailbox to use for the FW command
4368 * @nparams: the number of parameters
4369 * @params: the parameter names
4370 * @val: the parameter values
4372 * Does not ever sleep
4373 * Sets the value of FW or device parameters. Up to 7 parameters can be
4374 * specified at once.
4376 int t4_set_params_nosleep(struct adapter
*adap
, unsigned int mbox
,
4377 unsigned int pf
, unsigned int vf
,
4378 unsigned int nparams
, const u32
*params
,
4381 struct fw_params_cmd c
;
4382 __be32
*p
= &c
.param
[0].mnem
;
4387 memset(&c
, 0, sizeof(c
));
4388 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD
) |
4389 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
4390 FW_PARAMS_CMD_PFN_V(pf
) |
4391 FW_PARAMS_CMD_VFN_V(vf
));
4392 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
4395 *p
++ = cpu_to_be32(*params
++);
4396 *p
++ = cpu_to_be32(*val
++);
4399 return t4_wr_mbox_ns(adap
, mbox
, &c
, sizeof(c
), NULL
);
4403 * t4_set_params - sets FW or device parameters
4404 * @adap: the adapter
4405 * @mbox: mailbox to use for the FW command
4408 * @nparams: the number of parameters
4409 * @params: the parameter names
4410 * @val: the parameter values
4412 * Sets the value of FW or device parameters. Up to 7 parameters can be
4413 * specified at once.
4415 int t4_set_params(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
4416 unsigned int vf
, unsigned int nparams
, const u32
*params
,
4419 struct fw_params_cmd c
;
4420 __be32
*p
= &c
.param
[0].mnem
;
4425 memset(&c
, 0, sizeof(c
));
4426 c
.op_to_vfn
= htonl(FW_CMD_OP_V(FW_PARAMS_CMD
) | FW_CMD_REQUEST_F
|
4427 FW_CMD_WRITE_F
| FW_PARAMS_CMD_PFN_V(pf
) |
4428 FW_PARAMS_CMD_VFN_V(vf
));
4429 c
.retval_len16
= htonl(FW_LEN16(c
));
4431 *p
++ = htonl(*params
++);
4432 *p
++ = htonl(*val
++);
4435 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
4439 * t4_cfg_pfvf - configure PF/VF resource limits
4440 * @adap: the adapter
4441 * @mbox: mailbox to use for the FW command
4442 * @pf: the PF being configured
4443 * @vf: the VF being configured
4444 * @txq: the max number of egress queues
4445 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
4446 * @rxqi: the max number of interrupt-capable ingress queues
4447 * @rxq: the max number of interruptless ingress queues
4448 * @tc: the PCI traffic class
4449 * @vi: the max number of virtual interfaces
4450 * @cmask: the channel access rights mask for the PF/VF
4451 * @pmask: the port access rights mask for the PF/VF
4452 * @nexact: the maximum number of exact MPS filters
4453 * @rcaps: read capabilities
4454 * @wxcaps: write/execute capabilities
4456 * Configures resource limits and capabilities for a physical or virtual
4459 int t4_cfg_pfvf(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
4460 unsigned int vf
, unsigned int txq
, unsigned int txq_eth_ctrl
,
4461 unsigned int rxqi
, unsigned int rxq
, unsigned int tc
,
4462 unsigned int vi
, unsigned int cmask
, unsigned int pmask
,
4463 unsigned int nexact
, unsigned int rcaps
, unsigned int wxcaps
)
4465 struct fw_pfvf_cmd c
;
4467 memset(&c
, 0, sizeof(c
));
4468 c
.op_to_vfn
= htonl(FW_CMD_OP_V(FW_PFVF_CMD
) | FW_CMD_REQUEST_F
|
4469 FW_CMD_WRITE_F
| FW_PFVF_CMD_PFN_V(pf
) |
4470 FW_PFVF_CMD_VFN_V(vf
));
4471 c
.retval_len16
= htonl(FW_LEN16(c
));
4472 c
.niqflint_niq
= htonl(FW_PFVF_CMD_NIQFLINT_V(rxqi
) |
4473 FW_PFVF_CMD_NIQ_V(rxq
));
4474 c
.type_to_neq
= htonl(FW_PFVF_CMD_CMASK_V(cmask
) |
4475 FW_PFVF_CMD_PMASK_V(pmask
) |
4476 FW_PFVF_CMD_NEQ_V(txq
));
4477 c
.tc_to_nexactf
= htonl(FW_PFVF_CMD_TC_V(tc
) | FW_PFVF_CMD_NVI_V(vi
) |
4478 FW_PFVF_CMD_NEXACTF_V(nexact
));
4479 c
.r_caps_to_nethctrl
= htonl(FW_PFVF_CMD_R_CAPS_V(rcaps
) |
4480 FW_PFVF_CMD_WX_CAPS_V(wxcaps
) |
4481 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl
));
4482 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
4486 * t4_alloc_vi - allocate a virtual interface
4487 * @adap: the adapter
4488 * @mbox: mailbox to use for the FW command
4489 * @port: physical port associated with the VI
4490 * @pf: the PF owning the VI
4491 * @vf: the VF owning the VI
4492 * @nmac: number of MAC addresses needed (1 to 5)
4493 * @mac: the MAC addresses of the VI
4494 * @rss_size: size of RSS table slice associated with this VI
4496 * Allocates a virtual interface for the given physical port. If @mac is
4497 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
4498 * @mac should be large enough to hold @nmac Ethernet addresses, they are
4499 * stored consecutively so the space needed is @nmac * 6 bytes.
4500 * Returns a negative error number or the non-negative VI id.
4502 int t4_alloc_vi(struct adapter
*adap
, unsigned int mbox
, unsigned int port
,
4503 unsigned int pf
, unsigned int vf
, unsigned int nmac
, u8
*mac
,
4504 unsigned int *rss_size
)
4509 memset(&c
, 0, sizeof(c
));
4510 c
.op_to_vfn
= htonl(FW_CMD_OP_V(FW_VI_CMD
) | FW_CMD_REQUEST_F
|
4511 FW_CMD_WRITE_F
| FW_CMD_EXEC_F
|
4512 FW_VI_CMD_PFN_V(pf
) | FW_VI_CMD_VFN_V(vf
));
4513 c
.alloc_to_len16
= htonl(FW_VI_CMD_ALLOC_F
| FW_LEN16(c
));
4514 c
.portid_pkd
= FW_VI_CMD_PORTID_V(port
);
4517 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
4522 memcpy(mac
, c
.mac
, sizeof(c
.mac
));
4525 memcpy(mac
+ 24, c
.nmac3
, sizeof(c
.nmac3
));
4527 memcpy(mac
+ 18, c
.nmac2
, sizeof(c
.nmac2
));
4529 memcpy(mac
+ 12, c
.nmac1
, sizeof(c
.nmac1
));
4531 memcpy(mac
+ 6, c
.nmac0
, sizeof(c
.nmac0
));
4535 *rss_size
= FW_VI_CMD_RSSSIZE_G(ntohs(c
.rsssize_pkd
));
4536 return FW_VI_CMD_VIID_G(ntohs(c
.type_viid
));
4540 * t4_set_rxmode - set Rx properties of a virtual interface
4541 * @adap: the adapter
4542 * @mbox: mailbox to use for the FW command
4544 * @mtu: the new MTU or -1
4545 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
4546 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
4547 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
4548 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
4549 * @sleep_ok: if true we may sleep while awaiting command completion
4551 * Sets Rx properties of a virtual interface.
4553 int t4_set_rxmode(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
4554 int mtu
, int promisc
, int all_multi
, int bcast
, int vlanex
,
4557 struct fw_vi_rxmode_cmd c
;
4559 /* convert to FW values */
4561 mtu
= FW_RXMODE_MTU_NO_CHG
;
4563 promisc
= FW_VI_RXMODE_CMD_PROMISCEN_M
;
4565 all_multi
= FW_VI_RXMODE_CMD_ALLMULTIEN_M
;
4567 bcast
= FW_VI_RXMODE_CMD_BROADCASTEN_M
;
4569 vlanex
= FW_VI_RXMODE_CMD_VLANEXEN_M
;
4571 memset(&c
, 0, sizeof(c
));
4572 c
.op_to_viid
= htonl(FW_CMD_OP_V(FW_VI_RXMODE_CMD
) | FW_CMD_REQUEST_F
|
4573 FW_CMD_WRITE_F
| FW_VI_RXMODE_CMD_VIID_V(viid
));
4574 c
.retval_len16
= htonl(FW_LEN16(c
));
4575 c
.mtu_to_vlanexen
= htonl(FW_VI_RXMODE_CMD_MTU_V(mtu
) |
4576 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc
) |
4577 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi
) |
4578 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast
) |
4579 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex
));
4580 return t4_wr_mbox_meat(adap
, mbox
, &c
, sizeof(c
), NULL
, sleep_ok
);
4584 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
4585 * @adap: the adapter
4586 * @mbox: mailbox to use for the FW command
4588 * @free: if true any existing filters for this VI id are first removed
4589 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
4590 * @addr: the MAC address(es)
4591 * @idx: where to store the index of each allocated filter
4592 * @hash: pointer to hash address filter bitmap
4593 * @sleep_ok: call is allowed to sleep
4595 * Allocates an exact-match filter for each of the supplied addresses and
4596 * sets it to the corresponding address. If @idx is not %NULL it should
4597 * have at least @naddr entries, each of which will be set to the index of
4598 * the filter allocated for the corresponding MAC address. If a filter
4599 * could not be allocated for an address its index is set to 0xffff.
4600 * If @hash is not %NULL addresses that fail to allocate an exact filter
4601 * are hashed and update the hash filter bitmap pointed at by @hash.
4603 * Returns a negative error number or the number of filters allocated.
4605 int t4_alloc_mac_filt(struct adapter
*adap
, unsigned int mbox
,
4606 unsigned int viid
, bool free
, unsigned int naddr
,
4607 const u8
**addr
, u16
*idx
, u64
*hash
, bool sleep_ok
)
4610 struct fw_vi_mac_cmd c
;
4611 struct fw_vi_mac_exact
*p
;
4612 unsigned int max_naddr
= is_t4(adap
->params
.chip
) ?
4613 NUM_MPS_CLS_SRAM_L_INSTANCES
:
4614 NUM_MPS_T5_CLS_SRAM_L_INSTANCES
;
4619 memset(&c
, 0, sizeof(c
));
4620 c
.op_to_viid
= htonl(FW_CMD_OP_V(FW_VI_MAC_CMD
) | FW_CMD_REQUEST_F
|
4621 FW_CMD_WRITE_F
| (free
? FW_CMD_EXEC_F
: 0) |
4622 FW_VI_MAC_CMD_VIID_V(viid
));
4623 c
.freemacs_to_len16
= htonl(FW_VI_MAC_CMD_FREEMACS_V(free
) |
4624 FW_CMD_LEN16_V((naddr
+ 2) / 2));
4626 for (i
= 0, p
= c
.u
.exact
; i
< naddr
; i
++, p
++) {
4627 p
->valid_to_idx
= htons(FW_VI_MAC_CMD_VALID_F
|
4628 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC
));
4629 memcpy(p
->macaddr
, addr
[i
], sizeof(p
->macaddr
));
4632 ret
= t4_wr_mbox_meat(adap
, mbox
, &c
, sizeof(c
), &c
, sleep_ok
);
4636 for (i
= 0, p
= c
.u
.exact
; i
< naddr
; i
++, p
++) {
4637 u16 index
= FW_VI_MAC_CMD_IDX_G(ntohs(p
->valid_to_idx
));
4640 idx
[i
] = index
>= max_naddr
? 0xffff : index
;
4641 if (index
< max_naddr
)
4644 *hash
|= (1ULL << hash_mac_addr(addr
[i
]));
4650 * t4_change_mac - modifies the exact-match filter for a MAC address
4651 * @adap: the adapter
4652 * @mbox: mailbox to use for the FW command
4654 * @idx: index of existing filter for old value of MAC address, or -1
4655 * @addr: the new MAC address value
4656 * @persist: whether a new MAC allocation should be persistent
4657 * @add_smt: if true also add the address to the HW SMT
4659 * Modifies an exact-match filter and sets it to the new MAC address.
4660 * Note that in general it is not possible to modify the value of a given
4661 * filter so the generic way to modify an address filter is to free the one
4662 * being used by the old address value and allocate a new filter for the
4663 * new address value. @idx can be -1 if the address is a new addition.
4665 * Returns a negative error number or the index of the filter with the new
4668 int t4_change_mac(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
4669 int idx
, const u8
*addr
, bool persist
, bool add_smt
)
4672 struct fw_vi_mac_cmd c
;
4673 struct fw_vi_mac_exact
*p
= c
.u
.exact
;
4674 unsigned int max_mac_addr
= is_t4(adap
->params
.chip
) ?
4675 NUM_MPS_CLS_SRAM_L_INSTANCES
:
4676 NUM_MPS_T5_CLS_SRAM_L_INSTANCES
;
4678 if (idx
< 0) /* new allocation */
4679 idx
= persist
? FW_VI_MAC_ADD_PERSIST_MAC
: FW_VI_MAC_ADD_MAC
;
4680 mode
= add_smt
? FW_VI_MAC_SMT_AND_MPSTCAM
: FW_VI_MAC_MPS_TCAM_ENTRY
;
4682 memset(&c
, 0, sizeof(c
));
4683 c
.op_to_viid
= htonl(FW_CMD_OP_V(FW_VI_MAC_CMD
) | FW_CMD_REQUEST_F
|
4684 FW_CMD_WRITE_F
| FW_VI_MAC_CMD_VIID_V(viid
));
4685 c
.freemacs_to_len16
= htonl(FW_CMD_LEN16_V(1));
4686 p
->valid_to_idx
= htons(FW_VI_MAC_CMD_VALID_F
|
4687 FW_VI_MAC_CMD_SMAC_RESULT_V(mode
) |
4688 FW_VI_MAC_CMD_IDX_V(idx
));
4689 memcpy(p
->macaddr
, addr
, sizeof(p
->macaddr
));
4691 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
4693 ret
= FW_VI_MAC_CMD_IDX_G(ntohs(p
->valid_to_idx
));
4694 if (ret
>= max_mac_addr
)
4701 * t4_set_addr_hash - program the MAC inexact-match hash filter
4702 * @adap: the adapter
4703 * @mbox: mailbox to use for the FW command
4705 * @ucast: whether the hash filter should also match unicast addresses
4706 * @vec: the value to be written to the hash filter
4707 * @sleep_ok: call is allowed to sleep
4709 * Sets the 64-bit inexact-match hash filter for a virtual interface.
4711 int t4_set_addr_hash(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
4712 bool ucast
, u64 vec
, bool sleep_ok
)
4714 struct fw_vi_mac_cmd c
;
4716 memset(&c
, 0, sizeof(c
));
4717 c
.op_to_viid
= htonl(FW_CMD_OP_V(FW_VI_MAC_CMD
) | FW_CMD_REQUEST_F
|
4718 FW_CMD_WRITE_F
| FW_VI_ENABLE_CMD_VIID_V(viid
));
4719 c
.freemacs_to_len16
= htonl(FW_VI_MAC_CMD_HASHVECEN_F
|
4720 FW_VI_MAC_CMD_HASHUNIEN_V(ucast
) |
4722 c
.u
.hash
.hashvec
= cpu_to_be64(vec
);
4723 return t4_wr_mbox_meat(adap
, mbox
, &c
, sizeof(c
), NULL
, sleep_ok
);
4727 * t4_enable_vi_params - enable/disable a virtual interface
4728 * @adap: the adapter
4729 * @mbox: mailbox to use for the FW command
4731 * @rx_en: 1=enable Rx, 0=disable Rx
4732 * @tx_en: 1=enable Tx, 0=disable Tx
4733 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
4735 * Enables/disables a virtual interface. Note that setting DCB Enable
4736 * only makes sense when enabling a Virtual Interface ...
4738 int t4_enable_vi_params(struct adapter
*adap
, unsigned int mbox
,
4739 unsigned int viid
, bool rx_en
, bool tx_en
, bool dcb_en
)
4741 struct fw_vi_enable_cmd c
;
4743 memset(&c
, 0, sizeof(c
));
4744 c
.op_to_viid
= htonl(FW_CMD_OP_V(FW_VI_ENABLE_CMD
) | FW_CMD_REQUEST_F
|
4745 FW_CMD_EXEC_F
| FW_VI_ENABLE_CMD_VIID_V(viid
));
4747 c
.ien_to_len16
= htonl(FW_VI_ENABLE_CMD_IEN_V(rx_en
) |
4748 FW_VI_ENABLE_CMD_EEN_V(tx_en
) | FW_LEN16(c
) |
4749 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en
));
4750 return t4_wr_mbox_ns(adap
, mbox
, &c
, sizeof(c
), NULL
);
4754 * t4_enable_vi - enable/disable a virtual interface
4755 * @adap: the adapter
4756 * @mbox: mailbox to use for the FW command
4758 * @rx_en: 1=enable Rx, 0=disable Rx
4759 * @tx_en: 1=enable Tx, 0=disable Tx
4761 * Enables/disables a virtual interface.
4763 int t4_enable_vi(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
4764 bool rx_en
, bool tx_en
)
4766 return t4_enable_vi_params(adap
, mbox
, viid
, rx_en
, tx_en
, 0);
4770 * t4_identify_port - identify a VI's port by blinking its LED
4771 * @adap: the adapter
4772 * @mbox: mailbox to use for the FW command
4774 * @nblinks: how many times to blink LED at 2.5 Hz
4776 * Identifies a VI's port by blinking its LED.
4778 int t4_identify_port(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
4779 unsigned int nblinks
)
4781 struct fw_vi_enable_cmd c
;
4783 memset(&c
, 0, sizeof(c
));
4784 c
.op_to_viid
= htonl(FW_CMD_OP_V(FW_VI_ENABLE_CMD
) | FW_CMD_REQUEST_F
|
4785 FW_CMD_EXEC_F
| FW_VI_ENABLE_CMD_VIID_V(viid
));
4786 c
.ien_to_len16
= htonl(FW_VI_ENABLE_CMD_LED_F
| FW_LEN16(c
));
4787 c
.blinkdur
= htons(nblinks
);
4788 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
4792 * t4_iq_free - free an ingress queue and its FLs
4793 * @adap: the adapter
4794 * @mbox: mailbox to use for the FW command
4795 * @pf: the PF owning the queues
4796 * @vf: the VF owning the queues
4797 * @iqtype: the ingress queue type
4798 * @iqid: ingress queue id
4799 * @fl0id: FL0 queue id or 0xffff if no attached FL0
4800 * @fl1id: FL1 queue id or 0xffff if no attached FL1
4802 * Frees an ingress queue and its associated FLs, if any.
4804 int t4_iq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
4805 unsigned int vf
, unsigned int iqtype
, unsigned int iqid
,
4806 unsigned int fl0id
, unsigned int fl1id
)
4810 memset(&c
, 0, sizeof(c
));
4811 c
.op_to_vfn
= htonl(FW_CMD_OP_V(FW_IQ_CMD
) | FW_CMD_REQUEST_F
|
4812 FW_CMD_EXEC_F
| FW_IQ_CMD_PFN_V(pf
) |
4813 FW_IQ_CMD_VFN_V(vf
));
4814 c
.alloc_to_len16
= htonl(FW_IQ_CMD_FREE_F
| FW_LEN16(c
));
4815 c
.type_to_iqandstindex
= htonl(FW_IQ_CMD_TYPE_V(iqtype
));
4816 c
.iqid
= htons(iqid
);
4817 c
.fl0id
= htons(fl0id
);
4818 c
.fl1id
= htons(fl1id
);
4819 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
4823 * t4_eth_eq_free - free an Ethernet egress queue
4824 * @adap: the adapter
4825 * @mbox: mailbox to use for the FW command
4826 * @pf: the PF owning the queue
4827 * @vf: the VF owning the queue
4828 * @eqid: egress queue id
4830 * Frees an Ethernet egress queue.
4832 int t4_eth_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
4833 unsigned int vf
, unsigned int eqid
)
4835 struct fw_eq_eth_cmd c
;
4837 memset(&c
, 0, sizeof(c
));
4838 c
.op_to_vfn
= htonl(FW_CMD_OP_V(FW_EQ_ETH_CMD
) | FW_CMD_REQUEST_F
|
4839 FW_CMD_EXEC_F
| FW_EQ_ETH_CMD_PFN_V(pf
) |
4840 FW_EQ_ETH_CMD_VFN_V(vf
));
4841 c
.alloc_to_len16
= htonl(FW_EQ_ETH_CMD_FREE_F
| FW_LEN16(c
));
4842 c
.eqid_pkd
= htonl(FW_EQ_ETH_CMD_EQID_V(eqid
));
4843 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
4847 * t4_ctrl_eq_free - free a control egress queue
4848 * @adap: the adapter
4849 * @mbox: mailbox to use for the FW command
4850 * @pf: the PF owning the queue
4851 * @vf: the VF owning the queue
4852 * @eqid: egress queue id
4854 * Frees a control egress queue.
4856 int t4_ctrl_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
4857 unsigned int vf
, unsigned int eqid
)
4859 struct fw_eq_ctrl_cmd c
;
4861 memset(&c
, 0, sizeof(c
));
4862 c
.op_to_vfn
= htonl(FW_CMD_OP_V(FW_EQ_CTRL_CMD
) | FW_CMD_REQUEST_F
|
4863 FW_CMD_EXEC_F
| FW_EQ_CTRL_CMD_PFN_V(pf
) |
4864 FW_EQ_CTRL_CMD_VFN_V(vf
));
4865 c
.alloc_to_len16
= htonl(FW_EQ_CTRL_CMD_FREE_F
| FW_LEN16(c
));
4866 c
.cmpliqid_eqid
= htonl(FW_EQ_CTRL_CMD_EQID_V(eqid
));
4867 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
4871 * t4_ofld_eq_free - free an offload egress queue
4872 * @adap: the adapter
4873 * @mbox: mailbox to use for the FW command
4874 * @pf: the PF owning the queue
4875 * @vf: the VF owning the queue
4876 * @eqid: egress queue id
4878 * Frees a control egress queue.
4880 int t4_ofld_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
4881 unsigned int vf
, unsigned int eqid
)
4883 struct fw_eq_ofld_cmd c
;
4885 memset(&c
, 0, sizeof(c
));
4886 c
.op_to_vfn
= htonl(FW_CMD_OP_V(FW_EQ_OFLD_CMD
) | FW_CMD_REQUEST_F
|
4887 FW_CMD_EXEC_F
| FW_EQ_OFLD_CMD_PFN_V(pf
) |
4888 FW_EQ_OFLD_CMD_VFN_V(vf
));
4889 c
.alloc_to_len16
= htonl(FW_EQ_OFLD_CMD_FREE_F
| FW_LEN16(c
));
4890 c
.eqid_pkd
= htonl(FW_EQ_OFLD_CMD_EQID_V(eqid
));
4891 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
4895 * t4_handle_fw_rpl - process a FW reply message
4896 * @adap: the adapter
4897 * @rpl: start of the FW message
4899 * Processes a FW message, such as link state change messages.
4901 int t4_handle_fw_rpl(struct adapter
*adap
, const __be64
*rpl
)
4903 u8 opcode
= *(const u8
*)rpl
;
4905 if (opcode
== FW_PORT_CMD
) { /* link/module state change message */
4906 int speed
= 0, fc
= 0;
4907 const struct fw_port_cmd
*p
= (void *)rpl
;
4908 int chan
= FW_PORT_CMD_PORTID_G(ntohl(p
->op_to_portid
));
4909 int port
= adap
->chan_map
[chan
];
4910 struct port_info
*pi
= adap2pinfo(adap
, port
);
4911 struct link_config
*lc
= &pi
->link_cfg
;
4912 u32 stat
= ntohl(p
->u
.info
.lstatus_to_modtype
);
4913 int link_ok
= (stat
& FW_PORT_CMD_LSTATUS_F
) != 0;
4914 u32 mod
= FW_PORT_CMD_MODTYPE_G(stat
);
4916 if (stat
& FW_PORT_CMD_RXPAUSE_F
)
4918 if (stat
& FW_PORT_CMD_TXPAUSE_F
)
4920 if (stat
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M
))
4922 else if (stat
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G
))
4924 else if (stat
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G
))
4926 else if (stat
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G
))
4929 if (link_ok
!= lc
->link_ok
|| speed
!= lc
->speed
||
4930 fc
!= lc
->fc
) { /* something changed */
4931 lc
->link_ok
= link_ok
;
4934 lc
->supported
= be16_to_cpu(p
->u
.info
.pcap
);
4935 t4_os_link_changed(adap
, port
, link_ok
);
4937 if (mod
!= pi
->mod_type
) {
4939 t4_os_portmod_changed(adap
, port
);
4945 static void get_pci_mode(struct adapter
*adapter
, struct pci_params
*p
)
4949 if (pci_is_pcie(adapter
->pdev
)) {
4950 pcie_capability_read_word(adapter
->pdev
, PCI_EXP_LNKSTA
, &val
);
4951 p
->speed
= val
& PCI_EXP_LNKSTA_CLS
;
4952 p
->width
= (val
& PCI_EXP_LNKSTA_NLW
) >> 4;
4957 * init_link_config - initialize a link's SW state
4958 * @lc: structure holding the link state
4959 * @caps: link capabilities
4961 * Initializes the SW state maintained for each link, including the link's
4962 * capabilities and default speed/flow-control/autonegotiation settings.
4964 static void init_link_config(struct link_config
*lc
, unsigned int caps
)
4966 lc
->supported
= caps
;
4967 lc
->requested_speed
= 0;
4969 lc
->requested_fc
= lc
->fc
= PAUSE_RX
| PAUSE_TX
;
4970 if (lc
->supported
& FW_PORT_CAP_ANEG
) {
4971 lc
->advertising
= lc
->supported
& ADVERT_MASK
;
4972 lc
->autoneg
= AUTONEG_ENABLE
;
4973 lc
->requested_fc
|= PAUSE_AUTONEG
;
4975 lc
->advertising
= 0;
4976 lc
->autoneg
= AUTONEG_DISABLE
;
4980 #define CIM_PF_NOACCESS 0xeeeeeeee
4982 int t4_wait_dev_ready(void __iomem
*regs
)
4986 whoami
= readl(regs
+ PL_WHOAMI_A
);
4987 if (whoami
!= 0xffffffff && whoami
!= CIM_PF_NOACCESS
)
4991 whoami
= readl(regs
+ PL_WHOAMI_A
);
4992 return (whoami
!= 0xffffffff && whoami
!= CIM_PF_NOACCESS
? 0 : -EIO
);
4996 u32 vendor_and_model_id
;
5000 static int get_flash_params(struct adapter
*adap
)
5002 /* Table for non-Numonix supported flash parts. Numonix parts are left
5003 * to the preexisting code. All flash parts have 64KB sectors.
5005 static struct flash_desc supported_flash
[] = {
5006 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
5012 ret
= sf1_write(adap
, 1, 1, 0, SF_RD_ID
);
5014 ret
= sf1_read(adap
, 3, 0, 1, &info
);
5015 t4_write_reg(adap
, SF_OP_A
, 0); /* unlock SF */
5019 for (ret
= 0; ret
< ARRAY_SIZE(supported_flash
); ++ret
)
5020 if (supported_flash
[ret
].vendor_and_model_id
== info
) {
5021 adap
->params
.sf_size
= supported_flash
[ret
].size_mb
;
5022 adap
->params
.sf_nsec
=
5023 adap
->params
.sf_size
/ SF_SEC_SIZE
;
5027 if ((info
& 0xff) != 0x20) /* not a Numonix flash */
5029 info
>>= 16; /* log2 of size */
5030 if (info
>= 0x14 && info
< 0x18)
5031 adap
->params
.sf_nsec
= 1 << (info
- 16);
5032 else if (info
== 0x18)
5033 adap
->params
.sf_nsec
= 64;
5036 adap
->params
.sf_size
= 1 << info
;
5037 adap
->params
.sf_fw_start
=
5038 t4_read_reg(adap
, CIM_BOOT_CFG_A
) & BOOTADDR_M
;
5040 if (adap
->params
.sf_size
< FLASH_MIN_SIZE
)
5041 dev_warn(adap
->pdev_dev
, "WARNING!!! FLASH size %#x < %#x!!!\n",
5042 adap
->params
.sf_size
, FLASH_MIN_SIZE
);
5047 * t4_prep_adapter - prepare SW and HW for operation
5048 * @adapter: the adapter
5049 * @reset: if true perform a HW reset
5051 * Initialize adapter SW state for the various HW modules, set initial
5052 * values for some adapter tunables, take PHYs out of reset, and
5053 * initialize the MDIO interface.
5055 int t4_prep_adapter(struct adapter
*adapter
)
5061 get_pci_mode(adapter
, &adapter
->params
.pci
);
5062 pl_rev
= REV_G(t4_read_reg(adapter
, PL_REV_A
));
5064 ret
= get_flash_params(adapter
);
5066 dev_err(adapter
->pdev_dev
, "error %d identifying flash\n", ret
);
5070 /* Retrieve adapter's device ID
5072 pci_read_config_word(adapter
->pdev
, PCI_DEVICE_ID
, &device_id
);
5073 ver
= device_id
>> 12;
5074 adapter
->params
.chip
= 0;
5077 adapter
->params
.chip
|= CHELSIO_CHIP_CODE(CHELSIO_T4
, pl_rev
);
5080 adapter
->params
.chip
|= CHELSIO_CHIP_CODE(CHELSIO_T5
, pl_rev
);
5083 dev_err(adapter
->pdev_dev
, "Device %d is not supported\n",
5088 adapter
->params
.cim_la_size
= CIMLA_SIZE
;
5089 init_cong_ctrl(adapter
->params
.a_wnd
, adapter
->params
.b_wnd
);
5092 * Default port for debugging in case we can't reach FW.
5094 adapter
->params
.nports
= 1;
5095 adapter
->params
.portvec
= 1;
5096 adapter
->params
.vpd
.cclk
= 50000;
5101 * cxgb4_t4_bar2_sge_qregs - return BAR2 SGE Queue register information
5102 * @adapter: the adapter
5103 * @qid: the Queue ID
5104 * @qtype: the Ingress or Egress type for @qid
5105 * @pbar2_qoffset: BAR2 Queue Offset
5106 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
5108 * Returns the BAR2 SGE Queue Registers information associated with the
5109 * indicated Absolute Queue ID. These are passed back in return value
5110 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
5111 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
5113 * This may return an error which indicates that BAR2 SGE Queue
5114 * registers aren't available. If an error is not returned, then the
5115 * following values are returned:
5117 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
5118 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
5120 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
5121 * require the "Inferred Queue ID" ability may be used. E.g. the
5122 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
5123 * then these "Inferred Queue ID" register may not be used.
5125 int cxgb4_t4_bar2_sge_qregs(struct adapter
*adapter
,
5127 enum t4_bar2_qtype qtype
,
5129 unsigned int *pbar2_qid
)
5131 unsigned int page_shift
, page_size
, qpp_shift
, qpp_mask
;
5132 u64 bar2_page_offset
, bar2_qoffset
;
5133 unsigned int bar2_qid
, bar2_qid_offset
, bar2_qinferred
;
5135 /* T4 doesn't support BAR2 SGE Queue registers.
5137 if (is_t4(adapter
->params
.chip
))
5140 /* Get our SGE Page Size parameters.
5142 page_shift
= adapter
->params
.sge
.hps
+ 10;
5143 page_size
= 1 << page_shift
;
5145 /* Get the right Queues per Page parameters for our Queue.
5147 qpp_shift
= (qtype
== T4_BAR2_QTYPE_EGRESS
5148 ? adapter
->params
.sge
.eq_qpp
5149 : adapter
->params
.sge
.iq_qpp
);
5150 qpp_mask
= (1 << qpp_shift
) - 1;
5152 /* Calculate the basics of the BAR2 SGE Queue register area:
5153 * o The BAR2 page the Queue registers will be in.
5154 * o The BAR2 Queue ID.
5155 * o The BAR2 Queue ID Offset into the BAR2 page.
5157 bar2_page_offset
= ((qid
>> qpp_shift
) << page_shift
);
5158 bar2_qid
= qid
& qpp_mask
;
5159 bar2_qid_offset
= bar2_qid
* SGE_UDB_SIZE
;
5161 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
5162 * hardware will infer the Absolute Queue ID simply from the writes to
5163 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
5164 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
5165 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
5166 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
5167 * from the BAR2 Page and BAR2 Queue ID.
5169 * One important censequence of this is that some BAR2 SGE registers
5170 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
5171 * there. But other registers synthesize the SGE Queue ID purely
5172 * from the writes to the registers -- the Write Combined Doorbell
5173 * Buffer is a good example. These BAR2 SGE Registers are only
5174 * available for those BAR2 SGE Register areas where the SGE Absolute
5175 * Queue ID can be inferred from simple writes.
5177 bar2_qoffset
= bar2_page_offset
;
5178 bar2_qinferred
= (bar2_qid_offset
< page_size
);
5179 if (bar2_qinferred
) {
5180 bar2_qoffset
+= bar2_qid_offset
;
5184 *pbar2_qoffset
= bar2_qoffset
;
5185 *pbar2_qid
= bar2_qid
;
5190 * t4_init_devlog_params - initialize adapter->params.devlog
5191 * @adap: the adapter
5193 * Initialize various fields of the adapter's Firmware Device Log
5194 * Parameters structure.
5196 int t4_init_devlog_params(struct adapter
*adap
)
5198 struct devlog_params
*dparams
= &adap
->params
.devlog
;
5200 unsigned int devlog_meminfo
;
5201 struct fw_devlog_cmd devlog_cmd
;
5204 /* If we're dealing with newer firmware, the Device Log Paramerters
5205 * are stored in a designated register which allows us to access the
5206 * Device Log even if we can't talk to the firmware.
5209 t4_read_reg(adap
, PCIE_FW_REG(PCIE_FW_PF_A
, PCIE_FW_PF_DEVLOG
));
5211 unsigned int nentries
, nentries128
;
5213 dparams
->memtype
= PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams
);
5214 dparams
->start
= PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams
) << 4;
5216 nentries128
= PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams
);
5217 nentries
= (nentries128
+ 1) * 128;
5218 dparams
->size
= nentries
* sizeof(struct fw_devlog_e
);
5223 /* Otherwise, ask the firmware for it's Device Log Parameters.
5225 memset(&devlog_cmd
, 0, sizeof(devlog_cmd
));
5226 devlog_cmd
.op_to_write
= htonl(FW_CMD_OP_V(FW_DEVLOG_CMD
) |
5227 FW_CMD_REQUEST_F
| FW_CMD_READ_F
);
5228 devlog_cmd
.retval_len16
= htonl(FW_LEN16(devlog_cmd
));
5229 ret
= t4_wr_mbox(adap
, adap
->mbox
, &devlog_cmd
, sizeof(devlog_cmd
),
5234 devlog_meminfo
= ntohl(devlog_cmd
.memtype_devlog_memaddr16_devlog
);
5235 dparams
->memtype
= FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo
);
5236 dparams
->start
= FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo
) << 4;
5237 dparams
->size
= ntohl(devlog_cmd
.memsize_devlog
);
5243 * t4_init_sge_params - initialize adap->params.sge
5244 * @adapter: the adapter
5246 * Initialize various fields of the adapter's SGE Parameters structure.
5248 int t4_init_sge_params(struct adapter
*adapter
)
5250 struct sge_params
*sge_params
= &adapter
->params
.sge
;
5252 unsigned int s_hps
, s_qpp
;
5254 /* Extract the SGE Page Size for our PF.
5256 hps
= t4_read_reg(adapter
, SGE_HOST_PAGE_SIZE_A
);
5257 s_hps
= (HOSTPAGESIZEPF0_S
+
5258 (HOSTPAGESIZEPF1_S
- HOSTPAGESIZEPF0_S
) * adapter
->fn
);
5259 sge_params
->hps
= ((hps
>> s_hps
) & HOSTPAGESIZEPF0_M
);
5261 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
5263 s_qpp
= (QUEUESPERPAGEPF0_S
+
5264 (QUEUESPERPAGEPF1_S
- QUEUESPERPAGEPF0_S
) * adapter
->fn
);
5265 qpp
= t4_read_reg(adapter
, SGE_EGRESS_QUEUES_PER_PAGE_PF_A
);
5266 sge_params
->eq_qpp
= ((qpp
>> s_qpp
) & QUEUESPERPAGEPF0_M
);
5267 qpp
= t4_read_reg(adapter
, SGE_INGRESS_QUEUES_PER_PAGE_PF_A
);
5268 sge_params
->iq_qpp
= ((qpp
>> s_qpp
) & QUEUESPERPAGEPF0_M
);
5274 * t4_init_tp_params - initialize adap->params.tp
5275 * @adap: the adapter
5277 * Initialize various fields of the adapter's TP Parameters structure.
5279 int t4_init_tp_params(struct adapter
*adap
)
5284 v
= t4_read_reg(adap
, TP_TIMER_RESOLUTION_A
);
5285 adap
->params
.tp
.tre
= TIMERRESOLUTION_G(v
);
5286 adap
->params
.tp
.dack_re
= DELAYEDACKRESOLUTION_G(v
);
5288 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
5289 for (chan
= 0; chan
< NCHAN
; chan
++)
5290 adap
->params
.tp
.tx_modq
[chan
] = chan
;
5292 /* Cache the adapter's Compressed Filter Mode and global Incress
5295 t4_read_indirect(adap
, TP_PIO_ADDR_A
, TP_PIO_DATA_A
,
5296 &adap
->params
.tp
.vlan_pri_map
, 1,
5298 t4_read_indirect(adap
, TP_PIO_ADDR_A
, TP_PIO_DATA_A
,
5299 &adap
->params
.tp
.ingress_config
, 1,
5300 TP_INGRESS_CONFIG_A
);
5302 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
5303 * shift positions of several elements of the Compressed Filter Tuple
5304 * for this adapter which we need frequently ...
5306 adap
->params
.tp
.vlan_shift
= t4_filter_field_shift(adap
, VLAN_F
);
5307 adap
->params
.tp
.vnic_shift
= t4_filter_field_shift(adap
, VNIC_ID_F
);
5308 adap
->params
.tp
.port_shift
= t4_filter_field_shift(adap
, PORT_F
);
5309 adap
->params
.tp
.protocol_shift
= t4_filter_field_shift(adap
,
5312 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
5313 * represents the presence of an Outer VLAN instead of a VNIC ID.
5315 if ((adap
->params
.tp
.ingress_config
& VNIC_F
) == 0)
5316 adap
->params
.tp
.vnic_shift
= -1;
5322 * t4_filter_field_shift - calculate filter field shift
5323 * @adap: the adapter
5324 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
5326 * Return the shift position of a filter field within the Compressed
5327 * Filter Tuple. The filter field is specified via its selection bit
5328 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
5330 int t4_filter_field_shift(const struct adapter
*adap
, int filter_sel
)
5332 unsigned int filter_mode
= adap
->params
.tp
.vlan_pri_map
;
5336 if ((filter_mode
& filter_sel
) == 0)
5339 for (sel
= 1, field_shift
= 0; sel
< filter_sel
; sel
<<= 1) {
5340 switch (filter_mode
& sel
) {
5342 field_shift
+= FT_FCOE_W
;
5345 field_shift
+= FT_PORT_W
;
5348 field_shift
+= FT_VNIC_ID_W
;
5351 field_shift
+= FT_VLAN_W
;
5354 field_shift
+= FT_TOS_W
;
5357 field_shift
+= FT_PROTOCOL_W
;
5360 field_shift
+= FT_ETHERTYPE_W
;
5363 field_shift
+= FT_MACMATCH_W
;
5366 field_shift
+= FT_MPSHITTYPE_W
;
5368 case FRAGMENTATION_F
:
5369 field_shift
+= FT_FRAGMENTATION_W
;
5376 int t4_port_init(struct adapter
*adap
, int mbox
, int pf
, int vf
)
5380 struct fw_port_cmd c
;
5381 struct fw_rss_vi_config_cmd rvc
;
5383 memset(&c
, 0, sizeof(c
));
5384 memset(&rvc
, 0, sizeof(rvc
));
5386 for_each_port(adap
, i
) {
5387 unsigned int rss_size
;
5388 struct port_info
*p
= adap2pinfo(adap
, i
);
5390 while ((adap
->params
.portvec
& (1 << j
)) == 0)
5393 c
.op_to_portid
= htonl(FW_CMD_OP_V(FW_PORT_CMD
) |
5394 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
5395 FW_PORT_CMD_PORTID_V(j
));
5396 c
.action_to_len16
= htonl(
5397 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO
) |
5399 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
5403 ret
= t4_alloc_vi(adap
, mbox
, j
, pf
, vf
, 1, addr
, &rss_size
);
5410 p
->rss_size
= rss_size
;
5411 memcpy(adap
->port
[i
]->dev_addr
, addr
, ETH_ALEN
);
5412 adap
->port
[i
]->dev_port
= j
;
5414 ret
= ntohl(c
.u
.info
.lstatus_to_modtype
);
5415 p
->mdio_addr
= (ret
& FW_PORT_CMD_MDIOCAP_F
) ?
5416 FW_PORT_CMD_MDIOADDR_G(ret
) : -1;
5417 p
->port_type
= FW_PORT_CMD_PTYPE_G(ret
);
5418 p
->mod_type
= FW_PORT_MOD_TYPE_NA
;
5420 rvc
.op_to_viid
= htonl(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD
) |
5421 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
5422 FW_RSS_VI_CONFIG_CMD_VIID(p
->viid
));
5423 rvc
.retval_len16
= htonl(FW_LEN16(rvc
));
5424 ret
= t4_wr_mbox(adap
, mbox
, &rvc
, sizeof(rvc
), &rvc
);
5427 p
->rss_mode
= ntohl(rvc
.u
.basicvirtual
.defaultq_to_udpen
);
5429 init_link_config(&p
->link_cfg
, ntohs(c
.u
.info
.pcap
));
5436 * t4_read_cimq_cfg - read CIM queue configuration
5437 * @adap: the adapter
5438 * @base: holds the queue base addresses in bytes
5439 * @size: holds the queue sizes in bytes
5440 * @thres: holds the queue full thresholds in bytes
5442 * Returns the current configuration of the CIM queues, starting with
5443 * the IBQs, then the OBQs.
5445 void t4_read_cimq_cfg(struct adapter
*adap
, u16
*base
, u16
*size
, u16
*thres
)
5448 int cim_num_obq
= is_t4(adap
->params
.chip
) ?
5449 CIM_NUM_OBQ
: CIM_NUM_OBQ_T5
;
5451 for (i
= 0; i
< CIM_NUM_IBQ
; i
++) {
5452 t4_write_reg(adap
, CIM_QUEUE_CONFIG_REF_A
, IBQSELECT_F
|
5454 v
= t4_read_reg(adap
, CIM_QUEUE_CONFIG_CTRL_A
);
5455 /* value is in 256-byte units */
5456 *base
++ = CIMQBASE_G(v
) * 256;
5457 *size
++ = CIMQSIZE_G(v
) * 256;
5458 *thres
++ = QUEFULLTHRSH_G(v
) * 8; /* 8-byte unit */
5460 for (i
= 0; i
< cim_num_obq
; i
++) {
5461 t4_write_reg(adap
, CIM_QUEUE_CONFIG_REF_A
, OBQSELECT_F
|
5463 v
= t4_read_reg(adap
, CIM_QUEUE_CONFIG_CTRL_A
);
5464 /* value is in 256-byte units */
5465 *base
++ = CIMQBASE_G(v
) * 256;
5466 *size
++ = CIMQSIZE_G(v
) * 256;
5471 * t4_read_cim_ibq - read the contents of a CIM inbound queue
5472 * @adap: the adapter
5473 * @qid: the queue index
5474 * @data: where to store the queue contents
5475 * @n: capacity of @data in 32-bit words
5477 * Reads the contents of the selected CIM queue starting at address 0 up
5478 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
5479 * error and the number of 32-bit words actually read on success.
5481 int t4_read_cim_ibq(struct adapter
*adap
, unsigned int qid
, u32
*data
, size_t n
)
5483 int i
, err
, attempts
;
5485 const unsigned int nwords
= CIM_IBQ_SIZE
* 4;
5487 if (qid
> 5 || (n
& 3))
5490 addr
= qid
* nwords
;
5494 /* It might take 3-10ms before the IBQ debug read access is allowed.
5495 * Wait for 1 Sec with a delay of 1 usec.
5499 for (i
= 0; i
< n
; i
++, addr
++) {
5500 t4_write_reg(adap
, CIM_IBQ_DBG_CFG_A
, IBQDBGADDR_V(addr
) |
5502 err
= t4_wait_op_done(adap
, CIM_IBQ_DBG_CFG_A
, IBQDBGBUSY_F
, 0,
5506 *data
++ = t4_read_reg(adap
, CIM_IBQ_DBG_DATA_A
);
5508 t4_write_reg(adap
, CIM_IBQ_DBG_CFG_A
, 0);
5513 * t4_read_cim_obq - read the contents of a CIM outbound queue
5514 * @adap: the adapter
5515 * @qid: the queue index
5516 * @data: where to store the queue contents
5517 * @n: capacity of @data in 32-bit words
5519 * Reads the contents of the selected CIM queue starting at address 0 up
5520 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
5521 * error and the number of 32-bit words actually read on success.
5523 int t4_read_cim_obq(struct adapter
*adap
, unsigned int qid
, u32
*data
, size_t n
)
5526 unsigned int addr
, v
, nwords
;
5527 int cim_num_obq
= is_t4(adap
->params
.chip
) ?
5528 CIM_NUM_OBQ
: CIM_NUM_OBQ_T5
;
5530 if ((qid
> (cim_num_obq
- 1)) || (n
& 3))
5533 t4_write_reg(adap
, CIM_QUEUE_CONFIG_REF_A
, OBQSELECT_F
|
5534 QUENUMSELECT_V(qid
));
5535 v
= t4_read_reg(adap
, CIM_QUEUE_CONFIG_CTRL_A
);
5537 addr
= CIMQBASE_G(v
) * 64; /* muliple of 256 -> muliple of 4 */
5538 nwords
= CIMQSIZE_G(v
) * 64; /* same */
5542 for (i
= 0; i
< n
; i
++, addr
++) {
5543 t4_write_reg(adap
, CIM_OBQ_DBG_CFG_A
, OBQDBGADDR_V(addr
) |
5545 err
= t4_wait_op_done(adap
, CIM_OBQ_DBG_CFG_A
, OBQDBGBUSY_F
, 0,
5549 *data
++ = t4_read_reg(adap
, CIM_OBQ_DBG_DATA_A
);
5551 t4_write_reg(adap
, CIM_OBQ_DBG_CFG_A
, 0);
5556 * t4_cim_read - read a block from CIM internal address space
5557 * @adap: the adapter
5558 * @addr: the start address within the CIM address space
5559 * @n: number of words to read
5560 * @valp: where to store the result
5562 * Reads a block of 4-byte words from the CIM intenal address space.
5564 int t4_cim_read(struct adapter
*adap
, unsigned int addr
, unsigned int n
,
5569 if (t4_read_reg(adap
, CIM_HOST_ACC_CTRL_A
) & HOSTBUSY_F
)
5572 for ( ; !ret
&& n
--; addr
+= 4) {
5573 t4_write_reg(adap
, CIM_HOST_ACC_CTRL_A
, addr
);
5574 ret
= t4_wait_op_done(adap
, CIM_HOST_ACC_CTRL_A
, HOSTBUSY_F
,
5577 *valp
++ = t4_read_reg(adap
, CIM_HOST_ACC_DATA_A
);
5583 * t4_cim_write - write a block into CIM internal address space
5584 * @adap: the adapter
5585 * @addr: the start address within the CIM address space
5586 * @n: number of words to write
5587 * @valp: set of values to write
5589 * Writes a block of 4-byte words into the CIM intenal address space.
5591 int t4_cim_write(struct adapter
*adap
, unsigned int addr
, unsigned int n
,
5592 const unsigned int *valp
)
5596 if (t4_read_reg(adap
, CIM_HOST_ACC_CTRL_A
) & HOSTBUSY_F
)
5599 for ( ; !ret
&& n
--; addr
+= 4) {
5600 t4_write_reg(adap
, CIM_HOST_ACC_DATA_A
, *valp
++);
5601 t4_write_reg(adap
, CIM_HOST_ACC_CTRL_A
, addr
| HOSTWRITE_F
);
5602 ret
= t4_wait_op_done(adap
, CIM_HOST_ACC_CTRL_A
, HOSTBUSY_F
,
5608 static int t4_cim_write1(struct adapter
*adap
, unsigned int addr
,
5611 return t4_cim_write(adap
, addr
, 1, &val
);
5615 * t4_cim_read_la - read CIM LA capture buffer
5616 * @adap: the adapter
5617 * @la_buf: where to store the LA data
5618 * @wrptr: the HW write pointer within the capture buffer
5620 * Reads the contents of the CIM LA buffer with the most recent entry at
5621 * the end of the returned data and with the entry at @wrptr first.
5622 * We try to leave the LA in the running state we find it in.
5624 int t4_cim_read_la(struct adapter
*adap
, u32
*la_buf
, unsigned int *wrptr
)
5627 unsigned int cfg
, val
, idx
;
5629 ret
= t4_cim_read(adap
, UP_UP_DBG_LA_CFG_A
, 1, &cfg
);
5633 if (cfg
& UPDBGLAEN_F
) { /* LA is running, freeze it */
5634 ret
= t4_cim_write1(adap
, UP_UP_DBG_LA_CFG_A
, 0);
5639 ret
= t4_cim_read(adap
, UP_UP_DBG_LA_CFG_A
, 1, &val
);
5643 idx
= UPDBGLAWRPTR_G(val
);
5647 for (i
= 0; i
< adap
->params
.cim_la_size
; i
++) {
5648 ret
= t4_cim_write1(adap
, UP_UP_DBG_LA_CFG_A
,
5649 UPDBGLARDPTR_V(idx
) | UPDBGLARDEN_F
);
5652 ret
= t4_cim_read(adap
, UP_UP_DBG_LA_CFG_A
, 1, &val
);
5655 if (val
& UPDBGLARDEN_F
) {
5659 ret
= t4_cim_read(adap
, UP_UP_DBG_LA_DATA_A
, 1, &la_buf
[i
]);
5662 idx
= (idx
+ 1) & UPDBGLARDPTR_M
;
5665 if (cfg
& UPDBGLAEN_F
) {
5666 int r
= t4_cim_write1(adap
, UP_UP_DBG_LA_CFG_A
,
5667 cfg
& ~UPDBGLARDEN_F
);
5675 * t4_tp_read_la - read TP LA capture buffer
5676 * @adap: the adapter
5677 * @la_buf: where to store the LA data
5678 * @wrptr: the HW write pointer within the capture buffer
5680 * Reads the contents of the TP LA buffer with the most recent entry at
5681 * the end of the returned data and with the entry at @wrptr first.
5682 * We leave the LA in the running state we find it in.
5684 void t4_tp_read_la(struct adapter
*adap
, u64
*la_buf
, unsigned int *wrptr
)
5686 bool last_incomplete
;
5687 unsigned int i
, cfg
, val
, idx
;
5689 cfg
= t4_read_reg(adap
, TP_DBG_LA_CONFIG_A
) & 0xffff;
5690 if (cfg
& DBGLAENABLE_F
) /* freeze LA */
5691 t4_write_reg(adap
, TP_DBG_LA_CONFIG_A
,
5692 adap
->params
.tp
.la_mask
| (cfg
^ DBGLAENABLE_F
));
5694 val
= t4_read_reg(adap
, TP_DBG_LA_CONFIG_A
);
5695 idx
= DBGLAWPTR_G(val
);
5696 last_incomplete
= DBGLAMODE_G(val
) >= 2 && (val
& DBGLAWHLF_F
) == 0;
5697 if (last_incomplete
)
5698 idx
= (idx
+ 1) & DBGLARPTR_M
;
5703 val
&= ~DBGLARPTR_V(DBGLARPTR_M
);
5704 val
|= adap
->params
.tp
.la_mask
;
5706 for (i
= 0; i
< TPLA_SIZE
; i
++) {
5707 t4_write_reg(adap
, TP_DBG_LA_CONFIG_A
, DBGLARPTR_V(idx
) | val
);
5708 la_buf
[i
] = t4_read_reg64(adap
, TP_DBG_LA_DATAL_A
);
5709 idx
= (idx
+ 1) & DBGLARPTR_M
;
5712 /* Wipe out last entry if it isn't valid */
5713 if (last_incomplete
)
5714 la_buf
[TPLA_SIZE
- 1] = ~0ULL;
5716 if (cfg
& DBGLAENABLE_F
) /* restore running state */
5717 t4_write_reg(adap
, TP_DBG_LA_CONFIG_A
,
5718 cfg
| adap
->params
.tp
.la_mask
);