2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
38 #include "t4_values.h"
40 #include "t4fw_version.h"
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
57 static int t4_wait_op_done_val(struct adapter
*adapter
, int reg
, u32 mask
,
58 int polarity
, int attempts
, int delay
, u32
*valp
)
61 u32 val
= t4_read_reg(adapter
, reg
);
63 if (!!(val
& mask
) == polarity
) {
75 static inline int t4_wait_op_done(struct adapter
*adapter
, int reg
, u32 mask
,
76 int polarity
, int attempts
, int delay
)
78 return t4_wait_op_done_val(adapter
, reg
, mask
, polarity
, attempts
,
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
89 * Sets a register field specified by the supplied mask to the
92 void t4_set_reg_field(struct adapter
*adapter
, unsigned int addr
, u32 mask
,
95 u32 v
= t4_read_reg(adapter
, addr
) & ~mask
;
97 t4_write_reg(adapter
, addr
, v
| val
);
98 (void) t4_read_reg(adapter
, addr
); /* flush */
102 * t4_read_indirect - read indirectly addressed registers
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
110 * Reads registers that are accessed indirectly through an address/data
113 void t4_read_indirect(struct adapter
*adap
, unsigned int addr_reg
,
114 unsigned int data_reg
, u32
*vals
,
115 unsigned int nregs
, unsigned int start_idx
)
118 t4_write_reg(adap
, addr_reg
, start_idx
);
119 *vals
++ = t4_read_reg(adap
, data_reg
);
125 * t4_write_indirect - write indirectly addressed registers
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
136 void t4_write_indirect(struct adapter
*adap
, unsigned int addr_reg
,
137 unsigned int data_reg
, const u32
*vals
,
138 unsigned int nregs
, unsigned int start_idx
)
141 t4_write_reg(adap
, addr_reg
, start_idx
++);
142 t4_write_reg(adap
, data_reg
, *vals
++);
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
152 void t4_hw_pci_read_cfg4(struct adapter
*adap
, int reg
, u32
*val
)
154 u32 req
= FUNCTION_V(adap
->pf
) | REGISTER_V(reg
);
156 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) <= CHELSIO_T5
)
161 if (is_t4(adap
->params
.chip
))
164 t4_write_reg(adap
, PCIE_CFG_SPACE_REQ_A
, req
);
165 *val
= t4_read_reg(adap
, PCIE_CFG_SPACE_DATA_A
);
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
172 t4_write_reg(adap
, PCIE_CFG_SPACE_REQ_A
, 0);
176 * t4_report_fw_error - report firmware error
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
183 static void t4_report_fw_error(struct adapter
*adap
)
185 static const char *const reason
[] = {
186 "Crash", /* PCIE_FW_EVAL_CRASH */
187 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
188 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
189 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
190 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
191 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
192 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
193 "Reserved", /* reserved */
197 pcie_fw
= t4_read_reg(adap
, PCIE_FW_A
);
198 if (pcie_fw
& PCIE_FW_ERR_F
) {
199 dev_err(adap
->pdev_dev
, "Firmware reports adapter error: %s\n",
200 reason
[PCIE_FW_EVAL_G(pcie_fw
)]);
201 adap
->flags
&= ~FW_OK
;
206 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
208 static void get_mbox_rpl(struct adapter
*adap
, __be64
*rpl
, int nflit
,
211 for ( ; nflit
; nflit
--, mbox_addr
+= 8)
212 *rpl
++ = cpu_to_be64(t4_read_reg64(adap
, mbox_addr
));
216 * Handle a FW assertion reported in a mailbox.
218 static void fw_asrt(struct adapter
*adap
, u32 mbox_addr
)
220 struct fw_debug_cmd asrt
;
222 get_mbox_rpl(adap
, (__be64
*)&asrt
, sizeof(asrt
) / 8, mbox_addr
);
223 dev_alert(adap
->pdev_dev
,
224 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
225 asrt
.u
.assert.filename_0_7
, be32_to_cpu(asrt
.u
.assert.line
),
226 be32_to_cpu(asrt
.u
.assert.x
), be32_to_cpu(asrt
.u
.assert.y
));
230 * t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
231 * @adapter: the adapter
232 * @cmd: the Firmware Mailbox Command or Reply
233 * @size: command length in bytes
234 * @access: the time (ms) needed to access the Firmware Mailbox
235 * @execute: the time (ms) the command spent being executed
237 static void t4_record_mbox(struct adapter
*adapter
,
238 const __be64
*cmd
, unsigned int size
,
239 int access
, int execute
)
241 struct mbox_cmd_log
*log
= adapter
->mbox_log
;
242 struct mbox_cmd
*entry
;
245 entry
= mbox_cmd_log_entry(log
, log
->cursor
++);
246 if (log
->cursor
== log
->size
)
249 for (i
= 0; i
< size
/ 8; i
++)
250 entry
->cmd
[i
] = be64_to_cpu(cmd
[i
]);
251 while (i
< MBOX_LEN
/ 8)
253 entry
->timestamp
= jiffies
;
254 entry
->seqno
= log
->seqno
++;
255 entry
->access
= access
;
256 entry
->execute
= execute
;
260 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
262 * @mbox: index of the mailbox to use
263 * @cmd: the command to write
264 * @size: command length in bytes
265 * @rpl: where to optionally store the reply
266 * @sleep_ok: if true we may sleep while awaiting command completion
267 * @timeout: time to wait for command to finish before timing out
269 * Sends the given command to FW through the selected mailbox and waits
270 * for the FW to execute the command. If @rpl is not %NULL it is used to
271 * store the FW's reply to the command. The command and its optional
272 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
273 * to respond. @sleep_ok determines whether we may sleep while awaiting
274 * the response. If sleeping is allowed we use progressive backoff
277 * The return value is 0 on success or a negative errno on failure. A
278 * failure can happen either because we are not able to execute the
279 * command or FW executes it but signals an error. In the latter case
280 * the return value is the error code indicated by FW (negated).
282 int t4_wr_mbox_meat_timeout(struct adapter
*adap
, int mbox
, const void *cmd
,
283 int size
, void *rpl
, bool sleep_ok
, int timeout
)
285 static const int delay
[] = {
286 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
289 struct mbox_list entry
;
294 int i
, ms
, delay_idx
, ret
;
295 const __be64
*p
= cmd
;
296 u32 data_reg
= PF_REG(mbox
, CIM_PF_MAILBOX_DATA_A
);
297 u32 ctl_reg
= PF_REG(mbox
, CIM_PF_MAILBOX_CTRL_A
);
298 __be64 cmd_rpl
[MBOX_LEN
/ 8];
301 if ((size
& 15) || size
> MBOX_LEN
)
305 * If the device is off-line, as in EEH, commands will time out.
306 * Fail them early so we don't waste time waiting.
308 if (adap
->pdev
->error_state
!= pci_channel_io_normal
)
311 /* If we have a negative timeout, that implies that we can't sleep. */
317 /* Queue ourselves onto the mailbox access list. When our entry is at
318 * the front of the list, we have rights to access the mailbox. So we
319 * wait [for a while] till we're at the front [or bail out with an
322 spin_lock_bh(&adap
->mbox_lock
);
323 list_add_tail(&entry
.list
, &adap
->mlist
.list
);
324 spin_unlock_bh(&adap
->mbox_lock
);
329 for (i
= 0; ; i
+= ms
) {
330 /* If we've waited too long, return a busy indication. This
331 * really ought to be based on our initial position in the
332 * mailbox access list but this is a start. We very rearely
333 * contend on access to the mailbox ...
335 pcie_fw
= t4_read_reg(adap
, PCIE_FW_A
);
336 if (i
> FW_CMD_MAX_TIMEOUT
|| (pcie_fw
& PCIE_FW_ERR_F
)) {
337 spin_lock_bh(&adap
->mbox_lock
);
338 list_del(&entry
.list
);
339 spin_unlock_bh(&adap
->mbox_lock
);
340 ret
= (pcie_fw
& PCIE_FW_ERR_F
) ? -ENXIO
: -EBUSY
;
341 t4_record_mbox(adap
, cmd
, size
, access
, ret
);
345 /* If we're at the head, break out and start the mailbox
348 if (list_first_entry(&adap
->mlist
.list
, struct mbox_list
,
352 /* Delay for a bit before checking again ... */
354 ms
= delay
[delay_idx
]; /* last element may repeat */
355 if (delay_idx
< ARRAY_SIZE(delay
) - 1)
363 /* Loop trying to get ownership of the mailbox. Return an error
364 * if we can't gain ownership.
366 v
= MBOWNER_G(t4_read_reg(adap
, ctl_reg
));
367 for (i
= 0; v
== MBOX_OWNER_NONE
&& i
< 3; i
++)
368 v
= MBOWNER_G(t4_read_reg(adap
, ctl_reg
));
369 if (v
!= MBOX_OWNER_DRV
) {
370 spin_lock_bh(&adap
->mbox_lock
);
371 list_del(&entry
.list
);
372 spin_unlock_bh(&adap
->mbox_lock
);
373 ret
= (v
== MBOX_OWNER_FW
) ? -EBUSY
: -ETIMEDOUT
;
374 t4_record_mbox(adap
, cmd
, size
, access
, ret
);
378 /* Copy in the new mailbox command and send it on its way ... */
379 t4_record_mbox(adap
, cmd
, size
, access
, 0);
380 for (i
= 0; i
< size
; i
+= 8)
381 t4_write_reg64(adap
, data_reg
+ i
, be64_to_cpu(*p
++));
383 t4_write_reg(adap
, ctl_reg
, MBMSGVALID_F
| MBOWNER_V(MBOX_OWNER_FW
));
384 t4_read_reg(adap
, ctl_reg
); /* flush write */
390 !((pcie_fw
= t4_read_reg(adap
, PCIE_FW_A
)) & PCIE_FW_ERR_F
) &&
394 ms
= delay
[delay_idx
]; /* last element may repeat */
395 if (delay_idx
< ARRAY_SIZE(delay
) - 1)
401 v
= t4_read_reg(adap
, ctl_reg
);
402 if (MBOWNER_G(v
) == MBOX_OWNER_DRV
) {
403 if (!(v
& MBMSGVALID_F
)) {
404 t4_write_reg(adap
, ctl_reg
, 0);
408 get_mbox_rpl(adap
, cmd_rpl
, MBOX_LEN
/ 8, data_reg
);
409 res
= be64_to_cpu(cmd_rpl
[0]);
411 if (FW_CMD_OP_G(res
>> 32) == FW_DEBUG_CMD
) {
412 fw_asrt(adap
, data_reg
);
413 res
= FW_CMD_RETVAL_V(EIO
);
415 memcpy(rpl
, cmd_rpl
, size
);
418 t4_write_reg(adap
, ctl_reg
, 0);
421 t4_record_mbox(adap
, cmd_rpl
,
422 MBOX_LEN
, access
, execute
);
423 spin_lock_bh(&adap
->mbox_lock
);
424 list_del(&entry
.list
);
425 spin_unlock_bh(&adap
->mbox_lock
);
426 return -FW_CMD_RETVAL_G((int)res
);
430 ret
= (pcie_fw
& PCIE_FW_ERR_F
) ? -ENXIO
: -ETIMEDOUT
;
431 t4_record_mbox(adap
, cmd
, size
, access
, ret
);
432 dev_err(adap
->pdev_dev
, "command %#x in mailbox %d timed out\n",
433 *(const u8
*)cmd
, mbox
);
434 t4_report_fw_error(adap
);
435 spin_lock_bh(&adap
->mbox_lock
);
436 list_del(&entry
.list
);
437 spin_unlock_bh(&adap
->mbox_lock
);
442 int t4_wr_mbox_meat(struct adapter
*adap
, int mbox
, const void *cmd
, int size
,
443 void *rpl
, bool sleep_ok
)
445 return t4_wr_mbox_meat_timeout(adap
, mbox
, cmd
, size
, rpl
, sleep_ok
,
449 static int t4_edc_err_read(struct adapter
*adap
, int idx
)
451 u32 edc_ecc_err_addr_reg
;
454 if (is_t4(adap
->params
.chip
)) {
455 CH_WARN(adap
, "%s: T4 NOT supported.\n", __func__
);
458 if (idx
!= 0 && idx
!= 1) {
459 CH_WARN(adap
, "%s: idx %d NOT supported.\n", __func__
, idx
);
463 edc_ecc_err_addr_reg
= EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A
, idx
);
464 rdata_reg
= EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A
, idx
);
467 "edc%d err addr 0x%x: 0x%x.\n",
468 idx
, edc_ecc_err_addr_reg
,
469 t4_read_reg(adap
, edc_ecc_err_addr_reg
));
471 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
473 (unsigned long long)t4_read_reg64(adap
, rdata_reg
),
474 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 8),
475 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 16),
476 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 24),
477 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 32),
478 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 40),
479 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 48),
480 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 56),
481 (unsigned long long)t4_read_reg64(adap
, rdata_reg
+ 64));
487 * t4_memory_rw_init - Get memory window relative offset, base, and size.
489 * @win: PCI-E Memory Window to use
490 * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_HMA or MEM_MC
491 * @mem_off: memory relative offset with respect to @mtype.
492 * @mem_base: configured memory base address.
493 * @mem_aperture: configured memory window aperture.
495 * Get the configured memory window's relative offset, base, and size.
497 int t4_memory_rw_init(struct adapter
*adap
, int win
, int mtype
, u32
*mem_off
,
498 u32
*mem_base
, u32
*mem_aperture
)
500 u32 edc_size
, mc_size
, mem_reg
;
502 /* Offset into the region of memory which is being accessed
505 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
506 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
509 edc_size
= EDRAM0_SIZE_G(t4_read_reg(adap
, MA_EDRAM0_BAR_A
));
510 if (mtype
== MEM_HMA
) {
511 *mem_off
= 2 * (edc_size
* 1024 * 1024);
512 } else if (mtype
!= MEM_MC1
) {
513 *mem_off
= (mtype
* (edc_size
* 1024 * 1024));
515 mc_size
= EXT_MEM0_SIZE_G(t4_read_reg(adap
,
516 MA_EXT_MEMORY0_BAR_A
));
517 *mem_off
= (MEM_MC0
* edc_size
+ mc_size
) * 1024 * 1024;
520 /* Each PCI-E Memory Window is programmed with a window size -- or
521 * "aperture" -- which controls the granularity of its mapping onto
522 * adapter memory. We need to grab that aperture in order to know
523 * how to use the specified window. The window is also programmed
524 * with the base address of the Memory Window in BAR0's address
525 * space. For T4 this is an absolute PCI-E Bus Address. For T5
526 * the address is relative to BAR0.
528 mem_reg
= t4_read_reg(adap
,
529 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A
,
531 /* a dead adapter will return 0xffffffff for PIO reads */
532 if (mem_reg
== 0xffffffff)
535 *mem_aperture
= 1 << (WINDOW_G(mem_reg
) + WINDOW_SHIFT_X
);
536 *mem_base
= PCIEOFST_G(mem_reg
) << PCIEOFST_SHIFT_X
;
537 if (is_t4(adap
->params
.chip
))
538 *mem_base
-= adap
->t4_bar0
;
544 * t4_memory_update_win - Move memory window to specified address.
546 * @win: PCI-E Memory Window to use
547 * @addr: location to move.
549 * Move memory window to specified address.
551 void t4_memory_update_win(struct adapter
*adap
, int win
, u32 addr
)
554 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A
, win
),
556 /* Read it back to ensure that changes propagate before we
557 * attempt to use the new value.
560 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A
, win
));
564 * t4_memory_rw_residual - Read/Write residual data.
566 * @off: relative offset within residual to start read/write.
567 * @addr: address within indicated memory type.
568 * @buf: host memory buffer
569 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
571 * Read/Write residual data less than 32-bits.
573 void t4_memory_rw_residual(struct adapter
*adap
, u32 off
, u32 addr
, u8
*buf
,
583 if (dir
== T4_MEMORY_READ
) {
584 last
.word
= le32_to_cpu((__force __le32
)
585 t4_read_reg(adap
, addr
));
586 for (bp
= (unsigned char *)buf
, i
= off
; i
< 4; i
++)
587 bp
[i
] = last
.byte
[i
];
590 for (i
= off
; i
< 4; i
++)
592 t4_write_reg(adap
, addr
,
593 (__force u32
)cpu_to_le32(last
.word
));
598 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
600 * @win: PCI-E Memory Window to use
601 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
602 * @addr: address within indicated memory type
603 * @len: amount of memory to transfer
604 * @hbuf: host memory buffer
605 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
607 * Reads/writes an [almost] arbitrary memory region in the firmware: the
608 * firmware memory address and host buffer must be aligned on 32-bit
609 * boudaries; the length may be arbitrary. The memory is transferred as
610 * a raw byte sequence from/to the firmware's memory. If this memory
611 * contains data structures which contain multi-byte integers, it's the
612 * caller's responsibility to perform appropriate byte order conversions.
614 int t4_memory_rw(struct adapter
*adap
, int win
, int mtype
, u32 addr
,
615 u32 len
, void *hbuf
, int dir
)
617 u32 pos
, offset
, resid
, memoffset
;
618 u32 win_pf
, mem_aperture
, mem_base
;
622 /* Argument sanity checks ...
624 if (addr
& 0x3 || (uintptr_t)hbuf
& 0x3)
628 /* It's convenient to be able to handle lengths which aren't a
629 * multiple of 32-bits because we often end up transferring files to
630 * the firmware. So we'll handle that by normalizing the length here
631 * and then handling any residual transfer at the end.
636 ret
= t4_memory_rw_init(adap
, win
, mtype
, &memoffset
, &mem_base
,
641 /* Determine the PCIE_MEM_ACCESS_OFFSET */
642 addr
= addr
+ memoffset
;
644 win_pf
= is_t4(adap
->params
.chip
) ? 0 : PFNUM_V(adap
->pf
);
646 /* Calculate our initial PCI-E Memory Window Position and Offset into
649 pos
= addr
& ~(mem_aperture
- 1);
652 /* Set up initial PCI-E Memory Window to cover the start of our
655 t4_memory_update_win(adap
, win
, pos
| win_pf
);
657 /* Transfer data to/from the adapter as long as there's an integral
658 * number of 32-bit transfers to complete.
660 * A note on Endianness issues:
662 * The "register" reads and writes below from/to the PCI-E Memory
663 * Window invoke the standard adapter Big-Endian to PCI-E Link
664 * Little-Endian "swizzel." As a result, if we have the following
665 * data in adapter memory:
667 * Memory: ... | b0 | b1 | b2 | b3 | ...
668 * Address: i+0 i+1 i+2 i+3
670 * Then a read of the adapter memory via the PCI-E Memory Window
675 * [ b3 | b2 | b1 | b0 ]
677 * If this value is stored into local memory on a Little-Endian system
678 * it will show up correctly in local memory as:
680 * ( ..., b0, b1, b2, b3, ... )
682 * But on a Big-Endian system, the store will show up in memory
683 * incorrectly swizzled as:
685 * ( ..., b3, b2, b1, b0, ... )
687 * So we need to account for this in the reads and writes to the
688 * PCI-E Memory Window below by undoing the register read/write
692 if (dir
== T4_MEMORY_READ
)
693 *buf
++ = le32_to_cpu((__force __le32
)t4_read_reg(adap
,
696 t4_write_reg(adap
, mem_base
+ offset
,
697 (__force u32
)cpu_to_le32(*buf
++));
698 offset
+= sizeof(__be32
);
699 len
-= sizeof(__be32
);
701 /* If we've reached the end of our current window aperture,
702 * move the PCI-E Memory Window on to the next. Note that
703 * doing this here after "len" may be 0 allows us to set up
704 * the PCI-E Memory Window for a possible final residual
707 if (offset
== mem_aperture
) {
710 t4_memory_update_win(adap
, win
, pos
| win_pf
);
714 /* If the original transfer had a length which wasn't a multiple of
715 * 32-bits, now's where we need to finish off the transfer of the
716 * residual amount. The PCI-E Memory Window has already been moved
717 * above (if necessary) to cover this final transfer.
720 t4_memory_rw_residual(adap
, resid
, mem_base
+ offset
,
726 /* Return the specified PCI-E Configuration Space register from our Physical
727 * Function. We try first via a Firmware LDST Command since we prefer to let
728 * the firmware own all of these registers, but if that fails we go for it
729 * directly ourselves.
731 u32
t4_read_pcie_cfg4(struct adapter
*adap
, int reg
)
733 u32 val
, ldst_addrspace
;
735 /* If fw_attach != 0, construct and send the Firmware LDST Command to
736 * retrieve the specified PCI-E Configuration Space register.
738 struct fw_ldst_cmd ldst_cmd
;
741 memset(&ldst_cmd
, 0, sizeof(ldst_cmd
));
742 ldst_addrspace
= FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE
);
743 ldst_cmd
.op_to_addrspace
= cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
747 ldst_cmd
.cycles_to_len16
= cpu_to_be32(FW_LEN16(ldst_cmd
));
748 ldst_cmd
.u
.pcie
.select_naccess
= FW_LDST_CMD_NACCESS_V(1);
749 ldst_cmd
.u
.pcie
.ctrl_to_fn
=
750 (FW_LDST_CMD_LC_F
| FW_LDST_CMD_FN_V(adap
->pf
));
751 ldst_cmd
.u
.pcie
.r
= reg
;
753 /* If the LDST Command succeeds, return the result, otherwise
754 * fall through to reading it directly ourselves ...
756 ret
= t4_wr_mbox(adap
, adap
->mbox
, &ldst_cmd
, sizeof(ldst_cmd
),
759 val
= be32_to_cpu(ldst_cmd
.u
.pcie
.data
[0]);
761 /* Read the desired Configuration Space register via the PCI-E
762 * Backdoor mechanism.
764 t4_hw_pci_read_cfg4(adap
, reg
, &val
);
768 /* Get the window based on base passed to it.
769 * Window aperture is currently unhandled, but there is no use case for it
772 static u32
t4_get_window(struct adapter
*adap
, u32 pci_base
, u64 pci_mask
,
777 if (is_t4(adap
->params
.chip
)) {
780 /* Truncation intentional: we only read the bottom 32-bits of
781 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
782 * mechanism to read BAR0 instead of using
783 * pci_resource_start() because we could be operating from
784 * within a Virtual Machine which is trapping our accesses to
785 * our Configuration Space and we need to set up the PCI-E
786 * Memory Window decoders with the actual addresses which will
787 * be coming across the PCI-E link.
789 bar0
= t4_read_pcie_cfg4(adap
, pci_base
);
791 adap
->t4_bar0
= bar0
;
793 ret
= bar0
+ memwin_base
;
795 /* For T5, only relative offset inside the PCIe BAR is passed */
801 /* Get the default utility window (win0) used by everyone */
802 u32
t4_get_util_window(struct adapter
*adap
)
804 return t4_get_window(adap
, PCI_BASE_ADDRESS_0
,
805 PCI_BASE_ADDRESS_MEM_MASK
, MEMWIN0_BASE
);
808 /* Set up memory window for accessing adapter memory ranges. (Read
809 * back MA register to ensure that changes propagate before we attempt
810 * to use the new values.)
812 void t4_setup_memwin(struct adapter
*adap
, u32 memwin_base
, u32 window
)
815 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A
, window
),
816 memwin_base
| BIR_V(0) |
817 WINDOW_V(ilog2(MEMWIN0_APERTURE
) - WINDOW_SHIFT_X
));
819 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A
, window
));
823 * t4_get_regs_len - return the size of the chips register set
824 * @adapter: the adapter
826 * Returns the size of the chip's BAR0 register space.
828 unsigned int t4_get_regs_len(struct adapter
*adapter
)
830 unsigned int chip_version
= CHELSIO_CHIP_VERSION(adapter
->params
.chip
);
832 switch (chip_version
) {
834 return T4_REGMAP_SIZE
;
838 return T5_REGMAP_SIZE
;
841 dev_err(adapter
->pdev_dev
,
842 "Unsupported chip version %d\n", chip_version
);
847 * t4_get_regs - read chip registers into provided buffer
849 * @buf: register buffer
850 * @buf_size: size (in bytes) of register buffer
852 * If the provided register buffer isn't large enough for the chip's
853 * full register range, the register dump will be truncated to the
854 * register buffer's size.
856 void t4_get_regs(struct adapter
*adap
, void *buf
, size_t buf_size
)
858 static const unsigned int t4_reg_ranges
[] = {
1317 static const unsigned int t5_reg_ranges
[] = {
2084 static const unsigned int t6_reg_ranges
[] = {
2645 u32
*buf_end
= (u32
*)((char *)buf
+ buf_size
);
2646 const unsigned int *reg_ranges
;
2647 int reg_ranges_size
, range
;
2648 unsigned int chip_version
= CHELSIO_CHIP_VERSION(adap
->params
.chip
);
2650 /* Select the right set of register ranges to dump depending on the
2651 * adapter chip type.
2653 switch (chip_version
) {
2655 reg_ranges
= t4_reg_ranges
;
2656 reg_ranges_size
= ARRAY_SIZE(t4_reg_ranges
);
2660 reg_ranges
= t5_reg_ranges
;
2661 reg_ranges_size
= ARRAY_SIZE(t5_reg_ranges
);
2665 reg_ranges
= t6_reg_ranges
;
2666 reg_ranges_size
= ARRAY_SIZE(t6_reg_ranges
);
2670 dev_err(adap
->pdev_dev
,
2671 "Unsupported chip version %d\n", chip_version
);
2675 /* Clear the register buffer and insert the appropriate register
2676 * values selected by the above register ranges.
2678 memset(buf
, 0, buf_size
);
2679 for (range
= 0; range
< reg_ranges_size
; range
+= 2) {
2680 unsigned int reg
= reg_ranges
[range
];
2681 unsigned int last_reg
= reg_ranges
[range
+ 1];
2682 u32
*bufp
= (u32
*)((char *)buf
+ reg
);
2684 /* Iterate across the register range filling in the register
2685 * buffer but don't write past the end of the register buffer.
2687 while (reg
<= last_reg
&& bufp
< buf_end
) {
2688 *bufp
++ = t4_read_reg(adap
, reg
);
2694 #define EEPROM_STAT_ADDR 0x7bfc
2695 #define VPD_BASE 0x400
2696 #define VPD_BASE_OLD 0
2697 #define VPD_LEN 1024
2698 #define CHELSIO_VPD_UNIQUE_ID 0x82
2701 * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2702 * @phys_addr: the physical EEPROM address
2703 * @fn: the PCI function number
2704 * @sz: size of function-specific area
2706 * Translate a physical EEPROM address to virtual. The first 1K is
2707 * accessed through virtual addresses starting at 31K, the rest is
2708 * accessed through virtual addresses starting at 0.
2710 * The mapping is as follows:
2711 * [0..1K) -> [31K..32K)
2712 * [1K..1K+A) -> [31K-A..31K)
2713 * [1K+A..ES) -> [0..ES-A-1K)
2715 * where A = @fn * @sz, and ES = EEPROM size.
2717 int t4_eeprom_ptov(unsigned int phys_addr
, unsigned int fn
, unsigned int sz
)
2720 if (phys_addr
< 1024)
2721 return phys_addr
+ (31 << 10);
2722 if (phys_addr
< 1024 + fn
)
2723 return 31744 - fn
+ phys_addr
- 1024;
2724 if (phys_addr
< EEPROMSIZE
)
2725 return phys_addr
- 1024 - fn
;
2730 * t4_seeprom_wp - enable/disable EEPROM write protection
2731 * @adapter: the adapter
2732 * @enable: whether to enable or disable write protection
2734 * Enables or disables write protection on the serial EEPROM.
2736 int t4_seeprom_wp(struct adapter
*adapter
, bool enable
)
2738 unsigned int v
= enable
? 0xc : 0;
2739 int ret
= pci_write_vpd(adapter
->pdev
, EEPROM_STAT_ADDR
, 4, &v
);
2740 return ret
< 0 ? ret
: 0;
2744 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2745 * @adapter: adapter to read
2746 * @p: where to store the parameters
2748 * Reads card parameters stored in VPD EEPROM.
2750 int t4_get_raw_vpd_params(struct adapter
*adapter
, struct vpd_params
*p
)
2752 int i
, ret
= 0, addr
;
2755 unsigned int vpdr_len
, kw_offset
, id_len
;
2757 vpd
= vmalloc(VPD_LEN
);
2761 /* Card information normally starts at VPD_BASE but early cards had
2764 ret
= pci_read_vpd(adapter
->pdev
, VPD_BASE
, sizeof(u32
), vpd
);
2768 /* The VPD shall have a unique identifier specified by the PCI SIG.
2769 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2770 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2771 * is expected to automatically put this entry at the
2772 * beginning of the VPD.
2774 addr
= *vpd
== CHELSIO_VPD_UNIQUE_ID
? VPD_BASE
: VPD_BASE_OLD
;
2776 ret
= pci_read_vpd(adapter
->pdev
, addr
, VPD_LEN
, vpd
);
2780 if (vpd
[0] != PCI_VPD_LRDT_ID_STRING
) {
2781 dev_err(adapter
->pdev_dev
, "missing VPD ID string\n");
2786 id_len
= pci_vpd_lrdt_size(vpd
);
2787 if (id_len
> ID_LEN
)
2790 i
= pci_vpd_find_tag(vpd
, 0, VPD_LEN
, PCI_VPD_LRDT_RO_DATA
);
2792 dev_err(adapter
->pdev_dev
, "missing VPD-R section\n");
2797 vpdr_len
= pci_vpd_lrdt_size(&vpd
[i
]);
2798 kw_offset
= i
+ PCI_VPD_LRDT_TAG_SIZE
;
2799 if (vpdr_len
+ kw_offset
> VPD_LEN
) {
2800 dev_err(adapter
->pdev_dev
, "bad VPD-R length %u\n", vpdr_len
);
2805 #define FIND_VPD_KW(var, name) do { \
2806 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2808 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2812 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2815 FIND_VPD_KW(i
, "RV");
2816 for (csum
= 0; i
>= 0; i
--)
2820 dev_err(adapter
->pdev_dev
,
2821 "corrupted VPD EEPROM, actual csum %u\n", csum
);
2826 FIND_VPD_KW(ec
, "EC");
2827 FIND_VPD_KW(sn
, "SN");
2828 FIND_VPD_KW(pn
, "PN");
2829 FIND_VPD_KW(na
, "NA");
2832 memcpy(p
->id
, vpd
+ PCI_VPD_LRDT_TAG_SIZE
, id_len
);
2834 memcpy(p
->ec
, vpd
+ ec
, EC_LEN
);
2836 i
= pci_vpd_info_field_size(vpd
+ sn
- PCI_VPD_INFO_FLD_HDR_SIZE
);
2837 memcpy(p
->sn
, vpd
+ sn
, min(i
, SERNUM_LEN
));
2839 i
= pci_vpd_info_field_size(vpd
+ pn
- PCI_VPD_INFO_FLD_HDR_SIZE
);
2840 memcpy(p
->pn
, vpd
+ pn
, min(i
, PN_LEN
));
2842 memcpy(p
->na
, vpd
+ na
, min(i
, MACADDR_LEN
));
2843 strim((char *)p
->na
);
2847 return ret
< 0 ? ret
: 0;
2851 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2852 * @adapter: adapter to read
2853 * @p: where to store the parameters
2855 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2856 * Clock. This can only be called after a connection to the firmware
2859 int t4_get_vpd_params(struct adapter
*adapter
, struct vpd_params
*p
)
2861 u32 cclk_param
, cclk_val
;
2864 /* Grab the raw VPD parameters.
2866 ret
= t4_get_raw_vpd_params(adapter
, p
);
2870 /* Ask firmware for the Core Clock since it knows how to translate the
2871 * Reference Clock ('V2') VPD field into a Core Clock value ...
2873 cclk_param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
2874 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK
));
2875 ret
= t4_query_params(adapter
, adapter
->mbox
, adapter
->pf
, 0,
2876 1, &cclk_param
, &cclk_val
);
2886 * t4_get_pfres - retrieve VF resource limits
2887 * @adapter: the adapter
2889 * Retrieves configured resource limits and capabilities for a physical
2890 * function. The results are stored in @adapter->pfres.
2892 int t4_get_pfres(struct adapter
*adapter
)
2894 struct pf_resources
*pfres
= &adapter
->params
.pfres
;
2895 struct fw_pfvf_cmd cmd
, rpl
;
2899 /* Execute PFVF Read command to get VF resource limits; bail out early
2900 * with error on command failure.
2902 memset(&cmd
, 0, sizeof(cmd
));
2903 cmd
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD
) |
2906 FW_PFVF_CMD_PFN_V(adapter
->pf
) |
2907 FW_PFVF_CMD_VFN_V(0));
2908 cmd
.retval_len16
= cpu_to_be32(FW_LEN16(cmd
));
2909 v
= t4_wr_mbox(adapter
, adapter
->mbox
, &cmd
, sizeof(cmd
), &rpl
);
2910 if (v
!= FW_SUCCESS
)
2913 /* Extract PF resource limits and return success.
2915 word
= be32_to_cpu(rpl
.niqflint_niq
);
2916 pfres
->niqflint
= FW_PFVF_CMD_NIQFLINT_G(word
);
2917 pfres
->niq
= FW_PFVF_CMD_NIQ_G(word
);
2919 word
= be32_to_cpu(rpl
.type_to_neq
);
2920 pfres
->neq
= FW_PFVF_CMD_NEQ_G(word
);
2921 pfres
->pmask
= FW_PFVF_CMD_PMASK_G(word
);
2923 word
= be32_to_cpu(rpl
.tc_to_nexactf
);
2924 pfres
->tc
= FW_PFVF_CMD_TC_G(word
);
2925 pfres
->nvi
= FW_PFVF_CMD_NVI_G(word
);
2926 pfres
->nexactf
= FW_PFVF_CMD_NEXACTF_G(word
);
2928 word
= be32_to_cpu(rpl
.r_caps_to_nethctrl
);
2929 pfres
->r_caps
= FW_PFVF_CMD_R_CAPS_G(word
);
2930 pfres
->wx_caps
= FW_PFVF_CMD_WX_CAPS_G(word
);
2931 pfres
->nethctrl
= FW_PFVF_CMD_NETHCTRL_G(word
);
2936 /* serial flash and firmware constants */
2938 SF_ATTEMPTS
= 10, /* max retries for SF operations */
2940 /* flash command opcodes */
2941 SF_PROG_PAGE
= 2, /* program page */
2942 SF_WR_DISABLE
= 4, /* disable writes */
2943 SF_RD_STATUS
= 5, /* read status register */
2944 SF_WR_ENABLE
= 6, /* enable writes */
2945 SF_RD_DATA_FAST
= 0xb, /* read flash */
2946 SF_RD_ID
= 0x9f, /* read ID */
2947 SF_ERASE_SECTOR
= 0xd8, /* erase sector */
2951 * sf1_read - read data from the serial flash
2952 * @adapter: the adapter
2953 * @byte_cnt: number of bytes to read
2954 * @cont: whether another operation will be chained
2955 * @lock: whether to lock SF for PL access only
2956 * @valp: where to store the read data
2958 * Reads up to 4 bytes of data from the serial flash. The location of
2959 * the read needs to be specified prior to calling this by issuing the
2960 * appropriate commands to the serial flash.
2962 static int sf1_read(struct adapter
*adapter
, unsigned int byte_cnt
, int cont
,
2963 int lock
, u32
*valp
)
2967 if (!byte_cnt
|| byte_cnt
> 4)
2969 if (t4_read_reg(adapter
, SF_OP_A
) & SF_BUSY_F
)
2971 t4_write_reg(adapter
, SF_OP_A
, SF_LOCK_V(lock
) |
2972 SF_CONT_V(cont
) | BYTECNT_V(byte_cnt
- 1));
2973 ret
= t4_wait_op_done(adapter
, SF_OP_A
, SF_BUSY_F
, 0, SF_ATTEMPTS
, 5);
2975 *valp
= t4_read_reg(adapter
, SF_DATA_A
);
2980 * sf1_write - write data to the serial flash
2981 * @adapter: the adapter
2982 * @byte_cnt: number of bytes to write
2983 * @cont: whether another operation will be chained
2984 * @lock: whether to lock SF for PL access only
2985 * @val: value to write
2987 * Writes up to 4 bytes of data to the serial flash. The location of
2988 * the write needs to be specified prior to calling this by issuing the
2989 * appropriate commands to the serial flash.
2991 static int sf1_write(struct adapter
*adapter
, unsigned int byte_cnt
, int cont
,
2994 if (!byte_cnt
|| byte_cnt
> 4)
2996 if (t4_read_reg(adapter
, SF_OP_A
) & SF_BUSY_F
)
2998 t4_write_reg(adapter
, SF_DATA_A
, val
);
2999 t4_write_reg(adapter
, SF_OP_A
, SF_LOCK_V(lock
) |
3000 SF_CONT_V(cont
) | BYTECNT_V(byte_cnt
- 1) | OP_V(1));
3001 return t4_wait_op_done(adapter
, SF_OP_A
, SF_BUSY_F
, 0, SF_ATTEMPTS
, 5);
3005 * flash_wait_op - wait for a flash operation to complete
3006 * @adapter: the adapter
3007 * @attempts: max number of polls of the status register
3008 * @delay: delay between polls in ms
3010 * Wait for a flash operation to complete by polling the status register.
3012 static int flash_wait_op(struct adapter
*adapter
, int attempts
, int delay
)
3018 if ((ret
= sf1_write(adapter
, 1, 1, 1, SF_RD_STATUS
)) != 0 ||
3019 (ret
= sf1_read(adapter
, 1, 0, 1, &status
)) != 0)
3023 if (--attempts
== 0)
3031 * t4_read_flash - read words from serial flash
3032 * @adapter: the adapter
3033 * @addr: the start address for the read
3034 * @nwords: how many 32-bit words to read
3035 * @data: where to store the read data
3036 * @byte_oriented: whether to store data as bytes or as words
3038 * Read the specified number of 32-bit words from the serial flash.
3039 * If @byte_oriented is set the read data is stored as a byte array
3040 * (i.e., big-endian), otherwise as 32-bit words in the platform's
3041 * natural endianness.
3043 int t4_read_flash(struct adapter
*adapter
, unsigned int addr
,
3044 unsigned int nwords
, u32
*data
, int byte_oriented
)
3048 if (addr
+ nwords
* sizeof(u32
) > adapter
->params
.sf_size
|| (addr
& 3))
3051 addr
= swab32(addr
) | SF_RD_DATA_FAST
;
3053 if ((ret
= sf1_write(adapter
, 4, 1, 0, addr
)) != 0 ||
3054 (ret
= sf1_read(adapter
, 1, 1, 0, data
)) != 0)
3057 for ( ; nwords
; nwords
--, data
++) {
3058 ret
= sf1_read(adapter
, 4, nwords
> 1, nwords
== 1, data
);
3060 t4_write_reg(adapter
, SF_OP_A
, 0); /* unlock SF */
3064 *data
= (__force __u32
)(cpu_to_be32(*data
));
3070 * t4_write_flash - write up to a page of data to the serial flash
3071 * @adapter: the adapter
3072 * @addr: the start address to write
3073 * @n: length of data to write in bytes
3074 * @data: the data to write
3076 * Writes up to a page of data (256 bytes) to the serial flash starting
3077 * at the given address. All the data must be written to the same page.
3079 static int t4_write_flash(struct adapter
*adapter
, unsigned int addr
,
3080 unsigned int n
, const u8
*data
)
3084 unsigned int i
, c
, left
, val
, offset
= addr
& 0xff;
3086 if (addr
>= adapter
->params
.sf_size
|| offset
+ n
> SF_PAGE_SIZE
)
3089 val
= swab32(addr
) | SF_PROG_PAGE
;
3091 if ((ret
= sf1_write(adapter
, 1, 0, 1, SF_WR_ENABLE
)) != 0 ||
3092 (ret
= sf1_write(adapter
, 4, 1, 1, val
)) != 0)
3095 for (left
= n
; left
; left
-= c
) {
3097 for (val
= 0, i
= 0; i
< c
; ++i
)
3098 val
= (val
<< 8) + *data
++;
3100 ret
= sf1_write(adapter
, c
, c
!= left
, 1, val
);
3104 ret
= flash_wait_op(adapter
, 8, 1);
3108 t4_write_reg(adapter
, SF_OP_A
, 0); /* unlock SF */
3110 /* Read the page to verify the write succeeded */
3111 ret
= t4_read_flash(adapter
, addr
& ~0xff, ARRAY_SIZE(buf
), buf
, 1);
3115 if (memcmp(data
- n
, (u8
*)buf
+ offset
, n
)) {
3116 dev_err(adapter
->pdev_dev
,
3117 "failed to correctly write the flash page at %#x\n",
3124 t4_write_reg(adapter
, SF_OP_A
, 0); /* unlock SF */
3129 * t4_get_fw_version - read the firmware version
3130 * @adapter: the adapter
3131 * @vers: where to place the version
3133 * Reads the FW version from flash.
3135 int t4_get_fw_version(struct adapter
*adapter
, u32
*vers
)
3137 return t4_read_flash(adapter
, FLASH_FW_START
+
3138 offsetof(struct fw_hdr
, fw_ver
), 1,
3143 * t4_get_bs_version - read the firmware bootstrap version
3144 * @adapter: the adapter
3145 * @vers: where to place the version
3147 * Reads the FW Bootstrap version from flash.
3149 int t4_get_bs_version(struct adapter
*adapter
, u32
*vers
)
3151 return t4_read_flash(adapter
, FLASH_FWBOOTSTRAP_START
+
3152 offsetof(struct fw_hdr
, fw_ver
), 1,
3157 * t4_get_tp_version - read the TP microcode version
3158 * @adapter: the adapter
3159 * @vers: where to place the version
3161 * Reads the TP microcode version from flash.
3163 int t4_get_tp_version(struct adapter
*adapter
, u32
*vers
)
3165 return t4_read_flash(adapter
, FLASH_FW_START
+
3166 offsetof(struct fw_hdr
, tp_microcode_ver
),
3171 * t4_get_exprom_version - return the Expansion ROM version (if any)
3172 * @adapter: the adapter
3173 * @vers: where to place the version
3175 * Reads the Expansion ROM header from FLASH and returns the version
3176 * number (if present) through the @vers return value pointer. We return
3177 * this in the Firmware Version Format since it's convenient. Return
3178 * 0 on success, -ENOENT if no Expansion ROM is present.
3180 int t4_get_exprom_version(struct adapter
*adap
, u32
*vers
)
3182 struct exprom_header
{
3183 unsigned char hdr_arr
[16]; /* must start with 0x55aa */
3184 unsigned char hdr_ver
[4]; /* Expansion ROM version */
3186 u32 exprom_header_buf
[DIV_ROUND_UP(sizeof(struct exprom_header
),
3190 ret
= t4_read_flash(adap
, FLASH_EXP_ROM_START
,
3191 ARRAY_SIZE(exprom_header_buf
), exprom_header_buf
,
3196 hdr
= (struct exprom_header
*)exprom_header_buf
;
3197 if (hdr
->hdr_arr
[0] != 0x55 || hdr
->hdr_arr
[1] != 0xaa)
3200 *vers
= (FW_HDR_FW_VER_MAJOR_V(hdr
->hdr_ver
[0]) |
3201 FW_HDR_FW_VER_MINOR_V(hdr
->hdr_ver
[1]) |
3202 FW_HDR_FW_VER_MICRO_V(hdr
->hdr_ver
[2]) |
3203 FW_HDR_FW_VER_BUILD_V(hdr
->hdr_ver
[3]));
3208 * t4_get_vpd_version - return the VPD version
3209 * @adapter: the adapter
3210 * @vers: where to place the version
3212 * Reads the VPD via the Firmware interface (thus this can only be called
3213 * once we're ready to issue Firmware commands). The format of the
3214 * VPD version is adapter specific. Returns 0 on success, an error on
3217 * Note that early versions of the Firmware didn't include the ability
3218 * to retrieve the VPD version, so we zero-out the return-value parameter
3219 * in that case to avoid leaving it with garbage in it.
3221 * Also note that the Firmware will return its cached copy of the VPD
3222 * Revision ID, not the actual Revision ID as written in the Serial
3223 * EEPROM. This is only an issue if a new VPD has been written and the
3224 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best
3225 * to defer calling this routine till after a FW_RESET_CMD has been issued
3226 * if the Host Driver will be performing a full adapter initialization.
3228 int t4_get_vpd_version(struct adapter
*adapter
, u32
*vers
)
3233 vpdrev_param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
3234 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_VPDREV
));
3235 ret
= t4_query_params(adapter
, adapter
->mbox
, adapter
->pf
, 0,
3236 1, &vpdrev_param
, vers
);
3243 * t4_get_scfg_version - return the Serial Configuration version
3244 * @adapter: the adapter
3245 * @vers: where to place the version
3247 * Reads the Serial Configuration Version via the Firmware interface
3248 * (thus this can only be called once we're ready to issue Firmware
3249 * commands). The format of the Serial Configuration version is
3250 * adapter specific. Returns 0 on success, an error on failure.
3252 * Note that early versions of the Firmware didn't include the ability
3253 * to retrieve the Serial Configuration version, so we zero-out the
3254 * return-value parameter in that case to avoid leaving it with
3257 * Also note that the Firmware will return its cached copy of the Serial
3258 * Initialization Revision ID, not the actual Revision ID as written in
3259 * the Serial EEPROM. This is only an issue if a new VPD has been written
3260 * and the Firmware/Chip haven't yet gone through a RESET sequence. So
3261 * it's best to defer calling this routine till after a FW_RESET_CMD has
3262 * been issued if the Host Driver will be performing a full adapter
3265 int t4_get_scfg_version(struct adapter
*adapter
, u32
*vers
)
3270 scfgrev_param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
3271 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_SCFGREV
));
3272 ret
= t4_query_params(adapter
, adapter
->mbox
, adapter
->pf
, 0,
3273 1, &scfgrev_param
, vers
);
3280 * t4_get_version_info - extract various chip/firmware version information
3281 * @adapter: the adapter
3283 * Reads various chip/firmware version numbers and stores them into the
3284 * adapter Adapter Parameters structure. If any of the efforts fails
3285 * the first failure will be returned, but all of the version numbers
3288 int t4_get_version_info(struct adapter
*adapter
)
3292 #define FIRST_RET(__getvinfo) \
3294 int __ret = __getvinfo; \
3295 if (__ret && !ret) \
3299 FIRST_RET(t4_get_fw_version(adapter
, &adapter
->params
.fw_vers
));
3300 FIRST_RET(t4_get_bs_version(adapter
, &adapter
->params
.bs_vers
));
3301 FIRST_RET(t4_get_tp_version(adapter
, &adapter
->params
.tp_vers
));
3302 FIRST_RET(t4_get_exprom_version(adapter
, &adapter
->params
.er_vers
));
3303 FIRST_RET(t4_get_scfg_version(adapter
, &adapter
->params
.scfg_vers
));
3304 FIRST_RET(t4_get_vpd_version(adapter
, &adapter
->params
.vpd_vers
));
3311 * t4_dump_version_info - dump all of the adapter configuration IDs
3312 * @adapter: the adapter
3314 * Dumps all of the various bits of adapter configuration version/revision
3315 * IDs information. This is typically called at some point after
3316 * t4_get_version_info() has been called.
3318 void t4_dump_version_info(struct adapter
*adapter
)
3320 /* Device information */
3321 dev_info(adapter
->pdev_dev
, "Chelsio %s rev %d\n",
3322 adapter
->params
.vpd
.id
,
3323 CHELSIO_CHIP_RELEASE(adapter
->params
.chip
));
3324 dev_info(adapter
->pdev_dev
, "S/N: %s, P/N: %s\n",
3325 adapter
->params
.vpd
.sn
, adapter
->params
.vpd
.pn
);
3327 /* Firmware Version */
3328 if (!adapter
->params
.fw_vers
)
3329 dev_warn(adapter
->pdev_dev
, "No firmware loaded\n");
3331 dev_info(adapter
->pdev_dev
, "Firmware version: %u.%u.%u.%u\n",
3332 FW_HDR_FW_VER_MAJOR_G(adapter
->params
.fw_vers
),
3333 FW_HDR_FW_VER_MINOR_G(adapter
->params
.fw_vers
),
3334 FW_HDR_FW_VER_MICRO_G(adapter
->params
.fw_vers
),
3335 FW_HDR_FW_VER_BUILD_G(adapter
->params
.fw_vers
));
3337 /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
3338 * Firmware, so dev_info() is more appropriate here.)
3340 if (!adapter
->params
.bs_vers
)
3341 dev_info(adapter
->pdev_dev
, "No bootstrap loaded\n");
3343 dev_info(adapter
->pdev_dev
, "Bootstrap version: %u.%u.%u.%u\n",
3344 FW_HDR_FW_VER_MAJOR_G(adapter
->params
.bs_vers
),
3345 FW_HDR_FW_VER_MINOR_G(adapter
->params
.bs_vers
),
3346 FW_HDR_FW_VER_MICRO_G(adapter
->params
.bs_vers
),
3347 FW_HDR_FW_VER_BUILD_G(adapter
->params
.bs_vers
));
3349 /* TP Microcode Version */
3350 if (!adapter
->params
.tp_vers
)
3351 dev_warn(adapter
->pdev_dev
, "No TP Microcode loaded\n");
3353 dev_info(adapter
->pdev_dev
,
3354 "TP Microcode version: %u.%u.%u.%u\n",
3355 FW_HDR_FW_VER_MAJOR_G(adapter
->params
.tp_vers
),
3356 FW_HDR_FW_VER_MINOR_G(adapter
->params
.tp_vers
),
3357 FW_HDR_FW_VER_MICRO_G(adapter
->params
.tp_vers
),
3358 FW_HDR_FW_VER_BUILD_G(adapter
->params
.tp_vers
));
3360 /* Expansion ROM version */
3361 if (!adapter
->params
.er_vers
)
3362 dev_info(adapter
->pdev_dev
, "No Expansion ROM loaded\n");
3364 dev_info(adapter
->pdev_dev
,
3365 "Expansion ROM version: %u.%u.%u.%u\n",
3366 FW_HDR_FW_VER_MAJOR_G(adapter
->params
.er_vers
),
3367 FW_HDR_FW_VER_MINOR_G(adapter
->params
.er_vers
),
3368 FW_HDR_FW_VER_MICRO_G(adapter
->params
.er_vers
),
3369 FW_HDR_FW_VER_BUILD_G(adapter
->params
.er_vers
));
3371 /* Serial Configuration version */
3372 dev_info(adapter
->pdev_dev
, "Serial Configuration version: %#x\n",
3373 adapter
->params
.scfg_vers
);
3376 dev_info(adapter
->pdev_dev
, "VPD version: %#x\n",
3377 adapter
->params
.vpd_vers
);
3381 * t4_check_fw_version - check if the FW is supported with this driver
3382 * @adap: the adapter
3384 * Checks if an adapter's FW is compatible with the driver. Returns 0
3385 * if there's exact match, a negative error if the version could not be
3386 * read or there's a major version mismatch
3388 int t4_check_fw_version(struct adapter
*adap
)
3390 int i
, ret
, major
, minor
, micro
;
3391 int exp_major
, exp_minor
, exp_micro
;
3392 unsigned int chip_version
= CHELSIO_CHIP_VERSION(adap
->params
.chip
);
3394 ret
= t4_get_fw_version(adap
, &adap
->params
.fw_vers
);
3395 /* Try multiple times before returning error */
3396 for (i
= 0; (ret
== -EBUSY
|| ret
== -EAGAIN
) && i
< 3; i
++)
3397 ret
= t4_get_fw_version(adap
, &adap
->params
.fw_vers
);
3402 major
= FW_HDR_FW_VER_MAJOR_G(adap
->params
.fw_vers
);
3403 minor
= FW_HDR_FW_VER_MINOR_G(adap
->params
.fw_vers
);
3404 micro
= FW_HDR_FW_VER_MICRO_G(adap
->params
.fw_vers
);
3406 switch (chip_version
) {
3408 exp_major
= T4FW_MIN_VERSION_MAJOR
;
3409 exp_minor
= T4FW_MIN_VERSION_MINOR
;
3410 exp_micro
= T4FW_MIN_VERSION_MICRO
;
3413 exp_major
= T5FW_MIN_VERSION_MAJOR
;
3414 exp_minor
= T5FW_MIN_VERSION_MINOR
;
3415 exp_micro
= T5FW_MIN_VERSION_MICRO
;
3418 exp_major
= T6FW_MIN_VERSION_MAJOR
;
3419 exp_minor
= T6FW_MIN_VERSION_MINOR
;
3420 exp_micro
= T6FW_MIN_VERSION_MICRO
;
3423 dev_err(adap
->pdev_dev
, "Unsupported chip type, %x\n",
3428 if (major
< exp_major
|| (major
== exp_major
&& minor
< exp_minor
) ||
3429 (major
== exp_major
&& minor
== exp_minor
&& micro
< exp_micro
)) {
3430 dev_err(adap
->pdev_dev
,
3431 "Card has firmware version %u.%u.%u, minimum "
3432 "supported firmware is %u.%u.%u.\n", major
, minor
,
3433 micro
, exp_major
, exp_minor
, exp_micro
);
3439 /* Is the given firmware API compatible with the one the driver was compiled
3442 static int fw_compatible(const struct fw_hdr
*hdr1
, const struct fw_hdr
*hdr2
)
3445 /* short circuit if it's the exact same firmware version */
3446 if (hdr1
->chip
== hdr2
->chip
&& hdr1
->fw_ver
== hdr2
->fw_ver
)
3449 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3450 if (hdr1
->chip
== hdr2
->chip
&& SAME_INTF(nic
) && SAME_INTF(vnic
) &&
3451 SAME_INTF(ri
) && SAME_INTF(iscsi
) && SAME_INTF(fcoe
))
3458 /* The firmware in the filesystem is usable, but should it be installed?
3459 * This routine explains itself in detail if it indicates the filesystem
3460 * firmware should be installed.
3462 static int should_install_fs_fw(struct adapter
*adap
, int card_fw_usable
,
3467 if (!card_fw_usable
) {
3468 reason
= "incompatible or unusable";
3473 reason
= "older than the version supported with this driver";
3480 dev_err(adap
->pdev_dev
, "firmware on card (%u.%u.%u.%u) is %s, "
3481 "installing firmware %u.%u.%u.%u on card.\n",
3482 FW_HDR_FW_VER_MAJOR_G(c
), FW_HDR_FW_VER_MINOR_G(c
),
3483 FW_HDR_FW_VER_MICRO_G(c
), FW_HDR_FW_VER_BUILD_G(c
), reason
,
3484 FW_HDR_FW_VER_MAJOR_G(k
), FW_HDR_FW_VER_MINOR_G(k
),
3485 FW_HDR_FW_VER_MICRO_G(k
), FW_HDR_FW_VER_BUILD_G(k
));
3490 int t4_prep_fw(struct adapter
*adap
, struct fw_info
*fw_info
,
3491 const u8
*fw_data
, unsigned int fw_size
,
3492 struct fw_hdr
*card_fw
, enum dev_state state
,
3495 int ret
, card_fw_usable
, fs_fw_usable
;
3496 const struct fw_hdr
*fs_fw
;
3497 const struct fw_hdr
*drv_fw
;
3499 drv_fw
= &fw_info
->fw_hdr
;
3501 /* Read the header of the firmware on the card */
3502 ret
= -t4_read_flash(adap
, FLASH_FW_START
,
3503 sizeof(*card_fw
) / sizeof(uint32_t),
3504 (uint32_t *)card_fw
, 1);
3506 card_fw_usable
= fw_compatible(drv_fw
, (const void *)card_fw
);
3508 dev_err(adap
->pdev_dev
,
3509 "Unable to read card's firmware header: %d\n", ret
);
3513 if (fw_data
!= NULL
) {
3514 fs_fw
= (const void *)fw_data
;
3515 fs_fw_usable
= fw_compatible(drv_fw
, fs_fw
);
3521 if (card_fw_usable
&& card_fw
->fw_ver
== drv_fw
->fw_ver
&&
3522 (!fs_fw_usable
|| fs_fw
->fw_ver
== drv_fw
->fw_ver
)) {
3523 /* Common case: the firmware on the card is an exact match and
3524 * the filesystem one is an exact match too, or the filesystem
3525 * one is absent/incompatible.
3527 } else if (fs_fw_usable
&& state
== DEV_STATE_UNINIT
&&
3528 should_install_fs_fw(adap
, card_fw_usable
,
3529 be32_to_cpu(fs_fw
->fw_ver
),
3530 be32_to_cpu(card_fw
->fw_ver
))) {
3531 ret
= -t4_fw_upgrade(adap
, adap
->mbox
, fw_data
,
3534 dev_err(adap
->pdev_dev
,
3535 "failed to install firmware: %d\n", ret
);
3539 /* Installed successfully, update the cached header too. */
3542 *reset
= 0; /* already reset as part of load_fw */
3545 if (!card_fw_usable
) {
3548 d
= be32_to_cpu(drv_fw
->fw_ver
);
3549 c
= be32_to_cpu(card_fw
->fw_ver
);
3550 k
= fs_fw
? be32_to_cpu(fs_fw
->fw_ver
) : 0;
3552 dev_err(adap
->pdev_dev
, "Cannot find a usable firmware: "
3554 "driver compiled with %d.%d.%d.%d, "
3555 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3557 FW_HDR_FW_VER_MAJOR_G(d
), FW_HDR_FW_VER_MINOR_G(d
),
3558 FW_HDR_FW_VER_MICRO_G(d
), FW_HDR_FW_VER_BUILD_G(d
),
3559 FW_HDR_FW_VER_MAJOR_G(c
), FW_HDR_FW_VER_MINOR_G(c
),
3560 FW_HDR_FW_VER_MICRO_G(c
), FW_HDR_FW_VER_BUILD_G(c
),
3561 FW_HDR_FW_VER_MAJOR_G(k
), FW_HDR_FW_VER_MINOR_G(k
),
3562 FW_HDR_FW_VER_MICRO_G(k
), FW_HDR_FW_VER_BUILD_G(k
));
3567 /* We're using whatever's on the card and it's known to be good. */
3568 adap
->params
.fw_vers
= be32_to_cpu(card_fw
->fw_ver
);
3569 adap
->params
.tp_vers
= be32_to_cpu(card_fw
->tp_microcode_ver
);
3576 * t4_flash_erase_sectors - erase a range of flash sectors
3577 * @adapter: the adapter
3578 * @start: the first sector to erase
3579 * @end: the last sector to erase
3581 * Erases the sectors in the given inclusive range.
3583 static int t4_flash_erase_sectors(struct adapter
*adapter
, int start
, int end
)
3587 if (end
>= adapter
->params
.sf_nsec
)
3590 while (start
<= end
) {
3591 if ((ret
= sf1_write(adapter
, 1, 0, 1, SF_WR_ENABLE
)) != 0 ||
3592 (ret
= sf1_write(adapter
, 4, 0, 1,
3593 SF_ERASE_SECTOR
| (start
<< 8))) != 0 ||
3594 (ret
= flash_wait_op(adapter
, 14, 500)) != 0) {
3595 dev_err(adapter
->pdev_dev
,
3596 "erase of flash sector %d failed, error %d\n",
3602 t4_write_reg(adapter
, SF_OP_A
, 0); /* unlock SF */
3607 * t4_flash_cfg_addr - return the address of the flash configuration file
3608 * @adapter: the adapter
3610 * Return the address within the flash where the Firmware Configuration
3613 unsigned int t4_flash_cfg_addr(struct adapter
*adapter
)
3615 if (adapter
->params
.sf_size
== 0x100000)
3616 return FLASH_FPGA_CFG_START
;
3618 return FLASH_CFG_START
;
3621 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3622 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3623 * and emit an error message for mismatched firmware to save our caller the
3626 static bool t4_fw_matches_chip(const struct adapter
*adap
,
3627 const struct fw_hdr
*hdr
)
3629 /* The expression below will return FALSE for any unsupported adapter
3630 * which will keep us "honest" in the future ...
3632 if ((is_t4(adap
->params
.chip
) && hdr
->chip
== FW_HDR_CHIP_T4
) ||
3633 (is_t5(adap
->params
.chip
) && hdr
->chip
== FW_HDR_CHIP_T5
) ||
3634 (is_t6(adap
->params
.chip
) && hdr
->chip
== FW_HDR_CHIP_T6
))
3637 dev_err(adap
->pdev_dev
,
3638 "FW image (%d) is not suitable for this adapter (%d)\n",
3639 hdr
->chip
, CHELSIO_CHIP_VERSION(adap
->params
.chip
));
3644 * t4_load_fw - download firmware
3645 * @adap: the adapter
3646 * @fw_data: the firmware image to write
3649 * Write the supplied firmware image to the card's serial flash.
3651 int t4_load_fw(struct adapter
*adap
, const u8
*fw_data
, unsigned int size
)
3656 u8 first_page
[SF_PAGE_SIZE
];
3657 const __be32
*p
= (const __be32
*)fw_data
;
3658 const struct fw_hdr
*hdr
= (const struct fw_hdr
*)fw_data
;
3659 unsigned int sf_sec_size
= adap
->params
.sf_size
/ adap
->params
.sf_nsec
;
3660 unsigned int fw_start_sec
= FLASH_FW_START_SEC
;
3661 unsigned int fw_size
= FLASH_FW_MAX_SIZE
;
3662 unsigned int fw_start
= FLASH_FW_START
;
3665 dev_err(adap
->pdev_dev
, "FW image has no data\n");
3669 dev_err(adap
->pdev_dev
,
3670 "FW image size not multiple of 512 bytes\n");
3673 if ((unsigned int)be16_to_cpu(hdr
->len512
) * 512 != size
) {
3674 dev_err(adap
->pdev_dev
,
3675 "FW image size differs from size in FW header\n");
3678 if (size
> fw_size
) {
3679 dev_err(adap
->pdev_dev
, "FW image too large, max is %u bytes\n",
3683 if (!t4_fw_matches_chip(adap
, hdr
))
3686 for (csum
= 0, i
= 0; i
< size
/ sizeof(csum
); i
++)
3687 csum
+= be32_to_cpu(p
[i
]);
3689 if (csum
!= 0xffffffff) {
3690 dev_err(adap
->pdev_dev
,
3691 "corrupted firmware image, checksum %#x\n", csum
);
3695 i
= DIV_ROUND_UP(size
, sf_sec_size
); /* # of sectors spanned */
3696 ret
= t4_flash_erase_sectors(adap
, fw_start_sec
, fw_start_sec
+ i
- 1);
3701 * We write the correct version at the end so the driver can see a bad
3702 * version if the FW write fails. Start by writing a copy of the
3703 * first page with a bad version.
3705 memcpy(first_page
, fw_data
, SF_PAGE_SIZE
);
3706 ((struct fw_hdr
*)first_page
)->fw_ver
= cpu_to_be32(0xffffffff);
3707 ret
= t4_write_flash(adap
, fw_start
, SF_PAGE_SIZE
, first_page
);
3712 for (size
-= SF_PAGE_SIZE
; size
; size
-= SF_PAGE_SIZE
) {
3713 addr
+= SF_PAGE_SIZE
;
3714 fw_data
+= SF_PAGE_SIZE
;
3715 ret
= t4_write_flash(adap
, addr
, SF_PAGE_SIZE
, fw_data
);
3720 ret
= t4_write_flash(adap
,
3721 fw_start
+ offsetof(struct fw_hdr
, fw_ver
),
3722 sizeof(hdr
->fw_ver
), (const u8
*)&hdr
->fw_ver
);
3725 dev_err(adap
->pdev_dev
, "firmware download failed, error %d\n",
3728 ret
= t4_get_fw_version(adap
, &adap
->params
.fw_vers
);
3733 * t4_phy_fw_ver - return current PHY firmware version
3734 * @adap: the adapter
3735 * @phy_fw_ver: return value buffer for PHY firmware version
3737 * Returns the current version of external PHY firmware on the
3740 int t4_phy_fw_ver(struct adapter
*adap
, int *phy_fw_ver
)
3745 param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
3746 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW
) |
3747 FW_PARAMS_PARAM_Y_V(adap
->params
.portvec
) |
3748 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION
));
3749 ret
= t4_query_params(adap
, adap
->mbox
, adap
->pf
, 0, 1,
3758 * t4_load_phy_fw - download port PHY firmware
3759 * @adap: the adapter
3760 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3761 * @win_lock: the lock to use to guard the memory copy
3762 * @phy_fw_version: function to check PHY firmware versions
3763 * @phy_fw_data: the PHY firmware image to write
3764 * @phy_fw_size: image size
3766 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3767 * @phy_fw_version is supplied, then it will be used to determine if
3768 * it's necessary to perform the transfer by comparing the version
3769 * of any existing adapter PHY firmware with that of the passed in
3770 * PHY firmware image. If @win_lock is non-NULL then it will be used
3771 * around the call to t4_memory_rw() which transfers the PHY firmware
3774 * A negative error number will be returned if an error occurs. If
3775 * version number support is available and there's no need to upgrade
3776 * the firmware, 0 will be returned. If firmware is successfully
3777 * transferred to the adapter, 1 will be retured.
3779 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3780 * a result, a RESET of the adapter would cause that RAM to lose its
3781 * contents. Thus, loading PHY firmware on such adapters must happen
3782 * after any FW_RESET_CMDs ...
3784 int t4_load_phy_fw(struct adapter
*adap
,
3785 int win
, spinlock_t
*win_lock
,
3786 int (*phy_fw_version
)(const u8
*, size_t),
3787 const u8
*phy_fw_data
, size_t phy_fw_size
)
3789 unsigned long mtype
= 0, maddr
= 0;
3791 int cur_phy_fw_ver
= 0, new_phy_fw_vers
= 0;
3794 /* If we have version number support, then check to see if the adapter
3795 * already has up-to-date PHY firmware loaded.
3797 if (phy_fw_version
) {
3798 new_phy_fw_vers
= phy_fw_version(phy_fw_data
, phy_fw_size
);
3799 ret
= t4_phy_fw_ver(adap
, &cur_phy_fw_ver
);
3803 if (cur_phy_fw_ver
>= new_phy_fw_vers
) {
3804 CH_WARN(adap
, "PHY Firmware already up-to-date, "
3805 "version %#x\n", cur_phy_fw_ver
);
3810 /* Ask the firmware where it wants us to copy the PHY firmware image.
3811 * The size of the file requires a special version of the READ coommand
3812 * which will pass the file size via the values field in PARAMS_CMD and
3813 * retrieve the return value from firmware and place it in the same
3816 param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
3817 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW
) |
3818 FW_PARAMS_PARAM_Y_V(adap
->params
.portvec
) |
3819 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD
));
3821 ret
= t4_query_params_rw(adap
, adap
->mbox
, adap
->pf
, 0, 1,
3822 ¶m
, &val
, 1, true);
3826 maddr
= (val
& 0xff) << 16;
3828 /* Copy the supplied PHY Firmware image to the adapter memory location
3829 * allocated by the adapter firmware.
3832 spin_lock_bh(win_lock
);
3833 ret
= t4_memory_rw(adap
, win
, mtype
, maddr
,
3834 phy_fw_size
, (__be32
*)phy_fw_data
,
3837 spin_unlock_bh(win_lock
);
3841 /* Tell the firmware that the PHY firmware image has been written to
3842 * RAM and it can now start copying it over to the PHYs. The chip
3843 * firmware will RESET the affected PHYs as part of this operation
3844 * leaving them running the new PHY firmware image.
3846 param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
3847 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW
) |
3848 FW_PARAMS_PARAM_Y_V(adap
->params
.portvec
) |
3849 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD
));
3850 ret
= t4_set_params_timeout(adap
, adap
->mbox
, adap
->pf
, 0, 1,
3851 ¶m
, &val
, 30000);
3853 /* If we have version number support, then check to see that the new
3854 * firmware got loaded properly.
3856 if (phy_fw_version
) {
3857 ret
= t4_phy_fw_ver(adap
, &cur_phy_fw_ver
);
3861 if (cur_phy_fw_ver
!= new_phy_fw_vers
) {
3862 CH_WARN(adap
, "PHY Firmware did not update: "
3863 "version on adapter %#x, "
3864 "version flashed %#x\n",
3865 cur_phy_fw_ver
, new_phy_fw_vers
);
3874 * t4_fwcache - firmware cache operation
3875 * @adap: the adapter
3876 * @op : the operation (flush or flush and invalidate)
3878 int t4_fwcache(struct adapter
*adap
, enum fw_params_param_dev_fwcache op
)
3880 struct fw_params_cmd c
;
3882 memset(&c
, 0, sizeof(c
));
3884 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD
) |
3885 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
3886 FW_PARAMS_CMD_PFN_V(adap
->pf
) |
3887 FW_PARAMS_CMD_VFN_V(0));
3888 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
3890 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
3891 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE
));
3892 c
.param
[0].val
= cpu_to_be32(op
);
3894 return t4_wr_mbox(adap
, adap
->mbox
, &c
, sizeof(c
), NULL
);
3897 void t4_cim_read_pif_la(struct adapter
*adap
, u32
*pif_req
, u32
*pif_rsp
,
3898 unsigned int *pif_req_wrptr
,
3899 unsigned int *pif_rsp_wrptr
)
3902 u32 cfg
, val
, req
, rsp
;
3904 cfg
= t4_read_reg(adap
, CIM_DEBUGCFG_A
);
3905 if (cfg
& LADBGEN_F
)
3906 t4_write_reg(adap
, CIM_DEBUGCFG_A
, cfg
^ LADBGEN_F
);
3908 val
= t4_read_reg(adap
, CIM_DEBUGSTS_A
);
3909 req
= POLADBGWRPTR_G(val
);
3910 rsp
= PILADBGWRPTR_G(val
);
3912 *pif_req_wrptr
= req
;
3914 *pif_rsp_wrptr
= rsp
;
3916 for (i
= 0; i
< CIM_PIFLA_SIZE
; i
++) {
3917 for (j
= 0; j
< 6; j
++) {
3918 t4_write_reg(adap
, CIM_DEBUGCFG_A
, POLADBGRDPTR_V(req
) |
3919 PILADBGRDPTR_V(rsp
));
3920 *pif_req
++ = t4_read_reg(adap
, CIM_PO_LA_DEBUGDATA_A
);
3921 *pif_rsp
++ = t4_read_reg(adap
, CIM_PI_LA_DEBUGDATA_A
);
3925 req
= (req
+ 2) & POLADBGRDPTR_M
;
3926 rsp
= (rsp
+ 2) & PILADBGRDPTR_M
;
3928 t4_write_reg(adap
, CIM_DEBUGCFG_A
, cfg
);
3931 void t4_cim_read_ma_la(struct adapter
*adap
, u32
*ma_req
, u32
*ma_rsp
)
3936 cfg
= t4_read_reg(adap
, CIM_DEBUGCFG_A
);
3937 if (cfg
& LADBGEN_F
)
3938 t4_write_reg(adap
, CIM_DEBUGCFG_A
, cfg
^ LADBGEN_F
);
3940 for (i
= 0; i
< CIM_MALA_SIZE
; i
++) {
3941 for (j
= 0; j
< 5; j
++) {
3943 t4_write_reg(adap
, CIM_DEBUGCFG_A
, POLADBGRDPTR_V(idx
) |
3944 PILADBGRDPTR_V(idx
));
3945 *ma_req
++ = t4_read_reg(adap
, CIM_PO_LA_MADEBUGDATA_A
);
3946 *ma_rsp
++ = t4_read_reg(adap
, CIM_PI_LA_MADEBUGDATA_A
);
3949 t4_write_reg(adap
, CIM_DEBUGCFG_A
, cfg
);
3952 void t4_ulprx_read_la(struct adapter
*adap
, u32
*la_buf
)
3956 for (i
= 0; i
< 8; i
++) {
3957 u32
*p
= la_buf
+ i
;
3959 t4_write_reg(adap
, ULP_RX_LA_CTL_A
, i
);
3960 j
= t4_read_reg(adap
, ULP_RX_LA_WRPTR_A
);
3961 t4_write_reg(adap
, ULP_RX_LA_RDPTR_A
, j
);
3962 for (j
= 0; j
< ULPRX_LA_SIZE
; j
++, p
+= 8)
3963 *p
= t4_read_reg(adap
, ULP_RX_LA_RDDATA_A
);
3967 #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
3971 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3972 * @caps16: a 16-bit Port Capabilities value
3974 * Returns the equivalent 32-bit Port Capabilities value.
3976 static fw_port_cap32_t
fwcaps16_to_caps32(fw_port_cap16_t caps16
)
3978 fw_port_cap32_t caps32
= 0;
3980 #define CAP16_TO_CAP32(__cap) \
3982 if (caps16 & FW_PORT_CAP_##__cap) \
3983 caps32 |= FW_PORT_CAP32_##__cap; \
3986 CAP16_TO_CAP32(SPEED_100M
);
3987 CAP16_TO_CAP32(SPEED_1G
);
3988 CAP16_TO_CAP32(SPEED_25G
);
3989 CAP16_TO_CAP32(SPEED_10G
);
3990 CAP16_TO_CAP32(SPEED_40G
);
3991 CAP16_TO_CAP32(SPEED_100G
);
3992 CAP16_TO_CAP32(FC_RX
);
3993 CAP16_TO_CAP32(FC_TX
);
3994 CAP16_TO_CAP32(ANEG
);
3995 CAP16_TO_CAP32(FORCE_PAUSE
);
3996 CAP16_TO_CAP32(MDIAUTO
);
3997 CAP16_TO_CAP32(MDISTRAIGHT
);
3998 CAP16_TO_CAP32(FEC_RS
);
3999 CAP16_TO_CAP32(FEC_BASER_RS
);
4000 CAP16_TO_CAP32(802_3_PAUSE
);
4001 CAP16_TO_CAP32(802_3_ASM_DIR
);
4003 #undef CAP16_TO_CAP32
4009 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
4010 * @caps32: a 32-bit Port Capabilities value
4012 * Returns the equivalent 16-bit Port Capabilities value. Note that
4013 * not all 32-bit Port Capabilities can be represented in the 16-bit
4014 * Port Capabilities and some fields/values may not make it.
4016 static fw_port_cap16_t
fwcaps32_to_caps16(fw_port_cap32_t caps32
)
4018 fw_port_cap16_t caps16
= 0;
4020 #define CAP32_TO_CAP16(__cap) \
4022 if (caps32 & FW_PORT_CAP32_##__cap) \
4023 caps16 |= FW_PORT_CAP_##__cap; \
4026 CAP32_TO_CAP16(SPEED_100M
);
4027 CAP32_TO_CAP16(SPEED_1G
);
4028 CAP32_TO_CAP16(SPEED_10G
);
4029 CAP32_TO_CAP16(SPEED_25G
);
4030 CAP32_TO_CAP16(SPEED_40G
);
4031 CAP32_TO_CAP16(SPEED_100G
);
4032 CAP32_TO_CAP16(FC_RX
);
4033 CAP32_TO_CAP16(FC_TX
);
4034 CAP32_TO_CAP16(802_3_PAUSE
);
4035 CAP32_TO_CAP16(802_3_ASM_DIR
);
4036 CAP32_TO_CAP16(ANEG
);
4037 CAP32_TO_CAP16(FORCE_PAUSE
);
4038 CAP32_TO_CAP16(MDIAUTO
);
4039 CAP32_TO_CAP16(MDISTRAIGHT
);
4040 CAP32_TO_CAP16(FEC_RS
);
4041 CAP32_TO_CAP16(FEC_BASER_RS
);
4043 #undef CAP32_TO_CAP16
4048 /* Translate Firmware Port Capabilities Pause specification to Common Code */
4049 static inline enum cc_pause
fwcap_to_cc_pause(fw_port_cap32_t fw_pause
)
4051 enum cc_pause cc_pause
= 0;
4053 if (fw_pause
& FW_PORT_CAP32_FC_RX
)
4054 cc_pause
|= PAUSE_RX
;
4055 if (fw_pause
& FW_PORT_CAP32_FC_TX
)
4056 cc_pause
|= PAUSE_TX
;
4061 /* Translate Common Code Pause specification into Firmware Port Capabilities */
4062 static inline fw_port_cap32_t
cc_to_fwcap_pause(enum cc_pause cc_pause
)
4064 fw_port_cap32_t fw_pause
= 0;
4066 if (cc_pause
& PAUSE_RX
)
4067 fw_pause
|= FW_PORT_CAP32_FC_RX
;
4068 if (cc_pause
& PAUSE_TX
)
4069 fw_pause
|= FW_PORT_CAP32_FC_TX
;
4070 if (!(cc_pause
& PAUSE_AUTONEG
))
4071 fw_pause
|= FW_PORT_CAP32_FORCE_PAUSE
;
4076 /* Translate Firmware Forward Error Correction specification to Common Code */
4077 static inline enum cc_fec
fwcap_to_cc_fec(fw_port_cap32_t fw_fec
)
4079 enum cc_fec cc_fec
= 0;
4081 if (fw_fec
& FW_PORT_CAP32_FEC_RS
)
4083 if (fw_fec
& FW_PORT_CAP32_FEC_BASER_RS
)
4084 cc_fec
|= FEC_BASER_RS
;
4089 /* Translate Common Code Forward Error Correction specification to Firmware */
4090 static inline fw_port_cap32_t
cc_to_fwcap_fec(enum cc_fec cc_fec
)
4092 fw_port_cap32_t fw_fec
= 0;
4094 if (cc_fec
& FEC_RS
)
4095 fw_fec
|= FW_PORT_CAP32_FEC_RS
;
4096 if (cc_fec
& FEC_BASER_RS
)
4097 fw_fec
|= FW_PORT_CAP32_FEC_BASER_RS
;
4103 * t4_link_l1cfg - apply link configuration to MAC/PHY
4104 * @adapter: the adapter
4105 * @mbox: the Firmware Mailbox to use
4106 * @port: the Port ID
4107 * @lc: the Port's Link Configuration
4109 * Set up a port's MAC and PHY according to a desired link configuration.
4110 * - If the PHY can auto-negotiate first decide what to advertise, then
4111 * enable/disable auto-negotiation as desired, and reset.
4112 * - If the PHY does not auto-negotiate just reset it.
4113 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4114 * otherwise do it later based on the outcome of auto-negotiation.
4116 int t4_link_l1cfg_core(struct adapter
*adapter
, unsigned int mbox
,
4117 unsigned int port
, struct link_config
*lc
,
4118 bool sleep_ok
, int timeout
)
4120 unsigned int fw_caps
= adapter
->params
.fw_caps_support
;
4121 fw_port_cap32_t fw_fc
, cc_fec
, fw_fec
, rcap
;
4122 struct fw_port_cmd cmd
;
4123 unsigned int fw_mdi
;
4126 fw_mdi
= (FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO
) & lc
->pcaps
);
4127 /* Convert driver coding of Pause Frame Flow Control settings into the
4130 fw_fc
= cc_to_fwcap_pause(lc
->requested_fc
);
4132 /* Convert Common Code Forward Error Control settings into the
4133 * Firmware's API. If the current Requested FEC has "Automatic"
4134 * (IEEE 802.3) specified, then we use whatever the Firmware
4135 * sent us as part of it's IEEE 802.3-based interpratation of
4136 * the Transceiver Module EPROM FEC parameters. Otherwise we
4137 * use whatever is in the current Requested FEC settings.
4139 if (lc
->requested_fec
& FEC_AUTO
)
4140 cc_fec
= fwcap_to_cc_fec(lc
->def_acaps
);
4142 cc_fec
= lc
->requested_fec
;
4143 fw_fec
= cc_to_fwcap_fec(cc_fec
);
4145 /* Figure out what our Requested Port Capabilities are going to be.
4147 if (!(lc
->pcaps
& FW_PORT_CAP32_ANEG
)) {
4148 rcap
= lc
->acaps
| fw_fc
| fw_fec
;
4149 lc
->fc
= lc
->requested_fc
& ~PAUSE_AUTONEG
;
4151 } else if (lc
->autoneg
== AUTONEG_DISABLE
) {
4152 rcap
= lc
->speed_caps
| fw_fc
| fw_fec
| fw_mdi
;
4153 lc
->fc
= lc
->requested_fc
& ~PAUSE_AUTONEG
;
4156 rcap
= lc
->acaps
| fw_fc
| fw_fec
| fw_mdi
;
4159 /* Note that older Firmware doesn't have FW_PORT_CAP32_FORCE_PAUSE, so
4160 * we need to exclude this from this check in order to maintain
4163 if ((rcap
& ~lc
->pcaps
) & ~FW_PORT_CAP32_FORCE_PAUSE
) {
4164 dev_err(adapter
->pdev_dev
,
4165 "Requested Port Capabilities %#x exceed Physical Port Capabilities %#x\n",
4170 /* And send that on to the Firmware ...
4172 memset(&cmd
, 0, sizeof(cmd
));
4173 cmd
.op_to_portid
= cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD
) |
4174 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
4175 FW_PORT_CMD_PORTID_V(port
));
4176 cmd
.action_to_len16
=
4177 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps
== FW_CAPS16
4178 ? FW_PORT_ACTION_L1_CFG
4179 : FW_PORT_ACTION_L1_CFG32
) |
4181 if (fw_caps
== FW_CAPS16
)
4182 cmd
.u
.l1cfg
.rcap
= cpu_to_be32(fwcaps32_to_caps16(rcap
));
4184 cmd
.u
.l1cfg32
.rcap32
= cpu_to_be32(rcap
);
4186 ret
= t4_wr_mbox_meat_timeout(adapter
, mbox
, &cmd
, sizeof(cmd
), NULL
,
4189 dev_err(adapter
->pdev_dev
,
4190 "Requested Port Capabilities %#x rejected, error %d\n",
4198 * t4_restart_aneg - restart autonegotiation
4199 * @adap: the adapter
4200 * @mbox: mbox to use for the FW command
4201 * @port: the port id
4203 * Restarts autonegotiation for the selected port.
4205 int t4_restart_aneg(struct adapter
*adap
, unsigned int mbox
, unsigned int port
)
4207 unsigned int fw_caps
= adap
->params
.fw_caps_support
;
4208 struct fw_port_cmd c
;
4210 memset(&c
, 0, sizeof(c
));
4211 c
.op_to_portid
= cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD
) |
4212 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
4213 FW_PORT_CMD_PORTID_V(port
));
4215 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps
== FW_CAPS16
4216 ? FW_PORT_ACTION_L1_CFG
4217 : FW_PORT_ACTION_L1_CFG32
) |
4219 if (fw_caps
== FW_CAPS16
)
4220 c
.u
.l1cfg
.rcap
= cpu_to_be32(FW_PORT_CAP_ANEG
);
4222 c
.u
.l1cfg32
.rcap32
= cpu_to_be32(FW_PORT_CAP32_ANEG
);
4223 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
4226 typedef void (*int_handler_t
)(struct adapter
*adap
);
4229 unsigned int mask
; /* bits to check in interrupt status */
4230 const char *msg
; /* message to print or NULL */
4231 short stat_idx
; /* stat counter to increment or -1 */
4232 unsigned short fatal
; /* whether the condition reported is fatal */
4233 int_handler_t int_handler
; /* platform-specific int handler */
4237 * t4_handle_intr_status - table driven interrupt handler
4238 * @adapter: the adapter that generated the interrupt
4239 * @reg: the interrupt status register to process
4240 * @acts: table of interrupt actions
4242 * A table driven interrupt handler that applies a set of masks to an
4243 * interrupt status word and performs the corresponding actions if the
4244 * interrupts described by the mask have occurred. The actions include
4245 * optionally emitting a warning or alert message. The table is terminated
4246 * by an entry specifying mask 0. Returns the number of fatal interrupt
4249 static int t4_handle_intr_status(struct adapter
*adapter
, unsigned int reg
,
4250 const struct intr_info
*acts
)
4253 unsigned int mask
= 0;
4254 unsigned int status
= t4_read_reg(adapter
, reg
);
4256 for ( ; acts
->mask
; ++acts
) {
4257 if (!(status
& acts
->mask
))
4261 dev_alert(adapter
->pdev_dev
, "%s (0x%x)\n", acts
->msg
,
4262 status
& acts
->mask
);
4263 } else if (acts
->msg
&& printk_ratelimit())
4264 dev_warn(adapter
->pdev_dev
, "%s (0x%x)\n", acts
->msg
,
4265 status
& acts
->mask
);
4266 if (acts
->int_handler
)
4267 acts
->int_handler(adapter
);
4271 if (status
) /* clear processed interrupts */
4272 t4_write_reg(adapter
, reg
, status
);
4277 * Interrupt handler for the PCIE module.
4279 static void pcie_intr_handler(struct adapter
*adapter
)
4281 static const struct intr_info sysbus_intr_info
[] = {
4282 { RNPP_F
, "RXNP array parity error", -1, 1 },
4283 { RPCP_F
, "RXPC array parity error", -1, 1 },
4284 { RCIP_F
, "RXCIF array parity error", -1, 1 },
4285 { RCCP_F
, "Rx completions control array parity error", -1, 1 },
4286 { RFTP_F
, "RXFT array parity error", -1, 1 },
4289 static const struct intr_info pcie_port_intr_info
[] = {
4290 { TPCP_F
, "TXPC array parity error", -1, 1 },
4291 { TNPP_F
, "TXNP array parity error", -1, 1 },
4292 { TFTP_F
, "TXFT array parity error", -1, 1 },
4293 { TCAP_F
, "TXCA array parity error", -1, 1 },
4294 { TCIP_F
, "TXCIF array parity error", -1, 1 },
4295 { RCAP_F
, "RXCA array parity error", -1, 1 },
4296 { OTDD_F
, "outbound request TLP discarded", -1, 1 },
4297 { RDPE_F
, "Rx data parity error", -1, 1 },
4298 { TDUE_F
, "Tx uncorrectable data error", -1, 1 },
4301 static const struct intr_info pcie_intr_info
[] = {
4302 { MSIADDRLPERR_F
, "MSI AddrL parity error", -1, 1 },
4303 { MSIADDRHPERR_F
, "MSI AddrH parity error", -1, 1 },
4304 { MSIDATAPERR_F
, "MSI data parity error", -1, 1 },
4305 { MSIXADDRLPERR_F
, "MSI-X AddrL parity error", -1, 1 },
4306 { MSIXADDRHPERR_F
, "MSI-X AddrH parity error", -1, 1 },
4307 { MSIXDATAPERR_F
, "MSI-X data parity error", -1, 1 },
4308 { MSIXDIPERR_F
, "MSI-X DI parity error", -1, 1 },
4309 { PIOCPLPERR_F
, "PCI PIO completion FIFO parity error", -1, 1 },
4310 { PIOREQPERR_F
, "PCI PIO request FIFO parity error", -1, 1 },
4311 { TARTAGPERR_F
, "PCI PCI target tag FIFO parity error", -1, 1 },
4312 { CCNTPERR_F
, "PCI CMD channel count parity error", -1, 1 },
4313 { CREQPERR_F
, "PCI CMD channel request parity error", -1, 1 },
4314 { CRSPPERR_F
, "PCI CMD channel response parity error", -1, 1 },
4315 { DCNTPERR_F
, "PCI DMA channel count parity error", -1, 1 },
4316 { DREQPERR_F
, "PCI DMA channel request parity error", -1, 1 },
4317 { DRSPPERR_F
, "PCI DMA channel response parity error", -1, 1 },
4318 { HCNTPERR_F
, "PCI HMA channel count parity error", -1, 1 },
4319 { HREQPERR_F
, "PCI HMA channel request parity error", -1, 1 },
4320 { HRSPPERR_F
, "PCI HMA channel response parity error", -1, 1 },
4321 { CFGSNPPERR_F
, "PCI config snoop FIFO parity error", -1, 1 },
4322 { FIDPERR_F
, "PCI FID parity error", -1, 1 },
4323 { INTXCLRPERR_F
, "PCI INTx clear parity error", -1, 1 },
4324 { MATAGPERR_F
, "PCI MA tag parity error", -1, 1 },
4325 { PIOTAGPERR_F
, "PCI PIO tag parity error", -1, 1 },
4326 { RXCPLPERR_F
, "PCI Rx completion parity error", -1, 1 },
4327 { RXWRPERR_F
, "PCI Rx write parity error", -1, 1 },
4328 { RPLPERR_F
, "PCI replay buffer parity error", -1, 1 },
4329 { PCIESINT_F
, "PCI core secondary fault", -1, 1 },
4330 { PCIEPINT_F
, "PCI core primary fault", -1, 1 },
4331 { UNXSPLCPLERR_F
, "PCI unexpected split completion error",
4336 static struct intr_info t5_pcie_intr_info
[] = {
4337 { MSTGRPPERR_F
, "Master Response Read Queue parity error",
4339 { MSTTIMEOUTPERR_F
, "Master Timeout FIFO parity error", -1, 1 },
4340 { MSIXSTIPERR_F
, "MSI-X STI SRAM parity error", -1, 1 },
4341 { MSIXADDRLPERR_F
, "MSI-X AddrL parity error", -1, 1 },
4342 { MSIXADDRHPERR_F
, "MSI-X AddrH parity error", -1, 1 },
4343 { MSIXDATAPERR_F
, "MSI-X data parity error", -1, 1 },
4344 { MSIXDIPERR_F
, "MSI-X DI parity error", -1, 1 },
4345 { PIOCPLGRPPERR_F
, "PCI PIO completion Group FIFO parity error",
4347 { PIOREQGRPPERR_F
, "PCI PIO request Group FIFO parity error",
4349 { TARTAGPERR_F
, "PCI PCI target tag FIFO parity error", -1, 1 },
4350 { MSTTAGQPERR_F
, "PCI master tag queue parity error", -1, 1 },
4351 { CREQPERR_F
, "PCI CMD channel request parity error", -1, 1 },
4352 { CRSPPERR_F
, "PCI CMD channel response parity error", -1, 1 },
4353 { DREQWRPERR_F
, "PCI DMA channel write request parity error",
4355 { DREQPERR_F
, "PCI DMA channel request parity error", -1, 1 },
4356 { DRSPPERR_F
, "PCI DMA channel response parity error", -1, 1 },
4357 { HREQWRPERR_F
, "PCI HMA channel count parity error", -1, 1 },
4358 { HREQPERR_F
, "PCI HMA channel request parity error", -1, 1 },
4359 { HRSPPERR_F
, "PCI HMA channel response parity error", -1, 1 },
4360 { CFGSNPPERR_F
, "PCI config snoop FIFO parity error", -1, 1 },
4361 { FIDPERR_F
, "PCI FID parity error", -1, 1 },
4362 { VFIDPERR_F
, "PCI INTx clear parity error", -1, 1 },
4363 { MAGRPPERR_F
, "PCI MA group FIFO parity error", -1, 1 },
4364 { PIOTAGPERR_F
, "PCI PIO tag parity error", -1, 1 },
4365 { IPRXHDRGRPPERR_F
, "PCI IP Rx header group parity error",
4367 { IPRXDATAGRPPERR_F
, "PCI IP Rx data group parity error",
4369 { RPLPERR_F
, "PCI IP replay buffer parity error", -1, 1 },
4370 { IPSOTPERR_F
, "PCI IP SOT buffer parity error", -1, 1 },
4371 { TRGT1GRPPERR_F
, "PCI TRGT1 group FIFOs parity error", -1, 1 },
4372 { READRSPERR_F
, "Outbound read error", -1, 0 },
4378 if (is_t4(adapter
->params
.chip
))
4379 fat
= t4_handle_intr_status(adapter
,
4380 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A
,
4382 t4_handle_intr_status(adapter
,
4383 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A
,
4384 pcie_port_intr_info
) +
4385 t4_handle_intr_status(adapter
, PCIE_INT_CAUSE_A
,
4388 fat
= t4_handle_intr_status(adapter
, PCIE_INT_CAUSE_A
,
4392 t4_fatal_err(adapter
);
4396 * TP interrupt handler.
4398 static void tp_intr_handler(struct adapter
*adapter
)
4400 static const struct intr_info tp_intr_info
[] = {
4401 { 0x3fffffff, "TP parity error", -1, 1 },
4402 { FLMTXFLSTEMPTY_F
, "TP out of Tx pages", -1, 1 },
4406 if (t4_handle_intr_status(adapter
, TP_INT_CAUSE_A
, tp_intr_info
))
4407 t4_fatal_err(adapter
);
4411 * SGE interrupt handler.
4413 static void sge_intr_handler(struct adapter
*adapter
)
4418 static const struct intr_info sge_intr_info
[] = {
4419 { ERR_CPL_EXCEED_IQE_SIZE_F
,
4420 "SGE received CPL exceeding IQE size", -1, 1 },
4421 { ERR_INVALID_CIDX_INC_F
,
4422 "SGE GTS CIDX increment too large", -1, 0 },
4423 { ERR_CPL_OPCODE_0_F
, "SGE received 0-length CPL", -1, 0 },
4424 { DBFIFO_LP_INT_F
, NULL
, -1, 0, t4_db_full
},
4425 { ERR_DATA_CPL_ON_HIGH_QID1_F
| ERR_DATA_CPL_ON_HIGH_QID0_F
,
4426 "SGE IQID > 1023 received CPL for FL", -1, 0 },
4427 { ERR_BAD_DB_PIDX3_F
, "SGE DBP 3 pidx increment too large", -1,
4429 { ERR_BAD_DB_PIDX2_F
, "SGE DBP 2 pidx increment too large", -1,
4431 { ERR_BAD_DB_PIDX1_F
, "SGE DBP 1 pidx increment too large", -1,
4433 { ERR_BAD_DB_PIDX0_F
, "SGE DBP 0 pidx increment too large", -1,
4435 { ERR_ING_CTXT_PRIO_F
,
4436 "SGE too many priority ingress contexts", -1, 0 },
4437 { INGRESS_SIZE_ERR_F
, "SGE illegal ingress QID", -1, 0 },
4438 { EGRESS_SIZE_ERR_F
, "SGE illegal egress QID", -1, 0 },
4442 static struct intr_info t4t5_sge_intr_info
[] = {
4443 { ERR_DROPPED_DB_F
, NULL
, -1, 0, t4_db_dropped
},
4444 { DBFIFO_HP_INT_F
, NULL
, -1, 0, t4_db_full
},
4445 { ERR_EGR_CTXT_PRIO_F
,
4446 "SGE too many priority egress contexts", -1, 0 },
4450 v
= (u64
)t4_read_reg(adapter
, SGE_INT_CAUSE1_A
) |
4451 ((u64
)t4_read_reg(adapter
, SGE_INT_CAUSE2_A
) << 32);
4453 dev_alert(adapter
->pdev_dev
, "SGE parity error (%#llx)\n",
4454 (unsigned long long)v
);
4455 t4_write_reg(adapter
, SGE_INT_CAUSE1_A
, v
);
4456 t4_write_reg(adapter
, SGE_INT_CAUSE2_A
, v
>> 32);
4459 v
|= t4_handle_intr_status(adapter
, SGE_INT_CAUSE3_A
, sge_intr_info
);
4460 if (CHELSIO_CHIP_VERSION(adapter
->params
.chip
) <= CHELSIO_T5
)
4461 v
|= t4_handle_intr_status(adapter
, SGE_INT_CAUSE3_A
,
4462 t4t5_sge_intr_info
);
4464 err
= t4_read_reg(adapter
, SGE_ERROR_STATS_A
);
4465 if (err
& ERROR_QID_VALID_F
) {
4466 dev_err(adapter
->pdev_dev
, "SGE error for queue %u\n",
4468 if (err
& UNCAPTURED_ERROR_F
)
4469 dev_err(adapter
->pdev_dev
,
4470 "SGE UNCAPTURED_ERROR set (clearing)\n");
4471 t4_write_reg(adapter
, SGE_ERROR_STATS_A
, ERROR_QID_VALID_F
|
4472 UNCAPTURED_ERROR_F
);
4476 t4_fatal_err(adapter
);
4479 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4480 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4481 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4482 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4485 * CIM interrupt handler.
4487 static void cim_intr_handler(struct adapter
*adapter
)
4489 static const struct intr_info cim_intr_info
[] = {
4490 { PREFDROPINT_F
, "CIM control register prefetch drop", -1, 1 },
4491 { CIM_OBQ_INTR
, "CIM OBQ parity error", -1, 1 },
4492 { CIM_IBQ_INTR
, "CIM IBQ parity error", -1, 1 },
4493 { MBUPPARERR_F
, "CIM mailbox uP parity error", -1, 1 },
4494 { MBHOSTPARERR_F
, "CIM mailbox host parity error", -1, 1 },
4495 { TIEQINPARERRINT_F
, "CIM TIEQ outgoing parity error", -1, 1 },
4496 { TIEQOUTPARERRINT_F
, "CIM TIEQ incoming parity error", -1, 1 },
4497 { TIMER0INT_F
, "CIM TIMER0 interrupt", -1, 1 },
4500 static const struct intr_info cim_upintr_info
[] = {
4501 { RSVDSPACEINT_F
, "CIM reserved space access", -1, 1 },
4502 { ILLTRANSINT_F
, "CIM illegal transaction", -1, 1 },
4503 { ILLWRINT_F
, "CIM illegal write", -1, 1 },
4504 { ILLRDINT_F
, "CIM illegal read", -1, 1 },
4505 { ILLRDBEINT_F
, "CIM illegal read BE", -1, 1 },
4506 { ILLWRBEINT_F
, "CIM illegal write BE", -1, 1 },
4507 { SGLRDBOOTINT_F
, "CIM single read from boot space", -1, 1 },
4508 { SGLWRBOOTINT_F
, "CIM single write to boot space", -1, 1 },
4509 { BLKWRBOOTINT_F
, "CIM block write to boot space", -1, 1 },
4510 { SGLRDFLASHINT_F
, "CIM single read from flash space", -1, 1 },
4511 { SGLWRFLASHINT_F
, "CIM single write to flash space", -1, 1 },
4512 { BLKWRFLASHINT_F
, "CIM block write to flash space", -1, 1 },
4513 { SGLRDEEPROMINT_F
, "CIM single EEPROM read", -1, 1 },
4514 { SGLWREEPROMINT_F
, "CIM single EEPROM write", -1, 1 },
4515 { BLKRDEEPROMINT_F
, "CIM block EEPROM read", -1, 1 },
4516 { BLKWREEPROMINT_F
, "CIM block EEPROM write", -1, 1 },
4517 { SGLRDCTLINT_F
, "CIM single read from CTL space", -1, 1 },
4518 { SGLWRCTLINT_F
, "CIM single write to CTL space", -1, 1 },
4519 { BLKRDCTLINT_F
, "CIM block read from CTL space", -1, 1 },
4520 { BLKWRCTLINT_F
, "CIM block write to CTL space", -1, 1 },
4521 { SGLRDPLINT_F
, "CIM single read from PL space", -1, 1 },
4522 { SGLWRPLINT_F
, "CIM single write to PL space", -1, 1 },
4523 { BLKRDPLINT_F
, "CIM block read from PL space", -1, 1 },
4524 { BLKWRPLINT_F
, "CIM block write to PL space", -1, 1 },
4525 { REQOVRLOOKUPINT_F
, "CIM request FIFO overwrite", -1, 1 },
4526 { RSPOVRLOOKUPINT_F
, "CIM response FIFO overwrite", -1, 1 },
4527 { TIMEOUTINT_F
, "CIM PIF timeout", -1, 1 },
4528 { TIMEOUTMAINT_F
, "CIM PIF MA timeout", -1, 1 },
4535 fw_err
= t4_read_reg(adapter
, PCIE_FW_A
);
4536 if (fw_err
& PCIE_FW_ERR_F
)
4537 t4_report_fw_error(adapter
);
4539 /* When the Firmware detects an internal error which normally
4540 * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4541 * in order to make sure the Host sees the Firmware Crash. So
4542 * if we have a Timer0 interrupt and don't see a Firmware Crash,
4543 * ignore the Timer0 interrupt.
4546 val
= t4_read_reg(adapter
, CIM_HOST_INT_CAUSE_A
);
4547 if (val
& TIMER0INT_F
)
4548 if (!(fw_err
& PCIE_FW_ERR_F
) ||
4549 (PCIE_FW_EVAL_G(fw_err
) != PCIE_FW_EVAL_CRASH
))
4550 t4_write_reg(adapter
, CIM_HOST_INT_CAUSE_A
,
4553 fat
= t4_handle_intr_status(adapter
, CIM_HOST_INT_CAUSE_A
,
4555 t4_handle_intr_status(adapter
, CIM_HOST_UPACC_INT_CAUSE_A
,
4558 t4_fatal_err(adapter
);
4562 * ULP RX interrupt handler.
4564 static void ulprx_intr_handler(struct adapter
*adapter
)
4566 static const struct intr_info ulprx_intr_info
[] = {
4567 { 0x1800000, "ULPRX context error", -1, 1 },
4568 { 0x7fffff, "ULPRX parity error", -1, 1 },
4572 if (t4_handle_intr_status(adapter
, ULP_RX_INT_CAUSE_A
, ulprx_intr_info
))
4573 t4_fatal_err(adapter
);
4577 * ULP TX interrupt handler.
4579 static void ulptx_intr_handler(struct adapter
*adapter
)
4581 static const struct intr_info ulptx_intr_info
[] = {
4582 { PBL_BOUND_ERR_CH3_F
, "ULPTX channel 3 PBL out of bounds", -1,
4584 { PBL_BOUND_ERR_CH2_F
, "ULPTX channel 2 PBL out of bounds", -1,
4586 { PBL_BOUND_ERR_CH1_F
, "ULPTX channel 1 PBL out of bounds", -1,
4588 { PBL_BOUND_ERR_CH0_F
, "ULPTX channel 0 PBL out of bounds", -1,
4590 { 0xfffffff, "ULPTX parity error", -1, 1 },
4594 if (t4_handle_intr_status(adapter
, ULP_TX_INT_CAUSE_A
, ulptx_intr_info
))
4595 t4_fatal_err(adapter
);
4599 * PM TX interrupt handler.
4601 static void pmtx_intr_handler(struct adapter
*adapter
)
4603 static const struct intr_info pmtx_intr_info
[] = {
4604 { PCMD_LEN_OVFL0_F
, "PMTX channel 0 pcmd too large", -1, 1 },
4605 { PCMD_LEN_OVFL1_F
, "PMTX channel 1 pcmd too large", -1, 1 },
4606 { PCMD_LEN_OVFL2_F
, "PMTX channel 2 pcmd too large", -1, 1 },
4607 { ZERO_C_CMD_ERROR_F
, "PMTX 0-length pcmd", -1, 1 },
4608 { PMTX_FRAMING_ERROR_F
, "PMTX framing error", -1, 1 },
4609 { OESPI_PAR_ERROR_F
, "PMTX oespi parity error", -1, 1 },
4610 { DB_OPTIONS_PAR_ERROR_F
, "PMTX db_options parity error",
4612 { ICSPI_PAR_ERROR_F
, "PMTX icspi parity error", -1, 1 },
4613 { PMTX_C_PCMD_PAR_ERROR_F
, "PMTX c_pcmd parity error", -1, 1},
4617 if (t4_handle_intr_status(adapter
, PM_TX_INT_CAUSE_A
, pmtx_intr_info
))
4618 t4_fatal_err(adapter
);
4622 * PM RX interrupt handler.
4624 static void pmrx_intr_handler(struct adapter
*adapter
)
4626 static const struct intr_info pmrx_intr_info
[] = {
4627 { ZERO_E_CMD_ERROR_F
, "PMRX 0-length pcmd", -1, 1 },
4628 { PMRX_FRAMING_ERROR_F
, "PMRX framing error", -1, 1 },
4629 { OCSPI_PAR_ERROR_F
, "PMRX ocspi parity error", -1, 1 },
4630 { DB_OPTIONS_PAR_ERROR_F
, "PMRX db_options parity error",
4632 { IESPI_PAR_ERROR_F
, "PMRX iespi parity error", -1, 1 },
4633 { PMRX_E_PCMD_PAR_ERROR_F
, "PMRX e_pcmd parity error", -1, 1},
4637 if (t4_handle_intr_status(adapter
, PM_RX_INT_CAUSE_A
, pmrx_intr_info
))
4638 t4_fatal_err(adapter
);
4642 * CPL switch interrupt handler.
4644 static void cplsw_intr_handler(struct adapter
*adapter
)
4646 static const struct intr_info cplsw_intr_info
[] = {
4647 { CIM_OP_MAP_PERR_F
, "CPLSW CIM op_map parity error", -1, 1 },
4648 { CIM_OVFL_ERROR_F
, "CPLSW CIM overflow", -1, 1 },
4649 { TP_FRAMING_ERROR_F
, "CPLSW TP framing error", -1, 1 },
4650 { SGE_FRAMING_ERROR_F
, "CPLSW SGE framing error", -1, 1 },
4651 { CIM_FRAMING_ERROR_F
, "CPLSW CIM framing error", -1, 1 },
4652 { ZERO_SWITCH_ERROR_F
, "CPLSW no-switch error", -1, 1 },
4656 if (t4_handle_intr_status(adapter
, CPL_INTR_CAUSE_A
, cplsw_intr_info
))
4657 t4_fatal_err(adapter
);
4661 * LE interrupt handler.
4663 static void le_intr_handler(struct adapter
*adap
)
4665 enum chip_type chip
= CHELSIO_CHIP_VERSION(adap
->params
.chip
);
4666 static const struct intr_info le_intr_info
[] = {
4667 { LIPMISS_F
, "LE LIP miss", -1, 0 },
4668 { LIP0_F
, "LE 0 LIP error", -1, 0 },
4669 { PARITYERR_F
, "LE parity error", -1, 1 },
4670 { UNKNOWNCMD_F
, "LE unknown command", -1, 1 },
4671 { REQQPARERR_F
, "LE request queue parity error", -1, 1 },
4675 static struct intr_info t6_le_intr_info
[] = {
4676 { T6_LIPMISS_F
, "LE LIP miss", -1, 0 },
4677 { T6_LIP0_F
, "LE 0 LIP error", -1, 0 },
4678 { TCAMINTPERR_F
, "LE parity error", -1, 1 },
4679 { T6_UNKNOWNCMD_F
, "LE unknown command", -1, 1 },
4680 { SSRAMINTPERR_F
, "LE request queue parity error", -1, 1 },
4684 if (t4_handle_intr_status(adap
, LE_DB_INT_CAUSE_A
,
4685 (chip
<= CHELSIO_T5
) ?
4686 le_intr_info
: t6_le_intr_info
))
4691 * MPS interrupt handler.
4693 static void mps_intr_handler(struct adapter
*adapter
)
4695 static const struct intr_info mps_rx_intr_info
[] = {
4696 { 0xffffff, "MPS Rx parity error", -1, 1 },
4699 static const struct intr_info mps_tx_intr_info
[] = {
4700 { TPFIFO_V(TPFIFO_M
), "MPS Tx TP FIFO parity error", -1, 1 },
4701 { NCSIFIFO_F
, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4702 { TXDATAFIFO_V(TXDATAFIFO_M
), "MPS Tx data FIFO parity error",
4704 { TXDESCFIFO_V(TXDESCFIFO_M
), "MPS Tx desc FIFO parity error",
4706 { BUBBLE_F
, "MPS Tx underflow", -1, 1 },
4707 { SECNTERR_F
, "MPS Tx SOP/EOP error", -1, 1 },
4708 { FRMERR_F
, "MPS Tx framing error", -1, 1 },
4711 static const struct intr_info t6_mps_tx_intr_info
[] = {
4712 { TPFIFO_V(TPFIFO_M
), "MPS Tx TP FIFO parity error", -1, 1 },
4713 { NCSIFIFO_F
, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4714 { TXDATAFIFO_V(TXDATAFIFO_M
), "MPS Tx data FIFO parity error",
4716 { TXDESCFIFO_V(TXDESCFIFO_M
), "MPS Tx desc FIFO parity error",
4718 /* MPS Tx Bubble is normal for T6 */
4719 { SECNTERR_F
, "MPS Tx SOP/EOP error", -1, 1 },
4720 { FRMERR_F
, "MPS Tx framing error", -1, 1 },
4723 static const struct intr_info mps_trc_intr_info
[] = {
4724 { FILTMEM_V(FILTMEM_M
), "MPS TRC filter parity error", -1, 1 },
4725 { PKTFIFO_V(PKTFIFO_M
), "MPS TRC packet FIFO parity error",
4727 { MISCPERR_F
, "MPS TRC misc parity error", -1, 1 },
4730 static const struct intr_info mps_stat_sram_intr_info
[] = {
4731 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4734 static const struct intr_info mps_stat_tx_intr_info
[] = {
4735 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4738 static const struct intr_info mps_stat_rx_intr_info
[] = {
4739 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4742 static const struct intr_info mps_cls_intr_info
[] = {
4743 { MATCHSRAM_F
, "MPS match SRAM parity error", -1, 1 },
4744 { MATCHTCAM_F
, "MPS match TCAM parity error", -1, 1 },
4745 { HASHSRAM_F
, "MPS hash SRAM parity error", -1, 1 },
4751 fat
= t4_handle_intr_status(adapter
, MPS_RX_PERR_INT_CAUSE_A
,
4753 t4_handle_intr_status(adapter
, MPS_TX_INT_CAUSE_A
,
4754 is_t6(adapter
->params
.chip
)
4755 ? t6_mps_tx_intr_info
4756 : mps_tx_intr_info
) +
4757 t4_handle_intr_status(adapter
, MPS_TRC_INT_CAUSE_A
,
4758 mps_trc_intr_info
) +
4759 t4_handle_intr_status(adapter
, MPS_STAT_PERR_INT_CAUSE_SRAM_A
,
4760 mps_stat_sram_intr_info
) +
4761 t4_handle_intr_status(adapter
, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A
,
4762 mps_stat_tx_intr_info
) +
4763 t4_handle_intr_status(adapter
, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A
,
4764 mps_stat_rx_intr_info
) +
4765 t4_handle_intr_status(adapter
, MPS_CLS_INT_CAUSE_A
,
4768 t4_write_reg(adapter
, MPS_INT_CAUSE_A
, 0);
4769 t4_read_reg(adapter
, MPS_INT_CAUSE_A
); /* flush */
4771 t4_fatal_err(adapter
);
4774 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4778 * EDC/MC interrupt handler.
4780 static void mem_intr_handler(struct adapter
*adapter
, int idx
)
4782 static const char name
[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4784 unsigned int addr
, cnt_addr
, v
;
4786 if (idx
<= MEM_EDC1
) {
4787 addr
= EDC_REG(EDC_INT_CAUSE_A
, idx
);
4788 cnt_addr
= EDC_REG(EDC_ECC_STATUS_A
, idx
);
4789 } else if (idx
== MEM_MC
) {
4790 if (is_t4(adapter
->params
.chip
)) {
4791 addr
= MC_INT_CAUSE_A
;
4792 cnt_addr
= MC_ECC_STATUS_A
;
4794 addr
= MC_P_INT_CAUSE_A
;
4795 cnt_addr
= MC_P_ECC_STATUS_A
;
4798 addr
= MC_REG(MC_P_INT_CAUSE_A
, 1);
4799 cnt_addr
= MC_REG(MC_P_ECC_STATUS_A
, 1);
4802 v
= t4_read_reg(adapter
, addr
) & MEM_INT_MASK
;
4803 if (v
& PERR_INT_CAUSE_F
)
4804 dev_alert(adapter
->pdev_dev
, "%s FIFO parity error\n",
4806 if (v
& ECC_CE_INT_CAUSE_F
) {
4807 u32 cnt
= ECC_CECNT_G(t4_read_reg(adapter
, cnt_addr
));
4809 t4_edc_err_read(adapter
, idx
);
4811 t4_write_reg(adapter
, cnt_addr
, ECC_CECNT_V(ECC_CECNT_M
));
4812 if (printk_ratelimit())
4813 dev_warn(adapter
->pdev_dev
,
4814 "%u %s correctable ECC data error%s\n",
4815 cnt
, name
[idx
], cnt
> 1 ? "s" : "");
4817 if (v
& ECC_UE_INT_CAUSE_F
)
4818 dev_alert(adapter
->pdev_dev
,
4819 "%s uncorrectable ECC data error\n", name
[idx
]);
4821 t4_write_reg(adapter
, addr
, v
);
4822 if (v
& (PERR_INT_CAUSE_F
| ECC_UE_INT_CAUSE_F
))
4823 t4_fatal_err(adapter
);
4827 * MA interrupt handler.
4829 static void ma_intr_handler(struct adapter
*adap
)
4831 u32 v
, status
= t4_read_reg(adap
, MA_INT_CAUSE_A
);
4833 if (status
& MEM_PERR_INT_CAUSE_F
) {
4834 dev_alert(adap
->pdev_dev
,
4835 "MA parity error, parity status %#x\n",
4836 t4_read_reg(adap
, MA_PARITY_ERROR_STATUS1_A
));
4837 if (is_t5(adap
->params
.chip
))
4838 dev_alert(adap
->pdev_dev
,
4839 "MA parity error, parity status %#x\n",
4841 MA_PARITY_ERROR_STATUS2_A
));
4843 if (status
& MEM_WRAP_INT_CAUSE_F
) {
4844 v
= t4_read_reg(adap
, MA_INT_WRAP_STATUS_A
);
4845 dev_alert(adap
->pdev_dev
, "MA address wrap-around error by "
4846 "client %u to address %#x\n",
4847 MEM_WRAP_CLIENT_NUM_G(v
),
4848 MEM_WRAP_ADDRESS_G(v
) << 4);
4850 t4_write_reg(adap
, MA_INT_CAUSE_A
, status
);
4855 * SMB interrupt handler.
4857 static void smb_intr_handler(struct adapter
*adap
)
4859 static const struct intr_info smb_intr_info
[] = {
4860 { MSTTXFIFOPARINT_F
, "SMB master Tx FIFO parity error", -1, 1 },
4861 { MSTRXFIFOPARINT_F
, "SMB master Rx FIFO parity error", -1, 1 },
4862 { SLVFIFOPARINT_F
, "SMB slave FIFO parity error", -1, 1 },
4866 if (t4_handle_intr_status(adap
, SMB_INT_CAUSE_A
, smb_intr_info
))
4871 * NC-SI interrupt handler.
4873 static void ncsi_intr_handler(struct adapter
*adap
)
4875 static const struct intr_info ncsi_intr_info
[] = {
4876 { CIM_DM_PRTY_ERR_F
, "NC-SI CIM parity error", -1, 1 },
4877 { MPS_DM_PRTY_ERR_F
, "NC-SI MPS parity error", -1, 1 },
4878 { TXFIFO_PRTY_ERR_F
, "NC-SI Tx FIFO parity error", -1, 1 },
4879 { RXFIFO_PRTY_ERR_F
, "NC-SI Rx FIFO parity error", -1, 1 },
4883 if (t4_handle_intr_status(adap
, NCSI_INT_CAUSE_A
, ncsi_intr_info
))
4888 * XGMAC interrupt handler.
4890 static void xgmac_intr_handler(struct adapter
*adap
, int port
)
4892 u32 v
, int_cause_reg
;
4894 if (is_t4(adap
->params
.chip
))
4895 int_cause_reg
= PORT_REG(port
, XGMAC_PORT_INT_CAUSE_A
);
4897 int_cause_reg
= T5_PORT_REG(port
, MAC_PORT_INT_CAUSE_A
);
4899 v
= t4_read_reg(adap
, int_cause_reg
);
4901 v
&= TXFIFO_PRTY_ERR_F
| RXFIFO_PRTY_ERR_F
;
4905 if (v
& TXFIFO_PRTY_ERR_F
)
4906 dev_alert(adap
->pdev_dev
, "XGMAC %d Tx FIFO parity error\n",
4908 if (v
& RXFIFO_PRTY_ERR_F
)
4909 dev_alert(adap
->pdev_dev
, "XGMAC %d Rx FIFO parity error\n",
4911 t4_write_reg(adap
, PORT_REG(port
, XGMAC_PORT_INT_CAUSE_A
), v
);
4916 * PL interrupt handler.
4918 static void pl_intr_handler(struct adapter
*adap
)
4920 static const struct intr_info pl_intr_info
[] = {
4921 { FATALPERR_F
, "T4 fatal parity error", -1, 1 },
4922 { PERRVFID_F
, "PL VFID_MAP parity error", -1, 1 },
4926 if (t4_handle_intr_status(adap
, PL_PL_INT_CAUSE_A
, pl_intr_info
))
4930 #define PF_INTR_MASK (PFSW_F)
4931 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4932 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4933 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
4936 * t4_slow_intr_handler - control path interrupt handler
4937 * @adapter: the adapter
4939 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
4940 * The designation 'slow' is because it involves register reads, while
4941 * data interrupts typically don't involve any MMIOs.
4943 int t4_slow_intr_handler(struct adapter
*adapter
)
4945 u32 cause
= t4_read_reg(adapter
, PL_INT_CAUSE_A
);
4947 if (!(cause
& GLBL_INTR_MASK
))
4950 cim_intr_handler(adapter
);
4952 mps_intr_handler(adapter
);
4954 ncsi_intr_handler(adapter
);
4956 pl_intr_handler(adapter
);
4958 smb_intr_handler(adapter
);
4959 if (cause
& XGMAC0_F
)
4960 xgmac_intr_handler(adapter
, 0);
4961 if (cause
& XGMAC1_F
)
4962 xgmac_intr_handler(adapter
, 1);
4963 if (cause
& XGMAC_KR0_F
)
4964 xgmac_intr_handler(adapter
, 2);
4965 if (cause
& XGMAC_KR1_F
)
4966 xgmac_intr_handler(adapter
, 3);
4968 pcie_intr_handler(adapter
);
4970 mem_intr_handler(adapter
, MEM_MC
);
4971 if (is_t5(adapter
->params
.chip
) && (cause
& MC1_F
))
4972 mem_intr_handler(adapter
, MEM_MC1
);
4974 mem_intr_handler(adapter
, MEM_EDC0
);
4976 mem_intr_handler(adapter
, MEM_EDC1
);
4978 le_intr_handler(adapter
);
4980 tp_intr_handler(adapter
);
4982 ma_intr_handler(adapter
);
4983 if (cause
& PM_TX_F
)
4984 pmtx_intr_handler(adapter
);
4985 if (cause
& PM_RX_F
)
4986 pmrx_intr_handler(adapter
);
4987 if (cause
& ULP_RX_F
)
4988 ulprx_intr_handler(adapter
);
4989 if (cause
& CPL_SWITCH_F
)
4990 cplsw_intr_handler(adapter
);
4992 sge_intr_handler(adapter
);
4993 if (cause
& ULP_TX_F
)
4994 ulptx_intr_handler(adapter
);
4996 /* Clear the interrupts just processed for which we are the master. */
4997 t4_write_reg(adapter
, PL_INT_CAUSE_A
, cause
& GLBL_INTR_MASK
);
4998 (void)t4_read_reg(adapter
, PL_INT_CAUSE_A
); /* flush */
5003 * t4_intr_enable - enable interrupts
5004 * @adapter: the adapter whose interrupts should be enabled
5006 * Enable PF-specific interrupts for the calling function and the top-level
5007 * interrupt concentrator for global interrupts. Interrupts are already
5008 * enabled at each module, here we just enable the roots of the interrupt
5011 * Note: this function should be called only when the driver manages
5012 * non PF-specific interrupts from the various HW modules. Only one PCI
5013 * function at a time should be doing this.
5015 void t4_intr_enable(struct adapter
*adapter
)
5018 u32 whoami
= t4_read_reg(adapter
, PL_WHOAMI_A
);
5019 u32 pf
= CHELSIO_CHIP_VERSION(adapter
->params
.chip
) <= CHELSIO_T5
?
5020 SOURCEPF_G(whoami
) : T6_SOURCEPF_G(whoami
);
5022 if (CHELSIO_CHIP_VERSION(adapter
->params
.chip
) <= CHELSIO_T5
)
5023 val
= ERR_DROPPED_DB_F
| ERR_EGR_CTXT_PRIO_F
| DBFIFO_HP_INT_F
;
5024 t4_write_reg(adapter
, SGE_INT_ENABLE3_A
, ERR_CPL_EXCEED_IQE_SIZE_F
|
5025 ERR_INVALID_CIDX_INC_F
| ERR_CPL_OPCODE_0_F
|
5026 ERR_DATA_CPL_ON_HIGH_QID1_F
| INGRESS_SIZE_ERR_F
|
5027 ERR_DATA_CPL_ON_HIGH_QID0_F
| ERR_BAD_DB_PIDX3_F
|
5028 ERR_BAD_DB_PIDX2_F
| ERR_BAD_DB_PIDX1_F
|
5029 ERR_BAD_DB_PIDX0_F
| ERR_ING_CTXT_PRIO_F
|
5030 DBFIFO_LP_INT_F
| EGRESS_SIZE_ERR_F
| val
);
5031 t4_write_reg(adapter
, MYPF_REG(PL_PF_INT_ENABLE_A
), PF_INTR_MASK
);
5032 t4_set_reg_field(adapter
, PL_INT_MAP0_A
, 0, 1 << pf
);
5036 * t4_intr_disable - disable interrupts
5037 * @adapter: the adapter whose interrupts should be disabled
5039 * Disable interrupts. We only disable the top-level interrupt
5040 * concentrators. The caller must be a PCI function managing global
5043 void t4_intr_disable(struct adapter
*adapter
)
5047 if (pci_channel_offline(adapter
->pdev
))
5050 whoami
= t4_read_reg(adapter
, PL_WHOAMI_A
);
5051 pf
= CHELSIO_CHIP_VERSION(adapter
->params
.chip
) <= CHELSIO_T5
?
5052 SOURCEPF_G(whoami
) : T6_SOURCEPF_G(whoami
);
5054 t4_write_reg(adapter
, MYPF_REG(PL_PF_INT_ENABLE_A
), 0);
5055 t4_set_reg_field(adapter
, PL_INT_MAP0_A
, 1 << pf
, 0);
5058 unsigned int t4_chip_rss_size(struct adapter
*adap
)
5060 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) <= CHELSIO_T5
)
5061 return RSS_NENTRIES
;
5063 return T6_RSS_NENTRIES
;
5067 * t4_config_rss_range - configure a portion of the RSS mapping table
5068 * @adapter: the adapter
5069 * @mbox: mbox to use for the FW command
5070 * @viid: virtual interface whose RSS subtable is to be written
5071 * @start: start entry in the table to write
5072 * @n: how many table entries to write
5073 * @rspq: values for the response queue lookup table
5074 * @nrspq: number of values in @rspq
5076 * Programs the selected part of the VI's RSS mapping table with the
5077 * provided values. If @nrspq < @n the supplied values are used repeatedly
5078 * until the full table range is populated.
5080 * The caller must ensure the values in @rspq are in the range allowed for
5083 int t4_config_rss_range(struct adapter
*adapter
, int mbox
, unsigned int viid
,
5084 int start
, int n
, const u16
*rspq
, unsigned int nrspq
)
5087 const u16
*rsp
= rspq
;
5088 const u16
*rsp_end
= rspq
+ nrspq
;
5089 struct fw_rss_ind_tbl_cmd cmd
;
5091 memset(&cmd
, 0, sizeof(cmd
));
5092 cmd
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD
) |
5093 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
5094 FW_RSS_IND_TBL_CMD_VIID_V(viid
));
5095 cmd
.retval_len16
= cpu_to_be32(FW_LEN16(cmd
));
5097 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
5099 int nq
= min(n
, 32);
5100 __be32
*qp
= &cmd
.iq0_to_iq2
;
5102 cmd
.niqid
= cpu_to_be16(nq
);
5103 cmd
.startidx
= cpu_to_be16(start
);
5111 v
= FW_RSS_IND_TBL_CMD_IQ0_V(*rsp
);
5112 if (++rsp
>= rsp_end
)
5114 v
|= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp
);
5115 if (++rsp
>= rsp_end
)
5117 v
|= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp
);
5118 if (++rsp
>= rsp_end
)
5121 *qp
++ = cpu_to_be32(v
);
5125 ret
= t4_wr_mbox(adapter
, mbox
, &cmd
, sizeof(cmd
), NULL
);
5133 * t4_config_glbl_rss - configure the global RSS mode
5134 * @adapter: the adapter
5135 * @mbox: mbox to use for the FW command
5136 * @mode: global RSS mode
5137 * @flags: mode-specific flags
5139 * Sets the global RSS mode.
5141 int t4_config_glbl_rss(struct adapter
*adapter
, int mbox
, unsigned int mode
,
5144 struct fw_rss_glb_config_cmd c
;
5146 memset(&c
, 0, sizeof(c
));
5147 c
.op_to_write
= cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD
) |
5148 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
);
5149 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
5150 if (mode
== FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL
) {
5151 c
.u
.manual
.mode_pkd
=
5152 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode
));
5153 } else if (mode
== FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL
) {
5154 c
.u
.basicvirtual
.mode_pkd
=
5155 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode
));
5156 c
.u
.basicvirtual
.synmapen_to_hashtoeplitz
= cpu_to_be32(flags
);
5159 return t4_wr_mbox(adapter
, mbox
, &c
, sizeof(c
), NULL
);
5163 * t4_config_vi_rss - configure per VI RSS settings
5164 * @adapter: the adapter
5165 * @mbox: mbox to use for the FW command
5168 * @defq: id of the default RSS queue for the VI.
5170 * Configures VI-specific RSS properties.
5172 int t4_config_vi_rss(struct adapter
*adapter
, int mbox
, unsigned int viid
,
5173 unsigned int flags
, unsigned int defq
)
5175 struct fw_rss_vi_config_cmd c
;
5177 memset(&c
, 0, sizeof(c
));
5178 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD
) |
5179 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
5180 FW_RSS_VI_CONFIG_CMD_VIID_V(viid
));
5181 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
5182 c
.u
.basicvirtual
.defaultq_to_udpen
= cpu_to_be32(flags
|
5183 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq
));
5184 return t4_wr_mbox(adapter
, mbox
, &c
, sizeof(c
), NULL
);
5187 /* Read an RSS table row */
5188 static int rd_rss_row(struct adapter
*adap
, int row
, u32
*val
)
5190 t4_write_reg(adap
, TP_RSS_LKP_TABLE_A
, 0xfff00000 | row
);
5191 return t4_wait_op_done_val(adap
, TP_RSS_LKP_TABLE_A
, LKPTBLROWVLD_F
, 1,
5196 * t4_read_rss - read the contents of the RSS mapping table
5197 * @adapter: the adapter
5198 * @map: holds the contents of the RSS mapping table
5200 * Reads the contents of the RSS hash->queue mapping table.
5202 int t4_read_rss(struct adapter
*adapter
, u16
*map
)
5204 int i
, ret
, nentries
;
5207 nentries
= t4_chip_rss_size(adapter
);
5208 for (i
= 0; i
< nentries
/ 2; ++i
) {
5209 ret
= rd_rss_row(adapter
, i
, &val
);
5212 *map
++ = LKPTBLQUEUE0_G(val
);
5213 *map
++ = LKPTBLQUEUE1_G(val
);
5218 static unsigned int t4_use_ldst(struct adapter
*adap
)
5220 return (adap
->flags
& FW_OK
) && !adap
->use_bd
;
5224 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5225 * @adap: the adapter
5226 * @cmd: TP fw ldst address space type
5227 * @vals: where the indirect register values are stored/written
5228 * @nregs: how many indirect registers to read/write
5229 * @start_idx: index of first indirect register to read/write
5230 * @rw: Read (1) or Write (0)
5231 * @sleep_ok: if true we may sleep while awaiting command completion
5233 * Access TP indirect registers through LDST
5235 static int t4_tp_fw_ldst_rw(struct adapter
*adap
, int cmd
, u32
*vals
,
5236 unsigned int nregs
, unsigned int start_index
,
5237 unsigned int rw
, bool sleep_ok
)
5241 struct fw_ldst_cmd c
;
5243 for (i
= 0; i
< nregs
; i
++) {
5244 memset(&c
, 0, sizeof(c
));
5245 c
.op_to_addrspace
= cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
5247 (rw
? FW_CMD_READ_F
:
5249 FW_LDST_CMD_ADDRSPACE_V(cmd
));
5250 c
.cycles_to_len16
= cpu_to_be32(FW_LEN16(c
));
5252 c
.u
.addrval
.addr
= cpu_to_be32(start_index
+ i
);
5253 c
.u
.addrval
.val
= rw
? 0 : cpu_to_be32(vals
[i
]);
5254 ret
= t4_wr_mbox_meat(adap
, adap
->mbox
, &c
, sizeof(c
), &c
,
5260 vals
[i
] = be32_to_cpu(c
.u
.addrval
.val
);
5266 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5267 * @adap: the adapter
5268 * @reg_addr: Address Register
5269 * @reg_data: Data register
5270 * @buff: where the indirect register values are stored/written
5271 * @nregs: how many indirect registers to read/write
5272 * @start_index: index of first indirect register to read/write
5273 * @rw: READ(1) or WRITE(0)
5274 * @sleep_ok: if true we may sleep while awaiting command completion
5276 * Read/Write TP indirect registers through LDST if possible.
5277 * Else, use backdoor access
5279 static void t4_tp_indirect_rw(struct adapter
*adap
, u32 reg_addr
, u32 reg_data
,
5280 u32
*buff
, u32 nregs
, u32 start_index
, int rw
,
5288 cmd
= FW_LDST_ADDRSPC_TP_PIO
;
5290 case TP_TM_PIO_ADDR_A
:
5291 cmd
= FW_LDST_ADDRSPC_TP_TM_PIO
;
5293 case TP_MIB_INDEX_A
:
5294 cmd
= FW_LDST_ADDRSPC_TP_MIB
;
5297 goto indirect_access
;
5300 if (t4_use_ldst(adap
))
5301 rc
= t4_tp_fw_ldst_rw(adap
, cmd
, buff
, nregs
, start_index
, rw
,
5308 t4_read_indirect(adap
, reg_addr
, reg_data
, buff
, nregs
,
5311 t4_write_indirect(adap
, reg_addr
, reg_data
, buff
, nregs
,
5317 * t4_tp_pio_read - Read TP PIO registers
5318 * @adap: the adapter
5319 * @buff: where the indirect register values are written
5320 * @nregs: how many indirect registers to read
5321 * @start_index: index of first indirect register to read
5322 * @sleep_ok: if true we may sleep while awaiting command completion
5324 * Read TP PIO Registers
5326 void t4_tp_pio_read(struct adapter
*adap
, u32
*buff
, u32 nregs
,
5327 u32 start_index
, bool sleep_ok
)
5329 t4_tp_indirect_rw(adap
, TP_PIO_ADDR_A
, TP_PIO_DATA_A
, buff
, nregs
,
5330 start_index
, 1, sleep_ok
);
5334 * t4_tp_pio_write - Write TP PIO registers
5335 * @adap: the adapter
5336 * @buff: where the indirect register values are stored
5337 * @nregs: how many indirect registers to write
5338 * @start_index: index of first indirect register to write
5339 * @sleep_ok: if true we may sleep while awaiting command completion
5341 * Write TP PIO Registers
5343 static void t4_tp_pio_write(struct adapter
*adap
, u32
*buff
, u32 nregs
,
5344 u32 start_index
, bool sleep_ok
)
5346 t4_tp_indirect_rw(adap
, TP_PIO_ADDR_A
, TP_PIO_DATA_A
, buff
, nregs
,
5347 start_index
, 0, sleep_ok
);
5351 * t4_tp_tm_pio_read - Read TP TM PIO registers
5352 * @adap: the adapter
5353 * @buff: where the indirect register values are written
5354 * @nregs: how many indirect registers to read
5355 * @start_index: index of first indirect register to read
5356 * @sleep_ok: if true we may sleep while awaiting command completion
5358 * Read TP TM PIO Registers
5360 void t4_tp_tm_pio_read(struct adapter
*adap
, u32
*buff
, u32 nregs
,
5361 u32 start_index
, bool sleep_ok
)
5363 t4_tp_indirect_rw(adap
, TP_TM_PIO_ADDR_A
, TP_TM_PIO_DATA_A
, buff
,
5364 nregs
, start_index
, 1, sleep_ok
);
5368 * t4_tp_mib_read - Read TP MIB registers
5369 * @adap: the adapter
5370 * @buff: where the indirect register values are written
5371 * @nregs: how many indirect registers to read
5372 * @start_index: index of first indirect register to read
5373 * @sleep_ok: if true we may sleep while awaiting command completion
5375 * Read TP MIB Registers
5377 void t4_tp_mib_read(struct adapter
*adap
, u32
*buff
, u32 nregs
, u32 start_index
,
5380 t4_tp_indirect_rw(adap
, TP_MIB_INDEX_A
, TP_MIB_DATA_A
, buff
, nregs
,
5381 start_index
, 1, sleep_ok
);
5385 * t4_read_rss_key - read the global RSS key
5386 * @adap: the adapter
5387 * @key: 10-entry array holding the 320-bit RSS key
5388 * @sleep_ok: if true we may sleep while awaiting command completion
5390 * Reads the global 320-bit RSS key.
5392 void t4_read_rss_key(struct adapter
*adap
, u32
*key
, bool sleep_ok
)
5394 t4_tp_pio_read(adap
, key
, 10, TP_RSS_SECRET_KEY0_A
, sleep_ok
);
5398 * t4_write_rss_key - program one of the RSS keys
5399 * @adap: the adapter
5400 * @key: 10-entry array holding the 320-bit RSS key
5401 * @idx: which RSS key to write
5402 * @sleep_ok: if true we may sleep while awaiting command completion
5404 * Writes one of the RSS keys with the given 320-bit value. If @idx is
5405 * 0..15 the corresponding entry in the RSS key table is written,
5406 * otherwise the global RSS key is written.
5408 void t4_write_rss_key(struct adapter
*adap
, const u32
*key
, int idx
,
5411 u8 rss_key_addr_cnt
= 16;
5412 u32 vrt
= t4_read_reg(adap
, TP_RSS_CONFIG_VRT_A
);
5414 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5415 * allows access to key addresses 16-63 by using KeyWrAddrX
5416 * as index[5:4](upper 2) into key table
5418 if ((CHELSIO_CHIP_VERSION(adap
->params
.chip
) > CHELSIO_T5
) &&
5419 (vrt
& KEYEXTEND_F
) && (KEYMODE_G(vrt
) == 3))
5420 rss_key_addr_cnt
= 32;
5422 t4_tp_pio_write(adap
, (void *)key
, 10, TP_RSS_SECRET_KEY0_A
, sleep_ok
);
5424 if (idx
>= 0 && idx
< rss_key_addr_cnt
) {
5425 if (rss_key_addr_cnt
> 16)
5426 t4_write_reg(adap
, TP_RSS_CONFIG_VRT_A
,
5427 KEYWRADDRX_V(idx
>> 4) |
5428 T6_VFWRADDR_V(idx
) | KEYWREN_F
);
5430 t4_write_reg(adap
, TP_RSS_CONFIG_VRT_A
,
5431 KEYWRADDR_V(idx
) | KEYWREN_F
);
5436 * t4_read_rss_pf_config - read PF RSS Configuration Table
5437 * @adapter: the adapter
5438 * @index: the entry in the PF RSS table to read
5439 * @valp: where to store the returned value
5440 * @sleep_ok: if true we may sleep while awaiting command completion
5442 * Reads the PF RSS Configuration Table at the specified index and returns
5443 * the value found there.
5445 void t4_read_rss_pf_config(struct adapter
*adapter
, unsigned int index
,
5446 u32
*valp
, bool sleep_ok
)
5448 t4_tp_pio_read(adapter
, valp
, 1, TP_RSS_PF0_CONFIG_A
+ index
, sleep_ok
);
5452 * t4_read_rss_vf_config - read VF RSS Configuration Table
5453 * @adapter: the adapter
5454 * @index: the entry in the VF RSS table to read
5455 * @vfl: where to store the returned VFL
5456 * @vfh: where to store the returned VFH
5457 * @sleep_ok: if true we may sleep while awaiting command completion
5459 * Reads the VF RSS Configuration Table at the specified index and returns
5460 * the (VFL, VFH) values found there.
5462 void t4_read_rss_vf_config(struct adapter
*adapter
, unsigned int index
,
5463 u32
*vfl
, u32
*vfh
, bool sleep_ok
)
5465 u32 vrt
, mask
, data
;
5467 if (CHELSIO_CHIP_VERSION(adapter
->params
.chip
) <= CHELSIO_T5
) {
5468 mask
= VFWRADDR_V(VFWRADDR_M
);
5469 data
= VFWRADDR_V(index
);
5471 mask
= T6_VFWRADDR_V(T6_VFWRADDR_M
);
5472 data
= T6_VFWRADDR_V(index
);
5475 /* Request that the index'th VF Table values be read into VFL/VFH.
5477 vrt
= t4_read_reg(adapter
, TP_RSS_CONFIG_VRT_A
);
5478 vrt
&= ~(VFRDRG_F
| VFWREN_F
| KEYWREN_F
| mask
);
5479 vrt
|= data
| VFRDEN_F
;
5480 t4_write_reg(adapter
, TP_RSS_CONFIG_VRT_A
, vrt
);
5482 /* Grab the VFL/VFH values ...
5484 t4_tp_pio_read(adapter
, vfl
, 1, TP_RSS_VFL_CONFIG_A
, sleep_ok
);
5485 t4_tp_pio_read(adapter
, vfh
, 1, TP_RSS_VFH_CONFIG_A
, sleep_ok
);
5489 * t4_read_rss_pf_map - read PF RSS Map
5490 * @adapter: the adapter
5491 * @sleep_ok: if true we may sleep while awaiting command completion
5493 * Reads the PF RSS Map register and returns its value.
5495 u32
t4_read_rss_pf_map(struct adapter
*adapter
, bool sleep_ok
)
5499 t4_tp_pio_read(adapter
, &pfmap
, 1, TP_RSS_PF_MAP_A
, sleep_ok
);
5504 * t4_read_rss_pf_mask - read PF RSS Mask
5505 * @adapter: the adapter
5506 * @sleep_ok: if true we may sleep while awaiting command completion
5508 * Reads the PF RSS Mask register and returns its value.
5510 u32
t4_read_rss_pf_mask(struct adapter
*adapter
, bool sleep_ok
)
5514 t4_tp_pio_read(adapter
, &pfmask
, 1, TP_RSS_PF_MSK_A
, sleep_ok
);
5519 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
5520 * @adap: the adapter
5521 * @v4: holds the TCP/IP counter values
5522 * @v6: holds the TCP/IPv6 counter values
5523 * @sleep_ok: if true we may sleep while awaiting command completion
5525 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5526 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5528 void t4_tp_get_tcp_stats(struct adapter
*adap
, struct tp_tcp_stats
*v4
,
5529 struct tp_tcp_stats
*v6
, bool sleep_ok
)
5531 u32 val
[TP_MIB_TCP_RXT_SEG_LO_A
- TP_MIB_TCP_OUT_RST_A
+ 1];
5533 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
5534 #define STAT(x) val[STAT_IDX(x)]
5535 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5538 t4_tp_mib_read(adap
, val
, ARRAY_SIZE(val
),
5539 TP_MIB_TCP_OUT_RST_A
, sleep_ok
);
5540 v4
->tcp_out_rsts
= STAT(OUT_RST
);
5541 v4
->tcp_in_segs
= STAT64(IN_SEG
);
5542 v4
->tcp_out_segs
= STAT64(OUT_SEG
);
5543 v4
->tcp_retrans_segs
= STAT64(RXT_SEG
);
5546 t4_tp_mib_read(adap
, val
, ARRAY_SIZE(val
),
5547 TP_MIB_TCP_V6OUT_RST_A
, sleep_ok
);
5548 v6
->tcp_out_rsts
= STAT(OUT_RST
);
5549 v6
->tcp_in_segs
= STAT64(IN_SEG
);
5550 v6
->tcp_out_segs
= STAT64(OUT_SEG
);
5551 v6
->tcp_retrans_segs
= STAT64(RXT_SEG
);
5559 * t4_tp_get_err_stats - read TP's error MIB counters
5560 * @adap: the adapter
5561 * @st: holds the counter values
5562 * @sleep_ok: if true we may sleep while awaiting command completion
5564 * Returns the values of TP's error counters.
5566 void t4_tp_get_err_stats(struct adapter
*adap
, struct tp_err_stats
*st
,
5569 int nchan
= adap
->params
.arch
.nchan
;
5571 t4_tp_mib_read(adap
, st
->mac_in_errs
, nchan
, TP_MIB_MAC_IN_ERR_0_A
,
5573 t4_tp_mib_read(adap
, st
->hdr_in_errs
, nchan
, TP_MIB_HDR_IN_ERR_0_A
,
5575 t4_tp_mib_read(adap
, st
->tcp_in_errs
, nchan
, TP_MIB_TCP_IN_ERR_0_A
,
5577 t4_tp_mib_read(adap
, st
->tnl_cong_drops
, nchan
,
5578 TP_MIB_TNL_CNG_DROP_0_A
, sleep_ok
);
5579 t4_tp_mib_read(adap
, st
->ofld_chan_drops
, nchan
,
5580 TP_MIB_OFD_CHN_DROP_0_A
, sleep_ok
);
5581 t4_tp_mib_read(adap
, st
->tnl_tx_drops
, nchan
, TP_MIB_TNL_DROP_0_A
,
5583 t4_tp_mib_read(adap
, st
->ofld_vlan_drops
, nchan
,
5584 TP_MIB_OFD_VLN_DROP_0_A
, sleep_ok
);
5585 t4_tp_mib_read(adap
, st
->tcp6_in_errs
, nchan
,
5586 TP_MIB_TCP_V6IN_ERR_0_A
, sleep_ok
);
5587 t4_tp_mib_read(adap
, &st
->ofld_no_neigh
, 2, TP_MIB_OFD_ARP_DROP_A
,
5592 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
5593 * @adap: the adapter
5594 * @st: holds the counter values
5595 * @sleep_ok: if true we may sleep while awaiting command completion
5597 * Returns the values of TP's CPL counters.
5599 void t4_tp_get_cpl_stats(struct adapter
*adap
, struct tp_cpl_stats
*st
,
5602 int nchan
= adap
->params
.arch
.nchan
;
5604 t4_tp_mib_read(adap
, st
->req
, nchan
, TP_MIB_CPL_IN_REQ_0_A
, sleep_ok
);
5606 t4_tp_mib_read(adap
, st
->rsp
, nchan
, TP_MIB_CPL_OUT_RSP_0_A
, sleep_ok
);
5610 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5611 * @adap: the adapter
5612 * @st: holds the counter values
5613 * @sleep_ok: if true we may sleep while awaiting command completion
5615 * Returns the values of TP's RDMA counters.
5617 void t4_tp_get_rdma_stats(struct adapter
*adap
, struct tp_rdma_stats
*st
,
5620 t4_tp_mib_read(adap
, &st
->rqe_dfr_pkt
, 2, TP_MIB_RQE_DFR_PKT_A
,
5625 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5626 * @adap: the adapter
5627 * @idx: the port index
5628 * @st: holds the counter values
5629 * @sleep_ok: if true we may sleep while awaiting command completion
5631 * Returns the values of TP's FCoE counters for the selected port.
5633 void t4_get_fcoe_stats(struct adapter
*adap
, unsigned int idx
,
5634 struct tp_fcoe_stats
*st
, bool sleep_ok
)
5638 t4_tp_mib_read(adap
, &st
->frames_ddp
, 1, TP_MIB_FCOE_DDP_0_A
+ idx
,
5641 t4_tp_mib_read(adap
, &st
->frames_drop
, 1,
5642 TP_MIB_FCOE_DROP_0_A
+ idx
, sleep_ok
);
5644 t4_tp_mib_read(adap
, val
, 2, TP_MIB_FCOE_BYTE_0_HI_A
+ 2 * idx
,
5647 st
->octets_ddp
= ((u64
)val
[0] << 32) | val
[1];
5651 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5652 * @adap: the adapter
5653 * @st: holds the counter values
5654 * @sleep_ok: if true we may sleep while awaiting command completion
5656 * Returns the values of TP's counters for non-TCP directly-placed packets.
5658 void t4_get_usm_stats(struct adapter
*adap
, struct tp_usm_stats
*st
,
5663 t4_tp_mib_read(adap
, val
, 4, TP_MIB_USM_PKTS_A
, sleep_ok
);
5664 st
->frames
= val
[0];
5666 st
->octets
= ((u64
)val
[2] << 32) | val
[3];
5670 * t4_read_mtu_tbl - returns the values in the HW path MTU table
5671 * @adap: the adapter
5672 * @mtus: where to store the MTU values
5673 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
5675 * Reads the HW path MTU table.
5677 void t4_read_mtu_tbl(struct adapter
*adap
, u16
*mtus
, u8
*mtu_log
)
5682 for (i
= 0; i
< NMTUS
; ++i
) {
5683 t4_write_reg(adap
, TP_MTU_TABLE_A
,
5684 MTUINDEX_V(0xff) | MTUVALUE_V(i
));
5685 v
= t4_read_reg(adap
, TP_MTU_TABLE_A
);
5686 mtus
[i
] = MTUVALUE_G(v
);
5688 mtu_log
[i
] = MTUWIDTH_G(v
);
5693 * t4_read_cong_tbl - reads the congestion control table
5694 * @adap: the adapter
5695 * @incr: where to store the alpha values
5697 * Reads the additive increments programmed into the HW congestion
5700 void t4_read_cong_tbl(struct adapter
*adap
, u16 incr
[NMTUS
][NCCTRL_WIN
])
5702 unsigned int mtu
, w
;
5704 for (mtu
= 0; mtu
< NMTUS
; ++mtu
)
5705 for (w
= 0; w
< NCCTRL_WIN
; ++w
) {
5706 t4_write_reg(adap
, TP_CCTRL_TABLE_A
,
5707 ROWINDEX_V(0xffff) | (mtu
<< 5) | w
);
5708 incr
[mtu
][w
] = (u16
)t4_read_reg(adap
,
5709 TP_CCTRL_TABLE_A
) & 0x1fff;
5714 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5715 * @adap: the adapter
5716 * @addr: the indirect TP register address
5717 * @mask: specifies the field within the register to modify
5718 * @val: new value for the field
5720 * Sets a field of an indirect TP register to the given value.
5722 void t4_tp_wr_bits_indirect(struct adapter
*adap
, unsigned int addr
,
5723 unsigned int mask
, unsigned int val
)
5725 t4_write_reg(adap
, TP_PIO_ADDR_A
, addr
);
5726 val
|= t4_read_reg(adap
, TP_PIO_DATA_A
) & ~mask
;
5727 t4_write_reg(adap
, TP_PIO_DATA_A
, val
);
5731 * init_cong_ctrl - initialize congestion control parameters
5732 * @a: the alpha values for congestion control
5733 * @b: the beta values for congestion control
5735 * Initialize the congestion control parameters.
5737 static void init_cong_ctrl(unsigned short *a
, unsigned short *b
)
5739 a
[0] = a
[1] = a
[2] = a
[3] = a
[4] = a
[5] = a
[6] = a
[7] = a
[8] = 1;
5764 b
[0] = b
[1] = b
[2] = b
[3] = b
[4] = b
[5] = b
[6] = b
[7] = b
[8] = 0;
5767 b
[13] = b
[14] = b
[15] = b
[16] = 3;
5768 b
[17] = b
[18] = b
[19] = b
[20] = b
[21] = 4;
5769 b
[22] = b
[23] = b
[24] = b
[25] = b
[26] = b
[27] = 5;
5774 /* The minimum additive increment value for the congestion control table */
5775 #define CC_MIN_INCR 2U
5778 * t4_load_mtus - write the MTU and congestion control HW tables
5779 * @adap: the adapter
5780 * @mtus: the values for the MTU table
5781 * @alpha: the values for the congestion control alpha parameter
5782 * @beta: the values for the congestion control beta parameter
5784 * Write the HW MTU table with the supplied MTUs and the high-speed
5785 * congestion control table with the supplied alpha, beta, and MTUs.
5786 * We write the two tables together because the additive increments
5787 * depend on the MTUs.
5789 void t4_load_mtus(struct adapter
*adap
, const unsigned short *mtus
,
5790 const unsigned short *alpha
, const unsigned short *beta
)
5792 static const unsigned int avg_pkts
[NCCTRL_WIN
] = {
5793 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5794 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5795 28672, 40960, 57344, 81920, 114688, 163840, 229376
5800 for (i
= 0; i
< NMTUS
; ++i
) {
5801 unsigned int mtu
= mtus
[i
];
5802 unsigned int log2
= fls(mtu
);
5804 if (!(mtu
& ((1 << log2
) >> 2))) /* round */
5806 t4_write_reg(adap
, TP_MTU_TABLE_A
, MTUINDEX_V(i
) |
5807 MTUWIDTH_V(log2
) | MTUVALUE_V(mtu
));
5809 for (w
= 0; w
< NCCTRL_WIN
; ++w
) {
5812 inc
= max(((mtu
- 40) * alpha
[w
]) / avg_pkts
[w
],
5815 t4_write_reg(adap
, TP_CCTRL_TABLE_A
, (i
<< 21) |
5816 (w
<< 16) | (beta
[w
] << 13) | inc
);
5821 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5822 * clocks. The formula is
5824 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5826 * which is equivalent to
5828 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5830 static u64
chan_rate(struct adapter
*adap
, unsigned int bytes256
)
5832 u64 v
= bytes256
* adap
->params
.vpd
.cclk
;
5834 return v
* 62 + v
/ 2;
5838 * t4_get_chan_txrate - get the current per channel Tx rates
5839 * @adap: the adapter
5840 * @nic_rate: rates for NIC traffic
5841 * @ofld_rate: rates for offloaded traffic
5843 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5846 void t4_get_chan_txrate(struct adapter
*adap
, u64
*nic_rate
, u64
*ofld_rate
)
5850 v
= t4_read_reg(adap
, TP_TX_TRATE_A
);
5851 nic_rate
[0] = chan_rate(adap
, TNLRATE0_G(v
));
5852 nic_rate
[1] = chan_rate(adap
, TNLRATE1_G(v
));
5853 if (adap
->params
.arch
.nchan
== NCHAN
) {
5854 nic_rate
[2] = chan_rate(adap
, TNLRATE2_G(v
));
5855 nic_rate
[3] = chan_rate(adap
, TNLRATE3_G(v
));
5858 v
= t4_read_reg(adap
, TP_TX_ORATE_A
);
5859 ofld_rate
[0] = chan_rate(adap
, OFDRATE0_G(v
));
5860 ofld_rate
[1] = chan_rate(adap
, OFDRATE1_G(v
));
5861 if (adap
->params
.arch
.nchan
== NCHAN
) {
5862 ofld_rate
[2] = chan_rate(adap
, OFDRATE2_G(v
));
5863 ofld_rate
[3] = chan_rate(adap
, OFDRATE3_G(v
));
5868 * t4_set_trace_filter - configure one of the tracing filters
5869 * @adap: the adapter
5870 * @tp: the desired trace filter parameters
5871 * @idx: which filter to configure
5872 * @enable: whether to enable or disable the filter
5874 * Configures one of the tracing filters available in HW. If @enable is
5875 * %0 @tp is not examined and may be %NULL. The user is responsible to
5876 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5878 int t4_set_trace_filter(struct adapter
*adap
, const struct trace_params
*tp
,
5879 int idx
, int enable
)
5881 int i
, ofst
= idx
* 4;
5882 u32 data_reg
, mask_reg
, cfg
;
5885 t4_write_reg(adap
, MPS_TRC_FILTER_MATCH_CTL_A_A
+ ofst
, 0);
5889 cfg
= t4_read_reg(adap
, MPS_TRC_CFG_A
);
5890 if (cfg
& TRCMULTIFILTER_F
) {
5891 /* If multiple tracers are enabled, then maximum
5892 * capture size is 2.5KB (FIFO size of a single channel)
5893 * minus 2 flits for CPL_TRACE_PKT header.
5895 if (tp
->snap_len
> ((10 * 1024 / 4) - (2 * 8)))
5898 /* If multiple tracers are disabled, to avoid deadlocks
5899 * maximum packet capture size of 9600 bytes is recommended.
5900 * Also in this mode, only trace0 can be enabled and running.
5902 if (tp
->snap_len
> 9600 || idx
)
5906 if (tp
->port
> (is_t4(adap
->params
.chip
) ? 11 : 19) || tp
->invert
> 1 ||
5907 tp
->skip_len
> TFLENGTH_M
|| tp
->skip_ofst
> TFOFFSET_M
||
5908 tp
->min_len
> TFMINPKTSIZE_M
)
5911 /* stop the tracer we'll be changing */
5912 t4_write_reg(adap
, MPS_TRC_FILTER_MATCH_CTL_A_A
+ ofst
, 0);
5914 idx
*= (MPS_TRC_FILTER1_MATCH_A
- MPS_TRC_FILTER0_MATCH_A
);
5915 data_reg
= MPS_TRC_FILTER0_MATCH_A
+ idx
;
5916 mask_reg
= MPS_TRC_FILTER0_DONT_CARE_A
+ idx
;
5918 for (i
= 0; i
< TRACE_LEN
/ 4; i
++, data_reg
+= 4, mask_reg
+= 4) {
5919 t4_write_reg(adap
, data_reg
, tp
->data
[i
]);
5920 t4_write_reg(adap
, mask_reg
, ~tp
->mask
[i
]);
5922 t4_write_reg(adap
, MPS_TRC_FILTER_MATCH_CTL_B_A
+ ofst
,
5923 TFCAPTUREMAX_V(tp
->snap_len
) |
5924 TFMINPKTSIZE_V(tp
->min_len
));
5925 t4_write_reg(adap
, MPS_TRC_FILTER_MATCH_CTL_A_A
+ ofst
,
5926 TFOFFSET_V(tp
->skip_ofst
) | TFLENGTH_V(tp
->skip_len
) |
5927 (is_t4(adap
->params
.chip
) ?
5928 TFPORT_V(tp
->port
) | TFEN_F
| TFINVERTMATCH_V(tp
->invert
) :
5929 T5_TFPORT_V(tp
->port
) | T5_TFEN_F
|
5930 T5_TFINVERTMATCH_V(tp
->invert
)));
5936 * t4_get_trace_filter - query one of the tracing filters
5937 * @adap: the adapter
5938 * @tp: the current trace filter parameters
5939 * @idx: which trace filter to query
5940 * @enabled: non-zero if the filter is enabled
5942 * Returns the current settings of one of the HW tracing filters.
5944 void t4_get_trace_filter(struct adapter
*adap
, struct trace_params
*tp
, int idx
,
5948 int i
, ofst
= idx
* 4;
5949 u32 data_reg
, mask_reg
;
5951 ctla
= t4_read_reg(adap
, MPS_TRC_FILTER_MATCH_CTL_A_A
+ ofst
);
5952 ctlb
= t4_read_reg(adap
, MPS_TRC_FILTER_MATCH_CTL_B_A
+ ofst
);
5954 if (is_t4(adap
->params
.chip
)) {
5955 *enabled
= !!(ctla
& TFEN_F
);
5956 tp
->port
= TFPORT_G(ctla
);
5957 tp
->invert
= !!(ctla
& TFINVERTMATCH_F
);
5959 *enabled
= !!(ctla
& T5_TFEN_F
);
5960 tp
->port
= T5_TFPORT_G(ctla
);
5961 tp
->invert
= !!(ctla
& T5_TFINVERTMATCH_F
);
5963 tp
->snap_len
= TFCAPTUREMAX_G(ctlb
);
5964 tp
->min_len
= TFMINPKTSIZE_G(ctlb
);
5965 tp
->skip_ofst
= TFOFFSET_G(ctla
);
5966 tp
->skip_len
= TFLENGTH_G(ctla
);
5968 ofst
= (MPS_TRC_FILTER1_MATCH_A
- MPS_TRC_FILTER0_MATCH_A
) * idx
;
5969 data_reg
= MPS_TRC_FILTER0_MATCH_A
+ ofst
;
5970 mask_reg
= MPS_TRC_FILTER0_DONT_CARE_A
+ ofst
;
5972 for (i
= 0; i
< TRACE_LEN
/ 4; i
++, data_reg
+= 4, mask_reg
+= 4) {
5973 tp
->mask
[i
] = ~t4_read_reg(adap
, mask_reg
);
5974 tp
->data
[i
] = t4_read_reg(adap
, data_reg
) & tp
->mask
[i
];
5979 * t4_pmtx_get_stats - returns the HW stats from PMTX
5980 * @adap: the adapter
5981 * @cnt: where to store the count statistics
5982 * @cycles: where to store the cycle statistics
5984 * Returns performance statistics from PMTX.
5986 void t4_pmtx_get_stats(struct adapter
*adap
, u32 cnt
[], u64 cycles
[])
5991 for (i
= 0; i
< adap
->params
.arch
.pm_stats_cnt
; i
++) {
5992 t4_write_reg(adap
, PM_TX_STAT_CONFIG_A
, i
+ 1);
5993 cnt
[i
] = t4_read_reg(adap
, PM_TX_STAT_COUNT_A
);
5994 if (is_t4(adap
->params
.chip
)) {
5995 cycles
[i
] = t4_read_reg64(adap
, PM_TX_STAT_LSB_A
);
5997 t4_read_indirect(adap
, PM_TX_DBG_CTRL_A
,
5998 PM_TX_DBG_DATA_A
, data
, 2,
5999 PM_TX_DBG_STAT_MSB_A
);
6000 cycles
[i
] = (((u64
)data
[0] << 32) | data
[1]);
6006 * t4_pmrx_get_stats - returns the HW stats from PMRX
6007 * @adap: the adapter
6008 * @cnt: where to store the count statistics
6009 * @cycles: where to store the cycle statistics
6011 * Returns performance statistics from PMRX.
6013 void t4_pmrx_get_stats(struct adapter
*adap
, u32 cnt
[], u64 cycles
[])
6018 for (i
= 0; i
< adap
->params
.arch
.pm_stats_cnt
; i
++) {
6019 t4_write_reg(adap
, PM_RX_STAT_CONFIG_A
, i
+ 1);
6020 cnt
[i
] = t4_read_reg(adap
, PM_RX_STAT_COUNT_A
);
6021 if (is_t4(adap
->params
.chip
)) {
6022 cycles
[i
] = t4_read_reg64(adap
, PM_RX_STAT_LSB_A
);
6024 t4_read_indirect(adap
, PM_RX_DBG_CTRL_A
,
6025 PM_RX_DBG_DATA_A
, data
, 2,
6026 PM_RX_DBG_STAT_MSB_A
);
6027 cycles
[i
] = (((u64
)data
[0] << 32) | data
[1]);
6033 * compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
6034 * @adap: the adapter
6035 * @pidx: the port index
6037 * Computes and returns a bitmap indicating which MPS buffer groups are
6038 * associated with the given Port. Bit i is set if buffer group i is
6041 static inline unsigned int compute_mps_bg_map(struct adapter
*adapter
,
6044 unsigned int chip_version
, nports
;
6046 chip_version
= CHELSIO_CHIP_VERSION(adapter
->params
.chip
);
6047 nports
= 1 << NUMPORTS_G(t4_read_reg(adapter
, MPS_CMN_CTL_A
));
6049 switch (chip_version
) {
6054 case 2: return 3 << (2 * pidx
);
6055 case 4: return 1 << pidx
;
6061 case 2: return 1 << (2 * pidx
);
6066 dev_err(adapter
->pdev_dev
, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
6067 chip_version
, nports
);
6073 * t4_get_mps_bg_map - return the buffer groups associated with a port
6074 * @adapter: the adapter
6075 * @pidx: the port index
6077 * Returns a bitmap indicating which MPS buffer groups are associated
6078 * with the given Port. Bit i is set if buffer group i is used by the
6081 unsigned int t4_get_mps_bg_map(struct adapter
*adapter
, int pidx
)
6084 unsigned int nports
;
6086 nports
= 1 << NUMPORTS_G(t4_read_reg(adapter
, MPS_CMN_CTL_A
));
6087 if (pidx
>= nports
) {
6088 CH_WARN(adapter
, "MPS Port Index %d >= Nports %d\n",
6093 /* If we've already retrieved/computed this, just return the result.
6095 mps_bg_map
= adapter
->params
.mps_bg_map
;
6096 if (mps_bg_map
[pidx
])
6097 return mps_bg_map
[pidx
];
6099 /* Newer Firmware can tell us what the MPS Buffer Group Map is.
6100 * If we're talking to such Firmware, let it tell us. If the new
6101 * API isn't supported, revert back to old hardcoded way. The value
6102 * obtained from Firmware is encoded in below format:
6104 * val = (( MPSBGMAP[Port 3] << 24 ) |
6105 * ( MPSBGMAP[Port 2] << 16 ) |
6106 * ( MPSBGMAP[Port 1] << 8 ) |
6107 * ( MPSBGMAP[Port 0] << 0 ))
6109 if (adapter
->flags
& FW_OK
) {
6113 param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
6114 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_MPSBGMAP
));
6115 ret
= t4_query_params_ns(adapter
, adapter
->mbox
, adapter
->pf
,
6116 0, 1, ¶m
, &val
);
6120 /* Store the BG Map for all of the Ports in order to
6121 * avoid more calls to the Firmware in the future.
6123 for (p
= 0; p
< MAX_NPORTS
; p
++, val
>>= 8)
6124 mps_bg_map
[p
] = val
& 0xff;
6126 return mps_bg_map
[pidx
];
6130 /* Either we're not talking to the Firmware or we're dealing with
6131 * older Firmware which doesn't support the new API to get the MPS
6132 * Buffer Group Map. Fall back to computing it ourselves.
6134 mps_bg_map
[pidx
] = compute_mps_bg_map(adapter
, pidx
);
6135 return mps_bg_map
[pidx
];
6139 * t4_get_tp_ch_map - return TP ingress channels associated with a port
6140 * @adapter: the adapter
6141 * @pidx: the port index
6143 * Returns a bitmap indicating which TP Ingress Channels are associated
6144 * with a given Port. Bit i is set if TP Ingress Channel i is used by
6147 unsigned int t4_get_tp_ch_map(struct adapter
*adap
, int pidx
)
6149 unsigned int chip_version
= CHELSIO_CHIP_VERSION(adap
->params
.chip
);
6150 unsigned int nports
= 1 << NUMPORTS_G(t4_read_reg(adap
, MPS_CMN_CTL_A
));
6152 if (pidx
>= nports
) {
6153 dev_warn(adap
->pdev_dev
, "TP Port Index %d >= Nports %d\n",
6158 switch (chip_version
) {
6161 /* Note that this happens to be the same values as the MPS
6162 * Buffer Group Map for these Chips. But we replicate the code
6163 * here because they're really separate concepts.
6167 case 2: return 3 << (2 * pidx
);
6168 case 4: return 1 << pidx
;
6175 case 2: return 1 << pidx
;
6180 dev_err(adap
->pdev_dev
, "Need TP Channel Map for Chip %0x, Nports %d\n",
6181 chip_version
, nports
);
6186 * t4_get_port_type_description - return Port Type string description
6187 * @port_type: firmware Port Type enumeration
6189 const char *t4_get_port_type_description(enum fw_port_type port_type
)
6191 static const char *const port_type_description
[] = {
6217 if (port_type
< ARRAY_SIZE(port_type_description
))
6218 return port_type_description
[port_type
];
6223 * t4_get_port_stats_offset - collect port stats relative to a previous
6225 * @adap: The adapter
6227 * @stats: Current stats to fill
6228 * @offset: Previous stats snapshot
6230 void t4_get_port_stats_offset(struct adapter
*adap
, int idx
,
6231 struct port_stats
*stats
,
6232 struct port_stats
*offset
)
6237 t4_get_port_stats(adap
, idx
, stats
);
6238 for (i
= 0, s
= (u64
*)stats
, o
= (u64
*)offset
;
6239 i
< (sizeof(struct port_stats
) / sizeof(u64
));
6245 * t4_get_port_stats - collect port statistics
6246 * @adap: the adapter
6247 * @idx: the port index
6248 * @p: the stats structure to fill
6250 * Collect statistics related to the given port from HW.
6252 void t4_get_port_stats(struct adapter
*adap
, int idx
, struct port_stats
*p
)
6254 u32 bgmap
= t4_get_mps_bg_map(adap
, idx
);
6255 u32 stat_ctl
= t4_read_reg(adap
, MPS_STAT_CTL_A
);
6257 #define GET_STAT(name) \
6258 t4_read_reg64(adap, \
6259 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
6260 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
6261 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6263 p
->tx_octets
= GET_STAT(TX_PORT_BYTES
);
6264 p
->tx_frames
= GET_STAT(TX_PORT_FRAMES
);
6265 p
->tx_bcast_frames
= GET_STAT(TX_PORT_BCAST
);
6266 p
->tx_mcast_frames
= GET_STAT(TX_PORT_MCAST
);
6267 p
->tx_ucast_frames
= GET_STAT(TX_PORT_UCAST
);
6268 p
->tx_error_frames
= GET_STAT(TX_PORT_ERROR
);
6269 p
->tx_frames_64
= GET_STAT(TX_PORT_64B
);
6270 p
->tx_frames_65_127
= GET_STAT(TX_PORT_65B_127B
);
6271 p
->tx_frames_128_255
= GET_STAT(TX_PORT_128B_255B
);
6272 p
->tx_frames_256_511
= GET_STAT(TX_PORT_256B_511B
);
6273 p
->tx_frames_512_1023
= GET_STAT(TX_PORT_512B_1023B
);
6274 p
->tx_frames_1024_1518
= GET_STAT(TX_PORT_1024B_1518B
);
6275 p
->tx_frames_1519_max
= GET_STAT(TX_PORT_1519B_MAX
);
6276 p
->tx_drop
= GET_STAT(TX_PORT_DROP
);
6277 p
->tx_pause
= GET_STAT(TX_PORT_PAUSE
);
6278 p
->tx_ppp0
= GET_STAT(TX_PORT_PPP0
);
6279 p
->tx_ppp1
= GET_STAT(TX_PORT_PPP1
);
6280 p
->tx_ppp2
= GET_STAT(TX_PORT_PPP2
);
6281 p
->tx_ppp3
= GET_STAT(TX_PORT_PPP3
);
6282 p
->tx_ppp4
= GET_STAT(TX_PORT_PPP4
);
6283 p
->tx_ppp5
= GET_STAT(TX_PORT_PPP5
);
6284 p
->tx_ppp6
= GET_STAT(TX_PORT_PPP6
);
6285 p
->tx_ppp7
= GET_STAT(TX_PORT_PPP7
);
6287 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) >= CHELSIO_T5
) {
6288 if (stat_ctl
& COUNTPAUSESTATTX_F
)
6289 p
->tx_frames_64
-= p
->tx_pause
;
6290 if (stat_ctl
& COUNTPAUSEMCTX_F
)
6291 p
->tx_mcast_frames
-= p
->tx_pause
;
6293 p
->rx_octets
= GET_STAT(RX_PORT_BYTES
);
6294 p
->rx_frames
= GET_STAT(RX_PORT_FRAMES
);
6295 p
->rx_bcast_frames
= GET_STAT(RX_PORT_BCAST
);
6296 p
->rx_mcast_frames
= GET_STAT(RX_PORT_MCAST
);
6297 p
->rx_ucast_frames
= GET_STAT(RX_PORT_UCAST
);
6298 p
->rx_too_long
= GET_STAT(RX_PORT_MTU_ERROR
);
6299 p
->rx_jabber
= GET_STAT(RX_PORT_MTU_CRC_ERROR
);
6300 p
->rx_fcs_err
= GET_STAT(RX_PORT_CRC_ERROR
);
6301 p
->rx_len_err
= GET_STAT(RX_PORT_LEN_ERROR
);
6302 p
->rx_symbol_err
= GET_STAT(RX_PORT_SYM_ERROR
);
6303 p
->rx_runt
= GET_STAT(RX_PORT_LESS_64B
);
6304 p
->rx_frames_64
= GET_STAT(RX_PORT_64B
);
6305 p
->rx_frames_65_127
= GET_STAT(RX_PORT_65B_127B
);
6306 p
->rx_frames_128_255
= GET_STAT(RX_PORT_128B_255B
);
6307 p
->rx_frames_256_511
= GET_STAT(RX_PORT_256B_511B
);
6308 p
->rx_frames_512_1023
= GET_STAT(RX_PORT_512B_1023B
);
6309 p
->rx_frames_1024_1518
= GET_STAT(RX_PORT_1024B_1518B
);
6310 p
->rx_frames_1519_max
= GET_STAT(RX_PORT_1519B_MAX
);
6311 p
->rx_pause
= GET_STAT(RX_PORT_PAUSE
);
6312 p
->rx_ppp0
= GET_STAT(RX_PORT_PPP0
);
6313 p
->rx_ppp1
= GET_STAT(RX_PORT_PPP1
);
6314 p
->rx_ppp2
= GET_STAT(RX_PORT_PPP2
);
6315 p
->rx_ppp3
= GET_STAT(RX_PORT_PPP3
);
6316 p
->rx_ppp4
= GET_STAT(RX_PORT_PPP4
);
6317 p
->rx_ppp5
= GET_STAT(RX_PORT_PPP5
);
6318 p
->rx_ppp6
= GET_STAT(RX_PORT_PPP6
);
6319 p
->rx_ppp7
= GET_STAT(RX_PORT_PPP7
);
6321 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) >= CHELSIO_T5
) {
6322 if (stat_ctl
& COUNTPAUSESTATRX_F
)
6323 p
->rx_frames_64
-= p
->rx_pause
;
6324 if (stat_ctl
& COUNTPAUSEMCRX_F
)
6325 p
->rx_mcast_frames
-= p
->rx_pause
;
6328 p
->rx_ovflow0
= (bgmap
& 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME
) : 0;
6329 p
->rx_ovflow1
= (bgmap
& 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME
) : 0;
6330 p
->rx_ovflow2
= (bgmap
& 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME
) : 0;
6331 p
->rx_ovflow3
= (bgmap
& 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME
) : 0;
6332 p
->rx_trunc0
= (bgmap
& 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME
) : 0;
6333 p
->rx_trunc1
= (bgmap
& 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME
) : 0;
6334 p
->rx_trunc2
= (bgmap
& 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME
) : 0;
6335 p
->rx_trunc3
= (bgmap
& 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME
) : 0;
6342 * t4_get_lb_stats - collect loopback port statistics
6343 * @adap: the adapter
6344 * @idx: the loopback port index
6345 * @p: the stats structure to fill
6347 * Return HW statistics for the given loopback port.
6349 void t4_get_lb_stats(struct adapter
*adap
, int idx
, struct lb_port_stats
*p
)
6351 u32 bgmap
= t4_get_mps_bg_map(adap
, idx
);
6353 #define GET_STAT(name) \
6354 t4_read_reg64(adap, \
6355 (is_t4(adap->params.chip) ? \
6356 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
6357 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
6358 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6360 p
->octets
= GET_STAT(BYTES
);
6361 p
->frames
= GET_STAT(FRAMES
);
6362 p
->bcast_frames
= GET_STAT(BCAST
);
6363 p
->mcast_frames
= GET_STAT(MCAST
);
6364 p
->ucast_frames
= GET_STAT(UCAST
);
6365 p
->error_frames
= GET_STAT(ERROR
);
6367 p
->frames_64
= GET_STAT(64B
);
6368 p
->frames_65_127
= GET_STAT(65B_127B
);
6369 p
->frames_128_255
= GET_STAT(128B_255B
);
6370 p
->frames_256_511
= GET_STAT(256B_511B
);
6371 p
->frames_512_1023
= GET_STAT(512B_1023B
);
6372 p
->frames_1024_1518
= GET_STAT(1024B_1518B
);
6373 p
->frames_1519_max
= GET_STAT(1519B_MAX
);
6374 p
->drop
= GET_STAT(DROP_FRAMES
);
6376 p
->ovflow0
= (bgmap
& 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME
) : 0;
6377 p
->ovflow1
= (bgmap
& 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME
) : 0;
6378 p
->ovflow2
= (bgmap
& 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME
) : 0;
6379 p
->ovflow3
= (bgmap
& 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME
) : 0;
6380 p
->trunc0
= (bgmap
& 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME
) : 0;
6381 p
->trunc1
= (bgmap
& 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME
) : 0;
6382 p
->trunc2
= (bgmap
& 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME
) : 0;
6383 p
->trunc3
= (bgmap
& 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME
) : 0;
6389 /* t4_mk_filtdelwr - create a delete filter WR
6390 * @ftid: the filter ID
6391 * @wr: the filter work request to populate
6392 * @qid: ingress queue to receive the delete notification
6394 * Creates a filter work request to delete the supplied filter. If @qid is
6395 * negative the delete notification is suppressed.
6397 void t4_mk_filtdelwr(unsigned int ftid
, struct fw_filter_wr
*wr
, int qid
)
6399 memset(wr
, 0, sizeof(*wr
));
6400 wr
->op_pkd
= cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR
));
6401 wr
->len16_pkd
= cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr
) / 16));
6402 wr
->tid_to_iq
= cpu_to_be32(FW_FILTER_WR_TID_V(ftid
) |
6403 FW_FILTER_WR_NOREPLY_V(qid
< 0));
6404 wr
->del_filter_to_l2tix
= cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F
);
6406 wr
->rx_chan_rx_rpl_iq
=
6407 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid
));
6410 #define INIT_CMD(var, cmd, rd_wr) do { \
6411 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
6412 FW_CMD_REQUEST_F | \
6413 FW_CMD_##rd_wr##_F); \
6414 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6417 int t4_fwaddrspace_write(struct adapter
*adap
, unsigned int mbox
,
6421 struct fw_ldst_cmd c
;
6423 memset(&c
, 0, sizeof(c
));
6424 ldst_addrspace
= FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE
);
6425 c
.op_to_addrspace
= cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
6429 c
.cycles_to_len16
= cpu_to_be32(FW_LEN16(c
));
6430 c
.u
.addrval
.addr
= cpu_to_be32(addr
);
6431 c
.u
.addrval
.val
= cpu_to_be32(val
);
6433 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
6437 * t4_mdio_rd - read a PHY register through MDIO
6438 * @adap: the adapter
6439 * @mbox: mailbox to use for the FW command
6440 * @phy_addr: the PHY address
6441 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6442 * @reg: the register to read
6443 * @valp: where to store the value
6445 * Issues a FW command through the given mailbox to read a PHY register.
6447 int t4_mdio_rd(struct adapter
*adap
, unsigned int mbox
, unsigned int phy_addr
,
6448 unsigned int mmd
, unsigned int reg
, u16
*valp
)
6452 struct fw_ldst_cmd c
;
6454 memset(&c
, 0, sizeof(c
));
6455 ldst_addrspace
= FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO
);
6456 c
.op_to_addrspace
= cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
6457 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
6459 c
.cycles_to_len16
= cpu_to_be32(FW_LEN16(c
));
6460 c
.u
.mdio
.paddr_mmd
= cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr
) |
6461 FW_LDST_CMD_MMD_V(mmd
));
6462 c
.u
.mdio
.raddr
= cpu_to_be16(reg
);
6464 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
6466 *valp
= be16_to_cpu(c
.u
.mdio
.rval
);
6471 * t4_mdio_wr - write a PHY register through MDIO
6472 * @adap: the adapter
6473 * @mbox: mailbox to use for the FW command
6474 * @phy_addr: the PHY address
6475 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6476 * @reg: the register to write
6477 * @valp: value to write
6479 * Issues a FW command through the given mailbox to write a PHY register.
6481 int t4_mdio_wr(struct adapter
*adap
, unsigned int mbox
, unsigned int phy_addr
,
6482 unsigned int mmd
, unsigned int reg
, u16 val
)
6485 struct fw_ldst_cmd c
;
6487 memset(&c
, 0, sizeof(c
));
6488 ldst_addrspace
= FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO
);
6489 c
.op_to_addrspace
= cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
6490 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
6492 c
.cycles_to_len16
= cpu_to_be32(FW_LEN16(c
));
6493 c
.u
.mdio
.paddr_mmd
= cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr
) |
6494 FW_LDST_CMD_MMD_V(mmd
));
6495 c
.u
.mdio
.raddr
= cpu_to_be16(reg
);
6496 c
.u
.mdio
.rval
= cpu_to_be16(val
);
6498 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
6502 * t4_sge_decode_idma_state - decode the idma state
6503 * @adap: the adapter
6504 * @state: the state idma is stuck in
6506 void t4_sge_decode_idma_state(struct adapter
*adapter
, int state
)
6508 static const char * const t4_decode
[] = {
6510 "IDMA_PUSH_MORE_CPL_FIFO",
6511 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6513 "IDMA_PHYSADDR_SEND_PCIEHDR",
6514 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6515 "IDMA_PHYSADDR_SEND_PAYLOAD",
6516 "IDMA_SEND_FIFO_TO_IMSG",
6517 "IDMA_FL_REQ_DATA_FL_PREP",
6518 "IDMA_FL_REQ_DATA_FL",
6520 "IDMA_FL_H_REQ_HEADER_FL",
6521 "IDMA_FL_H_SEND_PCIEHDR",
6522 "IDMA_FL_H_PUSH_CPL_FIFO",
6523 "IDMA_FL_H_SEND_CPL",
6524 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6525 "IDMA_FL_H_SEND_IP_HDR",
6526 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6527 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6528 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6529 "IDMA_FL_D_SEND_PCIEHDR",
6530 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6531 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6532 "IDMA_FL_SEND_PCIEHDR",
6533 "IDMA_FL_PUSH_CPL_FIFO",
6535 "IDMA_FL_SEND_PAYLOAD_FIRST",
6536 "IDMA_FL_SEND_PAYLOAD",
6537 "IDMA_FL_REQ_NEXT_DATA_FL",
6538 "IDMA_FL_SEND_NEXT_PCIEHDR",
6539 "IDMA_FL_SEND_PADDING",
6540 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6541 "IDMA_FL_SEND_FIFO_TO_IMSG",
6542 "IDMA_FL_REQ_DATAFL_DONE",
6543 "IDMA_FL_REQ_HEADERFL_DONE",
6545 static const char * const t5_decode
[] = {
6548 "IDMA_PUSH_MORE_CPL_FIFO",
6549 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6550 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6551 "IDMA_PHYSADDR_SEND_PCIEHDR",
6552 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6553 "IDMA_PHYSADDR_SEND_PAYLOAD",
6554 "IDMA_SEND_FIFO_TO_IMSG",
6555 "IDMA_FL_REQ_DATA_FL",
6557 "IDMA_FL_DROP_SEND_INC",
6558 "IDMA_FL_H_REQ_HEADER_FL",
6559 "IDMA_FL_H_SEND_PCIEHDR",
6560 "IDMA_FL_H_PUSH_CPL_FIFO",
6561 "IDMA_FL_H_SEND_CPL",
6562 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6563 "IDMA_FL_H_SEND_IP_HDR",
6564 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6565 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6566 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6567 "IDMA_FL_D_SEND_PCIEHDR",
6568 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6569 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6570 "IDMA_FL_SEND_PCIEHDR",
6571 "IDMA_FL_PUSH_CPL_FIFO",
6573 "IDMA_FL_SEND_PAYLOAD_FIRST",
6574 "IDMA_FL_SEND_PAYLOAD",
6575 "IDMA_FL_REQ_NEXT_DATA_FL",
6576 "IDMA_FL_SEND_NEXT_PCIEHDR",
6577 "IDMA_FL_SEND_PADDING",
6578 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6580 static const char * const t6_decode
[] = {
6582 "IDMA_PUSH_MORE_CPL_FIFO",
6583 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6584 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6585 "IDMA_PHYSADDR_SEND_PCIEHDR",
6586 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6587 "IDMA_PHYSADDR_SEND_PAYLOAD",
6588 "IDMA_FL_REQ_DATA_FL",
6590 "IDMA_FL_DROP_SEND_INC",
6591 "IDMA_FL_H_REQ_HEADER_FL",
6592 "IDMA_FL_H_SEND_PCIEHDR",
6593 "IDMA_FL_H_PUSH_CPL_FIFO",
6594 "IDMA_FL_H_SEND_CPL",
6595 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6596 "IDMA_FL_H_SEND_IP_HDR",
6597 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6598 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6599 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6600 "IDMA_FL_D_SEND_PCIEHDR",
6601 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6602 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6603 "IDMA_FL_SEND_PCIEHDR",
6604 "IDMA_FL_PUSH_CPL_FIFO",
6606 "IDMA_FL_SEND_PAYLOAD_FIRST",
6607 "IDMA_FL_SEND_PAYLOAD",
6608 "IDMA_FL_REQ_NEXT_DATA_FL",
6609 "IDMA_FL_SEND_NEXT_PCIEHDR",
6610 "IDMA_FL_SEND_PADDING",
6611 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6613 static const u32 sge_regs
[] = {
6614 SGE_DEBUG_DATA_LOW_INDEX_2_A
,
6615 SGE_DEBUG_DATA_LOW_INDEX_3_A
,
6616 SGE_DEBUG_DATA_HIGH_INDEX_10_A
,
6618 const char **sge_idma_decode
;
6619 int sge_idma_decode_nstates
;
6621 unsigned int chip_version
= CHELSIO_CHIP_VERSION(adapter
->params
.chip
);
6623 /* Select the right set of decode strings to dump depending on the
6624 * adapter chip type.
6626 switch (chip_version
) {
6628 sge_idma_decode
= (const char **)t4_decode
;
6629 sge_idma_decode_nstates
= ARRAY_SIZE(t4_decode
);
6633 sge_idma_decode
= (const char **)t5_decode
;
6634 sge_idma_decode_nstates
= ARRAY_SIZE(t5_decode
);
6638 sge_idma_decode
= (const char **)t6_decode
;
6639 sge_idma_decode_nstates
= ARRAY_SIZE(t6_decode
);
6643 dev_err(adapter
->pdev_dev
,
6644 "Unsupported chip version %d\n", chip_version
);
6648 if (is_t4(adapter
->params
.chip
)) {
6649 sge_idma_decode
= (const char **)t4_decode
;
6650 sge_idma_decode_nstates
= ARRAY_SIZE(t4_decode
);
6652 sge_idma_decode
= (const char **)t5_decode
;
6653 sge_idma_decode_nstates
= ARRAY_SIZE(t5_decode
);
6656 if (state
< sge_idma_decode_nstates
)
6657 CH_WARN(adapter
, "idma state %s\n", sge_idma_decode
[state
]);
6659 CH_WARN(adapter
, "idma state %d unknown\n", state
);
6661 for (i
= 0; i
< ARRAY_SIZE(sge_regs
); i
++)
6662 CH_WARN(adapter
, "SGE register %#x value %#x\n",
6663 sge_regs
[i
], t4_read_reg(adapter
, sge_regs
[i
]));
6667 * t4_sge_ctxt_flush - flush the SGE context cache
6668 * @adap: the adapter
6669 * @mbox: mailbox to use for the FW command
6670 * @ctx_type: Egress or Ingress
6672 * Issues a FW command through the given mailbox to flush the
6673 * SGE context cache.
6675 int t4_sge_ctxt_flush(struct adapter
*adap
, unsigned int mbox
, int ctxt_type
)
6679 struct fw_ldst_cmd c
;
6681 memset(&c
, 0, sizeof(c
));
6682 ldst_addrspace
= FW_LDST_CMD_ADDRSPACE_V(ctxt_type
== CTXT_EGRESS
?
6683 FW_LDST_ADDRSPC_SGE_EGRC
:
6684 FW_LDST_ADDRSPC_SGE_INGC
);
6685 c
.op_to_addrspace
= cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
6686 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
6688 c
.cycles_to_len16
= cpu_to_be32(FW_LEN16(c
));
6689 c
.u
.idctxt
.msg_ctxtflush
= cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F
);
6691 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
6696 * t4_fw_hello - establish communication with FW
6697 * @adap: the adapter
6698 * @mbox: mailbox to use for the FW command
6699 * @evt_mbox: mailbox to receive async FW events
6700 * @master: specifies the caller's willingness to be the device master
6701 * @state: returns the current device state (if non-NULL)
6703 * Issues a command to establish communication with FW. Returns either
6704 * an error (negative integer) or the mailbox of the Master PF.
6706 int t4_fw_hello(struct adapter
*adap
, unsigned int mbox
, unsigned int evt_mbox
,
6707 enum dev_master master
, enum dev_state
*state
)
6710 struct fw_hello_cmd c
;
6712 unsigned int master_mbox
;
6713 int retries
= FW_CMD_HELLO_RETRIES
;
6716 memset(&c
, 0, sizeof(c
));
6717 INIT_CMD(c
, HELLO
, WRITE
);
6718 c
.err_to_clearinit
= cpu_to_be32(
6719 FW_HELLO_CMD_MASTERDIS_V(master
== MASTER_CANT
) |
6720 FW_HELLO_CMD_MASTERFORCE_V(master
== MASTER_MUST
) |
6721 FW_HELLO_CMD_MBMASTER_V(master
== MASTER_MUST
?
6722 mbox
: FW_HELLO_CMD_MBMASTER_M
) |
6723 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox
) |
6724 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os
) |
6725 FW_HELLO_CMD_CLEARINIT_F
);
6728 * Issue the HELLO command to the firmware. If it's not successful
6729 * but indicates that we got a "busy" or "timeout" condition, retry
6730 * the HELLO until we exhaust our retry limit. If we do exceed our
6731 * retry limit, check to see if the firmware left us any error
6732 * information and report that if so.
6734 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
6736 if ((ret
== -EBUSY
|| ret
== -ETIMEDOUT
) && retries
-- > 0)
6738 if (t4_read_reg(adap
, PCIE_FW_A
) & PCIE_FW_ERR_F
)
6739 t4_report_fw_error(adap
);
6743 v
= be32_to_cpu(c
.err_to_clearinit
);
6744 master_mbox
= FW_HELLO_CMD_MBMASTER_G(v
);
6746 if (v
& FW_HELLO_CMD_ERR_F
)
6747 *state
= DEV_STATE_ERR
;
6748 else if (v
& FW_HELLO_CMD_INIT_F
)
6749 *state
= DEV_STATE_INIT
;
6751 *state
= DEV_STATE_UNINIT
;
6755 * If we're not the Master PF then we need to wait around for the
6756 * Master PF Driver to finish setting up the adapter.
6758 * Note that we also do this wait if we're a non-Master-capable PF and
6759 * there is no current Master PF; a Master PF may show up momentarily
6760 * and we wouldn't want to fail pointlessly. (This can happen when an
6761 * OS loads lots of different drivers rapidly at the same time). In
6762 * this case, the Master PF returned by the firmware will be
6763 * PCIE_FW_MASTER_M so the test below will work ...
6765 if ((v
& (FW_HELLO_CMD_ERR_F
|FW_HELLO_CMD_INIT_F
)) == 0 &&
6766 master_mbox
!= mbox
) {
6767 int waiting
= FW_CMD_HELLO_TIMEOUT
;
6770 * Wait for the firmware to either indicate an error or
6771 * initialized state. If we see either of these we bail out
6772 * and report the issue to the caller. If we exhaust the
6773 * "hello timeout" and we haven't exhausted our retries, try
6774 * again. Otherwise bail with a timeout error.
6783 * If neither Error nor Initialialized are indicated
6784 * by the firmware keep waiting till we exaust our
6785 * timeout ... and then retry if we haven't exhausted
6788 pcie_fw
= t4_read_reg(adap
, PCIE_FW_A
);
6789 if (!(pcie_fw
& (PCIE_FW_ERR_F
|PCIE_FW_INIT_F
))) {
6800 * We either have an Error or Initialized condition
6801 * report errors preferentially.
6804 if (pcie_fw
& PCIE_FW_ERR_F
)
6805 *state
= DEV_STATE_ERR
;
6806 else if (pcie_fw
& PCIE_FW_INIT_F
)
6807 *state
= DEV_STATE_INIT
;
6811 * If we arrived before a Master PF was selected and
6812 * there's not a valid Master PF, grab its identity
6815 if (master_mbox
== PCIE_FW_MASTER_M
&&
6816 (pcie_fw
& PCIE_FW_MASTER_VLD_F
))
6817 master_mbox
= PCIE_FW_MASTER_G(pcie_fw
);
6826 * t4_fw_bye - end communication with FW
6827 * @adap: the adapter
6828 * @mbox: mailbox to use for the FW command
6830 * Issues a command to terminate communication with FW.
6832 int t4_fw_bye(struct adapter
*adap
, unsigned int mbox
)
6834 struct fw_bye_cmd c
;
6836 memset(&c
, 0, sizeof(c
));
6837 INIT_CMD(c
, BYE
, WRITE
);
6838 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
6842 * t4_init_cmd - ask FW to initialize the device
6843 * @adap: the adapter
6844 * @mbox: mailbox to use for the FW command
6846 * Issues a command to FW to partially initialize the device. This
6847 * performs initialization that generally doesn't depend on user input.
6849 int t4_early_init(struct adapter
*adap
, unsigned int mbox
)
6851 struct fw_initialize_cmd c
;
6853 memset(&c
, 0, sizeof(c
));
6854 INIT_CMD(c
, INITIALIZE
, WRITE
);
6855 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
6859 * t4_fw_reset - issue a reset to FW
6860 * @adap: the adapter
6861 * @mbox: mailbox to use for the FW command
6862 * @reset: specifies the type of reset to perform
6864 * Issues a reset command of the specified type to FW.
6866 int t4_fw_reset(struct adapter
*adap
, unsigned int mbox
, int reset
)
6868 struct fw_reset_cmd c
;
6870 memset(&c
, 0, sizeof(c
));
6871 INIT_CMD(c
, RESET
, WRITE
);
6872 c
.val
= cpu_to_be32(reset
);
6873 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
6877 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6878 * @adap: the adapter
6879 * @mbox: mailbox to use for the FW RESET command (if desired)
6880 * @force: force uP into RESET even if FW RESET command fails
6882 * Issues a RESET command to firmware (if desired) with a HALT indication
6883 * and then puts the microprocessor into RESET state. The RESET command
6884 * will only be issued if a legitimate mailbox is provided (mbox <=
6885 * PCIE_FW_MASTER_M).
6887 * This is generally used in order for the host to safely manipulate the
6888 * adapter without fear of conflicting with whatever the firmware might
6889 * be doing. The only way out of this state is to RESTART the firmware
6892 static int t4_fw_halt(struct adapter
*adap
, unsigned int mbox
, int force
)
6897 * If a legitimate mailbox is provided, issue a RESET command
6898 * with a HALT indication.
6900 if (mbox
<= PCIE_FW_MASTER_M
) {
6901 struct fw_reset_cmd c
;
6903 memset(&c
, 0, sizeof(c
));
6904 INIT_CMD(c
, RESET
, WRITE
);
6905 c
.val
= cpu_to_be32(PIORST_F
| PIORSTMODE_F
);
6906 c
.halt_pkd
= cpu_to_be32(FW_RESET_CMD_HALT_F
);
6907 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
6911 * Normally we won't complete the operation if the firmware RESET
6912 * command fails but if our caller insists we'll go ahead and put the
6913 * uP into RESET. This can be useful if the firmware is hung or even
6914 * missing ... We'll have to take the risk of putting the uP into
6915 * RESET without the cooperation of firmware in that case.
6917 * We also force the firmware's HALT flag to be on in case we bypassed
6918 * the firmware RESET command above or we're dealing with old firmware
6919 * which doesn't have the HALT capability. This will serve as a flag
6920 * for the incoming firmware to know that it's coming out of a HALT
6921 * rather than a RESET ... if it's new enough to understand that ...
6923 if (ret
== 0 || force
) {
6924 t4_set_reg_field(adap
, CIM_BOOT_CFG_A
, UPCRST_F
, UPCRST_F
);
6925 t4_set_reg_field(adap
, PCIE_FW_A
, PCIE_FW_HALT_F
,
6930 * And we always return the result of the firmware RESET command
6931 * even when we force the uP into RESET ...
6937 * t4_fw_restart - restart the firmware by taking the uP out of RESET
6938 * @adap: the adapter
6939 * @reset: if we want to do a RESET to restart things
6941 * Restart firmware previously halted by t4_fw_halt(). On successful
6942 * return the previous PF Master remains as the new PF Master and there
6943 * is no need to issue a new HELLO command, etc.
6945 * We do this in two ways:
6947 * 1. If we're dealing with newer firmware we'll simply want to take
6948 * the chip's microprocessor out of RESET. This will cause the
6949 * firmware to start up from its start vector. And then we'll loop
6950 * until the firmware indicates it's started again (PCIE_FW.HALT
6951 * reset to 0) or we timeout.
6953 * 2. If we're dealing with older firmware then we'll need to RESET
6954 * the chip since older firmware won't recognize the PCIE_FW.HALT
6955 * flag and automatically RESET itself on startup.
6957 static int t4_fw_restart(struct adapter
*adap
, unsigned int mbox
, int reset
)
6961 * Since we're directing the RESET instead of the firmware
6962 * doing it automatically, we need to clear the PCIE_FW.HALT
6965 t4_set_reg_field(adap
, PCIE_FW_A
, PCIE_FW_HALT_F
, 0);
6968 * If we've been given a valid mailbox, first try to get the
6969 * firmware to do the RESET. If that works, great and we can
6970 * return success. Otherwise, if we haven't been given a
6971 * valid mailbox or the RESET command failed, fall back to
6972 * hitting the chip with a hammer.
6974 if (mbox
<= PCIE_FW_MASTER_M
) {
6975 t4_set_reg_field(adap
, CIM_BOOT_CFG_A
, UPCRST_F
, 0);
6977 if (t4_fw_reset(adap
, mbox
,
6978 PIORST_F
| PIORSTMODE_F
) == 0)
6982 t4_write_reg(adap
, PL_RST_A
, PIORST_F
| PIORSTMODE_F
);
6987 t4_set_reg_field(adap
, CIM_BOOT_CFG_A
, UPCRST_F
, 0);
6988 for (ms
= 0; ms
< FW_CMD_MAX_TIMEOUT
; ) {
6989 if (!(t4_read_reg(adap
, PCIE_FW_A
) & PCIE_FW_HALT_F
))
7000 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
7001 * @adap: the adapter
7002 * @mbox: mailbox to use for the FW RESET command (if desired)
7003 * @fw_data: the firmware image to write
7005 * @force: force upgrade even if firmware doesn't cooperate
7007 * Perform all of the steps necessary for upgrading an adapter's
7008 * firmware image. Normally this requires the cooperation of the
7009 * existing firmware in order to halt all existing activities
7010 * but if an invalid mailbox token is passed in we skip that step
7011 * (though we'll still put the adapter microprocessor into RESET in
7014 * On successful return the new firmware will have been loaded and
7015 * the adapter will have been fully RESET losing all previous setup
7016 * state. On unsuccessful return the adapter may be completely hosed ...
7017 * positive errno indicates that the adapter is ~probably~ intact, a
7018 * negative errno indicates that things are looking bad ...
7020 int t4_fw_upgrade(struct adapter
*adap
, unsigned int mbox
,
7021 const u8
*fw_data
, unsigned int size
, int force
)
7023 const struct fw_hdr
*fw_hdr
= (const struct fw_hdr
*)fw_data
;
7026 if (!t4_fw_matches_chip(adap
, fw_hdr
))
7029 /* Disable FW_OK flag so that mbox commands with FW_OK flag set
7030 * wont be sent when we are flashing FW.
7032 adap
->flags
&= ~FW_OK
;
7034 ret
= t4_fw_halt(adap
, mbox
, force
);
7035 if (ret
< 0 && !force
)
7038 ret
= t4_load_fw(adap
, fw_data
, size
);
7043 * If there was a Firmware Configuration File stored in FLASH,
7044 * there's a good chance that it won't be compatible with the new
7045 * Firmware. In order to prevent difficult to diagnose adapter
7046 * initialization issues, we clear out the Firmware Configuration File
7047 * portion of the FLASH . The user will need to re-FLASH a new
7048 * Firmware Configuration File which is compatible with the new
7049 * Firmware if that's desired.
7051 (void)t4_load_cfg(adap
, NULL
, 0);
7054 * Older versions of the firmware don't understand the new
7055 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
7056 * restart. So for newly loaded older firmware we'll have to do the
7057 * RESET for it so it starts up on a clean slate. We can tell if
7058 * the newly loaded firmware will handle this right by checking
7059 * its header flags to see if it advertises the capability.
7061 reset
= ((be32_to_cpu(fw_hdr
->flags
) & FW_HDR_FLAGS_RESET_HALT
) == 0);
7062 ret
= t4_fw_restart(adap
, mbox
, reset
);
7064 /* Grab potentially new Firmware Device Log parameters so we can see
7065 * how healthy the new Firmware is. It's okay to contact the new
7066 * Firmware for these parameters even though, as far as it's
7067 * concerned, we've never said "HELLO" to it ...
7069 (void)t4_init_devlog_params(adap
);
7071 adap
->flags
|= FW_OK
;
7076 * t4_fl_pkt_align - return the fl packet alignment
7077 * @adap: the adapter
7079 * T4 has a single field to specify the packing and padding boundary.
7080 * T5 onwards has separate fields for this and hence the alignment for
7081 * next packet offset is maximum of these two.
7084 int t4_fl_pkt_align(struct adapter
*adap
)
7086 u32 sge_control
, sge_control2
;
7087 unsigned int ingpadboundary
, ingpackboundary
, fl_align
, ingpad_shift
;
7089 sge_control
= t4_read_reg(adap
, SGE_CONTROL_A
);
7091 /* T4 uses a single control field to specify both the PCIe Padding and
7092 * Packing Boundary. T5 introduced the ability to specify these
7093 * separately. The actual Ingress Packet Data alignment boundary
7094 * within Packed Buffer Mode is the maximum of these two
7095 * specifications. (Note that it makes no real practical sense to
7096 * have the Pading Boudary be larger than the Packing Boundary but you
7097 * could set the chip up that way and, in fact, legacy T4 code would
7098 * end doing this because it would initialize the Padding Boundary and
7099 * leave the Packing Boundary initialized to 0 (16 bytes).)
7100 * Padding Boundary values in T6 starts from 8B,
7101 * where as it is 32B for T4 and T5.
7103 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) <= CHELSIO_T5
)
7104 ingpad_shift
= INGPADBOUNDARY_SHIFT_X
;
7106 ingpad_shift
= T6_INGPADBOUNDARY_SHIFT_X
;
7108 ingpadboundary
= 1 << (INGPADBOUNDARY_G(sge_control
) + ingpad_shift
);
7110 fl_align
= ingpadboundary
;
7111 if (!is_t4(adap
->params
.chip
)) {
7112 /* T5 has a weird interpretation of one of the PCIe Packing
7113 * Boundary values. No idea why ...
7115 sge_control2
= t4_read_reg(adap
, SGE_CONTROL2_A
);
7116 ingpackboundary
= INGPACKBOUNDARY_G(sge_control2
);
7117 if (ingpackboundary
== INGPACKBOUNDARY_16B_X
)
7118 ingpackboundary
= 16;
7120 ingpackboundary
= 1 << (ingpackboundary
+
7121 INGPACKBOUNDARY_SHIFT_X
);
7123 fl_align
= max(ingpadboundary
, ingpackboundary
);
7129 * t4_fixup_host_params - fix up host-dependent parameters
7130 * @adap: the adapter
7131 * @page_size: the host's Base Page Size
7132 * @cache_line_size: the host's Cache Line Size
7134 * Various registers in T4 contain values which are dependent on the
7135 * host's Base Page and Cache Line Sizes. This function will fix all of
7136 * those registers with the appropriate values as passed in ...
7138 int t4_fixup_host_params(struct adapter
*adap
, unsigned int page_size
,
7139 unsigned int cache_line_size
)
7141 unsigned int page_shift
= fls(page_size
) - 1;
7142 unsigned int stat_len
= cache_line_size
> 64 ? 128 : 64;
7143 unsigned int fl_align
= cache_line_size
< 32 ? 32 : cache_line_size
;
7144 unsigned int fl_align_log
= fls(fl_align
) - 1;
7146 if (is_t4(adap
->params
.chip
)) {
7147 t4_set_reg_field(adap
, SGE_CONTROL_A
,
7148 INGPADBOUNDARY_V(INGPADBOUNDARY_M
) |
7149 EGRSTATUSPAGESIZE_F
,
7150 INGPADBOUNDARY_V(fl_align_log
-
7151 INGPADBOUNDARY_SHIFT_X
) |
7152 EGRSTATUSPAGESIZE_V(stat_len
!= 64));
7154 unsigned int pack_align
;
7155 unsigned int ingpad
, ingpack
;
7156 unsigned int pcie_cap
;
7158 /* T5 introduced the separation of the Free List Padding and
7159 * Packing Boundaries. Thus, we can select a smaller Padding
7160 * Boundary to avoid uselessly chewing up PCIe Link and Memory
7161 * Bandwidth, and use a Packing Boundary which is large enough
7162 * to avoid false sharing between CPUs, etc.
7164 * For the PCI Link, the smaller the Padding Boundary the
7165 * better. For the Memory Controller, a smaller Padding
7166 * Boundary is better until we cross under the Memory Line
7167 * Size (the minimum unit of transfer to/from Memory). If we
7168 * have a Padding Boundary which is smaller than the Memory
7169 * Line Size, that'll involve a Read-Modify-Write cycle on the
7170 * Memory Controller which is never good.
7173 /* We want the Packing Boundary to be based on the Cache Line
7174 * Size in order to help avoid False Sharing performance
7175 * issues between CPUs, etc. We also want the Packing
7176 * Boundary to incorporate the PCI-E Maximum Payload Size. We
7177 * get best performance when the Packing Boundary is a
7178 * multiple of the Maximum Payload Size.
7180 pack_align
= fl_align
;
7181 pcie_cap
= pci_find_capability(adap
->pdev
, PCI_CAP_ID_EXP
);
7183 unsigned int mps
, mps_log
;
7186 /* The PCIe Device Control Maximum Payload Size field
7187 * [bits 7:5] encodes sizes as powers of 2 starting at
7190 pci_read_config_word(adap
->pdev
,
7191 pcie_cap
+ PCI_EXP_DEVCTL
,
7193 mps_log
= ((devctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5) + 7;
7195 if (mps
> pack_align
)
7199 /* N.B. T5/T6 have a crazy special interpretation of the "0"
7200 * value for the Packing Boundary. This corresponds to 16
7201 * bytes instead of the expected 32 bytes. So if we want 32
7202 * bytes, the best we can really do is 64 bytes ...
7204 if (pack_align
<= 16) {
7205 ingpack
= INGPACKBOUNDARY_16B_X
;
7207 } else if (pack_align
== 32) {
7208 ingpack
= INGPACKBOUNDARY_64B_X
;
7211 unsigned int pack_align_log
= fls(pack_align
) - 1;
7213 ingpack
= pack_align_log
- INGPACKBOUNDARY_SHIFT_X
;
7214 fl_align
= pack_align
;
7217 /* Use the smallest Ingress Padding which isn't smaller than
7218 * the Memory Controller Read/Write Size. We'll take that as
7219 * being 8 bytes since we don't know of any system with a
7220 * wider Memory Controller Bus Width.
7222 if (is_t5(adap
->params
.chip
))
7223 ingpad
= INGPADBOUNDARY_32B_X
;
7225 ingpad
= T6_INGPADBOUNDARY_8B_X
;
7227 t4_set_reg_field(adap
, SGE_CONTROL_A
,
7228 INGPADBOUNDARY_V(INGPADBOUNDARY_M
) |
7229 EGRSTATUSPAGESIZE_F
,
7230 INGPADBOUNDARY_V(ingpad
) |
7231 EGRSTATUSPAGESIZE_V(stat_len
!= 64));
7232 t4_set_reg_field(adap
, SGE_CONTROL2_A
,
7233 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M
),
7234 INGPACKBOUNDARY_V(ingpack
));
7237 * Adjust various SGE Free List Host Buffer Sizes.
7239 * This is something of a crock since we're using fixed indices into
7240 * the array which are also known by the sge.c code and the T4
7241 * Firmware Configuration File. We need to come up with a much better
7242 * approach to managing this array. For now, the first four entries
7247 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
7248 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
7250 * For the single-MTU buffers in unpacked mode we need to include
7251 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
7252 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
7253 * Padding boundary. All of these are accommodated in the Factory
7254 * Default Firmware Configuration File but we need to adjust it for
7255 * this host's cache line size.
7257 t4_write_reg(adap
, SGE_FL_BUFFER_SIZE0_A
, page_size
);
7258 t4_write_reg(adap
, SGE_FL_BUFFER_SIZE2_A
,
7259 (t4_read_reg(adap
, SGE_FL_BUFFER_SIZE2_A
) + fl_align
-1)
7261 t4_write_reg(adap
, SGE_FL_BUFFER_SIZE3_A
,
7262 (t4_read_reg(adap
, SGE_FL_BUFFER_SIZE3_A
) + fl_align
-1)
7265 t4_write_reg(adap
, ULP_RX_TDDP_PSZ_A
, HPZ0_V(page_shift
- 12));
7271 * t4_fw_initialize - ask FW to initialize the device
7272 * @adap: the adapter
7273 * @mbox: mailbox to use for the FW command
7275 * Issues a command to FW to partially initialize the device. This
7276 * performs initialization that generally doesn't depend on user input.
7278 int t4_fw_initialize(struct adapter
*adap
, unsigned int mbox
)
7280 struct fw_initialize_cmd c
;
7282 memset(&c
, 0, sizeof(c
));
7283 INIT_CMD(c
, INITIALIZE
, WRITE
);
7284 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
7288 * t4_query_params_rw - query FW or device parameters
7289 * @adap: the adapter
7290 * @mbox: mailbox to use for the FW command
7293 * @nparams: the number of parameters
7294 * @params: the parameter names
7295 * @val: the parameter values
7296 * @rw: Write and read flag
7297 * @sleep_ok: if true, we may sleep awaiting mbox cmd completion
7299 * Reads the value of FW or device parameters. Up to 7 parameters can be
7302 int t4_query_params_rw(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
7303 unsigned int vf
, unsigned int nparams
, const u32
*params
,
7304 u32
*val
, int rw
, bool sleep_ok
)
7307 struct fw_params_cmd c
;
7308 __be32
*p
= &c
.param
[0].mnem
;
7313 memset(&c
, 0, sizeof(c
));
7314 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD
) |
7315 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
7316 FW_PARAMS_CMD_PFN_V(pf
) |
7317 FW_PARAMS_CMD_VFN_V(vf
));
7318 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
7320 for (i
= 0; i
< nparams
; i
++) {
7321 *p
++ = cpu_to_be32(*params
++);
7323 *p
= cpu_to_be32(*(val
+ i
));
7327 ret
= t4_wr_mbox_meat(adap
, mbox
, &c
, sizeof(c
), &c
, sleep_ok
);
7329 for (i
= 0, p
= &c
.param
[0].val
; i
< nparams
; i
++, p
+= 2)
7330 *val
++ = be32_to_cpu(*p
);
7334 int t4_query_params(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
7335 unsigned int vf
, unsigned int nparams
, const u32
*params
,
7338 return t4_query_params_rw(adap
, mbox
, pf
, vf
, nparams
, params
, val
, 0,
7342 int t4_query_params_ns(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
7343 unsigned int vf
, unsigned int nparams
, const u32
*params
,
7346 return t4_query_params_rw(adap
, mbox
, pf
, vf
, nparams
, params
, val
, 0,
7351 * t4_set_params_timeout - sets FW or device parameters
7352 * @adap: the adapter
7353 * @mbox: mailbox to use for the FW command
7356 * @nparams: the number of parameters
7357 * @params: the parameter names
7358 * @val: the parameter values
7359 * @timeout: the timeout time
7361 * Sets the value of FW or device parameters. Up to 7 parameters can be
7362 * specified at once.
7364 int t4_set_params_timeout(struct adapter
*adap
, unsigned int mbox
,
7365 unsigned int pf
, unsigned int vf
,
7366 unsigned int nparams
, const u32
*params
,
7367 const u32
*val
, int timeout
)
7369 struct fw_params_cmd c
;
7370 __be32
*p
= &c
.param
[0].mnem
;
7375 memset(&c
, 0, sizeof(c
));
7376 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD
) |
7377 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
7378 FW_PARAMS_CMD_PFN_V(pf
) |
7379 FW_PARAMS_CMD_VFN_V(vf
));
7380 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
7383 *p
++ = cpu_to_be32(*params
++);
7384 *p
++ = cpu_to_be32(*val
++);
7387 return t4_wr_mbox_timeout(adap
, mbox
, &c
, sizeof(c
), NULL
, timeout
);
7391 * t4_set_params - sets FW or device parameters
7392 * @adap: the adapter
7393 * @mbox: mailbox to use for the FW command
7396 * @nparams: the number of parameters
7397 * @params: the parameter names
7398 * @val: the parameter values
7400 * Sets the value of FW or device parameters. Up to 7 parameters can be
7401 * specified at once.
7403 int t4_set_params(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
7404 unsigned int vf
, unsigned int nparams
, const u32
*params
,
7407 return t4_set_params_timeout(adap
, mbox
, pf
, vf
, nparams
, params
, val
,
7408 FW_CMD_MAX_TIMEOUT
);
7412 * t4_cfg_pfvf - configure PF/VF resource limits
7413 * @adap: the adapter
7414 * @mbox: mailbox to use for the FW command
7415 * @pf: the PF being configured
7416 * @vf: the VF being configured
7417 * @txq: the max number of egress queues
7418 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
7419 * @rxqi: the max number of interrupt-capable ingress queues
7420 * @rxq: the max number of interruptless ingress queues
7421 * @tc: the PCI traffic class
7422 * @vi: the max number of virtual interfaces
7423 * @cmask: the channel access rights mask for the PF/VF
7424 * @pmask: the port access rights mask for the PF/VF
7425 * @nexact: the maximum number of exact MPS filters
7426 * @rcaps: read capabilities
7427 * @wxcaps: write/execute capabilities
7429 * Configures resource limits and capabilities for a physical or virtual
7432 int t4_cfg_pfvf(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
7433 unsigned int vf
, unsigned int txq
, unsigned int txq_eth_ctrl
,
7434 unsigned int rxqi
, unsigned int rxq
, unsigned int tc
,
7435 unsigned int vi
, unsigned int cmask
, unsigned int pmask
,
7436 unsigned int nexact
, unsigned int rcaps
, unsigned int wxcaps
)
7438 struct fw_pfvf_cmd c
;
7440 memset(&c
, 0, sizeof(c
));
7441 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD
) | FW_CMD_REQUEST_F
|
7442 FW_CMD_WRITE_F
| FW_PFVF_CMD_PFN_V(pf
) |
7443 FW_PFVF_CMD_VFN_V(vf
));
7444 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
7445 c
.niqflint_niq
= cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi
) |
7446 FW_PFVF_CMD_NIQ_V(rxq
));
7447 c
.type_to_neq
= cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask
) |
7448 FW_PFVF_CMD_PMASK_V(pmask
) |
7449 FW_PFVF_CMD_NEQ_V(txq
));
7450 c
.tc_to_nexactf
= cpu_to_be32(FW_PFVF_CMD_TC_V(tc
) |
7451 FW_PFVF_CMD_NVI_V(vi
) |
7452 FW_PFVF_CMD_NEXACTF_V(nexact
));
7453 c
.r_caps_to_nethctrl
= cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps
) |
7454 FW_PFVF_CMD_WX_CAPS_V(wxcaps
) |
7455 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl
));
7456 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
7460 * t4_alloc_vi - allocate a virtual interface
7461 * @adap: the adapter
7462 * @mbox: mailbox to use for the FW command
7463 * @port: physical port associated with the VI
7464 * @pf: the PF owning the VI
7465 * @vf: the VF owning the VI
7466 * @nmac: number of MAC addresses needed (1 to 5)
7467 * @mac: the MAC addresses of the VI
7468 * @rss_size: size of RSS table slice associated with this VI
7470 * Allocates a virtual interface for the given physical port. If @mac is
7471 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
7472 * @mac should be large enough to hold @nmac Ethernet addresses, they are
7473 * stored consecutively so the space needed is @nmac * 6 bytes.
7474 * Returns a negative error number or the non-negative VI id.
7476 int t4_alloc_vi(struct adapter
*adap
, unsigned int mbox
, unsigned int port
,
7477 unsigned int pf
, unsigned int vf
, unsigned int nmac
, u8
*mac
,
7478 unsigned int *rss_size
, u8
*vivld
, u8
*vin
)
7483 memset(&c
, 0, sizeof(c
));
7484 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD
) | FW_CMD_REQUEST_F
|
7485 FW_CMD_WRITE_F
| FW_CMD_EXEC_F
|
7486 FW_VI_CMD_PFN_V(pf
) | FW_VI_CMD_VFN_V(vf
));
7487 c
.alloc_to_len16
= cpu_to_be32(FW_VI_CMD_ALLOC_F
| FW_LEN16(c
));
7488 c
.portid_pkd
= FW_VI_CMD_PORTID_V(port
);
7491 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
7496 memcpy(mac
, c
.mac
, sizeof(c
.mac
));
7499 memcpy(mac
+ 24, c
.nmac3
, sizeof(c
.nmac3
));
7502 memcpy(mac
+ 18, c
.nmac2
, sizeof(c
.nmac2
));
7505 memcpy(mac
+ 12, c
.nmac1
, sizeof(c
.nmac1
));
7508 memcpy(mac
+ 6, c
.nmac0
, sizeof(c
.nmac0
));
7512 *rss_size
= FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c
.rsssize_pkd
));
7515 *vivld
= FW_VI_CMD_VFVLD_G(be32_to_cpu(c
.alloc_to_len16
));
7518 *vin
= FW_VI_CMD_VIN_G(be32_to_cpu(c
.alloc_to_len16
));
7520 return FW_VI_CMD_VIID_G(be16_to_cpu(c
.type_viid
));
7524 * t4_free_vi - free a virtual interface
7525 * @adap: the adapter
7526 * @mbox: mailbox to use for the FW command
7527 * @pf: the PF owning the VI
7528 * @vf: the VF owning the VI
7529 * @viid: virtual interface identifiler
7531 * Free a previously allocated virtual interface.
7533 int t4_free_vi(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
7534 unsigned int vf
, unsigned int viid
)
7538 memset(&c
, 0, sizeof(c
));
7539 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD
) |
7542 FW_VI_CMD_PFN_V(pf
) |
7543 FW_VI_CMD_VFN_V(vf
));
7544 c
.alloc_to_len16
= cpu_to_be32(FW_VI_CMD_FREE_F
| FW_LEN16(c
));
7545 c
.type_viid
= cpu_to_be16(FW_VI_CMD_VIID_V(viid
));
7547 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
7551 * t4_set_rxmode - set Rx properties of a virtual interface
7552 * @adap: the adapter
7553 * @mbox: mailbox to use for the FW command
7555 * @mtu: the new MTU or -1
7556 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7557 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7558 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7559 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7560 * @sleep_ok: if true we may sleep while awaiting command completion
7562 * Sets Rx properties of a virtual interface.
7564 int t4_set_rxmode(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
7565 int mtu
, int promisc
, int all_multi
, int bcast
, int vlanex
,
7568 struct fw_vi_rxmode_cmd c
;
7570 /* convert to FW values */
7572 mtu
= FW_RXMODE_MTU_NO_CHG
;
7574 promisc
= FW_VI_RXMODE_CMD_PROMISCEN_M
;
7576 all_multi
= FW_VI_RXMODE_CMD_ALLMULTIEN_M
;
7578 bcast
= FW_VI_RXMODE_CMD_BROADCASTEN_M
;
7580 vlanex
= FW_VI_RXMODE_CMD_VLANEXEN_M
;
7582 memset(&c
, 0, sizeof(c
));
7583 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD
) |
7584 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
7585 FW_VI_RXMODE_CMD_VIID_V(viid
));
7586 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
7588 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu
) |
7589 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc
) |
7590 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi
) |
7591 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast
) |
7592 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex
));
7593 return t4_wr_mbox_meat(adap
, mbox
, &c
, sizeof(c
), NULL
, sleep_ok
);
7597 * t4_free_encap_mac_filt - frees MPS entry at given index
7598 * @adap: the adapter
7600 * @idx: index of MPS entry to be freed
7601 * @sleep_ok: call is allowed to sleep
7603 * Frees the MPS entry at supplied index
7605 * Returns a negative error number or zero on success
7607 int t4_free_encap_mac_filt(struct adapter
*adap
, unsigned int viid
,
7608 int idx
, bool sleep_ok
)
7610 struct fw_vi_mac_exact
*p
;
7611 u8 addr
[] = {0, 0, 0, 0, 0, 0};
7612 struct fw_vi_mac_cmd c
;
7616 memset(&c
, 0, sizeof(c
));
7617 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
7618 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
7620 FW_VI_MAC_CMD_VIID_V(viid
));
7621 exact
= FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC
);
7622 c
.freemacs_to_len16
= cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7626 p
->valid_to_idx
= cpu_to_be16(FW_VI_MAC_CMD_VALID_F
|
7627 FW_VI_MAC_CMD_IDX_V(idx
));
7628 memcpy(p
->macaddr
, addr
, sizeof(p
->macaddr
));
7629 ret
= t4_wr_mbox_meat(adap
, adap
->mbox
, &c
, sizeof(c
), &c
, sleep_ok
);
7634 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
7635 * @adap: the adapter
7637 * @addr: the MAC address
7639 * @idx: index of the entry in mps tcam
7640 * @lookup_type: MAC address for inner (1) or outer (0) header
7641 * @port_id: the port index
7642 * @sleep_ok: call is allowed to sleep
7644 * Removes the mac entry at the specified index using raw mac interface.
7646 * Returns a negative error number on failure.
7648 int t4_free_raw_mac_filt(struct adapter
*adap
, unsigned int viid
,
7649 const u8
*addr
, const u8
*mask
, unsigned int idx
,
7650 u8 lookup_type
, u8 port_id
, bool sleep_ok
)
7652 struct fw_vi_mac_cmd c
;
7653 struct fw_vi_mac_raw
*p
= &c
.u
.raw
;
7656 memset(&c
, 0, sizeof(c
));
7657 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
7658 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
7660 FW_VI_MAC_CMD_VIID_V(viid
));
7661 val
= FW_CMD_LEN16_V(1) |
7662 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW
);
7663 c
.freemacs_to_len16
= cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7664 FW_CMD_LEN16_V(val
));
7666 p
->raw_idx_pkd
= cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx
) |
7667 FW_VI_MAC_ID_BASED_FREE
);
7669 /* Lookup Type. Outer header: 0, Inner header: 1 */
7670 p
->data0_pkd
= cpu_to_be32(DATALKPTYPE_V(lookup_type
) |
7671 DATAPORTNUM_V(port_id
));
7672 /* Lookup mask and port mask */
7673 p
->data0m_pkd
= cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M
) |
7674 DATAPORTNUM_V(DATAPORTNUM_M
));
7676 /* Copy the address and the mask */
7677 memcpy((u8
*)&p
->data1
[0] + 2, addr
, ETH_ALEN
);
7678 memcpy((u8
*)&p
->data1m
[0] + 2, mask
, ETH_ALEN
);
7680 return t4_wr_mbox_meat(adap
, adap
->mbox
, &c
, sizeof(c
), &c
, sleep_ok
);
7684 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support
7685 * @adap: the adapter
7687 * @mac: the MAC address
7689 * @vni: the VNI id for the tunnel protocol
7690 * @vni_mask: mask for the VNI id
7691 * @dip_hit: to enable DIP match for the MPS entry
7692 * @lookup_type: MAC address for inner (1) or outer (0) header
7693 * @sleep_ok: call is allowed to sleep
7695 * Allocates an MPS entry with specified MAC address and VNI value.
7697 * Returns a negative error number or the allocated index for this mac.
7699 int t4_alloc_encap_mac_filt(struct adapter
*adap
, unsigned int viid
,
7700 const u8
*addr
, const u8
*mask
, unsigned int vni
,
7701 unsigned int vni_mask
, u8 dip_hit
, u8 lookup_type
,
7704 struct fw_vi_mac_cmd c
;
7705 struct fw_vi_mac_vni
*p
= c
.u
.exact_vni
;
7709 memset(&c
, 0, sizeof(c
));
7710 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
7711 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
7712 FW_VI_MAC_CMD_VIID_V(viid
));
7713 val
= FW_CMD_LEN16_V(1) |
7714 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC_VNI
);
7715 c
.freemacs_to_len16
= cpu_to_be32(val
);
7716 p
->valid_to_idx
= cpu_to_be16(FW_VI_MAC_CMD_VALID_F
|
7717 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC
));
7718 memcpy(p
->macaddr
, addr
, sizeof(p
->macaddr
));
7719 memcpy(p
->macaddr_mask
, mask
, sizeof(p
->macaddr_mask
));
7721 p
->lookup_type_to_vni
=
7722 cpu_to_be32(FW_VI_MAC_CMD_VNI_V(vni
) |
7723 FW_VI_MAC_CMD_DIP_HIT_V(dip_hit
) |
7724 FW_VI_MAC_CMD_LOOKUP_TYPE_V(lookup_type
));
7725 p
->vni_mask_pkd
= cpu_to_be32(FW_VI_MAC_CMD_VNI_MASK_V(vni_mask
));
7726 ret
= t4_wr_mbox_meat(adap
, adap
->mbox
, &c
, sizeof(c
), &c
, sleep_ok
);
7728 ret
= FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p
->valid_to_idx
));
7733 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
7734 * @adap: the adapter
7736 * @mac: the MAC address
7738 * @idx: index at which to add this entry
7739 * @port_id: the port index
7740 * @lookup_type: MAC address for inner (1) or outer (0) header
7741 * @sleep_ok: call is allowed to sleep
7743 * Adds the mac entry at the specified index using raw mac interface.
7745 * Returns a negative error number or the allocated index for this mac.
7747 int t4_alloc_raw_mac_filt(struct adapter
*adap
, unsigned int viid
,
7748 const u8
*addr
, const u8
*mask
, unsigned int idx
,
7749 u8 lookup_type
, u8 port_id
, bool sleep_ok
)
7752 struct fw_vi_mac_cmd c
;
7753 struct fw_vi_mac_raw
*p
= &c
.u
.raw
;
7756 memset(&c
, 0, sizeof(c
));
7757 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
7758 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
7759 FW_VI_MAC_CMD_VIID_V(viid
));
7760 val
= FW_CMD_LEN16_V(1) |
7761 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW
);
7762 c
.freemacs_to_len16
= cpu_to_be32(val
);
7764 /* Specify that this is an inner mac address */
7765 p
->raw_idx_pkd
= cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx
));
7767 /* Lookup Type. Outer header: 0, Inner header: 1 */
7768 p
->data0_pkd
= cpu_to_be32(DATALKPTYPE_V(lookup_type
) |
7769 DATAPORTNUM_V(port_id
));
7770 /* Lookup mask and port mask */
7771 p
->data0m_pkd
= cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M
) |
7772 DATAPORTNUM_V(DATAPORTNUM_M
));
7774 /* Copy the address and the mask */
7775 memcpy((u8
*)&p
->data1
[0] + 2, addr
, ETH_ALEN
);
7776 memcpy((u8
*)&p
->data1m
[0] + 2, mask
, ETH_ALEN
);
7778 ret
= t4_wr_mbox_meat(adap
, adap
->mbox
, &c
, sizeof(c
), &c
, sleep_ok
);
7780 ret
= FW_VI_MAC_CMD_RAW_IDX_G(be32_to_cpu(p
->raw_idx_pkd
));
7789 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7790 * @adap: the adapter
7791 * @mbox: mailbox to use for the FW command
7793 * @free: if true any existing filters for this VI id are first removed
7794 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
7795 * @addr: the MAC address(es)
7796 * @idx: where to store the index of each allocated filter
7797 * @hash: pointer to hash address filter bitmap
7798 * @sleep_ok: call is allowed to sleep
7800 * Allocates an exact-match filter for each of the supplied addresses and
7801 * sets it to the corresponding address. If @idx is not %NULL it should
7802 * have at least @naddr entries, each of which will be set to the index of
7803 * the filter allocated for the corresponding MAC address. If a filter
7804 * could not be allocated for an address its index is set to 0xffff.
7805 * If @hash is not %NULL addresses that fail to allocate an exact filter
7806 * are hashed and update the hash filter bitmap pointed at by @hash.
7808 * Returns a negative error number or the number of filters allocated.
7810 int t4_alloc_mac_filt(struct adapter
*adap
, unsigned int mbox
,
7811 unsigned int viid
, bool free
, unsigned int naddr
,
7812 const u8
**addr
, u16
*idx
, u64
*hash
, bool sleep_ok
)
7814 int offset
, ret
= 0;
7815 struct fw_vi_mac_cmd c
;
7816 unsigned int nfilters
= 0;
7817 unsigned int max_naddr
= adap
->params
.arch
.mps_tcam_size
;
7818 unsigned int rem
= naddr
;
7820 if (naddr
> max_naddr
)
7823 for (offset
= 0; offset
< naddr
; /**/) {
7824 unsigned int fw_naddr
= (rem
< ARRAY_SIZE(c
.u
.exact
) ?
7825 rem
: ARRAY_SIZE(c
.u
.exact
));
7826 size_t len16
= DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd
,
7827 u
.exact
[fw_naddr
]), 16);
7828 struct fw_vi_mac_exact
*p
;
7831 memset(&c
, 0, sizeof(c
));
7832 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
7835 FW_CMD_EXEC_V(free
) |
7836 FW_VI_MAC_CMD_VIID_V(viid
));
7837 c
.freemacs_to_len16
=
7838 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free
) |
7839 FW_CMD_LEN16_V(len16
));
7841 for (i
= 0, p
= c
.u
.exact
; i
< fw_naddr
; i
++, p
++) {
7843 cpu_to_be16(FW_VI_MAC_CMD_VALID_F
|
7844 FW_VI_MAC_CMD_IDX_V(
7845 FW_VI_MAC_ADD_MAC
));
7846 memcpy(p
->macaddr
, addr
[offset
+ i
],
7847 sizeof(p
->macaddr
));
7850 /* It's okay if we run out of space in our MAC address arena.
7851 * Some of the addresses we submit may get stored so we need
7852 * to run through the reply to see what the results were ...
7854 ret
= t4_wr_mbox_meat(adap
, mbox
, &c
, sizeof(c
), &c
, sleep_ok
);
7855 if (ret
&& ret
!= -FW_ENOMEM
)
7858 for (i
= 0, p
= c
.u
.exact
; i
< fw_naddr
; i
++, p
++) {
7859 u16 index
= FW_VI_MAC_CMD_IDX_G(
7860 be16_to_cpu(p
->valid_to_idx
));
7863 idx
[offset
+ i
] = (index
>= max_naddr
?
7865 if (index
< max_naddr
)
7869 hash_mac_addr(addr
[offset
+ i
]));
7877 if (ret
== 0 || ret
== -FW_ENOMEM
)
7883 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
7884 * @adap: the adapter
7885 * @mbox: mailbox to use for the FW command
7887 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
7888 * @addr: the MAC address(es)
7889 * @sleep_ok: call is allowed to sleep
7891 * Frees the exact-match filter for each of the supplied addresses
7893 * Returns a negative error number or the number of filters freed.
7895 int t4_free_mac_filt(struct adapter
*adap
, unsigned int mbox
,
7896 unsigned int viid
, unsigned int naddr
,
7897 const u8
**addr
, bool sleep_ok
)
7899 int offset
, ret
= 0;
7900 struct fw_vi_mac_cmd c
;
7901 unsigned int nfilters
= 0;
7902 unsigned int max_naddr
= is_t4(adap
->params
.chip
) ?
7903 NUM_MPS_CLS_SRAM_L_INSTANCES
:
7904 NUM_MPS_T5_CLS_SRAM_L_INSTANCES
;
7905 unsigned int rem
= naddr
;
7907 if (naddr
> max_naddr
)
7910 for (offset
= 0; offset
< (int)naddr
; /**/) {
7911 unsigned int fw_naddr
= (rem
< ARRAY_SIZE(c
.u
.exact
)
7913 : ARRAY_SIZE(c
.u
.exact
));
7914 size_t len16
= DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd
,
7915 u
.exact
[fw_naddr
]), 16);
7916 struct fw_vi_mac_exact
*p
;
7919 memset(&c
, 0, sizeof(c
));
7920 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
7924 FW_VI_MAC_CMD_VIID_V(viid
));
7925 c
.freemacs_to_len16
=
7926 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7927 FW_CMD_LEN16_V(len16
));
7929 for (i
= 0, p
= c
.u
.exact
; i
< (int)fw_naddr
; i
++, p
++) {
7930 p
->valid_to_idx
= cpu_to_be16(
7931 FW_VI_MAC_CMD_VALID_F
|
7932 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE
));
7933 memcpy(p
->macaddr
, addr
[offset
+i
], sizeof(p
->macaddr
));
7936 ret
= t4_wr_mbox_meat(adap
, mbox
, &c
, sizeof(c
), &c
, sleep_ok
);
7940 for (i
= 0, p
= c
.u
.exact
; i
< fw_naddr
; i
++, p
++) {
7941 u16 index
= FW_VI_MAC_CMD_IDX_G(
7942 be16_to_cpu(p
->valid_to_idx
));
7944 if (index
< max_naddr
)
7958 * t4_change_mac - modifies the exact-match filter for a MAC address
7959 * @adap: the adapter
7960 * @mbox: mailbox to use for the FW command
7962 * @idx: index of existing filter for old value of MAC address, or -1
7963 * @addr: the new MAC address value
7964 * @persist: whether a new MAC allocation should be persistent
7965 * @add_smt: if true also add the address to the HW SMT
7967 * Modifies an exact-match filter and sets it to the new MAC address.
7968 * Note that in general it is not possible to modify the value of a given
7969 * filter so the generic way to modify an address filter is to free the one
7970 * being used by the old address value and allocate a new filter for the
7971 * new address value. @idx can be -1 if the address is a new addition.
7973 * Returns a negative error number or the index of the filter with the new
7976 int t4_change_mac(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
7977 int idx
, const u8
*addr
, bool persist
, u8
*smt_idx
)
7980 struct fw_vi_mac_cmd c
;
7981 struct fw_vi_mac_exact
*p
= c
.u
.exact
;
7982 unsigned int max_mac_addr
= adap
->params
.arch
.mps_tcam_size
;
7984 if (idx
< 0) /* new allocation */
7985 idx
= persist
? FW_VI_MAC_ADD_PERSIST_MAC
: FW_VI_MAC_ADD_MAC
;
7986 mode
= smt_idx
? FW_VI_MAC_SMT_AND_MPSTCAM
: FW_VI_MAC_MPS_TCAM_ENTRY
;
7988 memset(&c
, 0, sizeof(c
));
7989 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
7990 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
7991 FW_VI_MAC_CMD_VIID_V(viid
));
7992 c
.freemacs_to_len16
= cpu_to_be32(FW_CMD_LEN16_V(1));
7993 p
->valid_to_idx
= cpu_to_be16(FW_VI_MAC_CMD_VALID_F
|
7994 FW_VI_MAC_CMD_SMAC_RESULT_V(mode
) |
7995 FW_VI_MAC_CMD_IDX_V(idx
));
7996 memcpy(p
->macaddr
, addr
, sizeof(p
->macaddr
));
7998 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
8000 ret
= FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p
->valid_to_idx
));
8001 if (ret
>= max_mac_addr
)
8004 if (adap
->params
.viid_smt_extn_support
) {
8005 *smt_idx
= FW_VI_MAC_CMD_SMTID_G
8006 (be32_to_cpu(c
.op_to_viid
));
8008 /* In T4/T5, SMT contains 256 SMAC entries
8009 * organized in 128 rows of 2 entries each.
8010 * In T6, SMT contains 256 SMAC entries in
8013 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) <=
8015 *smt_idx
= (viid
& FW_VIID_VIN_M
) << 1;
8017 *smt_idx
= (viid
& FW_VIID_VIN_M
);
8025 * t4_set_addr_hash - program the MAC inexact-match hash filter
8026 * @adap: the adapter
8027 * @mbox: mailbox to use for the FW command
8029 * @ucast: whether the hash filter should also match unicast addresses
8030 * @vec: the value to be written to the hash filter
8031 * @sleep_ok: call is allowed to sleep
8033 * Sets the 64-bit inexact-match hash filter for a virtual interface.
8035 int t4_set_addr_hash(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
8036 bool ucast
, u64 vec
, bool sleep_ok
)
8038 struct fw_vi_mac_cmd c
;
8040 memset(&c
, 0, sizeof(c
));
8041 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD
) |
8042 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
8043 FW_VI_ENABLE_CMD_VIID_V(viid
));
8044 c
.freemacs_to_len16
= cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F
|
8045 FW_VI_MAC_CMD_HASHUNIEN_V(ucast
) |
8047 c
.u
.hash
.hashvec
= cpu_to_be64(vec
);
8048 return t4_wr_mbox_meat(adap
, mbox
, &c
, sizeof(c
), NULL
, sleep_ok
);
8052 * t4_enable_vi_params - enable/disable a virtual interface
8053 * @adap: the adapter
8054 * @mbox: mailbox to use for the FW command
8056 * @rx_en: 1=enable Rx, 0=disable Rx
8057 * @tx_en: 1=enable Tx, 0=disable Tx
8058 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
8060 * Enables/disables a virtual interface. Note that setting DCB Enable
8061 * only makes sense when enabling a Virtual Interface ...
8063 int t4_enable_vi_params(struct adapter
*adap
, unsigned int mbox
,
8064 unsigned int viid
, bool rx_en
, bool tx_en
, bool dcb_en
)
8066 struct fw_vi_enable_cmd c
;
8068 memset(&c
, 0, sizeof(c
));
8069 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD
) |
8070 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
8071 FW_VI_ENABLE_CMD_VIID_V(viid
));
8072 c
.ien_to_len16
= cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en
) |
8073 FW_VI_ENABLE_CMD_EEN_V(tx_en
) |
8074 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en
) |
8076 return t4_wr_mbox_ns(adap
, mbox
, &c
, sizeof(c
), NULL
);
8080 * t4_enable_vi - enable/disable a virtual interface
8081 * @adap: the adapter
8082 * @mbox: mailbox to use for the FW command
8084 * @rx_en: 1=enable Rx, 0=disable Rx
8085 * @tx_en: 1=enable Tx, 0=disable Tx
8087 * Enables/disables a virtual interface.
8089 int t4_enable_vi(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
8090 bool rx_en
, bool tx_en
)
8092 return t4_enable_vi_params(adap
, mbox
, viid
, rx_en
, tx_en
, 0);
8096 * t4_enable_pi_params - enable/disable a Port's Virtual Interface
8097 * @adap: the adapter
8098 * @mbox: mailbox to use for the FW command
8099 * @pi: the Port Information structure
8100 * @rx_en: 1=enable Rx, 0=disable Rx
8101 * @tx_en: 1=enable Tx, 0=disable Tx
8102 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
8104 * Enables/disables a Port's Virtual Interface. Note that setting DCB
8105 * Enable only makes sense when enabling a Virtual Interface ...
8106 * If the Virtual Interface enable/disable operation is successful,
8107 * we notify the OS-specific code of a potential Link Status change
8108 * via the OS Contract API t4_os_link_changed().
8110 int t4_enable_pi_params(struct adapter
*adap
, unsigned int mbox
,
8111 struct port_info
*pi
,
8112 bool rx_en
, bool tx_en
, bool dcb_en
)
8114 int ret
= t4_enable_vi_params(adap
, mbox
, pi
->viid
,
8115 rx_en
, tx_en
, dcb_en
);
8118 t4_os_link_changed(adap
, pi
->port_id
,
8119 rx_en
&& tx_en
&& pi
->link_cfg
.link_ok
);
8124 * t4_identify_port - identify a VI's port by blinking its LED
8125 * @adap: the adapter
8126 * @mbox: mailbox to use for the FW command
8128 * @nblinks: how many times to blink LED at 2.5 Hz
8130 * Identifies a VI's port by blinking its LED.
8132 int t4_identify_port(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
8133 unsigned int nblinks
)
8135 struct fw_vi_enable_cmd c
;
8137 memset(&c
, 0, sizeof(c
));
8138 c
.op_to_viid
= cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD
) |
8139 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
8140 FW_VI_ENABLE_CMD_VIID_V(viid
));
8141 c
.ien_to_len16
= cpu_to_be32(FW_VI_ENABLE_CMD_LED_F
| FW_LEN16(c
));
8142 c
.blinkdur
= cpu_to_be16(nblinks
);
8143 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
8147 * t4_iq_stop - stop an ingress queue and its FLs
8148 * @adap: the adapter
8149 * @mbox: mailbox to use for the FW command
8150 * @pf: the PF owning the queues
8151 * @vf: the VF owning the queues
8152 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8153 * @iqid: ingress queue id
8154 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8155 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8157 * Stops an ingress queue and its associated FLs, if any. This causes
8158 * any current or future data/messages destined for these queues to be
8161 int t4_iq_stop(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
8162 unsigned int vf
, unsigned int iqtype
, unsigned int iqid
,
8163 unsigned int fl0id
, unsigned int fl1id
)
8167 memset(&c
, 0, sizeof(c
));
8168 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD
) | FW_CMD_REQUEST_F
|
8169 FW_CMD_EXEC_F
| FW_IQ_CMD_PFN_V(pf
) |
8170 FW_IQ_CMD_VFN_V(vf
));
8171 c
.alloc_to_len16
= cpu_to_be32(FW_IQ_CMD_IQSTOP_F
| FW_LEN16(c
));
8172 c
.type_to_iqandstindex
= cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype
));
8173 c
.iqid
= cpu_to_be16(iqid
);
8174 c
.fl0id
= cpu_to_be16(fl0id
);
8175 c
.fl1id
= cpu_to_be16(fl1id
);
8176 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
8180 * t4_iq_free - free an ingress queue and its FLs
8181 * @adap: the adapter
8182 * @mbox: mailbox to use for the FW command
8183 * @pf: the PF owning the queues
8184 * @vf: the VF owning the queues
8185 * @iqtype: the ingress queue type
8186 * @iqid: ingress queue id
8187 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8188 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8190 * Frees an ingress queue and its associated FLs, if any.
8192 int t4_iq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
8193 unsigned int vf
, unsigned int iqtype
, unsigned int iqid
,
8194 unsigned int fl0id
, unsigned int fl1id
)
8198 memset(&c
, 0, sizeof(c
));
8199 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD
) | FW_CMD_REQUEST_F
|
8200 FW_CMD_EXEC_F
| FW_IQ_CMD_PFN_V(pf
) |
8201 FW_IQ_CMD_VFN_V(vf
));
8202 c
.alloc_to_len16
= cpu_to_be32(FW_IQ_CMD_FREE_F
| FW_LEN16(c
));
8203 c
.type_to_iqandstindex
= cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype
));
8204 c
.iqid
= cpu_to_be16(iqid
);
8205 c
.fl0id
= cpu_to_be16(fl0id
);
8206 c
.fl1id
= cpu_to_be16(fl1id
);
8207 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
8211 * t4_eth_eq_free - free an Ethernet egress queue
8212 * @adap: the adapter
8213 * @mbox: mailbox to use for the FW command
8214 * @pf: the PF owning the queue
8215 * @vf: the VF owning the queue
8216 * @eqid: egress queue id
8218 * Frees an Ethernet egress queue.
8220 int t4_eth_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
8221 unsigned int vf
, unsigned int eqid
)
8223 struct fw_eq_eth_cmd c
;
8225 memset(&c
, 0, sizeof(c
));
8226 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD
) |
8227 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
8228 FW_EQ_ETH_CMD_PFN_V(pf
) |
8229 FW_EQ_ETH_CMD_VFN_V(vf
));
8230 c
.alloc_to_len16
= cpu_to_be32(FW_EQ_ETH_CMD_FREE_F
| FW_LEN16(c
));
8231 c
.eqid_pkd
= cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid
));
8232 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
8236 * t4_ctrl_eq_free - free a control egress queue
8237 * @adap: the adapter
8238 * @mbox: mailbox to use for the FW command
8239 * @pf: the PF owning the queue
8240 * @vf: the VF owning the queue
8241 * @eqid: egress queue id
8243 * Frees a control egress queue.
8245 int t4_ctrl_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
8246 unsigned int vf
, unsigned int eqid
)
8248 struct fw_eq_ctrl_cmd c
;
8250 memset(&c
, 0, sizeof(c
));
8251 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD
) |
8252 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
8253 FW_EQ_CTRL_CMD_PFN_V(pf
) |
8254 FW_EQ_CTRL_CMD_VFN_V(vf
));
8255 c
.alloc_to_len16
= cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F
| FW_LEN16(c
));
8256 c
.cmpliqid_eqid
= cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid
));
8257 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
8261 * t4_ofld_eq_free - free an offload egress queue
8262 * @adap: the adapter
8263 * @mbox: mailbox to use for the FW command
8264 * @pf: the PF owning the queue
8265 * @vf: the VF owning the queue
8266 * @eqid: egress queue id
8268 * Frees a control egress queue.
8270 int t4_ofld_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
8271 unsigned int vf
, unsigned int eqid
)
8273 struct fw_eq_ofld_cmd c
;
8275 memset(&c
, 0, sizeof(c
));
8276 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD
) |
8277 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
8278 FW_EQ_OFLD_CMD_PFN_V(pf
) |
8279 FW_EQ_OFLD_CMD_VFN_V(vf
));
8280 c
.alloc_to_len16
= cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F
| FW_LEN16(c
));
8281 c
.eqid_pkd
= cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid
));
8282 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
8286 * t4_link_down_rc_str - return a string for a Link Down Reason Code
8287 * @adap: the adapter
8288 * @link_down_rc: Link Down Reason Code
8290 * Returns a string representation of the Link Down Reason Code.
8292 static const char *t4_link_down_rc_str(unsigned char link_down_rc
)
8294 static const char * const reason
[] = {
8297 "Auto-negotiation Failure",
8299 "Insufficient Airflow",
8300 "Unable To Determine Reason",
8301 "No RX Signal Detected",
8305 if (link_down_rc
>= ARRAY_SIZE(reason
))
8306 return "Bad Reason Code";
8308 return reason
[link_down_rc
];
8312 * Return the highest speed set in the port capabilities, in Mb/s.
8314 static unsigned int fwcap_to_speed(fw_port_cap32_t caps
)
8316 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8318 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8322 TEST_SPEED_RETURN(400G
, 400000);
8323 TEST_SPEED_RETURN(200G
, 200000);
8324 TEST_SPEED_RETURN(100G
, 100000);
8325 TEST_SPEED_RETURN(50G
, 50000);
8326 TEST_SPEED_RETURN(40G
, 40000);
8327 TEST_SPEED_RETURN(25G
, 25000);
8328 TEST_SPEED_RETURN(10G
, 10000);
8329 TEST_SPEED_RETURN(1G
, 1000);
8330 TEST_SPEED_RETURN(100M
, 100);
8332 #undef TEST_SPEED_RETURN
8338 * fwcap_to_fwspeed - return highest speed in Port Capabilities
8339 * @acaps: advertised Port Capabilities
8341 * Get the highest speed for the port from the advertised Port
8342 * Capabilities. It will be either the highest speed from the list of
8343 * speeds or whatever user has set using ethtool.
8345 static fw_port_cap32_t
fwcap_to_fwspeed(fw_port_cap32_t acaps
)
8347 #define TEST_SPEED_RETURN(__caps_speed) \
8349 if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8350 return FW_PORT_CAP32_SPEED_##__caps_speed; \
8353 TEST_SPEED_RETURN(400G
);
8354 TEST_SPEED_RETURN(200G
);
8355 TEST_SPEED_RETURN(100G
);
8356 TEST_SPEED_RETURN(50G
);
8357 TEST_SPEED_RETURN(40G
);
8358 TEST_SPEED_RETURN(25G
);
8359 TEST_SPEED_RETURN(10G
);
8360 TEST_SPEED_RETURN(1G
);
8361 TEST_SPEED_RETURN(100M
);
8363 #undef TEST_SPEED_RETURN
8369 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8370 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
8372 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
8373 * 32-bit Port Capabilities value.
8375 static fw_port_cap32_t
lstatus_to_fwcap(u32 lstatus
)
8377 fw_port_cap32_t linkattr
= 0;
8379 /* Unfortunately the format of the Link Status in the old
8380 * 16-bit Port Information message isn't the same as the
8381 * 16-bit Port Capabilities bitfield used everywhere else ...
8383 if (lstatus
& FW_PORT_CMD_RXPAUSE_F
)
8384 linkattr
|= FW_PORT_CAP32_FC_RX
;
8385 if (lstatus
& FW_PORT_CMD_TXPAUSE_F
)
8386 linkattr
|= FW_PORT_CAP32_FC_TX
;
8387 if (lstatus
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M
))
8388 linkattr
|= FW_PORT_CAP32_SPEED_100M
;
8389 if (lstatus
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G
))
8390 linkattr
|= FW_PORT_CAP32_SPEED_1G
;
8391 if (lstatus
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G
))
8392 linkattr
|= FW_PORT_CAP32_SPEED_10G
;
8393 if (lstatus
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G
))
8394 linkattr
|= FW_PORT_CAP32_SPEED_25G
;
8395 if (lstatus
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G
))
8396 linkattr
|= FW_PORT_CAP32_SPEED_40G
;
8397 if (lstatus
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G
))
8398 linkattr
|= FW_PORT_CAP32_SPEED_100G
;
8404 * t4_handle_get_port_info - process a FW reply message
8405 * @pi: the port info
8406 * @rpl: start of the FW message
8408 * Processes a GET_PORT_INFO FW reply message.
8410 void t4_handle_get_port_info(struct port_info
*pi
, const __be64
*rpl
)
8412 const struct fw_port_cmd
*cmd
= (const void *)rpl
;
8413 int action
= FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd
->action_to_len16
));
8414 struct adapter
*adapter
= pi
->adapter
;
8415 struct link_config
*lc
= &pi
->link_cfg
;
8416 int link_ok
, linkdnrc
;
8417 enum fw_port_type port_type
;
8418 enum fw_port_module_type mod_type
;
8419 unsigned int speed
, fc
, fec
;
8420 fw_port_cap32_t pcaps
, acaps
, lpacaps
, linkattr
;
8422 /* Extract the various fields from the Port Information message.
8425 case FW_PORT_ACTION_GET_PORT_INFO
: {
8426 u32 lstatus
= be32_to_cpu(cmd
->u
.info
.lstatus_to_modtype
);
8428 link_ok
= (lstatus
& FW_PORT_CMD_LSTATUS_F
) != 0;
8429 linkdnrc
= FW_PORT_CMD_LINKDNRC_G(lstatus
);
8430 port_type
= FW_PORT_CMD_PTYPE_G(lstatus
);
8431 mod_type
= FW_PORT_CMD_MODTYPE_G(lstatus
);
8432 pcaps
= fwcaps16_to_caps32(be16_to_cpu(cmd
->u
.info
.pcap
));
8433 acaps
= fwcaps16_to_caps32(be16_to_cpu(cmd
->u
.info
.acap
));
8434 lpacaps
= fwcaps16_to_caps32(be16_to_cpu(cmd
->u
.info
.lpacap
));
8435 linkattr
= lstatus_to_fwcap(lstatus
);
8439 case FW_PORT_ACTION_GET_PORT_INFO32
: {
8442 lstatus32
= be32_to_cpu(cmd
->u
.info32
.lstatus32_to_cbllen32
);
8443 link_ok
= (lstatus32
& FW_PORT_CMD_LSTATUS32_F
) != 0;
8444 linkdnrc
= FW_PORT_CMD_LINKDNRC32_G(lstatus32
);
8445 port_type
= FW_PORT_CMD_PORTTYPE32_G(lstatus32
);
8446 mod_type
= FW_PORT_CMD_MODTYPE32_G(lstatus32
);
8447 pcaps
= be32_to_cpu(cmd
->u
.info32
.pcaps32
);
8448 acaps
= be32_to_cpu(cmd
->u
.info32
.acaps32
);
8449 lpacaps
= be32_to_cpu(cmd
->u
.info32
.lpacaps32
);
8450 linkattr
= be32_to_cpu(cmd
->u
.info32
.linkattr32
);
8455 dev_err(adapter
->pdev_dev
, "Handle Port Information: Bad Command/Action %#x\n",
8456 be32_to_cpu(cmd
->action_to_len16
));
8460 fec
= fwcap_to_cc_fec(acaps
);
8461 fc
= fwcap_to_cc_pause(linkattr
);
8462 speed
= fwcap_to_speed(linkattr
);
8464 lc
->new_module
= false;
8465 lc
->redo_l1cfg
= false;
8467 if (mod_type
!= pi
->mod_type
) {
8468 /* With the newer SFP28 and QSFP28 Transceiver Module Types,
8469 * various fundamental Port Capabilities which used to be
8470 * immutable can now change radically. We can now have
8471 * Speeds, Auto-Negotiation, Forward Error Correction, etc.
8472 * all change based on what Transceiver Module is inserted.
8473 * So we need to record the Physical "Port" Capabilities on
8474 * every Transceiver Module change.
8478 /* When a new Transceiver Module is inserted, the Firmware
8479 * will examine its i2c EPROM to determine its type and
8480 * general operating parameters including things like Forward
8481 * Error Control, etc. Various IEEE 802.3 standards dictate
8482 * how to interpret these i2c values to determine default
8483 * "sutomatic" settings. We record these for future use when
8484 * the user explicitly requests these standards-based values.
8486 lc
->def_acaps
= acaps
;
8488 /* Some versions of the early T6 Firmware "cheated" when
8489 * handling different Transceiver Modules by changing the
8490 * underlaying Port Type reported to the Host Drivers. As
8491 * such we need to capture whatever Port Type the Firmware
8492 * sends us and record it in case it's different from what we
8493 * were told earlier. Unfortunately, since Firmware is
8494 * forever, we'll need to keep this code here forever, but in
8495 * later T6 Firmware it should just be an assignment of the
8496 * same value already recorded.
8498 pi
->port_type
= port_type
;
8500 pi
->mod_type
= mod_type
;
8502 lc
->new_module
= t4_is_inserted_mod_type(mod_type
);
8503 t4_os_portmod_changed(adapter
, pi
->port_id
);
8506 if (link_ok
!= lc
->link_ok
|| speed
!= lc
->speed
||
8507 fc
!= lc
->fc
|| fec
!= lc
->fec
) { /* something changed */
8508 if (!link_ok
&& lc
->link_ok
) {
8509 lc
->link_down_rc
= linkdnrc
;
8510 dev_warn(adapter
->pdev_dev
, "Port %d link down, reason: %s\n",
8511 pi
->tx_chan
, t4_link_down_rc_str(linkdnrc
));
8513 lc
->link_ok
= link_ok
;
8518 lc
->lpacaps
= lpacaps
;
8519 lc
->acaps
= acaps
& ADVERT_MASK
;
8521 if (!(lc
->acaps
& FW_PORT_CAP32_ANEG
)) {
8522 lc
->autoneg
= AUTONEG_DISABLE
;
8523 } else if (lc
->acaps
& FW_PORT_CAP32_ANEG
) {
8524 lc
->autoneg
= AUTONEG_ENABLE
;
8526 /* When Autoneg is disabled, user needs to set
8528 * Similar to cxgb4_ethtool.c: set_link_ksettings
8531 lc
->speed_caps
= fwcap_to_fwspeed(acaps
);
8532 lc
->autoneg
= AUTONEG_DISABLE
;
8535 t4_os_link_changed(adapter
, pi
->port_id
, link_ok
);
8538 if (lc
->new_module
&& lc
->redo_l1cfg
) {
8539 struct link_config old_lc
;
8542 /* Save the current L1 Configuration and restore it if an
8543 * error occurs. We probably should fix the l1_cfg*()
8544 * routines not to change the link_config when an error
8548 ret
= t4_link_l1cfg_ns(adapter
, adapter
->mbox
, pi
->lport
, lc
);
8551 dev_warn(adapter
->pdev_dev
,
8552 "Attempt to update new Transceiver Module settings failed\n");
8555 lc
->new_module
= false;
8556 lc
->redo_l1cfg
= false;
8560 * t4_update_port_info - retrieve and update port information if changed
8561 * @pi: the port_info
8563 * We issue a Get Port Information Command to the Firmware and, if
8564 * successful, we check to see if anything is different from what we
8565 * last recorded and update things accordingly.
8567 int t4_update_port_info(struct port_info
*pi
)
8569 unsigned int fw_caps
= pi
->adapter
->params
.fw_caps_support
;
8570 struct fw_port_cmd port_cmd
;
8573 memset(&port_cmd
, 0, sizeof(port_cmd
));
8574 port_cmd
.op_to_portid
= cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD
) |
8575 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
8576 FW_PORT_CMD_PORTID_V(pi
->tx_chan
));
8577 port_cmd
.action_to_len16
= cpu_to_be32(
8578 FW_PORT_CMD_ACTION_V(fw_caps
== FW_CAPS16
8579 ? FW_PORT_ACTION_GET_PORT_INFO
8580 : FW_PORT_ACTION_GET_PORT_INFO32
) |
8581 FW_LEN16(port_cmd
));
8582 ret
= t4_wr_mbox(pi
->adapter
, pi
->adapter
->mbox
,
8583 &port_cmd
, sizeof(port_cmd
), &port_cmd
);
8587 t4_handle_get_port_info(pi
, (__be64
*)&port_cmd
);
8592 * t4_get_link_params - retrieve basic link parameters for given port
8594 * @link_okp: value return pointer for link up/down
8595 * @speedp: value return pointer for speed (Mb/s)
8596 * @mtup: value return pointer for mtu
8598 * Retrieves basic link parameters for a port: link up/down, speed (Mb/s),
8599 * and MTU for a specified port. A negative error is returned on
8600 * failure; 0 on success.
8602 int t4_get_link_params(struct port_info
*pi
, unsigned int *link_okp
,
8603 unsigned int *speedp
, unsigned int *mtup
)
8605 unsigned int fw_caps
= pi
->adapter
->params
.fw_caps_support
;
8606 struct fw_port_cmd port_cmd
;
8607 unsigned int action
, link_ok
, mtu
;
8608 fw_port_cap32_t linkattr
;
8611 memset(&port_cmd
, 0, sizeof(port_cmd
));
8612 port_cmd
.op_to_portid
= cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD
) |
8613 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
8614 FW_PORT_CMD_PORTID_V(pi
->tx_chan
));
8615 action
= (fw_caps
== FW_CAPS16
8616 ? FW_PORT_ACTION_GET_PORT_INFO
8617 : FW_PORT_ACTION_GET_PORT_INFO32
);
8618 port_cmd
.action_to_len16
= cpu_to_be32(
8619 FW_PORT_CMD_ACTION_V(action
) |
8620 FW_LEN16(port_cmd
));
8621 ret
= t4_wr_mbox(pi
->adapter
, pi
->adapter
->mbox
,
8622 &port_cmd
, sizeof(port_cmd
), &port_cmd
);
8626 if (action
== FW_PORT_ACTION_GET_PORT_INFO
) {
8627 u32 lstatus
= be32_to_cpu(port_cmd
.u
.info
.lstatus_to_modtype
);
8629 link_ok
= !!(lstatus
& FW_PORT_CMD_LSTATUS_F
);
8630 linkattr
= lstatus_to_fwcap(lstatus
);
8631 mtu
= be16_to_cpu(port_cmd
.u
.info
.mtu
);
8634 be32_to_cpu(port_cmd
.u
.info32
.lstatus32_to_cbllen32
);
8636 link_ok
= !!(lstatus32
& FW_PORT_CMD_LSTATUS32_F
);
8637 linkattr
= be32_to_cpu(port_cmd
.u
.info32
.linkattr32
);
8638 mtu
= FW_PORT_CMD_MTU32_G(
8639 be32_to_cpu(port_cmd
.u
.info32
.auxlinfo32_mtu32
));
8642 *link_okp
= link_ok
;
8643 *speedp
= fwcap_to_speed(linkattr
);
8650 * t4_handle_fw_rpl - process a FW reply message
8651 * @adap: the adapter
8652 * @rpl: start of the FW message
8654 * Processes a FW message, such as link state change messages.
8656 int t4_handle_fw_rpl(struct adapter
*adap
, const __be64
*rpl
)
8658 u8 opcode
= *(const u8
*)rpl
;
8660 /* This might be a port command ... this simplifies the following
8661 * conditionals ... We can get away with pre-dereferencing
8662 * action_to_len16 because it's in the first 16 bytes and all messages
8663 * will be at least that long.
8665 const struct fw_port_cmd
*p
= (const void *)rpl
;
8666 unsigned int action
=
8667 FW_PORT_CMD_ACTION_G(be32_to_cpu(p
->action_to_len16
));
8669 if (opcode
== FW_PORT_CMD
&&
8670 (action
== FW_PORT_ACTION_GET_PORT_INFO
||
8671 action
== FW_PORT_ACTION_GET_PORT_INFO32
)) {
8673 int chan
= FW_PORT_CMD_PORTID_G(be32_to_cpu(p
->op_to_portid
));
8674 struct port_info
*pi
= NULL
;
8676 for_each_port(adap
, i
) {
8677 pi
= adap2pinfo(adap
, i
);
8678 if (pi
->tx_chan
== chan
)
8682 t4_handle_get_port_info(pi
, rpl
);
8684 dev_warn(adap
->pdev_dev
, "Unknown firmware reply %d\n",
8691 static void get_pci_mode(struct adapter
*adapter
, struct pci_params
*p
)
8695 if (pci_is_pcie(adapter
->pdev
)) {
8696 pcie_capability_read_word(adapter
->pdev
, PCI_EXP_LNKSTA
, &val
);
8697 p
->speed
= val
& PCI_EXP_LNKSTA_CLS
;
8698 p
->width
= (val
& PCI_EXP_LNKSTA_NLW
) >> 4;
8703 * init_link_config - initialize a link's SW state
8704 * @lc: pointer to structure holding the link state
8705 * @pcaps: link Port Capabilities
8706 * @acaps: link current Advertised Port Capabilities
8708 * Initializes the SW state maintained for each link, including the link's
8709 * capabilities and default speed/flow-control/autonegotiation settings.
8711 static void init_link_config(struct link_config
*lc
, fw_port_cap32_t pcaps
,
8712 fw_port_cap32_t acaps
)
8715 lc
->def_acaps
= acaps
;
8719 lc
->requested_fc
= lc
->fc
= PAUSE_RX
| PAUSE_TX
;
8721 /* For Forward Error Control, we default to whatever the Firmware
8722 * tells us the Link is currently advertising.
8724 lc
->requested_fec
= FEC_AUTO
;
8725 lc
->fec
= fwcap_to_cc_fec(lc
->def_acaps
);
8727 /* If the Port is capable of Auto-Negtotiation, initialize it as
8728 * "enabled" and copy over all of the Physical Port Capabilities
8729 * to the Advertised Port Capabilities. Otherwise mark it as
8730 * Auto-Negotiate disabled and select the highest supported speed
8731 * for the link. Note parallel structure in t4_link_l1cfg_core()
8732 * and t4_handle_get_port_info().
8734 if (lc
->pcaps
& FW_PORT_CAP32_ANEG
) {
8735 lc
->acaps
= lc
->pcaps
& ADVERT_MASK
;
8736 lc
->autoneg
= AUTONEG_ENABLE
;
8737 lc
->requested_fc
|= PAUSE_AUTONEG
;
8740 lc
->autoneg
= AUTONEG_DISABLE
;
8741 lc
->speed_caps
= fwcap_to_fwspeed(acaps
);
8745 #define CIM_PF_NOACCESS 0xeeeeeeee
8747 int t4_wait_dev_ready(void __iomem
*regs
)
8751 whoami
= readl(regs
+ PL_WHOAMI_A
);
8752 if (whoami
!= 0xffffffff && whoami
!= CIM_PF_NOACCESS
)
8756 whoami
= readl(regs
+ PL_WHOAMI_A
);
8757 return (whoami
!= 0xffffffff && whoami
!= CIM_PF_NOACCESS
? 0 : -EIO
);
8761 u32 vendor_and_model_id
;
8765 static int t4_get_flash_params(struct adapter
*adap
)
8767 /* Table for non-Numonix supported flash parts. Numonix parts are left
8768 * to the preexisting code. All flash parts have 64KB sectors.
8770 static struct flash_desc supported_flash
[] = {
8771 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
8774 unsigned int part
, manufacturer
;
8775 unsigned int density
, size
= 0;
8779 /* Issue a Read ID Command to the Flash part. We decode supported
8780 * Flash parts and their sizes from this. There's a newer Query
8781 * Command which can retrieve detailed geometry information but many
8782 * Flash parts don't support it.
8785 ret
= sf1_write(adap
, 1, 1, 0, SF_RD_ID
);
8787 ret
= sf1_read(adap
, 3, 0, 1, &flashid
);
8788 t4_write_reg(adap
, SF_OP_A
, 0); /* unlock SF */
8792 /* Check to see if it's one of our non-standard supported Flash parts.
8794 for (part
= 0; part
< ARRAY_SIZE(supported_flash
); part
++)
8795 if (supported_flash
[part
].vendor_and_model_id
== flashid
) {
8796 adap
->params
.sf_size
= supported_flash
[part
].size_mb
;
8797 adap
->params
.sf_nsec
=
8798 adap
->params
.sf_size
/ SF_SEC_SIZE
;
8802 /* Decode Flash part size. The code below looks repetative with
8803 * common encodings, but that's not guaranteed in the JEDEC
8804 * specification for the Read JADEC ID command. The only thing that
8805 * we're guaranteed by the JADEC specification is where the
8806 * Manufacturer ID is in the returned result. After that each
8807 * Manufacturer ~could~ encode things completely differently.
8808 * Note, all Flash parts must have 64KB sectors.
8810 manufacturer
= flashid
& 0xff;
8811 switch (manufacturer
) {
8812 case 0x20: { /* Micron/Numonix */
8813 /* This Density -> Size decoding table is taken from Micron
8816 density
= (flashid
>> 16) & 0xff;
8818 case 0x14: /* 1MB */
8821 case 0x15: /* 2MB */
8824 case 0x16: /* 4MB */
8827 case 0x17: /* 8MB */
8830 case 0x18: /* 16MB */
8833 case 0x19: /* 32MB */
8836 case 0x20: /* 64MB */
8839 case 0x21: /* 128MB */
8842 case 0x22: /* 256MB */
8848 case 0x9d: { /* ISSI -- Integrated Silicon Solution, Inc. */
8849 /* This Density -> Size decoding table is taken from ISSI
8852 density
= (flashid
>> 16) & 0xff;
8854 case 0x16: /* 32 MB */
8857 case 0x17: /* 64MB */
8863 case 0xc2: { /* Macronix */
8864 /* This Density -> Size decoding table is taken from Macronix
8867 density
= (flashid
>> 16) & 0xff;
8869 case 0x17: /* 8MB */
8872 case 0x18: /* 16MB */
8878 case 0xef: { /* Winbond */
8879 /* This Density -> Size decoding table is taken from Winbond
8882 density
= (flashid
>> 16) & 0xff;
8884 case 0x17: /* 8MB */
8887 case 0x18: /* 16MB */
8895 /* If we didn't recognize the FLASH part, that's no real issue: the
8896 * Hardware/Software contract says that Hardware will _*ALWAYS*_
8897 * use a FLASH part which is at least 4MB in size and has 64KB
8898 * sectors. The unrecognized FLASH part is likely to be much larger
8899 * than 4MB, but that's all we really need.
8902 dev_warn(adap
->pdev_dev
, "Unknown Flash Part, ID = %#x, assuming 4MB\n",
8907 /* Store decoded Flash size and fall through into vetting code. */
8908 adap
->params
.sf_size
= size
;
8909 adap
->params
.sf_nsec
= size
/ SF_SEC_SIZE
;
8912 if (adap
->params
.sf_size
< FLASH_MIN_SIZE
)
8913 dev_warn(adap
->pdev_dev
, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
8914 flashid
, adap
->params
.sf_size
, FLASH_MIN_SIZE
);
8919 * t4_prep_adapter - prepare SW and HW for operation
8920 * @adapter: the adapter
8921 * @reset: if true perform a HW reset
8923 * Initialize adapter SW state for the various HW modules, set initial
8924 * values for some adapter tunables, take PHYs out of reset, and
8925 * initialize the MDIO interface.
8927 int t4_prep_adapter(struct adapter
*adapter
)
8933 get_pci_mode(adapter
, &adapter
->params
.pci
);
8934 pl_rev
= REV_G(t4_read_reg(adapter
, PL_REV_A
));
8936 ret
= t4_get_flash_params(adapter
);
8938 dev_err(adapter
->pdev_dev
, "error %d identifying flash\n", ret
);
8942 /* Retrieve adapter's device ID
8944 pci_read_config_word(adapter
->pdev
, PCI_DEVICE_ID
, &device_id
);
8945 ver
= device_id
>> 12;
8946 adapter
->params
.chip
= 0;
8949 adapter
->params
.chip
|= CHELSIO_CHIP_CODE(CHELSIO_T4
, pl_rev
);
8950 adapter
->params
.arch
.sge_fl_db
= DBPRIO_F
;
8951 adapter
->params
.arch
.mps_tcam_size
=
8952 NUM_MPS_CLS_SRAM_L_INSTANCES
;
8953 adapter
->params
.arch
.mps_rplc_size
= 128;
8954 adapter
->params
.arch
.nchan
= NCHAN
;
8955 adapter
->params
.arch
.pm_stats_cnt
= PM_NSTATS
;
8956 adapter
->params
.arch
.vfcount
= 128;
8957 /* Congestion map is for 4 channels so that
8958 * MPS can have 4 priority per port.
8960 adapter
->params
.arch
.cng_ch_bits_log
= 2;
8963 adapter
->params
.chip
|= CHELSIO_CHIP_CODE(CHELSIO_T5
, pl_rev
);
8964 adapter
->params
.arch
.sge_fl_db
= DBPRIO_F
| DBTYPE_F
;
8965 adapter
->params
.arch
.mps_tcam_size
=
8966 NUM_MPS_T5_CLS_SRAM_L_INSTANCES
;
8967 adapter
->params
.arch
.mps_rplc_size
= 128;
8968 adapter
->params
.arch
.nchan
= NCHAN
;
8969 adapter
->params
.arch
.pm_stats_cnt
= PM_NSTATS
;
8970 adapter
->params
.arch
.vfcount
= 128;
8971 adapter
->params
.arch
.cng_ch_bits_log
= 2;
8974 adapter
->params
.chip
|= CHELSIO_CHIP_CODE(CHELSIO_T6
, pl_rev
);
8975 adapter
->params
.arch
.sge_fl_db
= 0;
8976 adapter
->params
.arch
.mps_tcam_size
=
8977 NUM_MPS_T5_CLS_SRAM_L_INSTANCES
;
8978 adapter
->params
.arch
.mps_rplc_size
= 256;
8979 adapter
->params
.arch
.nchan
= 2;
8980 adapter
->params
.arch
.pm_stats_cnt
= T6_PM_NSTATS
;
8981 adapter
->params
.arch
.vfcount
= 256;
8982 /* Congestion map will be for 2 channels so that
8983 * MPS can have 8 priority per port.
8985 adapter
->params
.arch
.cng_ch_bits_log
= 3;
8988 dev_err(adapter
->pdev_dev
, "Device %d is not supported\n",
8993 adapter
->params
.cim_la_size
= CIMLA_SIZE
;
8994 init_cong_ctrl(adapter
->params
.a_wnd
, adapter
->params
.b_wnd
);
8997 * Default port for debugging in case we can't reach FW.
8999 adapter
->params
.nports
= 1;
9000 adapter
->params
.portvec
= 1;
9001 adapter
->params
.vpd
.cclk
= 50000;
9003 /* Set PCIe completion timeout to 4 seconds. */
9004 pcie_capability_clear_and_set_word(adapter
->pdev
, PCI_EXP_DEVCTL2
,
9005 PCI_EXP_DEVCTL2_COMP_TIMEOUT
, 0xd);
9010 * t4_shutdown_adapter - shut down adapter, host & wire
9011 * @adapter: the adapter
9013 * Perform an emergency shutdown of the adapter and stop it from
9014 * continuing any further communication on the ports or DMA to the
9015 * host. This is typically used when the adapter and/or firmware
9016 * have crashed and we want to prevent any further accidental
9017 * communication with the rest of the world. This will also force
9018 * the port Link Status to go down -- if register writes work --
9019 * which should help our peers figure out that we're down.
9021 int t4_shutdown_adapter(struct adapter
*adapter
)
9025 t4_intr_disable(adapter
);
9026 t4_write_reg(adapter
, DBG_GPIO_EN_A
, 0);
9027 for_each_port(adapter
, port
) {
9028 u32 a_port_cfg
= is_t4(adapter
->params
.chip
) ?
9029 PORT_REG(port
, XGMAC_PORT_CFG_A
) :
9030 T5_PORT_REG(port
, MAC_PORT_CFG_A
);
9032 t4_write_reg(adapter
, a_port_cfg
,
9033 t4_read_reg(adapter
, a_port_cfg
)
9034 & ~SIGNAL_DET_V(1));
9036 t4_set_reg_field(adapter
, SGE_CONTROL_A
, GLOBALENABLE_F
, 0);
9042 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
9043 * @adapter: the adapter
9044 * @qid: the Queue ID
9045 * @qtype: the Ingress or Egress type for @qid
9046 * @user: true if this request is for a user mode queue
9047 * @pbar2_qoffset: BAR2 Queue Offset
9048 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
9050 * Returns the BAR2 SGE Queue Registers information associated with the
9051 * indicated Absolute Queue ID. These are passed back in return value
9052 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
9053 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
9055 * This may return an error which indicates that BAR2 SGE Queue
9056 * registers aren't available. If an error is not returned, then the
9057 * following values are returned:
9059 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
9060 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
9062 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
9063 * require the "Inferred Queue ID" ability may be used. E.g. the
9064 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
9065 * then these "Inferred Queue ID" register may not be used.
9067 int t4_bar2_sge_qregs(struct adapter
*adapter
,
9069 enum t4_bar2_qtype qtype
,
9072 unsigned int *pbar2_qid
)
9074 unsigned int page_shift
, page_size
, qpp_shift
, qpp_mask
;
9075 u64 bar2_page_offset
, bar2_qoffset
;
9076 unsigned int bar2_qid
, bar2_qid_offset
, bar2_qinferred
;
9078 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
9079 if (!user
&& is_t4(adapter
->params
.chip
))
9082 /* Get our SGE Page Size parameters.
9084 page_shift
= adapter
->params
.sge
.hps
+ 10;
9085 page_size
= 1 << page_shift
;
9087 /* Get the right Queues per Page parameters for our Queue.
9089 qpp_shift
= (qtype
== T4_BAR2_QTYPE_EGRESS
9090 ? adapter
->params
.sge
.eq_qpp
9091 : adapter
->params
.sge
.iq_qpp
);
9092 qpp_mask
= (1 << qpp_shift
) - 1;
9094 /* Calculate the basics of the BAR2 SGE Queue register area:
9095 * o The BAR2 page the Queue registers will be in.
9096 * o The BAR2 Queue ID.
9097 * o The BAR2 Queue ID Offset into the BAR2 page.
9099 bar2_page_offset
= ((u64
)(qid
>> qpp_shift
) << page_shift
);
9100 bar2_qid
= qid
& qpp_mask
;
9101 bar2_qid_offset
= bar2_qid
* SGE_UDB_SIZE
;
9103 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
9104 * hardware will infer the Absolute Queue ID simply from the writes to
9105 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
9106 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
9107 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
9108 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
9109 * from the BAR2 Page and BAR2 Queue ID.
9111 * One important censequence of this is that some BAR2 SGE registers
9112 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
9113 * there. But other registers synthesize the SGE Queue ID purely
9114 * from the writes to the registers -- the Write Combined Doorbell
9115 * Buffer is a good example. These BAR2 SGE Registers are only
9116 * available for those BAR2 SGE Register areas where the SGE Absolute
9117 * Queue ID can be inferred from simple writes.
9119 bar2_qoffset
= bar2_page_offset
;
9120 bar2_qinferred
= (bar2_qid_offset
< page_size
);
9121 if (bar2_qinferred
) {
9122 bar2_qoffset
+= bar2_qid_offset
;
9126 *pbar2_qoffset
= bar2_qoffset
;
9127 *pbar2_qid
= bar2_qid
;
9132 * t4_init_devlog_params - initialize adapter->params.devlog
9133 * @adap: the adapter
9135 * Initialize various fields of the adapter's Firmware Device Log
9136 * Parameters structure.
9138 int t4_init_devlog_params(struct adapter
*adap
)
9140 struct devlog_params
*dparams
= &adap
->params
.devlog
;
9142 unsigned int devlog_meminfo
;
9143 struct fw_devlog_cmd devlog_cmd
;
9146 /* If we're dealing with newer firmware, the Device Log Paramerters
9147 * are stored in a designated register which allows us to access the
9148 * Device Log even if we can't talk to the firmware.
9151 t4_read_reg(adap
, PCIE_FW_REG(PCIE_FW_PF_A
, PCIE_FW_PF_DEVLOG
));
9153 unsigned int nentries
, nentries128
;
9155 dparams
->memtype
= PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams
);
9156 dparams
->start
= PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams
) << 4;
9158 nentries128
= PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams
);
9159 nentries
= (nentries128
+ 1) * 128;
9160 dparams
->size
= nentries
* sizeof(struct fw_devlog_e
);
9165 /* Otherwise, ask the firmware for it's Device Log Parameters.
9167 memset(&devlog_cmd
, 0, sizeof(devlog_cmd
));
9168 devlog_cmd
.op_to_write
= cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD
) |
9169 FW_CMD_REQUEST_F
| FW_CMD_READ_F
);
9170 devlog_cmd
.retval_len16
= cpu_to_be32(FW_LEN16(devlog_cmd
));
9171 ret
= t4_wr_mbox(adap
, adap
->mbox
, &devlog_cmd
, sizeof(devlog_cmd
),
9177 be32_to_cpu(devlog_cmd
.memtype_devlog_memaddr16_devlog
);
9178 dparams
->memtype
= FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo
);
9179 dparams
->start
= FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo
) << 4;
9180 dparams
->size
= be32_to_cpu(devlog_cmd
.memsize_devlog
);
9186 * t4_init_sge_params - initialize adap->params.sge
9187 * @adapter: the adapter
9189 * Initialize various fields of the adapter's SGE Parameters structure.
9191 int t4_init_sge_params(struct adapter
*adapter
)
9193 struct sge_params
*sge_params
= &adapter
->params
.sge
;
9195 unsigned int s_hps
, s_qpp
;
9197 /* Extract the SGE Page Size for our PF.
9199 hps
= t4_read_reg(adapter
, SGE_HOST_PAGE_SIZE_A
);
9200 s_hps
= (HOSTPAGESIZEPF0_S
+
9201 (HOSTPAGESIZEPF1_S
- HOSTPAGESIZEPF0_S
) * adapter
->pf
);
9202 sge_params
->hps
= ((hps
>> s_hps
) & HOSTPAGESIZEPF0_M
);
9204 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
9206 s_qpp
= (QUEUESPERPAGEPF0_S
+
9207 (QUEUESPERPAGEPF1_S
- QUEUESPERPAGEPF0_S
) * adapter
->pf
);
9208 qpp
= t4_read_reg(adapter
, SGE_EGRESS_QUEUES_PER_PAGE_PF_A
);
9209 sge_params
->eq_qpp
= ((qpp
>> s_qpp
) & QUEUESPERPAGEPF0_M
);
9210 qpp
= t4_read_reg(adapter
, SGE_INGRESS_QUEUES_PER_PAGE_PF_A
);
9211 sge_params
->iq_qpp
= ((qpp
>> s_qpp
) & QUEUESPERPAGEPF0_M
);
9217 * t4_init_tp_params - initialize adap->params.tp
9218 * @adap: the adapter
9219 * @sleep_ok: if true we may sleep while awaiting command completion
9221 * Initialize various fields of the adapter's TP Parameters structure.
9223 int t4_init_tp_params(struct adapter
*adap
, bool sleep_ok
)
9228 v
= t4_read_reg(adap
, TP_TIMER_RESOLUTION_A
);
9229 adap
->params
.tp
.tre
= TIMERRESOLUTION_G(v
);
9230 adap
->params
.tp
.dack_re
= DELAYEDACKRESOLUTION_G(v
);
9232 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
9233 for (chan
= 0; chan
< NCHAN
; chan
++)
9234 adap
->params
.tp
.tx_modq
[chan
] = chan
;
9236 /* Cache the adapter's Compressed Filter Mode and global Incress
9239 t4_tp_pio_read(adap
, &adap
->params
.tp
.vlan_pri_map
, 1,
9240 TP_VLAN_PRI_MAP_A
, sleep_ok
);
9241 t4_tp_pio_read(adap
, &adap
->params
.tp
.ingress_config
, 1,
9242 TP_INGRESS_CONFIG_A
, sleep_ok
);
9244 /* For T6, cache the adapter's compressed error vector
9245 * and passing outer header info for encapsulated packets.
9247 if (CHELSIO_CHIP_VERSION(adap
->params
.chip
) > CHELSIO_T5
) {
9248 v
= t4_read_reg(adap
, TP_OUT_CONFIG_A
);
9249 adap
->params
.tp
.rx_pkt_encap
= (v
& CRXPKTENC_F
) ? 1 : 0;
9252 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
9253 * shift positions of several elements of the Compressed Filter Tuple
9254 * for this adapter which we need frequently ...
9256 adap
->params
.tp
.fcoe_shift
= t4_filter_field_shift(adap
, FCOE_F
);
9257 adap
->params
.tp
.port_shift
= t4_filter_field_shift(adap
, PORT_F
);
9258 adap
->params
.tp
.vnic_shift
= t4_filter_field_shift(adap
, VNIC_ID_F
);
9259 adap
->params
.tp
.vlan_shift
= t4_filter_field_shift(adap
, VLAN_F
);
9260 adap
->params
.tp
.tos_shift
= t4_filter_field_shift(adap
, TOS_F
);
9261 adap
->params
.tp
.protocol_shift
= t4_filter_field_shift(adap
,
9263 adap
->params
.tp
.ethertype_shift
= t4_filter_field_shift(adap
,
9265 adap
->params
.tp
.macmatch_shift
= t4_filter_field_shift(adap
,
9267 adap
->params
.tp
.matchtype_shift
= t4_filter_field_shift(adap
,
9269 adap
->params
.tp
.frag_shift
= t4_filter_field_shift(adap
,
9272 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
9273 * represents the presence of an Outer VLAN instead of a VNIC ID.
9275 if ((adap
->params
.tp
.ingress_config
& VNIC_F
) == 0)
9276 adap
->params
.tp
.vnic_shift
= -1;
9278 v
= t4_read_reg(adap
, LE_3_DB_HASH_MASK_GEN_IPV4_T6_A
);
9279 adap
->params
.tp
.hash_filter_mask
= v
;
9280 v
= t4_read_reg(adap
, LE_4_DB_HASH_MASK_GEN_IPV4_T6_A
);
9281 adap
->params
.tp
.hash_filter_mask
|= ((u64
)v
<< 32);
9286 * t4_filter_field_shift - calculate filter field shift
9287 * @adap: the adapter
9288 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
9290 * Return the shift position of a filter field within the Compressed
9291 * Filter Tuple. The filter field is specified via its selection bit
9292 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
9294 int t4_filter_field_shift(const struct adapter
*adap
, int filter_sel
)
9296 unsigned int filter_mode
= adap
->params
.tp
.vlan_pri_map
;
9300 if ((filter_mode
& filter_sel
) == 0)
9303 for (sel
= 1, field_shift
= 0; sel
< filter_sel
; sel
<<= 1) {
9304 switch (filter_mode
& sel
) {
9306 field_shift
+= FT_FCOE_W
;
9309 field_shift
+= FT_PORT_W
;
9312 field_shift
+= FT_VNIC_ID_W
;
9315 field_shift
+= FT_VLAN_W
;
9318 field_shift
+= FT_TOS_W
;
9321 field_shift
+= FT_PROTOCOL_W
;
9324 field_shift
+= FT_ETHERTYPE_W
;
9327 field_shift
+= FT_MACMATCH_W
;
9330 field_shift
+= FT_MPSHITTYPE_W
;
9332 case FRAGMENTATION_F
:
9333 field_shift
+= FT_FRAGMENTATION_W
;
9340 int t4_init_rss_mode(struct adapter
*adap
, int mbox
)
9343 struct fw_rss_vi_config_cmd rvc
;
9345 memset(&rvc
, 0, sizeof(rvc
));
9347 for_each_port(adap
, i
) {
9348 struct port_info
*p
= adap2pinfo(adap
, i
);
9351 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD
) |
9352 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
9353 FW_RSS_VI_CONFIG_CMD_VIID_V(p
->viid
));
9354 rvc
.retval_len16
= cpu_to_be32(FW_LEN16(rvc
));
9355 ret
= t4_wr_mbox(adap
, mbox
, &rvc
, sizeof(rvc
), &rvc
);
9358 p
->rss_mode
= be32_to_cpu(rvc
.u
.basicvirtual
.defaultq_to_udpen
);
9364 * t4_init_portinfo - allocate a virtual interface and initialize port_info
9365 * @pi: the port_info
9366 * @mbox: mailbox to use for the FW command
9367 * @port: physical port associated with the VI
9368 * @pf: the PF owning the VI
9369 * @vf: the VF owning the VI
9370 * @mac: the MAC address of the VI
9372 * Allocates a virtual interface for the given physical port. If @mac is
9373 * not %NULL it contains the MAC address of the VI as assigned by FW.
9374 * @mac should be large enough to hold an Ethernet address.
9375 * Returns < 0 on error.
9377 int t4_init_portinfo(struct port_info
*pi
, int mbox
,
9378 int port
, int pf
, int vf
, u8 mac
[])
9380 struct adapter
*adapter
= pi
->adapter
;
9381 unsigned int fw_caps
= adapter
->params
.fw_caps_support
;
9382 struct fw_port_cmd cmd
;
9383 unsigned int rss_size
;
9384 enum fw_port_type port_type
;
9386 fw_port_cap32_t pcaps
, acaps
;
9387 u8 vivld
= 0, vin
= 0;
9390 /* If we haven't yet determined whether we're talking to Firmware
9391 * which knows the new 32-bit Port Capabilities, it's time to find
9392 * out now. This will also tell new Firmware to send us Port Status
9393 * Updates using the new 32-bit Port Capabilities version of the
9394 * Port Information message.
9396 if (fw_caps
== FW_CAPS_UNKNOWN
) {
9399 param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF
) |
9400 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_PORT_CAPS32
));
9402 ret
= t4_set_params(adapter
, mbox
, pf
, vf
, 1, ¶m
, &val
);
9403 fw_caps
= (ret
== 0 ? FW_CAPS32
: FW_CAPS16
);
9404 adapter
->params
.fw_caps_support
= fw_caps
;
9407 memset(&cmd
, 0, sizeof(cmd
));
9408 cmd
.op_to_portid
= cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD
) |
9409 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
9410 FW_PORT_CMD_PORTID_V(port
));
9411 cmd
.action_to_len16
= cpu_to_be32(
9412 FW_PORT_CMD_ACTION_V(fw_caps
== FW_CAPS16
9413 ? FW_PORT_ACTION_GET_PORT_INFO
9414 : FW_PORT_ACTION_GET_PORT_INFO32
) |
9416 ret
= t4_wr_mbox(pi
->adapter
, mbox
, &cmd
, sizeof(cmd
), &cmd
);
9420 /* Extract the various fields from the Port Information message.
9422 if (fw_caps
== FW_CAPS16
) {
9423 u32 lstatus
= be32_to_cpu(cmd
.u
.info
.lstatus_to_modtype
);
9425 port_type
= FW_PORT_CMD_PTYPE_G(lstatus
);
9426 mdio_addr
= ((lstatus
& FW_PORT_CMD_MDIOCAP_F
)
9427 ? FW_PORT_CMD_MDIOADDR_G(lstatus
)
9429 pcaps
= fwcaps16_to_caps32(be16_to_cpu(cmd
.u
.info
.pcap
));
9430 acaps
= fwcaps16_to_caps32(be16_to_cpu(cmd
.u
.info
.acap
));
9432 u32 lstatus32
= be32_to_cpu(cmd
.u
.info32
.lstatus32_to_cbllen32
);
9434 port_type
= FW_PORT_CMD_PORTTYPE32_G(lstatus32
);
9435 mdio_addr
= ((lstatus32
& FW_PORT_CMD_MDIOCAP32_F
)
9436 ? FW_PORT_CMD_MDIOADDR32_G(lstatus32
)
9438 pcaps
= be32_to_cpu(cmd
.u
.info32
.pcaps32
);
9439 acaps
= be32_to_cpu(cmd
.u
.info32
.acaps32
);
9442 ret
= t4_alloc_vi(pi
->adapter
, mbox
, port
, pf
, vf
, 1, mac
, &rss_size
,
9450 pi
->rss_size
= rss_size
;
9452 /* If fw supports returning the VIN as part of FW_VI_CMD,
9453 * save the returned values.
9455 if (adapter
->params
.viid_smt_extn_support
) {
9459 /* Retrieve the values from VIID */
9460 pi
->vivld
= FW_VIID_VIVLD_G(pi
->viid
);
9461 pi
->vin
= FW_VIID_VIN_G(pi
->viid
);
9464 pi
->port_type
= port_type
;
9465 pi
->mdio_addr
= mdio_addr
;
9466 pi
->mod_type
= FW_PORT_MOD_TYPE_NA
;
9468 init_link_config(&pi
->link_cfg
, pcaps
, acaps
);
9472 int t4_port_init(struct adapter
*adap
, int mbox
, int pf
, int vf
)
9477 for_each_port(adap
, i
) {
9478 struct port_info
*pi
= adap2pinfo(adap
, i
);
9480 while ((adap
->params
.portvec
& (1 << j
)) == 0)
9483 ret
= t4_init_portinfo(pi
, mbox
, j
, pf
, vf
, addr
);
9487 memcpy(adap
->port
[i
]->dev_addr
, addr
, ETH_ALEN
);
9494 * t4_read_cimq_cfg - read CIM queue configuration
9495 * @adap: the adapter
9496 * @base: holds the queue base addresses in bytes
9497 * @size: holds the queue sizes in bytes
9498 * @thres: holds the queue full thresholds in bytes
9500 * Returns the current configuration of the CIM queues, starting with
9501 * the IBQs, then the OBQs.
9503 void t4_read_cimq_cfg(struct adapter
*adap
, u16
*base
, u16
*size
, u16
*thres
)
9506 int cim_num_obq
= is_t4(adap
->params
.chip
) ?
9507 CIM_NUM_OBQ
: CIM_NUM_OBQ_T5
;
9509 for (i
= 0; i
< CIM_NUM_IBQ
; i
++) {
9510 t4_write_reg(adap
, CIM_QUEUE_CONFIG_REF_A
, IBQSELECT_F
|
9512 v
= t4_read_reg(adap
, CIM_QUEUE_CONFIG_CTRL_A
);
9513 /* value is in 256-byte units */
9514 *base
++ = CIMQBASE_G(v
) * 256;
9515 *size
++ = CIMQSIZE_G(v
) * 256;
9516 *thres
++ = QUEFULLTHRSH_G(v
) * 8; /* 8-byte unit */
9518 for (i
= 0; i
< cim_num_obq
; i
++) {
9519 t4_write_reg(adap
, CIM_QUEUE_CONFIG_REF_A
, OBQSELECT_F
|
9521 v
= t4_read_reg(adap
, CIM_QUEUE_CONFIG_CTRL_A
);
9522 /* value is in 256-byte units */
9523 *base
++ = CIMQBASE_G(v
) * 256;
9524 *size
++ = CIMQSIZE_G(v
) * 256;
9529 * t4_read_cim_ibq - read the contents of a CIM inbound queue
9530 * @adap: the adapter
9531 * @qid: the queue index
9532 * @data: where to store the queue contents
9533 * @n: capacity of @data in 32-bit words
9535 * Reads the contents of the selected CIM queue starting at address 0 up
9536 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9537 * error and the number of 32-bit words actually read on success.
9539 int t4_read_cim_ibq(struct adapter
*adap
, unsigned int qid
, u32
*data
, size_t n
)
9541 int i
, err
, attempts
;
9543 const unsigned int nwords
= CIM_IBQ_SIZE
* 4;
9545 if (qid
> 5 || (n
& 3))
9548 addr
= qid
* nwords
;
9552 /* It might take 3-10ms before the IBQ debug read access is allowed.
9553 * Wait for 1 Sec with a delay of 1 usec.
9557 for (i
= 0; i
< n
; i
++, addr
++) {
9558 t4_write_reg(adap
, CIM_IBQ_DBG_CFG_A
, IBQDBGADDR_V(addr
) |
9560 err
= t4_wait_op_done(adap
, CIM_IBQ_DBG_CFG_A
, IBQDBGBUSY_F
, 0,
9564 *data
++ = t4_read_reg(adap
, CIM_IBQ_DBG_DATA_A
);
9566 t4_write_reg(adap
, CIM_IBQ_DBG_CFG_A
, 0);
9571 * t4_read_cim_obq - read the contents of a CIM outbound queue
9572 * @adap: the adapter
9573 * @qid: the queue index
9574 * @data: where to store the queue contents
9575 * @n: capacity of @data in 32-bit words
9577 * Reads the contents of the selected CIM queue starting at address 0 up
9578 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9579 * error and the number of 32-bit words actually read on success.
9581 int t4_read_cim_obq(struct adapter
*adap
, unsigned int qid
, u32
*data
, size_t n
)
9584 unsigned int addr
, v
, nwords
;
9585 int cim_num_obq
= is_t4(adap
->params
.chip
) ?
9586 CIM_NUM_OBQ
: CIM_NUM_OBQ_T5
;
9588 if ((qid
> (cim_num_obq
- 1)) || (n
& 3))
9591 t4_write_reg(adap
, CIM_QUEUE_CONFIG_REF_A
, OBQSELECT_F
|
9592 QUENUMSELECT_V(qid
));
9593 v
= t4_read_reg(adap
, CIM_QUEUE_CONFIG_CTRL_A
);
9595 addr
= CIMQBASE_G(v
) * 64; /* muliple of 256 -> muliple of 4 */
9596 nwords
= CIMQSIZE_G(v
) * 64; /* same */
9600 for (i
= 0; i
< n
; i
++, addr
++) {
9601 t4_write_reg(adap
, CIM_OBQ_DBG_CFG_A
, OBQDBGADDR_V(addr
) |
9603 err
= t4_wait_op_done(adap
, CIM_OBQ_DBG_CFG_A
, OBQDBGBUSY_F
, 0,
9607 *data
++ = t4_read_reg(adap
, CIM_OBQ_DBG_DATA_A
);
9609 t4_write_reg(adap
, CIM_OBQ_DBG_CFG_A
, 0);
9614 * t4_cim_read - read a block from CIM internal address space
9615 * @adap: the adapter
9616 * @addr: the start address within the CIM address space
9617 * @n: number of words to read
9618 * @valp: where to store the result
9620 * Reads a block of 4-byte words from the CIM intenal address space.
9622 int t4_cim_read(struct adapter
*adap
, unsigned int addr
, unsigned int n
,
9627 if (t4_read_reg(adap
, CIM_HOST_ACC_CTRL_A
) & HOSTBUSY_F
)
9630 for ( ; !ret
&& n
--; addr
+= 4) {
9631 t4_write_reg(adap
, CIM_HOST_ACC_CTRL_A
, addr
);
9632 ret
= t4_wait_op_done(adap
, CIM_HOST_ACC_CTRL_A
, HOSTBUSY_F
,
9635 *valp
++ = t4_read_reg(adap
, CIM_HOST_ACC_DATA_A
);
9641 * t4_cim_write - write a block into CIM internal address space
9642 * @adap: the adapter
9643 * @addr: the start address within the CIM address space
9644 * @n: number of words to write
9645 * @valp: set of values to write
9647 * Writes a block of 4-byte words into the CIM intenal address space.
9649 int t4_cim_write(struct adapter
*adap
, unsigned int addr
, unsigned int n
,
9650 const unsigned int *valp
)
9654 if (t4_read_reg(adap
, CIM_HOST_ACC_CTRL_A
) & HOSTBUSY_F
)
9657 for ( ; !ret
&& n
--; addr
+= 4) {
9658 t4_write_reg(adap
, CIM_HOST_ACC_DATA_A
, *valp
++);
9659 t4_write_reg(adap
, CIM_HOST_ACC_CTRL_A
, addr
| HOSTWRITE_F
);
9660 ret
= t4_wait_op_done(adap
, CIM_HOST_ACC_CTRL_A
, HOSTBUSY_F
,
9666 static int t4_cim_write1(struct adapter
*adap
, unsigned int addr
,
9669 return t4_cim_write(adap
, addr
, 1, &val
);
9673 * t4_cim_read_la - read CIM LA capture buffer
9674 * @adap: the adapter
9675 * @la_buf: where to store the LA data
9676 * @wrptr: the HW write pointer within the capture buffer
9678 * Reads the contents of the CIM LA buffer with the most recent entry at
9679 * the end of the returned data and with the entry at @wrptr first.
9680 * We try to leave the LA in the running state we find it in.
9682 int t4_cim_read_la(struct adapter
*adap
, u32
*la_buf
, unsigned int *wrptr
)
9685 unsigned int cfg
, val
, idx
;
9687 ret
= t4_cim_read(adap
, UP_UP_DBG_LA_CFG_A
, 1, &cfg
);
9691 if (cfg
& UPDBGLAEN_F
) { /* LA is running, freeze it */
9692 ret
= t4_cim_write1(adap
, UP_UP_DBG_LA_CFG_A
, 0);
9697 ret
= t4_cim_read(adap
, UP_UP_DBG_LA_CFG_A
, 1, &val
);
9701 idx
= UPDBGLAWRPTR_G(val
);
9705 for (i
= 0; i
< adap
->params
.cim_la_size
; i
++) {
9706 ret
= t4_cim_write1(adap
, UP_UP_DBG_LA_CFG_A
,
9707 UPDBGLARDPTR_V(idx
) | UPDBGLARDEN_F
);
9710 ret
= t4_cim_read(adap
, UP_UP_DBG_LA_CFG_A
, 1, &val
);
9713 if (val
& UPDBGLARDEN_F
) {
9717 ret
= t4_cim_read(adap
, UP_UP_DBG_LA_DATA_A
, 1, &la_buf
[i
]);
9721 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9722 * identify the 32-bit portion of the full 312-bit data
9724 if (is_t6(adap
->params
.chip
) && (idx
& 0xf) >= 9)
9725 idx
= (idx
& 0xff0) + 0x10;
9728 /* address can't exceed 0xfff */
9729 idx
&= UPDBGLARDPTR_M
;
9732 if (cfg
& UPDBGLAEN_F
) {
9733 int r
= t4_cim_write1(adap
, UP_UP_DBG_LA_CFG_A
,
9734 cfg
& ~UPDBGLARDEN_F
);
9742 * t4_tp_read_la - read TP LA capture buffer
9743 * @adap: the adapter
9744 * @la_buf: where to store the LA data
9745 * @wrptr: the HW write pointer within the capture buffer
9747 * Reads the contents of the TP LA buffer with the most recent entry at
9748 * the end of the returned data and with the entry at @wrptr first.
9749 * We leave the LA in the running state we find it in.
9751 void t4_tp_read_la(struct adapter
*adap
, u64
*la_buf
, unsigned int *wrptr
)
9753 bool last_incomplete
;
9754 unsigned int i
, cfg
, val
, idx
;
9756 cfg
= t4_read_reg(adap
, TP_DBG_LA_CONFIG_A
) & 0xffff;
9757 if (cfg
& DBGLAENABLE_F
) /* freeze LA */
9758 t4_write_reg(adap
, TP_DBG_LA_CONFIG_A
,
9759 adap
->params
.tp
.la_mask
| (cfg
^ DBGLAENABLE_F
));
9761 val
= t4_read_reg(adap
, TP_DBG_LA_CONFIG_A
);
9762 idx
= DBGLAWPTR_G(val
);
9763 last_incomplete
= DBGLAMODE_G(val
) >= 2 && (val
& DBGLAWHLF_F
) == 0;
9764 if (last_incomplete
)
9765 idx
= (idx
+ 1) & DBGLARPTR_M
;
9770 val
&= ~DBGLARPTR_V(DBGLARPTR_M
);
9771 val
|= adap
->params
.tp
.la_mask
;
9773 for (i
= 0; i
< TPLA_SIZE
; i
++) {
9774 t4_write_reg(adap
, TP_DBG_LA_CONFIG_A
, DBGLARPTR_V(idx
) | val
);
9775 la_buf
[i
] = t4_read_reg64(adap
, TP_DBG_LA_DATAL_A
);
9776 idx
= (idx
+ 1) & DBGLARPTR_M
;
9779 /* Wipe out last entry if it isn't valid */
9780 if (last_incomplete
)
9781 la_buf
[TPLA_SIZE
- 1] = ~0ULL;
9783 if (cfg
& DBGLAENABLE_F
) /* restore running state */
9784 t4_write_reg(adap
, TP_DBG_LA_CONFIG_A
,
9785 cfg
| adap
->params
.tp
.la_mask
);
9788 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
9789 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
9790 * state for more than the Warning Threshold then we'll issue a warning about
9791 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
9792 * appears to be hung every Warning Repeat second till the situation clears.
9793 * If the situation clears, we'll note that as well.
9795 #define SGE_IDMA_WARN_THRESH 1
9796 #define SGE_IDMA_WARN_REPEAT 300
9799 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
9800 * @adapter: the adapter
9801 * @idma: the adapter IDMA Monitor state
9803 * Initialize the state of an SGE Ingress DMA Monitor.
9805 void t4_idma_monitor_init(struct adapter
*adapter
,
9806 struct sge_idma_monitor_state
*idma
)
9808 /* Initialize the state variables for detecting an SGE Ingress DMA
9809 * hang. The SGE has internal counters which count up on each clock
9810 * tick whenever the SGE finds its Ingress DMA State Engines in the
9811 * same state they were on the previous clock tick. The clock used is
9812 * the Core Clock so we have a limit on the maximum "time" they can
9813 * record; typically a very small number of seconds. For instance,
9814 * with a 600MHz Core Clock, we can only count up to a bit more than
9815 * 7s. So we'll synthesize a larger counter in order to not run the
9816 * risk of having the "timers" overflow and give us the flexibility to
9817 * maintain a Hung SGE State Machine of our own which operates across
9818 * a longer time frame.
9820 idma
->idma_1s_thresh
= core_ticks_per_usec(adapter
) * 1000000; /* 1s */
9821 idma
->idma_stalled
[0] = 0;
9822 idma
->idma_stalled
[1] = 0;
9826 * t4_idma_monitor - monitor SGE Ingress DMA state
9827 * @adapter: the adapter
9828 * @idma: the adapter IDMA Monitor state
9829 * @hz: number of ticks/second
9830 * @ticks: number of ticks since the last IDMA Monitor call
9832 void t4_idma_monitor(struct adapter
*adapter
,
9833 struct sge_idma_monitor_state
*idma
,
9836 int i
, idma_same_state_cnt
[2];
9838 /* Read the SGE Debug Ingress DMA Same State Count registers. These
9839 * are counters inside the SGE which count up on each clock when the
9840 * SGE finds its Ingress DMA State Engines in the same states they
9841 * were in the previous clock. The counters will peg out at
9842 * 0xffffffff without wrapping around so once they pass the 1s
9843 * threshold they'll stay above that till the IDMA state changes.
9845 t4_write_reg(adapter
, SGE_DEBUG_INDEX_A
, 13);
9846 idma_same_state_cnt
[0] = t4_read_reg(adapter
, SGE_DEBUG_DATA_HIGH_A
);
9847 idma_same_state_cnt
[1] = t4_read_reg(adapter
, SGE_DEBUG_DATA_LOW_A
);
9849 for (i
= 0; i
< 2; i
++) {
9850 u32 debug0
, debug11
;
9852 /* If the Ingress DMA Same State Counter ("timer") is less
9853 * than 1s, then we can reset our synthesized Stall Timer and
9854 * continue. If we have previously emitted warnings about a
9855 * potential stalled Ingress Queue, issue a note indicating
9856 * that the Ingress Queue has resumed forward progress.
9858 if (idma_same_state_cnt
[i
] < idma
->idma_1s_thresh
) {
9859 if (idma
->idma_stalled
[i
] >= SGE_IDMA_WARN_THRESH
* hz
)
9860 dev_warn(adapter
->pdev_dev
, "SGE idma%d, queue %u, "
9861 "resumed after %d seconds\n",
9862 i
, idma
->idma_qid
[i
],
9863 idma
->idma_stalled
[i
] / hz
);
9864 idma
->idma_stalled
[i
] = 0;
9868 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
9869 * domain. The first time we get here it'll be because we
9870 * passed the 1s Threshold; each additional time it'll be
9871 * because the RX Timer Callback is being fired on its regular
9874 * If the stall is below our Potential Hung Ingress Queue
9875 * Warning Threshold, continue.
9877 if (idma
->idma_stalled
[i
] == 0) {
9878 idma
->idma_stalled
[i
] = hz
;
9879 idma
->idma_warn
[i
] = 0;
9881 idma
->idma_stalled
[i
] += ticks
;
9882 idma
->idma_warn
[i
] -= ticks
;
9885 if (idma
->idma_stalled
[i
] < SGE_IDMA_WARN_THRESH
* hz
)
9888 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
9890 if (idma
->idma_warn
[i
] > 0)
9892 idma
->idma_warn
[i
] = SGE_IDMA_WARN_REPEAT
* hz
;
9894 /* Read and save the SGE IDMA State and Queue ID information.
9895 * We do this every time in case it changes across time ...
9896 * can't be too careful ...
9898 t4_write_reg(adapter
, SGE_DEBUG_INDEX_A
, 0);
9899 debug0
= t4_read_reg(adapter
, SGE_DEBUG_DATA_LOW_A
);
9900 idma
->idma_state
[i
] = (debug0
>> (i
* 9)) & 0x3f;
9902 t4_write_reg(adapter
, SGE_DEBUG_INDEX_A
, 11);
9903 debug11
= t4_read_reg(adapter
, SGE_DEBUG_DATA_LOW_A
);
9904 idma
->idma_qid
[i
] = (debug11
>> (i
* 16)) & 0xffff;
9906 dev_warn(adapter
->pdev_dev
, "SGE idma%u, queue %u, potentially stuck in "
9907 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
9908 i
, idma
->idma_qid
[i
], idma
->idma_state
[i
],
9909 idma
->idma_stalled
[i
] / hz
,
9911 t4_sge_decode_idma_state(adapter
, idma
->idma_state
[i
]);
9916 * t4_load_cfg - download config file
9917 * @adap: the adapter
9918 * @cfg_data: the cfg text file to write
9919 * @size: text file size
9921 * Write the supplied config text file to the card's serial flash.
9923 int t4_load_cfg(struct adapter
*adap
, const u8
*cfg_data
, unsigned int size
)
9925 int ret
, i
, n
, cfg_addr
;
9927 unsigned int flash_cfg_start_sec
;
9928 unsigned int sf_sec_size
= adap
->params
.sf_size
/ adap
->params
.sf_nsec
;
9930 cfg_addr
= t4_flash_cfg_addr(adap
);
9935 flash_cfg_start_sec
= addr
/ SF_SEC_SIZE
;
9937 if (size
> FLASH_CFG_MAX_SIZE
) {
9938 dev_err(adap
->pdev_dev
, "cfg file too large, max is %u bytes\n",
9939 FLASH_CFG_MAX_SIZE
);
9943 i
= DIV_ROUND_UP(FLASH_CFG_MAX_SIZE
, /* # of sectors spanned */
9945 ret
= t4_flash_erase_sectors(adap
, flash_cfg_start_sec
,
9946 flash_cfg_start_sec
+ i
- 1);
9947 /* If size == 0 then we're simply erasing the FLASH sectors associated
9948 * with the on-adapter Firmware Configuration File.
9950 if (ret
|| size
== 0)
9953 /* this will write to the flash up to SF_PAGE_SIZE at a time */
9954 for (i
= 0; i
< size
; i
+= SF_PAGE_SIZE
) {
9955 if ((size
- i
) < SF_PAGE_SIZE
)
9959 ret
= t4_write_flash(adap
, addr
, n
, cfg_data
);
9963 addr
+= SF_PAGE_SIZE
;
9964 cfg_data
+= SF_PAGE_SIZE
;
9969 dev_err(adap
->pdev_dev
, "config file %s failed %d\n",
9970 (size
== 0 ? "clear" : "download"), ret
);
9975 * t4_set_vf_mac - Set MAC address for the specified VF
9976 * @adapter: The adapter
9977 * @vf: one of the VFs instantiated by the specified PF
9978 * @naddr: the number of MAC addresses
9979 * @addr: the MAC address(es) to be set to the specified VF
9981 int t4_set_vf_mac_acl(struct adapter
*adapter
, unsigned int vf
,
9982 unsigned int naddr
, u8
*addr
)
9984 struct fw_acl_mac_cmd cmd
;
9986 memset(&cmd
, 0, sizeof(cmd
));
9987 cmd
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD
) |
9990 FW_ACL_MAC_CMD_PFN_V(adapter
->pf
) |
9991 FW_ACL_MAC_CMD_VFN_V(vf
));
9993 /* Note: Do not enable the ACL */
9994 cmd
.en_to_len16
= cpu_to_be32((unsigned int)FW_LEN16(cmd
));
9997 switch (adapter
->pf
) {
9999 memcpy(cmd
.macaddr3
, addr
, sizeof(cmd
.macaddr3
));
10002 memcpy(cmd
.macaddr2
, addr
, sizeof(cmd
.macaddr2
));
10005 memcpy(cmd
.macaddr1
, addr
, sizeof(cmd
.macaddr1
));
10008 memcpy(cmd
.macaddr0
, addr
, sizeof(cmd
.macaddr0
));
10012 return t4_wr_mbox(adapter
, adapter
->mbox
, &cmd
, sizeof(cmd
), &cmd
);
10016 * t4_read_pace_tbl - read the pace table
10017 * @adap: the adapter
10018 * @pace_vals: holds the returned values
10020 * Returns the values of TP's pace table in microseconds.
10022 void t4_read_pace_tbl(struct adapter
*adap
, unsigned int pace_vals
[NTX_SCHED
])
10026 for (i
= 0; i
< NTX_SCHED
; i
++) {
10027 t4_write_reg(adap
, TP_PACE_TABLE_A
, 0xffff0000 + i
);
10028 v
= t4_read_reg(adap
, TP_PACE_TABLE_A
);
10029 pace_vals
[i
] = dack_ticks_to_usec(adap
, v
);
10034 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
10035 * @adap: the adapter
10036 * @sched: the scheduler index
10037 * @kbps: the byte rate in Kbps
10038 * @ipg: the interpacket delay in tenths of nanoseconds
10039 * @sleep_ok: if true we may sleep while awaiting command completion
10041 * Return the current configuration of a HW Tx scheduler.
10043 void t4_get_tx_sched(struct adapter
*adap
, unsigned int sched
,
10044 unsigned int *kbps
, unsigned int *ipg
, bool sleep_ok
)
10046 unsigned int v
, addr
, bpt
, cpt
;
10049 addr
= TP_TX_MOD_Q1_Q0_RATE_LIMIT_A
- sched
/ 2;
10050 t4_tp_tm_pio_read(adap
, &v
, 1, addr
, sleep_ok
);
10053 bpt
= (v
>> 8) & 0xff;
10056 *kbps
= 0; /* scheduler disabled */
10058 v
= (adap
->params
.vpd
.cclk
* 1000) / cpt
; /* ticks/s */
10059 *kbps
= (v
* bpt
) / 125;
10063 addr
= TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A
- sched
/ 2;
10064 t4_tp_tm_pio_read(adap
, &v
, 1, addr
, sleep_ok
);
10068 *ipg
= (10000 * v
) / core_ticks_per_usec(adap
);
10072 /* t4_sge_ctxt_rd - read an SGE context through FW
10073 * @adap: the adapter
10074 * @mbox: mailbox to use for the FW command
10075 * @cid: the context id
10076 * @ctype: the context type
10077 * @data: where to store the context data
10079 * Issues a FW command through the given mailbox to read an SGE context.
10081 int t4_sge_ctxt_rd(struct adapter
*adap
, unsigned int mbox
, unsigned int cid
,
10082 enum ctxt_type ctype
, u32
*data
)
10084 struct fw_ldst_cmd c
;
10087 if (ctype
== CTXT_FLM
)
10088 ret
= FW_LDST_ADDRSPC_SGE_FLMC
;
10090 ret
= FW_LDST_ADDRSPC_SGE_CONMC
;
10092 memset(&c
, 0, sizeof(c
));
10093 c
.op_to_addrspace
= cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
10094 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
10095 FW_LDST_CMD_ADDRSPACE_V(ret
));
10096 c
.cycles_to_len16
= cpu_to_be32(FW_LEN16(c
));
10097 c
.u
.idctxt
.physid
= cpu_to_be32(cid
);
10099 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
10101 data
[0] = be32_to_cpu(c
.u
.idctxt
.ctxt_data0
);
10102 data
[1] = be32_to_cpu(c
.u
.idctxt
.ctxt_data1
);
10103 data
[2] = be32_to_cpu(c
.u
.idctxt
.ctxt_data2
);
10104 data
[3] = be32_to_cpu(c
.u
.idctxt
.ctxt_data3
);
10105 data
[4] = be32_to_cpu(c
.u
.idctxt
.ctxt_data4
);
10106 data
[5] = be32_to_cpu(c
.u
.idctxt
.ctxt_data5
);
10112 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
10113 * @adap: the adapter
10114 * @cid: the context id
10115 * @ctype: the context type
10116 * @data: where to store the context data
10118 * Reads an SGE context directly, bypassing FW. This is only for
10119 * debugging when FW is unavailable.
10121 int t4_sge_ctxt_rd_bd(struct adapter
*adap
, unsigned int cid
,
10122 enum ctxt_type ctype
, u32
*data
)
10126 t4_write_reg(adap
, SGE_CTXT_CMD_A
, CTXTQID_V(cid
) | CTXTTYPE_V(ctype
));
10127 ret
= t4_wait_op_done(adap
, SGE_CTXT_CMD_A
, BUSY_F
, 0, 3, 1);
10129 for (i
= SGE_CTXT_DATA0_A
; i
<= SGE_CTXT_DATA5_A
; i
+= 4)
10130 *data
++ = t4_read_reg(adap
, i
);
10134 int t4_sched_params(struct adapter
*adapter
, int type
, int level
, int mode
,
10135 int rateunit
, int ratemode
, int channel
, int class,
10136 int minrate
, int maxrate
, int weight
, int pktsize
)
10138 struct fw_sched_cmd cmd
;
10140 memset(&cmd
, 0, sizeof(cmd
));
10141 cmd
.op_to_write
= cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD
) |
10144 cmd
.retval_len16
= cpu_to_be32(FW_LEN16(cmd
));
10146 cmd
.u
.params
.sc
= FW_SCHED_SC_PARAMS
;
10147 cmd
.u
.params
.type
= type
;
10148 cmd
.u
.params
.level
= level
;
10149 cmd
.u
.params
.mode
= mode
;
10150 cmd
.u
.params
.ch
= channel
;
10151 cmd
.u
.params
.cl
= class;
10152 cmd
.u
.params
.unit
= rateunit
;
10153 cmd
.u
.params
.rate
= ratemode
;
10154 cmd
.u
.params
.min
= cpu_to_be32(minrate
);
10155 cmd
.u
.params
.max
= cpu_to_be32(maxrate
);
10156 cmd
.u
.params
.weight
= cpu_to_be16(weight
);
10157 cmd
.u
.params
.pktsize
= cpu_to_be16(pktsize
);
10159 return t4_wr_mbox_meat(adapter
, adapter
->mbox
, &cmd
, sizeof(cmd
),
10164 * t4_i2c_rd - read I2C data from adapter
10165 * @adap: the adapter
10166 * @port: Port number if per-port device; <0 if not
10167 * @devid: per-port device ID or absolute device ID
10168 * @offset: byte offset into device I2C space
10169 * @len: byte length of I2C space data
10170 * @buf: buffer in which to return I2C data
10172 * Reads the I2C data from the indicated device and location.
10174 int t4_i2c_rd(struct adapter
*adap
, unsigned int mbox
, int port
,
10175 unsigned int devid
, unsigned int offset
,
10176 unsigned int len
, u8
*buf
)
10178 struct fw_ldst_cmd ldst_cmd
, ldst_rpl
;
10179 unsigned int i2c_max
= sizeof(ldst_cmd
.u
.i2c
.data
);
10182 if (len
> I2C_PAGE_SIZE
)
10185 /* Dont allow reads that spans multiple pages */
10186 if (offset
< I2C_PAGE_SIZE
&& offset
+ len
> I2C_PAGE_SIZE
)
10189 memset(&ldst_cmd
, 0, sizeof(ldst_cmd
));
10190 ldst_cmd
.op_to_addrspace
=
10191 cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD
) |
10194 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_I2C
));
10195 ldst_cmd
.cycles_to_len16
= cpu_to_be32(FW_LEN16(ldst_cmd
));
10196 ldst_cmd
.u
.i2c
.pid
= (port
< 0 ? 0xff : port
);
10197 ldst_cmd
.u
.i2c
.did
= devid
;
10200 unsigned int i2c_len
= (len
< i2c_max
) ? len
: i2c_max
;
10202 ldst_cmd
.u
.i2c
.boffset
= offset
;
10203 ldst_cmd
.u
.i2c
.blen
= i2c_len
;
10205 ret
= t4_wr_mbox(adap
, mbox
, &ldst_cmd
, sizeof(ldst_cmd
),
10210 memcpy(buf
, ldst_rpl
.u
.i2c
.data
, i2c_len
);
10220 * t4_set_vlan_acl - Set a VLAN id for the specified VF
10221 * @adapter: the adapter
10222 * @mbox: mailbox to use for the FW command
10223 * @vf: one of the VFs instantiated by the specified PF
10224 * @vlan: The vlanid to be set
10226 int t4_set_vlan_acl(struct adapter
*adap
, unsigned int mbox
, unsigned int vf
,
10229 struct fw_acl_vlan_cmd vlan_cmd
;
10230 unsigned int enable
;
10232 enable
= (vlan
? FW_ACL_VLAN_CMD_EN_F
: 0);
10233 memset(&vlan_cmd
, 0, sizeof(vlan_cmd
));
10234 vlan_cmd
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_ACL_VLAN_CMD
) |
10238 FW_ACL_VLAN_CMD_PFN_V(adap
->pf
) |
10239 FW_ACL_VLAN_CMD_VFN_V(vf
));
10240 vlan_cmd
.en_to_len16
= cpu_to_be32(enable
| FW_LEN16(vlan_cmd
));
10241 /* Drop all packets that donot match vlan id */
10242 vlan_cmd
.dropnovlan_fm
= (enable
10243 ? (FW_ACL_VLAN_CMD_DROPNOVLAN_F
|
10244 FW_ACL_VLAN_CMD_FM_F
) : 0);
10246 vlan_cmd
.nvlan
= 1;
10247 vlan_cmd
.vlanid
[0] = cpu_to_be16(vlan
);
10250 return t4_wr_mbox(adap
, adap
->mbox
, &vlan_cmd
, sizeof(vlan_cmd
), NULL
);