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Merge branch 'cxgb4-mbox-cmd-logging'
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / chelsio / cxgb4 / t4_hw.c
1 /*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/delay.h>
36 #include "cxgb4.h"
37 #include "t4_regs.h"
38 #include "t4_values.h"
39 #include "t4fw_api.h"
40 #include "t4fw_version.h"
41
42 /**
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
51 *
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
56 */
57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
58 int polarity, int attempts, int delay, u32 *valp)
59 {
60 while (1) {
61 u32 val = t4_read_reg(adapter, reg);
62
63 if (!!(val & mask) == polarity) {
64 if (valp)
65 *valp = val;
66 return 0;
67 }
68 if (--attempts == 0)
69 return -EAGAIN;
70 if (delay)
71 udelay(delay);
72 }
73 }
74
75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
76 int polarity, int attempts, int delay)
77 {
78 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
79 delay, NULL);
80 }
81
82 /**
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
88 *
89 * Sets a register field specified by the supplied mask to the
90 * given value.
91 */
92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
93 u32 val)
94 {
95 u32 v = t4_read_reg(adapter, addr) & ~mask;
96
97 t4_write_reg(adapter, addr, v | val);
98 (void) t4_read_reg(adapter, addr); /* flush */
99 }
100
101 /**
102 * t4_read_indirect - read indirectly addressed registers
103 * @adap: the adapter
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
109 *
110 * Reads registers that are accessed indirectly through an address/data
111 * register pair.
112 */
113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
114 unsigned int data_reg, u32 *vals,
115 unsigned int nregs, unsigned int start_idx)
116 {
117 while (nregs--) {
118 t4_write_reg(adap, addr_reg, start_idx);
119 *vals++ = t4_read_reg(adap, data_reg);
120 start_idx++;
121 }
122 }
123
124 /**
125 * t4_write_indirect - write indirectly addressed registers
126 * @adap: the adapter
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
132 *
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
135 */
136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
137 unsigned int data_reg, const u32 *vals,
138 unsigned int nregs, unsigned int start_idx)
139 {
140 while (nregs--) {
141 t4_write_reg(adap, addr_reg, start_idx++);
142 t4_write_reg(adap, data_reg, *vals++);
143 }
144 }
145
146 /*
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
151 */
152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
153 {
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
155
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
157 req |= ENABLE_F;
158 else
159 req |= T6_ENABLE_F;
160
161 if (is_t4(adap->params.chip))
162 req |= LOCALCFG_F;
163
164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
166
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
171 */
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
173 }
174
175 /*
176 * t4_report_fw_error - report firmware error
177 * @adap: the adapter
178 *
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
182 */
183 static void t4_report_fw_error(struct adapter *adap)
184 {
185 static const char *const reason[] = {
186 "Crash", /* PCIE_FW_EVAL_CRASH */
187 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
188 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
189 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
190 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
191 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
192 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
193 "Reserved", /* reserved */
194 };
195 u32 pcie_fw;
196
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
198 if (pcie_fw & PCIE_FW_ERR_F)
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
200 reason[PCIE_FW_EVAL_G(pcie_fw)]);
201 }
202
203 /*
204 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
205 */
206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
207 u32 mbox_addr)
208 {
209 for ( ; nflit; nflit--, mbox_addr += 8)
210 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
211 }
212
213 /*
214 * Handle a FW assertion reported in a mailbox.
215 */
216 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
217 {
218 struct fw_debug_cmd asrt;
219
220 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
221 dev_alert(adap->pdev_dev,
222 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
223 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
224 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
225 }
226
227 /**
228 * t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
229 * @adapter: the adapter
230 * @cmd: the Firmware Mailbox Command or Reply
231 * @size: command length in bytes
232 * @access: the time (ms) needed to access the Firmware Mailbox
233 * @execute: the time (ms) the command spent being executed
234 */
235 static void t4_record_mbox(struct adapter *adapter,
236 const __be64 *cmd, unsigned int size,
237 int access, int execute)
238 {
239 struct mbox_cmd_log *log = adapter->mbox_log;
240 struct mbox_cmd *entry;
241 int i;
242
243 entry = mbox_cmd_log_entry(log, log->cursor++);
244 if (log->cursor == log->size)
245 log->cursor = 0;
246
247 for (i = 0; i < size / 8; i++)
248 entry->cmd[i] = be64_to_cpu(cmd[i]);
249 while (i < MBOX_LEN / 8)
250 entry->cmd[i++] = 0;
251 entry->timestamp = jiffies;
252 entry->seqno = log->seqno++;
253 entry->access = access;
254 entry->execute = execute;
255 }
256
257 /**
258 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
259 * @adap: the adapter
260 * @mbox: index of the mailbox to use
261 * @cmd: the command to write
262 * @size: command length in bytes
263 * @rpl: where to optionally store the reply
264 * @sleep_ok: if true we may sleep while awaiting command completion
265 * @timeout: time to wait for command to finish before timing out
266 *
267 * Sends the given command to FW through the selected mailbox and waits
268 * for the FW to execute the command. If @rpl is not %NULL it is used to
269 * store the FW's reply to the command. The command and its optional
270 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
271 * to respond. @sleep_ok determines whether we may sleep while awaiting
272 * the response. If sleeping is allowed we use progressive backoff
273 * otherwise we spin.
274 *
275 * The return value is 0 on success or a negative errno on failure. A
276 * failure can happen either because we are not able to execute the
277 * command or FW executes it but signals an error. In the latter case
278 * the return value is the error code indicated by FW (negated).
279 */
280 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
281 int size, void *rpl, bool sleep_ok, int timeout)
282 {
283 static const int delay[] = {
284 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
285 };
286
287 u16 access = 0;
288 u16 execute = 0;
289 u32 v;
290 u64 res;
291 int i, ms, delay_idx, ret;
292 const __be64 *p = cmd;
293 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
294 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
295 __be64 cmd_rpl[MBOX_LEN / 8];
296
297 if ((size & 15) || size > MBOX_LEN)
298 return -EINVAL;
299
300 /*
301 * If the device is off-line, as in EEH, commands will time out.
302 * Fail them early so we don't waste time waiting.
303 */
304 if (adap->pdev->error_state != pci_channel_io_normal)
305 return -EIO;
306
307 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
308 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
309 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
310
311 if (v != MBOX_OWNER_DRV) {
312 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
313 t4_record_mbox(adap, cmd, MBOX_LEN, access, ret);
314 return ret;
315 }
316
317 /* Copy in the new mailbox command and send it on its way ... */
318 t4_record_mbox(adap, cmd, MBOX_LEN, access, 0);
319 for (i = 0; i < size; i += 8)
320 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
321
322 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
323 t4_read_reg(adap, ctl_reg); /* flush write */
324
325 delay_idx = 0;
326 ms = delay[0];
327
328 for (i = 0; i < timeout; i += ms) {
329 if (sleep_ok) {
330 ms = delay[delay_idx]; /* last element may repeat */
331 if (delay_idx < ARRAY_SIZE(delay) - 1)
332 delay_idx++;
333 msleep(ms);
334 } else
335 mdelay(ms);
336
337 v = t4_read_reg(adap, ctl_reg);
338 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
339 if (!(v & MBMSGVALID_F)) {
340 t4_write_reg(adap, ctl_reg, 0);
341 continue;
342 }
343
344 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
345 res = be64_to_cpu(cmd_rpl[0]);
346
347 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
348 fw_asrt(adap, data_reg);
349 res = FW_CMD_RETVAL_V(EIO);
350 } else if (rpl) {
351 memcpy(rpl, cmd_rpl, size);
352 }
353
354 t4_write_reg(adap, ctl_reg, 0);
355
356 execute = i + ms;
357 t4_record_mbox(adap, cmd_rpl,
358 MBOX_LEN, access, execute);
359 return -FW_CMD_RETVAL_G((int)res);
360 }
361 }
362
363 ret = -ETIMEDOUT;
364 t4_record_mbox(adap, cmd, MBOX_LEN, access, ret);
365 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
366 *(const u8 *)cmd, mbox);
367 t4_report_fw_error(adap);
368 return ret;
369 }
370
371 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
372 void *rpl, bool sleep_ok)
373 {
374 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
375 FW_CMD_MAX_TIMEOUT);
376 }
377
378 static int t4_edc_err_read(struct adapter *adap, int idx)
379 {
380 u32 edc_ecc_err_addr_reg;
381 u32 rdata_reg;
382
383 if (is_t4(adap->params.chip)) {
384 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
385 return 0;
386 }
387 if (idx != 0 && idx != 1) {
388 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
389 return 0;
390 }
391
392 edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
393 rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
394
395 CH_WARN(adap,
396 "edc%d err addr 0x%x: 0x%x.\n",
397 idx, edc_ecc_err_addr_reg,
398 t4_read_reg(adap, edc_ecc_err_addr_reg));
399 CH_WARN(adap,
400 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
401 rdata_reg,
402 (unsigned long long)t4_read_reg64(adap, rdata_reg),
403 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
404 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
405 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
406 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
407 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
408 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
409 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
410 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
411
412 return 0;
413 }
414
415 /**
416 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
417 * @adap: the adapter
418 * @win: PCI-E Memory Window to use
419 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
420 * @addr: address within indicated memory type
421 * @len: amount of memory to transfer
422 * @hbuf: host memory buffer
423 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
424 *
425 * Reads/writes an [almost] arbitrary memory region in the firmware: the
426 * firmware memory address and host buffer must be aligned on 32-bit
427 * boudaries; the length may be arbitrary. The memory is transferred as
428 * a raw byte sequence from/to the firmware's memory. If this memory
429 * contains data structures which contain multi-byte integers, it's the
430 * caller's responsibility to perform appropriate byte order conversions.
431 */
432 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
433 u32 len, void *hbuf, int dir)
434 {
435 u32 pos, offset, resid, memoffset;
436 u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
437 u32 *buf;
438
439 /* Argument sanity checks ...
440 */
441 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
442 return -EINVAL;
443 buf = (u32 *)hbuf;
444
445 /* It's convenient to be able to handle lengths which aren't a
446 * multiple of 32-bits because we often end up transferring files to
447 * the firmware. So we'll handle that by normalizing the length here
448 * and then handling any residual transfer at the end.
449 */
450 resid = len & 0x3;
451 len -= resid;
452
453 /* Offset into the region of memory which is being accessed
454 * MEM_EDC0 = 0
455 * MEM_EDC1 = 1
456 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
457 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
458 */
459 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
460 if (mtype != MEM_MC1)
461 memoffset = (mtype * (edc_size * 1024 * 1024));
462 else {
463 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
464 MA_EXT_MEMORY0_BAR_A));
465 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
466 }
467
468 /* Determine the PCIE_MEM_ACCESS_OFFSET */
469 addr = addr + memoffset;
470
471 /* Each PCI-E Memory Window is programmed with a window size -- or
472 * "aperture" -- which controls the granularity of its mapping onto
473 * adapter memory. We need to grab that aperture in order to know
474 * how to use the specified window. The window is also programmed
475 * with the base address of the Memory Window in BAR0's address
476 * space. For T4 this is an absolute PCI-E Bus Address. For T5
477 * the address is relative to BAR0.
478 */
479 mem_reg = t4_read_reg(adap,
480 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
481 win));
482 mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
483 mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
484 if (is_t4(adap->params.chip))
485 mem_base -= adap->t4_bar0;
486 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
487
488 /* Calculate our initial PCI-E Memory Window Position and Offset into
489 * that Window.
490 */
491 pos = addr & ~(mem_aperture-1);
492 offset = addr - pos;
493
494 /* Set up initial PCI-E Memory Window to cover the start of our
495 * transfer. (Read it back to ensure that changes propagate before we
496 * attempt to use the new value.)
497 */
498 t4_write_reg(adap,
499 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
500 pos | win_pf);
501 t4_read_reg(adap,
502 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
503
504 /* Transfer data to/from the adapter as long as there's an integral
505 * number of 32-bit transfers to complete.
506 *
507 * A note on Endianness issues:
508 *
509 * The "register" reads and writes below from/to the PCI-E Memory
510 * Window invoke the standard adapter Big-Endian to PCI-E Link
511 * Little-Endian "swizzel." As a result, if we have the following
512 * data in adapter memory:
513 *
514 * Memory: ... | b0 | b1 | b2 | b3 | ...
515 * Address: i+0 i+1 i+2 i+3
516 *
517 * Then a read of the adapter memory via the PCI-E Memory Window
518 * will yield:
519 *
520 * x = readl(i)
521 * 31 0
522 * [ b3 | b2 | b1 | b0 ]
523 *
524 * If this value is stored into local memory on a Little-Endian system
525 * it will show up correctly in local memory as:
526 *
527 * ( ..., b0, b1, b2, b3, ... )
528 *
529 * But on a Big-Endian system, the store will show up in memory
530 * incorrectly swizzled as:
531 *
532 * ( ..., b3, b2, b1, b0, ... )
533 *
534 * So we need to account for this in the reads and writes to the
535 * PCI-E Memory Window below by undoing the register read/write
536 * swizzels.
537 */
538 while (len > 0) {
539 if (dir == T4_MEMORY_READ)
540 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
541 mem_base + offset));
542 else
543 t4_write_reg(adap, mem_base + offset,
544 (__force u32)cpu_to_le32(*buf++));
545 offset += sizeof(__be32);
546 len -= sizeof(__be32);
547
548 /* If we've reached the end of our current window aperture,
549 * move the PCI-E Memory Window on to the next. Note that
550 * doing this here after "len" may be 0 allows us to set up
551 * the PCI-E Memory Window for a possible final residual
552 * transfer below ...
553 */
554 if (offset == mem_aperture) {
555 pos += mem_aperture;
556 offset = 0;
557 t4_write_reg(adap,
558 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
559 win), pos | win_pf);
560 t4_read_reg(adap,
561 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
562 win));
563 }
564 }
565
566 /* If the original transfer had a length which wasn't a multiple of
567 * 32-bits, now's where we need to finish off the transfer of the
568 * residual amount. The PCI-E Memory Window has already been moved
569 * above (if necessary) to cover this final transfer.
570 */
571 if (resid) {
572 union {
573 u32 word;
574 char byte[4];
575 } last;
576 unsigned char *bp;
577 int i;
578
579 if (dir == T4_MEMORY_READ) {
580 last.word = le32_to_cpu(
581 (__force __le32)t4_read_reg(adap,
582 mem_base + offset));
583 for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
584 bp[i] = last.byte[i];
585 } else {
586 last.word = *buf;
587 for (i = resid; i < 4; i++)
588 last.byte[i] = 0;
589 t4_write_reg(adap, mem_base + offset,
590 (__force u32)cpu_to_le32(last.word));
591 }
592 }
593
594 return 0;
595 }
596
597 /* Return the specified PCI-E Configuration Space register from our Physical
598 * Function. We try first via a Firmware LDST Command since we prefer to let
599 * the firmware own all of these registers, but if that fails we go for it
600 * directly ourselves.
601 */
602 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
603 {
604 u32 val, ldst_addrspace;
605
606 /* If fw_attach != 0, construct and send the Firmware LDST Command to
607 * retrieve the specified PCI-E Configuration Space register.
608 */
609 struct fw_ldst_cmd ldst_cmd;
610 int ret;
611
612 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
613 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
614 ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
615 FW_CMD_REQUEST_F |
616 FW_CMD_READ_F |
617 ldst_addrspace);
618 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
619 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
620 ldst_cmd.u.pcie.ctrl_to_fn =
621 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
622 ldst_cmd.u.pcie.r = reg;
623
624 /* If the LDST Command succeeds, return the result, otherwise
625 * fall through to reading it directly ourselves ...
626 */
627 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
628 &ldst_cmd);
629 if (ret == 0)
630 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
631 else
632 /* Read the desired Configuration Space register via the PCI-E
633 * Backdoor mechanism.
634 */
635 t4_hw_pci_read_cfg4(adap, reg, &val);
636 return val;
637 }
638
639 /* Get the window based on base passed to it.
640 * Window aperture is currently unhandled, but there is no use case for it
641 * right now
642 */
643 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
644 u32 memwin_base)
645 {
646 u32 ret;
647
648 if (is_t4(adap->params.chip)) {
649 u32 bar0;
650
651 /* Truncation intentional: we only read the bottom 32-bits of
652 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
653 * mechanism to read BAR0 instead of using
654 * pci_resource_start() because we could be operating from
655 * within a Virtual Machine which is trapping our accesses to
656 * our Configuration Space and we need to set up the PCI-E
657 * Memory Window decoders with the actual addresses which will
658 * be coming across the PCI-E link.
659 */
660 bar0 = t4_read_pcie_cfg4(adap, pci_base);
661 bar0 &= pci_mask;
662 adap->t4_bar0 = bar0;
663
664 ret = bar0 + memwin_base;
665 } else {
666 /* For T5, only relative offset inside the PCIe BAR is passed */
667 ret = memwin_base;
668 }
669 return ret;
670 }
671
672 /* Get the default utility window (win0) used by everyone */
673 u32 t4_get_util_window(struct adapter *adap)
674 {
675 return t4_get_window(adap, PCI_BASE_ADDRESS_0,
676 PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
677 }
678
679 /* Set up memory window for accessing adapter memory ranges. (Read
680 * back MA register to ensure that changes propagate before we attempt
681 * to use the new values.)
682 */
683 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
684 {
685 t4_write_reg(adap,
686 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
687 memwin_base | BIR_V(0) |
688 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
689 t4_read_reg(adap,
690 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
691 }
692
693 /**
694 * t4_get_regs_len - return the size of the chips register set
695 * @adapter: the adapter
696 *
697 * Returns the size of the chip's BAR0 register space.
698 */
699 unsigned int t4_get_regs_len(struct adapter *adapter)
700 {
701 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
702
703 switch (chip_version) {
704 case CHELSIO_T4:
705 return T4_REGMAP_SIZE;
706
707 case CHELSIO_T5:
708 case CHELSIO_T6:
709 return T5_REGMAP_SIZE;
710 }
711
712 dev_err(adapter->pdev_dev,
713 "Unsupported chip version %d\n", chip_version);
714 return 0;
715 }
716
717 /**
718 * t4_get_regs - read chip registers into provided buffer
719 * @adap: the adapter
720 * @buf: register buffer
721 * @buf_size: size (in bytes) of register buffer
722 *
723 * If the provided register buffer isn't large enough for the chip's
724 * full register range, the register dump will be truncated to the
725 * register buffer's size.
726 */
727 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
728 {
729 static const unsigned int t4_reg_ranges[] = {
730 0x1008, 0x1108,
731 0x1180, 0x1184,
732 0x1190, 0x1194,
733 0x11a0, 0x11a4,
734 0x11b0, 0x11b4,
735 0x11fc, 0x123c,
736 0x1300, 0x173c,
737 0x1800, 0x18fc,
738 0x3000, 0x30d8,
739 0x30e0, 0x30e4,
740 0x30ec, 0x5910,
741 0x5920, 0x5924,
742 0x5960, 0x5960,
743 0x5968, 0x5968,
744 0x5970, 0x5970,
745 0x5978, 0x5978,
746 0x5980, 0x5980,
747 0x5988, 0x5988,
748 0x5990, 0x5990,
749 0x5998, 0x5998,
750 0x59a0, 0x59d4,
751 0x5a00, 0x5ae0,
752 0x5ae8, 0x5ae8,
753 0x5af0, 0x5af0,
754 0x5af8, 0x5af8,
755 0x6000, 0x6098,
756 0x6100, 0x6150,
757 0x6200, 0x6208,
758 0x6240, 0x6248,
759 0x6280, 0x62b0,
760 0x62c0, 0x6338,
761 0x6370, 0x638c,
762 0x6400, 0x643c,
763 0x6500, 0x6524,
764 0x6a00, 0x6a04,
765 0x6a14, 0x6a38,
766 0x6a60, 0x6a70,
767 0x6a78, 0x6a78,
768 0x6b00, 0x6b0c,
769 0x6b1c, 0x6b84,
770 0x6bf0, 0x6bf8,
771 0x6c00, 0x6c0c,
772 0x6c1c, 0x6c84,
773 0x6cf0, 0x6cf8,
774 0x6d00, 0x6d0c,
775 0x6d1c, 0x6d84,
776 0x6df0, 0x6df8,
777 0x6e00, 0x6e0c,
778 0x6e1c, 0x6e84,
779 0x6ef0, 0x6ef8,
780 0x6f00, 0x6f0c,
781 0x6f1c, 0x6f84,
782 0x6ff0, 0x6ff8,
783 0x7000, 0x700c,
784 0x701c, 0x7084,
785 0x70f0, 0x70f8,
786 0x7100, 0x710c,
787 0x711c, 0x7184,
788 0x71f0, 0x71f8,
789 0x7200, 0x720c,
790 0x721c, 0x7284,
791 0x72f0, 0x72f8,
792 0x7300, 0x730c,
793 0x731c, 0x7384,
794 0x73f0, 0x73f8,
795 0x7400, 0x7450,
796 0x7500, 0x7530,
797 0x7600, 0x760c,
798 0x7614, 0x761c,
799 0x7680, 0x76cc,
800 0x7700, 0x7798,
801 0x77c0, 0x77fc,
802 0x7900, 0x79fc,
803 0x7b00, 0x7b58,
804 0x7b60, 0x7b84,
805 0x7b8c, 0x7c38,
806 0x7d00, 0x7d38,
807 0x7d40, 0x7d80,
808 0x7d8c, 0x7ddc,
809 0x7de4, 0x7e04,
810 0x7e10, 0x7e1c,
811 0x7e24, 0x7e38,
812 0x7e40, 0x7e44,
813 0x7e4c, 0x7e78,
814 0x7e80, 0x7ea4,
815 0x7eac, 0x7edc,
816 0x7ee8, 0x7efc,
817 0x8dc0, 0x8e04,
818 0x8e10, 0x8e1c,
819 0x8e30, 0x8e78,
820 0x8ea0, 0x8eb8,
821 0x8ec0, 0x8f6c,
822 0x8fc0, 0x9008,
823 0x9010, 0x9058,
824 0x9060, 0x9060,
825 0x9068, 0x9074,
826 0x90fc, 0x90fc,
827 0x9400, 0x9408,
828 0x9410, 0x9458,
829 0x9600, 0x9600,
830 0x9608, 0x9638,
831 0x9640, 0x96bc,
832 0x9800, 0x9808,
833 0x9820, 0x983c,
834 0x9850, 0x9864,
835 0x9c00, 0x9c6c,
836 0x9c80, 0x9cec,
837 0x9d00, 0x9d6c,
838 0x9d80, 0x9dec,
839 0x9e00, 0x9e6c,
840 0x9e80, 0x9eec,
841 0x9f00, 0x9f6c,
842 0x9f80, 0x9fec,
843 0xd004, 0xd004,
844 0xd010, 0xd03c,
845 0xdfc0, 0xdfe0,
846 0xe000, 0xea7c,
847 0xf000, 0x11190,
848 0x19040, 0x1906c,
849 0x19078, 0x19080,
850 0x1908c, 0x190e4,
851 0x190f0, 0x190f8,
852 0x19100, 0x19110,
853 0x19120, 0x19124,
854 0x19150, 0x19194,
855 0x1919c, 0x191b0,
856 0x191d0, 0x191e8,
857 0x19238, 0x1924c,
858 0x193f8, 0x1943c,
859 0x1944c, 0x19474,
860 0x19490, 0x194e0,
861 0x194f0, 0x194f8,
862 0x19800, 0x19c08,
863 0x19c10, 0x19c90,
864 0x19ca0, 0x19ce4,
865 0x19cf0, 0x19d40,
866 0x19d50, 0x19d94,
867 0x19da0, 0x19de8,
868 0x19df0, 0x19e40,
869 0x19e50, 0x19e90,
870 0x19ea0, 0x19f4c,
871 0x1a000, 0x1a004,
872 0x1a010, 0x1a06c,
873 0x1a0b0, 0x1a0e4,
874 0x1a0ec, 0x1a0f4,
875 0x1a100, 0x1a108,
876 0x1a114, 0x1a120,
877 0x1a128, 0x1a130,
878 0x1a138, 0x1a138,
879 0x1a190, 0x1a1c4,
880 0x1a1fc, 0x1a1fc,
881 0x1e040, 0x1e04c,
882 0x1e284, 0x1e28c,
883 0x1e2c0, 0x1e2c0,
884 0x1e2e0, 0x1e2e0,
885 0x1e300, 0x1e384,
886 0x1e3c0, 0x1e3c8,
887 0x1e440, 0x1e44c,
888 0x1e684, 0x1e68c,
889 0x1e6c0, 0x1e6c0,
890 0x1e6e0, 0x1e6e0,
891 0x1e700, 0x1e784,
892 0x1e7c0, 0x1e7c8,
893 0x1e840, 0x1e84c,
894 0x1ea84, 0x1ea8c,
895 0x1eac0, 0x1eac0,
896 0x1eae0, 0x1eae0,
897 0x1eb00, 0x1eb84,
898 0x1ebc0, 0x1ebc8,
899 0x1ec40, 0x1ec4c,
900 0x1ee84, 0x1ee8c,
901 0x1eec0, 0x1eec0,
902 0x1eee0, 0x1eee0,
903 0x1ef00, 0x1ef84,
904 0x1efc0, 0x1efc8,
905 0x1f040, 0x1f04c,
906 0x1f284, 0x1f28c,
907 0x1f2c0, 0x1f2c0,
908 0x1f2e0, 0x1f2e0,
909 0x1f300, 0x1f384,
910 0x1f3c0, 0x1f3c8,
911 0x1f440, 0x1f44c,
912 0x1f684, 0x1f68c,
913 0x1f6c0, 0x1f6c0,
914 0x1f6e0, 0x1f6e0,
915 0x1f700, 0x1f784,
916 0x1f7c0, 0x1f7c8,
917 0x1f840, 0x1f84c,
918 0x1fa84, 0x1fa8c,
919 0x1fac0, 0x1fac0,
920 0x1fae0, 0x1fae0,
921 0x1fb00, 0x1fb84,
922 0x1fbc0, 0x1fbc8,
923 0x1fc40, 0x1fc4c,
924 0x1fe84, 0x1fe8c,
925 0x1fec0, 0x1fec0,
926 0x1fee0, 0x1fee0,
927 0x1ff00, 0x1ff84,
928 0x1ffc0, 0x1ffc8,
929 0x20000, 0x2002c,
930 0x20100, 0x2013c,
931 0x20190, 0x201a0,
932 0x201a8, 0x201b8,
933 0x201c4, 0x201c8,
934 0x20200, 0x20318,
935 0x20400, 0x204b4,
936 0x204c0, 0x20528,
937 0x20540, 0x20614,
938 0x21000, 0x21040,
939 0x2104c, 0x21060,
940 0x210c0, 0x210ec,
941 0x21200, 0x21268,
942 0x21270, 0x21284,
943 0x212fc, 0x21388,
944 0x21400, 0x21404,
945 0x21500, 0x21500,
946 0x21510, 0x21518,
947 0x2152c, 0x21530,
948 0x2153c, 0x2153c,
949 0x21550, 0x21554,
950 0x21600, 0x21600,
951 0x21608, 0x2161c,
952 0x21624, 0x21628,
953 0x21630, 0x21634,
954 0x2163c, 0x2163c,
955 0x21700, 0x2171c,
956 0x21780, 0x2178c,
957 0x21800, 0x21818,
958 0x21820, 0x21828,
959 0x21830, 0x21848,
960 0x21850, 0x21854,
961 0x21860, 0x21868,
962 0x21870, 0x21870,
963 0x21878, 0x21898,
964 0x218a0, 0x218a8,
965 0x218b0, 0x218c8,
966 0x218d0, 0x218d4,
967 0x218e0, 0x218e8,
968 0x218f0, 0x218f0,
969 0x218f8, 0x21a18,
970 0x21a20, 0x21a28,
971 0x21a30, 0x21a48,
972 0x21a50, 0x21a54,
973 0x21a60, 0x21a68,
974 0x21a70, 0x21a70,
975 0x21a78, 0x21a98,
976 0x21aa0, 0x21aa8,
977 0x21ab0, 0x21ac8,
978 0x21ad0, 0x21ad4,
979 0x21ae0, 0x21ae8,
980 0x21af0, 0x21af0,
981 0x21af8, 0x21c18,
982 0x21c20, 0x21c20,
983 0x21c28, 0x21c30,
984 0x21c38, 0x21c38,
985 0x21c80, 0x21c98,
986 0x21ca0, 0x21ca8,
987 0x21cb0, 0x21cc8,
988 0x21cd0, 0x21cd4,
989 0x21ce0, 0x21ce8,
990 0x21cf0, 0x21cf0,
991 0x21cf8, 0x21d7c,
992 0x21e00, 0x21e04,
993 0x22000, 0x2202c,
994 0x22100, 0x2213c,
995 0x22190, 0x221a0,
996 0x221a8, 0x221b8,
997 0x221c4, 0x221c8,
998 0x22200, 0x22318,
999 0x22400, 0x224b4,
1000 0x224c0, 0x22528,
1001 0x22540, 0x22614,
1002 0x23000, 0x23040,
1003 0x2304c, 0x23060,
1004 0x230c0, 0x230ec,
1005 0x23200, 0x23268,
1006 0x23270, 0x23284,
1007 0x232fc, 0x23388,
1008 0x23400, 0x23404,
1009 0x23500, 0x23500,
1010 0x23510, 0x23518,
1011 0x2352c, 0x23530,
1012 0x2353c, 0x2353c,
1013 0x23550, 0x23554,
1014 0x23600, 0x23600,
1015 0x23608, 0x2361c,
1016 0x23624, 0x23628,
1017 0x23630, 0x23634,
1018 0x2363c, 0x2363c,
1019 0x23700, 0x2371c,
1020 0x23780, 0x2378c,
1021 0x23800, 0x23818,
1022 0x23820, 0x23828,
1023 0x23830, 0x23848,
1024 0x23850, 0x23854,
1025 0x23860, 0x23868,
1026 0x23870, 0x23870,
1027 0x23878, 0x23898,
1028 0x238a0, 0x238a8,
1029 0x238b0, 0x238c8,
1030 0x238d0, 0x238d4,
1031 0x238e0, 0x238e8,
1032 0x238f0, 0x238f0,
1033 0x238f8, 0x23a18,
1034 0x23a20, 0x23a28,
1035 0x23a30, 0x23a48,
1036 0x23a50, 0x23a54,
1037 0x23a60, 0x23a68,
1038 0x23a70, 0x23a70,
1039 0x23a78, 0x23a98,
1040 0x23aa0, 0x23aa8,
1041 0x23ab0, 0x23ac8,
1042 0x23ad0, 0x23ad4,
1043 0x23ae0, 0x23ae8,
1044 0x23af0, 0x23af0,
1045 0x23af8, 0x23c18,
1046 0x23c20, 0x23c20,
1047 0x23c28, 0x23c30,
1048 0x23c38, 0x23c38,
1049 0x23c80, 0x23c98,
1050 0x23ca0, 0x23ca8,
1051 0x23cb0, 0x23cc8,
1052 0x23cd0, 0x23cd4,
1053 0x23ce0, 0x23ce8,
1054 0x23cf0, 0x23cf0,
1055 0x23cf8, 0x23d7c,
1056 0x23e00, 0x23e04,
1057 0x24000, 0x2402c,
1058 0x24100, 0x2413c,
1059 0x24190, 0x241a0,
1060 0x241a8, 0x241b8,
1061 0x241c4, 0x241c8,
1062 0x24200, 0x24318,
1063 0x24400, 0x244b4,
1064 0x244c0, 0x24528,
1065 0x24540, 0x24614,
1066 0x25000, 0x25040,
1067 0x2504c, 0x25060,
1068 0x250c0, 0x250ec,
1069 0x25200, 0x25268,
1070 0x25270, 0x25284,
1071 0x252fc, 0x25388,
1072 0x25400, 0x25404,
1073 0x25500, 0x25500,
1074 0x25510, 0x25518,
1075 0x2552c, 0x25530,
1076 0x2553c, 0x2553c,
1077 0x25550, 0x25554,
1078 0x25600, 0x25600,
1079 0x25608, 0x2561c,
1080 0x25624, 0x25628,
1081 0x25630, 0x25634,
1082 0x2563c, 0x2563c,
1083 0x25700, 0x2571c,
1084 0x25780, 0x2578c,
1085 0x25800, 0x25818,
1086 0x25820, 0x25828,
1087 0x25830, 0x25848,
1088 0x25850, 0x25854,
1089 0x25860, 0x25868,
1090 0x25870, 0x25870,
1091 0x25878, 0x25898,
1092 0x258a0, 0x258a8,
1093 0x258b0, 0x258c8,
1094 0x258d0, 0x258d4,
1095 0x258e0, 0x258e8,
1096 0x258f0, 0x258f0,
1097 0x258f8, 0x25a18,
1098 0x25a20, 0x25a28,
1099 0x25a30, 0x25a48,
1100 0x25a50, 0x25a54,
1101 0x25a60, 0x25a68,
1102 0x25a70, 0x25a70,
1103 0x25a78, 0x25a98,
1104 0x25aa0, 0x25aa8,
1105 0x25ab0, 0x25ac8,
1106 0x25ad0, 0x25ad4,
1107 0x25ae0, 0x25ae8,
1108 0x25af0, 0x25af0,
1109 0x25af8, 0x25c18,
1110 0x25c20, 0x25c20,
1111 0x25c28, 0x25c30,
1112 0x25c38, 0x25c38,
1113 0x25c80, 0x25c98,
1114 0x25ca0, 0x25ca8,
1115 0x25cb0, 0x25cc8,
1116 0x25cd0, 0x25cd4,
1117 0x25ce0, 0x25ce8,
1118 0x25cf0, 0x25cf0,
1119 0x25cf8, 0x25d7c,
1120 0x25e00, 0x25e04,
1121 0x26000, 0x2602c,
1122 0x26100, 0x2613c,
1123 0x26190, 0x261a0,
1124 0x261a8, 0x261b8,
1125 0x261c4, 0x261c8,
1126 0x26200, 0x26318,
1127 0x26400, 0x264b4,
1128 0x264c0, 0x26528,
1129 0x26540, 0x26614,
1130 0x27000, 0x27040,
1131 0x2704c, 0x27060,
1132 0x270c0, 0x270ec,
1133 0x27200, 0x27268,
1134 0x27270, 0x27284,
1135 0x272fc, 0x27388,
1136 0x27400, 0x27404,
1137 0x27500, 0x27500,
1138 0x27510, 0x27518,
1139 0x2752c, 0x27530,
1140 0x2753c, 0x2753c,
1141 0x27550, 0x27554,
1142 0x27600, 0x27600,
1143 0x27608, 0x2761c,
1144 0x27624, 0x27628,
1145 0x27630, 0x27634,
1146 0x2763c, 0x2763c,
1147 0x27700, 0x2771c,
1148 0x27780, 0x2778c,
1149 0x27800, 0x27818,
1150 0x27820, 0x27828,
1151 0x27830, 0x27848,
1152 0x27850, 0x27854,
1153 0x27860, 0x27868,
1154 0x27870, 0x27870,
1155 0x27878, 0x27898,
1156 0x278a0, 0x278a8,
1157 0x278b0, 0x278c8,
1158 0x278d0, 0x278d4,
1159 0x278e0, 0x278e8,
1160 0x278f0, 0x278f0,
1161 0x278f8, 0x27a18,
1162 0x27a20, 0x27a28,
1163 0x27a30, 0x27a48,
1164 0x27a50, 0x27a54,
1165 0x27a60, 0x27a68,
1166 0x27a70, 0x27a70,
1167 0x27a78, 0x27a98,
1168 0x27aa0, 0x27aa8,
1169 0x27ab0, 0x27ac8,
1170 0x27ad0, 0x27ad4,
1171 0x27ae0, 0x27ae8,
1172 0x27af0, 0x27af0,
1173 0x27af8, 0x27c18,
1174 0x27c20, 0x27c20,
1175 0x27c28, 0x27c30,
1176 0x27c38, 0x27c38,
1177 0x27c80, 0x27c98,
1178 0x27ca0, 0x27ca8,
1179 0x27cb0, 0x27cc8,
1180 0x27cd0, 0x27cd4,
1181 0x27ce0, 0x27ce8,
1182 0x27cf0, 0x27cf0,
1183 0x27cf8, 0x27d7c,
1184 0x27e00, 0x27e04,
1185 };
1186
1187 static const unsigned int t5_reg_ranges[] = {
1188 0x1008, 0x10c0,
1189 0x10cc, 0x10f8,
1190 0x1100, 0x1100,
1191 0x110c, 0x1148,
1192 0x1180, 0x1184,
1193 0x1190, 0x1194,
1194 0x11a0, 0x11a4,
1195 0x11b0, 0x11b4,
1196 0x11fc, 0x123c,
1197 0x1280, 0x173c,
1198 0x1800, 0x18fc,
1199 0x3000, 0x3028,
1200 0x3060, 0x30b0,
1201 0x30b8, 0x30d8,
1202 0x30e0, 0x30fc,
1203 0x3140, 0x357c,
1204 0x35a8, 0x35cc,
1205 0x35ec, 0x35ec,
1206 0x3600, 0x5624,
1207 0x56cc, 0x56ec,
1208 0x56f4, 0x5720,
1209 0x5728, 0x575c,
1210 0x580c, 0x5814,
1211 0x5890, 0x589c,
1212 0x58a4, 0x58ac,
1213 0x58b8, 0x58bc,
1214 0x5940, 0x59c8,
1215 0x59d0, 0x59dc,
1216 0x59fc, 0x5a18,
1217 0x5a60, 0x5a70,
1218 0x5a80, 0x5a9c,
1219 0x5b94, 0x5bfc,
1220 0x6000, 0x6020,
1221 0x6028, 0x6040,
1222 0x6058, 0x609c,
1223 0x60a8, 0x614c,
1224 0x7700, 0x7798,
1225 0x77c0, 0x78fc,
1226 0x7b00, 0x7b58,
1227 0x7b60, 0x7b84,
1228 0x7b8c, 0x7c54,
1229 0x7d00, 0x7d38,
1230 0x7d40, 0x7d80,
1231 0x7d8c, 0x7ddc,
1232 0x7de4, 0x7e04,
1233 0x7e10, 0x7e1c,
1234 0x7e24, 0x7e38,
1235 0x7e40, 0x7e44,
1236 0x7e4c, 0x7e78,
1237 0x7e80, 0x7edc,
1238 0x7ee8, 0x7efc,
1239 0x8dc0, 0x8de0,
1240 0x8df8, 0x8e04,
1241 0x8e10, 0x8e84,
1242 0x8ea0, 0x8f84,
1243 0x8fc0, 0x9058,
1244 0x9060, 0x9060,
1245 0x9068, 0x90f8,
1246 0x9400, 0x9408,
1247 0x9410, 0x9470,
1248 0x9600, 0x9600,
1249 0x9608, 0x9638,
1250 0x9640, 0x96f4,
1251 0x9800, 0x9808,
1252 0x9820, 0x983c,
1253 0x9850, 0x9864,
1254 0x9c00, 0x9c6c,
1255 0x9c80, 0x9cec,
1256 0x9d00, 0x9d6c,
1257 0x9d80, 0x9dec,
1258 0x9e00, 0x9e6c,
1259 0x9e80, 0x9eec,
1260 0x9f00, 0x9f6c,
1261 0x9f80, 0xa020,
1262 0xd004, 0xd004,
1263 0xd010, 0xd03c,
1264 0xdfc0, 0xdfe0,
1265 0xe000, 0x1106c,
1266 0x11074, 0x11088,
1267 0x1109c, 0x1117c,
1268 0x11190, 0x11204,
1269 0x19040, 0x1906c,
1270 0x19078, 0x19080,
1271 0x1908c, 0x190e8,
1272 0x190f0, 0x190f8,
1273 0x19100, 0x19110,
1274 0x19120, 0x19124,
1275 0x19150, 0x19194,
1276 0x1919c, 0x191b0,
1277 0x191d0, 0x191e8,
1278 0x19238, 0x19290,
1279 0x193f8, 0x19428,
1280 0x19430, 0x19444,
1281 0x1944c, 0x1946c,
1282 0x19474, 0x19474,
1283 0x19490, 0x194cc,
1284 0x194f0, 0x194f8,
1285 0x19c00, 0x19c08,
1286 0x19c10, 0x19c60,
1287 0x19c94, 0x19ce4,
1288 0x19cf0, 0x19d40,
1289 0x19d50, 0x19d94,
1290 0x19da0, 0x19de8,
1291 0x19df0, 0x19e10,
1292 0x19e50, 0x19e90,
1293 0x19ea0, 0x19f24,
1294 0x19f34, 0x19f34,
1295 0x19f40, 0x19f50,
1296 0x19f90, 0x19fb4,
1297 0x19fc4, 0x19fe4,
1298 0x1a000, 0x1a004,
1299 0x1a010, 0x1a06c,
1300 0x1a0b0, 0x1a0e4,
1301 0x1a0ec, 0x1a0f8,
1302 0x1a100, 0x1a108,
1303 0x1a114, 0x1a120,
1304 0x1a128, 0x1a130,
1305 0x1a138, 0x1a138,
1306 0x1a190, 0x1a1c4,
1307 0x1a1fc, 0x1a1fc,
1308 0x1e008, 0x1e00c,
1309 0x1e040, 0x1e044,
1310 0x1e04c, 0x1e04c,
1311 0x1e284, 0x1e290,
1312 0x1e2c0, 0x1e2c0,
1313 0x1e2e0, 0x1e2e0,
1314 0x1e300, 0x1e384,
1315 0x1e3c0, 0x1e3c8,
1316 0x1e408, 0x1e40c,
1317 0x1e440, 0x1e444,
1318 0x1e44c, 0x1e44c,
1319 0x1e684, 0x1e690,
1320 0x1e6c0, 0x1e6c0,
1321 0x1e6e0, 0x1e6e0,
1322 0x1e700, 0x1e784,
1323 0x1e7c0, 0x1e7c8,
1324 0x1e808, 0x1e80c,
1325 0x1e840, 0x1e844,
1326 0x1e84c, 0x1e84c,
1327 0x1ea84, 0x1ea90,
1328 0x1eac0, 0x1eac0,
1329 0x1eae0, 0x1eae0,
1330 0x1eb00, 0x1eb84,
1331 0x1ebc0, 0x1ebc8,
1332 0x1ec08, 0x1ec0c,
1333 0x1ec40, 0x1ec44,
1334 0x1ec4c, 0x1ec4c,
1335 0x1ee84, 0x1ee90,
1336 0x1eec0, 0x1eec0,
1337 0x1eee0, 0x1eee0,
1338 0x1ef00, 0x1ef84,
1339 0x1efc0, 0x1efc8,
1340 0x1f008, 0x1f00c,
1341 0x1f040, 0x1f044,
1342 0x1f04c, 0x1f04c,
1343 0x1f284, 0x1f290,
1344 0x1f2c0, 0x1f2c0,
1345 0x1f2e0, 0x1f2e0,
1346 0x1f300, 0x1f384,
1347 0x1f3c0, 0x1f3c8,
1348 0x1f408, 0x1f40c,
1349 0x1f440, 0x1f444,
1350 0x1f44c, 0x1f44c,
1351 0x1f684, 0x1f690,
1352 0x1f6c0, 0x1f6c0,
1353 0x1f6e0, 0x1f6e0,
1354 0x1f700, 0x1f784,
1355 0x1f7c0, 0x1f7c8,
1356 0x1f808, 0x1f80c,
1357 0x1f840, 0x1f844,
1358 0x1f84c, 0x1f84c,
1359 0x1fa84, 0x1fa90,
1360 0x1fac0, 0x1fac0,
1361 0x1fae0, 0x1fae0,
1362 0x1fb00, 0x1fb84,
1363 0x1fbc0, 0x1fbc8,
1364 0x1fc08, 0x1fc0c,
1365 0x1fc40, 0x1fc44,
1366 0x1fc4c, 0x1fc4c,
1367 0x1fe84, 0x1fe90,
1368 0x1fec0, 0x1fec0,
1369 0x1fee0, 0x1fee0,
1370 0x1ff00, 0x1ff84,
1371 0x1ffc0, 0x1ffc8,
1372 0x30000, 0x30030,
1373 0x30038, 0x30038,
1374 0x30040, 0x30040,
1375 0x30100, 0x30144,
1376 0x30190, 0x301a0,
1377 0x301a8, 0x301b8,
1378 0x301c4, 0x301c8,
1379 0x301d0, 0x301d0,
1380 0x30200, 0x30318,
1381 0x30400, 0x304b4,
1382 0x304c0, 0x3052c,
1383 0x30540, 0x3061c,
1384 0x30800, 0x30828,
1385 0x30834, 0x30834,
1386 0x308c0, 0x30908,
1387 0x30910, 0x309ac,
1388 0x30a00, 0x30a14,
1389 0x30a1c, 0x30a2c,
1390 0x30a44, 0x30a50,
1391 0x30a74, 0x30a74,
1392 0x30a7c, 0x30afc,
1393 0x30b08, 0x30c24,
1394 0x30d00, 0x30d00,
1395 0x30d08, 0x30d14,
1396 0x30d1c, 0x30d20,
1397 0x30d3c, 0x30d3c,
1398 0x30d48, 0x30d50,
1399 0x31200, 0x3120c,
1400 0x31220, 0x31220,
1401 0x31240, 0x31240,
1402 0x31600, 0x3160c,
1403 0x31a00, 0x31a1c,
1404 0x31e00, 0x31e20,
1405 0x31e38, 0x31e3c,
1406 0x31e80, 0x31e80,
1407 0x31e88, 0x31ea8,
1408 0x31eb0, 0x31eb4,
1409 0x31ec8, 0x31ed4,
1410 0x31fb8, 0x32004,
1411 0x32200, 0x32200,
1412 0x32208, 0x32240,
1413 0x32248, 0x32280,
1414 0x32288, 0x322c0,
1415 0x322c8, 0x322fc,
1416 0x32600, 0x32630,
1417 0x32a00, 0x32abc,
1418 0x32b00, 0x32b10,
1419 0x32b20, 0x32b30,
1420 0x32b40, 0x32b50,
1421 0x32b60, 0x32b70,
1422 0x33000, 0x33028,
1423 0x33030, 0x33048,
1424 0x33060, 0x33068,
1425 0x33070, 0x3309c,
1426 0x330f0, 0x33128,
1427 0x33130, 0x33148,
1428 0x33160, 0x33168,
1429 0x33170, 0x3319c,
1430 0x331f0, 0x33238,
1431 0x33240, 0x33240,
1432 0x33248, 0x33250,
1433 0x3325c, 0x33264,
1434 0x33270, 0x332b8,
1435 0x332c0, 0x332e4,
1436 0x332f8, 0x33338,
1437 0x33340, 0x33340,
1438 0x33348, 0x33350,
1439 0x3335c, 0x33364,
1440 0x33370, 0x333b8,
1441 0x333c0, 0x333e4,
1442 0x333f8, 0x33428,
1443 0x33430, 0x33448,
1444 0x33460, 0x33468,
1445 0x33470, 0x3349c,
1446 0x334f0, 0x33528,
1447 0x33530, 0x33548,
1448 0x33560, 0x33568,
1449 0x33570, 0x3359c,
1450 0x335f0, 0x33638,
1451 0x33640, 0x33640,
1452 0x33648, 0x33650,
1453 0x3365c, 0x33664,
1454 0x33670, 0x336b8,
1455 0x336c0, 0x336e4,
1456 0x336f8, 0x33738,
1457 0x33740, 0x33740,
1458 0x33748, 0x33750,
1459 0x3375c, 0x33764,
1460 0x33770, 0x337b8,
1461 0x337c0, 0x337e4,
1462 0x337f8, 0x337fc,
1463 0x33814, 0x33814,
1464 0x3382c, 0x3382c,
1465 0x33880, 0x3388c,
1466 0x338e8, 0x338ec,
1467 0x33900, 0x33928,
1468 0x33930, 0x33948,
1469 0x33960, 0x33968,
1470 0x33970, 0x3399c,
1471 0x339f0, 0x33a38,
1472 0x33a40, 0x33a40,
1473 0x33a48, 0x33a50,
1474 0x33a5c, 0x33a64,
1475 0x33a70, 0x33ab8,
1476 0x33ac0, 0x33ae4,
1477 0x33af8, 0x33b10,
1478 0x33b28, 0x33b28,
1479 0x33b3c, 0x33b50,
1480 0x33bf0, 0x33c10,
1481 0x33c28, 0x33c28,
1482 0x33c3c, 0x33c50,
1483 0x33cf0, 0x33cfc,
1484 0x34000, 0x34030,
1485 0x34038, 0x34038,
1486 0x34040, 0x34040,
1487 0x34100, 0x34144,
1488 0x34190, 0x341a0,
1489 0x341a8, 0x341b8,
1490 0x341c4, 0x341c8,
1491 0x341d0, 0x341d0,
1492 0x34200, 0x34318,
1493 0x34400, 0x344b4,
1494 0x344c0, 0x3452c,
1495 0x34540, 0x3461c,
1496 0x34800, 0x34828,
1497 0x34834, 0x34834,
1498 0x348c0, 0x34908,
1499 0x34910, 0x349ac,
1500 0x34a00, 0x34a14,
1501 0x34a1c, 0x34a2c,
1502 0x34a44, 0x34a50,
1503 0x34a74, 0x34a74,
1504 0x34a7c, 0x34afc,
1505 0x34b08, 0x34c24,
1506 0x34d00, 0x34d00,
1507 0x34d08, 0x34d14,
1508 0x34d1c, 0x34d20,
1509 0x34d3c, 0x34d3c,
1510 0x34d48, 0x34d50,
1511 0x35200, 0x3520c,
1512 0x35220, 0x35220,
1513 0x35240, 0x35240,
1514 0x35600, 0x3560c,
1515 0x35a00, 0x35a1c,
1516 0x35e00, 0x35e20,
1517 0x35e38, 0x35e3c,
1518 0x35e80, 0x35e80,
1519 0x35e88, 0x35ea8,
1520 0x35eb0, 0x35eb4,
1521 0x35ec8, 0x35ed4,
1522 0x35fb8, 0x36004,
1523 0x36200, 0x36200,
1524 0x36208, 0x36240,
1525 0x36248, 0x36280,
1526 0x36288, 0x362c0,
1527 0x362c8, 0x362fc,
1528 0x36600, 0x36630,
1529 0x36a00, 0x36abc,
1530 0x36b00, 0x36b10,
1531 0x36b20, 0x36b30,
1532 0x36b40, 0x36b50,
1533 0x36b60, 0x36b70,
1534 0x37000, 0x37028,
1535 0x37030, 0x37048,
1536 0x37060, 0x37068,
1537 0x37070, 0x3709c,
1538 0x370f0, 0x37128,
1539 0x37130, 0x37148,
1540 0x37160, 0x37168,
1541 0x37170, 0x3719c,
1542 0x371f0, 0x37238,
1543 0x37240, 0x37240,
1544 0x37248, 0x37250,
1545 0x3725c, 0x37264,
1546 0x37270, 0x372b8,
1547 0x372c0, 0x372e4,
1548 0x372f8, 0x37338,
1549 0x37340, 0x37340,
1550 0x37348, 0x37350,
1551 0x3735c, 0x37364,
1552 0x37370, 0x373b8,
1553 0x373c0, 0x373e4,
1554 0x373f8, 0x37428,
1555 0x37430, 0x37448,
1556 0x37460, 0x37468,
1557 0x37470, 0x3749c,
1558 0x374f0, 0x37528,
1559 0x37530, 0x37548,
1560 0x37560, 0x37568,
1561 0x37570, 0x3759c,
1562 0x375f0, 0x37638,
1563 0x37640, 0x37640,
1564 0x37648, 0x37650,
1565 0x3765c, 0x37664,
1566 0x37670, 0x376b8,
1567 0x376c0, 0x376e4,
1568 0x376f8, 0x37738,
1569 0x37740, 0x37740,
1570 0x37748, 0x37750,
1571 0x3775c, 0x37764,
1572 0x37770, 0x377b8,
1573 0x377c0, 0x377e4,
1574 0x377f8, 0x377fc,
1575 0x37814, 0x37814,
1576 0x3782c, 0x3782c,
1577 0x37880, 0x3788c,
1578 0x378e8, 0x378ec,
1579 0x37900, 0x37928,
1580 0x37930, 0x37948,
1581 0x37960, 0x37968,
1582 0x37970, 0x3799c,
1583 0x379f0, 0x37a38,
1584 0x37a40, 0x37a40,
1585 0x37a48, 0x37a50,
1586 0x37a5c, 0x37a64,
1587 0x37a70, 0x37ab8,
1588 0x37ac0, 0x37ae4,
1589 0x37af8, 0x37b10,
1590 0x37b28, 0x37b28,
1591 0x37b3c, 0x37b50,
1592 0x37bf0, 0x37c10,
1593 0x37c28, 0x37c28,
1594 0x37c3c, 0x37c50,
1595 0x37cf0, 0x37cfc,
1596 0x38000, 0x38030,
1597 0x38038, 0x38038,
1598 0x38040, 0x38040,
1599 0x38100, 0x38144,
1600 0x38190, 0x381a0,
1601 0x381a8, 0x381b8,
1602 0x381c4, 0x381c8,
1603 0x381d0, 0x381d0,
1604 0x38200, 0x38318,
1605 0x38400, 0x384b4,
1606 0x384c0, 0x3852c,
1607 0x38540, 0x3861c,
1608 0x38800, 0x38828,
1609 0x38834, 0x38834,
1610 0x388c0, 0x38908,
1611 0x38910, 0x389ac,
1612 0x38a00, 0x38a14,
1613 0x38a1c, 0x38a2c,
1614 0x38a44, 0x38a50,
1615 0x38a74, 0x38a74,
1616 0x38a7c, 0x38afc,
1617 0x38b08, 0x38c24,
1618 0x38d00, 0x38d00,
1619 0x38d08, 0x38d14,
1620 0x38d1c, 0x38d20,
1621 0x38d3c, 0x38d3c,
1622 0x38d48, 0x38d50,
1623 0x39200, 0x3920c,
1624 0x39220, 0x39220,
1625 0x39240, 0x39240,
1626 0x39600, 0x3960c,
1627 0x39a00, 0x39a1c,
1628 0x39e00, 0x39e20,
1629 0x39e38, 0x39e3c,
1630 0x39e80, 0x39e80,
1631 0x39e88, 0x39ea8,
1632 0x39eb0, 0x39eb4,
1633 0x39ec8, 0x39ed4,
1634 0x39fb8, 0x3a004,
1635 0x3a200, 0x3a200,
1636 0x3a208, 0x3a240,
1637 0x3a248, 0x3a280,
1638 0x3a288, 0x3a2c0,
1639 0x3a2c8, 0x3a2fc,
1640 0x3a600, 0x3a630,
1641 0x3aa00, 0x3aabc,
1642 0x3ab00, 0x3ab10,
1643 0x3ab20, 0x3ab30,
1644 0x3ab40, 0x3ab50,
1645 0x3ab60, 0x3ab70,
1646 0x3b000, 0x3b028,
1647 0x3b030, 0x3b048,
1648 0x3b060, 0x3b068,
1649 0x3b070, 0x3b09c,
1650 0x3b0f0, 0x3b128,
1651 0x3b130, 0x3b148,
1652 0x3b160, 0x3b168,
1653 0x3b170, 0x3b19c,
1654 0x3b1f0, 0x3b238,
1655 0x3b240, 0x3b240,
1656 0x3b248, 0x3b250,
1657 0x3b25c, 0x3b264,
1658 0x3b270, 0x3b2b8,
1659 0x3b2c0, 0x3b2e4,
1660 0x3b2f8, 0x3b338,
1661 0x3b340, 0x3b340,
1662 0x3b348, 0x3b350,
1663 0x3b35c, 0x3b364,
1664 0x3b370, 0x3b3b8,
1665 0x3b3c0, 0x3b3e4,
1666 0x3b3f8, 0x3b428,
1667 0x3b430, 0x3b448,
1668 0x3b460, 0x3b468,
1669 0x3b470, 0x3b49c,
1670 0x3b4f0, 0x3b528,
1671 0x3b530, 0x3b548,
1672 0x3b560, 0x3b568,
1673 0x3b570, 0x3b59c,
1674 0x3b5f0, 0x3b638,
1675 0x3b640, 0x3b640,
1676 0x3b648, 0x3b650,
1677 0x3b65c, 0x3b664,
1678 0x3b670, 0x3b6b8,
1679 0x3b6c0, 0x3b6e4,
1680 0x3b6f8, 0x3b738,
1681 0x3b740, 0x3b740,
1682 0x3b748, 0x3b750,
1683 0x3b75c, 0x3b764,
1684 0x3b770, 0x3b7b8,
1685 0x3b7c0, 0x3b7e4,
1686 0x3b7f8, 0x3b7fc,
1687 0x3b814, 0x3b814,
1688 0x3b82c, 0x3b82c,
1689 0x3b880, 0x3b88c,
1690 0x3b8e8, 0x3b8ec,
1691 0x3b900, 0x3b928,
1692 0x3b930, 0x3b948,
1693 0x3b960, 0x3b968,
1694 0x3b970, 0x3b99c,
1695 0x3b9f0, 0x3ba38,
1696 0x3ba40, 0x3ba40,
1697 0x3ba48, 0x3ba50,
1698 0x3ba5c, 0x3ba64,
1699 0x3ba70, 0x3bab8,
1700 0x3bac0, 0x3bae4,
1701 0x3baf8, 0x3bb10,
1702 0x3bb28, 0x3bb28,
1703 0x3bb3c, 0x3bb50,
1704 0x3bbf0, 0x3bc10,
1705 0x3bc28, 0x3bc28,
1706 0x3bc3c, 0x3bc50,
1707 0x3bcf0, 0x3bcfc,
1708 0x3c000, 0x3c030,
1709 0x3c038, 0x3c038,
1710 0x3c040, 0x3c040,
1711 0x3c100, 0x3c144,
1712 0x3c190, 0x3c1a0,
1713 0x3c1a8, 0x3c1b8,
1714 0x3c1c4, 0x3c1c8,
1715 0x3c1d0, 0x3c1d0,
1716 0x3c200, 0x3c318,
1717 0x3c400, 0x3c4b4,
1718 0x3c4c0, 0x3c52c,
1719 0x3c540, 0x3c61c,
1720 0x3c800, 0x3c828,
1721 0x3c834, 0x3c834,
1722 0x3c8c0, 0x3c908,
1723 0x3c910, 0x3c9ac,
1724 0x3ca00, 0x3ca14,
1725 0x3ca1c, 0x3ca2c,
1726 0x3ca44, 0x3ca50,
1727 0x3ca74, 0x3ca74,
1728 0x3ca7c, 0x3cafc,
1729 0x3cb08, 0x3cc24,
1730 0x3cd00, 0x3cd00,
1731 0x3cd08, 0x3cd14,
1732 0x3cd1c, 0x3cd20,
1733 0x3cd3c, 0x3cd3c,
1734 0x3cd48, 0x3cd50,
1735 0x3d200, 0x3d20c,
1736 0x3d220, 0x3d220,
1737 0x3d240, 0x3d240,
1738 0x3d600, 0x3d60c,
1739 0x3da00, 0x3da1c,
1740 0x3de00, 0x3de20,
1741 0x3de38, 0x3de3c,
1742 0x3de80, 0x3de80,
1743 0x3de88, 0x3dea8,
1744 0x3deb0, 0x3deb4,
1745 0x3dec8, 0x3ded4,
1746 0x3dfb8, 0x3e004,
1747 0x3e200, 0x3e200,
1748 0x3e208, 0x3e240,
1749 0x3e248, 0x3e280,
1750 0x3e288, 0x3e2c0,
1751 0x3e2c8, 0x3e2fc,
1752 0x3e600, 0x3e630,
1753 0x3ea00, 0x3eabc,
1754 0x3eb00, 0x3eb10,
1755 0x3eb20, 0x3eb30,
1756 0x3eb40, 0x3eb50,
1757 0x3eb60, 0x3eb70,
1758 0x3f000, 0x3f028,
1759 0x3f030, 0x3f048,
1760 0x3f060, 0x3f068,
1761 0x3f070, 0x3f09c,
1762 0x3f0f0, 0x3f128,
1763 0x3f130, 0x3f148,
1764 0x3f160, 0x3f168,
1765 0x3f170, 0x3f19c,
1766 0x3f1f0, 0x3f238,
1767 0x3f240, 0x3f240,
1768 0x3f248, 0x3f250,
1769 0x3f25c, 0x3f264,
1770 0x3f270, 0x3f2b8,
1771 0x3f2c0, 0x3f2e4,
1772 0x3f2f8, 0x3f338,
1773 0x3f340, 0x3f340,
1774 0x3f348, 0x3f350,
1775 0x3f35c, 0x3f364,
1776 0x3f370, 0x3f3b8,
1777 0x3f3c0, 0x3f3e4,
1778 0x3f3f8, 0x3f428,
1779 0x3f430, 0x3f448,
1780 0x3f460, 0x3f468,
1781 0x3f470, 0x3f49c,
1782 0x3f4f0, 0x3f528,
1783 0x3f530, 0x3f548,
1784 0x3f560, 0x3f568,
1785 0x3f570, 0x3f59c,
1786 0x3f5f0, 0x3f638,
1787 0x3f640, 0x3f640,
1788 0x3f648, 0x3f650,
1789 0x3f65c, 0x3f664,
1790 0x3f670, 0x3f6b8,
1791 0x3f6c0, 0x3f6e4,
1792 0x3f6f8, 0x3f738,
1793 0x3f740, 0x3f740,
1794 0x3f748, 0x3f750,
1795 0x3f75c, 0x3f764,
1796 0x3f770, 0x3f7b8,
1797 0x3f7c0, 0x3f7e4,
1798 0x3f7f8, 0x3f7fc,
1799 0x3f814, 0x3f814,
1800 0x3f82c, 0x3f82c,
1801 0x3f880, 0x3f88c,
1802 0x3f8e8, 0x3f8ec,
1803 0x3f900, 0x3f928,
1804 0x3f930, 0x3f948,
1805 0x3f960, 0x3f968,
1806 0x3f970, 0x3f99c,
1807 0x3f9f0, 0x3fa38,
1808 0x3fa40, 0x3fa40,
1809 0x3fa48, 0x3fa50,
1810 0x3fa5c, 0x3fa64,
1811 0x3fa70, 0x3fab8,
1812 0x3fac0, 0x3fae4,
1813 0x3faf8, 0x3fb10,
1814 0x3fb28, 0x3fb28,
1815 0x3fb3c, 0x3fb50,
1816 0x3fbf0, 0x3fc10,
1817 0x3fc28, 0x3fc28,
1818 0x3fc3c, 0x3fc50,
1819 0x3fcf0, 0x3fcfc,
1820 0x40000, 0x4000c,
1821 0x40040, 0x40050,
1822 0x40060, 0x40068,
1823 0x4007c, 0x4008c,
1824 0x40094, 0x400b0,
1825 0x400c0, 0x40144,
1826 0x40180, 0x4018c,
1827 0x40200, 0x40254,
1828 0x40260, 0x40264,
1829 0x40270, 0x40288,
1830 0x40290, 0x40298,
1831 0x402ac, 0x402c8,
1832 0x402d0, 0x402e0,
1833 0x402f0, 0x402f0,
1834 0x40300, 0x4033c,
1835 0x403f8, 0x403fc,
1836 0x41304, 0x413c4,
1837 0x41400, 0x4140c,
1838 0x41414, 0x4141c,
1839 0x41480, 0x414d0,
1840 0x44000, 0x44054,
1841 0x4405c, 0x44078,
1842 0x440c0, 0x44174,
1843 0x44180, 0x441ac,
1844 0x441b4, 0x441b8,
1845 0x441c0, 0x44254,
1846 0x4425c, 0x44278,
1847 0x442c0, 0x44374,
1848 0x44380, 0x443ac,
1849 0x443b4, 0x443b8,
1850 0x443c0, 0x44454,
1851 0x4445c, 0x44478,
1852 0x444c0, 0x44574,
1853 0x44580, 0x445ac,
1854 0x445b4, 0x445b8,
1855 0x445c0, 0x44654,
1856 0x4465c, 0x44678,
1857 0x446c0, 0x44774,
1858 0x44780, 0x447ac,
1859 0x447b4, 0x447b8,
1860 0x447c0, 0x44854,
1861 0x4485c, 0x44878,
1862 0x448c0, 0x44974,
1863 0x44980, 0x449ac,
1864 0x449b4, 0x449b8,
1865 0x449c0, 0x449fc,
1866 0x45000, 0x45004,
1867 0x45010, 0x45030,
1868 0x45040, 0x45060,
1869 0x45068, 0x45068,
1870 0x45080, 0x45084,
1871 0x450a0, 0x450b0,
1872 0x45200, 0x45204,
1873 0x45210, 0x45230,
1874 0x45240, 0x45260,
1875 0x45268, 0x45268,
1876 0x45280, 0x45284,
1877 0x452a0, 0x452b0,
1878 0x460c0, 0x460e4,
1879 0x47000, 0x4703c,
1880 0x47044, 0x4708c,
1881 0x47200, 0x47250,
1882 0x47400, 0x47408,
1883 0x47414, 0x47420,
1884 0x47600, 0x47618,
1885 0x47800, 0x47814,
1886 0x48000, 0x4800c,
1887 0x48040, 0x48050,
1888 0x48060, 0x48068,
1889 0x4807c, 0x4808c,
1890 0x48094, 0x480b0,
1891 0x480c0, 0x48144,
1892 0x48180, 0x4818c,
1893 0x48200, 0x48254,
1894 0x48260, 0x48264,
1895 0x48270, 0x48288,
1896 0x48290, 0x48298,
1897 0x482ac, 0x482c8,
1898 0x482d0, 0x482e0,
1899 0x482f0, 0x482f0,
1900 0x48300, 0x4833c,
1901 0x483f8, 0x483fc,
1902 0x49304, 0x493c4,
1903 0x49400, 0x4940c,
1904 0x49414, 0x4941c,
1905 0x49480, 0x494d0,
1906 0x4c000, 0x4c054,
1907 0x4c05c, 0x4c078,
1908 0x4c0c0, 0x4c174,
1909 0x4c180, 0x4c1ac,
1910 0x4c1b4, 0x4c1b8,
1911 0x4c1c0, 0x4c254,
1912 0x4c25c, 0x4c278,
1913 0x4c2c0, 0x4c374,
1914 0x4c380, 0x4c3ac,
1915 0x4c3b4, 0x4c3b8,
1916 0x4c3c0, 0x4c454,
1917 0x4c45c, 0x4c478,
1918 0x4c4c0, 0x4c574,
1919 0x4c580, 0x4c5ac,
1920 0x4c5b4, 0x4c5b8,
1921 0x4c5c0, 0x4c654,
1922 0x4c65c, 0x4c678,
1923 0x4c6c0, 0x4c774,
1924 0x4c780, 0x4c7ac,
1925 0x4c7b4, 0x4c7b8,
1926 0x4c7c0, 0x4c854,
1927 0x4c85c, 0x4c878,
1928 0x4c8c0, 0x4c974,
1929 0x4c980, 0x4c9ac,
1930 0x4c9b4, 0x4c9b8,
1931 0x4c9c0, 0x4c9fc,
1932 0x4d000, 0x4d004,
1933 0x4d010, 0x4d030,
1934 0x4d040, 0x4d060,
1935 0x4d068, 0x4d068,
1936 0x4d080, 0x4d084,
1937 0x4d0a0, 0x4d0b0,
1938 0x4d200, 0x4d204,
1939 0x4d210, 0x4d230,
1940 0x4d240, 0x4d260,
1941 0x4d268, 0x4d268,
1942 0x4d280, 0x4d284,
1943 0x4d2a0, 0x4d2b0,
1944 0x4e0c0, 0x4e0e4,
1945 0x4f000, 0x4f03c,
1946 0x4f044, 0x4f08c,
1947 0x4f200, 0x4f250,
1948 0x4f400, 0x4f408,
1949 0x4f414, 0x4f420,
1950 0x4f600, 0x4f618,
1951 0x4f800, 0x4f814,
1952 0x50000, 0x50084,
1953 0x50090, 0x500cc,
1954 0x50400, 0x50400,
1955 0x50800, 0x50884,
1956 0x50890, 0x508cc,
1957 0x50c00, 0x50c00,
1958 0x51000, 0x5101c,
1959 0x51300, 0x51308,
1960 };
1961
1962 static const unsigned int t6_reg_ranges[] = {
1963 0x1008, 0x101c,
1964 0x1024, 0x10a8,
1965 0x10b4, 0x10f8,
1966 0x1100, 0x1114,
1967 0x111c, 0x112c,
1968 0x1138, 0x113c,
1969 0x1144, 0x114c,
1970 0x1180, 0x1184,
1971 0x1190, 0x1194,
1972 0x11a0, 0x11a4,
1973 0x11b0, 0x11b4,
1974 0x11fc, 0x1258,
1975 0x1280, 0x12d4,
1976 0x12d9, 0x12d9,
1977 0x12de, 0x12de,
1978 0x12e3, 0x12e3,
1979 0x12e8, 0x133c,
1980 0x1800, 0x18fc,
1981 0x3000, 0x302c,
1982 0x3060, 0x30b0,
1983 0x30b8, 0x30d8,
1984 0x30e0, 0x30fc,
1985 0x3140, 0x357c,
1986 0x35a8, 0x35cc,
1987 0x35ec, 0x35ec,
1988 0x3600, 0x5624,
1989 0x56cc, 0x56ec,
1990 0x56f4, 0x5720,
1991 0x5728, 0x575c,
1992 0x580c, 0x5814,
1993 0x5890, 0x589c,
1994 0x58a4, 0x58ac,
1995 0x58b8, 0x58bc,
1996 0x5940, 0x595c,
1997 0x5980, 0x598c,
1998 0x59b0, 0x59c8,
1999 0x59d0, 0x59dc,
2000 0x59fc, 0x5a18,
2001 0x5a60, 0x5a6c,
2002 0x5a80, 0x5a8c,
2003 0x5a94, 0x5a9c,
2004 0x5b94, 0x5bfc,
2005 0x5c10, 0x5e48,
2006 0x5e50, 0x5e94,
2007 0x5ea0, 0x5eb0,
2008 0x5ec0, 0x5ec0,
2009 0x5ec8, 0x5ed0,
2010 0x6000, 0x6020,
2011 0x6028, 0x6040,
2012 0x6058, 0x609c,
2013 0x60a8, 0x619c,
2014 0x7700, 0x7798,
2015 0x77c0, 0x7880,
2016 0x78cc, 0x78fc,
2017 0x7b00, 0x7b58,
2018 0x7b60, 0x7b84,
2019 0x7b8c, 0x7c54,
2020 0x7d00, 0x7d38,
2021 0x7d40, 0x7d84,
2022 0x7d8c, 0x7ddc,
2023 0x7de4, 0x7e04,
2024 0x7e10, 0x7e1c,
2025 0x7e24, 0x7e38,
2026 0x7e40, 0x7e44,
2027 0x7e4c, 0x7e78,
2028 0x7e80, 0x7edc,
2029 0x7ee8, 0x7efc,
2030 0x8dc0, 0x8de4,
2031 0x8df8, 0x8e04,
2032 0x8e10, 0x8e84,
2033 0x8ea0, 0x8f88,
2034 0x8fb8, 0x9058,
2035 0x9060, 0x9060,
2036 0x9068, 0x90f8,
2037 0x9100, 0x9124,
2038 0x9400, 0x9470,
2039 0x9600, 0x9600,
2040 0x9608, 0x9638,
2041 0x9640, 0x9704,
2042 0x9710, 0x971c,
2043 0x9800, 0x9808,
2044 0x9820, 0x983c,
2045 0x9850, 0x9864,
2046 0x9c00, 0x9c6c,
2047 0x9c80, 0x9cec,
2048 0x9d00, 0x9d6c,
2049 0x9d80, 0x9dec,
2050 0x9e00, 0x9e6c,
2051 0x9e80, 0x9eec,
2052 0x9f00, 0x9f6c,
2053 0x9f80, 0xa020,
2054 0xd004, 0xd03c,
2055 0xd100, 0xd118,
2056 0xd200, 0xd214,
2057 0xd220, 0xd234,
2058 0xd240, 0xd254,
2059 0xd260, 0xd274,
2060 0xd280, 0xd294,
2061 0xd2a0, 0xd2b4,
2062 0xd2c0, 0xd2d4,
2063 0xd2e0, 0xd2f4,
2064 0xd300, 0xd31c,
2065 0xdfc0, 0xdfe0,
2066 0xe000, 0xf008,
2067 0x11000, 0x11014,
2068 0x11048, 0x1106c,
2069 0x11074, 0x11088,
2070 0x11098, 0x11120,
2071 0x1112c, 0x1117c,
2072 0x11190, 0x112e0,
2073 0x11300, 0x1130c,
2074 0x12000, 0x1206c,
2075 0x19040, 0x1906c,
2076 0x19078, 0x19080,
2077 0x1908c, 0x190e8,
2078 0x190f0, 0x190f8,
2079 0x19100, 0x19110,
2080 0x19120, 0x19124,
2081 0x19150, 0x19194,
2082 0x1919c, 0x191b0,
2083 0x191d0, 0x191e8,
2084 0x19238, 0x19290,
2085 0x192a4, 0x192b0,
2086 0x192bc, 0x192bc,
2087 0x19348, 0x1934c,
2088 0x193f8, 0x19418,
2089 0x19420, 0x19428,
2090 0x19430, 0x19444,
2091 0x1944c, 0x1946c,
2092 0x19474, 0x19474,
2093 0x19490, 0x194cc,
2094 0x194f0, 0x194f8,
2095 0x19c00, 0x19c48,
2096 0x19c50, 0x19c80,
2097 0x19c94, 0x19c98,
2098 0x19ca0, 0x19cbc,
2099 0x19ce4, 0x19ce4,
2100 0x19cf0, 0x19cf8,
2101 0x19d00, 0x19d28,
2102 0x19d50, 0x19d78,
2103 0x19d94, 0x19d98,
2104 0x19da0, 0x19dc8,
2105 0x19df0, 0x19e10,
2106 0x19e50, 0x19e6c,
2107 0x19ea0, 0x19ebc,
2108 0x19ec4, 0x19ef4,
2109 0x19f04, 0x19f2c,
2110 0x19f34, 0x19f34,
2111 0x19f40, 0x19f50,
2112 0x19f90, 0x19fac,
2113 0x19fc4, 0x19fc8,
2114 0x19fd0, 0x19fe4,
2115 0x1a000, 0x1a004,
2116 0x1a010, 0x1a06c,
2117 0x1a0b0, 0x1a0e4,
2118 0x1a0ec, 0x1a0f8,
2119 0x1a100, 0x1a108,
2120 0x1a114, 0x1a120,
2121 0x1a128, 0x1a130,
2122 0x1a138, 0x1a138,
2123 0x1a190, 0x1a1c4,
2124 0x1a1fc, 0x1a1fc,
2125 0x1e008, 0x1e00c,
2126 0x1e040, 0x1e044,
2127 0x1e04c, 0x1e04c,
2128 0x1e284, 0x1e290,
2129 0x1e2c0, 0x1e2c0,
2130 0x1e2e0, 0x1e2e0,
2131 0x1e300, 0x1e384,
2132 0x1e3c0, 0x1e3c8,
2133 0x1e408, 0x1e40c,
2134 0x1e440, 0x1e444,
2135 0x1e44c, 0x1e44c,
2136 0x1e684, 0x1e690,
2137 0x1e6c0, 0x1e6c0,
2138 0x1e6e0, 0x1e6e0,
2139 0x1e700, 0x1e784,
2140 0x1e7c0, 0x1e7c8,
2141 0x1e808, 0x1e80c,
2142 0x1e840, 0x1e844,
2143 0x1e84c, 0x1e84c,
2144 0x1ea84, 0x1ea90,
2145 0x1eac0, 0x1eac0,
2146 0x1eae0, 0x1eae0,
2147 0x1eb00, 0x1eb84,
2148 0x1ebc0, 0x1ebc8,
2149 0x1ec08, 0x1ec0c,
2150 0x1ec40, 0x1ec44,
2151 0x1ec4c, 0x1ec4c,
2152 0x1ee84, 0x1ee90,
2153 0x1eec0, 0x1eec0,
2154 0x1eee0, 0x1eee0,
2155 0x1ef00, 0x1ef84,
2156 0x1efc0, 0x1efc8,
2157 0x1f008, 0x1f00c,
2158 0x1f040, 0x1f044,
2159 0x1f04c, 0x1f04c,
2160 0x1f284, 0x1f290,
2161 0x1f2c0, 0x1f2c0,
2162 0x1f2e0, 0x1f2e0,
2163 0x1f300, 0x1f384,
2164 0x1f3c0, 0x1f3c8,
2165 0x1f408, 0x1f40c,
2166 0x1f440, 0x1f444,
2167 0x1f44c, 0x1f44c,
2168 0x1f684, 0x1f690,
2169 0x1f6c0, 0x1f6c0,
2170 0x1f6e0, 0x1f6e0,
2171 0x1f700, 0x1f784,
2172 0x1f7c0, 0x1f7c8,
2173 0x1f808, 0x1f80c,
2174 0x1f840, 0x1f844,
2175 0x1f84c, 0x1f84c,
2176 0x1fa84, 0x1fa90,
2177 0x1fac0, 0x1fac0,
2178 0x1fae0, 0x1fae0,
2179 0x1fb00, 0x1fb84,
2180 0x1fbc0, 0x1fbc8,
2181 0x1fc08, 0x1fc0c,
2182 0x1fc40, 0x1fc44,
2183 0x1fc4c, 0x1fc4c,
2184 0x1fe84, 0x1fe90,
2185 0x1fec0, 0x1fec0,
2186 0x1fee0, 0x1fee0,
2187 0x1ff00, 0x1ff84,
2188 0x1ffc0, 0x1ffc8,
2189 0x30000, 0x30030,
2190 0x30038, 0x30038,
2191 0x30040, 0x30040,
2192 0x30048, 0x30048,
2193 0x30050, 0x30050,
2194 0x3005c, 0x30060,
2195 0x30068, 0x30068,
2196 0x30070, 0x30070,
2197 0x30100, 0x30168,
2198 0x30190, 0x301a0,
2199 0x301a8, 0x301b8,
2200 0x301c4, 0x301c8,
2201 0x301d0, 0x301d0,
2202 0x30200, 0x30320,
2203 0x30400, 0x304b4,
2204 0x304c0, 0x3052c,
2205 0x30540, 0x3061c,
2206 0x30800, 0x308a0,
2207 0x308c0, 0x30908,
2208 0x30910, 0x309b8,
2209 0x30a00, 0x30a04,
2210 0x30a0c, 0x30a14,
2211 0x30a1c, 0x30a2c,
2212 0x30a44, 0x30a50,
2213 0x30a74, 0x30a74,
2214 0x30a7c, 0x30afc,
2215 0x30b08, 0x30c24,
2216 0x30d00, 0x30d14,
2217 0x30d1c, 0x30d3c,
2218 0x30d44, 0x30d4c,
2219 0x30d54, 0x30d74,
2220 0x30d7c, 0x30d7c,
2221 0x30de0, 0x30de0,
2222 0x30e00, 0x30ed4,
2223 0x30f00, 0x30fa4,
2224 0x30fc0, 0x30fc4,
2225 0x31000, 0x31004,
2226 0x31080, 0x310fc,
2227 0x31208, 0x31220,
2228 0x3123c, 0x31254,
2229 0x31300, 0x31300,
2230 0x31308, 0x3131c,
2231 0x31338, 0x3133c,
2232 0x31380, 0x31380,
2233 0x31388, 0x313a8,
2234 0x313b4, 0x313b4,
2235 0x31400, 0x31420,
2236 0x31438, 0x3143c,
2237 0x31480, 0x31480,
2238 0x314a8, 0x314a8,
2239 0x314b0, 0x314b4,
2240 0x314c8, 0x314d4,
2241 0x31a40, 0x31a4c,
2242 0x31af0, 0x31b20,
2243 0x31b38, 0x31b3c,
2244 0x31b80, 0x31b80,
2245 0x31ba8, 0x31ba8,
2246 0x31bb0, 0x31bb4,
2247 0x31bc8, 0x31bd4,
2248 0x32140, 0x3218c,
2249 0x321f0, 0x321f4,
2250 0x32200, 0x32200,
2251 0x32218, 0x32218,
2252 0x32400, 0x32400,
2253 0x32408, 0x3241c,
2254 0x32618, 0x32620,
2255 0x32664, 0x32664,
2256 0x326a8, 0x326a8,
2257 0x326ec, 0x326ec,
2258 0x32a00, 0x32abc,
2259 0x32b00, 0x32b38,
2260 0x32b40, 0x32b58,
2261 0x32b60, 0x32b78,
2262 0x32c00, 0x32c00,
2263 0x32c08, 0x32c3c,
2264 0x32e00, 0x32e2c,
2265 0x32f00, 0x32f2c,
2266 0x33000, 0x3302c,
2267 0x33034, 0x33050,
2268 0x33058, 0x33058,
2269 0x33060, 0x3308c,
2270 0x3309c, 0x330ac,
2271 0x330c0, 0x330c0,
2272 0x330c8, 0x330d0,
2273 0x330d8, 0x330e0,
2274 0x330ec, 0x3312c,
2275 0x33134, 0x33150,
2276 0x33158, 0x33158,
2277 0x33160, 0x3318c,
2278 0x3319c, 0x331ac,
2279 0x331c0, 0x331c0,
2280 0x331c8, 0x331d0,
2281 0x331d8, 0x331e0,
2282 0x331ec, 0x33290,
2283 0x33298, 0x332c4,
2284 0x332e4, 0x33390,
2285 0x33398, 0x333c4,
2286 0x333e4, 0x3342c,
2287 0x33434, 0x33450,
2288 0x33458, 0x33458,
2289 0x33460, 0x3348c,
2290 0x3349c, 0x334ac,
2291 0x334c0, 0x334c0,
2292 0x334c8, 0x334d0,
2293 0x334d8, 0x334e0,
2294 0x334ec, 0x3352c,
2295 0x33534, 0x33550,
2296 0x33558, 0x33558,
2297 0x33560, 0x3358c,
2298 0x3359c, 0x335ac,
2299 0x335c0, 0x335c0,
2300 0x335c8, 0x335d0,
2301 0x335d8, 0x335e0,
2302 0x335ec, 0x33690,
2303 0x33698, 0x336c4,
2304 0x336e4, 0x33790,
2305 0x33798, 0x337c4,
2306 0x337e4, 0x337fc,
2307 0x33814, 0x33814,
2308 0x33854, 0x33868,
2309 0x33880, 0x3388c,
2310 0x338c0, 0x338d0,
2311 0x338e8, 0x338ec,
2312 0x33900, 0x3392c,
2313 0x33934, 0x33950,
2314 0x33958, 0x33958,
2315 0x33960, 0x3398c,
2316 0x3399c, 0x339ac,
2317 0x339c0, 0x339c0,
2318 0x339c8, 0x339d0,
2319 0x339d8, 0x339e0,
2320 0x339ec, 0x33a90,
2321 0x33a98, 0x33ac4,
2322 0x33ae4, 0x33b10,
2323 0x33b24, 0x33b28,
2324 0x33b38, 0x33b50,
2325 0x33bf0, 0x33c10,
2326 0x33c24, 0x33c28,
2327 0x33c38, 0x33c50,
2328 0x33cf0, 0x33cfc,
2329 0x34000, 0x34030,
2330 0x34038, 0x34038,
2331 0x34040, 0x34040,
2332 0x34048, 0x34048,
2333 0x34050, 0x34050,
2334 0x3405c, 0x34060,
2335 0x34068, 0x34068,
2336 0x34070, 0x34070,
2337 0x34100, 0x34168,
2338 0x34190, 0x341a0,
2339 0x341a8, 0x341b8,
2340 0x341c4, 0x341c8,
2341 0x341d0, 0x341d0,
2342 0x34200, 0x34320,
2343 0x34400, 0x344b4,
2344 0x344c0, 0x3452c,
2345 0x34540, 0x3461c,
2346 0x34800, 0x348a0,
2347 0x348c0, 0x34908,
2348 0x34910, 0x349b8,
2349 0x34a00, 0x34a04,
2350 0x34a0c, 0x34a14,
2351 0x34a1c, 0x34a2c,
2352 0x34a44, 0x34a50,
2353 0x34a74, 0x34a74,
2354 0x34a7c, 0x34afc,
2355 0x34b08, 0x34c24,
2356 0x34d00, 0x34d14,
2357 0x34d1c, 0x34d3c,
2358 0x34d44, 0x34d4c,
2359 0x34d54, 0x34d74,
2360 0x34d7c, 0x34d7c,
2361 0x34de0, 0x34de0,
2362 0x34e00, 0x34ed4,
2363 0x34f00, 0x34fa4,
2364 0x34fc0, 0x34fc4,
2365 0x35000, 0x35004,
2366 0x35080, 0x350fc,
2367 0x35208, 0x35220,
2368 0x3523c, 0x35254,
2369 0x35300, 0x35300,
2370 0x35308, 0x3531c,
2371 0x35338, 0x3533c,
2372 0x35380, 0x35380,
2373 0x35388, 0x353a8,
2374 0x353b4, 0x353b4,
2375 0x35400, 0x35420,
2376 0x35438, 0x3543c,
2377 0x35480, 0x35480,
2378 0x354a8, 0x354a8,
2379 0x354b0, 0x354b4,
2380 0x354c8, 0x354d4,
2381 0x35a40, 0x35a4c,
2382 0x35af0, 0x35b20,
2383 0x35b38, 0x35b3c,
2384 0x35b80, 0x35b80,
2385 0x35ba8, 0x35ba8,
2386 0x35bb0, 0x35bb4,
2387 0x35bc8, 0x35bd4,
2388 0x36140, 0x3618c,
2389 0x361f0, 0x361f4,
2390 0x36200, 0x36200,
2391 0x36218, 0x36218,
2392 0x36400, 0x36400,
2393 0x36408, 0x3641c,
2394 0x36618, 0x36620,
2395 0x36664, 0x36664,
2396 0x366a8, 0x366a8,
2397 0x366ec, 0x366ec,
2398 0x36a00, 0x36abc,
2399 0x36b00, 0x36b38,
2400 0x36b40, 0x36b58,
2401 0x36b60, 0x36b78,
2402 0x36c00, 0x36c00,
2403 0x36c08, 0x36c3c,
2404 0x36e00, 0x36e2c,
2405 0x36f00, 0x36f2c,
2406 0x37000, 0x3702c,
2407 0x37034, 0x37050,
2408 0x37058, 0x37058,
2409 0x37060, 0x3708c,
2410 0x3709c, 0x370ac,
2411 0x370c0, 0x370c0,
2412 0x370c8, 0x370d0,
2413 0x370d8, 0x370e0,
2414 0x370ec, 0x3712c,
2415 0x37134, 0x37150,
2416 0x37158, 0x37158,
2417 0x37160, 0x3718c,
2418 0x3719c, 0x371ac,
2419 0x371c0, 0x371c0,
2420 0x371c8, 0x371d0,
2421 0x371d8, 0x371e0,
2422 0x371ec, 0x37290,
2423 0x37298, 0x372c4,
2424 0x372e4, 0x37390,
2425 0x37398, 0x373c4,
2426 0x373e4, 0x3742c,
2427 0x37434, 0x37450,
2428 0x37458, 0x37458,
2429 0x37460, 0x3748c,
2430 0x3749c, 0x374ac,
2431 0x374c0, 0x374c0,
2432 0x374c8, 0x374d0,
2433 0x374d8, 0x374e0,
2434 0x374ec, 0x3752c,
2435 0x37534, 0x37550,
2436 0x37558, 0x37558,
2437 0x37560, 0x3758c,
2438 0x3759c, 0x375ac,
2439 0x375c0, 0x375c0,
2440 0x375c8, 0x375d0,
2441 0x375d8, 0x375e0,
2442 0x375ec, 0x37690,
2443 0x37698, 0x376c4,
2444 0x376e4, 0x37790,
2445 0x37798, 0x377c4,
2446 0x377e4, 0x377fc,
2447 0x37814, 0x37814,
2448 0x37854, 0x37868,
2449 0x37880, 0x3788c,
2450 0x378c0, 0x378d0,
2451 0x378e8, 0x378ec,
2452 0x37900, 0x3792c,
2453 0x37934, 0x37950,
2454 0x37958, 0x37958,
2455 0x37960, 0x3798c,
2456 0x3799c, 0x379ac,
2457 0x379c0, 0x379c0,
2458 0x379c8, 0x379d0,
2459 0x379d8, 0x379e0,
2460 0x379ec, 0x37a90,
2461 0x37a98, 0x37ac4,
2462 0x37ae4, 0x37b10,
2463 0x37b24, 0x37b28,
2464 0x37b38, 0x37b50,
2465 0x37bf0, 0x37c10,
2466 0x37c24, 0x37c28,
2467 0x37c38, 0x37c50,
2468 0x37cf0, 0x37cfc,
2469 0x40040, 0x40040,
2470 0x40080, 0x40084,
2471 0x40100, 0x40100,
2472 0x40140, 0x401bc,
2473 0x40200, 0x40214,
2474 0x40228, 0x40228,
2475 0x40240, 0x40258,
2476 0x40280, 0x40280,
2477 0x40304, 0x40304,
2478 0x40330, 0x4033c,
2479 0x41304, 0x413b8,
2480 0x413c0, 0x413c8,
2481 0x413d0, 0x413dc,
2482 0x413f0, 0x413f0,
2483 0x41400, 0x4140c,
2484 0x41414, 0x4141c,
2485 0x41480, 0x414d0,
2486 0x44000, 0x4407c,
2487 0x440c0, 0x441ac,
2488 0x441b4, 0x4427c,
2489 0x442c0, 0x443ac,
2490 0x443b4, 0x4447c,
2491 0x444c0, 0x445ac,
2492 0x445b4, 0x4467c,
2493 0x446c0, 0x447ac,
2494 0x447b4, 0x4487c,
2495 0x448c0, 0x449ac,
2496 0x449b4, 0x44a7c,
2497 0x44ac0, 0x44bac,
2498 0x44bb4, 0x44c7c,
2499 0x44cc0, 0x44dac,
2500 0x44db4, 0x44e7c,
2501 0x44ec0, 0x44fac,
2502 0x44fb4, 0x4507c,
2503 0x450c0, 0x451ac,
2504 0x451b4, 0x451fc,
2505 0x45800, 0x45804,
2506 0x45810, 0x45830,
2507 0x45840, 0x45860,
2508 0x45868, 0x45868,
2509 0x45880, 0x45884,
2510 0x458a0, 0x458b0,
2511 0x45a00, 0x45a04,
2512 0x45a10, 0x45a30,
2513 0x45a40, 0x45a60,
2514 0x45a68, 0x45a68,
2515 0x45a80, 0x45a84,
2516 0x45aa0, 0x45ab0,
2517 0x460c0, 0x460e4,
2518 0x47000, 0x4703c,
2519 0x47044, 0x4708c,
2520 0x47200, 0x47250,
2521 0x47400, 0x47408,
2522 0x47414, 0x47420,
2523 0x47600, 0x47618,
2524 0x47800, 0x47814,
2525 0x47820, 0x4782c,
2526 0x50000, 0x50084,
2527 0x50090, 0x500cc,
2528 0x50300, 0x50384,
2529 0x50400, 0x50400,
2530 0x50800, 0x50884,
2531 0x50890, 0x508cc,
2532 0x50b00, 0x50b84,
2533 0x50c00, 0x50c00,
2534 0x51000, 0x51020,
2535 0x51028, 0x510b0,
2536 0x51300, 0x51324,
2537 };
2538
2539 u32 *buf_end = (u32 *)((char *)buf + buf_size);
2540 const unsigned int *reg_ranges;
2541 int reg_ranges_size, range;
2542 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2543
2544 /* Select the right set of register ranges to dump depending on the
2545 * adapter chip type.
2546 */
2547 switch (chip_version) {
2548 case CHELSIO_T4:
2549 reg_ranges = t4_reg_ranges;
2550 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2551 break;
2552
2553 case CHELSIO_T5:
2554 reg_ranges = t5_reg_ranges;
2555 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2556 break;
2557
2558 case CHELSIO_T6:
2559 reg_ranges = t6_reg_ranges;
2560 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2561 break;
2562
2563 default:
2564 dev_err(adap->pdev_dev,
2565 "Unsupported chip version %d\n", chip_version);
2566 return;
2567 }
2568
2569 /* Clear the register buffer and insert the appropriate register
2570 * values selected by the above register ranges.
2571 */
2572 memset(buf, 0, buf_size);
2573 for (range = 0; range < reg_ranges_size; range += 2) {
2574 unsigned int reg = reg_ranges[range];
2575 unsigned int last_reg = reg_ranges[range + 1];
2576 u32 *bufp = (u32 *)((char *)buf + reg);
2577
2578 /* Iterate across the register range filling in the register
2579 * buffer but don't write past the end of the register buffer.
2580 */
2581 while (reg <= last_reg && bufp < buf_end) {
2582 *bufp++ = t4_read_reg(adap, reg);
2583 reg += sizeof(u32);
2584 }
2585 }
2586 }
2587
2588 #define EEPROM_STAT_ADDR 0x7bfc
2589 #define VPD_SIZE 0x800
2590 #define VPD_BASE 0x400
2591 #define VPD_BASE_OLD 0
2592 #define VPD_LEN 1024
2593 #define CHELSIO_VPD_UNIQUE_ID 0x82
2594
2595 /**
2596 * t4_seeprom_wp - enable/disable EEPROM write protection
2597 * @adapter: the adapter
2598 * @enable: whether to enable or disable write protection
2599 *
2600 * Enables or disables write protection on the serial EEPROM.
2601 */
2602 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2603 {
2604 unsigned int v = enable ? 0xc : 0;
2605 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2606 return ret < 0 ? ret : 0;
2607 }
2608
2609 /**
2610 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2611 * @adapter: adapter to read
2612 * @p: where to store the parameters
2613 *
2614 * Reads card parameters stored in VPD EEPROM.
2615 */
2616 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2617 {
2618 int i, ret = 0, addr;
2619 int ec, sn, pn, na;
2620 u8 *vpd, csum;
2621 unsigned int vpdr_len, kw_offset, id_len;
2622
2623 vpd = vmalloc(VPD_LEN);
2624 if (!vpd)
2625 return -ENOMEM;
2626
2627 /* We have two VPD data structures stored in the adapter VPD area.
2628 * By default, Linux calculates the size of the VPD area by traversing
2629 * the first VPD area at offset 0x0, so we need to tell the OS what
2630 * our real VPD size is.
2631 */
2632 ret = pci_set_vpd_size(adapter->pdev, VPD_SIZE);
2633 if (ret < 0)
2634 goto out;
2635
2636 /* Card information normally starts at VPD_BASE but early cards had
2637 * it at 0.
2638 */
2639 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2640 if (ret < 0)
2641 goto out;
2642
2643 /* The VPD shall have a unique identifier specified by the PCI SIG.
2644 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2645 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2646 * is expected to automatically put this entry at the
2647 * beginning of the VPD.
2648 */
2649 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2650
2651 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2652 if (ret < 0)
2653 goto out;
2654
2655 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2656 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2657 ret = -EINVAL;
2658 goto out;
2659 }
2660
2661 id_len = pci_vpd_lrdt_size(vpd);
2662 if (id_len > ID_LEN)
2663 id_len = ID_LEN;
2664
2665 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2666 if (i < 0) {
2667 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2668 ret = -EINVAL;
2669 goto out;
2670 }
2671
2672 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2673 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2674 if (vpdr_len + kw_offset > VPD_LEN) {
2675 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2676 ret = -EINVAL;
2677 goto out;
2678 }
2679
2680 #define FIND_VPD_KW(var, name) do { \
2681 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2682 if (var < 0) { \
2683 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2684 ret = -EINVAL; \
2685 goto out; \
2686 } \
2687 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2688 } while (0)
2689
2690 FIND_VPD_KW(i, "RV");
2691 for (csum = 0; i >= 0; i--)
2692 csum += vpd[i];
2693
2694 if (csum) {
2695 dev_err(adapter->pdev_dev,
2696 "corrupted VPD EEPROM, actual csum %u\n", csum);
2697 ret = -EINVAL;
2698 goto out;
2699 }
2700
2701 FIND_VPD_KW(ec, "EC");
2702 FIND_VPD_KW(sn, "SN");
2703 FIND_VPD_KW(pn, "PN");
2704 FIND_VPD_KW(na, "NA");
2705 #undef FIND_VPD_KW
2706
2707 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2708 strim(p->id);
2709 memcpy(p->ec, vpd + ec, EC_LEN);
2710 strim(p->ec);
2711 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2712 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2713 strim(p->sn);
2714 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2715 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2716 strim(p->pn);
2717 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2718 strim((char *)p->na);
2719
2720 out:
2721 vfree(vpd);
2722 return ret;
2723 }
2724
2725 /**
2726 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2727 * @adapter: adapter to read
2728 * @p: where to store the parameters
2729 *
2730 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2731 * Clock. This can only be called after a connection to the firmware
2732 * is established.
2733 */
2734 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2735 {
2736 u32 cclk_param, cclk_val;
2737 int ret;
2738
2739 /* Grab the raw VPD parameters.
2740 */
2741 ret = t4_get_raw_vpd_params(adapter, p);
2742 if (ret)
2743 return ret;
2744
2745 /* Ask firmware for the Core Clock since it knows how to translate the
2746 * Reference Clock ('V2') VPD field into a Core Clock value ...
2747 */
2748 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2749 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2750 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2751 1, &cclk_param, &cclk_val);
2752
2753 if (ret)
2754 return ret;
2755 p->cclk = cclk_val;
2756
2757 return 0;
2758 }
2759
2760 /* serial flash and firmware constants */
2761 enum {
2762 SF_ATTEMPTS = 10, /* max retries for SF operations */
2763
2764 /* flash command opcodes */
2765 SF_PROG_PAGE = 2, /* program page */
2766 SF_WR_DISABLE = 4, /* disable writes */
2767 SF_RD_STATUS = 5, /* read status register */
2768 SF_WR_ENABLE = 6, /* enable writes */
2769 SF_RD_DATA_FAST = 0xb, /* read flash */
2770 SF_RD_ID = 0x9f, /* read ID */
2771 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2772
2773 FW_MAX_SIZE = 16 * SF_SEC_SIZE,
2774 };
2775
2776 /**
2777 * sf1_read - read data from the serial flash
2778 * @adapter: the adapter
2779 * @byte_cnt: number of bytes to read
2780 * @cont: whether another operation will be chained
2781 * @lock: whether to lock SF for PL access only
2782 * @valp: where to store the read data
2783 *
2784 * Reads up to 4 bytes of data from the serial flash. The location of
2785 * the read needs to be specified prior to calling this by issuing the
2786 * appropriate commands to the serial flash.
2787 */
2788 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2789 int lock, u32 *valp)
2790 {
2791 int ret;
2792
2793 if (!byte_cnt || byte_cnt > 4)
2794 return -EINVAL;
2795 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2796 return -EBUSY;
2797 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2798 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2799 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2800 if (!ret)
2801 *valp = t4_read_reg(adapter, SF_DATA_A);
2802 return ret;
2803 }
2804
2805 /**
2806 * sf1_write - write data to the serial flash
2807 * @adapter: the adapter
2808 * @byte_cnt: number of bytes to write
2809 * @cont: whether another operation will be chained
2810 * @lock: whether to lock SF for PL access only
2811 * @val: value to write
2812 *
2813 * Writes up to 4 bytes of data to the serial flash. The location of
2814 * the write needs to be specified prior to calling this by issuing the
2815 * appropriate commands to the serial flash.
2816 */
2817 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2818 int lock, u32 val)
2819 {
2820 if (!byte_cnt || byte_cnt > 4)
2821 return -EINVAL;
2822 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2823 return -EBUSY;
2824 t4_write_reg(adapter, SF_DATA_A, val);
2825 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2826 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2827 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2828 }
2829
2830 /**
2831 * flash_wait_op - wait for a flash operation to complete
2832 * @adapter: the adapter
2833 * @attempts: max number of polls of the status register
2834 * @delay: delay between polls in ms
2835 *
2836 * Wait for a flash operation to complete by polling the status register.
2837 */
2838 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2839 {
2840 int ret;
2841 u32 status;
2842
2843 while (1) {
2844 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2845 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2846 return ret;
2847 if (!(status & 1))
2848 return 0;
2849 if (--attempts == 0)
2850 return -EAGAIN;
2851 if (delay)
2852 msleep(delay);
2853 }
2854 }
2855
2856 /**
2857 * t4_read_flash - read words from serial flash
2858 * @adapter: the adapter
2859 * @addr: the start address for the read
2860 * @nwords: how many 32-bit words to read
2861 * @data: where to store the read data
2862 * @byte_oriented: whether to store data as bytes or as words
2863 *
2864 * Read the specified number of 32-bit words from the serial flash.
2865 * If @byte_oriented is set the read data is stored as a byte array
2866 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2867 * natural endianness.
2868 */
2869 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2870 unsigned int nwords, u32 *data, int byte_oriented)
2871 {
2872 int ret;
2873
2874 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
2875 return -EINVAL;
2876
2877 addr = swab32(addr) | SF_RD_DATA_FAST;
2878
2879 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
2880 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
2881 return ret;
2882
2883 for ( ; nwords; nwords--, data++) {
2884 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2885 if (nwords == 1)
2886 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2887 if (ret)
2888 return ret;
2889 if (byte_oriented)
2890 *data = (__force __u32)(cpu_to_be32(*data));
2891 }
2892 return 0;
2893 }
2894
2895 /**
2896 * t4_write_flash - write up to a page of data to the serial flash
2897 * @adapter: the adapter
2898 * @addr: the start address to write
2899 * @n: length of data to write in bytes
2900 * @data: the data to write
2901 *
2902 * Writes up to a page of data (256 bytes) to the serial flash starting
2903 * at the given address. All the data must be written to the same page.
2904 */
2905 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
2906 unsigned int n, const u8 *data)
2907 {
2908 int ret;
2909 u32 buf[64];
2910 unsigned int i, c, left, val, offset = addr & 0xff;
2911
2912 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
2913 return -EINVAL;
2914
2915 val = swab32(addr) | SF_PROG_PAGE;
2916
2917 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2918 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
2919 goto unlock;
2920
2921 for (left = n; left; left -= c) {
2922 c = min(left, 4U);
2923 for (val = 0, i = 0; i < c; ++i)
2924 val = (val << 8) + *data++;
2925
2926 ret = sf1_write(adapter, c, c != left, 1, val);
2927 if (ret)
2928 goto unlock;
2929 }
2930 ret = flash_wait_op(adapter, 8, 1);
2931 if (ret)
2932 goto unlock;
2933
2934 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2935
2936 /* Read the page to verify the write succeeded */
2937 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
2938 if (ret)
2939 return ret;
2940
2941 if (memcmp(data - n, (u8 *)buf + offset, n)) {
2942 dev_err(adapter->pdev_dev,
2943 "failed to correctly write the flash page at %#x\n",
2944 addr);
2945 return -EIO;
2946 }
2947 return 0;
2948
2949 unlock:
2950 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2951 return ret;
2952 }
2953
2954 /**
2955 * t4_get_fw_version - read the firmware version
2956 * @adapter: the adapter
2957 * @vers: where to place the version
2958 *
2959 * Reads the FW version from flash.
2960 */
2961 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2962 {
2963 return t4_read_flash(adapter, FLASH_FW_START +
2964 offsetof(struct fw_hdr, fw_ver), 1,
2965 vers, 0);
2966 }
2967
2968 /**
2969 * t4_get_bs_version - read the firmware bootstrap version
2970 * @adapter: the adapter
2971 * @vers: where to place the version
2972 *
2973 * Reads the FW Bootstrap version from flash.
2974 */
2975 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
2976 {
2977 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
2978 offsetof(struct fw_hdr, fw_ver), 1,
2979 vers, 0);
2980 }
2981
2982 /**
2983 * t4_get_tp_version - read the TP microcode version
2984 * @adapter: the adapter
2985 * @vers: where to place the version
2986 *
2987 * Reads the TP microcode version from flash.
2988 */
2989 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
2990 {
2991 return t4_read_flash(adapter, FLASH_FW_START +
2992 offsetof(struct fw_hdr, tp_microcode_ver),
2993 1, vers, 0);
2994 }
2995
2996 /**
2997 * t4_get_exprom_version - return the Expansion ROM version (if any)
2998 * @adapter: the adapter
2999 * @vers: where to place the version
3000 *
3001 * Reads the Expansion ROM header from FLASH and returns the version
3002 * number (if present) through the @vers return value pointer. We return
3003 * this in the Firmware Version Format since it's convenient. Return
3004 * 0 on success, -ENOENT if no Expansion ROM is present.
3005 */
3006 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3007 {
3008 struct exprom_header {
3009 unsigned char hdr_arr[16]; /* must start with 0x55aa */
3010 unsigned char hdr_ver[4]; /* Expansion ROM version */
3011 } *hdr;
3012 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3013 sizeof(u32))];
3014 int ret;
3015
3016 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3017 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3018 0);
3019 if (ret)
3020 return ret;
3021
3022 hdr = (struct exprom_header *)exprom_header_buf;
3023 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3024 return -ENOENT;
3025
3026 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3027 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3028 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3029 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3030 return 0;
3031 }
3032
3033 /**
3034 * t4_check_fw_version - check if the FW is supported with this driver
3035 * @adap: the adapter
3036 *
3037 * Checks if an adapter's FW is compatible with the driver. Returns 0
3038 * if there's exact match, a negative error if the version could not be
3039 * read or there's a major version mismatch
3040 */
3041 int t4_check_fw_version(struct adapter *adap)
3042 {
3043 int i, ret, major, minor, micro;
3044 int exp_major, exp_minor, exp_micro;
3045 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3046
3047 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3048 /* Try multiple times before returning error */
3049 for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3050 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3051
3052 if (ret)
3053 return ret;
3054
3055 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3056 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3057 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3058
3059 switch (chip_version) {
3060 case CHELSIO_T4:
3061 exp_major = T4FW_MIN_VERSION_MAJOR;
3062 exp_minor = T4FW_MIN_VERSION_MINOR;
3063 exp_micro = T4FW_MIN_VERSION_MICRO;
3064 break;
3065 case CHELSIO_T5:
3066 exp_major = T5FW_MIN_VERSION_MAJOR;
3067 exp_minor = T5FW_MIN_VERSION_MINOR;
3068 exp_micro = T5FW_MIN_VERSION_MICRO;
3069 break;
3070 case CHELSIO_T6:
3071 exp_major = T6FW_MIN_VERSION_MAJOR;
3072 exp_minor = T6FW_MIN_VERSION_MINOR;
3073 exp_micro = T6FW_MIN_VERSION_MICRO;
3074 break;
3075 default:
3076 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3077 adap->chip);
3078 return -EINVAL;
3079 }
3080
3081 if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3082 (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3083 dev_err(adap->pdev_dev,
3084 "Card has firmware version %u.%u.%u, minimum "
3085 "supported firmware is %u.%u.%u.\n", major, minor,
3086 micro, exp_major, exp_minor, exp_micro);
3087 return -EFAULT;
3088 }
3089 return 0;
3090 }
3091
3092 /* Is the given firmware API compatible with the one the driver was compiled
3093 * with?
3094 */
3095 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3096 {
3097
3098 /* short circuit if it's the exact same firmware version */
3099 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3100 return 1;
3101
3102 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3103 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3104 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3105 return 1;
3106 #undef SAME_INTF
3107
3108 return 0;
3109 }
3110
3111 /* The firmware in the filesystem is usable, but should it be installed?
3112 * This routine explains itself in detail if it indicates the filesystem
3113 * firmware should be installed.
3114 */
3115 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3116 int k, int c)
3117 {
3118 const char *reason;
3119
3120 if (!card_fw_usable) {
3121 reason = "incompatible or unusable";
3122 goto install;
3123 }
3124
3125 if (k > c) {
3126 reason = "older than the version supported with this driver";
3127 goto install;
3128 }
3129
3130 return 0;
3131
3132 install:
3133 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3134 "installing firmware %u.%u.%u.%u on card.\n",
3135 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3136 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3137 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3138 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3139
3140 return 1;
3141 }
3142
3143 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3144 const u8 *fw_data, unsigned int fw_size,
3145 struct fw_hdr *card_fw, enum dev_state state,
3146 int *reset)
3147 {
3148 int ret, card_fw_usable, fs_fw_usable;
3149 const struct fw_hdr *fs_fw;
3150 const struct fw_hdr *drv_fw;
3151
3152 drv_fw = &fw_info->fw_hdr;
3153
3154 /* Read the header of the firmware on the card */
3155 ret = -t4_read_flash(adap, FLASH_FW_START,
3156 sizeof(*card_fw) / sizeof(uint32_t),
3157 (uint32_t *)card_fw, 1);
3158 if (ret == 0) {
3159 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3160 } else {
3161 dev_err(adap->pdev_dev,
3162 "Unable to read card's firmware header: %d\n", ret);
3163 card_fw_usable = 0;
3164 }
3165
3166 if (fw_data != NULL) {
3167 fs_fw = (const void *)fw_data;
3168 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3169 } else {
3170 fs_fw = NULL;
3171 fs_fw_usable = 0;
3172 }
3173
3174 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3175 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3176 /* Common case: the firmware on the card is an exact match and
3177 * the filesystem one is an exact match too, or the filesystem
3178 * one is absent/incompatible.
3179 */
3180 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3181 should_install_fs_fw(adap, card_fw_usable,
3182 be32_to_cpu(fs_fw->fw_ver),
3183 be32_to_cpu(card_fw->fw_ver))) {
3184 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3185 fw_size, 0);
3186 if (ret != 0) {
3187 dev_err(adap->pdev_dev,
3188 "failed to install firmware: %d\n", ret);
3189 goto bye;
3190 }
3191
3192 /* Installed successfully, update the cached header too. */
3193 *card_fw = *fs_fw;
3194 card_fw_usable = 1;
3195 *reset = 0; /* already reset as part of load_fw */
3196 }
3197
3198 if (!card_fw_usable) {
3199 uint32_t d, c, k;
3200
3201 d = be32_to_cpu(drv_fw->fw_ver);
3202 c = be32_to_cpu(card_fw->fw_ver);
3203 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3204
3205 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3206 "chip state %d, "
3207 "driver compiled with %d.%d.%d.%d, "
3208 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3209 state,
3210 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3211 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3212 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3213 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3214 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3215 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3216 ret = EINVAL;
3217 goto bye;
3218 }
3219
3220 /* We're using whatever's on the card and it's known to be good. */
3221 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3222 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3223
3224 bye:
3225 return ret;
3226 }
3227
3228 /**
3229 * t4_flash_erase_sectors - erase a range of flash sectors
3230 * @adapter: the adapter
3231 * @start: the first sector to erase
3232 * @end: the last sector to erase
3233 *
3234 * Erases the sectors in the given inclusive range.
3235 */
3236 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3237 {
3238 int ret = 0;
3239
3240 if (end >= adapter->params.sf_nsec)
3241 return -EINVAL;
3242
3243 while (start <= end) {
3244 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3245 (ret = sf1_write(adapter, 4, 0, 1,
3246 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3247 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3248 dev_err(adapter->pdev_dev,
3249 "erase of flash sector %d failed, error %d\n",
3250 start, ret);
3251 break;
3252 }
3253 start++;
3254 }
3255 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3256 return ret;
3257 }
3258
3259 /**
3260 * t4_flash_cfg_addr - return the address of the flash configuration file
3261 * @adapter: the adapter
3262 *
3263 * Return the address within the flash where the Firmware Configuration
3264 * File is stored.
3265 */
3266 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3267 {
3268 if (adapter->params.sf_size == 0x100000)
3269 return FLASH_FPGA_CFG_START;
3270 else
3271 return FLASH_CFG_START;
3272 }
3273
3274 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3275 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3276 * and emit an error message for mismatched firmware to save our caller the
3277 * effort ...
3278 */
3279 static bool t4_fw_matches_chip(const struct adapter *adap,
3280 const struct fw_hdr *hdr)
3281 {
3282 /* The expression below will return FALSE for any unsupported adapter
3283 * which will keep us "honest" in the future ...
3284 */
3285 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3286 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3287 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3288 return true;
3289
3290 dev_err(adap->pdev_dev,
3291 "FW image (%d) is not suitable for this adapter (%d)\n",
3292 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3293 return false;
3294 }
3295
3296 /**
3297 * t4_load_fw - download firmware
3298 * @adap: the adapter
3299 * @fw_data: the firmware image to write
3300 * @size: image size
3301 *
3302 * Write the supplied firmware image to the card's serial flash.
3303 */
3304 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3305 {
3306 u32 csum;
3307 int ret, addr;
3308 unsigned int i;
3309 u8 first_page[SF_PAGE_SIZE];
3310 const __be32 *p = (const __be32 *)fw_data;
3311 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3312 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3313 unsigned int fw_img_start = adap->params.sf_fw_start;
3314 unsigned int fw_start_sec = fw_img_start / sf_sec_size;
3315
3316 if (!size) {
3317 dev_err(adap->pdev_dev, "FW image has no data\n");
3318 return -EINVAL;
3319 }
3320 if (size & 511) {
3321 dev_err(adap->pdev_dev,
3322 "FW image size not multiple of 512 bytes\n");
3323 return -EINVAL;
3324 }
3325 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3326 dev_err(adap->pdev_dev,
3327 "FW image size differs from size in FW header\n");
3328 return -EINVAL;
3329 }
3330 if (size > FW_MAX_SIZE) {
3331 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3332 FW_MAX_SIZE);
3333 return -EFBIG;
3334 }
3335 if (!t4_fw_matches_chip(adap, hdr))
3336 return -EINVAL;
3337
3338 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3339 csum += be32_to_cpu(p[i]);
3340
3341 if (csum != 0xffffffff) {
3342 dev_err(adap->pdev_dev,
3343 "corrupted firmware image, checksum %#x\n", csum);
3344 return -EINVAL;
3345 }
3346
3347 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3348 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3349 if (ret)
3350 goto out;
3351
3352 /*
3353 * We write the correct version at the end so the driver can see a bad
3354 * version if the FW write fails. Start by writing a copy of the
3355 * first page with a bad version.
3356 */
3357 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3358 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3359 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
3360 if (ret)
3361 goto out;
3362
3363 addr = fw_img_start;
3364 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3365 addr += SF_PAGE_SIZE;
3366 fw_data += SF_PAGE_SIZE;
3367 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3368 if (ret)
3369 goto out;
3370 }
3371
3372 ret = t4_write_flash(adap,
3373 fw_img_start + offsetof(struct fw_hdr, fw_ver),
3374 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3375 out:
3376 if (ret)
3377 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3378 ret);
3379 else
3380 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3381 return ret;
3382 }
3383
3384 /**
3385 * t4_phy_fw_ver - return current PHY firmware version
3386 * @adap: the adapter
3387 * @phy_fw_ver: return value buffer for PHY firmware version
3388 *
3389 * Returns the current version of external PHY firmware on the
3390 * adapter.
3391 */
3392 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3393 {
3394 u32 param, val;
3395 int ret;
3396
3397 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3398 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3399 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3400 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3401 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3402 &param, &val);
3403 if (ret < 0)
3404 return ret;
3405 *phy_fw_ver = val;
3406 return 0;
3407 }
3408
3409 /**
3410 * t4_load_phy_fw - download port PHY firmware
3411 * @adap: the adapter
3412 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3413 * @win_lock: the lock to use to guard the memory copy
3414 * @phy_fw_version: function to check PHY firmware versions
3415 * @phy_fw_data: the PHY firmware image to write
3416 * @phy_fw_size: image size
3417 *
3418 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3419 * @phy_fw_version is supplied, then it will be used to determine if
3420 * it's necessary to perform the transfer by comparing the version
3421 * of any existing adapter PHY firmware with that of the passed in
3422 * PHY firmware image. If @win_lock is non-NULL then it will be used
3423 * around the call to t4_memory_rw() which transfers the PHY firmware
3424 * to the adapter.
3425 *
3426 * A negative error number will be returned if an error occurs. If
3427 * version number support is available and there's no need to upgrade
3428 * the firmware, 0 will be returned. If firmware is successfully
3429 * transferred to the adapter, 1 will be retured.
3430 *
3431 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3432 * a result, a RESET of the adapter would cause that RAM to lose its
3433 * contents. Thus, loading PHY firmware on such adapters must happen
3434 * after any FW_RESET_CMDs ...
3435 */
3436 int t4_load_phy_fw(struct adapter *adap,
3437 int win, spinlock_t *win_lock,
3438 int (*phy_fw_version)(const u8 *, size_t),
3439 const u8 *phy_fw_data, size_t phy_fw_size)
3440 {
3441 unsigned long mtype = 0, maddr = 0;
3442 u32 param, val;
3443 int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3444 int ret;
3445
3446 /* If we have version number support, then check to see if the adapter
3447 * already has up-to-date PHY firmware loaded.
3448 */
3449 if (phy_fw_version) {
3450 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3451 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3452 if (ret < 0)
3453 return ret;
3454
3455 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3456 CH_WARN(adap, "PHY Firmware already up-to-date, "
3457 "version %#x\n", cur_phy_fw_ver);
3458 return 0;
3459 }
3460 }
3461
3462 /* Ask the firmware where it wants us to copy the PHY firmware image.
3463 * The size of the file requires a special version of the READ coommand
3464 * which will pass the file size via the values field in PARAMS_CMD and
3465 * retrieve the return value from firmware and place it in the same
3466 * buffer values
3467 */
3468 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3469 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3470 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3471 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3472 val = phy_fw_size;
3473 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3474 &param, &val, 1);
3475 if (ret < 0)
3476 return ret;
3477 mtype = val >> 8;
3478 maddr = (val & 0xff) << 16;
3479
3480 /* Copy the supplied PHY Firmware image to the adapter memory location
3481 * allocated by the adapter firmware.
3482 */
3483 if (win_lock)
3484 spin_lock_bh(win_lock);
3485 ret = t4_memory_rw(adap, win, mtype, maddr,
3486 phy_fw_size, (__be32 *)phy_fw_data,
3487 T4_MEMORY_WRITE);
3488 if (win_lock)
3489 spin_unlock_bh(win_lock);
3490 if (ret)
3491 return ret;
3492
3493 /* Tell the firmware that the PHY firmware image has been written to
3494 * RAM and it can now start copying it over to the PHYs. The chip
3495 * firmware will RESET the affected PHYs as part of this operation
3496 * leaving them running the new PHY firmware image.
3497 */
3498 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3499 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3500 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3501 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3502 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3503 &param, &val, 30000);
3504
3505 /* If we have version number support, then check to see that the new
3506 * firmware got loaded properly.
3507 */
3508 if (phy_fw_version) {
3509 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3510 if (ret < 0)
3511 return ret;
3512
3513 if (cur_phy_fw_ver != new_phy_fw_vers) {
3514 CH_WARN(adap, "PHY Firmware did not update: "
3515 "version on adapter %#x, "
3516 "version flashed %#x\n",
3517 cur_phy_fw_ver, new_phy_fw_vers);
3518 return -ENXIO;
3519 }
3520 }
3521
3522 return 1;
3523 }
3524
3525 /**
3526 * t4_fwcache - firmware cache operation
3527 * @adap: the adapter
3528 * @op : the operation (flush or flush and invalidate)
3529 */
3530 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3531 {
3532 struct fw_params_cmd c;
3533
3534 memset(&c, 0, sizeof(c));
3535 c.op_to_vfn =
3536 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3537 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3538 FW_PARAMS_CMD_PFN_V(adap->pf) |
3539 FW_PARAMS_CMD_VFN_V(0));
3540 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3541 c.param[0].mnem =
3542 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3543 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3544 c.param[0].val = (__force __be32)op;
3545
3546 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3547 }
3548
3549 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3550 unsigned int *pif_req_wrptr,
3551 unsigned int *pif_rsp_wrptr)
3552 {
3553 int i, j;
3554 u32 cfg, val, req, rsp;
3555
3556 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3557 if (cfg & LADBGEN_F)
3558 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3559
3560 val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3561 req = POLADBGWRPTR_G(val);
3562 rsp = PILADBGWRPTR_G(val);
3563 if (pif_req_wrptr)
3564 *pif_req_wrptr = req;
3565 if (pif_rsp_wrptr)
3566 *pif_rsp_wrptr = rsp;
3567
3568 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3569 for (j = 0; j < 6; j++) {
3570 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3571 PILADBGRDPTR_V(rsp));
3572 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3573 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3574 req++;
3575 rsp++;
3576 }
3577 req = (req + 2) & POLADBGRDPTR_M;
3578 rsp = (rsp + 2) & PILADBGRDPTR_M;
3579 }
3580 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3581 }
3582
3583 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3584 {
3585 u32 cfg;
3586 int i, j, idx;
3587
3588 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3589 if (cfg & LADBGEN_F)
3590 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3591
3592 for (i = 0; i < CIM_MALA_SIZE; i++) {
3593 for (j = 0; j < 5; j++) {
3594 idx = 8 * i + j;
3595 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3596 PILADBGRDPTR_V(idx));
3597 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3598 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3599 }
3600 }
3601 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3602 }
3603
3604 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3605 {
3606 unsigned int i, j;
3607
3608 for (i = 0; i < 8; i++) {
3609 u32 *p = la_buf + i;
3610
3611 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3612 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3613 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3614 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3615 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3616 }
3617 }
3618
3619 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
3620 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
3621 FW_PORT_CAP_ANEG)
3622
3623 /**
3624 * t4_link_l1cfg - apply link configuration to MAC/PHY
3625 * @phy: the PHY to setup
3626 * @mac: the MAC to setup
3627 * @lc: the requested link configuration
3628 *
3629 * Set up a port's MAC and PHY according to a desired link configuration.
3630 * - If the PHY can auto-negotiate first decide what to advertise, then
3631 * enable/disable auto-negotiation as desired, and reset.
3632 * - If the PHY does not auto-negotiate just reset it.
3633 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3634 * otherwise do it later based on the outcome of auto-negotiation.
3635 */
3636 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3637 struct link_config *lc)
3638 {
3639 struct fw_port_cmd c;
3640 unsigned int fc = 0, mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO);
3641
3642 lc->link_ok = 0;
3643 if (lc->requested_fc & PAUSE_RX)
3644 fc |= FW_PORT_CAP_FC_RX;
3645 if (lc->requested_fc & PAUSE_TX)
3646 fc |= FW_PORT_CAP_FC_TX;
3647
3648 memset(&c, 0, sizeof(c));
3649 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3650 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3651 FW_PORT_CMD_PORTID_V(port));
3652 c.action_to_len16 =
3653 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3654 FW_LEN16(c));
3655
3656 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
3657 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
3658 fc);
3659 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3660 } else if (lc->autoneg == AUTONEG_DISABLE) {
3661 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
3662 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3663 } else
3664 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
3665
3666 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3667 }
3668
3669 /**
3670 * t4_restart_aneg - restart autonegotiation
3671 * @adap: the adapter
3672 * @mbox: mbox to use for the FW command
3673 * @port: the port id
3674 *
3675 * Restarts autonegotiation for the selected port.
3676 */
3677 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3678 {
3679 struct fw_port_cmd c;
3680
3681 memset(&c, 0, sizeof(c));
3682 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3683 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3684 FW_PORT_CMD_PORTID_V(port));
3685 c.action_to_len16 =
3686 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3687 FW_LEN16(c));
3688 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3689 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3690 }
3691
3692 typedef void (*int_handler_t)(struct adapter *adap);
3693
3694 struct intr_info {
3695 unsigned int mask; /* bits to check in interrupt status */
3696 const char *msg; /* message to print or NULL */
3697 short stat_idx; /* stat counter to increment or -1 */
3698 unsigned short fatal; /* whether the condition reported is fatal */
3699 int_handler_t int_handler; /* platform-specific int handler */
3700 };
3701
3702 /**
3703 * t4_handle_intr_status - table driven interrupt handler
3704 * @adapter: the adapter that generated the interrupt
3705 * @reg: the interrupt status register to process
3706 * @acts: table of interrupt actions
3707 *
3708 * A table driven interrupt handler that applies a set of masks to an
3709 * interrupt status word and performs the corresponding actions if the
3710 * interrupts described by the mask have occurred. The actions include
3711 * optionally emitting a warning or alert message. The table is terminated
3712 * by an entry specifying mask 0. Returns the number of fatal interrupt
3713 * conditions.
3714 */
3715 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
3716 const struct intr_info *acts)
3717 {
3718 int fatal = 0;
3719 unsigned int mask = 0;
3720 unsigned int status = t4_read_reg(adapter, reg);
3721
3722 for ( ; acts->mask; ++acts) {
3723 if (!(status & acts->mask))
3724 continue;
3725 if (acts->fatal) {
3726 fatal++;
3727 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3728 status & acts->mask);
3729 } else if (acts->msg && printk_ratelimit())
3730 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3731 status & acts->mask);
3732 if (acts->int_handler)
3733 acts->int_handler(adapter);
3734 mask |= acts->mask;
3735 }
3736 status &= mask;
3737 if (status) /* clear processed interrupts */
3738 t4_write_reg(adapter, reg, status);
3739 return fatal;
3740 }
3741
3742 /*
3743 * Interrupt handler for the PCIE module.
3744 */
3745 static void pcie_intr_handler(struct adapter *adapter)
3746 {
3747 static const struct intr_info sysbus_intr_info[] = {
3748 { RNPP_F, "RXNP array parity error", -1, 1 },
3749 { RPCP_F, "RXPC array parity error", -1, 1 },
3750 { RCIP_F, "RXCIF array parity error", -1, 1 },
3751 { RCCP_F, "Rx completions control array parity error", -1, 1 },
3752 { RFTP_F, "RXFT array parity error", -1, 1 },
3753 { 0 }
3754 };
3755 static const struct intr_info pcie_port_intr_info[] = {
3756 { TPCP_F, "TXPC array parity error", -1, 1 },
3757 { TNPP_F, "TXNP array parity error", -1, 1 },
3758 { TFTP_F, "TXFT array parity error", -1, 1 },
3759 { TCAP_F, "TXCA array parity error", -1, 1 },
3760 { TCIP_F, "TXCIF array parity error", -1, 1 },
3761 { RCAP_F, "RXCA array parity error", -1, 1 },
3762 { OTDD_F, "outbound request TLP discarded", -1, 1 },
3763 { RDPE_F, "Rx data parity error", -1, 1 },
3764 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
3765 { 0 }
3766 };
3767 static const struct intr_info pcie_intr_info[] = {
3768 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
3769 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
3770 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
3771 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3772 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3773 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3774 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3775 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
3776 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
3777 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3778 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
3779 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3780 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3781 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
3782 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3783 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3784 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
3785 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3786 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3787 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3788 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3789 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
3790 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
3791 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3792 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
3793 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
3794 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
3795 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
3796 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
3797 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
3798 -1, 0 },
3799 { 0 }
3800 };
3801
3802 static struct intr_info t5_pcie_intr_info[] = {
3803 { MSTGRPPERR_F, "Master Response Read Queue parity error",
3804 -1, 1 },
3805 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
3806 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
3807 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3808 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3809 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3810 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3811 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
3812 -1, 1 },
3813 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
3814 -1, 1 },
3815 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3816 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
3817 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3818 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3819 { DREQWRPERR_F, "PCI DMA channel write request parity error",
3820 -1, 1 },
3821 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3822 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3823 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
3824 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3825 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3826 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3827 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3828 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
3829 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
3830 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3831 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
3832 -1, 1 },
3833 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
3834 -1, 1 },
3835 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
3836 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
3837 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
3838 { READRSPERR_F, "Outbound read error", -1, 0 },
3839 { 0 }
3840 };
3841
3842 int fat;
3843
3844 if (is_t4(adapter->params.chip))
3845 fat = t4_handle_intr_status(adapter,
3846 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
3847 sysbus_intr_info) +
3848 t4_handle_intr_status(adapter,
3849 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
3850 pcie_port_intr_info) +
3851 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3852 pcie_intr_info);
3853 else
3854 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3855 t5_pcie_intr_info);
3856
3857 if (fat)
3858 t4_fatal_err(adapter);
3859 }
3860
3861 /*
3862 * TP interrupt handler.
3863 */
3864 static void tp_intr_handler(struct adapter *adapter)
3865 {
3866 static const struct intr_info tp_intr_info[] = {
3867 { 0x3fffffff, "TP parity error", -1, 1 },
3868 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
3869 { 0 }
3870 };
3871
3872 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
3873 t4_fatal_err(adapter);
3874 }
3875
3876 /*
3877 * SGE interrupt handler.
3878 */
3879 static void sge_intr_handler(struct adapter *adapter)
3880 {
3881 u64 v;
3882 u32 err;
3883
3884 static const struct intr_info sge_intr_info[] = {
3885 { ERR_CPL_EXCEED_IQE_SIZE_F,
3886 "SGE received CPL exceeding IQE size", -1, 1 },
3887 { ERR_INVALID_CIDX_INC_F,
3888 "SGE GTS CIDX increment too large", -1, 0 },
3889 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
3890 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
3891 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
3892 "SGE IQID > 1023 received CPL for FL", -1, 0 },
3893 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
3894 0 },
3895 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
3896 0 },
3897 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
3898 0 },
3899 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
3900 0 },
3901 { ERR_ING_CTXT_PRIO_F,
3902 "SGE too many priority ingress contexts", -1, 0 },
3903 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
3904 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
3905 { 0 }
3906 };
3907
3908 static struct intr_info t4t5_sge_intr_info[] = {
3909 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
3910 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
3911 { ERR_EGR_CTXT_PRIO_F,
3912 "SGE too many priority egress contexts", -1, 0 },
3913 { 0 }
3914 };
3915
3916 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
3917 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
3918 if (v) {
3919 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
3920 (unsigned long long)v);
3921 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
3922 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
3923 }
3924
3925 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
3926 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
3927 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
3928 t4t5_sge_intr_info);
3929
3930 err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
3931 if (err & ERROR_QID_VALID_F) {
3932 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
3933 ERROR_QID_G(err));
3934 if (err & UNCAPTURED_ERROR_F)
3935 dev_err(adapter->pdev_dev,
3936 "SGE UNCAPTURED_ERROR set (clearing)\n");
3937 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
3938 UNCAPTURED_ERROR_F);
3939 }
3940
3941 if (v != 0)
3942 t4_fatal_err(adapter);
3943 }
3944
3945 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
3946 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
3947 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
3948 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
3949
3950 /*
3951 * CIM interrupt handler.
3952 */
3953 static void cim_intr_handler(struct adapter *adapter)
3954 {
3955 static const struct intr_info cim_intr_info[] = {
3956 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
3957 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
3958 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
3959 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
3960 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
3961 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
3962 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
3963 { 0 }
3964 };
3965 static const struct intr_info cim_upintr_info[] = {
3966 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
3967 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
3968 { ILLWRINT_F, "CIM illegal write", -1, 1 },
3969 { ILLRDINT_F, "CIM illegal read", -1, 1 },
3970 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
3971 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
3972 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
3973 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
3974 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
3975 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
3976 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
3977 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
3978 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
3979 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
3980 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
3981 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
3982 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
3983 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
3984 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
3985 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
3986 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
3987 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
3988 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
3989 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
3990 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
3991 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
3992 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
3993 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
3994 { 0 }
3995 };
3996
3997 int fat;
3998
3999 if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F)
4000 t4_report_fw_error(adapter);
4001
4002 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4003 cim_intr_info) +
4004 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4005 cim_upintr_info);
4006 if (fat)
4007 t4_fatal_err(adapter);
4008 }
4009
4010 /*
4011 * ULP RX interrupt handler.
4012 */
4013 static void ulprx_intr_handler(struct adapter *adapter)
4014 {
4015 static const struct intr_info ulprx_intr_info[] = {
4016 { 0x1800000, "ULPRX context error", -1, 1 },
4017 { 0x7fffff, "ULPRX parity error", -1, 1 },
4018 { 0 }
4019 };
4020
4021 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4022 t4_fatal_err(adapter);
4023 }
4024
4025 /*
4026 * ULP TX interrupt handler.
4027 */
4028 static void ulptx_intr_handler(struct adapter *adapter)
4029 {
4030 static const struct intr_info ulptx_intr_info[] = {
4031 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4032 0 },
4033 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4034 0 },
4035 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4036 0 },
4037 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4038 0 },
4039 { 0xfffffff, "ULPTX parity error", -1, 1 },
4040 { 0 }
4041 };
4042
4043 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4044 t4_fatal_err(adapter);
4045 }
4046
4047 /*
4048 * PM TX interrupt handler.
4049 */
4050 static void pmtx_intr_handler(struct adapter *adapter)
4051 {
4052 static const struct intr_info pmtx_intr_info[] = {
4053 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4054 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4055 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4056 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4057 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4058 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4059 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4060 -1, 1 },
4061 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4062 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4063 { 0 }
4064 };
4065
4066 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4067 t4_fatal_err(adapter);
4068 }
4069
4070 /*
4071 * PM RX interrupt handler.
4072 */
4073 static void pmrx_intr_handler(struct adapter *adapter)
4074 {
4075 static const struct intr_info pmrx_intr_info[] = {
4076 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4077 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4078 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4079 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4080 -1, 1 },
4081 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4082 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4083 { 0 }
4084 };
4085
4086 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4087 t4_fatal_err(adapter);
4088 }
4089
4090 /*
4091 * CPL switch interrupt handler.
4092 */
4093 static void cplsw_intr_handler(struct adapter *adapter)
4094 {
4095 static const struct intr_info cplsw_intr_info[] = {
4096 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4097 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4098 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4099 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4100 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4101 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4102 { 0 }
4103 };
4104
4105 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4106 t4_fatal_err(adapter);
4107 }
4108
4109 /*
4110 * LE interrupt handler.
4111 */
4112 static void le_intr_handler(struct adapter *adap)
4113 {
4114 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4115 static const struct intr_info le_intr_info[] = {
4116 { LIPMISS_F, "LE LIP miss", -1, 0 },
4117 { LIP0_F, "LE 0 LIP error", -1, 0 },
4118 { PARITYERR_F, "LE parity error", -1, 1 },
4119 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4120 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4121 { 0 }
4122 };
4123
4124 static struct intr_info t6_le_intr_info[] = {
4125 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4126 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4127 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4128 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4129 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4130 { 0 }
4131 };
4132
4133 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4134 (chip <= CHELSIO_T5) ?
4135 le_intr_info : t6_le_intr_info))
4136 t4_fatal_err(adap);
4137 }
4138
4139 /*
4140 * MPS interrupt handler.
4141 */
4142 static void mps_intr_handler(struct adapter *adapter)
4143 {
4144 static const struct intr_info mps_rx_intr_info[] = {
4145 { 0xffffff, "MPS Rx parity error", -1, 1 },
4146 { 0 }
4147 };
4148 static const struct intr_info mps_tx_intr_info[] = {
4149 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4150 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4151 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4152 -1, 1 },
4153 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4154 -1, 1 },
4155 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4156 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4157 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4158 { 0 }
4159 };
4160 static const struct intr_info mps_trc_intr_info[] = {
4161 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4162 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4163 -1, 1 },
4164 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4165 { 0 }
4166 };
4167 static const struct intr_info mps_stat_sram_intr_info[] = {
4168 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4169 { 0 }
4170 };
4171 static const struct intr_info mps_stat_tx_intr_info[] = {
4172 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4173 { 0 }
4174 };
4175 static const struct intr_info mps_stat_rx_intr_info[] = {
4176 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4177 { 0 }
4178 };
4179 static const struct intr_info mps_cls_intr_info[] = {
4180 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4181 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4182 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4183 { 0 }
4184 };
4185
4186 int fat;
4187
4188 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4189 mps_rx_intr_info) +
4190 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4191 mps_tx_intr_info) +
4192 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4193 mps_trc_intr_info) +
4194 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4195 mps_stat_sram_intr_info) +
4196 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4197 mps_stat_tx_intr_info) +
4198 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4199 mps_stat_rx_intr_info) +
4200 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4201 mps_cls_intr_info);
4202
4203 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4204 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
4205 if (fat)
4206 t4_fatal_err(adapter);
4207 }
4208
4209 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4210 ECC_UE_INT_CAUSE_F)
4211
4212 /*
4213 * EDC/MC interrupt handler.
4214 */
4215 static void mem_intr_handler(struct adapter *adapter, int idx)
4216 {
4217 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4218
4219 unsigned int addr, cnt_addr, v;
4220
4221 if (idx <= MEM_EDC1) {
4222 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4223 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4224 } else if (idx == MEM_MC) {
4225 if (is_t4(adapter->params.chip)) {
4226 addr = MC_INT_CAUSE_A;
4227 cnt_addr = MC_ECC_STATUS_A;
4228 } else {
4229 addr = MC_P_INT_CAUSE_A;
4230 cnt_addr = MC_P_ECC_STATUS_A;
4231 }
4232 } else {
4233 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4234 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4235 }
4236
4237 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4238 if (v & PERR_INT_CAUSE_F)
4239 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4240 name[idx]);
4241 if (v & ECC_CE_INT_CAUSE_F) {
4242 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4243
4244 t4_edc_err_read(adapter, idx);
4245
4246 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4247 if (printk_ratelimit())
4248 dev_warn(adapter->pdev_dev,
4249 "%u %s correctable ECC data error%s\n",
4250 cnt, name[idx], cnt > 1 ? "s" : "");
4251 }
4252 if (v & ECC_UE_INT_CAUSE_F)
4253 dev_alert(adapter->pdev_dev,
4254 "%s uncorrectable ECC data error\n", name[idx]);
4255
4256 t4_write_reg(adapter, addr, v);
4257 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4258 t4_fatal_err(adapter);
4259 }
4260
4261 /*
4262 * MA interrupt handler.
4263 */
4264 static void ma_intr_handler(struct adapter *adap)
4265 {
4266 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4267
4268 if (status & MEM_PERR_INT_CAUSE_F) {
4269 dev_alert(adap->pdev_dev,
4270 "MA parity error, parity status %#x\n",
4271 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4272 if (is_t5(adap->params.chip))
4273 dev_alert(adap->pdev_dev,
4274 "MA parity error, parity status %#x\n",
4275 t4_read_reg(adap,
4276 MA_PARITY_ERROR_STATUS2_A));
4277 }
4278 if (status & MEM_WRAP_INT_CAUSE_F) {
4279 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4280 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4281 "client %u to address %#x\n",
4282 MEM_WRAP_CLIENT_NUM_G(v),
4283 MEM_WRAP_ADDRESS_G(v) << 4);
4284 }
4285 t4_write_reg(adap, MA_INT_CAUSE_A, status);
4286 t4_fatal_err(adap);
4287 }
4288
4289 /*
4290 * SMB interrupt handler.
4291 */
4292 static void smb_intr_handler(struct adapter *adap)
4293 {
4294 static const struct intr_info smb_intr_info[] = {
4295 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4296 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4297 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4298 { 0 }
4299 };
4300
4301 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4302 t4_fatal_err(adap);
4303 }
4304
4305 /*
4306 * NC-SI interrupt handler.
4307 */
4308 static void ncsi_intr_handler(struct adapter *adap)
4309 {
4310 static const struct intr_info ncsi_intr_info[] = {
4311 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4312 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4313 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4314 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4315 { 0 }
4316 };
4317
4318 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4319 t4_fatal_err(adap);
4320 }
4321
4322 /*
4323 * XGMAC interrupt handler.
4324 */
4325 static void xgmac_intr_handler(struct adapter *adap, int port)
4326 {
4327 u32 v, int_cause_reg;
4328
4329 if (is_t4(adap->params.chip))
4330 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4331 else
4332 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4333
4334 v = t4_read_reg(adap, int_cause_reg);
4335
4336 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4337 if (!v)
4338 return;
4339
4340 if (v & TXFIFO_PRTY_ERR_F)
4341 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4342 port);
4343 if (v & RXFIFO_PRTY_ERR_F)
4344 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4345 port);
4346 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4347 t4_fatal_err(adap);
4348 }
4349
4350 /*
4351 * PL interrupt handler.
4352 */
4353 static void pl_intr_handler(struct adapter *adap)
4354 {
4355 static const struct intr_info pl_intr_info[] = {
4356 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4357 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4358 { 0 }
4359 };
4360
4361 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4362 t4_fatal_err(adap);
4363 }
4364
4365 #define PF_INTR_MASK (PFSW_F)
4366 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4367 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4368 CPL_SWITCH_F | SGE_F | ULP_TX_F)
4369
4370 /**
4371 * t4_slow_intr_handler - control path interrupt handler
4372 * @adapter: the adapter
4373 *
4374 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
4375 * The designation 'slow' is because it involves register reads, while
4376 * data interrupts typically don't involve any MMIOs.
4377 */
4378 int t4_slow_intr_handler(struct adapter *adapter)
4379 {
4380 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4381
4382 if (!(cause & GLBL_INTR_MASK))
4383 return 0;
4384 if (cause & CIM_F)
4385 cim_intr_handler(adapter);
4386 if (cause & MPS_F)
4387 mps_intr_handler(adapter);
4388 if (cause & NCSI_F)
4389 ncsi_intr_handler(adapter);
4390 if (cause & PL_F)
4391 pl_intr_handler(adapter);
4392 if (cause & SMB_F)
4393 smb_intr_handler(adapter);
4394 if (cause & XGMAC0_F)
4395 xgmac_intr_handler(adapter, 0);
4396 if (cause & XGMAC1_F)
4397 xgmac_intr_handler(adapter, 1);
4398 if (cause & XGMAC_KR0_F)
4399 xgmac_intr_handler(adapter, 2);
4400 if (cause & XGMAC_KR1_F)
4401 xgmac_intr_handler(adapter, 3);
4402 if (cause & PCIE_F)
4403 pcie_intr_handler(adapter);
4404 if (cause & MC_F)
4405 mem_intr_handler(adapter, MEM_MC);
4406 if (is_t5(adapter->params.chip) && (cause & MC1_F))
4407 mem_intr_handler(adapter, MEM_MC1);
4408 if (cause & EDC0_F)
4409 mem_intr_handler(adapter, MEM_EDC0);
4410 if (cause & EDC1_F)
4411 mem_intr_handler(adapter, MEM_EDC1);
4412 if (cause & LE_F)
4413 le_intr_handler(adapter);
4414 if (cause & TP_F)
4415 tp_intr_handler(adapter);
4416 if (cause & MA_F)
4417 ma_intr_handler(adapter);
4418 if (cause & PM_TX_F)
4419 pmtx_intr_handler(adapter);
4420 if (cause & PM_RX_F)
4421 pmrx_intr_handler(adapter);
4422 if (cause & ULP_RX_F)
4423 ulprx_intr_handler(adapter);
4424 if (cause & CPL_SWITCH_F)
4425 cplsw_intr_handler(adapter);
4426 if (cause & SGE_F)
4427 sge_intr_handler(adapter);
4428 if (cause & ULP_TX_F)
4429 ulptx_intr_handler(adapter);
4430
4431 /* Clear the interrupts just processed for which we are the master. */
4432 t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4433 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4434 return 1;
4435 }
4436
4437 /**
4438 * t4_intr_enable - enable interrupts
4439 * @adapter: the adapter whose interrupts should be enabled
4440 *
4441 * Enable PF-specific interrupts for the calling function and the top-level
4442 * interrupt concentrator for global interrupts. Interrupts are already
4443 * enabled at each module, here we just enable the roots of the interrupt
4444 * hierarchies.
4445 *
4446 * Note: this function should be called only when the driver manages
4447 * non PF-specific interrupts from the various HW modules. Only one PCI
4448 * function at a time should be doing this.
4449 */
4450 void t4_intr_enable(struct adapter *adapter)
4451 {
4452 u32 val = 0;
4453 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4454 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4455 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4456
4457 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4458 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4459 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4460 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4461 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4462 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4463 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4464 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4465 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4466 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4467 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4468 }
4469
4470 /**
4471 * t4_intr_disable - disable interrupts
4472 * @adapter: the adapter whose interrupts should be disabled
4473 *
4474 * Disable interrupts. We only disable the top-level interrupt
4475 * concentrators. The caller must be a PCI function managing global
4476 * interrupts.
4477 */
4478 void t4_intr_disable(struct adapter *adapter)
4479 {
4480 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4481 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4482 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4483
4484 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4485 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
4486 }
4487
4488 /**
4489 * t4_config_rss_range - configure a portion of the RSS mapping table
4490 * @adapter: the adapter
4491 * @mbox: mbox to use for the FW command
4492 * @viid: virtual interface whose RSS subtable is to be written
4493 * @start: start entry in the table to write
4494 * @n: how many table entries to write
4495 * @rspq: values for the response queue lookup table
4496 * @nrspq: number of values in @rspq
4497 *
4498 * Programs the selected part of the VI's RSS mapping table with the
4499 * provided values. If @nrspq < @n the supplied values are used repeatedly
4500 * until the full table range is populated.
4501 *
4502 * The caller must ensure the values in @rspq are in the range allowed for
4503 * @viid.
4504 */
4505 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4506 int start, int n, const u16 *rspq, unsigned int nrspq)
4507 {
4508 int ret;
4509 const u16 *rsp = rspq;
4510 const u16 *rsp_end = rspq + nrspq;
4511 struct fw_rss_ind_tbl_cmd cmd;
4512
4513 memset(&cmd, 0, sizeof(cmd));
4514 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
4515 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4516 FW_RSS_IND_TBL_CMD_VIID_V(viid));
4517 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4518
4519 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
4520 while (n > 0) {
4521 int nq = min(n, 32);
4522 __be32 *qp = &cmd.iq0_to_iq2;
4523
4524 cmd.niqid = cpu_to_be16(nq);
4525 cmd.startidx = cpu_to_be16(start);
4526
4527 start += nq;
4528 n -= nq;
4529
4530 while (nq > 0) {
4531 unsigned int v;
4532
4533 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
4534 if (++rsp >= rsp_end)
4535 rsp = rspq;
4536 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
4537 if (++rsp >= rsp_end)
4538 rsp = rspq;
4539 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
4540 if (++rsp >= rsp_end)
4541 rsp = rspq;
4542
4543 *qp++ = cpu_to_be32(v);
4544 nq -= 3;
4545 }
4546
4547 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4548 if (ret)
4549 return ret;
4550 }
4551 return 0;
4552 }
4553
4554 /**
4555 * t4_config_glbl_rss - configure the global RSS mode
4556 * @adapter: the adapter
4557 * @mbox: mbox to use for the FW command
4558 * @mode: global RSS mode
4559 * @flags: mode-specific flags
4560 *
4561 * Sets the global RSS mode.
4562 */
4563 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4564 unsigned int flags)
4565 {
4566 struct fw_rss_glb_config_cmd c;
4567
4568 memset(&c, 0, sizeof(c));
4569 c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
4570 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
4571 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4572 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4573 c.u.manual.mode_pkd =
4574 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4575 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4576 c.u.basicvirtual.mode_pkd =
4577 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4578 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4579 } else
4580 return -EINVAL;
4581 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4582 }
4583
4584 /**
4585 * t4_config_vi_rss - configure per VI RSS settings
4586 * @adapter: the adapter
4587 * @mbox: mbox to use for the FW command
4588 * @viid: the VI id
4589 * @flags: RSS flags
4590 * @defq: id of the default RSS queue for the VI.
4591 *
4592 * Configures VI-specific RSS properties.
4593 */
4594 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
4595 unsigned int flags, unsigned int defq)
4596 {
4597 struct fw_rss_vi_config_cmd c;
4598
4599 memset(&c, 0, sizeof(c));
4600 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
4601 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4602 FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
4603 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4604 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
4605 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
4606 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4607 }
4608
4609 /* Read an RSS table row */
4610 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
4611 {
4612 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
4613 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
4614 5, 0, val);
4615 }
4616
4617 /**
4618 * t4_read_rss - read the contents of the RSS mapping table
4619 * @adapter: the adapter
4620 * @map: holds the contents of the RSS mapping table
4621 *
4622 * Reads the contents of the RSS hash->queue mapping table.
4623 */
4624 int t4_read_rss(struct adapter *adapter, u16 *map)
4625 {
4626 u32 val;
4627 int i, ret;
4628
4629 for (i = 0; i < RSS_NENTRIES / 2; ++i) {
4630 ret = rd_rss_row(adapter, i, &val);
4631 if (ret)
4632 return ret;
4633 *map++ = LKPTBLQUEUE0_G(val);
4634 *map++ = LKPTBLQUEUE1_G(val);
4635 }
4636 return 0;
4637 }
4638
4639 static unsigned int t4_use_ldst(struct adapter *adap)
4640 {
4641 return (adap->flags & FW_OK) || !adap->use_bd;
4642 }
4643
4644 /**
4645 * t4_fw_tp_pio_rw - Access TP PIO through LDST
4646 * @adap: the adapter
4647 * @vals: where the indirect register values are stored/written
4648 * @nregs: how many indirect registers to read/write
4649 * @start_idx: index of first indirect register to read/write
4650 * @rw: Read (1) or Write (0)
4651 *
4652 * Access TP PIO registers through LDST
4653 */
4654 static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
4655 unsigned int start_index, unsigned int rw)
4656 {
4657 int ret, i;
4658 int cmd = FW_LDST_ADDRSPC_TP_PIO;
4659 struct fw_ldst_cmd c;
4660
4661 for (i = 0 ; i < nregs; i++) {
4662 memset(&c, 0, sizeof(c));
4663 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
4664 FW_CMD_REQUEST_F |
4665 (rw ? FW_CMD_READ_F :
4666 FW_CMD_WRITE_F) |
4667 FW_LDST_CMD_ADDRSPACE_V(cmd));
4668 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4669
4670 c.u.addrval.addr = cpu_to_be32(start_index + i);
4671 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
4672 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4673 if (!ret && rw)
4674 vals[i] = be32_to_cpu(c.u.addrval.val);
4675 }
4676 }
4677
4678 /**
4679 * t4_read_rss_key - read the global RSS key
4680 * @adap: the adapter
4681 * @key: 10-entry array holding the 320-bit RSS key
4682 *
4683 * Reads the global 320-bit RSS key.
4684 */
4685 void t4_read_rss_key(struct adapter *adap, u32 *key)
4686 {
4687 if (t4_use_ldst(adap))
4688 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1);
4689 else
4690 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4691 TP_RSS_SECRET_KEY0_A);
4692 }
4693
4694 /**
4695 * t4_write_rss_key - program one of the RSS keys
4696 * @adap: the adapter
4697 * @key: 10-entry array holding the 320-bit RSS key
4698 * @idx: which RSS key to write
4699 *
4700 * Writes one of the RSS keys with the given 320-bit value. If @idx is
4701 * 0..15 the corresponding entry in the RSS key table is written,
4702 * otherwise the global RSS key is written.
4703 */
4704 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx)
4705 {
4706 u8 rss_key_addr_cnt = 16;
4707 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
4708
4709 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
4710 * allows access to key addresses 16-63 by using KeyWrAddrX
4711 * as index[5:4](upper 2) into key table
4712 */
4713 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
4714 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
4715 rss_key_addr_cnt = 32;
4716
4717 if (t4_use_ldst(adap))
4718 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0);
4719 else
4720 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4721 TP_RSS_SECRET_KEY0_A);
4722
4723 if (idx >= 0 && idx < rss_key_addr_cnt) {
4724 if (rss_key_addr_cnt > 16)
4725 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4726 KEYWRADDRX_V(idx >> 4) |
4727 T6_VFWRADDR_V(idx) | KEYWREN_F);
4728 else
4729 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4730 KEYWRADDR_V(idx) | KEYWREN_F);
4731 }
4732 }
4733
4734 /**
4735 * t4_read_rss_pf_config - read PF RSS Configuration Table
4736 * @adapter: the adapter
4737 * @index: the entry in the PF RSS table to read
4738 * @valp: where to store the returned value
4739 *
4740 * Reads the PF RSS Configuration Table at the specified index and returns
4741 * the value found there.
4742 */
4743 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
4744 u32 *valp)
4745 {
4746 if (t4_use_ldst(adapter))
4747 t4_fw_tp_pio_rw(adapter, valp, 1,
4748 TP_RSS_PF0_CONFIG_A + index, 1);
4749 else
4750 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4751 valp, 1, TP_RSS_PF0_CONFIG_A + index);
4752 }
4753
4754 /**
4755 * t4_read_rss_vf_config - read VF RSS Configuration Table
4756 * @adapter: the adapter
4757 * @index: the entry in the VF RSS table to read
4758 * @vfl: where to store the returned VFL
4759 * @vfh: where to store the returned VFH
4760 *
4761 * Reads the VF RSS Configuration Table at the specified index and returns
4762 * the (VFL, VFH) values found there.
4763 */
4764 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
4765 u32 *vfl, u32 *vfh)
4766 {
4767 u32 vrt, mask, data;
4768
4769 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
4770 mask = VFWRADDR_V(VFWRADDR_M);
4771 data = VFWRADDR_V(index);
4772 } else {
4773 mask = T6_VFWRADDR_V(T6_VFWRADDR_M);
4774 data = T6_VFWRADDR_V(index);
4775 }
4776
4777 /* Request that the index'th VF Table values be read into VFL/VFH.
4778 */
4779 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
4780 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
4781 vrt |= data | VFRDEN_F;
4782 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
4783
4784 /* Grab the VFL/VFH values ...
4785 */
4786 if (t4_use_ldst(adapter)) {
4787 t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1);
4788 t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1);
4789 } else {
4790 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4791 vfl, 1, TP_RSS_VFL_CONFIG_A);
4792 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4793 vfh, 1, TP_RSS_VFH_CONFIG_A);
4794 }
4795 }
4796
4797 /**
4798 * t4_read_rss_pf_map - read PF RSS Map
4799 * @adapter: the adapter
4800 *
4801 * Reads the PF RSS Map register and returns its value.
4802 */
4803 u32 t4_read_rss_pf_map(struct adapter *adapter)
4804 {
4805 u32 pfmap;
4806
4807 if (t4_use_ldst(adapter))
4808 t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1);
4809 else
4810 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4811 &pfmap, 1, TP_RSS_PF_MAP_A);
4812 return pfmap;
4813 }
4814
4815 /**
4816 * t4_read_rss_pf_mask - read PF RSS Mask
4817 * @adapter: the adapter
4818 *
4819 * Reads the PF RSS Mask register and returns its value.
4820 */
4821 u32 t4_read_rss_pf_mask(struct adapter *adapter)
4822 {
4823 u32 pfmask;
4824
4825 if (t4_use_ldst(adapter))
4826 t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1);
4827 else
4828 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4829 &pfmask, 1, TP_RSS_PF_MSK_A);
4830 return pfmask;
4831 }
4832
4833 /**
4834 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
4835 * @adap: the adapter
4836 * @v4: holds the TCP/IP counter values
4837 * @v6: holds the TCP/IPv6 counter values
4838 *
4839 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
4840 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
4841 */
4842 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
4843 struct tp_tcp_stats *v6)
4844 {
4845 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
4846
4847 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
4848 #define STAT(x) val[STAT_IDX(x)]
4849 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
4850
4851 if (v4) {
4852 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4853 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A);
4854 v4->tcp_out_rsts = STAT(OUT_RST);
4855 v4->tcp_in_segs = STAT64(IN_SEG);
4856 v4->tcp_out_segs = STAT64(OUT_SEG);
4857 v4->tcp_retrans_segs = STAT64(RXT_SEG);
4858 }
4859 if (v6) {
4860 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4861 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A);
4862 v6->tcp_out_rsts = STAT(OUT_RST);
4863 v6->tcp_in_segs = STAT64(IN_SEG);
4864 v6->tcp_out_segs = STAT64(OUT_SEG);
4865 v6->tcp_retrans_segs = STAT64(RXT_SEG);
4866 }
4867 #undef STAT64
4868 #undef STAT
4869 #undef STAT_IDX
4870 }
4871
4872 /**
4873 * t4_tp_get_err_stats - read TP's error MIB counters
4874 * @adap: the adapter
4875 * @st: holds the counter values
4876 *
4877 * Returns the values of TP's error counters.
4878 */
4879 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
4880 {
4881 int nchan = adap->params.arch.nchan;
4882
4883 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4884 st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A);
4885 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4886 st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A);
4887 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4888 st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A);
4889 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4890 st->tnl_cong_drops, nchan, TP_MIB_TNL_CNG_DROP_0_A);
4891 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4892 st->ofld_chan_drops, nchan, TP_MIB_OFD_CHN_DROP_0_A);
4893 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4894 st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A);
4895 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4896 st->ofld_vlan_drops, nchan, TP_MIB_OFD_VLN_DROP_0_A);
4897 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4898 st->tcp6_in_errs, nchan, TP_MIB_TCP_V6IN_ERR_0_A);
4899
4900 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4901 &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A);
4902 }
4903
4904 /**
4905 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
4906 * @adap: the adapter
4907 * @st: holds the counter values
4908 *
4909 * Returns the values of TP's CPL counters.
4910 */
4911 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
4912 {
4913 int nchan = adap->params.arch.nchan;
4914
4915 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req,
4916 nchan, TP_MIB_CPL_IN_REQ_0_A);
4917 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp,
4918 nchan, TP_MIB_CPL_OUT_RSP_0_A);
4919
4920 }
4921
4922 /**
4923 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
4924 * @adap: the adapter
4925 * @st: holds the counter values
4926 *
4927 * Returns the values of TP's RDMA counters.
4928 */
4929 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
4930 {
4931 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt,
4932 2, TP_MIB_RQE_DFR_PKT_A);
4933 }
4934
4935 /**
4936 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
4937 * @adap: the adapter
4938 * @idx: the port index
4939 * @st: holds the counter values
4940 *
4941 * Returns the values of TP's FCoE counters for the selected port.
4942 */
4943 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
4944 struct tp_fcoe_stats *st)
4945 {
4946 u32 val[2];
4947
4948 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp,
4949 1, TP_MIB_FCOE_DDP_0_A + idx);
4950 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop,
4951 1, TP_MIB_FCOE_DROP_0_A + idx);
4952 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4953 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx);
4954 st->octets_ddp = ((u64)val[0] << 32) | val[1];
4955 }
4956
4957 /**
4958 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
4959 * @adap: the adapter
4960 * @st: holds the counter values
4961 *
4962 * Returns the values of TP's counters for non-TCP directly-placed packets.
4963 */
4964 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
4965 {
4966 u32 val[4];
4967
4968 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4,
4969 TP_MIB_USM_PKTS_A);
4970 st->frames = val[0];
4971 st->drops = val[1];
4972 st->octets = ((u64)val[2] << 32) | val[3];
4973 }
4974
4975 /**
4976 * t4_read_mtu_tbl - returns the values in the HW path MTU table
4977 * @adap: the adapter
4978 * @mtus: where to store the MTU values
4979 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
4980 *
4981 * Reads the HW path MTU table.
4982 */
4983 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
4984 {
4985 u32 v;
4986 int i;
4987
4988 for (i = 0; i < NMTUS; ++i) {
4989 t4_write_reg(adap, TP_MTU_TABLE_A,
4990 MTUINDEX_V(0xff) | MTUVALUE_V(i));
4991 v = t4_read_reg(adap, TP_MTU_TABLE_A);
4992 mtus[i] = MTUVALUE_G(v);
4993 if (mtu_log)
4994 mtu_log[i] = MTUWIDTH_G(v);
4995 }
4996 }
4997
4998 /**
4999 * t4_read_cong_tbl - reads the congestion control table
5000 * @adap: the adapter
5001 * @incr: where to store the alpha values
5002 *
5003 * Reads the additive increments programmed into the HW congestion
5004 * control table.
5005 */
5006 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5007 {
5008 unsigned int mtu, w;
5009
5010 for (mtu = 0; mtu < NMTUS; ++mtu)
5011 for (w = 0; w < NCCTRL_WIN; ++w) {
5012 t4_write_reg(adap, TP_CCTRL_TABLE_A,
5013 ROWINDEX_V(0xffff) | (mtu << 5) | w);
5014 incr[mtu][w] = (u16)t4_read_reg(adap,
5015 TP_CCTRL_TABLE_A) & 0x1fff;
5016 }
5017 }
5018
5019 /**
5020 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5021 * @adap: the adapter
5022 * @addr: the indirect TP register address
5023 * @mask: specifies the field within the register to modify
5024 * @val: new value for the field
5025 *
5026 * Sets a field of an indirect TP register to the given value.
5027 */
5028 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5029 unsigned int mask, unsigned int val)
5030 {
5031 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5032 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5033 t4_write_reg(adap, TP_PIO_DATA_A, val);
5034 }
5035
5036 /**
5037 * init_cong_ctrl - initialize congestion control parameters
5038 * @a: the alpha values for congestion control
5039 * @b: the beta values for congestion control
5040 *
5041 * Initialize the congestion control parameters.
5042 */
5043 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5044 {
5045 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5046 a[9] = 2;
5047 a[10] = 3;
5048 a[11] = 4;
5049 a[12] = 5;
5050 a[13] = 6;
5051 a[14] = 7;
5052 a[15] = 8;
5053 a[16] = 9;
5054 a[17] = 10;
5055 a[18] = 14;
5056 a[19] = 17;
5057 a[20] = 21;
5058 a[21] = 25;
5059 a[22] = 30;
5060 a[23] = 35;
5061 a[24] = 45;
5062 a[25] = 60;
5063 a[26] = 80;
5064 a[27] = 100;
5065 a[28] = 200;
5066 a[29] = 300;
5067 a[30] = 400;
5068 a[31] = 500;
5069
5070 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5071 b[9] = b[10] = 1;
5072 b[11] = b[12] = 2;
5073 b[13] = b[14] = b[15] = b[16] = 3;
5074 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5075 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5076 b[28] = b[29] = 6;
5077 b[30] = b[31] = 7;
5078 }
5079
5080 /* The minimum additive increment value for the congestion control table */
5081 #define CC_MIN_INCR 2U
5082
5083 /**
5084 * t4_load_mtus - write the MTU and congestion control HW tables
5085 * @adap: the adapter
5086 * @mtus: the values for the MTU table
5087 * @alpha: the values for the congestion control alpha parameter
5088 * @beta: the values for the congestion control beta parameter
5089 *
5090 * Write the HW MTU table with the supplied MTUs and the high-speed
5091 * congestion control table with the supplied alpha, beta, and MTUs.
5092 * We write the two tables together because the additive increments
5093 * depend on the MTUs.
5094 */
5095 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5096 const unsigned short *alpha, const unsigned short *beta)
5097 {
5098 static const unsigned int avg_pkts[NCCTRL_WIN] = {
5099 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5100 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5101 28672, 40960, 57344, 81920, 114688, 163840, 229376
5102 };
5103
5104 unsigned int i, w;
5105
5106 for (i = 0; i < NMTUS; ++i) {
5107 unsigned int mtu = mtus[i];
5108 unsigned int log2 = fls(mtu);
5109
5110 if (!(mtu & ((1 << log2) >> 2))) /* round */
5111 log2--;
5112 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5113 MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5114
5115 for (w = 0; w < NCCTRL_WIN; ++w) {
5116 unsigned int inc;
5117
5118 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5119 CC_MIN_INCR);
5120
5121 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5122 (w << 16) | (beta[w] << 13) | inc);
5123 }
5124 }
5125 }
5126
5127 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5128 * clocks. The formula is
5129 *
5130 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5131 *
5132 * which is equivalent to
5133 *
5134 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5135 */
5136 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5137 {
5138 u64 v = bytes256 * adap->params.vpd.cclk;
5139
5140 return v * 62 + v / 2;
5141 }
5142
5143 /**
5144 * t4_get_chan_txrate - get the current per channel Tx rates
5145 * @adap: the adapter
5146 * @nic_rate: rates for NIC traffic
5147 * @ofld_rate: rates for offloaded traffic
5148 *
5149 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5150 * for each channel.
5151 */
5152 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5153 {
5154 u32 v;
5155
5156 v = t4_read_reg(adap, TP_TX_TRATE_A);
5157 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5158 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5159 if (adap->params.arch.nchan == NCHAN) {
5160 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5161 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5162 }
5163
5164 v = t4_read_reg(adap, TP_TX_ORATE_A);
5165 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5166 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5167 if (adap->params.arch.nchan == NCHAN) {
5168 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5169 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5170 }
5171 }
5172
5173 /**
5174 * t4_set_trace_filter - configure one of the tracing filters
5175 * @adap: the adapter
5176 * @tp: the desired trace filter parameters
5177 * @idx: which filter to configure
5178 * @enable: whether to enable or disable the filter
5179 *
5180 * Configures one of the tracing filters available in HW. If @enable is
5181 * %0 @tp is not examined and may be %NULL. The user is responsible to
5182 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5183 */
5184 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5185 int idx, int enable)
5186 {
5187 int i, ofst = idx * 4;
5188 u32 data_reg, mask_reg, cfg;
5189 u32 multitrc = TRCMULTIFILTER_F;
5190
5191 if (!enable) {
5192 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5193 return 0;
5194 }
5195
5196 cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5197 if (cfg & TRCMULTIFILTER_F) {
5198 /* If multiple tracers are enabled, then maximum
5199 * capture size is 2.5KB (FIFO size of a single channel)
5200 * minus 2 flits for CPL_TRACE_PKT header.
5201 */
5202 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5203 return -EINVAL;
5204 } else {
5205 /* If multiple tracers are disabled, to avoid deadlocks
5206 * maximum packet capture size of 9600 bytes is recommended.
5207 * Also in this mode, only trace0 can be enabled and running.
5208 */
5209 multitrc = 0;
5210 if (tp->snap_len > 9600 || idx)
5211 return -EINVAL;
5212 }
5213
5214 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5215 tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5216 tp->min_len > TFMINPKTSIZE_M)
5217 return -EINVAL;
5218
5219 /* stop the tracer we'll be changing */
5220 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5221
5222 idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5223 data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5224 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5225
5226 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5227 t4_write_reg(adap, data_reg, tp->data[i]);
5228 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5229 }
5230 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5231 TFCAPTUREMAX_V(tp->snap_len) |
5232 TFMINPKTSIZE_V(tp->min_len));
5233 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5234 TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5235 (is_t4(adap->params.chip) ?
5236 TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5237 T5_TFPORT_V(tp->port) | T5_TFEN_F |
5238 T5_TFINVERTMATCH_V(tp->invert)));
5239
5240 return 0;
5241 }
5242
5243 /**
5244 * t4_get_trace_filter - query one of the tracing filters
5245 * @adap: the adapter
5246 * @tp: the current trace filter parameters
5247 * @idx: which trace filter to query
5248 * @enabled: non-zero if the filter is enabled
5249 *
5250 * Returns the current settings of one of the HW tracing filters.
5251 */
5252 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5253 int *enabled)
5254 {
5255 u32 ctla, ctlb;
5256 int i, ofst = idx * 4;
5257 u32 data_reg, mask_reg;
5258
5259 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5260 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5261
5262 if (is_t4(adap->params.chip)) {
5263 *enabled = !!(ctla & TFEN_F);
5264 tp->port = TFPORT_G(ctla);
5265 tp->invert = !!(ctla & TFINVERTMATCH_F);
5266 } else {
5267 *enabled = !!(ctla & T5_TFEN_F);
5268 tp->port = T5_TFPORT_G(ctla);
5269 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5270 }
5271 tp->snap_len = TFCAPTUREMAX_G(ctlb);
5272 tp->min_len = TFMINPKTSIZE_G(ctlb);
5273 tp->skip_ofst = TFOFFSET_G(ctla);
5274 tp->skip_len = TFLENGTH_G(ctla);
5275
5276 ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5277 data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5278 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5279
5280 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5281 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5282 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5283 }
5284 }
5285
5286 /**
5287 * t4_pmtx_get_stats - returns the HW stats from PMTX
5288 * @adap: the adapter
5289 * @cnt: where to store the count statistics
5290 * @cycles: where to store the cycle statistics
5291 *
5292 * Returns performance statistics from PMTX.
5293 */
5294 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5295 {
5296 int i;
5297 u32 data[2];
5298
5299 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5300 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5301 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5302 if (is_t4(adap->params.chip)) {
5303 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5304 } else {
5305 t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5306 PM_TX_DBG_DATA_A, data, 2,
5307 PM_TX_DBG_STAT_MSB_A);
5308 cycles[i] = (((u64)data[0] << 32) | data[1]);
5309 }
5310 }
5311 }
5312
5313 /**
5314 * t4_pmrx_get_stats - returns the HW stats from PMRX
5315 * @adap: the adapter
5316 * @cnt: where to store the count statistics
5317 * @cycles: where to store the cycle statistics
5318 *
5319 * Returns performance statistics from PMRX.
5320 */
5321 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5322 {
5323 int i;
5324 u32 data[2];
5325
5326 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5327 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5328 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5329 if (is_t4(adap->params.chip)) {
5330 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5331 } else {
5332 t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5333 PM_RX_DBG_DATA_A, data, 2,
5334 PM_RX_DBG_STAT_MSB_A);
5335 cycles[i] = (((u64)data[0] << 32) | data[1]);
5336 }
5337 }
5338 }
5339
5340 /**
5341 * t4_get_mps_bg_map - return the buffer groups associated with a port
5342 * @adap: the adapter
5343 * @idx: the port index
5344 *
5345 * Returns a bitmap indicating which MPS buffer groups are associated
5346 * with the given port. Bit i is set if buffer group i is used by the
5347 * port.
5348 */
5349 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
5350 {
5351 u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
5352
5353 if (n == 0)
5354 return idx == 0 ? 0xf : 0;
5355 /* In T6 (which is a 2 port card),
5356 * port 0 is mapped to channel 0 and port 1 is mapped to channel 1.
5357 * For 2 port T4/T5 adapter,
5358 * port 0 is mapped to channel 0 and 1,
5359 * port 1 is mapped to channel 2 and 3.
5360 */
5361 if ((n == 1) &&
5362 (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
5363 return idx < 2 ? (3 << (2 * idx)) : 0;
5364 return 1 << idx;
5365 }
5366
5367 /**
5368 * t4_get_port_type_description - return Port Type string description
5369 * @port_type: firmware Port Type enumeration
5370 */
5371 const char *t4_get_port_type_description(enum fw_port_type port_type)
5372 {
5373 static const char *const port_type_description[] = {
5374 "R XFI",
5375 "R XAUI",
5376 "T SGMII",
5377 "T XFI",
5378 "T XAUI",
5379 "KX4",
5380 "CX4",
5381 "KX",
5382 "KR",
5383 "R SFP+",
5384 "KR/KX",
5385 "KR/KX/KX4",
5386 "R QSFP_10G",
5387 "R QSA",
5388 "R QSFP",
5389 "R BP40_BA",
5390 };
5391
5392 if (port_type < ARRAY_SIZE(port_type_description))
5393 return port_type_description[port_type];
5394 return "UNKNOWN";
5395 }
5396
5397 /**
5398 * t4_get_port_stats_offset - collect port stats relative to a previous
5399 * snapshot
5400 * @adap: The adapter
5401 * @idx: The port
5402 * @stats: Current stats to fill
5403 * @offset: Previous stats snapshot
5404 */
5405 void t4_get_port_stats_offset(struct adapter *adap, int idx,
5406 struct port_stats *stats,
5407 struct port_stats *offset)
5408 {
5409 u64 *s, *o;
5410 int i;
5411
5412 t4_get_port_stats(adap, idx, stats);
5413 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
5414 i < (sizeof(struct port_stats) / sizeof(u64));
5415 i++, s++, o++)
5416 *s -= *o;
5417 }
5418
5419 /**
5420 * t4_get_port_stats - collect port statistics
5421 * @adap: the adapter
5422 * @idx: the port index
5423 * @p: the stats structure to fill
5424 *
5425 * Collect statistics related to the given port from HW.
5426 */
5427 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5428 {
5429 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5430
5431 #define GET_STAT(name) \
5432 t4_read_reg64(adap, \
5433 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
5434 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
5435 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5436
5437 p->tx_octets = GET_STAT(TX_PORT_BYTES);
5438 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
5439 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
5440 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
5441 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
5442 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
5443 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
5444 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
5445 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
5446 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
5447 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
5448 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
5449 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
5450 p->tx_drop = GET_STAT(TX_PORT_DROP);
5451 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
5452 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
5453 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
5454 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
5455 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
5456 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
5457 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
5458 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
5459 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
5460
5461 p->rx_octets = GET_STAT(RX_PORT_BYTES);
5462 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
5463 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
5464 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
5465 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
5466 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
5467 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
5468 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
5469 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
5470 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
5471 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
5472 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
5473 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
5474 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
5475 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
5476 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
5477 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
5478 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
5479 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
5480 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
5481 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
5482 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
5483 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
5484 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
5485 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
5486 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
5487 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
5488
5489 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
5490 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
5491 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
5492 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
5493 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
5494 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
5495 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
5496 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
5497
5498 #undef GET_STAT
5499 #undef GET_STAT_COM
5500 }
5501
5502 /**
5503 * t4_get_lb_stats - collect loopback port statistics
5504 * @adap: the adapter
5505 * @idx: the loopback port index
5506 * @p: the stats structure to fill
5507 *
5508 * Return HW statistics for the given loopback port.
5509 */
5510 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
5511 {
5512 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5513
5514 #define GET_STAT(name) \
5515 t4_read_reg64(adap, \
5516 (is_t4(adap->params.chip) ? \
5517 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
5518 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
5519 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5520
5521 p->octets = GET_STAT(BYTES);
5522 p->frames = GET_STAT(FRAMES);
5523 p->bcast_frames = GET_STAT(BCAST);
5524 p->mcast_frames = GET_STAT(MCAST);
5525 p->ucast_frames = GET_STAT(UCAST);
5526 p->error_frames = GET_STAT(ERROR);
5527
5528 p->frames_64 = GET_STAT(64B);
5529 p->frames_65_127 = GET_STAT(65B_127B);
5530 p->frames_128_255 = GET_STAT(128B_255B);
5531 p->frames_256_511 = GET_STAT(256B_511B);
5532 p->frames_512_1023 = GET_STAT(512B_1023B);
5533 p->frames_1024_1518 = GET_STAT(1024B_1518B);
5534 p->frames_1519_max = GET_STAT(1519B_MAX);
5535 p->drop = GET_STAT(DROP_FRAMES);
5536
5537 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
5538 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
5539 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
5540 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
5541 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
5542 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
5543 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
5544 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
5545
5546 #undef GET_STAT
5547 #undef GET_STAT_COM
5548 }
5549
5550 /* t4_mk_filtdelwr - create a delete filter WR
5551 * @ftid: the filter ID
5552 * @wr: the filter work request to populate
5553 * @qid: ingress queue to receive the delete notification
5554 *
5555 * Creates a filter work request to delete the supplied filter. If @qid is
5556 * negative the delete notification is suppressed.
5557 */
5558 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
5559 {
5560 memset(wr, 0, sizeof(*wr));
5561 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
5562 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
5563 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
5564 FW_FILTER_WR_NOREPLY_V(qid < 0));
5565 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
5566 if (qid >= 0)
5567 wr->rx_chan_rx_rpl_iq =
5568 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
5569 }
5570
5571 #define INIT_CMD(var, cmd, rd_wr) do { \
5572 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
5573 FW_CMD_REQUEST_F | \
5574 FW_CMD_##rd_wr##_F); \
5575 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
5576 } while (0)
5577
5578 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
5579 u32 addr, u32 val)
5580 {
5581 u32 ldst_addrspace;
5582 struct fw_ldst_cmd c;
5583
5584 memset(&c, 0, sizeof(c));
5585 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
5586 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5587 FW_CMD_REQUEST_F |
5588 FW_CMD_WRITE_F |
5589 ldst_addrspace);
5590 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5591 c.u.addrval.addr = cpu_to_be32(addr);
5592 c.u.addrval.val = cpu_to_be32(val);
5593
5594 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5595 }
5596
5597 /**
5598 * t4_mdio_rd - read a PHY register through MDIO
5599 * @adap: the adapter
5600 * @mbox: mailbox to use for the FW command
5601 * @phy_addr: the PHY address
5602 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5603 * @reg: the register to read
5604 * @valp: where to store the value
5605 *
5606 * Issues a FW command through the given mailbox to read a PHY register.
5607 */
5608 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5609 unsigned int mmd, unsigned int reg, u16 *valp)
5610 {
5611 int ret;
5612 u32 ldst_addrspace;
5613 struct fw_ldst_cmd c;
5614
5615 memset(&c, 0, sizeof(c));
5616 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5617 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5618 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5619 ldst_addrspace);
5620 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5621 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5622 FW_LDST_CMD_MMD_V(mmd));
5623 c.u.mdio.raddr = cpu_to_be16(reg);
5624
5625 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5626 if (ret == 0)
5627 *valp = be16_to_cpu(c.u.mdio.rval);
5628 return ret;
5629 }
5630
5631 /**
5632 * t4_mdio_wr - write a PHY register through MDIO
5633 * @adap: the adapter
5634 * @mbox: mailbox to use for the FW command
5635 * @phy_addr: the PHY address
5636 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5637 * @reg: the register to write
5638 * @valp: value to write
5639 *
5640 * Issues a FW command through the given mailbox to write a PHY register.
5641 */
5642 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5643 unsigned int mmd, unsigned int reg, u16 val)
5644 {
5645 u32 ldst_addrspace;
5646 struct fw_ldst_cmd c;
5647
5648 memset(&c, 0, sizeof(c));
5649 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5650 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5651 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5652 ldst_addrspace);
5653 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5654 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5655 FW_LDST_CMD_MMD_V(mmd));
5656 c.u.mdio.raddr = cpu_to_be16(reg);
5657 c.u.mdio.rval = cpu_to_be16(val);
5658
5659 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5660 }
5661
5662 /**
5663 * t4_sge_decode_idma_state - decode the idma state
5664 * @adap: the adapter
5665 * @state: the state idma is stuck in
5666 */
5667 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
5668 {
5669 static const char * const t4_decode[] = {
5670 "IDMA_IDLE",
5671 "IDMA_PUSH_MORE_CPL_FIFO",
5672 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5673 "Not used",
5674 "IDMA_PHYSADDR_SEND_PCIEHDR",
5675 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5676 "IDMA_PHYSADDR_SEND_PAYLOAD",
5677 "IDMA_SEND_FIFO_TO_IMSG",
5678 "IDMA_FL_REQ_DATA_FL_PREP",
5679 "IDMA_FL_REQ_DATA_FL",
5680 "IDMA_FL_DROP",
5681 "IDMA_FL_H_REQ_HEADER_FL",
5682 "IDMA_FL_H_SEND_PCIEHDR",
5683 "IDMA_FL_H_PUSH_CPL_FIFO",
5684 "IDMA_FL_H_SEND_CPL",
5685 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5686 "IDMA_FL_H_SEND_IP_HDR",
5687 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5688 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5689 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5690 "IDMA_FL_D_SEND_PCIEHDR",
5691 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5692 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5693 "IDMA_FL_SEND_PCIEHDR",
5694 "IDMA_FL_PUSH_CPL_FIFO",
5695 "IDMA_FL_SEND_CPL",
5696 "IDMA_FL_SEND_PAYLOAD_FIRST",
5697 "IDMA_FL_SEND_PAYLOAD",
5698 "IDMA_FL_REQ_NEXT_DATA_FL",
5699 "IDMA_FL_SEND_NEXT_PCIEHDR",
5700 "IDMA_FL_SEND_PADDING",
5701 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5702 "IDMA_FL_SEND_FIFO_TO_IMSG",
5703 "IDMA_FL_REQ_DATAFL_DONE",
5704 "IDMA_FL_REQ_HEADERFL_DONE",
5705 };
5706 static const char * const t5_decode[] = {
5707 "IDMA_IDLE",
5708 "IDMA_ALMOST_IDLE",
5709 "IDMA_PUSH_MORE_CPL_FIFO",
5710 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5711 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5712 "IDMA_PHYSADDR_SEND_PCIEHDR",
5713 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5714 "IDMA_PHYSADDR_SEND_PAYLOAD",
5715 "IDMA_SEND_FIFO_TO_IMSG",
5716 "IDMA_FL_REQ_DATA_FL",
5717 "IDMA_FL_DROP",
5718 "IDMA_FL_DROP_SEND_INC",
5719 "IDMA_FL_H_REQ_HEADER_FL",
5720 "IDMA_FL_H_SEND_PCIEHDR",
5721 "IDMA_FL_H_PUSH_CPL_FIFO",
5722 "IDMA_FL_H_SEND_CPL",
5723 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5724 "IDMA_FL_H_SEND_IP_HDR",
5725 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5726 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5727 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5728 "IDMA_FL_D_SEND_PCIEHDR",
5729 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5730 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5731 "IDMA_FL_SEND_PCIEHDR",
5732 "IDMA_FL_PUSH_CPL_FIFO",
5733 "IDMA_FL_SEND_CPL",
5734 "IDMA_FL_SEND_PAYLOAD_FIRST",
5735 "IDMA_FL_SEND_PAYLOAD",
5736 "IDMA_FL_REQ_NEXT_DATA_FL",
5737 "IDMA_FL_SEND_NEXT_PCIEHDR",
5738 "IDMA_FL_SEND_PADDING",
5739 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5740 };
5741 static const char * const t6_decode[] = {
5742 "IDMA_IDLE",
5743 "IDMA_PUSH_MORE_CPL_FIFO",
5744 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5745 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5746 "IDMA_PHYSADDR_SEND_PCIEHDR",
5747 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5748 "IDMA_PHYSADDR_SEND_PAYLOAD",
5749 "IDMA_FL_REQ_DATA_FL",
5750 "IDMA_FL_DROP",
5751 "IDMA_FL_DROP_SEND_INC",
5752 "IDMA_FL_H_REQ_HEADER_FL",
5753 "IDMA_FL_H_SEND_PCIEHDR",
5754 "IDMA_FL_H_PUSH_CPL_FIFO",
5755 "IDMA_FL_H_SEND_CPL",
5756 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5757 "IDMA_FL_H_SEND_IP_HDR",
5758 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5759 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5760 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5761 "IDMA_FL_D_SEND_PCIEHDR",
5762 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5763 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5764 "IDMA_FL_SEND_PCIEHDR",
5765 "IDMA_FL_PUSH_CPL_FIFO",
5766 "IDMA_FL_SEND_CPL",
5767 "IDMA_FL_SEND_PAYLOAD_FIRST",
5768 "IDMA_FL_SEND_PAYLOAD",
5769 "IDMA_FL_REQ_NEXT_DATA_FL",
5770 "IDMA_FL_SEND_NEXT_PCIEHDR",
5771 "IDMA_FL_SEND_PADDING",
5772 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5773 };
5774 static const u32 sge_regs[] = {
5775 SGE_DEBUG_DATA_LOW_INDEX_2_A,
5776 SGE_DEBUG_DATA_LOW_INDEX_3_A,
5777 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
5778 };
5779 const char **sge_idma_decode;
5780 int sge_idma_decode_nstates;
5781 int i;
5782 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
5783
5784 /* Select the right set of decode strings to dump depending on the
5785 * adapter chip type.
5786 */
5787 switch (chip_version) {
5788 case CHELSIO_T4:
5789 sge_idma_decode = (const char **)t4_decode;
5790 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5791 break;
5792
5793 case CHELSIO_T5:
5794 sge_idma_decode = (const char **)t5_decode;
5795 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5796 break;
5797
5798 case CHELSIO_T6:
5799 sge_idma_decode = (const char **)t6_decode;
5800 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
5801 break;
5802
5803 default:
5804 dev_err(adapter->pdev_dev,
5805 "Unsupported chip version %d\n", chip_version);
5806 return;
5807 }
5808
5809 if (is_t4(adapter->params.chip)) {
5810 sge_idma_decode = (const char **)t4_decode;
5811 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5812 } else {
5813 sge_idma_decode = (const char **)t5_decode;
5814 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5815 }
5816
5817 if (state < sge_idma_decode_nstates)
5818 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
5819 else
5820 CH_WARN(adapter, "idma state %d unknown\n", state);
5821
5822 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
5823 CH_WARN(adapter, "SGE register %#x value %#x\n",
5824 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
5825 }
5826
5827 /**
5828 * t4_sge_ctxt_flush - flush the SGE context cache
5829 * @adap: the adapter
5830 * @mbox: mailbox to use for the FW command
5831 *
5832 * Issues a FW command through the given mailbox to flush the
5833 * SGE context cache.
5834 */
5835 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
5836 {
5837 int ret;
5838 u32 ldst_addrspace;
5839 struct fw_ldst_cmd c;
5840
5841 memset(&c, 0, sizeof(c));
5842 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC);
5843 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5844 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5845 ldst_addrspace);
5846 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5847 c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
5848
5849 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5850 return ret;
5851 }
5852
5853 /**
5854 * t4_fw_hello - establish communication with FW
5855 * @adap: the adapter
5856 * @mbox: mailbox to use for the FW command
5857 * @evt_mbox: mailbox to receive async FW events
5858 * @master: specifies the caller's willingness to be the device master
5859 * @state: returns the current device state (if non-NULL)
5860 *
5861 * Issues a command to establish communication with FW. Returns either
5862 * an error (negative integer) or the mailbox of the Master PF.
5863 */
5864 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
5865 enum dev_master master, enum dev_state *state)
5866 {
5867 int ret;
5868 struct fw_hello_cmd c;
5869 u32 v;
5870 unsigned int master_mbox;
5871 int retries = FW_CMD_HELLO_RETRIES;
5872
5873 retry:
5874 memset(&c, 0, sizeof(c));
5875 INIT_CMD(c, HELLO, WRITE);
5876 c.err_to_clearinit = cpu_to_be32(
5877 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
5878 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
5879 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
5880 mbox : FW_HELLO_CMD_MBMASTER_M) |
5881 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
5882 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
5883 FW_HELLO_CMD_CLEARINIT_F);
5884
5885 /*
5886 * Issue the HELLO command to the firmware. If it's not successful
5887 * but indicates that we got a "busy" or "timeout" condition, retry
5888 * the HELLO until we exhaust our retry limit. If we do exceed our
5889 * retry limit, check to see if the firmware left us any error
5890 * information and report that if so.
5891 */
5892 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5893 if (ret < 0) {
5894 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
5895 goto retry;
5896 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
5897 t4_report_fw_error(adap);
5898 return ret;
5899 }
5900
5901 v = be32_to_cpu(c.err_to_clearinit);
5902 master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
5903 if (state) {
5904 if (v & FW_HELLO_CMD_ERR_F)
5905 *state = DEV_STATE_ERR;
5906 else if (v & FW_HELLO_CMD_INIT_F)
5907 *state = DEV_STATE_INIT;
5908 else
5909 *state = DEV_STATE_UNINIT;
5910 }
5911
5912 /*
5913 * If we're not the Master PF then we need to wait around for the
5914 * Master PF Driver to finish setting up the adapter.
5915 *
5916 * Note that we also do this wait if we're a non-Master-capable PF and
5917 * there is no current Master PF; a Master PF may show up momentarily
5918 * and we wouldn't want to fail pointlessly. (This can happen when an
5919 * OS loads lots of different drivers rapidly at the same time). In
5920 * this case, the Master PF returned by the firmware will be
5921 * PCIE_FW_MASTER_M so the test below will work ...
5922 */
5923 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
5924 master_mbox != mbox) {
5925 int waiting = FW_CMD_HELLO_TIMEOUT;
5926
5927 /*
5928 * Wait for the firmware to either indicate an error or
5929 * initialized state. If we see either of these we bail out
5930 * and report the issue to the caller. If we exhaust the
5931 * "hello timeout" and we haven't exhausted our retries, try
5932 * again. Otherwise bail with a timeout error.
5933 */
5934 for (;;) {
5935 u32 pcie_fw;
5936
5937 msleep(50);
5938 waiting -= 50;
5939
5940 /*
5941 * If neither Error nor Initialialized are indicated
5942 * by the firmware keep waiting till we exaust our
5943 * timeout ... and then retry if we haven't exhausted
5944 * our retries ...
5945 */
5946 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
5947 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
5948 if (waiting <= 0) {
5949 if (retries-- > 0)
5950 goto retry;
5951
5952 return -ETIMEDOUT;
5953 }
5954 continue;
5955 }
5956
5957 /*
5958 * We either have an Error or Initialized condition
5959 * report errors preferentially.
5960 */
5961 if (state) {
5962 if (pcie_fw & PCIE_FW_ERR_F)
5963 *state = DEV_STATE_ERR;
5964 else if (pcie_fw & PCIE_FW_INIT_F)
5965 *state = DEV_STATE_INIT;
5966 }
5967
5968 /*
5969 * If we arrived before a Master PF was selected and
5970 * there's not a valid Master PF, grab its identity
5971 * for our caller.
5972 */
5973 if (master_mbox == PCIE_FW_MASTER_M &&
5974 (pcie_fw & PCIE_FW_MASTER_VLD_F))
5975 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
5976 break;
5977 }
5978 }
5979
5980 return master_mbox;
5981 }
5982
5983 /**
5984 * t4_fw_bye - end communication with FW
5985 * @adap: the adapter
5986 * @mbox: mailbox to use for the FW command
5987 *
5988 * Issues a command to terminate communication with FW.
5989 */
5990 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
5991 {
5992 struct fw_bye_cmd c;
5993
5994 memset(&c, 0, sizeof(c));
5995 INIT_CMD(c, BYE, WRITE);
5996 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5997 }
5998
5999 /**
6000 * t4_init_cmd - ask FW to initialize the device
6001 * @adap: the adapter
6002 * @mbox: mailbox to use for the FW command
6003 *
6004 * Issues a command to FW to partially initialize the device. This
6005 * performs initialization that generally doesn't depend on user input.
6006 */
6007 int t4_early_init(struct adapter *adap, unsigned int mbox)
6008 {
6009 struct fw_initialize_cmd c;
6010
6011 memset(&c, 0, sizeof(c));
6012 INIT_CMD(c, INITIALIZE, WRITE);
6013 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6014 }
6015
6016 /**
6017 * t4_fw_reset - issue a reset to FW
6018 * @adap: the adapter
6019 * @mbox: mailbox to use for the FW command
6020 * @reset: specifies the type of reset to perform
6021 *
6022 * Issues a reset command of the specified type to FW.
6023 */
6024 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6025 {
6026 struct fw_reset_cmd c;
6027
6028 memset(&c, 0, sizeof(c));
6029 INIT_CMD(c, RESET, WRITE);
6030 c.val = cpu_to_be32(reset);
6031 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6032 }
6033
6034 /**
6035 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6036 * @adap: the adapter
6037 * @mbox: mailbox to use for the FW RESET command (if desired)
6038 * @force: force uP into RESET even if FW RESET command fails
6039 *
6040 * Issues a RESET command to firmware (if desired) with a HALT indication
6041 * and then puts the microprocessor into RESET state. The RESET command
6042 * will only be issued if a legitimate mailbox is provided (mbox <=
6043 * PCIE_FW_MASTER_M).
6044 *
6045 * This is generally used in order for the host to safely manipulate the
6046 * adapter without fear of conflicting with whatever the firmware might
6047 * be doing. The only way out of this state is to RESTART the firmware
6048 * ...
6049 */
6050 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6051 {
6052 int ret = 0;
6053
6054 /*
6055 * If a legitimate mailbox is provided, issue a RESET command
6056 * with a HALT indication.
6057 */
6058 if (mbox <= PCIE_FW_MASTER_M) {
6059 struct fw_reset_cmd c;
6060
6061 memset(&c, 0, sizeof(c));
6062 INIT_CMD(c, RESET, WRITE);
6063 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
6064 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
6065 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6066 }
6067
6068 /*
6069 * Normally we won't complete the operation if the firmware RESET
6070 * command fails but if our caller insists we'll go ahead and put the
6071 * uP into RESET. This can be useful if the firmware is hung or even
6072 * missing ... We'll have to take the risk of putting the uP into
6073 * RESET without the cooperation of firmware in that case.
6074 *
6075 * We also force the firmware's HALT flag to be on in case we bypassed
6076 * the firmware RESET command above or we're dealing with old firmware
6077 * which doesn't have the HALT capability. This will serve as a flag
6078 * for the incoming firmware to know that it's coming out of a HALT
6079 * rather than a RESET ... if it's new enough to understand that ...
6080 */
6081 if (ret == 0 || force) {
6082 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
6083 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
6084 PCIE_FW_HALT_F);
6085 }
6086
6087 /*
6088 * And we always return the result of the firmware RESET command
6089 * even when we force the uP into RESET ...
6090 */
6091 return ret;
6092 }
6093
6094 /**
6095 * t4_fw_restart - restart the firmware by taking the uP out of RESET
6096 * @adap: the adapter
6097 * @reset: if we want to do a RESET to restart things
6098 *
6099 * Restart firmware previously halted by t4_fw_halt(). On successful
6100 * return the previous PF Master remains as the new PF Master and there
6101 * is no need to issue a new HELLO command, etc.
6102 *
6103 * We do this in two ways:
6104 *
6105 * 1. If we're dealing with newer firmware we'll simply want to take
6106 * the chip's microprocessor out of RESET. This will cause the
6107 * firmware to start up from its start vector. And then we'll loop
6108 * until the firmware indicates it's started again (PCIE_FW.HALT
6109 * reset to 0) or we timeout.
6110 *
6111 * 2. If we're dealing with older firmware then we'll need to RESET
6112 * the chip since older firmware won't recognize the PCIE_FW.HALT
6113 * flag and automatically RESET itself on startup.
6114 */
6115 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6116 {
6117 if (reset) {
6118 /*
6119 * Since we're directing the RESET instead of the firmware
6120 * doing it automatically, we need to clear the PCIE_FW.HALT
6121 * bit.
6122 */
6123 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6124
6125 /*
6126 * If we've been given a valid mailbox, first try to get the
6127 * firmware to do the RESET. If that works, great and we can
6128 * return success. Otherwise, if we haven't been given a
6129 * valid mailbox or the RESET command failed, fall back to
6130 * hitting the chip with a hammer.
6131 */
6132 if (mbox <= PCIE_FW_MASTER_M) {
6133 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6134 msleep(100);
6135 if (t4_fw_reset(adap, mbox,
6136 PIORST_F | PIORSTMODE_F) == 0)
6137 return 0;
6138 }
6139
6140 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6141 msleep(2000);
6142 } else {
6143 int ms;
6144
6145 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6146 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6147 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6148 return 0;
6149 msleep(100);
6150 ms += 100;
6151 }
6152 return -ETIMEDOUT;
6153 }
6154 return 0;
6155 }
6156
6157 /**
6158 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6159 * @adap: the adapter
6160 * @mbox: mailbox to use for the FW RESET command (if desired)
6161 * @fw_data: the firmware image to write
6162 * @size: image size
6163 * @force: force upgrade even if firmware doesn't cooperate
6164 *
6165 * Perform all of the steps necessary for upgrading an adapter's
6166 * firmware image. Normally this requires the cooperation of the
6167 * existing firmware in order to halt all existing activities
6168 * but if an invalid mailbox token is passed in we skip that step
6169 * (though we'll still put the adapter microprocessor into RESET in
6170 * that case).
6171 *
6172 * On successful return the new firmware will have been loaded and
6173 * the adapter will have been fully RESET losing all previous setup
6174 * state. On unsuccessful return the adapter may be completely hosed ...
6175 * positive errno indicates that the adapter is ~probably~ intact, a
6176 * negative errno indicates that things are looking bad ...
6177 */
6178 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6179 const u8 *fw_data, unsigned int size, int force)
6180 {
6181 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6182 int reset, ret;
6183
6184 if (!t4_fw_matches_chip(adap, fw_hdr))
6185 return -EINVAL;
6186
6187 ret = t4_fw_halt(adap, mbox, force);
6188 if (ret < 0 && !force)
6189 return ret;
6190
6191 ret = t4_load_fw(adap, fw_data, size);
6192 if (ret < 0)
6193 return ret;
6194
6195 /*
6196 * Older versions of the firmware don't understand the new
6197 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6198 * restart. So for newly loaded older firmware we'll have to do the
6199 * RESET for it so it starts up on a clean slate. We can tell if
6200 * the newly loaded firmware will handle this right by checking
6201 * its header flags to see if it advertises the capability.
6202 */
6203 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6204 return t4_fw_restart(adap, mbox, reset);
6205 }
6206
6207 /**
6208 * t4_fl_pkt_align - return the fl packet alignment
6209 * @adap: the adapter
6210 *
6211 * T4 has a single field to specify the packing and padding boundary.
6212 * T5 onwards has separate fields for this and hence the alignment for
6213 * next packet offset is maximum of these two.
6214 *
6215 */
6216 int t4_fl_pkt_align(struct adapter *adap)
6217 {
6218 u32 sge_control, sge_control2;
6219 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
6220
6221 sge_control = t4_read_reg(adap, SGE_CONTROL_A);
6222
6223 /* T4 uses a single control field to specify both the PCIe Padding and
6224 * Packing Boundary. T5 introduced the ability to specify these
6225 * separately. The actual Ingress Packet Data alignment boundary
6226 * within Packed Buffer Mode is the maximum of these two
6227 * specifications. (Note that it makes no real practical sense to
6228 * have the Pading Boudary be larger than the Packing Boundary but you
6229 * could set the chip up that way and, in fact, legacy T4 code would
6230 * end doing this because it would initialize the Padding Boundary and
6231 * leave the Packing Boundary initialized to 0 (16 bytes).)
6232 * Padding Boundary values in T6 starts from 8B,
6233 * where as it is 32B for T4 and T5.
6234 */
6235 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
6236 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
6237 else
6238 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
6239
6240 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
6241
6242 fl_align = ingpadboundary;
6243 if (!is_t4(adap->params.chip)) {
6244 /* T5 has a weird interpretation of one of the PCIe Packing
6245 * Boundary values. No idea why ...
6246 */
6247 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
6248 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
6249 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
6250 ingpackboundary = 16;
6251 else
6252 ingpackboundary = 1 << (ingpackboundary +
6253 INGPACKBOUNDARY_SHIFT_X);
6254
6255 fl_align = max(ingpadboundary, ingpackboundary);
6256 }
6257 return fl_align;
6258 }
6259
6260 /**
6261 * t4_fixup_host_params - fix up host-dependent parameters
6262 * @adap: the adapter
6263 * @page_size: the host's Base Page Size
6264 * @cache_line_size: the host's Cache Line Size
6265 *
6266 * Various registers in T4 contain values which are dependent on the
6267 * host's Base Page and Cache Line Sizes. This function will fix all of
6268 * those registers with the appropriate values as passed in ...
6269 */
6270 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
6271 unsigned int cache_line_size)
6272 {
6273 unsigned int page_shift = fls(page_size) - 1;
6274 unsigned int sge_hps = page_shift - 10;
6275 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
6276 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
6277 unsigned int fl_align_log = fls(fl_align) - 1;
6278 unsigned int ingpad;
6279
6280 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
6281 HOSTPAGESIZEPF0_V(sge_hps) |
6282 HOSTPAGESIZEPF1_V(sge_hps) |
6283 HOSTPAGESIZEPF2_V(sge_hps) |
6284 HOSTPAGESIZEPF3_V(sge_hps) |
6285 HOSTPAGESIZEPF4_V(sge_hps) |
6286 HOSTPAGESIZEPF5_V(sge_hps) |
6287 HOSTPAGESIZEPF6_V(sge_hps) |
6288 HOSTPAGESIZEPF7_V(sge_hps));
6289
6290 if (is_t4(adap->params.chip)) {
6291 t4_set_reg_field(adap, SGE_CONTROL_A,
6292 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6293 EGRSTATUSPAGESIZE_F,
6294 INGPADBOUNDARY_V(fl_align_log -
6295 INGPADBOUNDARY_SHIFT_X) |
6296 EGRSTATUSPAGESIZE_V(stat_len != 64));
6297 } else {
6298 /* T5 introduced the separation of the Free List Padding and
6299 * Packing Boundaries. Thus, we can select a smaller Padding
6300 * Boundary to avoid uselessly chewing up PCIe Link and Memory
6301 * Bandwidth, and use a Packing Boundary which is large enough
6302 * to avoid false sharing between CPUs, etc.
6303 *
6304 * For the PCI Link, the smaller the Padding Boundary the
6305 * better. For the Memory Controller, a smaller Padding
6306 * Boundary is better until we cross under the Memory Line
6307 * Size (the minimum unit of transfer to/from Memory). If we
6308 * have a Padding Boundary which is smaller than the Memory
6309 * Line Size, that'll involve a Read-Modify-Write cycle on the
6310 * Memory Controller which is never good. For T5 the smallest
6311 * Padding Boundary which we can select is 32 bytes which is
6312 * larger than any known Memory Controller Line Size so we'll
6313 * use that.
6314 *
6315 * T5 has a different interpretation of the "0" value for the
6316 * Packing Boundary. This corresponds to 16 bytes instead of
6317 * the expected 32 bytes. We never have a Packing Boundary
6318 * less than 32 bytes so we can't use that special value but
6319 * on the other hand, if we wanted 32 bytes, the best we can
6320 * really do is 64 bytes.
6321 */
6322 if (fl_align <= 32) {
6323 fl_align = 64;
6324 fl_align_log = 6;
6325 }
6326
6327 if (is_t5(adap->params.chip))
6328 ingpad = INGPCIEBOUNDARY_32B_X;
6329 else
6330 ingpad = T6_INGPADBOUNDARY_32B_X;
6331
6332 t4_set_reg_field(adap, SGE_CONTROL_A,
6333 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6334 EGRSTATUSPAGESIZE_F,
6335 INGPADBOUNDARY_V(ingpad) |
6336 EGRSTATUSPAGESIZE_V(stat_len != 64));
6337 t4_set_reg_field(adap, SGE_CONTROL2_A,
6338 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
6339 INGPACKBOUNDARY_V(fl_align_log -
6340 INGPACKBOUNDARY_SHIFT_X));
6341 }
6342 /*
6343 * Adjust various SGE Free List Host Buffer Sizes.
6344 *
6345 * This is something of a crock since we're using fixed indices into
6346 * the array which are also known by the sge.c code and the T4
6347 * Firmware Configuration File. We need to come up with a much better
6348 * approach to managing this array. For now, the first four entries
6349 * are:
6350 *
6351 * 0: Host Page Size
6352 * 1: 64KB
6353 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
6354 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
6355 *
6356 * For the single-MTU buffers in unpacked mode we need to include
6357 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
6358 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
6359 * Padding boundary. All of these are accommodated in the Factory
6360 * Default Firmware Configuration File but we need to adjust it for
6361 * this host's cache line size.
6362 */
6363 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
6364 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
6365 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
6366 & ~(fl_align-1));
6367 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
6368 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
6369 & ~(fl_align-1));
6370
6371 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
6372
6373 return 0;
6374 }
6375
6376 /**
6377 * t4_fw_initialize - ask FW to initialize the device
6378 * @adap: the adapter
6379 * @mbox: mailbox to use for the FW command
6380 *
6381 * Issues a command to FW to partially initialize the device. This
6382 * performs initialization that generally doesn't depend on user input.
6383 */
6384 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
6385 {
6386 struct fw_initialize_cmd c;
6387
6388 memset(&c, 0, sizeof(c));
6389 INIT_CMD(c, INITIALIZE, WRITE);
6390 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6391 }
6392
6393 /**
6394 * t4_query_params_rw - query FW or device parameters
6395 * @adap: the adapter
6396 * @mbox: mailbox to use for the FW command
6397 * @pf: the PF
6398 * @vf: the VF
6399 * @nparams: the number of parameters
6400 * @params: the parameter names
6401 * @val: the parameter values
6402 * @rw: Write and read flag
6403 *
6404 * Reads the value of FW or device parameters. Up to 7 parameters can be
6405 * queried at once.
6406 */
6407 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
6408 unsigned int vf, unsigned int nparams, const u32 *params,
6409 u32 *val, int rw)
6410 {
6411 int i, ret;
6412 struct fw_params_cmd c;
6413 __be32 *p = &c.param[0].mnem;
6414
6415 if (nparams > 7)
6416 return -EINVAL;
6417
6418 memset(&c, 0, sizeof(c));
6419 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6420 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6421 FW_PARAMS_CMD_PFN_V(pf) |
6422 FW_PARAMS_CMD_VFN_V(vf));
6423 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6424
6425 for (i = 0; i < nparams; i++) {
6426 *p++ = cpu_to_be32(*params++);
6427 if (rw)
6428 *p = cpu_to_be32(*(val + i));
6429 p++;
6430 }
6431
6432 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6433 if (ret == 0)
6434 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
6435 *val++ = be32_to_cpu(*p);
6436 return ret;
6437 }
6438
6439 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6440 unsigned int vf, unsigned int nparams, const u32 *params,
6441 u32 *val)
6442 {
6443 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
6444 }
6445
6446 /**
6447 * t4_set_params_timeout - sets FW or device parameters
6448 * @adap: the adapter
6449 * @mbox: mailbox to use for the FW command
6450 * @pf: the PF
6451 * @vf: the VF
6452 * @nparams: the number of parameters
6453 * @params: the parameter names
6454 * @val: the parameter values
6455 * @timeout: the timeout time
6456 *
6457 * Sets the value of FW or device parameters. Up to 7 parameters can be
6458 * specified at once.
6459 */
6460 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
6461 unsigned int pf, unsigned int vf,
6462 unsigned int nparams, const u32 *params,
6463 const u32 *val, int timeout)
6464 {
6465 struct fw_params_cmd c;
6466 __be32 *p = &c.param[0].mnem;
6467
6468 if (nparams > 7)
6469 return -EINVAL;
6470
6471 memset(&c, 0, sizeof(c));
6472 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6473 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6474 FW_PARAMS_CMD_PFN_V(pf) |
6475 FW_PARAMS_CMD_VFN_V(vf));
6476 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6477
6478 while (nparams--) {
6479 *p++ = cpu_to_be32(*params++);
6480 *p++ = cpu_to_be32(*val++);
6481 }
6482
6483 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
6484 }
6485
6486 /**
6487 * t4_set_params - sets FW or device parameters
6488 * @adap: the adapter
6489 * @mbox: mailbox to use for the FW command
6490 * @pf: the PF
6491 * @vf: the VF
6492 * @nparams: the number of parameters
6493 * @params: the parameter names
6494 * @val: the parameter values
6495 *
6496 * Sets the value of FW or device parameters. Up to 7 parameters can be
6497 * specified at once.
6498 */
6499 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6500 unsigned int vf, unsigned int nparams, const u32 *params,
6501 const u32 *val)
6502 {
6503 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
6504 FW_CMD_MAX_TIMEOUT);
6505 }
6506
6507 /**
6508 * t4_cfg_pfvf - configure PF/VF resource limits
6509 * @adap: the adapter
6510 * @mbox: mailbox to use for the FW command
6511 * @pf: the PF being configured
6512 * @vf: the VF being configured
6513 * @txq: the max number of egress queues
6514 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
6515 * @rxqi: the max number of interrupt-capable ingress queues
6516 * @rxq: the max number of interruptless ingress queues
6517 * @tc: the PCI traffic class
6518 * @vi: the max number of virtual interfaces
6519 * @cmask: the channel access rights mask for the PF/VF
6520 * @pmask: the port access rights mask for the PF/VF
6521 * @nexact: the maximum number of exact MPS filters
6522 * @rcaps: read capabilities
6523 * @wxcaps: write/execute capabilities
6524 *
6525 * Configures resource limits and capabilities for a physical or virtual
6526 * function.
6527 */
6528 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
6529 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
6530 unsigned int rxqi, unsigned int rxq, unsigned int tc,
6531 unsigned int vi, unsigned int cmask, unsigned int pmask,
6532 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
6533 {
6534 struct fw_pfvf_cmd c;
6535
6536 memset(&c, 0, sizeof(c));
6537 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
6538 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
6539 FW_PFVF_CMD_VFN_V(vf));
6540 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6541 c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
6542 FW_PFVF_CMD_NIQ_V(rxq));
6543 c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
6544 FW_PFVF_CMD_PMASK_V(pmask) |
6545 FW_PFVF_CMD_NEQ_V(txq));
6546 c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
6547 FW_PFVF_CMD_NVI_V(vi) |
6548 FW_PFVF_CMD_NEXACTF_V(nexact));
6549 c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
6550 FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
6551 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
6552 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6553 }
6554
6555 /**
6556 * t4_alloc_vi - allocate a virtual interface
6557 * @adap: the adapter
6558 * @mbox: mailbox to use for the FW command
6559 * @port: physical port associated with the VI
6560 * @pf: the PF owning the VI
6561 * @vf: the VF owning the VI
6562 * @nmac: number of MAC addresses needed (1 to 5)
6563 * @mac: the MAC addresses of the VI
6564 * @rss_size: size of RSS table slice associated with this VI
6565 *
6566 * Allocates a virtual interface for the given physical port. If @mac is
6567 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
6568 * @mac should be large enough to hold @nmac Ethernet addresses, they are
6569 * stored consecutively so the space needed is @nmac * 6 bytes.
6570 * Returns a negative error number or the non-negative VI id.
6571 */
6572 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
6573 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
6574 unsigned int *rss_size)
6575 {
6576 int ret;
6577 struct fw_vi_cmd c;
6578
6579 memset(&c, 0, sizeof(c));
6580 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
6581 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
6582 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
6583 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
6584 c.portid_pkd = FW_VI_CMD_PORTID_V(port);
6585 c.nmac = nmac - 1;
6586
6587 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6588 if (ret)
6589 return ret;
6590
6591 if (mac) {
6592 memcpy(mac, c.mac, sizeof(c.mac));
6593 switch (nmac) {
6594 case 5:
6595 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
6596 case 4:
6597 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
6598 case 3:
6599 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
6600 case 2:
6601 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
6602 }
6603 }
6604 if (rss_size)
6605 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
6606 return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
6607 }
6608
6609 /**
6610 * t4_free_vi - free a virtual interface
6611 * @adap: the adapter
6612 * @mbox: mailbox to use for the FW command
6613 * @pf: the PF owning the VI
6614 * @vf: the VF owning the VI
6615 * @viid: virtual interface identifiler
6616 *
6617 * Free a previously allocated virtual interface.
6618 */
6619 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
6620 unsigned int vf, unsigned int viid)
6621 {
6622 struct fw_vi_cmd c;
6623
6624 memset(&c, 0, sizeof(c));
6625 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
6626 FW_CMD_REQUEST_F |
6627 FW_CMD_EXEC_F |
6628 FW_VI_CMD_PFN_V(pf) |
6629 FW_VI_CMD_VFN_V(vf));
6630 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
6631 c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
6632
6633 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6634 }
6635
6636 /**
6637 * t4_set_rxmode - set Rx properties of a virtual interface
6638 * @adap: the adapter
6639 * @mbox: mailbox to use for the FW command
6640 * @viid: the VI id
6641 * @mtu: the new MTU or -1
6642 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
6643 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
6644 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
6645 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
6646 * @sleep_ok: if true we may sleep while awaiting command completion
6647 *
6648 * Sets Rx properties of a virtual interface.
6649 */
6650 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
6651 int mtu, int promisc, int all_multi, int bcast, int vlanex,
6652 bool sleep_ok)
6653 {
6654 struct fw_vi_rxmode_cmd c;
6655
6656 /* convert to FW values */
6657 if (mtu < 0)
6658 mtu = FW_RXMODE_MTU_NO_CHG;
6659 if (promisc < 0)
6660 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
6661 if (all_multi < 0)
6662 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
6663 if (bcast < 0)
6664 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
6665 if (vlanex < 0)
6666 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
6667
6668 memset(&c, 0, sizeof(c));
6669 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
6670 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6671 FW_VI_RXMODE_CMD_VIID_V(viid));
6672 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6673 c.mtu_to_vlanexen =
6674 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
6675 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
6676 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
6677 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
6678 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
6679 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6680 }
6681
6682 /**
6683 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
6684 * @adap: the adapter
6685 * @mbox: mailbox to use for the FW command
6686 * @viid: the VI id
6687 * @free: if true any existing filters for this VI id are first removed
6688 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
6689 * @addr: the MAC address(es)
6690 * @idx: where to store the index of each allocated filter
6691 * @hash: pointer to hash address filter bitmap
6692 * @sleep_ok: call is allowed to sleep
6693 *
6694 * Allocates an exact-match filter for each of the supplied addresses and
6695 * sets it to the corresponding address. If @idx is not %NULL it should
6696 * have at least @naddr entries, each of which will be set to the index of
6697 * the filter allocated for the corresponding MAC address. If a filter
6698 * could not be allocated for an address its index is set to 0xffff.
6699 * If @hash is not %NULL addresses that fail to allocate an exact filter
6700 * are hashed and update the hash filter bitmap pointed at by @hash.
6701 *
6702 * Returns a negative error number or the number of filters allocated.
6703 */
6704 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
6705 unsigned int viid, bool free, unsigned int naddr,
6706 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
6707 {
6708 int offset, ret = 0;
6709 struct fw_vi_mac_cmd c;
6710 unsigned int nfilters = 0;
6711 unsigned int max_naddr = adap->params.arch.mps_tcam_size;
6712 unsigned int rem = naddr;
6713
6714 if (naddr > max_naddr)
6715 return -EINVAL;
6716
6717 for (offset = 0; offset < naddr ; /**/) {
6718 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
6719 rem : ARRAY_SIZE(c.u.exact));
6720 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6721 u.exact[fw_naddr]), 16);
6722 struct fw_vi_mac_exact *p;
6723 int i;
6724
6725 memset(&c, 0, sizeof(c));
6726 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6727 FW_CMD_REQUEST_F |
6728 FW_CMD_WRITE_F |
6729 FW_CMD_EXEC_V(free) |
6730 FW_VI_MAC_CMD_VIID_V(viid));
6731 c.freemacs_to_len16 =
6732 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
6733 FW_CMD_LEN16_V(len16));
6734
6735 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6736 p->valid_to_idx =
6737 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6738 FW_VI_MAC_CMD_IDX_V(
6739 FW_VI_MAC_ADD_MAC));
6740 memcpy(p->macaddr, addr[offset + i],
6741 sizeof(p->macaddr));
6742 }
6743
6744 /* It's okay if we run out of space in our MAC address arena.
6745 * Some of the addresses we submit may get stored so we need
6746 * to run through the reply to see what the results were ...
6747 */
6748 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6749 if (ret && ret != -FW_ENOMEM)
6750 break;
6751
6752 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6753 u16 index = FW_VI_MAC_CMD_IDX_G(
6754 be16_to_cpu(p->valid_to_idx));
6755
6756 if (idx)
6757 idx[offset + i] = (index >= max_naddr ?
6758 0xffff : index);
6759 if (index < max_naddr)
6760 nfilters++;
6761 else if (hash)
6762 *hash |= (1ULL <<
6763 hash_mac_addr(addr[offset + i]));
6764 }
6765
6766 free = false;
6767 offset += fw_naddr;
6768 rem -= fw_naddr;
6769 }
6770
6771 if (ret == 0 || ret == -FW_ENOMEM)
6772 ret = nfilters;
6773 return ret;
6774 }
6775
6776 /**
6777 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
6778 * @adap: the adapter
6779 * @mbox: mailbox to use for the FW command
6780 * @viid: the VI id
6781 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
6782 * @addr: the MAC address(es)
6783 * @sleep_ok: call is allowed to sleep
6784 *
6785 * Frees the exact-match filter for each of the supplied addresses
6786 *
6787 * Returns a negative error number or the number of filters freed.
6788 */
6789 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
6790 unsigned int viid, unsigned int naddr,
6791 const u8 **addr, bool sleep_ok)
6792 {
6793 int offset, ret = 0;
6794 struct fw_vi_mac_cmd c;
6795 unsigned int nfilters = 0;
6796 unsigned int max_naddr = is_t4(adap->params.chip) ?
6797 NUM_MPS_CLS_SRAM_L_INSTANCES :
6798 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
6799 unsigned int rem = naddr;
6800
6801 if (naddr > max_naddr)
6802 return -EINVAL;
6803
6804 for (offset = 0; offset < (int)naddr ; /**/) {
6805 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
6806 ? rem
6807 : ARRAY_SIZE(c.u.exact));
6808 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6809 u.exact[fw_naddr]), 16);
6810 struct fw_vi_mac_exact *p;
6811 int i;
6812
6813 memset(&c, 0, sizeof(c));
6814 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6815 FW_CMD_REQUEST_F |
6816 FW_CMD_WRITE_F |
6817 FW_CMD_EXEC_V(0) |
6818 FW_VI_MAC_CMD_VIID_V(viid));
6819 c.freemacs_to_len16 =
6820 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
6821 FW_CMD_LEN16_V(len16));
6822
6823 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
6824 p->valid_to_idx = cpu_to_be16(
6825 FW_VI_MAC_CMD_VALID_F |
6826 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
6827 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
6828 }
6829
6830 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6831 if (ret)
6832 break;
6833
6834 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6835 u16 index = FW_VI_MAC_CMD_IDX_G(
6836 be16_to_cpu(p->valid_to_idx));
6837
6838 if (index < max_naddr)
6839 nfilters++;
6840 }
6841
6842 offset += fw_naddr;
6843 rem -= fw_naddr;
6844 }
6845
6846 if (ret == 0)
6847 ret = nfilters;
6848 return ret;
6849 }
6850
6851 /**
6852 * t4_change_mac - modifies the exact-match filter for a MAC address
6853 * @adap: the adapter
6854 * @mbox: mailbox to use for the FW command
6855 * @viid: the VI id
6856 * @idx: index of existing filter for old value of MAC address, or -1
6857 * @addr: the new MAC address value
6858 * @persist: whether a new MAC allocation should be persistent
6859 * @add_smt: if true also add the address to the HW SMT
6860 *
6861 * Modifies an exact-match filter and sets it to the new MAC address.
6862 * Note that in general it is not possible to modify the value of a given
6863 * filter so the generic way to modify an address filter is to free the one
6864 * being used by the old address value and allocate a new filter for the
6865 * new address value. @idx can be -1 if the address is a new addition.
6866 *
6867 * Returns a negative error number or the index of the filter with the new
6868 * MAC value.
6869 */
6870 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
6871 int idx, const u8 *addr, bool persist, bool add_smt)
6872 {
6873 int ret, mode;
6874 struct fw_vi_mac_cmd c;
6875 struct fw_vi_mac_exact *p = c.u.exact;
6876 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
6877
6878 if (idx < 0) /* new allocation */
6879 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
6880 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
6881
6882 memset(&c, 0, sizeof(c));
6883 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6884 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6885 FW_VI_MAC_CMD_VIID_V(viid));
6886 c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
6887 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6888 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
6889 FW_VI_MAC_CMD_IDX_V(idx));
6890 memcpy(p->macaddr, addr, sizeof(p->macaddr));
6891
6892 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6893 if (ret == 0) {
6894 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
6895 if (ret >= max_mac_addr)
6896 ret = -ENOMEM;
6897 }
6898 return ret;
6899 }
6900
6901 /**
6902 * t4_set_addr_hash - program the MAC inexact-match hash filter
6903 * @adap: the adapter
6904 * @mbox: mailbox to use for the FW command
6905 * @viid: the VI id
6906 * @ucast: whether the hash filter should also match unicast addresses
6907 * @vec: the value to be written to the hash filter
6908 * @sleep_ok: call is allowed to sleep
6909 *
6910 * Sets the 64-bit inexact-match hash filter for a virtual interface.
6911 */
6912 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
6913 bool ucast, u64 vec, bool sleep_ok)
6914 {
6915 struct fw_vi_mac_cmd c;
6916
6917 memset(&c, 0, sizeof(c));
6918 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6919 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6920 FW_VI_ENABLE_CMD_VIID_V(viid));
6921 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
6922 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
6923 FW_CMD_LEN16_V(1));
6924 c.u.hash.hashvec = cpu_to_be64(vec);
6925 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6926 }
6927
6928 /**
6929 * t4_enable_vi_params - enable/disable a virtual interface
6930 * @adap: the adapter
6931 * @mbox: mailbox to use for the FW command
6932 * @viid: the VI id
6933 * @rx_en: 1=enable Rx, 0=disable Rx
6934 * @tx_en: 1=enable Tx, 0=disable Tx
6935 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
6936 *
6937 * Enables/disables a virtual interface. Note that setting DCB Enable
6938 * only makes sense when enabling a Virtual Interface ...
6939 */
6940 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
6941 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
6942 {
6943 struct fw_vi_enable_cmd c;
6944
6945 memset(&c, 0, sizeof(c));
6946 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
6947 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6948 FW_VI_ENABLE_CMD_VIID_V(viid));
6949 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
6950 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
6951 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
6952 FW_LEN16(c));
6953 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
6954 }
6955
6956 /**
6957 * t4_enable_vi - enable/disable a virtual interface
6958 * @adap: the adapter
6959 * @mbox: mailbox to use for the FW command
6960 * @viid: the VI id
6961 * @rx_en: 1=enable Rx, 0=disable Rx
6962 * @tx_en: 1=enable Tx, 0=disable Tx
6963 *
6964 * Enables/disables a virtual interface.
6965 */
6966 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
6967 bool rx_en, bool tx_en)
6968 {
6969 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
6970 }
6971
6972 /**
6973 * t4_identify_port - identify a VI's port by blinking its LED
6974 * @adap: the adapter
6975 * @mbox: mailbox to use for the FW command
6976 * @viid: the VI id
6977 * @nblinks: how many times to blink LED at 2.5 Hz
6978 *
6979 * Identifies a VI's port by blinking its LED.
6980 */
6981 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
6982 unsigned int nblinks)
6983 {
6984 struct fw_vi_enable_cmd c;
6985
6986 memset(&c, 0, sizeof(c));
6987 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
6988 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6989 FW_VI_ENABLE_CMD_VIID_V(viid));
6990 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
6991 c.blinkdur = cpu_to_be16(nblinks);
6992 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6993 }
6994
6995 /**
6996 * t4_iq_stop - stop an ingress queue and its FLs
6997 * @adap: the adapter
6998 * @mbox: mailbox to use for the FW command
6999 * @pf: the PF owning the queues
7000 * @vf: the VF owning the queues
7001 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7002 * @iqid: ingress queue id
7003 * @fl0id: FL0 queue id or 0xffff if no attached FL0
7004 * @fl1id: FL1 queue id or 0xffff if no attached FL1
7005 *
7006 * Stops an ingress queue and its associated FLs, if any. This causes
7007 * any current or future data/messages destined for these queues to be
7008 * tossed.
7009 */
7010 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
7011 unsigned int vf, unsigned int iqtype, unsigned int iqid,
7012 unsigned int fl0id, unsigned int fl1id)
7013 {
7014 struct fw_iq_cmd c;
7015
7016 memset(&c, 0, sizeof(c));
7017 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7018 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7019 FW_IQ_CMD_VFN_V(vf));
7020 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
7021 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7022 c.iqid = cpu_to_be16(iqid);
7023 c.fl0id = cpu_to_be16(fl0id);
7024 c.fl1id = cpu_to_be16(fl1id);
7025 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7026 }
7027
7028 /**
7029 * t4_iq_free - free an ingress queue and its FLs
7030 * @adap: the adapter
7031 * @mbox: mailbox to use for the FW command
7032 * @pf: the PF owning the queues
7033 * @vf: the VF owning the queues
7034 * @iqtype: the ingress queue type
7035 * @iqid: ingress queue id
7036 * @fl0id: FL0 queue id or 0xffff if no attached FL0
7037 * @fl1id: FL1 queue id or 0xffff if no attached FL1
7038 *
7039 * Frees an ingress queue and its associated FLs, if any.
7040 */
7041 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7042 unsigned int vf, unsigned int iqtype, unsigned int iqid,
7043 unsigned int fl0id, unsigned int fl1id)
7044 {
7045 struct fw_iq_cmd c;
7046
7047 memset(&c, 0, sizeof(c));
7048 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7049 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7050 FW_IQ_CMD_VFN_V(vf));
7051 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
7052 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7053 c.iqid = cpu_to_be16(iqid);
7054 c.fl0id = cpu_to_be16(fl0id);
7055 c.fl1id = cpu_to_be16(fl1id);
7056 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7057 }
7058
7059 /**
7060 * t4_eth_eq_free - free an Ethernet egress queue
7061 * @adap: the adapter
7062 * @mbox: mailbox to use for the FW command
7063 * @pf: the PF owning the queue
7064 * @vf: the VF owning the queue
7065 * @eqid: egress queue id
7066 *
7067 * Frees an Ethernet egress queue.
7068 */
7069 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7070 unsigned int vf, unsigned int eqid)
7071 {
7072 struct fw_eq_eth_cmd c;
7073
7074 memset(&c, 0, sizeof(c));
7075 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
7076 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7077 FW_EQ_ETH_CMD_PFN_V(pf) |
7078 FW_EQ_ETH_CMD_VFN_V(vf));
7079 c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
7080 c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
7081 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7082 }
7083
7084 /**
7085 * t4_ctrl_eq_free - free a control egress queue
7086 * @adap: the adapter
7087 * @mbox: mailbox to use for the FW command
7088 * @pf: the PF owning the queue
7089 * @vf: the VF owning the queue
7090 * @eqid: egress queue id
7091 *
7092 * Frees a control egress queue.
7093 */
7094 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7095 unsigned int vf, unsigned int eqid)
7096 {
7097 struct fw_eq_ctrl_cmd c;
7098
7099 memset(&c, 0, sizeof(c));
7100 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
7101 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7102 FW_EQ_CTRL_CMD_PFN_V(pf) |
7103 FW_EQ_CTRL_CMD_VFN_V(vf));
7104 c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
7105 c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
7106 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7107 }
7108
7109 /**
7110 * t4_ofld_eq_free - free an offload egress queue
7111 * @adap: the adapter
7112 * @mbox: mailbox to use for the FW command
7113 * @pf: the PF owning the queue
7114 * @vf: the VF owning the queue
7115 * @eqid: egress queue id
7116 *
7117 * Frees a control egress queue.
7118 */
7119 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7120 unsigned int vf, unsigned int eqid)
7121 {
7122 struct fw_eq_ofld_cmd c;
7123
7124 memset(&c, 0, sizeof(c));
7125 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
7126 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7127 FW_EQ_OFLD_CMD_PFN_V(pf) |
7128 FW_EQ_OFLD_CMD_VFN_V(vf));
7129 c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
7130 c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
7131 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7132 }
7133
7134 /**
7135 * t4_link_down_rc_str - return a string for a Link Down Reason Code
7136 * @adap: the adapter
7137 * @link_down_rc: Link Down Reason Code
7138 *
7139 * Returns a string representation of the Link Down Reason Code.
7140 */
7141 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
7142 {
7143 static const char * const reason[] = {
7144 "Link Down",
7145 "Remote Fault",
7146 "Auto-negotiation Failure",
7147 "Reserved",
7148 "Insufficient Airflow",
7149 "Unable To Determine Reason",
7150 "No RX Signal Detected",
7151 "Reserved",
7152 };
7153
7154 if (link_down_rc >= ARRAY_SIZE(reason))
7155 return "Bad Reason Code";
7156
7157 return reason[link_down_rc];
7158 }
7159
7160 /**
7161 * t4_handle_get_port_info - process a FW reply message
7162 * @pi: the port info
7163 * @rpl: start of the FW message
7164 *
7165 * Processes a GET_PORT_INFO FW reply message.
7166 */
7167 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
7168 {
7169 const struct fw_port_cmd *p = (const void *)rpl;
7170 struct adapter *adap = pi->adapter;
7171
7172 /* link/module state change message */
7173 int speed = 0, fc = 0;
7174 struct link_config *lc;
7175 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
7176 int link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0;
7177 u32 mod = FW_PORT_CMD_MODTYPE_G(stat);
7178
7179 if (stat & FW_PORT_CMD_RXPAUSE_F)
7180 fc |= PAUSE_RX;
7181 if (stat & FW_PORT_CMD_TXPAUSE_F)
7182 fc |= PAUSE_TX;
7183 if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
7184 speed = 100;
7185 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
7186 speed = 1000;
7187 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
7188 speed = 10000;
7189 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
7190 speed = 40000;
7191
7192 lc = &pi->link_cfg;
7193
7194 if (mod != pi->mod_type) {
7195 pi->mod_type = mod;
7196 t4_os_portmod_changed(adap, pi->port_id);
7197 }
7198 if (link_ok != lc->link_ok || speed != lc->speed ||
7199 fc != lc->fc) { /* something changed */
7200 if (!link_ok && lc->link_ok) {
7201 unsigned char rc = FW_PORT_CMD_LINKDNRC_G(stat);
7202
7203 lc->link_down_rc = rc;
7204 dev_warn(adap->pdev_dev,
7205 "Port %d link down, reason: %s\n",
7206 pi->port_id, t4_link_down_rc_str(rc));
7207 }
7208 lc->link_ok = link_ok;
7209 lc->speed = speed;
7210 lc->fc = fc;
7211 lc->supported = be16_to_cpu(p->u.info.pcap);
7212 t4_os_link_changed(adap, pi->port_id, link_ok);
7213 }
7214 }
7215
7216 /**
7217 * t4_handle_fw_rpl - process a FW reply message
7218 * @adap: the adapter
7219 * @rpl: start of the FW message
7220 *
7221 * Processes a FW message, such as link state change messages.
7222 */
7223 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
7224 {
7225 u8 opcode = *(const u8 *)rpl;
7226
7227 /* This might be a port command ... this simplifies the following
7228 * conditionals ... We can get away with pre-dereferencing
7229 * action_to_len16 because it's in the first 16 bytes and all messages
7230 * will be at least that long.
7231 */
7232 const struct fw_port_cmd *p = (const void *)rpl;
7233 unsigned int action =
7234 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
7235
7236 if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
7237 int i;
7238 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
7239 struct port_info *pi = NULL;
7240
7241 for_each_port(adap, i) {
7242 pi = adap2pinfo(adap, i);
7243 if (pi->tx_chan == chan)
7244 break;
7245 }
7246
7247 t4_handle_get_port_info(pi, rpl);
7248 } else {
7249 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n", opcode);
7250 return -EINVAL;
7251 }
7252 return 0;
7253 }
7254
7255 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
7256 {
7257 u16 val;
7258
7259 if (pci_is_pcie(adapter->pdev)) {
7260 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
7261 p->speed = val & PCI_EXP_LNKSTA_CLS;
7262 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
7263 }
7264 }
7265
7266 /**
7267 * init_link_config - initialize a link's SW state
7268 * @lc: structure holding the link state
7269 * @caps: link capabilities
7270 *
7271 * Initializes the SW state maintained for each link, including the link's
7272 * capabilities and default speed/flow-control/autonegotiation settings.
7273 */
7274 static void init_link_config(struct link_config *lc, unsigned int caps)
7275 {
7276 lc->supported = caps;
7277 lc->requested_speed = 0;
7278 lc->speed = 0;
7279 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
7280 if (lc->supported & FW_PORT_CAP_ANEG) {
7281 lc->advertising = lc->supported & ADVERT_MASK;
7282 lc->autoneg = AUTONEG_ENABLE;
7283 lc->requested_fc |= PAUSE_AUTONEG;
7284 } else {
7285 lc->advertising = 0;
7286 lc->autoneg = AUTONEG_DISABLE;
7287 }
7288 }
7289
7290 #define CIM_PF_NOACCESS 0xeeeeeeee
7291
7292 int t4_wait_dev_ready(void __iomem *regs)
7293 {
7294 u32 whoami;
7295
7296 whoami = readl(regs + PL_WHOAMI_A);
7297 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
7298 return 0;
7299
7300 msleep(500);
7301 whoami = readl(regs + PL_WHOAMI_A);
7302 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
7303 }
7304
7305 struct flash_desc {
7306 u32 vendor_and_model_id;
7307 u32 size_mb;
7308 };
7309
7310 static int get_flash_params(struct adapter *adap)
7311 {
7312 /* Table for non-Numonix supported flash parts. Numonix parts are left
7313 * to the preexisting code. All flash parts have 64KB sectors.
7314 */
7315 static struct flash_desc supported_flash[] = {
7316 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
7317 };
7318
7319 int ret;
7320 u32 info;
7321
7322 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
7323 if (!ret)
7324 ret = sf1_read(adap, 3, 0, 1, &info);
7325 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
7326 if (ret)
7327 return ret;
7328
7329 for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
7330 if (supported_flash[ret].vendor_and_model_id == info) {
7331 adap->params.sf_size = supported_flash[ret].size_mb;
7332 adap->params.sf_nsec =
7333 adap->params.sf_size / SF_SEC_SIZE;
7334 return 0;
7335 }
7336
7337 if ((info & 0xff) != 0x20) /* not a Numonix flash */
7338 return -EINVAL;
7339 info >>= 16; /* log2 of size */
7340 if (info >= 0x14 && info < 0x18)
7341 adap->params.sf_nsec = 1 << (info - 16);
7342 else if (info == 0x18)
7343 adap->params.sf_nsec = 64;
7344 else
7345 return -EINVAL;
7346 adap->params.sf_size = 1 << info;
7347 adap->params.sf_fw_start =
7348 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M;
7349
7350 if (adap->params.sf_size < FLASH_MIN_SIZE)
7351 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n",
7352 adap->params.sf_size, FLASH_MIN_SIZE);
7353 return 0;
7354 }
7355
7356 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
7357 {
7358 u16 val;
7359 u32 pcie_cap;
7360
7361 pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
7362 if (pcie_cap) {
7363 pci_read_config_word(adapter->pdev,
7364 pcie_cap + PCI_EXP_DEVCTL2, &val);
7365 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
7366 val |= range;
7367 pci_write_config_word(adapter->pdev,
7368 pcie_cap + PCI_EXP_DEVCTL2, val);
7369 }
7370 }
7371
7372 /**
7373 * t4_prep_adapter - prepare SW and HW for operation
7374 * @adapter: the adapter
7375 * @reset: if true perform a HW reset
7376 *
7377 * Initialize adapter SW state for the various HW modules, set initial
7378 * values for some adapter tunables, take PHYs out of reset, and
7379 * initialize the MDIO interface.
7380 */
7381 int t4_prep_adapter(struct adapter *adapter)
7382 {
7383 int ret, ver;
7384 uint16_t device_id;
7385 u32 pl_rev;
7386
7387 get_pci_mode(adapter, &adapter->params.pci);
7388 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
7389
7390 ret = get_flash_params(adapter);
7391 if (ret < 0) {
7392 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
7393 return ret;
7394 }
7395
7396 /* Retrieve adapter's device ID
7397 */
7398 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
7399 ver = device_id >> 12;
7400 adapter->params.chip = 0;
7401 switch (ver) {
7402 case CHELSIO_T4:
7403 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
7404 adapter->params.arch.sge_fl_db = DBPRIO_F;
7405 adapter->params.arch.mps_tcam_size =
7406 NUM_MPS_CLS_SRAM_L_INSTANCES;
7407 adapter->params.arch.mps_rplc_size = 128;
7408 adapter->params.arch.nchan = NCHAN;
7409 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7410 adapter->params.arch.vfcount = 128;
7411 /* Congestion map is for 4 channels so that
7412 * MPS can have 4 priority per port.
7413 */
7414 adapter->params.arch.cng_ch_bits_log = 2;
7415 break;
7416 case CHELSIO_T5:
7417 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
7418 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
7419 adapter->params.arch.mps_tcam_size =
7420 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7421 adapter->params.arch.mps_rplc_size = 128;
7422 adapter->params.arch.nchan = NCHAN;
7423 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7424 adapter->params.arch.vfcount = 128;
7425 adapter->params.arch.cng_ch_bits_log = 2;
7426 break;
7427 case CHELSIO_T6:
7428 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
7429 adapter->params.arch.sge_fl_db = 0;
7430 adapter->params.arch.mps_tcam_size =
7431 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7432 adapter->params.arch.mps_rplc_size = 256;
7433 adapter->params.arch.nchan = 2;
7434 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
7435 adapter->params.arch.vfcount = 256;
7436 /* Congestion map will be for 2 channels so that
7437 * MPS can have 8 priority per port.
7438 */
7439 adapter->params.arch.cng_ch_bits_log = 3;
7440 break;
7441 default:
7442 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
7443 device_id);
7444 return -EINVAL;
7445 }
7446
7447 adapter->params.cim_la_size = CIMLA_SIZE;
7448 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
7449
7450 /*
7451 * Default port for debugging in case we can't reach FW.
7452 */
7453 adapter->params.nports = 1;
7454 adapter->params.portvec = 1;
7455 adapter->params.vpd.cclk = 50000;
7456
7457 /* Set pci completion timeout value to 4 seconds. */
7458 set_pcie_completion_timeout(adapter, 0xd);
7459 return 0;
7460 }
7461
7462 /**
7463 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
7464 * @adapter: the adapter
7465 * @qid: the Queue ID
7466 * @qtype: the Ingress or Egress type for @qid
7467 * @user: true if this request is for a user mode queue
7468 * @pbar2_qoffset: BAR2 Queue Offset
7469 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
7470 *
7471 * Returns the BAR2 SGE Queue Registers information associated with the
7472 * indicated Absolute Queue ID. These are passed back in return value
7473 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
7474 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
7475 *
7476 * This may return an error which indicates that BAR2 SGE Queue
7477 * registers aren't available. If an error is not returned, then the
7478 * following values are returned:
7479 *
7480 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
7481 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
7482 *
7483 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
7484 * require the "Inferred Queue ID" ability may be used. E.g. the
7485 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
7486 * then these "Inferred Queue ID" register may not be used.
7487 */
7488 int t4_bar2_sge_qregs(struct adapter *adapter,
7489 unsigned int qid,
7490 enum t4_bar2_qtype qtype,
7491 int user,
7492 u64 *pbar2_qoffset,
7493 unsigned int *pbar2_qid)
7494 {
7495 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
7496 u64 bar2_page_offset, bar2_qoffset;
7497 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
7498
7499 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
7500 if (!user && is_t4(adapter->params.chip))
7501 return -EINVAL;
7502
7503 /* Get our SGE Page Size parameters.
7504 */
7505 page_shift = adapter->params.sge.hps + 10;
7506 page_size = 1 << page_shift;
7507
7508 /* Get the right Queues per Page parameters for our Queue.
7509 */
7510 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
7511 ? adapter->params.sge.eq_qpp
7512 : adapter->params.sge.iq_qpp);
7513 qpp_mask = (1 << qpp_shift) - 1;
7514
7515 /* Calculate the basics of the BAR2 SGE Queue register area:
7516 * o The BAR2 page the Queue registers will be in.
7517 * o The BAR2 Queue ID.
7518 * o The BAR2 Queue ID Offset into the BAR2 page.
7519 */
7520 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
7521 bar2_qid = qid & qpp_mask;
7522 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
7523
7524 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
7525 * hardware will infer the Absolute Queue ID simply from the writes to
7526 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
7527 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
7528 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
7529 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
7530 * from the BAR2 Page and BAR2 Queue ID.
7531 *
7532 * One important censequence of this is that some BAR2 SGE registers
7533 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
7534 * there. But other registers synthesize the SGE Queue ID purely
7535 * from the writes to the registers -- the Write Combined Doorbell
7536 * Buffer is a good example. These BAR2 SGE Registers are only
7537 * available for those BAR2 SGE Register areas where the SGE Absolute
7538 * Queue ID can be inferred from simple writes.
7539 */
7540 bar2_qoffset = bar2_page_offset;
7541 bar2_qinferred = (bar2_qid_offset < page_size);
7542 if (bar2_qinferred) {
7543 bar2_qoffset += bar2_qid_offset;
7544 bar2_qid = 0;
7545 }
7546
7547 *pbar2_qoffset = bar2_qoffset;
7548 *pbar2_qid = bar2_qid;
7549 return 0;
7550 }
7551
7552 /**
7553 * t4_init_devlog_params - initialize adapter->params.devlog
7554 * @adap: the adapter
7555 *
7556 * Initialize various fields of the adapter's Firmware Device Log
7557 * Parameters structure.
7558 */
7559 int t4_init_devlog_params(struct adapter *adap)
7560 {
7561 struct devlog_params *dparams = &adap->params.devlog;
7562 u32 pf_dparams;
7563 unsigned int devlog_meminfo;
7564 struct fw_devlog_cmd devlog_cmd;
7565 int ret;
7566
7567 /* If we're dealing with newer firmware, the Device Log Paramerters
7568 * are stored in a designated register which allows us to access the
7569 * Device Log even if we can't talk to the firmware.
7570 */
7571 pf_dparams =
7572 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
7573 if (pf_dparams) {
7574 unsigned int nentries, nentries128;
7575
7576 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
7577 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
7578
7579 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
7580 nentries = (nentries128 + 1) * 128;
7581 dparams->size = nentries * sizeof(struct fw_devlog_e);
7582
7583 return 0;
7584 }
7585
7586 /* Otherwise, ask the firmware for it's Device Log Parameters.
7587 */
7588 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
7589 devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
7590 FW_CMD_REQUEST_F | FW_CMD_READ_F);
7591 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
7592 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
7593 &devlog_cmd);
7594 if (ret)
7595 return ret;
7596
7597 devlog_meminfo =
7598 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
7599 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
7600 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
7601 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
7602
7603 return 0;
7604 }
7605
7606 /**
7607 * t4_init_sge_params - initialize adap->params.sge
7608 * @adapter: the adapter
7609 *
7610 * Initialize various fields of the adapter's SGE Parameters structure.
7611 */
7612 int t4_init_sge_params(struct adapter *adapter)
7613 {
7614 struct sge_params *sge_params = &adapter->params.sge;
7615 u32 hps, qpp;
7616 unsigned int s_hps, s_qpp;
7617
7618 /* Extract the SGE Page Size for our PF.
7619 */
7620 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
7621 s_hps = (HOSTPAGESIZEPF0_S +
7622 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
7623 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
7624
7625 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
7626 */
7627 s_qpp = (QUEUESPERPAGEPF0_S +
7628 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
7629 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
7630 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7631 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
7632 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7633
7634 return 0;
7635 }
7636
7637 /**
7638 * t4_init_tp_params - initialize adap->params.tp
7639 * @adap: the adapter
7640 *
7641 * Initialize various fields of the adapter's TP Parameters structure.
7642 */
7643 int t4_init_tp_params(struct adapter *adap)
7644 {
7645 int chan;
7646 u32 v;
7647
7648 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
7649 adap->params.tp.tre = TIMERRESOLUTION_G(v);
7650 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
7651
7652 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
7653 for (chan = 0; chan < NCHAN; chan++)
7654 adap->params.tp.tx_modq[chan] = chan;
7655
7656 /* Cache the adapter's Compressed Filter Mode and global Incress
7657 * Configuration.
7658 */
7659 if (t4_use_ldst(adap)) {
7660 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1,
7661 TP_VLAN_PRI_MAP_A, 1);
7662 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1,
7663 TP_INGRESS_CONFIG_A, 1);
7664 } else {
7665 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7666 &adap->params.tp.vlan_pri_map, 1,
7667 TP_VLAN_PRI_MAP_A);
7668 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7669 &adap->params.tp.ingress_config, 1,
7670 TP_INGRESS_CONFIG_A);
7671 }
7672
7673 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
7674 * shift positions of several elements of the Compressed Filter Tuple
7675 * for this adapter which we need frequently ...
7676 */
7677 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
7678 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
7679 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
7680 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
7681 PROTOCOL_F);
7682
7683 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
7684 * represents the presence of an Outer VLAN instead of a VNIC ID.
7685 */
7686 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
7687 adap->params.tp.vnic_shift = -1;
7688
7689 return 0;
7690 }
7691
7692 /**
7693 * t4_filter_field_shift - calculate filter field shift
7694 * @adap: the adapter
7695 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
7696 *
7697 * Return the shift position of a filter field within the Compressed
7698 * Filter Tuple. The filter field is specified via its selection bit
7699 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
7700 */
7701 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
7702 {
7703 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
7704 unsigned int sel;
7705 int field_shift;
7706
7707 if ((filter_mode & filter_sel) == 0)
7708 return -1;
7709
7710 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
7711 switch (filter_mode & sel) {
7712 case FCOE_F:
7713 field_shift += FT_FCOE_W;
7714 break;
7715 case PORT_F:
7716 field_shift += FT_PORT_W;
7717 break;
7718 case VNIC_ID_F:
7719 field_shift += FT_VNIC_ID_W;
7720 break;
7721 case VLAN_F:
7722 field_shift += FT_VLAN_W;
7723 break;
7724 case TOS_F:
7725 field_shift += FT_TOS_W;
7726 break;
7727 case PROTOCOL_F:
7728 field_shift += FT_PROTOCOL_W;
7729 break;
7730 case ETHERTYPE_F:
7731 field_shift += FT_ETHERTYPE_W;
7732 break;
7733 case MACMATCH_F:
7734 field_shift += FT_MACMATCH_W;
7735 break;
7736 case MPSHITTYPE_F:
7737 field_shift += FT_MPSHITTYPE_W;
7738 break;
7739 case FRAGMENTATION_F:
7740 field_shift += FT_FRAGMENTATION_W;
7741 break;
7742 }
7743 }
7744 return field_shift;
7745 }
7746
7747 int t4_init_rss_mode(struct adapter *adap, int mbox)
7748 {
7749 int i, ret;
7750 struct fw_rss_vi_config_cmd rvc;
7751
7752 memset(&rvc, 0, sizeof(rvc));
7753
7754 for_each_port(adap, i) {
7755 struct port_info *p = adap2pinfo(adap, i);
7756
7757 rvc.op_to_viid =
7758 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
7759 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7760 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
7761 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
7762 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
7763 if (ret)
7764 return ret;
7765 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
7766 }
7767 return 0;
7768 }
7769
7770 /**
7771 * t4_init_portinfo - allocate a virtual interface amd initialize port_info
7772 * @pi: the port_info
7773 * @mbox: mailbox to use for the FW command
7774 * @port: physical port associated with the VI
7775 * @pf: the PF owning the VI
7776 * @vf: the VF owning the VI
7777 * @mac: the MAC address of the VI
7778 *
7779 * Allocates a virtual interface for the given physical port. If @mac is
7780 * not %NULL it contains the MAC address of the VI as assigned by FW.
7781 * @mac should be large enough to hold an Ethernet address.
7782 * Returns < 0 on error.
7783 */
7784 int t4_init_portinfo(struct port_info *pi, int mbox,
7785 int port, int pf, int vf, u8 mac[])
7786 {
7787 int ret;
7788 struct fw_port_cmd c;
7789 unsigned int rss_size;
7790
7791 memset(&c, 0, sizeof(c));
7792 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
7793 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7794 FW_PORT_CMD_PORTID_V(port));
7795 c.action_to_len16 = cpu_to_be32(
7796 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
7797 FW_LEN16(c));
7798 ret = t4_wr_mbox(pi->adapter, mbox, &c, sizeof(c), &c);
7799 if (ret)
7800 return ret;
7801
7802 ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size);
7803 if (ret < 0)
7804 return ret;
7805
7806 pi->viid = ret;
7807 pi->tx_chan = port;
7808 pi->lport = port;
7809 pi->rss_size = rss_size;
7810
7811 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
7812 pi->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP_F) ?
7813 FW_PORT_CMD_MDIOADDR_G(ret) : -1;
7814 pi->port_type = FW_PORT_CMD_PTYPE_G(ret);
7815 pi->mod_type = FW_PORT_MOD_TYPE_NA;
7816
7817 init_link_config(&pi->link_cfg, be16_to_cpu(c.u.info.pcap));
7818 return 0;
7819 }
7820
7821 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
7822 {
7823 u8 addr[6];
7824 int ret, i, j = 0;
7825
7826 for_each_port(adap, i) {
7827 struct port_info *pi = adap2pinfo(adap, i);
7828
7829 while ((adap->params.portvec & (1 << j)) == 0)
7830 j++;
7831
7832 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
7833 if (ret)
7834 return ret;
7835
7836 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
7837 adap->port[i]->dev_port = j;
7838 j++;
7839 }
7840 return 0;
7841 }
7842
7843 /**
7844 * t4_read_cimq_cfg - read CIM queue configuration
7845 * @adap: the adapter
7846 * @base: holds the queue base addresses in bytes
7847 * @size: holds the queue sizes in bytes
7848 * @thres: holds the queue full thresholds in bytes
7849 *
7850 * Returns the current configuration of the CIM queues, starting with
7851 * the IBQs, then the OBQs.
7852 */
7853 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
7854 {
7855 unsigned int i, v;
7856 int cim_num_obq = is_t4(adap->params.chip) ?
7857 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
7858
7859 for (i = 0; i < CIM_NUM_IBQ; i++) {
7860 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
7861 QUENUMSELECT_V(i));
7862 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7863 /* value is in 256-byte units */
7864 *base++ = CIMQBASE_G(v) * 256;
7865 *size++ = CIMQSIZE_G(v) * 256;
7866 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
7867 }
7868 for (i = 0; i < cim_num_obq; i++) {
7869 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
7870 QUENUMSELECT_V(i));
7871 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7872 /* value is in 256-byte units */
7873 *base++ = CIMQBASE_G(v) * 256;
7874 *size++ = CIMQSIZE_G(v) * 256;
7875 }
7876 }
7877
7878 /**
7879 * t4_read_cim_ibq - read the contents of a CIM inbound queue
7880 * @adap: the adapter
7881 * @qid: the queue index
7882 * @data: where to store the queue contents
7883 * @n: capacity of @data in 32-bit words
7884 *
7885 * Reads the contents of the selected CIM queue starting at address 0 up
7886 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
7887 * error and the number of 32-bit words actually read on success.
7888 */
7889 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7890 {
7891 int i, err, attempts;
7892 unsigned int addr;
7893 const unsigned int nwords = CIM_IBQ_SIZE * 4;
7894
7895 if (qid > 5 || (n & 3))
7896 return -EINVAL;
7897
7898 addr = qid * nwords;
7899 if (n > nwords)
7900 n = nwords;
7901
7902 /* It might take 3-10ms before the IBQ debug read access is allowed.
7903 * Wait for 1 Sec with a delay of 1 usec.
7904 */
7905 attempts = 1000000;
7906
7907 for (i = 0; i < n; i++, addr++) {
7908 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
7909 IBQDBGEN_F);
7910 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
7911 attempts, 1);
7912 if (err)
7913 return err;
7914 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
7915 }
7916 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
7917 return i;
7918 }
7919
7920 /**
7921 * t4_read_cim_obq - read the contents of a CIM outbound queue
7922 * @adap: the adapter
7923 * @qid: the queue index
7924 * @data: where to store the queue contents
7925 * @n: capacity of @data in 32-bit words
7926 *
7927 * Reads the contents of the selected CIM queue starting at address 0 up
7928 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
7929 * error and the number of 32-bit words actually read on success.
7930 */
7931 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7932 {
7933 int i, err;
7934 unsigned int addr, v, nwords;
7935 int cim_num_obq = is_t4(adap->params.chip) ?
7936 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
7937
7938 if ((qid > (cim_num_obq - 1)) || (n & 3))
7939 return -EINVAL;
7940
7941 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
7942 QUENUMSELECT_V(qid));
7943 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7944
7945 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
7946 nwords = CIMQSIZE_G(v) * 64; /* same */
7947 if (n > nwords)
7948 n = nwords;
7949
7950 for (i = 0; i < n; i++, addr++) {
7951 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
7952 OBQDBGEN_F);
7953 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
7954 2, 1);
7955 if (err)
7956 return err;
7957 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
7958 }
7959 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
7960 return i;
7961 }
7962
7963 /**
7964 * t4_cim_read - read a block from CIM internal address space
7965 * @adap: the adapter
7966 * @addr: the start address within the CIM address space
7967 * @n: number of words to read
7968 * @valp: where to store the result
7969 *
7970 * Reads a block of 4-byte words from the CIM intenal address space.
7971 */
7972 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
7973 unsigned int *valp)
7974 {
7975 int ret = 0;
7976
7977 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
7978 return -EBUSY;
7979
7980 for ( ; !ret && n--; addr += 4) {
7981 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
7982 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
7983 0, 5, 2);
7984 if (!ret)
7985 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
7986 }
7987 return ret;
7988 }
7989
7990 /**
7991 * t4_cim_write - write a block into CIM internal address space
7992 * @adap: the adapter
7993 * @addr: the start address within the CIM address space
7994 * @n: number of words to write
7995 * @valp: set of values to write
7996 *
7997 * Writes a block of 4-byte words into the CIM intenal address space.
7998 */
7999 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
8000 const unsigned int *valp)
8001 {
8002 int ret = 0;
8003
8004 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
8005 return -EBUSY;
8006
8007 for ( ; !ret && n--; addr += 4) {
8008 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
8009 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
8010 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
8011 0, 5, 2);
8012 }
8013 return ret;
8014 }
8015
8016 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
8017 unsigned int val)
8018 {
8019 return t4_cim_write(adap, addr, 1, &val);
8020 }
8021
8022 /**
8023 * t4_cim_read_la - read CIM LA capture buffer
8024 * @adap: the adapter
8025 * @la_buf: where to store the LA data
8026 * @wrptr: the HW write pointer within the capture buffer
8027 *
8028 * Reads the contents of the CIM LA buffer with the most recent entry at
8029 * the end of the returned data and with the entry at @wrptr first.
8030 * We try to leave the LA in the running state we find it in.
8031 */
8032 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
8033 {
8034 int i, ret;
8035 unsigned int cfg, val, idx;
8036
8037 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
8038 if (ret)
8039 return ret;
8040
8041 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
8042 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
8043 if (ret)
8044 return ret;
8045 }
8046
8047 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
8048 if (ret)
8049 goto restart;
8050
8051 idx = UPDBGLAWRPTR_G(val);
8052 if (wrptr)
8053 *wrptr = idx;
8054
8055 for (i = 0; i < adap->params.cim_la_size; i++) {
8056 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
8057 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
8058 if (ret)
8059 break;
8060 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
8061 if (ret)
8062 break;
8063 if (val & UPDBGLARDEN_F) {
8064 ret = -ETIMEDOUT;
8065 break;
8066 }
8067 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
8068 if (ret)
8069 break;
8070 idx = (idx + 1) & UPDBGLARDPTR_M;
8071 }
8072 restart:
8073 if (cfg & UPDBGLAEN_F) {
8074 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
8075 cfg & ~UPDBGLARDEN_F);
8076 if (!ret)
8077 ret = r;
8078 }
8079 return ret;
8080 }
8081
8082 /**
8083 * t4_tp_read_la - read TP LA capture buffer
8084 * @adap: the adapter
8085 * @la_buf: where to store the LA data
8086 * @wrptr: the HW write pointer within the capture buffer
8087 *
8088 * Reads the contents of the TP LA buffer with the most recent entry at
8089 * the end of the returned data and with the entry at @wrptr first.
8090 * We leave the LA in the running state we find it in.
8091 */
8092 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
8093 {
8094 bool last_incomplete;
8095 unsigned int i, cfg, val, idx;
8096
8097 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
8098 if (cfg & DBGLAENABLE_F) /* freeze LA */
8099 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8100 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
8101
8102 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
8103 idx = DBGLAWPTR_G(val);
8104 last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
8105 if (last_incomplete)
8106 idx = (idx + 1) & DBGLARPTR_M;
8107 if (wrptr)
8108 *wrptr = idx;
8109
8110 val &= 0xffff;
8111 val &= ~DBGLARPTR_V(DBGLARPTR_M);
8112 val |= adap->params.tp.la_mask;
8113
8114 for (i = 0; i < TPLA_SIZE; i++) {
8115 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
8116 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
8117 idx = (idx + 1) & DBGLARPTR_M;
8118 }
8119
8120 /* Wipe out last entry if it isn't valid */
8121 if (last_incomplete)
8122 la_buf[TPLA_SIZE - 1] = ~0ULL;
8123
8124 if (cfg & DBGLAENABLE_F) /* restore running state */
8125 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8126 cfg | adap->params.tp.la_mask);
8127 }
8128
8129 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
8130 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
8131 * state for more than the Warning Threshold then we'll issue a warning about
8132 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
8133 * appears to be hung every Warning Repeat second till the situation clears.
8134 * If the situation clears, we'll note that as well.
8135 */
8136 #define SGE_IDMA_WARN_THRESH 1
8137 #define SGE_IDMA_WARN_REPEAT 300
8138
8139 /**
8140 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
8141 * @adapter: the adapter
8142 * @idma: the adapter IDMA Monitor state
8143 *
8144 * Initialize the state of an SGE Ingress DMA Monitor.
8145 */
8146 void t4_idma_monitor_init(struct adapter *adapter,
8147 struct sge_idma_monitor_state *idma)
8148 {
8149 /* Initialize the state variables for detecting an SGE Ingress DMA
8150 * hang. The SGE has internal counters which count up on each clock
8151 * tick whenever the SGE finds its Ingress DMA State Engines in the
8152 * same state they were on the previous clock tick. The clock used is
8153 * the Core Clock so we have a limit on the maximum "time" they can
8154 * record; typically a very small number of seconds. For instance,
8155 * with a 600MHz Core Clock, we can only count up to a bit more than
8156 * 7s. So we'll synthesize a larger counter in order to not run the
8157 * risk of having the "timers" overflow and give us the flexibility to
8158 * maintain a Hung SGE State Machine of our own which operates across
8159 * a longer time frame.
8160 */
8161 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
8162 idma->idma_stalled[0] = 0;
8163 idma->idma_stalled[1] = 0;
8164 }
8165
8166 /**
8167 * t4_idma_monitor - monitor SGE Ingress DMA state
8168 * @adapter: the adapter
8169 * @idma: the adapter IDMA Monitor state
8170 * @hz: number of ticks/second
8171 * @ticks: number of ticks since the last IDMA Monitor call
8172 */
8173 void t4_idma_monitor(struct adapter *adapter,
8174 struct sge_idma_monitor_state *idma,
8175 int hz, int ticks)
8176 {
8177 int i, idma_same_state_cnt[2];
8178
8179 /* Read the SGE Debug Ingress DMA Same State Count registers. These
8180 * are counters inside the SGE which count up on each clock when the
8181 * SGE finds its Ingress DMA State Engines in the same states they
8182 * were in the previous clock. The counters will peg out at
8183 * 0xffffffff without wrapping around so once they pass the 1s
8184 * threshold they'll stay above that till the IDMA state changes.
8185 */
8186 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
8187 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
8188 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8189
8190 for (i = 0; i < 2; i++) {
8191 u32 debug0, debug11;
8192
8193 /* If the Ingress DMA Same State Counter ("timer") is less
8194 * than 1s, then we can reset our synthesized Stall Timer and
8195 * continue. If we have previously emitted warnings about a
8196 * potential stalled Ingress Queue, issue a note indicating
8197 * that the Ingress Queue has resumed forward progress.
8198 */
8199 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
8200 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
8201 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
8202 "resumed after %d seconds\n",
8203 i, idma->idma_qid[i],
8204 idma->idma_stalled[i] / hz);
8205 idma->idma_stalled[i] = 0;
8206 continue;
8207 }
8208
8209 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
8210 * domain. The first time we get here it'll be because we
8211 * passed the 1s Threshold; each additional time it'll be
8212 * because the RX Timer Callback is being fired on its regular
8213 * schedule.
8214 *
8215 * If the stall is below our Potential Hung Ingress Queue
8216 * Warning Threshold, continue.
8217 */
8218 if (idma->idma_stalled[i] == 0) {
8219 idma->idma_stalled[i] = hz;
8220 idma->idma_warn[i] = 0;
8221 } else {
8222 idma->idma_stalled[i] += ticks;
8223 idma->idma_warn[i] -= ticks;
8224 }
8225
8226 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
8227 continue;
8228
8229 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
8230 */
8231 if (idma->idma_warn[i] > 0)
8232 continue;
8233 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
8234
8235 /* Read and save the SGE IDMA State and Queue ID information.
8236 * We do this every time in case it changes across time ...
8237 * can't be too careful ...
8238 */
8239 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
8240 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8241 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
8242
8243 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
8244 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8245 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
8246
8247 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
8248 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
8249 i, idma->idma_qid[i], idma->idma_state[i],
8250 idma->idma_stalled[i] / hz,
8251 debug0, debug11);
8252 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
8253 }
8254 }
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