]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/net/ethernet/chelsio/cxgb4/t4_msg.h
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'ceph-for-4.11-rc1' of git://github.com/ceph/ceph-client
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / chelsio / cxgb4 / t4_msg.h
1 /*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #ifndef __T4_MSG_H
36 #define __T4_MSG_H
37
38 #include <linux/types.h>
39
40 enum {
41 CPL_PASS_OPEN_REQ = 0x1,
42 CPL_PASS_ACCEPT_RPL = 0x2,
43 CPL_ACT_OPEN_REQ = 0x3,
44 CPL_SET_TCB_FIELD = 0x5,
45 CPL_GET_TCB = 0x6,
46 CPL_CLOSE_CON_REQ = 0x8,
47 CPL_CLOSE_LISTSRV_REQ = 0x9,
48 CPL_ABORT_REQ = 0xA,
49 CPL_ABORT_RPL = 0xB,
50 CPL_RX_DATA_ACK = 0xD,
51 CPL_TX_PKT = 0xE,
52 CPL_L2T_WRITE_REQ = 0x12,
53 CPL_TID_RELEASE = 0x1A,
54 CPL_TX_DATA_ISO = 0x1F,
55
56 CPL_CLOSE_LISTSRV_RPL = 0x20,
57 CPL_L2T_WRITE_RPL = 0x23,
58 CPL_PASS_OPEN_RPL = 0x24,
59 CPL_ACT_OPEN_RPL = 0x25,
60 CPL_PEER_CLOSE = 0x26,
61 CPL_ABORT_REQ_RSS = 0x2B,
62 CPL_ABORT_RPL_RSS = 0x2D,
63
64 CPL_RX_PHYS_ADDR = 0x30,
65 CPL_CLOSE_CON_RPL = 0x32,
66 CPL_ISCSI_HDR = 0x33,
67 CPL_RDMA_CQE = 0x35,
68 CPL_RDMA_CQE_READ_RSP = 0x36,
69 CPL_RDMA_CQE_ERR = 0x37,
70 CPL_RX_DATA = 0x39,
71 CPL_SET_TCB_RPL = 0x3A,
72 CPL_RX_PKT = 0x3B,
73 CPL_RX_DDP_COMPLETE = 0x3F,
74
75 CPL_ACT_ESTABLISH = 0x40,
76 CPL_PASS_ESTABLISH = 0x41,
77 CPL_RX_DATA_DDP = 0x42,
78 CPL_PASS_ACCEPT_REQ = 0x44,
79 CPL_RX_ISCSI_CMP = 0x45,
80 CPL_TRACE_PKT_T5 = 0x48,
81 CPL_RX_ISCSI_DDP = 0x49,
82
83 CPL_RDMA_READ_REQ = 0x60,
84
85 CPL_PASS_OPEN_REQ6 = 0x81,
86 CPL_ACT_OPEN_REQ6 = 0x83,
87
88 CPL_TX_TLS_PDU = 0x88,
89 CPL_TX_SEC_PDU = 0x8A,
90 CPL_TX_TLS_ACK = 0x8B,
91
92 CPL_RDMA_TERMINATE = 0xA2,
93 CPL_RDMA_WRITE = 0xA4,
94 CPL_SGE_EGR_UPDATE = 0xA5,
95
96 CPL_TRACE_PKT = 0xB0,
97 CPL_ISCSI_DATA = 0xB2,
98
99 CPL_FW4_MSG = 0xC0,
100 CPL_FW4_PLD = 0xC1,
101 CPL_FW4_ACK = 0xC3,
102
103 CPL_RX_PHYS_DSGL = 0xD0,
104
105 CPL_FW6_MSG = 0xE0,
106 CPL_FW6_PLD = 0xE1,
107 CPL_TX_PKT_LSO = 0xED,
108 CPL_TX_PKT_XT = 0xEE,
109
110 NUM_CPL_CMDS
111 };
112
113 enum CPL_error {
114 CPL_ERR_NONE = 0,
115 CPL_ERR_TCAM_PARITY = 1,
116 CPL_ERR_TCAM_MISS = 2,
117 CPL_ERR_TCAM_FULL = 3,
118 CPL_ERR_BAD_LENGTH = 15,
119 CPL_ERR_BAD_ROUTE = 18,
120 CPL_ERR_CONN_RESET = 20,
121 CPL_ERR_CONN_EXIST_SYNRECV = 21,
122 CPL_ERR_CONN_EXIST = 22,
123 CPL_ERR_ARP_MISS = 23,
124 CPL_ERR_BAD_SYN = 24,
125 CPL_ERR_CONN_TIMEDOUT = 30,
126 CPL_ERR_XMIT_TIMEDOUT = 31,
127 CPL_ERR_PERSIST_TIMEDOUT = 32,
128 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
129 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
130 CPL_ERR_RTX_NEG_ADVICE = 35,
131 CPL_ERR_PERSIST_NEG_ADVICE = 36,
132 CPL_ERR_KEEPALV_NEG_ADVICE = 37,
133 CPL_ERR_ABORT_FAILED = 42,
134 CPL_ERR_IWARP_FLM = 50,
135 };
136
137 enum {
138 CPL_CONN_POLICY_AUTO = 0,
139 CPL_CONN_POLICY_ASK = 1,
140 CPL_CONN_POLICY_FILTER = 2,
141 CPL_CONN_POLICY_DENY = 3
142 };
143
144 enum {
145 ULP_MODE_NONE = 0,
146 ULP_MODE_ISCSI = 2,
147 ULP_MODE_RDMA = 4,
148 ULP_MODE_TCPDDP = 5,
149 ULP_MODE_FCOE = 6,
150 };
151
152 enum {
153 ULP_CRC_HEADER = 1 << 0,
154 ULP_CRC_DATA = 1 << 1
155 };
156
157 enum {
158 CPL_ABORT_SEND_RST = 0,
159 CPL_ABORT_NO_RST,
160 };
161
162 enum { /* TX_PKT_XT checksum types */
163 TX_CSUM_TCP = 0,
164 TX_CSUM_UDP = 1,
165 TX_CSUM_CRC16 = 4,
166 TX_CSUM_CRC32 = 5,
167 TX_CSUM_CRC32C = 6,
168 TX_CSUM_FCOE = 7,
169 TX_CSUM_TCPIP = 8,
170 TX_CSUM_UDPIP = 9,
171 TX_CSUM_TCPIP6 = 10,
172 TX_CSUM_UDPIP6 = 11,
173 TX_CSUM_IP = 12,
174 };
175
176 union opcode_tid {
177 __be32 opcode_tid;
178 u8 opcode;
179 };
180
181 #define CPL_OPCODE_S 24
182 #define CPL_OPCODE_V(x) ((x) << CPL_OPCODE_S)
183 #define CPL_OPCODE_G(x) (((x) >> CPL_OPCODE_S) & 0xFF)
184 #define TID_G(x) ((x) & 0xFFFFFF)
185
186 /* tid is assumed to be 24-bits */
187 #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE_V(opcode) | (tid))
188
189 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
190
191 /* extract the TID from a CPL command */
192 #define GET_TID(cmd) (TID_G(be32_to_cpu(OPCODE_TID(cmd))))
193
194 /* partitioning of TID fields that also carry a queue id */
195 #define TID_TID_S 0
196 #define TID_TID_M 0x3fff
197 #define TID_TID_G(x) (((x) >> TID_TID_S) & TID_TID_M)
198
199 #define TID_QID_S 14
200 #define TID_QID_M 0x3ff
201 #define TID_QID_V(x) ((x) << TID_QID_S)
202 #define TID_QID_G(x) (((x) >> TID_QID_S) & TID_QID_M)
203
204 struct rss_header {
205 u8 opcode;
206 #if defined(__LITTLE_ENDIAN_BITFIELD)
207 u8 channel:2;
208 u8 filter_hit:1;
209 u8 filter_tid:1;
210 u8 hash_type:2;
211 u8 ipv6:1;
212 u8 send2fw:1;
213 #else
214 u8 send2fw:1;
215 u8 ipv6:1;
216 u8 hash_type:2;
217 u8 filter_tid:1;
218 u8 filter_hit:1;
219 u8 channel:2;
220 #endif
221 __be16 qid;
222 __be32 hash_val;
223 };
224
225 struct work_request_hdr {
226 __be32 wr_hi;
227 __be32 wr_mid;
228 __be64 wr_lo;
229 };
230
231 /* wr_hi fields */
232 #define WR_OP_S 24
233 #define WR_OP_V(x) ((__u64)(x) << WR_OP_S)
234
235 #define WR_HDR struct work_request_hdr wr
236
237 /* option 0 fields */
238 #define TX_CHAN_S 2
239 #define TX_CHAN_V(x) ((x) << TX_CHAN_S)
240
241 #define ULP_MODE_S 8
242 #define ULP_MODE_V(x) ((x) << ULP_MODE_S)
243
244 #define RCV_BUFSIZ_S 12
245 #define RCV_BUFSIZ_M 0x3FFU
246 #define RCV_BUFSIZ_V(x) ((x) << RCV_BUFSIZ_S)
247
248 #define SMAC_SEL_S 28
249 #define SMAC_SEL_V(x) ((__u64)(x) << SMAC_SEL_S)
250
251 #define L2T_IDX_S 36
252 #define L2T_IDX_V(x) ((__u64)(x) << L2T_IDX_S)
253
254 #define WND_SCALE_S 50
255 #define WND_SCALE_V(x) ((__u64)(x) << WND_SCALE_S)
256
257 #define KEEP_ALIVE_S 54
258 #define KEEP_ALIVE_V(x) ((__u64)(x) << KEEP_ALIVE_S)
259 #define KEEP_ALIVE_F KEEP_ALIVE_V(1ULL)
260
261 #define MSS_IDX_S 60
262 #define MSS_IDX_M 0xF
263 #define MSS_IDX_V(x) ((__u64)(x) << MSS_IDX_S)
264 #define MSS_IDX_G(x) (((x) >> MSS_IDX_S) & MSS_IDX_M)
265
266 /* option 2 fields */
267 #define RSS_QUEUE_S 0
268 #define RSS_QUEUE_M 0x3FF
269 #define RSS_QUEUE_V(x) ((x) << RSS_QUEUE_S)
270 #define RSS_QUEUE_G(x) (((x) >> RSS_QUEUE_S) & RSS_QUEUE_M)
271
272 #define RSS_QUEUE_VALID_S 10
273 #define RSS_QUEUE_VALID_V(x) ((x) << RSS_QUEUE_VALID_S)
274 #define RSS_QUEUE_VALID_F RSS_QUEUE_VALID_V(1U)
275
276 #define RX_FC_DISABLE_S 20
277 #define RX_FC_DISABLE_V(x) ((x) << RX_FC_DISABLE_S)
278 #define RX_FC_DISABLE_F RX_FC_DISABLE_V(1U)
279
280 #define RX_FC_VALID_S 22
281 #define RX_FC_VALID_V(x) ((x) << RX_FC_VALID_S)
282 #define RX_FC_VALID_F RX_FC_VALID_V(1U)
283
284 #define RX_CHANNEL_S 26
285 #define RX_CHANNEL_V(x) ((x) << RX_CHANNEL_S)
286
287 #define WND_SCALE_EN_S 28
288 #define WND_SCALE_EN_V(x) ((x) << WND_SCALE_EN_S)
289 #define WND_SCALE_EN_F WND_SCALE_EN_V(1U)
290
291 #define T5_OPT_2_VALID_S 31
292 #define T5_OPT_2_VALID_V(x) ((x) << T5_OPT_2_VALID_S)
293 #define T5_OPT_2_VALID_F T5_OPT_2_VALID_V(1U)
294
295 struct cpl_pass_open_req {
296 WR_HDR;
297 union opcode_tid ot;
298 __be16 local_port;
299 __be16 peer_port;
300 __be32 local_ip;
301 __be32 peer_ip;
302 __be64 opt0;
303 __be64 opt1;
304 };
305
306 /* option 0 fields */
307 #define NO_CONG_S 4
308 #define NO_CONG_V(x) ((x) << NO_CONG_S)
309 #define NO_CONG_F NO_CONG_V(1U)
310
311 #define DELACK_S 5
312 #define DELACK_V(x) ((x) << DELACK_S)
313 #define DELACK_F DELACK_V(1U)
314
315 #define DSCP_S 22
316 #define DSCP_M 0x3F
317 #define DSCP_V(x) ((x) << DSCP_S)
318 #define DSCP_G(x) (((x) >> DSCP_S) & DSCP_M)
319
320 #define TCAM_BYPASS_S 48
321 #define TCAM_BYPASS_V(x) ((__u64)(x) << TCAM_BYPASS_S)
322 #define TCAM_BYPASS_F TCAM_BYPASS_V(1ULL)
323
324 #define NAGLE_S 49
325 #define NAGLE_V(x) ((__u64)(x) << NAGLE_S)
326 #define NAGLE_F NAGLE_V(1ULL)
327
328 /* option 1 fields */
329 #define SYN_RSS_ENABLE_S 0
330 #define SYN_RSS_ENABLE_V(x) ((x) << SYN_RSS_ENABLE_S)
331 #define SYN_RSS_ENABLE_F SYN_RSS_ENABLE_V(1U)
332
333 #define SYN_RSS_QUEUE_S 2
334 #define SYN_RSS_QUEUE_V(x) ((x) << SYN_RSS_QUEUE_S)
335
336 #define CONN_POLICY_S 22
337 #define CONN_POLICY_V(x) ((x) << CONN_POLICY_S)
338
339 struct cpl_pass_open_req6 {
340 WR_HDR;
341 union opcode_tid ot;
342 __be16 local_port;
343 __be16 peer_port;
344 __be64 local_ip_hi;
345 __be64 local_ip_lo;
346 __be64 peer_ip_hi;
347 __be64 peer_ip_lo;
348 __be64 opt0;
349 __be64 opt1;
350 };
351
352 struct cpl_pass_open_rpl {
353 union opcode_tid ot;
354 u8 rsvd[3];
355 u8 status;
356 };
357
358 struct tcp_options {
359 __be16 mss;
360 __u8 wsf;
361 #if defined(__LITTLE_ENDIAN_BITFIELD)
362 __u8:4;
363 __u8 unknown:1;
364 __u8:1;
365 __u8 sack:1;
366 __u8 tstamp:1;
367 #else
368 __u8 tstamp:1;
369 __u8 sack:1;
370 __u8:1;
371 __u8 unknown:1;
372 __u8:4;
373 #endif
374 };
375
376 struct cpl_pass_accept_req {
377 union opcode_tid ot;
378 __be16 rsvd;
379 __be16 len;
380 __be32 hdr_len;
381 __be16 vlan;
382 __be16 l2info;
383 __be32 tos_stid;
384 struct tcp_options tcpopt;
385 };
386
387 /* cpl_pass_accept_req.hdr_len fields */
388 #define SYN_RX_CHAN_S 0
389 #define SYN_RX_CHAN_M 0xF
390 #define SYN_RX_CHAN_V(x) ((x) << SYN_RX_CHAN_S)
391 #define SYN_RX_CHAN_G(x) (((x) >> SYN_RX_CHAN_S) & SYN_RX_CHAN_M)
392
393 #define TCP_HDR_LEN_S 10
394 #define TCP_HDR_LEN_M 0x3F
395 #define TCP_HDR_LEN_V(x) ((x) << TCP_HDR_LEN_S)
396 #define TCP_HDR_LEN_G(x) (((x) >> TCP_HDR_LEN_S) & TCP_HDR_LEN_M)
397
398 #define IP_HDR_LEN_S 16
399 #define IP_HDR_LEN_M 0x3FF
400 #define IP_HDR_LEN_V(x) ((x) << IP_HDR_LEN_S)
401 #define IP_HDR_LEN_G(x) (((x) >> IP_HDR_LEN_S) & IP_HDR_LEN_M)
402
403 #define ETH_HDR_LEN_S 26
404 #define ETH_HDR_LEN_M 0x1F
405 #define ETH_HDR_LEN_V(x) ((x) << ETH_HDR_LEN_S)
406 #define ETH_HDR_LEN_G(x) (((x) >> ETH_HDR_LEN_S) & ETH_HDR_LEN_M)
407
408 /* cpl_pass_accept_req.l2info fields */
409 #define SYN_MAC_IDX_S 0
410 #define SYN_MAC_IDX_M 0x1FF
411 #define SYN_MAC_IDX_V(x) ((x) << SYN_MAC_IDX_S)
412 #define SYN_MAC_IDX_G(x) (((x) >> SYN_MAC_IDX_S) & SYN_MAC_IDX_M)
413
414 #define SYN_XACT_MATCH_S 9
415 #define SYN_XACT_MATCH_V(x) ((x) << SYN_XACT_MATCH_S)
416 #define SYN_XACT_MATCH_F SYN_XACT_MATCH_V(1U)
417
418 #define SYN_INTF_S 12
419 #define SYN_INTF_M 0xF
420 #define SYN_INTF_V(x) ((x) << SYN_INTF_S)
421 #define SYN_INTF_G(x) (((x) >> SYN_INTF_S) & SYN_INTF_M)
422
423 enum { /* TCP congestion control algorithms */
424 CONG_ALG_RENO,
425 CONG_ALG_TAHOE,
426 CONG_ALG_NEWRENO,
427 CONG_ALG_HIGHSPEED
428 };
429
430 #define CONG_CNTRL_S 14
431 #define CONG_CNTRL_M 0x3
432 #define CONG_CNTRL_V(x) ((x) << CONG_CNTRL_S)
433 #define CONG_CNTRL_G(x) (((x) >> CONG_CNTRL_S) & CONG_CNTRL_M)
434
435 #define T5_ISS_S 18
436 #define T5_ISS_V(x) ((x) << T5_ISS_S)
437 #define T5_ISS_F T5_ISS_V(1U)
438
439 struct cpl_pass_accept_rpl {
440 WR_HDR;
441 union opcode_tid ot;
442 __be32 opt2;
443 __be64 opt0;
444 };
445
446 /* option 2 fields */
447 #define RX_COALESCE_VALID_S 11
448 #define RX_COALESCE_VALID_V(x) ((x) << RX_COALESCE_VALID_S)
449 #define RX_COALESCE_VALID_F RX_COALESCE_VALID_V(1U)
450
451 #define RX_COALESCE_S 12
452 #define RX_COALESCE_V(x) ((x) << RX_COALESCE_S)
453
454 #define PACE_S 16
455 #define PACE_V(x) ((x) << PACE_S)
456
457 #define TX_QUEUE_S 23
458 #define TX_QUEUE_M 0x7
459 #define TX_QUEUE_V(x) ((x) << TX_QUEUE_S)
460 #define TX_QUEUE_G(x) (((x) >> TX_QUEUE_S) & TX_QUEUE_M)
461
462 #define CCTRL_ECN_S 27
463 #define CCTRL_ECN_V(x) ((x) << CCTRL_ECN_S)
464 #define CCTRL_ECN_F CCTRL_ECN_V(1U)
465
466 #define TSTAMPS_EN_S 29
467 #define TSTAMPS_EN_V(x) ((x) << TSTAMPS_EN_S)
468 #define TSTAMPS_EN_F TSTAMPS_EN_V(1U)
469
470 #define SACK_EN_S 30
471 #define SACK_EN_V(x) ((x) << SACK_EN_S)
472 #define SACK_EN_F SACK_EN_V(1U)
473
474 struct cpl_t5_pass_accept_rpl {
475 WR_HDR;
476 union opcode_tid ot;
477 __be32 opt2;
478 __be64 opt0;
479 __be32 iss;
480 __be32 rsvd;
481 };
482
483 struct cpl_act_open_req {
484 WR_HDR;
485 union opcode_tid ot;
486 __be16 local_port;
487 __be16 peer_port;
488 __be32 local_ip;
489 __be32 peer_ip;
490 __be64 opt0;
491 __be32 params;
492 __be32 opt2;
493 };
494
495 #define FILTER_TUPLE_S 24
496 #define FILTER_TUPLE_M 0xFFFFFFFFFF
497 #define FILTER_TUPLE_V(x) ((x) << FILTER_TUPLE_S)
498 #define FILTER_TUPLE_G(x) (((x) >> FILTER_TUPLE_S) & FILTER_TUPLE_M)
499 struct cpl_t5_act_open_req {
500 WR_HDR;
501 union opcode_tid ot;
502 __be16 local_port;
503 __be16 peer_port;
504 __be32 local_ip;
505 __be32 peer_ip;
506 __be64 opt0;
507 __be32 rsvd;
508 __be32 opt2;
509 __be64 params;
510 };
511
512 struct cpl_t6_act_open_req {
513 WR_HDR;
514 union opcode_tid ot;
515 __be16 local_port;
516 __be16 peer_port;
517 __be32 local_ip;
518 __be32 peer_ip;
519 __be64 opt0;
520 __be32 rsvd;
521 __be32 opt2;
522 __be64 params;
523 __be32 rsvd2;
524 __be32 opt3;
525 };
526
527 struct cpl_act_open_req6 {
528 WR_HDR;
529 union opcode_tid ot;
530 __be16 local_port;
531 __be16 peer_port;
532 __be64 local_ip_hi;
533 __be64 local_ip_lo;
534 __be64 peer_ip_hi;
535 __be64 peer_ip_lo;
536 __be64 opt0;
537 __be32 params;
538 __be32 opt2;
539 };
540
541 struct cpl_t5_act_open_req6 {
542 WR_HDR;
543 union opcode_tid ot;
544 __be16 local_port;
545 __be16 peer_port;
546 __be64 local_ip_hi;
547 __be64 local_ip_lo;
548 __be64 peer_ip_hi;
549 __be64 peer_ip_lo;
550 __be64 opt0;
551 __be32 rsvd;
552 __be32 opt2;
553 __be64 params;
554 };
555
556 struct cpl_t6_act_open_req6 {
557 WR_HDR;
558 union opcode_tid ot;
559 __be16 local_port;
560 __be16 peer_port;
561 __be64 local_ip_hi;
562 __be64 local_ip_lo;
563 __be64 peer_ip_hi;
564 __be64 peer_ip_lo;
565 __be64 opt0;
566 __be32 rsvd;
567 __be32 opt2;
568 __be64 params;
569 __be32 rsvd2;
570 __be32 opt3;
571 };
572
573 struct cpl_act_open_rpl {
574 union opcode_tid ot;
575 __be32 atid_status;
576 };
577
578 /* cpl_act_open_rpl.atid_status fields */
579 #define AOPEN_STATUS_S 0
580 #define AOPEN_STATUS_M 0xFF
581 #define AOPEN_STATUS_G(x) (((x) >> AOPEN_STATUS_S) & AOPEN_STATUS_M)
582
583 #define AOPEN_ATID_S 8
584 #define AOPEN_ATID_M 0xFFFFFF
585 #define AOPEN_ATID_G(x) (((x) >> AOPEN_ATID_S) & AOPEN_ATID_M)
586
587 struct cpl_pass_establish {
588 union opcode_tid ot;
589 __be32 rsvd;
590 __be32 tos_stid;
591 __be16 mac_idx;
592 __be16 tcp_opt;
593 __be32 snd_isn;
594 __be32 rcv_isn;
595 };
596
597 /* cpl_pass_establish.tos_stid fields */
598 #define PASS_OPEN_TID_S 0
599 #define PASS_OPEN_TID_M 0xFFFFFF
600 #define PASS_OPEN_TID_V(x) ((x) << PASS_OPEN_TID_S)
601 #define PASS_OPEN_TID_G(x) (((x) >> PASS_OPEN_TID_S) & PASS_OPEN_TID_M)
602
603 #define PASS_OPEN_TOS_S 24
604 #define PASS_OPEN_TOS_M 0xFF
605 #define PASS_OPEN_TOS_V(x) ((x) << PASS_OPEN_TOS_S)
606 #define PASS_OPEN_TOS_G(x) (((x) >> PASS_OPEN_TOS_S) & PASS_OPEN_TOS_M)
607
608 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */
609 #define TCPOPT_WSCALE_OK_S 5
610 #define TCPOPT_WSCALE_OK_M 0x1
611 #define TCPOPT_WSCALE_OK_G(x) \
612 (((x) >> TCPOPT_WSCALE_OK_S) & TCPOPT_WSCALE_OK_M)
613
614 #define TCPOPT_SACK_S 6
615 #define TCPOPT_SACK_M 0x1
616 #define TCPOPT_SACK_G(x) (((x) >> TCPOPT_SACK_S) & TCPOPT_SACK_M)
617
618 #define TCPOPT_TSTAMP_S 7
619 #define TCPOPT_TSTAMP_M 0x1
620 #define TCPOPT_TSTAMP_G(x) (((x) >> TCPOPT_TSTAMP_S) & TCPOPT_TSTAMP_M)
621
622 #define TCPOPT_SND_WSCALE_S 8
623 #define TCPOPT_SND_WSCALE_M 0xF
624 #define TCPOPT_SND_WSCALE_G(x) \
625 (((x) >> TCPOPT_SND_WSCALE_S) & TCPOPT_SND_WSCALE_M)
626
627 #define TCPOPT_MSS_S 12
628 #define TCPOPT_MSS_M 0xF
629 #define TCPOPT_MSS_G(x) (((x) >> TCPOPT_MSS_S) & TCPOPT_MSS_M)
630
631 #define T6_TCP_HDR_LEN_S 8
632 #define T6_TCP_HDR_LEN_V(x) ((x) << T6_TCP_HDR_LEN_S)
633 #define T6_TCP_HDR_LEN_G(x) (((x) >> T6_TCP_HDR_LEN_S) & TCP_HDR_LEN_M)
634
635 #define T6_IP_HDR_LEN_S 14
636 #define T6_IP_HDR_LEN_V(x) ((x) << T6_IP_HDR_LEN_S)
637 #define T6_IP_HDR_LEN_G(x) (((x) >> T6_IP_HDR_LEN_S) & IP_HDR_LEN_M)
638
639 #define T6_ETH_HDR_LEN_S 24
640 #define T6_ETH_HDR_LEN_M 0xFF
641 #define T6_ETH_HDR_LEN_V(x) ((x) << T6_ETH_HDR_LEN_S)
642 #define T6_ETH_HDR_LEN_G(x) (((x) >> T6_ETH_HDR_LEN_S) & T6_ETH_HDR_LEN_M)
643
644 struct cpl_act_establish {
645 union opcode_tid ot;
646 __be32 rsvd;
647 __be32 tos_atid;
648 __be16 mac_idx;
649 __be16 tcp_opt;
650 __be32 snd_isn;
651 __be32 rcv_isn;
652 };
653
654 struct cpl_get_tcb {
655 WR_HDR;
656 union opcode_tid ot;
657 __be16 reply_ctrl;
658 __be16 cookie;
659 };
660
661 /* cpl_get_tcb.reply_ctrl fields */
662 #define QUEUENO_S 0
663 #define QUEUENO_V(x) ((x) << QUEUENO_S)
664
665 #define REPLY_CHAN_S 14
666 #define REPLY_CHAN_V(x) ((x) << REPLY_CHAN_S)
667 #define REPLY_CHAN_F REPLY_CHAN_V(1U)
668
669 #define NO_REPLY_S 15
670 #define NO_REPLY_V(x) ((x) << NO_REPLY_S)
671 #define NO_REPLY_F NO_REPLY_V(1U)
672
673 struct cpl_set_tcb_field {
674 WR_HDR;
675 union opcode_tid ot;
676 __be16 reply_ctrl;
677 __be16 word_cookie;
678 __be64 mask;
679 __be64 val;
680 };
681
682 /* cpl_set_tcb_field.word_cookie fields */
683 #define TCB_WORD_S 0
684 #define TCB_WORD(x) ((x) << TCB_WORD_S)
685
686 #define TCB_COOKIE_S 5
687 #define TCB_COOKIE_M 0x7
688 #define TCB_COOKIE_V(x) ((x) << TCB_COOKIE_S)
689 #define TCB_COOKIE_G(x) (((x) >> TCB_COOKIE_S) & TCB_COOKIE_M)
690
691 struct cpl_set_tcb_rpl {
692 union opcode_tid ot;
693 __be16 rsvd;
694 u8 cookie;
695 u8 status;
696 __be64 oldval;
697 };
698
699 struct cpl_close_con_req {
700 WR_HDR;
701 union opcode_tid ot;
702 __be32 rsvd;
703 };
704
705 struct cpl_close_con_rpl {
706 union opcode_tid ot;
707 u8 rsvd[3];
708 u8 status;
709 __be32 snd_nxt;
710 __be32 rcv_nxt;
711 };
712
713 struct cpl_close_listsvr_req {
714 WR_HDR;
715 union opcode_tid ot;
716 __be16 reply_ctrl;
717 __be16 rsvd;
718 };
719
720 /* additional cpl_close_listsvr_req.reply_ctrl field */
721 #define LISTSVR_IPV6_S 14
722 #define LISTSVR_IPV6_V(x) ((x) << LISTSVR_IPV6_S)
723 #define LISTSVR_IPV6_F LISTSVR_IPV6_V(1U)
724
725 struct cpl_close_listsvr_rpl {
726 union opcode_tid ot;
727 u8 rsvd[3];
728 u8 status;
729 };
730
731 struct cpl_abort_req_rss {
732 union opcode_tid ot;
733 u8 rsvd[3];
734 u8 status;
735 };
736
737 struct cpl_abort_req {
738 WR_HDR;
739 union opcode_tid ot;
740 __be32 rsvd0;
741 u8 rsvd1;
742 u8 cmd;
743 u8 rsvd2[6];
744 };
745
746 struct cpl_abort_rpl_rss {
747 union opcode_tid ot;
748 u8 rsvd[3];
749 u8 status;
750 };
751
752 struct cpl_abort_rpl {
753 WR_HDR;
754 union opcode_tid ot;
755 __be32 rsvd0;
756 u8 rsvd1;
757 u8 cmd;
758 u8 rsvd2[6];
759 };
760
761 struct cpl_peer_close {
762 union opcode_tid ot;
763 __be32 rcv_nxt;
764 };
765
766 struct cpl_tid_release {
767 WR_HDR;
768 union opcode_tid ot;
769 __be32 rsvd;
770 };
771
772 struct cpl_tx_pkt_core {
773 __be32 ctrl0;
774 __be16 pack;
775 __be16 len;
776 __be64 ctrl1;
777 };
778
779 struct cpl_tx_pkt {
780 WR_HDR;
781 struct cpl_tx_pkt_core c;
782 };
783
784 #define cpl_tx_pkt_xt cpl_tx_pkt
785
786 /* cpl_tx_pkt_core.ctrl0 fields */
787 #define TXPKT_VF_S 0
788 #define TXPKT_VF_V(x) ((x) << TXPKT_VF_S)
789
790 #define TXPKT_PF_S 8
791 #define TXPKT_PF_V(x) ((x) << TXPKT_PF_S)
792
793 #define TXPKT_VF_VLD_S 11
794 #define TXPKT_VF_VLD_V(x) ((x) << TXPKT_VF_VLD_S)
795 #define TXPKT_VF_VLD_F TXPKT_VF_VLD_V(1U)
796
797 #define TXPKT_OVLAN_IDX_S 12
798 #define TXPKT_OVLAN_IDX_V(x) ((x) << TXPKT_OVLAN_IDX_S)
799
800 #define TXPKT_T5_OVLAN_IDX_S 12
801 #define TXPKT_T5_OVLAN_IDX_V(x) ((x) << TXPKT_T5_OVLAN_IDX_S)
802
803 #define TXPKT_INTF_S 16
804 #define TXPKT_INTF_V(x) ((x) << TXPKT_INTF_S)
805
806 #define TXPKT_INS_OVLAN_S 21
807 #define TXPKT_INS_OVLAN_V(x) ((x) << TXPKT_INS_OVLAN_S)
808 #define TXPKT_INS_OVLAN_F TXPKT_INS_OVLAN_V(1U)
809
810 #define TXPKT_OPCODE_S 24
811 #define TXPKT_OPCODE_V(x) ((x) << TXPKT_OPCODE_S)
812
813 /* cpl_tx_pkt_core.ctrl1 fields */
814 #define TXPKT_CSUM_END_S 12
815 #define TXPKT_CSUM_END_V(x) ((x) << TXPKT_CSUM_END_S)
816
817 #define TXPKT_CSUM_START_S 20
818 #define TXPKT_CSUM_START_V(x) ((x) << TXPKT_CSUM_START_S)
819
820 #define TXPKT_IPHDR_LEN_S 20
821 #define TXPKT_IPHDR_LEN_V(x) ((__u64)(x) << TXPKT_IPHDR_LEN_S)
822
823 #define TXPKT_CSUM_LOC_S 30
824 #define TXPKT_CSUM_LOC_V(x) ((__u64)(x) << TXPKT_CSUM_LOC_S)
825
826 #define TXPKT_ETHHDR_LEN_S 34
827 #define TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << TXPKT_ETHHDR_LEN_S)
828
829 #define T6_TXPKT_ETHHDR_LEN_S 32
830 #define T6_TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << T6_TXPKT_ETHHDR_LEN_S)
831
832 #define TXPKT_CSUM_TYPE_S 40
833 #define TXPKT_CSUM_TYPE_V(x) ((__u64)(x) << TXPKT_CSUM_TYPE_S)
834
835 #define TXPKT_VLAN_S 44
836 #define TXPKT_VLAN_V(x) ((__u64)(x) << TXPKT_VLAN_S)
837
838 #define TXPKT_VLAN_VLD_S 60
839 #define TXPKT_VLAN_VLD_V(x) ((__u64)(x) << TXPKT_VLAN_VLD_S)
840 #define TXPKT_VLAN_VLD_F TXPKT_VLAN_VLD_V(1ULL)
841
842 #define TXPKT_IPCSUM_DIS_S 62
843 #define TXPKT_IPCSUM_DIS_V(x) ((__u64)(x) << TXPKT_IPCSUM_DIS_S)
844 #define TXPKT_IPCSUM_DIS_F TXPKT_IPCSUM_DIS_V(1ULL)
845
846 #define TXPKT_L4CSUM_DIS_S 63
847 #define TXPKT_L4CSUM_DIS_V(x) ((__u64)(x) << TXPKT_L4CSUM_DIS_S)
848 #define TXPKT_L4CSUM_DIS_F TXPKT_L4CSUM_DIS_V(1ULL)
849
850 struct cpl_tx_pkt_lso_core {
851 __be32 lso_ctrl;
852 __be16 ipid_ofst;
853 __be16 mss;
854 __be32 seqno_offset;
855 __be32 len;
856 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
857 };
858
859 /* cpl_tx_pkt_lso_core.lso_ctrl fields */
860 #define LSO_TCPHDR_LEN_S 0
861 #define LSO_TCPHDR_LEN_V(x) ((x) << LSO_TCPHDR_LEN_S)
862
863 #define LSO_IPHDR_LEN_S 4
864 #define LSO_IPHDR_LEN_V(x) ((x) << LSO_IPHDR_LEN_S)
865
866 #define LSO_ETHHDR_LEN_S 16
867 #define LSO_ETHHDR_LEN_V(x) ((x) << LSO_ETHHDR_LEN_S)
868
869 #define LSO_IPV6_S 20
870 #define LSO_IPV6_V(x) ((x) << LSO_IPV6_S)
871 #define LSO_IPV6_F LSO_IPV6_V(1U)
872
873 #define LSO_LAST_SLICE_S 22
874 #define LSO_LAST_SLICE_V(x) ((x) << LSO_LAST_SLICE_S)
875 #define LSO_LAST_SLICE_F LSO_LAST_SLICE_V(1U)
876
877 #define LSO_FIRST_SLICE_S 23
878 #define LSO_FIRST_SLICE_V(x) ((x) << LSO_FIRST_SLICE_S)
879 #define LSO_FIRST_SLICE_F LSO_FIRST_SLICE_V(1U)
880
881 #define LSO_OPCODE_S 24
882 #define LSO_OPCODE_V(x) ((x) << LSO_OPCODE_S)
883
884 #define LSO_T5_XFER_SIZE_S 0
885 #define LSO_T5_XFER_SIZE_V(x) ((x) << LSO_T5_XFER_SIZE_S)
886
887 struct cpl_tx_pkt_lso {
888 WR_HDR;
889 struct cpl_tx_pkt_lso_core c;
890 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
891 };
892
893 struct cpl_iscsi_hdr {
894 union opcode_tid ot;
895 __be16 pdu_len_ddp;
896 __be16 len;
897 __be32 seq;
898 __be16 urg;
899 u8 rsvd;
900 u8 status;
901 };
902
903 /* cpl_iscsi_hdr.pdu_len_ddp fields */
904 #define ISCSI_PDU_LEN_S 0
905 #define ISCSI_PDU_LEN_M 0x7FFF
906 #define ISCSI_PDU_LEN_V(x) ((x) << ISCSI_PDU_LEN_S)
907 #define ISCSI_PDU_LEN_G(x) (((x) >> ISCSI_PDU_LEN_S) & ISCSI_PDU_LEN_M)
908
909 #define ISCSI_DDP_S 15
910 #define ISCSI_DDP_V(x) ((x) << ISCSI_DDP_S)
911 #define ISCSI_DDP_F ISCSI_DDP_V(1U)
912
913 struct cpl_rx_data_ddp {
914 union opcode_tid ot;
915 __be16 urg;
916 __be16 len;
917 __be32 seq;
918 union {
919 __be32 nxt_seq;
920 __be32 ddp_report;
921 };
922 __be32 ulp_crc;
923 __be32 ddpvld;
924 };
925
926 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp
927
928 struct cpl_iscsi_data {
929 union opcode_tid ot;
930 __u8 rsvd0[2];
931 __be16 len;
932 __be32 seq;
933 __be16 urg;
934 __u8 rsvd1;
935 __u8 status;
936 };
937
938 struct cpl_rx_iscsi_cmp {
939 union opcode_tid ot;
940 __be16 pdu_len_ddp;
941 __be16 len;
942 __be32 seq;
943 __be16 urg;
944 __u8 rsvd;
945 __u8 status;
946 __be32 ulp_crc;
947 __be32 ddpvld;
948 };
949
950 struct cpl_tx_data_iso {
951 __be32 op_to_scsi;
952 __u8 reserved1;
953 __u8 ahs_len;
954 __be16 mpdu;
955 __be32 burst_size;
956 __be32 len;
957 __be32 reserved2_seglen_offset;
958 __be32 datasn_offset;
959 __be32 buffer_offset;
960 __be32 reserved3;
961
962 /* encapsulated CPL_TX_DATA follows here */
963 };
964
965 /* cpl_tx_data_iso.op_to_scsi fields */
966 #define CPL_TX_DATA_ISO_OP_S 24
967 #define CPL_TX_DATA_ISO_OP_M 0xff
968 #define CPL_TX_DATA_ISO_OP_V(x) ((x) << CPL_TX_DATA_ISO_OP_S)
969 #define CPL_TX_DATA_ISO_OP_G(x) \
970 (((x) >> CPL_TX_DATA_ISO_OP_S) & CPL_TX_DATA_ISO_OP_M)
971
972 #define CPL_TX_DATA_ISO_FIRST_S 23
973 #define CPL_TX_DATA_ISO_FIRST_M 0x1
974 #define CPL_TX_DATA_ISO_FIRST_V(x) ((x) << CPL_TX_DATA_ISO_FIRST_S)
975 #define CPL_TX_DATA_ISO_FIRST_G(x) \
976 (((x) >> CPL_TX_DATA_ISO_FIRST_S) & CPL_TX_DATA_ISO_FIRST_M)
977 #define CPL_TX_DATA_ISO_FIRST_F CPL_TX_DATA_ISO_FIRST_V(1U)
978
979 #define CPL_TX_DATA_ISO_LAST_S 22
980 #define CPL_TX_DATA_ISO_LAST_M 0x1
981 #define CPL_TX_DATA_ISO_LAST_V(x) ((x) << CPL_TX_DATA_ISO_LAST_S)
982 #define CPL_TX_DATA_ISO_LAST_G(x) \
983 (((x) >> CPL_TX_DATA_ISO_LAST_S) & CPL_TX_DATA_ISO_LAST_M)
984 #define CPL_TX_DATA_ISO_LAST_F CPL_TX_DATA_ISO_LAST_V(1U)
985
986 #define CPL_TX_DATA_ISO_CPLHDRLEN_S 21
987 #define CPL_TX_DATA_ISO_CPLHDRLEN_M 0x1
988 #define CPL_TX_DATA_ISO_CPLHDRLEN_V(x) ((x) << CPL_TX_DATA_ISO_CPLHDRLEN_S)
989 #define CPL_TX_DATA_ISO_CPLHDRLEN_G(x) \
990 (((x) >> CPL_TX_DATA_ISO_CPLHDRLEN_S) & CPL_TX_DATA_ISO_CPLHDRLEN_M)
991 #define CPL_TX_DATA_ISO_CPLHDRLEN_F CPL_TX_DATA_ISO_CPLHDRLEN_V(1U)
992
993 #define CPL_TX_DATA_ISO_HDRCRC_S 20
994 #define CPL_TX_DATA_ISO_HDRCRC_M 0x1
995 #define CPL_TX_DATA_ISO_HDRCRC_V(x) ((x) << CPL_TX_DATA_ISO_HDRCRC_S)
996 #define CPL_TX_DATA_ISO_HDRCRC_G(x) \
997 (((x) >> CPL_TX_DATA_ISO_HDRCRC_S) & CPL_TX_DATA_ISO_HDRCRC_M)
998 #define CPL_TX_DATA_ISO_HDRCRC_F CPL_TX_DATA_ISO_HDRCRC_V(1U)
999
1000 #define CPL_TX_DATA_ISO_PLDCRC_S 19
1001 #define CPL_TX_DATA_ISO_PLDCRC_M 0x1
1002 #define CPL_TX_DATA_ISO_PLDCRC_V(x) ((x) << CPL_TX_DATA_ISO_PLDCRC_S)
1003 #define CPL_TX_DATA_ISO_PLDCRC_G(x) \
1004 (((x) >> CPL_TX_DATA_ISO_PLDCRC_S) & CPL_TX_DATA_ISO_PLDCRC_M)
1005 #define CPL_TX_DATA_ISO_PLDCRC_F CPL_TX_DATA_ISO_PLDCRC_V(1U)
1006
1007 #define CPL_TX_DATA_ISO_IMMEDIATE_S 18
1008 #define CPL_TX_DATA_ISO_IMMEDIATE_M 0x1
1009 #define CPL_TX_DATA_ISO_IMMEDIATE_V(x) ((x) << CPL_TX_DATA_ISO_IMMEDIATE_S)
1010 #define CPL_TX_DATA_ISO_IMMEDIATE_G(x) \
1011 (((x) >> CPL_TX_DATA_ISO_IMMEDIATE_S) & CPL_TX_DATA_ISO_IMMEDIATE_M)
1012 #define CPL_TX_DATA_ISO_IMMEDIATE_F CPL_TX_DATA_ISO_IMMEDIATE_V(1U)
1013
1014 #define CPL_TX_DATA_ISO_SCSI_S 16
1015 #define CPL_TX_DATA_ISO_SCSI_M 0x3
1016 #define CPL_TX_DATA_ISO_SCSI_V(x) ((x) << CPL_TX_DATA_ISO_SCSI_S)
1017 #define CPL_TX_DATA_ISO_SCSI_G(x) \
1018 (((x) >> CPL_TX_DATA_ISO_SCSI_S) & CPL_TX_DATA_ISO_SCSI_M)
1019
1020 /* cpl_tx_data_iso.reserved2_seglen_offset fields */
1021 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_S 0
1022 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_M 0xffffff
1023 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_V(x) \
1024 ((x) << CPL_TX_DATA_ISO_SEGLEN_OFFSET_S)
1025 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_G(x) \
1026 (((x) >> CPL_TX_DATA_ISO_SEGLEN_OFFSET_S) & \
1027 CPL_TX_DATA_ISO_SEGLEN_OFFSET_M)
1028
1029 struct cpl_rx_data {
1030 union opcode_tid ot;
1031 __be16 rsvd;
1032 __be16 len;
1033 __be32 seq;
1034 __be16 urg;
1035 #if defined(__LITTLE_ENDIAN_BITFIELD)
1036 u8 dack_mode:2;
1037 u8 psh:1;
1038 u8 heartbeat:1;
1039 u8 ddp_off:1;
1040 u8 :3;
1041 #else
1042 u8 :3;
1043 u8 ddp_off:1;
1044 u8 heartbeat:1;
1045 u8 psh:1;
1046 u8 dack_mode:2;
1047 #endif
1048 u8 status;
1049 };
1050
1051 struct cpl_rx_data_ack {
1052 WR_HDR;
1053 union opcode_tid ot;
1054 __be32 credit_dack;
1055 };
1056
1057 /* cpl_rx_data_ack.ack_seq fields */
1058 #define RX_CREDITS_S 0
1059 #define RX_CREDITS_V(x) ((x) << RX_CREDITS_S)
1060
1061 #define RX_FORCE_ACK_S 28
1062 #define RX_FORCE_ACK_V(x) ((x) << RX_FORCE_ACK_S)
1063 #define RX_FORCE_ACK_F RX_FORCE_ACK_V(1U)
1064
1065 #define RX_DACK_MODE_S 29
1066 #define RX_DACK_MODE_M 0x3
1067 #define RX_DACK_MODE_V(x) ((x) << RX_DACK_MODE_S)
1068 #define RX_DACK_MODE_G(x) (((x) >> RX_DACK_MODE_S) & RX_DACK_MODE_M)
1069
1070 #define RX_DACK_CHANGE_S 31
1071 #define RX_DACK_CHANGE_V(x) ((x) << RX_DACK_CHANGE_S)
1072 #define RX_DACK_CHANGE_F RX_DACK_CHANGE_V(1U)
1073
1074 struct cpl_rx_pkt {
1075 struct rss_header rsshdr;
1076 u8 opcode;
1077 #if defined(__LITTLE_ENDIAN_BITFIELD)
1078 u8 iff:4;
1079 u8 csum_calc:1;
1080 u8 ipmi_pkt:1;
1081 u8 vlan_ex:1;
1082 u8 ip_frag:1;
1083 #else
1084 u8 ip_frag:1;
1085 u8 vlan_ex:1;
1086 u8 ipmi_pkt:1;
1087 u8 csum_calc:1;
1088 u8 iff:4;
1089 #endif
1090 __be16 csum;
1091 __be16 vlan;
1092 __be16 len;
1093 __be32 l2info;
1094 __be16 hdr_len;
1095 __be16 err_vec;
1096 };
1097
1098 #define RX_T6_ETHHDR_LEN_M 0xFF
1099 #define RX_T6_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_T6_ETHHDR_LEN_M)
1100
1101 #define RXF_PSH_S 20
1102 #define RXF_PSH_V(x) ((x) << RXF_PSH_S)
1103 #define RXF_PSH_F RXF_PSH_V(1U)
1104
1105 #define RXF_SYN_S 21
1106 #define RXF_SYN_V(x) ((x) << RXF_SYN_S)
1107 #define RXF_SYN_F RXF_SYN_V(1U)
1108
1109 #define RXF_UDP_S 22
1110 #define RXF_UDP_V(x) ((x) << RXF_UDP_S)
1111 #define RXF_UDP_F RXF_UDP_V(1U)
1112
1113 #define RXF_TCP_S 23
1114 #define RXF_TCP_V(x) ((x) << RXF_TCP_S)
1115 #define RXF_TCP_F RXF_TCP_V(1U)
1116
1117 #define RXF_IP_S 24
1118 #define RXF_IP_V(x) ((x) << RXF_IP_S)
1119 #define RXF_IP_F RXF_IP_V(1U)
1120
1121 #define RXF_IP6_S 25
1122 #define RXF_IP6_V(x) ((x) << RXF_IP6_S)
1123 #define RXF_IP6_F RXF_IP6_V(1U)
1124
1125 #define RXF_SYN_COOKIE_S 26
1126 #define RXF_SYN_COOKIE_V(x) ((x) << RXF_SYN_COOKIE_S)
1127 #define RXF_SYN_COOKIE_F RXF_SYN_COOKIE_V(1U)
1128
1129 #define RXF_FCOE_S 26
1130 #define RXF_FCOE_V(x) ((x) << RXF_FCOE_S)
1131 #define RXF_FCOE_F RXF_FCOE_V(1U)
1132
1133 #define RXF_LRO_S 27
1134 #define RXF_LRO_V(x) ((x) << RXF_LRO_S)
1135 #define RXF_LRO_F RXF_LRO_V(1U)
1136
1137 /* rx_pkt.l2info fields */
1138 #define RX_ETHHDR_LEN_S 0
1139 #define RX_ETHHDR_LEN_M 0x1F
1140 #define RX_ETHHDR_LEN_V(x) ((x) << RX_ETHHDR_LEN_S)
1141 #define RX_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_ETHHDR_LEN_M)
1142
1143 #define RX_T5_ETHHDR_LEN_S 0
1144 #define RX_T5_ETHHDR_LEN_M 0x3F
1145 #define RX_T5_ETHHDR_LEN_V(x) ((x) << RX_T5_ETHHDR_LEN_S)
1146 #define RX_T5_ETHHDR_LEN_G(x) (((x) >> RX_T5_ETHHDR_LEN_S) & RX_T5_ETHHDR_LEN_M)
1147
1148 #define RX_MACIDX_S 8
1149 #define RX_MACIDX_M 0x1FF
1150 #define RX_MACIDX_V(x) ((x) << RX_MACIDX_S)
1151 #define RX_MACIDX_G(x) (((x) >> RX_MACIDX_S) & RX_MACIDX_M)
1152
1153 #define RXF_SYN_S 21
1154 #define RXF_SYN_V(x) ((x) << RXF_SYN_S)
1155 #define RXF_SYN_F RXF_SYN_V(1U)
1156
1157 #define RX_CHAN_S 28
1158 #define RX_CHAN_M 0xF
1159 #define RX_CHAN_V(x) ((x) << RX_CHAN_S)
1160 #define RX_CHAN_G(x) (((x) >> RX_CHAN_S) & RX_CHAN_M)
1161
1162 /* rx_pkt.hdr_len fields */
1163 #define RX_TCPHDR_LEN_S 0
1164 #define RX_TCPHDR_LEN_M 0x3F
1165 #define RX_TCPHDR_LEN_V(x) ((x) << RX_TCPHDR_LEN_S)
1166 #define RX_TCPHDR_LEN_G(x) (((x) >> RX_TCPHDR_LEN_S) & RX_TCPHDR_LEN_M)
1167
1168 #define RX_IPHDR_LEN_S 6
1169 #define RX_IPHDR_LEN_M 0x3FF
1170 #define RX_IPHDR_LEN_V(x) ((x) << RX_IPHDR_LEN_S)
1171 #define RX_IPHDR_LEN_G(x) (((x) >> RX_IPHDR_LEN_S) & RX_IPHDR_LEN_M)
1172
1173 /* rx_pkt.err_vec fields */
1174 #define RXERR_CSUM_S 13
1175 #define RXERR_CSUM_V(x) ((x) << RXERR_CSUM_S)
1176 #define RXERR_CSUM_F RXERR_CSUM_V(1U)
1177
1178 #define T6_COMPR_RXERR_LEN_S 1
1179 #define T6_COMPR_RXERR_LEN_V(x) ((x) << T6_COMPR_RXERR_LEN_S)
1180 #define T6_COMPR_RXERR_LEN_F T6_COMPR_RXERR_LEN_V(1U)
1181
1182 #define T6_COMPR_RXERR_VEC_S 0
1183 #define T6_COMPR_RXERR_VEC_M 0x3F
1184 #define T6_COMPR_RXERR_VEC_V(x) ((x) << T6_COMPR_RXERR_LEN_S)
1185 #define T6_COMPR_RXERR_VEC_G(x) \
1186 (((x) >> T6_COMPR_RXERR_VEC_S) & T6_COMPR_RXERR_VEC_M)
1187
1188 /* Logical OR of RX_ERROR_CSUM, RX_ERROR_CSIP */
1189 #define T6_COMPR_RXERR_SUM_S 4
1190 #define T6_COMPR_RXERR_SUM_V(x) ((x) << T6_COMPR_RXERR_SUM_S)
1191 #define T6_COMPR_RXERR_SUM_F T6_COMPR_RXERR_SUM_V(1U)
1192
1193 struct cpl_trace_pkt {
1194 u8 opcode;
1195 u8 intf;
1196 #if defined(__LITTLE_ENDIAN_BITFIELD)
1197 u8 runt:4;
1198 u8 filter_hit:4;
1199 u8 :6;
1200 u8 err:1;
1201 u8 trunc:1;
1202 #else
1203 u8 filter_hit:4;
1204 u8 runt:4;
1205 u8 trunc:1;
1206 u8 err:1;
1207 u8 :6;
1208 #endif
1209 __be16 rsvd;
1210 __be16 len;
1211 __be64 tstamp;
1212 };
1213
1214 struct cpl_t5_trace_pkt {
1215 __u8 opcode;
1216 __u8 intf;
1217 #if defined(__LITTLE_ENDIAN_BITFIELD)
1218 __u8 runt:4;
1219 __u8 filter_hit:4;
1220 __u8:6;
1221 __u8 err:1;
1222 __u8 trunc:1;
1223 #else
1224 __u8 filter_hit:4;
1225 __u8 runt:4;
1226 __u8 trunc:1;
1227 __u8 err:1;
1228 __u8:6;
1229 #endif
1230 __be16 rsvd;
1231 __be16 len;
1232 __be64 tstamp;
1233 __be64 rsvd1;
1234 };
1235
1236 struct cpl_l2t_write_req {
1237 WR_HDR;
1238 union opcode_tid ot;
1239 __be16 params;
1240 __be16 l2t_idx;
1241 __be16 vlan;
1242 u8 dst_mac[6];
1243 };
1244
1245 /* cpl_l2t_write_req.params fields */
1246 #define L2T_W_INFO_S 2
1247 #define L2T_W_INFO_V(x) ((x) << L2T_W_INFO_S)
1248
1249 #define L2T_W_PORT_S 8
1250 #define L2T_W_PORT_V(x) ((x) << L2T_W_PORT_S)
1251
1252 #define L2T_W_NOREPLY_S 15
1253 #define L2T_W_NOREPLY_V(x) ((x) << L2T_W_NOREPLY_S)
1254 #define L2T_W_NOREPLY_F L2T_W_NOREPLY_V(1U)
1255
1256 #define CPL_L2T_VLAN_NONE 0xfff
1257
1258 struct cpl_l2t_write_rpl {
1259 union opcode_tid ot;
1260 u8 status;
1261 u8 rsvd[3];
1262 };
1263
1264 struct cpl_rdma_terminate {
1265 union opcode_tid ot;
1266 __be16 rsvd;
1267 __be16 len;
1268 };
1269
1270 struct cpl_sge_egr_update {
1271 __be32 opcode_qid;
1272 __be16 cidx;
1273 __be16 pidx;
1274 };
1275
1276 /* cpl_sge_egr_update.ot fields */
1277 #define EGR_QID_S 0
1278 #define EGR_QID_M 0x1FFFF
1279 #define EGR_QID_G(x) (((x) >> EGR_QID_S) & EGR_QID_M)
1280
1281 /* cpl_fw*.type values */
1282 enum {
1283 FW_TYPE_CMD_RPL = 0,
1284 FW_TYPE_WR_RPL = 1,
1285 FW_TYPE_CQE = 2,
1286 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3,
1287 FW_TYPE_RSSCPL = 4,
1288 };
1289
1290 struct cpl_fw4_pld {
1291 u8 opcode;
1292 u8 rsvd0[3];
1293 u8 type;
1294 u8 rsvd1;
1295 __be16 len;
1296 __be64 data;
1297 __be64 rsvd2;
1298 };
1299
1300 struct cpl_fw6_pld {
1301 u8 opcode;
1302 u8 rsvd[5];
1303 __be16 len;
1304 __be64 data[4];
1305 };
1306
1307 struct cpl_fw4_msg {
1308 u8 opcode;
1309 u8 type;
1310 __be16 rsvd0;
1311 __be32 rsvd1;
1312 __be64 data[2];
1313 };
1314
1315 struct cpl_fw4_ack {
1316 union opcode_tid ot;
1317 u8 credits;
1318 u8 rsvd0[2];
1319 u8 seq_vld;
1320 __be32 snd_nxt;
1321 __be32 snd_una;
1322 __be64 rsvd1;
1323 };
1324
1325 enum {
1326 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */
1327 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */
1328 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */
1329 };
1330
1331 struct cpl_fw6_msg {
1332 u8 opcode;
1333 u8 type;
1334 __be16 rsvd0;
1335 __be32 rsvd1;
1336 __be64 data[4];
1337 };
1338
1339 /* cpl_fw6_msg.type values */
1340 enum {
1341 FW6_TYPE_CMD_RPL = 0,
1342 FW6_TYPE_WR_RPL = 1,
1343 FW6_TYPE_CQE = 2,
1344 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3,
1345 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL,
1346 };
1347
1348 struct cpl_fw6_msg_ofld_connection_wr_rpl {
1349 __u64 cookie;
1350 __be32 tid; /* or atid in case of active failure */
1351 __u8 t_state;
1352 __u8 retval;
1353 __u8 rsvd[2];
1354 };
1355
1356 struct cpl_tx_data {
1357 union opcode_tid ot;
1358 __be32 len;
1359 __be32 rsvd;
1360 __be32 flags;
1361 };
1362
1363 /* cpl_tx_data.flags field */
1364 #define TX_FORCE_S 13
1365 #define TX_FORCE_V(x) ((x) << TX_FORCE_S)
1366
1367 enum {
1368 ULP_TX_MEM_READ = 2,
1369 ULP_TX_MEM_WRITE = 3,
1370 ULP_TX_PKT = 4
1371 };
1372
1373 enum {
1374 ULP_TX_SC_NOOP = 0x80,
1375 ULP_TX_SC_IMM = 0x81,
1376 ULP_TX_SC_DSGL = 0x82,
1377 ULP_TX_SC_ISGL = 0x83
1378 };
1379
1380 #define ULPTX_CMD_S 24
1381 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S)
1382
1383 struct ulptx_sge_pair {
1384 __be32 len[2];
1385 __be64 addr[2];
1386 };
1387
1388 struct ulptx_sgl {
1389 __be32 cmd_nsge;
1390 __be32 len0;
1391 __be64 addr0;
1392 struct ulptx_sge_pair sge[0];
1393 };
1394
1395 struct ulptx_idata {
1396 __be32 cmd_more;
1397 __be32 len;
1398 };
1399
1400 struct ulp_txpkt {
1401 __be32 cmd_dest;
1402 __be32 len;
1403 };
1404
1405 #define ULPTX_CMD_S 24
1406 #define ULPTX_CMD_M 0xFF
1407 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S)
1408
1409 #define ULPTX_NSGE_S 0
1410 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
1411
1412 #define ULPTX_MORE_S 23
1413 #define ULPTX_MORE_V(x) ((x) << ULPTX_MORE_S)
1414 #define ULPTX_MORE_F ULPTX_MORE_V(1U)
1415
1416 #define ULP_TXPKT_DEST_S 16
1417 #define ULP_TXPKT_DEST_M 0x3
1418 #define ULP_TXPKT_DEST_V(x) ((x) << ULP_TXPKT_DEST_S)
1419
1420 #define ULP_TXPKT_FID_S 4
1421 #define ULP_TXPKT_FID_M 0x7ff
1422 #define ULP_TXPKT_FID_V(x) ((x) << ULP_TXPKT_FID_S)
1423
1424 #define ULP_TXPKT_RO_S 3
1425 #define ULP_TXPKT_RO_V(x) ((x) << ULP_TXPKT_RO_S)
1426 #define ULP_TXPKT_RO_F ULP_TXPKT_RO_V(1U)
1427
1428 #define ULP_TX_SC_MORE_S 23
1429 #define ULP_TX_SC_MORE_V(x) ((x) << ULP_TX_SC_MORE_S)
1430 #define ULP_TX_SC_MORE_F ULP_TX_SC_MORE_V(1U)
1431
1432 struct ulp_mem_io {
1433 WR_HDR;
1434 __be32 cmd;
1435 __be32 len16; /* command length */
1436 __be32 dlen; /* data length in 32-byte units */
1437 __be32 lock_addr;
1438 };
1439
1440 #define ULP_MEMIO_LOCK_S 31
1441 #define ULP_MEMIO_LOCK_V(x) ((x) << ULP_MEMIO_LOCK_S)
1442 #define ULP_MEMIO_LOCK_F ULP_MEMIO_LOCK_V(1U)
1443
1444 /* additional ulp_mem_io.cmd fields */
1445 #define ULP_MEMIO_ORDER_S 23
1446 #define ULP_MEMIO_ORDER_V(x) ((x) << ULP_MEMIO_ORDER_S)
1447 #define ULP_MEMIO_ORDER_F ULP_MEMIO_ORDER_V(1U)
1448
1449 #define T5_ULP_MEMIO_IMM_S 23
1450 #define T5_ULP_MEMIO_IMM_V(x) ((x) << T5_ULP_MEMIO_IMM_S)
1451 #define T5_ULP_MEMIO_IMM_F T5_ULP_MEMIO_IMM_V(1U)
1452
1453 #define T5_ULP_MEMIO_ORDER_S 22
1454 #define T5_ULP_MEMIO_ORDER_V(x) ((x) << T5_ULP_MEMIO_ORDER_S)
1455 #define T5_ULP_MEMIO_ORDER_F T5_ULP_MEMIO_ORDER_V(1U)
1456
1457 #define T5_ULP_MEMIO_FID_S 4
1458 #define T5_ULP_MEMIO_FID_M 0x7ff
1459 #define T5_ULP_MEMIO_FID_V(x) ((x) << T5_ULP_MEMIO_FID_S)
1460
1461 /* ulp_mem_io.lock_addr fields */
1462 #define ULP_MEMIO_ADDR_S 0
1463 #define ULP_MEMIO_ADDR_V(x) ((x) << ULP_MEMIO_ADDR_S)
1464
1465 /* ulp_mem_io.dlen fields */
1466 #define ULP_MEMIO_DATA_LEN_S 0
1467 #define ULP_MEMIO_DATA_LEN_V(x) ((x) << ULP_MEMIO_DATA_LEN_S)
1468
1469 #define ULPTX_NSGE_S 0
1470 #define ULPTX_NSGE_M 0xFFFF
1471 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
1472 #define ULPTX_NSGE_G(x) (((x) >> ULPTX_NSGE_S) & ULPTX_NSGE_M)
1473
1474 struct ulptx_sc_memrd {
1475 __be32 cmd_to_len;
1476 __be32 addr;
1477 };
1478
1479 #define ULP_TXPKT_DATAMODIFY_S 23
1480 #define ULP_TXPKT_DATAMODIFY_M 0x1
1481 #define ULP_TXPKT_DATAMODIFY_V(x) ((x) << ULP_TXPKT_DATAMODIFY_S)
1482 #define ULP_TXPKT_DATAMODIFY_G(x) \
1483 (((x) >> ULP_TXPKT_DATAMODIFY_S) & ULP_TXPKT_DATAMODIFY__M)
1484 #define ULP_TXPKT_DATAMODIFY_F ULP_TXPKT_DATAMODIFY_V(1U)
1485
1486 #define ULP_TXPKT_CHANNELID_S 22
1487 #define ULP_TXPKT_CHANNELID_M 0x1
1488 #define ULP_TXPKT_CHANNELID_V(x) ((x) << ULP_TXPKT_CHANNELID_S)
1489 #define ULP_TXPKT_CHANNELID_G(x) \
1490 (((x) >> ULP_TXPKT_CHANNELID_S) & ULP_TXPKT_CHANNELID_M)
1491 #define ULP_TXPKT_CHANNELID_F ULP_TXPKT_CHANNELID_V(1U)
1492
1493 #define SCMD_SEQ_NO_CTRL_S 29
1494 #define SCMD_SEQ_NO_CTRL_M 0x3
1495 #define SCMD_SEQ_NO_CTRL_V(x) ((x) << SCMD_SEQ_NO_CTRL_S)
1496 #define SCMD_SEQ_NO_CTRL_G(x) \
1497 (((x) >> SCMD_SEQ_NO_CTRL_S) & SCMD_SEQ_NO_CTRL_M)
1498
1499 /* StsFieldPrsnt- Status field at the end of the TLS PDU */
1500 #define SCMD_STATUS_PRESENT_S 28
1501 #define SCMD_STATUS_PRESENT_M 0x1
1502 #define SCMD_STATUS_PRESENT_V(x) ((x) << SCMD_STATUS_PRESENT_S)
1503 #define SCMD_STATUS_PRESENT_G(x) \
1504 (((x) >> SCMD_STATUS_PRESENT_S) & SCMD_STATUS_PRESENT_M)
1505 #define SCMD_STATUS_PRESENT_F SCMD_STATUS_PRESENT_V(1U)
1506
1507 /* ProtoVersion - Protocol Version 0: 1.2, 1:1.1, 2:DTLS, 3:Generic,
1508 * 3-15: Reserved.
1509 */
1510 #define SCMD_PROTO_VERSION_S 24
1511 #define SCMD_PROTO_VERSION_M 0xf
1512 #define SCMD_PROTO_VERSION_V(x) ((x) << SCMD_PROTO_VERSION_S)
1513 #define SCMD_PROTO_VERSION_G(x) \
1514 (((x) >> SCMD_PROTO_VERSION_S) & SCMD_PROTO_VERSION_M)
1515
1516 /* EncDecCtrl - Encryption/Decryption Control. 0: Encrypt, 1: Decrypt */
1517 #define SCMD_ENC_DEC_CTRL_S 23
1518 #define SCMD_ENC_DEC_CTRL_M 0x1
1519 #define SCMD_ENC_DEC_CTRL_V(x) ((x) << SCMD_ENC_DEC_CTRL_S)
1520 #define SCMD_ENC_DEC_CTRL_G(x) \
1521 (((x) >> SCMD_ENC_DEC_CTRL_S) & SCMD_ENC_DEC_CTRL_M)
1522 #define SCMD_ENC_DEC_CTRL_F SCMD_ENC_DEC_CTRL_V(1U)
1523
1524 /* CipherAuthSeqCtrl - Cipher Authentication Sequence Control. */
1525 #define SCMD_CIPH_AUTH_SEQ_CTRL_S 22
1526 #define SCMD_CIPH_AUTH_SEQ_CTRL_M 0x1
1527 #define SCMD_CIPH_AUTH_SEQ_CTRL_V(x) \
1528 ((x) << SCMD_CIPH_AUTH_SEQ_CTRL_S)
1529 #define SCMD_CIPH_AUTH_SEQ_CTRL_G(x) \
1530 (((x) >> SCMD_CIPH_AUTH_SEQ_CTRL_S) & SCMD_CIPH_AUTH_SEQ_CTRL_M)
1531 #define SCMD_CIPH_AUTH_SEQ_CTRL_F SCMD_CIPH_AUTH_SEQ_CTRL_V(1U)
1532
1533 /* CiphMode - Cipher Mode. 0: NOP, 1:AES-CBC, 2:AES-GCM, 3:AES-CTR,
1534 * 4:Generic-AES, 5-15: Reserved.
1535 */
1536 #define SCMD_CIPH_MODE_S 18
1537 #define SCMD_CIPH_MODE_M 0xf
1538 #define SCMD_CIPH_MODE_V(x) ((x) << SCMD_CIPH_MODE_S)
1539 #define SCMD_CIPH_MODE_G(x) \
1540 (((x) >> SCMD_CIPH_MODE_S) & SCMD_CIPH_MODE_M)
1541
1542 /* AuthMode - Auth Mode. 0: NOP, 1:SHA1, 2:SHA2-224, 3:SHA2-256
1543 * 4-15: Reserved
1544 */
1545 #define SCMD_AUTH_MODE_S 14
1546 #define SCMD_AUTH_MODE_M 0xf
1547 #define SCMD_AUTH_MODE_V(x) ((x) << SCMD_AUTH_MODE_S)
1548 #define SCMD_AUTH_MODE_G(x) \
1549 (((x) >> SCMD_AUTH_MODE_S) & SCMD_AUTH_MODE_M)
1550
1551 /* HmacCtrl - HMAC Control. 0:NOP, 1:No truncation, 2:Support HMAC Truncation
1552 * per RFC 4366, 3:IPSec 96 bits, 4-7:Reserved
1553 */
1554 #define SCMD_HMAC_CTRL_S 11
1555 #define SCMD_HMAC_CTRL_M 0x7
1556 #define SCMD_HMAC_CTRL_V(x) ((x) << SCMD_HMAC_CTRL_S)
1557 #define SCMD_HMAC_CTRL_G(x) \
1558 (((x) >> SCMD_HMAC_CTRL_S) & SCMD_HMAC_CTRL_M)
1559
1560 /* IvSize - IV size in units of 2 bytes */
1561 #define SCMD_IV_SIZE_S 7
1562 #define SCMD_IV_SIZE_M 0xf
1563 #define SCMD_IV_SIZE_V(x) ((x) << SCMD_IV_SIZE_S)
1564 #define SCMD_IV_SIZE_G(x) \
1565 (((x) >> SCMD_IV_SIZE_S) & SCMD_IV_SIZE_M)
1566
1567 /* NumIVs - Number of IVs */
1568 #define SCMD_NUM_IVS_S 0
1569 #define SCMD_NUM_IVS_M 0x7f
1570 #define SCMD_NUM_IVS_V(x) ((x) << SCMD_NUM_IVS_S)
1571 #define SCMD_NUM_IVS_G(x) \
1572 (((x) >> SCMD_NUM_IVS_S) & SCMD_NUM_IVS_M)
1573
1574 /* EnbDbgId - If this is enabled upper 20 (63:44) bits if SeqNumber
1575 * (below) are used as Cid (connection id for debug status), these
1576 * bits are padded to zero for forming the 64 bit
1577 * sequence number for TLS
1578 */
1579 #define SCMD_ENB_DBGID_S 31
1580 #define SCMD_ENB_DBGID_M 0x1
1581 #define SCMD_ENB_DBGID_V(x) ((x) << SCMD_ENB_DBGID_S)
1582 #define SCMD_ENB_DBGID_G(x) \
1583 (((x) >> SCMD_ENB_DBGID_S) & SCMD_ENB_DBGID_M)
1584
1585 /* IV generation in SW. */
1586 #define SCMD_IV_GEN_CTRL_S 30
1587 #define SCMD_IV_GEN_CTRL_M 0x1
1588 #define SCMD_IV_GEN_CTRL_V(x) ((x) << SCMD_IV_GEN_CTRL_S)
1589 #define SCMD_IV_GEN_CTRL_G(x) \
1590 (((x) >> SCMD_IV_GEN_CTRL_S) & SCMD_IV_GEN_CTRL_M)
1591 #define SCMD_IV_GEN_CTRL_F SCMD_IV_GEN_CTRL_V(1U)
1592
1593 /* More frags */
1594 #define SCMD_MORE_FRAGS_S 20
1595 #define SCMD_MORE_FRAGS_M 0x1
1596 #define SCMD_MORE_FRAGS_V(x) ((x) << SCMD_MORE_FRAGS_S)
1597 #define SCMD_MORE_FRAGS_G(x) (((x) >> SCMD_MORE_FRAGS_S) & SCMD_MORE_FRAGS_M)
1598
1599 /*last frag */
1600 #define SCMD_LAST_FRAG_S 19
1601 #define SCMD_LAST_FRAG_M 0x1
1602 #define SCMD_LAST_FRAG_V(x) ((x) << SCMD_LAST_FRAG_S)
1603 #define SCMD_LAST_FRAG_G(x) (((x) >> SCMD_LAST_FRAG_S) & SCMD_LAST_FRAG_M)
1604
1605 /* TlsCompPdu */
1606 #define SCMD_TLS_COMPPDU_S 18
1607 #define SCMD_TLS_COMPPDU_M 0x1
1608 #define SCMD_TLS_COMPPDU_V(x) ((x) << SCMD_TLS_COMPPDU_S)
1609 #define SCMD_TLS_COMPPDU_G(x) (((x) >> SCMD_TLS_COMPPDU_S) & SCMD_TLS_COMPPDU_M)
1610
1611 /* KeyCntxtInline - Key context inline after the scmd OR PayloadOnly*/
1612 #define SCMD_KEY_CTX_INLINE_S 17
1613 #define SCMD_KEY_CTX_INLINE_M 0x1
1614 #define SCMD_KEY_CTX_INLINE_V(x) ((x) << SCMD_KEY_CTX_INLINE_S)
1615 #define SCMD_KEY_CTX_INLINE_G(x) \
1616 (((x) >> SCMD_KEY_CTX_INLINE_S) & SCMD_KEY_CTX_INLINE_M)
1617 #define SCMD_KEY_CTX_INLINE_F SCMD_KEY_CTX_INLINE_V(1U)
1618
1619 /* TLSFragEnable - 0: Host created TLS PDUs, 1: TLS Framgmentation in ASIC */
1620 #define SCMD_TLS_FRAG_ENABLE_S 16
1621 #define SCMD_TLS_FRAG_ENABLE_M 0x1
1622 #define SCMD_TLS_FRAG_ENABLE_V(x) ((x) << SCMD_TLS_FRAG_ENABLE_S)
1623 #define SCMD_TLS_FRAG_ENABLE_G(x) \
1624 (((x) >> SCMD_TLS_FRAG_ENABLE_S) & SCMD_TLS_FRAG_ENABLE_M)
1625 #define SCMD_TLS_FRAG_ENABLE_F SCMD_TLS_FRAG_ENABLE_V(1U)
1626
1627 /* MacOnly - Only send the MAC and discard PDU. This is valid for hash only
1628 * modes, in this case TLS_TX will drop the PDU and only
1629 * send back the MAC bytes.
1630 */
1631 #define SCMD_MAC_ONLY_S 15
1632 #define SCMD_MAC_ONLY_M 0x1
1633 #define SCMD_MAC_ONLY_V(x) ((x) << SCMD_MAC_ONLY_S)
1634 #define SCMD_MAC_ONLY_G(x) \
1635 (((x) >> SCMD_MAC_ONLY_S) & SCMD_MAC_ONLY_M)
1636 #define SCMD_MAC_ONLY_F SCMD_MAC_ONLY_V(1U)
1637
1638 /* AadIVDrop - Drop the AAD and IV fields. Useful in protocols
1639 * which have complex AAD and IV formations Eg:AES-CCM
1640 */
1641 #define SCMD_AADIVDROP_S 14
1642 #define SCMD_AADIVDROP_M 0x1
1643 #define SCMD_AADIVDROP_V(x) ((x) << SCMD_AADIVDROP_S)
1644 #define SCMD_AADIVDROP_G(x) \
1645 (((x) >> SCMD_AADIVDROP_S) & SCMD_AADIVDROP_M)
1646 #define SCMD_AADIVDROP_F SCMD_AADIVDROP_V(1U)
1647
1648 /* HdrLength - Length of all headers excluding TLS header
1649 * present before start of crypto PDU/payload.
1650 */
1651 #define SCMD_HDR_LEN_S 0
1652 #define SCMD_HDR_LEN_M 0x3fff
1653 #define SCMD_HDR_LEN_V(x) ((x) << SCMD_HDR_LEN_S)
1654 #define SCMD_HDR_LEN_G(x) \
1655 (((x) >> SCMD_HDR_LEN_S) & SCMD_HDR_LEN_M)
1656
1657 struct cpl_tx_sec_pdu {
1658 __be32 op_ivinsrtofst;
1659 __be32 pldlen;
1660 __be32 aadstart_cipherstop_hi;
1661 __be32 cipherstop_lo_authinsert;
1662 __be32 seqno_numivs;
1663 __be32 ivgen_hdrlen;
1664 __be64 scmd1;
1665 };
1666
1667 #define CPL_TX_SEC_PDU_OPCODE_S 24
1668 #define CPL_TX_SEC_PDU_OPCODE_M 0xff
1669 #define CPL_TX_SEC_PDU_OPCODE_V(x) ((x) << CPL_TX_SEC_PDU_OPCODE_S)
1670 #define CPL_TX_SEC_PDU_OPCODE_G(x) \
1671 (((x) >> CPL_TX_SEC_PDU_OPCODE_S) & CPL_TX_SEC_PDU_OPCODE_M)
1672
1673 /* RX Channel Id */
1674 #define CPL_TX_SEC_PDU_RXCHID_S 22
1675 #define CPL_TX_SEC_PDU_RXCHID_M 0x1
1676 #define CPL_TX_SEC_PDU_RXCHID_V(x) ((x) << CPL_TX_SEC_PDU_RXCHID_S)
1677 #define CPL_TX_SEC_PDU_RXCHID_G(x) \
1678 (((x) >> CPL_TX_SEC_PDU_RXCHID_S) & CPL_TX_SEC_PDU_RXCHID_M)
1679 #define CPL_TX_SEC_PDU_RXCHID_F CPL_TX_SEC_PDU_RXCHID_V(1U)
1680
1681 /* Ack Follows */
1682 #define CPL_TX_SEC_PDU_ACKFOLLOWS_S 21
1683 #define CPL_TX_SEC_PDU_ACKFOLLOWS_M 0x1
1684 #define CPL_TX_SEC_PDU_ACKFOLLOWS_V(x) ((x) << CPL_TX_SEC_PDU_ACKFOLLOWS_S)
1685 #define CPL_TX_SEC_PDU_ACKFOLLOWS_G(x) \
1686 (((x) >> CPL_TX_SEC_PDU_ACKFOLLOWS_S) & CPL_TX_SEC_PDU_ACKFOLLOWS_M)
1687 #define CPL_TX_SEC_PDU_ACKFOLLOWS_F CPL_TX_SEC_PDU_ACKFOLLOWS_V(1U)
1688
1689 /* Loopback bit in cpl_tx_sec_pdu */
1690 #define CPL_TX_SEC_PDU_ULPTXLPBK_S 20
1691 #define CPL_TX_SEC_PDU_ULPTXLPBK_M 0x1
1692 #define CPL_TX_SEC_PDU_ULPTXLPBK_V(x) ((x) << CPL_TX_SEC_PDU_ULPTXLPBK_S)
1693 #define CPL_TX_SEC_PDU_ULPTXLPBK_G(x) \
1694 (((x) >> CPL_TX_SEC_PDU_ULPTXLPBK_S) & CPL_TX_SEC_PDU_ULPTXLPBK_M)
1695 #define CPL_TX_SEC_PDU_ULPTXLPBK_F CPL_TX_SEC_PDU_ULPTXLPBK_V(1U)
1696
1697 /* Length of cpl header encapsulated */
1698 #define CPL_TX_SEC_PDU_CPLLEN_S 16
1699 #define CPL_TX_SEC_PDU_CPLLEN_M 0xf
1700 #define CPL_TX_SEC_PDU_CPLLEN_V(x) ((x) << CPL_TX_SEC_PDU_CPLLEN_S)
1701 #define CPL_TX_SEC_PDU_CPLLEN_G(x) \
1702 (((x) >> CPL_TX_SEC_PDU_CPLLEN_S) & CPL_TX_SEC_PDU_CPLLEN_M)
1703
1704 /* PlaceHolder */
1705 #define CPL_TX_SEC_PDU_PLACEHOLDER_S 10
1706 #define CPL_TX_SEC_PDU_PLACEHOLDER_M 0x1
1707 #define CPL_TX_SEC_PDU_PLACEHOLDER_V(x) ((x) << CPL_TX_SEC_PDU_PLACEHOLDER_S)
1708 #define CPL_TX_SEC_PDU_PLACEHOLDER_G(x) \
1709 (((x) >> CPL_TX_SEC_PDU_PLACEHOLDER_S) & \
1710 CPL_TX_SEC_PDU_PLACEHOLDER_M)
1711
1712 /* IvInsrtOffset: Insertion location for IV */
1713 #define CPL_TX_SEC_PDU_IVINSRTOFST_S 0
1714 #define CPL_TX_SEC_PDU_IVINSRTOFST_M 0x3ff
1715 #define CPL_TX_SEC_PDU_IVINSRTOFST_V(x) ((x) << CPL_TX_SEC_PDU_IVINSRTOFST_S)
1716 #define CPL_TX_SEC_PDU_IVINSRTOFST_G(x) \
1717 (((x) >> CPL_TX_SEC_PDU_IVINSRTOFST_S) & \
1718 CPL_TX_SEC_PDU_IVINSRTOFST_M)
1719
1720 /* AadStartOffset: Offset in bytes for AAD start from
1721 * the first byte following the pkt headers (0-255 bytes)
1722 */
1723 #define CPL_TX_SEC_PDU_AADSTART_S 24
1724 #define CPL_TX_SEC_PDU_AADSTART_M 0xff
1725 #define CPL_TX_SEC_PDU_AADSTART_V(x) ((x) << CPL_TX_SEC_PDU_AADSTART_S)
1726 #define CPL_TX_SEC_PDU_AADSTART_G(x) \
1727 (((x) >> CPL_TX_SEC_PDU_AADSTART_S) & \
1728 CPL_TX_SEC_PDU_AADSTART_M)
1729
1730 /* AadStopOffset: offset in bytes for AAD stop/end from the first byte following
1731 * the pkt headers (0-511 bytes)
1732 */
1733 #define CPL_TX_SEC_PDU_AADSTOP_S 15
1734 #define CPL_TX_SEC_PDU_AADSTOP_M 0x1ff
1735 #define CPL_TX_SEC_PDU_AADSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AADSTOP_S)
1736 #define CPL_TX_SEC_PDU_AADSTOP_G(x) \
1737 (((x) >> CPL_TX_SEC_PDU_AADSTOP_S) & CPL_TX_SEC_PDU_AADSTOP_M)
1738
1739 /* CipherStartOffset: offset in bytes for encryption/decryption start from the
1740 * first byte following the pkt headers (0-1023 bytes)
1741 */
1742 #define CPL_TX_SEC_PDU_CIPHERSTART_S 5
1743 #define CPL_TX_SEC_PDU_CIPHERSTART_M 0x3ff
1744 #define CPL_TX_SEC_PDU_CIPHERSTART_V(x) ((x) << CPL_TX_SEC_PDU_CIPHERSTART_S)
1745 #define CPL_TX_SEC_PDU_CIPHERSTART_G(x) \
1746 (((x) >> CPL_TX_SEC_PDU_CIPHERSTART_S) & \
1747 CPL_TX_SEC_PDU_CIPHERSTART_M)
1748
1749 /* CipherStopOffset: offset in bytes for encryption/decryption end
1750 * from end of the payload of this command (0-511 bytes)
1751 */
1752 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_S 0
1753 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_M 0x1f
1754 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_V(x) \
1755 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_HI_S)
1756 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_G(x) \
1757 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_HI_S) & \
1758 CPL_TX_SEC_PDU_CIPHERSTOP_HI_M)
1759
1760 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_S 28
1761 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_M 0xf
1762 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_V(x) \
1763 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_LO_S)
1764 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_G(x) \
1765 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_LO_S) & \
1766 CPL_TX_SEC_PDU_CIPHERSTOP_LO_M)
1767
1768 /* AuthStartOffset: offset in bytes for authentication start from
1769 * the first byte following the pkt headers (0-1023)
1770 */
1771 #define CPL_TX_SEC_PDU_AUTHSTART_S 18
1772 #define CPL_TX_SEC_PDU_AUTHSTART_M 0x3ff
1773 #define CPL_TX_SEC_PDU_AUTHSTART_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTART_S)
1774 #define CPL_TX_SEC_PDU_AUTHSTART_G(x) \
1775 (((x) >> CPL_TX_SEC_PDU_AUTHSTART_S) & \
1776 CPL_TX_SEC_PDU_AUTHSTART_M)
1777
1778 /* AuthStopOffset: offset in bytes for authentication
1779 * end from end of the payload of this command (0-511 Bytes)
1780 */
1781 #define CPL_TX_SEC_PDU_AUTHSTOP_S 9
1782 #define CPL_TX_SEC_PDU_AUTHSTOP_M 0x1ff
1783 #define CPL_TX_SEC_PDU_AUTHSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTOP_S)
1784 #define CPL_TX_SEC_PDU_AUTHSTOP_G(x) \
1785 (((x) >> CPL_TX_SEC_PDU_AUTHSTOP_S) & \
1786 CPL_TX_SEC_PDU_AUTHSTOP_M)
1787
1788 /* AuthInsrtOffset: offset in bytes for authentication insertion
1789 * from end of the payload of this command (0-511 bytes)
1790 */
1791 #define CPL_TX_SEC_PDU_AUTHINSERT_S 0
1792 #define CPL_TX_SEC_PDU_AUTHINSERT_M 0x1ff
1793 #define CPL_TX_SEC_PDU_AUTHINSERT_V(x) ((x) << CPL_TX_SEC_PDU_AUTHINSERT_S)
1794 #define CPL_TX_SEC_PDU_AUTHINSERT_G(x) \
1795 (((x) >> CPL_TX_SEC_PDU_AUTHINSERT_S) & \
1796 CPL_TX_SEC_PDU_AUTHINSERT_M)
1797
1798 struct cpl_rx_phys_dsgl {
1799 __be32 op_to_tid;
1800 __be32 pcirlxorder_to_noofsgentr;
1801 struct rss_header rss_hdr_int;
1802 };
1803
1804 #define CPL_RX_PHYS_DSGL_OPCODE_S 24
1805 #define CPL_RX_PHYS_DSGL_OPCODE_M 0xff
1806 #define CPL_RX_PHYS_DSGL_OPCODE_V(x) ((x) << CPL_RX_PHYS_DSGL_OPCODE_S)
1807 #define CPL_RX_PHYS_DSGL_OPCODE_G(x) \
1808 (((x) >> CPL_RX_PHYS_DSGL_OPCODE_S) & CPL_RX_PHYS_DSGL_OPCODE_M)
1809
1810 #define CPL_RX_PHYS_DSGL_ISRDMA_S 23
1811 #define CPL_RX_PHYS_DSGL_ISRDMA_M 0x1
1812 #define CPL_RX_PHYS_DSGL_ISRDMA_V(x) ((x) << CPL_RX_PHYS_DSGL_ISRDMA_S)
1813 #define CPL_RX_PHYS_DSGL_ISRDMA_G(x) \
1814 (((x) >> CPL_RX_PHYS_DSGL_ISRDMA_S) & CPL_RX_PHYS_DSGL_ISRDMA_M)
1815 #define CPL_RX_PHYS_DSGL_ISRDMA_F CPL_RX_PHYS_DSGL_ISRDMA_V(1U)
1816
1817 #define CPL_RX_PHYS_DSGL_RSVD1_S 20
1818 #define CPL_RX_PHYS_DSGL_RSVD1_M 0x7
1819 #define CPL_RX_PHYS_DSGL_RSVD1_V(x) ((x) << CPL_RX_PHYS_DSGL_RSVD1_S)
1820 #define CPL_RX_PHYS_DSGL_RSVD1_G(x) \
1821 (((x) >> CPL_RX_PHYS_DSGL_RSVD1_S) & \
1822 CPL_RX_PHYS_DSGL_RSVD1_M)
1823
1824 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_S 31
1825 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_M 0x1
1826 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_V(x) \
1827 ((x) << CPL_RX_PHYS_DSGL_PCIRLXORDER_S)
1828 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_G(x) \
1829 (((x) >> CPL_RX_PHYS_DSGL_PCIRLXORDER_S) & \
1830 CPL_RX_PHYS_DSGL_PCIRLXORDER_M)
1831 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_F CPL_RX_PHYS_DSGL_PCIRLXORDER_V(1U)
1832
1833 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_S 30
1834 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_M 0x1
1835 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_V(x) \
1836 ((x) << CPL_RX_PHYS_DSGL_PCINOSNOOP_S)
1837 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_G(x) \
1838 (((x) >> CPL_RX_PHYS_DSGL_PCINOSNOOP_S) & \
1839 CPL_RX_PHYS_DSGL_PCINOSNOOP_M)
1840
1841 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_F CPL_RX_PHYS_DSGL_PCINOSNOOP_V(1U)
1842
1843 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_S 29
1844 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_M 0x1
1845 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_V(x) \
1846 ((x) << CPL_RX_PHYS_DSGL_PCITPHNTENB_S)
1847 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_G(x) \
1848 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNTENB_S) & \
1849 CPL_RX_PHYS_DSGL_PCITPHNTENB_M)
1850 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_F CPL_RX_PHYS_DSGL_PCITPHNTENB_V(1U)
1851
1852 #define CPL_RX_PHYS_DSGL_PCITPHNT_S 27
1853 #define CPL_RX_PHYS_DSGL_PCITPHNT_M 0x3
1854 #define CPL_RX_PHYS_DSGL_PCITPHNT_V(x) ((x) << CPL_RX_PHYS_DSGL_PCITPHNT_S)
1855 #define CPL_RX_PHYS_DSGL_PCITPHNT_G(x) \
1856 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNT_S) & \
1857 CPL_RX_PHYS_DSGL_PCITPHNT_M)
1858
1859 #define CPL_RX_PHYS_DSGL_DCAID_S 16
1860 #define CPL_RX_PHYS_DSGL_DCAID_M 0x7ff
1861 #define CPL_RX_PHYS_DSGL_DCAID_V(x) ((x) << CPL_RX_PHYS_DSGL_DCAID_S)
1862 #define CPL_RX_PHYS_DSGL_DCAID_G(x) \
1863 (((x) >> CPL_RX_PHYS_DSGL_DCAID_S) & \
1864 CPL_RX_PHYS_DSGL_DCAID_M)
1865
1866 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_S 0
1867 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_M 0xffff
1868 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_V(x) \
1869 ((x) << CPL_RX_PHYS_DSGL_NOOFSGENTR_S)
1870 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_G(x) \
1871 (((x) >> CPL_RX_PHYS_DSGL_NOOFSGENTR_S) & \
1872 CPL_RX_PHYS_DSGL_NOOFSGENTR_M)
1873
1874 #endif /* __T4_MSG_H */
Ubuntu Artful kernel mirror