2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
38 #include <linux/types.h>
41 CPL_PASS_OPEN_REQ
= 0x1,
42 CPL_PASS_ACCEPT_RPL
= 0x2,
43 CPL_ACT_OPEN_REQ
= 0x3,
44 CPL_SET_TCB_FIELD
= 0x5,
46 CPL_CLOSE_CON_REQ
= 0x8,
47 CPL_CLOSE_LISTSRV_REQ
= 0x9,
50 CPL_RX_DATA_ACK
= 0xD,
52 CPL_L2T_WRITE_REQ
= 0x12,
53 CPL_TID_RELEASE
= 0x1A,
54 CPL_TX_DATA_ISO
= 0x1F,
56 CPL_CLOSE_LISTSRV_RPL
= 0x20,
57 CPL_L2T_WRITE_RPL
= 0x23,
58 CPL_PASS_OPEN_RPL
= 0x24,
59 CPL_ACT_OPEN_RPL
= 0x25,
60 CPL_PEER_CLOSE
= 0x26,
61 CPL_ABORT_REQ_RSS
= 0x2B,
62 CPL_ABORT_RPL_RSS
= 0x2D,
64 CPL_RX_PHYS_ADDR
= 0x30,
65 CPL_CLOSE_CON_RPL
= 0x32,
68 CPL_RDMA_CQE_READ_RSP
= 0x36,
69 CPL_RDMA_CQE_ERR
= 0x37,
71 CPL_SET_TCB_RPL
= 0x3A,
73 CPL_RX_DDP_COMPLETE
= 0x3F,
75 CPL_ACT_ESTABLISH
= 0x40,
76 CPL_PASS_ESTABLISH
= 0x41,
77 CPL_RX_DATA_DDP
= 0x42,
78 CPL_PASS_ACCEPT_REQ
= 0x44,
79 CPL_RX_ISCSI_CMP
= 0x45,
80 CPL_TRACE_PKT_T5
= 0x48,
81 CPL_RX_ISCSI_DDP
= 0x49,
83 CPL_RDMA_READ_REQ
= 0x60,
85 CPL_PASS_OPEN_REQ6
= 0x81,
86 CPL_ACT_OPEN_REQ6
= 0x83,
88 CPL_TX_TLS_PDU
= 0x88,
89 CPL_TX_SEC_PDU
= 0x8A,
90 CPL_TX_TLS_ACK
= 0x8B,
92 CPL_RDMA_TERMINATE
= 0xA2,
93 CPL_RDMA_WRITE
= 0xA4,
94 CPL_SGE_EGR_UPDATE
= 0xA5,
97 CPL_ISCSI_DATA
= 0xB2,
103 CPL_RX_PHYS_DSGL
= 0xD0,
107 CPL_TX_PKT_LSO
= 0xED,
108 CPL_TX_PKT_XT
= 0xEE,
115 CPL_ERR_TCAM_PARITY
= 1,
116 CPL_ERR_TCAM_MISS
= 2,
117 CPL_ERR_TCAM_FULL
= 3,
118 CPL_ERR_BAD_LENGTH
= 15,
119 CPL_ERR_BAD_ROUTE
= 18,
120 CPL_ERR_CONN_RESET
= 20,
121 CPL_ERR_CONN_EXIST_SYNRECV
= 21,
122 CPL_ERR_CONN_EXIST
= 22,
123 CPL_ERR_ARP_MISS
= 23,
124 CPL_ERR_BAD_SYN
= 24,
125 CPL_ERR_CONN_TIMEDOUT
= 30,
126 CPL_ERR_XMIT_TIMEDOUT
= 31,
127 CPL_ERR_PERSIST_TIMEDOUT
= 32,
128 CPL_ERR_FINWAIT2_TIMEDOUT
= 33,
129 CPL_ERR_KEEPALIVE_TIMEDOUT
= 34,
130 CPL_ERR_RTX_NEG_ADVICE
= 35,
131 CPL_ERR_PERSIST_NEG_ADVICE
= 36,
132 CPL_ERR_KEEPALV_NEG_ADVICE
= 37,
133 CPL_ERR_ABORT_FAILED
= 42,
134 CPL_ERR_IWARP_FLM
= 50,
138 CPL_CONN_POLICY_AUTO
= 0,
139 CPL_CONN_POLICY_ASK
= 1,
140 CPL_CONN_POLICY_FILTER
= 2,
141 CPL_CONN_POLICY_DENY
= 3
153 ULP_CRC_HEADER
= 1 << 0,
154 ULP_CRC_DATA
= 1 << 1
158 CPL_ABORT_SEND_RST
= 0,
162 enum { /* TX_PKT_XT checksum types */
181 #define CPL_OPCODE_S 24
182 #define CPL_OPCODE_V(x) ((x) << CPL_OPCODE_S)
183 #define CPL_OPCODE_G(x) (((x) >> CPL_OPCODE_S) & 0xFF)
184 #define TID_G(x) ((x) & 0xFFFFFF)
186 /* tid is assumed to be 24-bits */
187 #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE_V(opcode) | (tid))
189 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
191 /* extract the TID from a CPL command */
192 #define GET_TID(cmd) (TID_G(be32_to_cpu(OPCODE_TID(cmd))))
194 /* partitioning of TID fields that also carry a queue id */
196 #define TID_TID_M 0x3fff
197 #define TID_TID_G(x) (((x) >> TID_TID_S) & TID_TID_M)
200 #define TID_QID_M 0x3ff
201 #define TID_QID_V(x) ((x) << TID_QID_S)
202 #define TID_QID_G(x) (((x) >> TID_QID_S) & TID_QID_M)
206 #if defined(__LITTLE_ENDIAN_BITFIELD)
225 struct work_request_hdr
{
233 #define WR_OP_V(x) ((__u64)(x) << WR_OP_S)
235 #define WR_HDR struct work_request_hdr wr
237 /* option 0 fields */
239 #define TX_CHAN_V(x) ((x) << TX_CHAN_S)
242 #define ULP_MODE_V(x) ((x) << ULP_MODE_S)
244 #define RCV_BUFSIZ_S 12
245 #define RCV_BUFSIZ_M 0x3FFU
246 #define RCV_BUFSIZ_V(x) ((x) << RCV_BUFSIZ_S)
248 #define SMAC_SEL_S 28
249 #define SMAC_SEL_V(x) ((__u64)(x) << SMAC_SEL_S)
252 #define L2T_IDX_V(x) ((__u64)(x) << L2T_IDX_S)
254 #define WND_SCALE_S 50
255 #define WND_SCALE_V(x) ((__u64)(x) << WND_SCALE_S)
257 #define KEEP_ALIVE_S 54
258 #define KEEP_ALIVE_V(x) ((__u64)(x) << KEEP_ALIVE_S)
259 #define KEEP_ALIVE_F KEEP_ALIVE_V(1ULL)
262 #define MSS_IDX_M 0xF
263 #define MSS_IDX_V(x) ((__u64)(x) << MSS_IDX_S)
264 #define MSS_IDX_G(x) (((x) >> MSS_IDX_S) & MSS_IDX_M)
266 /* option 2 fields */
267 #define RSS_QUEUE_S 0
268 #define RSS_QUEUE_M 0x3FF
269 #define RSS_QUEUE_V(x) ((x) << RSS_QUEUE_S)
270 #define RSS_QUEUE_G(x) (((x) >> RSS_QUEUE_S) & RSS_QUEUE_M)
272 #define RSS_QUEUE_VALID_S 10
273 #define RSS_QUEUE_VALID_V(x) ((x) << RSS_QUEUE_VALID_S)
274 #define RSS_QUEUE_VALID_F RSS_QUEUE_VALID_V(1U)
276 #define RX_FC_DISABLE_S 20
277 #define RX_FC_DISABLE_V(x) ((x) << RX_FC_DISABLE_S)
278 #define RX_FC_DISABLE_F RX_FC_DISABLE_V(1U)
280 #define RX_FC_VALID_S 22
281 #define RX_FC_VALID_V(x) ((x) << RX_FC_VALID_S)
282 #define RX_FC_VALID_F RX_FC_VALID_V(1U)
284 #define RX_CHANNEL_S 26
285 #define RX_CHANNEL_V(x) ((x) << RX_CHANNEL_S)
287 #define WND_SCALE_EN_S 28
288 #define WND_SCALE_EN_V(x) ((x) << WND_SCALE_EN_S)
289 #define WND_SCALE_EN_F WND_SCALE_EN_V(1U)
291 #define T5_OPT_2_VALID_S 31
292 #define T5_OPT_2_VALID_V(x) ((x) << T5_OPT_2_VALID_S)
293 #define T5_OPT_2_VALID_F T5_OPT_2_VALID_V(1U)
295 struct cpl_pass_open_req
{
306 /* option 0 fields */
308 #define NO_CONG_V(x) ((x) << NO_CONG_S)
309 #define NO_CONG_F NO_CONG_V(1U)
312 #define DELACK_V(x) ((x) << DELACK_S)
313 #define DELACK_F DELACK_V(1U)
317 #define DSCP_V(x) ((x) << DSCP_S)
318 #define DSCP_G(x) (((x) >> DSCP_S) & DSCP_M)
320 #define TCAM_BYPASS_S 48
321 #define TCAM_BYPASS_V(x) ((__u64)(x) << TCAM_BYPASS_S)
322 #define TCAM_BYPASS_F TCAM_BYPASS_V(1ULL)
325 #define NAGLE_V(x) ((__u64)(x) << NAGLE_S)
326 #define NAGLE_F NAGLE_V(1ULL)
328 /* option 1 fields */
329 #define SYN_RSS_ENABLE_S 0
330 #define SYN_RSS_ENABLE_V(x) ((x) << SYN_RSS_ENABLE_S)
331 #define SYN_RSS_ENABLE_F SYN_RSS_ENABLE_V(1U)
333 #define SYN_RSS_QUEUE_S 2
334 #define SYN_RSS_QUEUE_V(x) ((x) << SYN_RSS_QUEUE_S)
336 #define CONN_POLICY_S 22
337 #define CONN_POLICY_V(x) ((x) << CONN_POLICY_S)
339 struct cpl_pass_open_req6
{
352 struct cpl_pass_open_rpl
{
361 #if defined(__LITTLE_ENDIAN_BITFIELD)
376 struct cpl_pass_accept_req
{
384 struct tcp_options tcpopt
;
387 /* cpl_pass_accept_req.hdr_len fields */
388 #define SYN_RX_CHAN_S 0
389 #define SYN_RX_CHAN_M 0xF
390 #define SYN_RX_CHAN_V(x) ((x) << SYN_RX_CHAN_S)
391 #define SYN_RX_CHAN_G(x) (((x) >> SYN_RX_CHAN_S) & SYN_RX_CHAN_M)
393 #define TCP_HDR_LEN_S 10
394 #define TCP_HDR_LEN_M 0x3F
395 #define TCP_HDR_LEN_V(x) ((x) << TCP_HDR_LEN_S)
396 #define TCP_HDR_LEN_G(x) (((x) >> TCP_HDR_LEN_S) & TCP_HDR_LEN_M)
398 #define IP_HDR_LEN_S 16
399 #define IP_HDR_LEN_M 0x3FF
400 #define IP_HDR_LEN_V(x) ((x) << IP_HDR_LEN_S)
401 #define IP_HDR_LEN_G(x) (((x) >> IP_HDR_LEN_S) & IP_HDR_LEN_M)
403 #define ETH_HDR_LEN_S 26
404 #define ETH_HDR_LEN_M 0x1F
405 #define ETH_HDR_LEN_V(x) ((x) << ETH_HDR_LEN_S)
406 #define ETH_HDR_LEN_G(x) (((x) >> ETH_HDR_LEN_S) & ETH_HDR_LEN_M)
408 /* cpl_pass_accept_req.l2info fields */
409 #define SYN_MAC_IDX_S 0
410 #define SYN_MAC_IDX_M 0x1FF
411 #define SYN_MAC_IDX_V(x) ((x) << SYN_MAC_IDX_S)
412 #define SYN_MAC_IDX_G(x) (((x) >> SYN_MAC_IDX_S) & SYN_MAC_IDX_M)
414 #define SYN_XACT_MATCH_S 9
415 #define SYN_XACT_MATCH_V(x) ((x) << SYN_XACT_MATCH_S)
416 #define SYN_XACT_MATCH_F SYN_XACT_MATCH_V(1U)
418 #define SYN_INTF_S 12
419 #define SYN_INTF_M 0xF
420 #define SYN_INTF_V(x) ((x) << SYN_INTF_S)
421 #define SYN_INTF_G(x) (((x) >> SYN_INTF_S) & SYN_INTF_M)
423 enum { /* TCP congestion control algorithms */
430 #define CONG_CNTRL_S 14
431 #define CONG_CNTRL_M 0x3
432 #define CONG_CNTRL_V(x) ((x) << CONG_CNTRL_S)
433 #define CONG_CNTRL_G(x) (((x) >> CONG_CNTRL_S) & CONG_CNTRL_M)
436 #define T5_ISS_V(x) ((x) << T5_ISS_S)
437 #define T5_ISS_F T5_ISS_V(1U)
439 struct cpl_pass_accept_rpl
{
446 /* option 2 fields */
447 #define RX_COALESCE_VALID_S 11
448 #define RX_COALESCE_VALID_V(x) ((x) << RX_COALESCE_VALID_S)
449 #define RX_COALESCE_VALID_F RX_COALESCE_VALID_V(1U)
451 #define RX_COALESCE_S 12
452 #define RX_COALESCE_V(x) ((x) << RX_COALESCE_S)
455 #define PACE_V(x) ((x) << PACE_S)
457 #define TX_QUEUE_S 23
458 #define TX_QUEUE_M 0x7
459 #define TX_QUEUE_V(x) ((x) << TX_QUEUE_S)
460 #define TX_QUEUE_G(x) (((x) >> TX_QUEUE_S) & TX_QUEUE_M)
462 #define CCTRL_ECN_S 27
463 #define CCTRL_ECN_V(x) ((x) << CCTRL_ECN_S)
464 #define CCTRL_ECN_F CCTRL_ECN_V(1U)
466 #define TSTAMPS_EN_S 29
467 #define TSTAMPS_EN_V(x) ((x) << TSTAMPS_EN_S)
468 #define TSTAMPS_EN_F TSTAMPS_EN_V(1U)
471 #define SACK_EN_V(x) ((x) << SACK_EN_S)
472 #define SACK_EN_F SACK_EN_V(1U)
474 struct cpl_t5_pass_accept_rpl
{
483 struct cpl_act_open_req
{
495 #define FILTER_TUPLE_S 24
496 #define FILTER_TUPLE_M 0xFFFFFFFFFF
497 #define FILTER_TUPLE_V(x) ((x) << FILTER_TUPLE_S)
498 #define FILTER_TUPLE_G(x) (((x) >> FILTER_TUPLE_S) & FILTER_TUPLE_M)
499 struct cpl_t5_act_open_req
{
512 struct cpl_t6_act_open_req
{
527 struct cpl_act_open_req6
{
541 struct cpl_t5_act_open_req6
{
556 struct cpl_t6_act_open_req6
{
573 struct cpl_act_open_rpl
{
578 /* cpl_act_open_rpl.atid_status fields */
579 #define AOPEN_STATUS_S 0
580 #define AOPEN_STATUS_M 0xFF
581 #define AOPEN_STATUS_G(x) (((x) >> AOPEN_STATUS_S) & AOPEN_STATUS_M)
583 #define AOPEN_ATID_S 8
584 #define AOPEN_ATID_M 0xFFFFFF
585 #define AOPEN_ATID_G(x) (((x) >> AOPEN_ATID_S) & AOPEN_ATID_M)
587 struct cpl_pass_establish
{
597 /* cpl_pass_establish.tos_stid fields */
598 #define PASS_OPEN_TID_S 0
599 #define PASS_OPEN_TID_M 0xFFFFFF
600 #define PASS_OPEN_TID_V(x) ((x) << PASS_OPEN_TID_S)
601 #define PASS_OPEN_TID_G(x) (((x) >> PASS_OPEN_TID_S) & PASS_OPEN_TID_M)
603 #define PASS_OPEN_TOS_S 24
604 #define PASS_OPEN_TOS_M 0xFF
605 #define PASS_OPEN_TOS_V(x) ((x) << PASS_OPEN_TOS_S)
606 #define PASS_OPEN_TOS_G(x) (((x) >> PASS_OPEN_TOS_S) & PASS_OPEN_TOS_M)
608 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */
609 #define TCPOPT_WSCALE_OK_S 5
610 #define TCPOPT_WSCALE_OK_M 0x1
611 #define TCPOPT_WSCALE_OK_G(x) \
612 (((x) >> TCPOPT_WSCALE_OK_S) & TCPOPT_WSCALE_OK_M)
614 #define TCPOPT_SACK_S 6
615 #define TCPOPT_SACK_M 0x1
616 #define TCPOPT_SACK_G(x) (((x) >> TCPOPT_SACK_S) & TCPOPT_SACK_M)
618 #define TCPOPT_TSTAMP_S 7
619 #define TCPOPT_TSTAMP_M 0x1
620 #define TCPOPT_TSTAMP_G(x) (((x) >> TCPOPT_TSTAMP_S) & TCPOPT_TSTAMP_M)
622 #define TCPOPT_SND_WSCALE_S 8
623 #define TCPOPT_SND_WSCALE_M 0xF
624 #define TCPOPT_SND_WSCALE_G(x) \
625 (((x) >> TCPOPT_SND_WSCALE_S) & TCPOPT_SND_WSCALE_M)
627 #define TCPOPT_MSS_S 12
628 #define TCPOPT_MSS_M 0xF
629 #define TCPOPT_MSS_G(x) (((x) >> TCPOPT_MSS_S) & TCPOPT_MSS_M)
631 #define T6_TCP_HDR_LEN_S 8
632 #define T6_TCP_HDR_LEN_V(x) ((x) << T6_TCP_HDR_LEN_S)
633 #define T6_TCP_HDR_LEN_G(x) (((x) >> T6_TCP_HDR_LEN_S) & TCP_HDR_LEN_M)
635 #define T6_IP_HDR_LEN_S 14
636 #define T6_IP_HDR_LEN_V(x) ((x) << T6_IP_HDR_LEN_S)
637 #define T6_IP_HDR_LEN_G(x) (((x) >> T6_IP_HDR_LEN_S) & IP_HDR_LEN_M)
639 #define T6_ETH_HDR_LEN_S 24
640 #define T6_ETH_HDR_LEN_M 0xFF
641 #define T6_ETH_HDR_LEN_V(x) ((x) << T6_ETH_HDR_LEN_S)
642 #define T6_ETH_HDR_LEN_G(x) (((x) >> T6_ETH_HDR_LEN_S) & T6_ETH_HDR_LEN_M)
644 struct cpl_act_establish
{
661 /* cpl_get_tcb.reply_ctrl fields */
663 #define QUEUENO_V(x) ((x) << QUEUENO_S)
665 #define REPLY_CHAN_S 14
666 #define REPLY_CHAN_V(x) ((x) << REPLY_CHAN_S)
667 #define REPLY_CHAN_F REPLY_CHAN_V(1U)
669 #define NO_REPLY_S 15
670 #define NO_REPLY_V(x) ((x) << NO_REPLY_S)
671 #define NO_REPLY_F NO_REPLY_V(1U)
673 struct cpl_set_tcb_field
{
682 /* cpl_set_tcb_field.word_cookie fields */
684 #define TCB_WORD(x) ((x) << TCB_WORD_S)
686 #define TCB_COOKIE_S 5
687 #define TCB_COOKIE_M 0x7
688 #define TCB_COOKIE_V(x) ((x) << TCB_COOKIE_S)
689 #define TCB_COOKIE_G(x) (((x) >> TCB_COOKIE_S) & TCB_COOKIE_M)
691 struct cpl_set_tcb_rpl
{
699 struct cpl_close_con_req
{
705 struct cpl_close_con_rpl
{
713 struct cpl_close_listsvr_req
{
720 /* additional cpl_close_listsvr_req.reply_ctrl field */
721 #define LISTSVR_IPV6_S 14
722 #define LISTSVR_IPV6_V(x) ((x) << LISTSVR_IPV6_S)
723 #define LISTSVR_IPV6_F LISTSVR_IPV6_V(1U)
725 struct cpl_close_listsvr_rpl
{
731 struct cpl_abort_req_rss
{
737 struct cpl_abort_req
{
746 struct cpl_abort_rpl_rss
{
752 struct cpl_abort_rpl
{
761 struct cpl_peer_close
{
766 struct cpl_tid_release
{
772 struct cpl_tx_pkt_core
{
781 struct cpl_tx_pkt_core c
;
784 #define cpl_tx_pkt_xt cpl_tx_pkt
786 /* cpl_tx_pkt_core.ctrl0 fields */
788 #define TXPKT_VF_V(x) ((x) << TXPKT_VF_S)
791 #define TXPKT_PF_V(x) ((x) << TXPKT_PF_S)
793 #define TXPKT_VF_VLD_S 11
794 #define TXPKT_VF_VLD_V(x) ((x) << TXPKT_VF_VLD_S)
795 #define TXPKT_VF_VLD_F TXPKT_VF_VLD_V(1U)
797 #define TXPKT_OVLAN_IDX_S 12
798 #define TXPKT_OVLAN_IDX_V(x) ((x) << TXPKT_OVLAN_IDX_S)
800 #define TXPKT_T5_OVLAN_IDX_S 12
801 #define TXPKT_T5_OVLAN_IDX_V(x) ((x) << TXPKT_T5_OVLAN_IDX_S)
803 #define TXPKT_INTF_S 16
804 #define TXPKT_INTF_V(x) ((x) << TXPKT_INTF_S)
806 #define TXPKT_INS_OVLAN_S 21
807 #define TXPKT_INS_OVLAN_V(x) ((x) << TXPKT_INS_OVLAN_S)
808 #define TXPKT_INS_OVLAN_F TXPKT_INS_OVLAN_V(1U)
810 #define TXPKT_OPCODE_S 24
811 #define TXPKT_OPCODE_V(x) ((x) << TXPKT_OPCODE_S)
813 /* cpl_tx_pkt_core.ctrl1 fields */
814 #define TXPKT_CSUM_END_S 12
815 #define TXPKT_CSUM_END_V(x) ((x) << TXPKT_CSUM_END_S)
817 #define TXPKT_CSUM_START_S 20
818 #define TXPKT_CSUM_START_V(x) ((x) << TXPKT_CSUM_START_S)
820 #define TXPKT_IPHDR_LEN_S 20
821 #define TXPKT_IPHDR_LEN_V(x) ((__u64)(x) << TXPKT_IPHDR_LEN_S)
823 #define TXPKT_CSUM_LOC_S 30
824 #define TXPKT_CSUM_LOC_V(x) ((__u64)(x) << TXPKT_CSUM_LOC_S)
826 #define TXPKT_ETHHDR_LEN_S 34
827 #define TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << TXPKT_ETHHDR_LEN_S)
829 #define T6_TXPKT_ETHHDR_LEN_S 32
830 #define T6_TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << T6_TXPKT_ETHHDR_LEN_S)
832 #define TXPKT_CSUM_TYPE_S 40
833 #define TXPKT_CSUM_TYPE_V(x) ((__u64)(x) << TXPKT_CSUM_TYPE_S)
835 #define TXPKT_VLAN_S 44
836 #define TXPKT_VLAN_V(x) ((__u64)(x) << TXPKT_VLAN_S)
838 #define TXPKT_VLAN_VLD_S 60
839 #define TXPKT_VLAN_VLD_V(x) ((__u64)(x) << TXPKT_VLAN_VLD_S)
840 #define TXPKT_VLAN_VLD_F TXPKT_VLAN_VLD_V(1ULL)
842 #define TXPKT_IPCSUM_DIS_S 62
843 #define TXPKT_IPCSUM_DIS_V(x) ((__u64)(x) << TXPKT_IPCSUM_DIS_S)
844 #define TXPKT_IPCSUM_DIS_F TXPKT_IPCSUM_DIS_V(1ULL)
846 #define TXPKT_L4CSUM_DIS_S 63
847 #define TXPKT_L4CSUM_DIS_V(x) ((__u64)(x) << TXPKT_L4CSUM_DIS_S)
848 #define TXPKT_L4CSUM_DIS_F TXPKT_L4CSUM_DIS_V(1ULL)
850 struct cpl_tx_pkt_lso_core
{
856 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
859 /* cpl_tx_pkt_lso_core.lso_ctrl fields */
860 #define LSO_TCPHDR_LEN_S 0
861 #define LSO_TCPHDR_LEN_V(x) ((x) << LSO_TCPHDR_LEN_S)
863 #define LSO_IPHDR_LEN_S 4
864 #define LSO_IPHDR_LEN_V(x) ((x) << LSO_IPHDR_LEN_S)
866 #define LSO_ETHHDR_LEN_S 16
867 #define LSO_ETHHDR_LEN_V(x) ((x) << LSO_ETHHDR_LEN_S)
869 #define LSO_IPV6_S 20
870 #define LSO_IPV6_V(x) ((x) << LSO_IPV6_S)
871 #define LSO_IPV6_F LSO_IPV6_V(1U)
873 #define LSO_LAST_SLICE_S 22
874 #define LSO_LAST_SLICE_V(x) ((x) << LSO_LAST_SLICE_S)
875 #define LSO_LAST_SLICE_F LSO_LAST_SLICE_V(1U)
877 #define LSO_FIRST_SLICE_S 23
878 #define LSO_FIRST_SLICE_V(x) ((x) << LSO_FIRST_SLICE_S)
879 #define LSO_FIRST_SLICE_F LSO_FIRST_SLICE_V(1U)
881 #define LSO_OPCODE_S 24
882 #define LSO_OPCODE_V(x) ((x) << LSO_OPCODE_S)
884 #define LSO_T5_XFER_SIZE_S 0
885 #define LSO_T5_XFER_SIZE_V(x) ((x) << LSO_T5_XFER_SIZE_S)
887 struct cpl_tx_pkt_lso
{
889 struct cpl_tx_pkt_lso_core c
;
890 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
893 struct cpl_iscsi_hdr
{
903 /* cpl_iscsi_hdr.pdu_len_ddp fields */
904 #define ISCSI_PDU_LEN_S 0
905 #define ISCSI_PDU_LEN_M 0x7FFF
906 #define ISCSI_PDU_LEN_V(x) ((x) << ISCSI_PDU_LEN_S)
907 #define ISCSI_PDU_LEN_G(x) (((x) >> ISCSI_PDU_LEN_S) & ISCSI_PDU_LEN_M)
909 #define ISCSI_DDP_S 15
910 #define ISCSI_DDP_V(x) ((x) << ISCSI_DDP_S)
911 #define ISCSI_DDP_F ISCSI_DDP_V(1U)
913 struct cpl_rx_data_ddp
{
926 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp
928 struct cpl_iscsi_data
{
938 struct cpl_rx_iscsi_cmp
{
950 struct cpl_tx_data_iso
{
957 __be32 reserved2_seglen_offset
;
958 __be32 datasn_offset
;
959 __be32 buffer_offset
;
962 /* encapsulated CPL_TX_DATA follows here */
965 /* cpl_tx_data_iso.op_to_scsi fields */
966 #define CPL_TX_DATA_ISO_OP_S 24
967 #define CPL_TX_DATA_ISO_OP_M 0xff
968 #define CPL_TX_DATA_ISO_OP_V(x) ((x) << CPL_TX_DATA_ISO_OP_S)
969 #define CPL_TX_DATA_ISO_OP_G(x) \
970 (((x) >> CPL_TX_DATA_ISO_OP_S) & CPL_TX_DATA_ISO_OP_M)
972 #define CPL_TX_DATA_ISO_FIRST_S 23
973 #define CPL_TX_DATA_ISO_FIRST_M 0x1
974 #define CPL_TX_DATA_ISO_FIRST_V(x) ((x) << CPL_TX_DATA_ISO_FIRST_S)
975 #define CPL_TX_DATA_ISO_FIRST_G(x) \
976 (((x) >> CPL_TX_DATA_ISO_FIRST_S) & CPL_TX_DATA_ISO_FIRST_M)
977 #define CPL_TX_DATA_ISO_FIRST_F CPL_TX_DATA_ISO_FIRST_V(1U)
979 #define CPL_TX_DATA_ISO_LAST_S 22
980 #define CPL_TX_DATA_ISO_LAST_M 0x1
981 #define CPL_TX_DATA_ISO_LAST_V(x) ((x) << CPL_TX_DATA_ISO_LAST_S)
982 #define CPL_TX_DATA_ISO_LAST_G(x) \
983 (((x) >> CPL_TX_DATA_ISO_LAST_S) & CPL_TX_DATA_ISO_LAST_M)
984 #define CPL_TX_DATA_ISO_LAST_F CPL_TX_DATA_ISO_LAST_V(1U)
986 #define CPL_TX_DATA_ISO_CPLHDRLEN_S 21
987 #define CPL_TX_DATA_ISO_CPLHDRLEN_M 0x1
988 #define CPL_TX_DATA_ISO_CPLHDRLEN_V(x) ((x) << CPL_TX_DATA_ISO_CPLHDRLEN_S)
989 #define CPL_TX_DATA_ISO_CPLHDRLEN_G(x) \
990 (((x) >> CPL_TX_DATA_ISO_CPLHDRLEN_S) & CPL_TX_DATA_ISO_CPLHDRLEN_M)
991 #define CPL_TX_DATA_ISO_CPLHDRLEN_F CPL_TX_DATA_ISO_CPLHDRLEN_V(1U)
993 #define CPL_TX_DATA_ISO_HDRCRC_S 20
994 #define CPL_TX_DATA_ISO_HDRCRC_M 0x1
995 #define CPL_TX_DATA_ISO_HDRCRC_V(x) ((x) << CPL_TX_DATA_ISO_HDRCRC_S)
996 #define CPL_TX_DATA_ISO_HDRCRC_G(x) \
997 (((x) >> CPL_TX_DATA_ISO_HDRCRC_S) & CPL_TX_DATA_ISO_HDRCRC_M)
998 #define CPL_TX_DATA_ISO_HDRCRC_F CPL_TX_DATA_ISO_HDRCRC_V(1U)
1000 #define CPL_TX_DATA_ISO_PLDCRC_S 19
1001 #define CPL_TX_DATA_ISO_PLDCRC_M 0x1
1002 #define CPL_TX_DATA_ISO_PLDCRC_V(x) ((x) << CPL_TX_DATA_ISO_PLDCRC_S)
1003 #define CPL_TX_DATA_ISO_PLDCRC_G(x) \
1004 (((x) >> CPL_TX_DATA_ISO_PLDCRC_S) & CPL_TX_DATA_ISO_PLDCRC_M)
1005 #define CPL_TX_DATA_ISO_PLDCRC_F CPL_TX_DATA_ISO_PLDCRC_V(1U)
1007 #define CPL_TX_DATA_ISO_IMMEDIATE_S 18
1008 #define CPL_TX_DATA_ISO_IMMEDIATE_M 0x1
1009 #define CPL_TX_DATA_ISO_IMMEDIATE_V(x) ((x) << CPL_TX_DATA_ISO_IMMEDIATE_S)
1010 #define CPL_TX_DATA_ISO_IMMEDIATE_G(x) \
1011 (((x) >> CPL_TX_DATA_ISO_IMMEDIATE_S) & CPL_TX_DATA_ISO_IMMEDIATE_M)
1012 #define CPL_TX_DATA_ISO_IMMEDIATE_F CPL_TX_DATA_ISO_IMMEDIATE_V(1U)
1014 #define CPL_TX_DATA_ISO_SCSI_S 16
1015 #define CPL_TX_DATA_ISO_SCSI_M 0x3
1016 #define CPL_TX_DATA_ISO_SCSI_V(x) ((x) << CPL_TX_DATA_ISO_SCSI_S)
1017 #define CPL_TX_DATA_ISO_SCSI_G(x) \
1018 (((x) >> CPL_TX_DATA_ISO_SCSI_S) & CPL_TX_DATA_ISO_SCSI_M)
1020 /* cpl_tx_data_iso.reserved2_seglen_offset fields */
1021 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_S 0
1022 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_M 0xffffff
1023 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_V(x) \
1024 ((x) << CPL_TX_DATA_ISO_SEGLEN_OFFSET_S)
1025 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_G(x) \
1026 (((x) >> CPL_TX_DATA_ISO_SEGLEN_OFFSET_S) & \
1027 CPL_TX_DATA_ISO_SEGLEN_OFFSET_M)
1029 struct cpl_rx_data
{
1030 union opcode_tid ot
;
1035 #if defined(__LITTLE_ENDIAN_BITFIELD)
1051 struct cpl_rx_data_ack
{
1053 union opcode_tid ot
;
1057 /* cpl_rx_data_ack.ack_seq fields */
1058 #define RX_CREDITS_S 0
1059 #define RX_CREDITS_V(x) ((x) << RX_CREDITS_S)
1061 #define RX_FORCE_ACK_S 28
1062 #define RX_FORCE_ACK_V(x) ((x) << RX_FORCE_ACK_S)
1063 #define RX_FORCE_ACK_F RX_FORCE_ACK_V(1U)
1065 #define RX_DACK_MODE_S 29
1066 #define RX_DACK_MODE_M 0x3
1067 #define RX_DACK_MODE_V(x) ((x) << RX_DACK_MODE_S)
1068 #define RX_DACK_MODE_G(x) (((x) >> RX_DACK_MODE_S) & RX_DACK_MODE_M)
1070 #define RX_DACK_CHANGE_S 31
1071 #define RX_DACK_CHANGE_V(x) ((x) << RX_DACK_CHANGE_S)
1072 #define RX_DACK_CHANGE_F RX_DACK_CHANGE_V(1U)
1075 struct rss_header rsshdr
;
1077 #if defined(__LITTLE_ENDIAN_BITFIELD)
1098 #define RX_T6_ETHHDR_LEN_M 0xFF
1099 #define RX_T6_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_T6_ETHHDR_LEN_M)
1101 #define RXF_PSH_S 20
1102 #define RXF_PSH_V(x) ((x) << RXF_PSH_S)
1103 #define RXF_PSH_F RXF_PSH_V(1U)
1105 #define RXF_SYN_S 21
1106 #define RXF_SYN_V(x) ((x) << RXF_SYN_S)
1107 #define RXF_SYN_F RXF_SYN_V(1U)
1109 #define RXF_UDP_S 22
1110 #define RXF_UDP_V(x) ((x) << RXF_UDP_S)
1111 #define RXF_UDP_F RXF_UDP_V(1U)
1113 #define RXF_TCP_S 23
1114 #define RXF_TCP_V(x) ((x) << RXF_TCP_S)
1115 #define RXF_TCP_F RXF_TCP_V(1U)
1118 #define RXF_IP_V(x) ((x) << RXF_IP_S)
1119 #define RXF_IP_F RXF_IP_V(1U)
1121 #define RXF_IP6_S 25
1122 #define RXF_IP6_V(x) ((x) << RXF_IP6_S)
1123 #define RXF_IP6_F RXF_IP6_V(1U)
1125 #define RXF_SYN_COOKIE_S 26
1126 #define RXF_SYN_COOKIE_V(x) ((x) << RXF_SYN_COOKIE_S)
1127 #define RXF_SYN_COOKIE_F RXF_SYN_COOKIE_V(1U)
1129 #define RXF_FCOE_S 26
1130 #define RXF_FCOE_V(x) ((x) << RXF_FCOE_S)
1131 #define RXF_FCOE_F RXF_FCOE_V(1U)
1133 #define RXF_LRO_S 27
1134 #define RXF_LRO_V(x) ((x) << RXF_LRO_S)
1135 #define RXF_LRO_F RXF_LRO_V(1U)
1137 /* rx_pkt.l2info fields */
1138 #define RX_ETHHDR_LEN_S 0
1139 #define RX_ETHHDR_LEN_M 0x1F
1140 #define RX_ETHHDR_LEN_V(x) ((x) << RX_ETHHDR_LEN_S)
1141 #define RX_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_ETHHDR_LEN_M)
1143 #define RX_T5_ETHHDR_LEN_S 0
1144 #define RX_T5_ETHHDR_LEN_M 0x3F
1145 #define RX_T5_ETHHDR_LEN_V(x) ((x) << RX_T5_ETHHDR_LEN_S)
1146 #define RX_T5_ETHHDR_LEN_G(x) (((x) >> RX_T5_ETHHDR_LEN_S) & RX_T5_ETHHDR_LEN_M)
1148 #define RX_MACIDX_S 8
1149 #define RX_MACIDX_M 0x1FF
1150 #define RX_MACIDX_V(x) ((x) << RX_MACIDX_S)
1151 #define RX_MACIDX_G(x) (((x) >> RX_MACIDX_S) & RX_MACIDX_M)
1153 #define RXF_SYN_S 21
1154 #define RXF_SYN_V(x) ((x) << RXF_SYN_S)
1155 #define RXF_SYN_F RXF_SYN_V(1U)
1157 #define RX_CHAN_S 28
1158 #define RX_CHAN_M 0xF
1159 #define RX_CHAN_V(x) ((x) << RX_CHAN_S)
1160 #define RX_CHAN_G(x) (((x) >> RX_CHAN_S) & RX_CHAN_M)
1162 /* rx_pkt.hdr_len fields */
1163 #define RX_TCPHDR_LEN_S 0
1164 #define RX_TCPHDR_LEN_M 0x3F
1165 #define RX_TCPHDR_LEN_V(x) ((x) << RX_TCPHDR_LEN_S)
1166 #define RX_TCPHDR_LEN_G(x) (((x) >> RX_TCPHDR_LEN_S) & RX_TCPHDR_LEN_M)
1168 #define RX_IPHDR_LEN_S 6
1169 #define RX_IPHDR_LEN_M 0x3FF
1170 #define RX_IPHDR_LEN_V(x) ((x) << RX_IPHDR_LEN_S)
1171 #define RX_IPHDR_LEN_G(x) (((x) >> RX_IPHDR_LEN_S) & RX_IPHDR_LEN_M)
1173 /* rx_pkt.err_vec fields */
1174 #define RXERR_CSUM_S 13
1175 #define RXERR_CSUM_V(x) ((x) << RXERR_CSUM_S)
1176 #define RXERR_CSUM_F RXERR_CSUM_V(1U)
1178 #define T6_COMPR_RXERR_LEN_S 1
1179 #define T6_COMPR_RXERR_LEN_V(x) ((x) << T6_COMPR_RXERR_LEN_S)
1180 #define T6_COMPR_RXERR_LEN_F T6_COMPR_RXERR_LEN_V(1U)
1182 #define T6_COMPR_RXERR_VEC_S 0
1183 #define T6_COMPR_RXERR_VEC_M 0x3F
1184 #define T6_COMPR_RXERR_VEC_V(x) ((x) << T6_COMPR_RXERR_LEN_S)
1185 #define T6_COMPR_RXERR_VEC_G(x) \
1186 (((x) >> T6_COMPR_RXERR_VEC_S) & T6_COMPR_RXERR_VEC_M)
1188 /* Logical OR of RX_ERROR_CSUM, RX_ERROR_CSIP */
1189 #define T6_COMPR_RXERR_SUM_S 4
1190 #define T6_COMPR_RXERR_SUM_V(x) ((x) << T6_COMPR_RXERR_SUM_S)
1191 #define T6_COMPR_RXERR_SUM_F T6_COMPR_RXERR_SUM_V(1U)
1193 struct cpl_trace_pkt
{
1196 #if defined(__LITTLE_ENDIAN_BITFIELD)
1214 struct cpl_t5_trace_pkt
{
1217 #if defined(__LITTLE_ENDIAN_BITFIELD)
1236 struct cpl_l2t_write_req
{
1238 union opcode_tid ot
;
1245 /* cpl_l2t_write_req.params fields */
1246 #define L2T_W_INFO_S 2
1247 #define L2T_W_INFO_V(x) ((x) << L2T_W_INFO_S)
1249 #define L2T_W_PORT_S 8
1250 #define L2T_W_PORT_V(x) ((x) << L2T_W_PORT_S)
1252 #define L2T_W_NOREPLY_S 15
1253 #define L2T_W_NOREPLY_V(x) ((x) << L2T_W_NOREPLY_S)
1254 #define L2T_W_NOREPLY_F L2T_W_NOREPLY_V(1U)
1256 #define CPL_L2T_VLAN_NONE 0xfff
1258 struct cpl_l2t_write_rpl
{
1259 union opcode_tid ot
;
1264 struct cpl_rdma_terminate
{
1265 union opcode_tid ot
;
1270 struct cpl_sge_egr_update
{
1276 /* cpl_sge_egr_update.ot fields */
1278 #define EGR_QID_M 0x1FFFF
1279 #define EGR_QID_G(x) (((x) >> EGR_QID_S) & EGR_QID_M)
1281 /* cpl_fw*.type values */
1283 FW_TYPE_CMD_RPL
= 0,
1286 FW_TYPE_OFLD_CONNECTION_WR_RPL
= 3,
1290 struct cpl_fw4_pld
{
1300 struct cpl_fw6_pld
{
1307 struct cpl_fw4_msg
{
1315 struct cpl_fw4_ack
{
1316 union opcode_tid ot
;
1326 CPL_FW4_ACK_FLAGS_SEQVAL
= 0x1, /* seqn valid */
1327 CPL_FW4_ACK_FLAGS_CH
= 0x2, /* channel change complete */
1328 CPL_FW4_ACK_FLAGS_FLOWC
= 0x4, /* fw_flowc_wr complete */
1331 struct cpl_fw6_msg
{
1339 /* cpl_fw6_msg.type values */
1341 FW6_TYPE_CMD_RPL
= 0,
1342 FW6_TYPE_WR_RPL
= 1,
1344 FW6_TYPE_OFLD_CONNECTION_WR_RPL
= 3,
1345 FW6_TYPE_RSSCPL
= FW_TYPE_RSSCPL
,
1348 struct cpl_fw6_msg_ofld_connection_wr_rpl
{
1350 __be32 tid
; /* or atid in case of active failure */
1356 struct cpl_tx_data
{
1357 union opcode_tid ot
;
1363 /* cpl_tx_data.flags field */
1364 #define TX_FORCE_S 13
1365 #define TX_FORCE_V(x) ((x) << TX_FORCE_S)
1368 ULP_TX_MEM_READ
= 2,
1369 ULP_TX_MEM_WRITE
= 3,
1374 ULP_TX_SC_NOOP
= 0x80,
1375 ULP_TX_SC_IMM
= 0x81,
1376 ULP_TX_SC_DSGL
= 0x82,
1377 ULP_TX_SC_ISGL
= 0x83
1380 #define ULPTX_CMD_S 24
1381 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S)
1383 struct ulptx_sge_pair
{
1392 struct ulptx_sge_pair sge
[0];
1395 struct ulptx_idata
{
1405 #define ULPTX_CMD_S 24
1406 #define ULPTX_CMD_M 0xFF
1407 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S)
1409 #define ULPTX_NSGE_S 0
1410 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
1412 #define ULPTX_MORE_S 23
1413 #define ULPTX_MORE_V(x) ((x) << ULPTX_MORE_S)
1414 #define ULPTX_MORE_F ULPTX_MORE_V(1U)
1416 #define ULP_TXPKT_DEST_S 16
1417 #define ULP_TXPKT_DEST_M 0x3
1418 #define ULP_TXPKT_DEST_V(x) ((x) << ULP_TXPKT_DEST_S)
1420 #define ULP_TXPKT_FID_S 4
1421 #define ULP_TXPKT_FID_M 0x7ff
1422 #define ULP_TXPKT_FID_V(x) ((x) << ULP_TXPKT_FID_S)
1424 #define ULP_TXPKT_RO_S 3
1425 #define ULP_TXPKT_RO_V(x) ((x) << ULP_TXPKT_RO_S)
1426 #define ULP_TXPKT_RO_F ULP_TXPKT_RO_V(1U)
1428 #define ULP_TX_SC_MORE_S 23
1429 #define ULP_TX_SC_MORE_V(x) ((x) << ULP_TX_SC_MORE_S)
1430 #define ULP_TX_SC_MORE_F ULP_TX_SC_MORE_V(1U)
1435 __be32 len16
; /* command length */
1436 __be32 dlen
; /* data length in 32-byte units */
1440 #define ULP_MEMIO_LOCK_S 31
1441 #define ULP_MEMIO_LOCK_V(x) ((x) << ULP_MEMIO_LOCK_S)
1442 #define ULP_MEMIO_LOCK_F ULP_MEMIO_LOCK_V(1U)
1444 /* additional ulp_mem_io.cmd fields */
1445 #define ULP_MEMIO_ORDER_S 23
1446 #define ULP_MEMIO_ORDER_V(x) ((x) << ULP_MEMIO_ORDER_S)
1447 #define ULP_MEMIO_ORDER_F ULP_MEMIO_ORDER_V(1U)
1449 #define T5_ULP_MEMIO_IMM_S 23
1450 #define T5_ULP_MEMIO_IMM_V(x) ((x) << T5_ULP_MEMIO_IMM_S)
1451 #define T5_ULP_MEMIO_IMM_F T5_ULP_MEMIO_IMM_V(1U)
1453 #define T5_ULP_MEMIO_ORDER_S 22
1454 #define T5_ULP_MEMIO_ORDER_V(x) ((x) << T5_ULP_MEMIO_ORDER_S)
1455 #define T5_ULP_MEMIO_ORDER_F T5_ULP_MEMIO_ORDER_V(1U)
1457 #define T5_ULP_MEMIO_FID_S 4
1458 #define T5_ULP_MEMIO_FID_M 0x7ff
1459 #define T5_ULP_MEMIO_FID_V(x) ((x) << T5_ULP_MEMIO_FID_S)
1461 /* ulp_mem_io.lock_addr fields */
1462 #define ULP_MEMIO_ADDR_S 0
1463 #define ULP_MEMIO_ADDR_V(x) ((x) << ULP_MEMIO_ADDR_S)
1465 /* ulp_mem_io.dlen fields */
1466 #define ULP_MEMIO_DATA_LEN_S 0
1467 #define ULP_MEMIO_DATA_LEN_V(x) ((x) << ULP_MEMIO_DATA_LEN_S)
1469 #define ULPTX_NSGE_S 0
1470 #define ULPTX_NSGE_M 0xFFFF
1471 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
1472 #define ULPTX_NSGE_G(x) (((x) >> ULPTX_NSGE_S) & ULPTX_NSGE_M)
1474 struct ulptx_sc_memrd
{
1479 #define ULP_TXPKT_DATAMODIFY_S 23
1480 #define ULP_TXPKT_DATAMODIFY_M 0x1
1481 #define ULP_TXPKT_DATAMODIFY_V(x) ((x) << ULP_TXPKT_DATAMODIFY_S)
1482 #define ULP_TXPKT_DATAMODIFY_G(x) \
1483 (((x) >> ULP_TXPKT_DATAMODIFY_S) & ULP_TXPKT_DATAMODIFY__M)
1484 #define ULP_TXPKT_DATAMODIFY_F ULP_TXPKT_DATAMODIFY_V(1U)
1486 #define ULP_TXPKT_CHANNELID_S 22
1487 #define ULP_TXPKT_CHANNELID_M 0x1
1488 #define ULP_TXPKT_CHANNELID_V(x) ((x) << ULP_TXPKT_CHANNELID_S)
1489 #define ULP_TXPKT_CHANNELID_G(x) \
1490 (((x) >> ULP_TXPKT_CHANNELID_S) & ULP_TXPKT_CHANNELID_M)
1491 #define ULP_TXPKT_CHANNELID_F ULP_TXPKT_CHANNELID_V(1U)
1493 #define SCMD_SEQ_NO_CTRL_S 29
1494 #define SCMD_SEQ_NO_CTRL_M 0x3
1495 #define SCMD_SEQ_NO_CTRL_V(x) ((x) << SCMD_SEQ_NO_CTRL_S)
1496 #define SCMD_SEQ_NO_CTRL_G(x) \
1497 (((x) >> SCMD_SEQ_NO_CTRL_S) & SCMD_SEQ_NO_CTRL_M)
1499 /* StsFieldPrsnt- Status field at the end of the TLS PDU */
1500 #define SCMD_STATUS_PRESENT_S 28
1501 #define SCMD_STATUS_PRESENT_M 0x1
1502 #define SCMD_STATUS_PRESENT_V(x) ((x) << SCMD_STATUS_PRESENT_S)
1503 #define SCMD_STATUS_PRESENT_G(x) \
1504 (((x) >> SCMD_STATUS_PRESENT_S) & SCMD_STATUS_PRESENT_M)
1505 #define SCMD_STATUS_PRESENT_F SCMD_STATUS_PRESENT_V(1U)
1507 /* ProtoVersion - Protocol Version 0: 1.2, 1:1.1, 2:DTLS, 3:Generic,
1510 #define SCMD_PROTO_VERSION_S 24
1511 #define SCMD_PROTO_VERSION_M 0xf
1512 #define SCMD_PROTO_VERSION_V(x) ((x) << SCMD_PROTO_VERSION_S)
1513 #define SCMD_PROTO_VERSION_G(x) \
1514 (((x) >> SCMD_PROTO_VERSION_S) & SCMD_PROTO_VERSION_M)
1516 /* EncDecCtrl - Encryption/Decryption Control. 0: Encrypt, 1: Decrypt */
1517 #define SCMD_ENC_DEC_CTRL_S 23
1518 #define SCMD_ENC_DEC_CTRL_M 0x1
1519 #define SCMD_ENC_DEC_CTRL_V(x) ((x) << SCMD_ENC_DEC_CTRL_S)
1520 #define SCMD_ENC_DEC_CTRL_G(x) \
1521 (((x) >> SCMD_ENC_DEC_CTRL_S) & SCMD_ENC_DEC_CTRL_M)
1522 #define SCMD_ENC_DEC_CTRL_F SCMD_ENC_DEC_CTRL_V(1U)
1524 /* CipherAuthSeqCtrl - Cipher Authentication Sequence Control. */
1525 #define SCMD_CIPH_AUTH_SEQ_CTRL_S 22
1526 #define SCMD_CIPH_AUTH_SEQ_CTRL_M 0x1
1527 #define SCMD_CIPH_AUTH_SEQ_CTRL_V(x) \
1528 ((x) << SCMD_CIPH_AUTH_SEQ_CTRL_S)
1529 #define SCMD_CIPH_AUTH_SEQ_CTRL_G(x) \
1530 (((x) >> SCMD_CIPH_AUTH_SEQ_CTRL_S) & SCMD_CIPH_AUTH_SEQ_CTRL_M)
1531 #define SCMD_CIPH_AUTH_SEQ_CTRL_F SCMD_CIPH_AUTH_SEQ_CTRL_V(1U)
1533 /* CiphMode - Cipher Mode. 0: NOP, 1:AES-CBC, 2:AES-GCM, 3:AES-CTR,
1534 * 4:Generic-AES, 5-15: Reserved.
1536 #define SCMD_CIPH_MODE_S 18
1537 #define SCMD_CIPH_MODE_M 0xf
1538 #define SCMD_CIPH_MODE_V(x) ((x) << SCMD_CIPH_MODE_S)
1539 #define SCMD_CIPH_MODE_G(x) \
1540 (((x) >> SCMD_CIPH_MODE_S) & SCMD_CIPH_MODE_M)
1542 /* AuthMode - Auth Mode. 0: NOP, 1:SHA1, 2:SHA2-224, 3:SHA2-256
1545 #define SCMD_AUTH_MODE_S 14
1546 #define SCMD_AUTH_MODE_M 0xf
1547 #define SCMD_AUTH_MODE_V(x) ((x) << SCMD_AUTH_MODE_S)
1548 #define SCMD_AUTH_MODE_G(x) \
1549 (((x) >> SCMD_AUTH_MODE_S) & SCMD_AUTH_MODE_M)
1551 /* HmacCtrl - HMAC Control. 0:NOP, 1:No truncation, 2:Support HMAC Truncation
1552 * per RFC 4366, 3:IPSec 96 bits, 4-7:Reserved
1554 #define SCMD_HMAC_CTRL_S 11
1555 #define SCMD_HMAC_CTRL_M 0x7
1556 #define SCMD_HMAC_CTRL_V(x) ((x) << SCMD_HMAC_CTRL_S)
1557 #define SCMD_HMAC_CTRL_G(x) \
1558 (((x) >> SCMD_HMAC_CTRL_S) & SCMD_HMAC_CTRL_M)
1560 /* IvSize - IV size in units of 2 bytes */
1561 #define SCMD_IV_SIZE_S 7
1562 #define SCMD_IV_SIZE_M 0xf
1563 #define SCMD_IV_SIZE_V(x) ((x) << SCMD_IV_SIZE_S)
1564 #define SCMD_IV_SIZE_G(x) \
1565 (((x) >> SCMD_IV_SIZE_S) & SCMD_IV_SIZE_M)
1567 /* NumIVs - Number of IVs */
1568 #define SCMD_NUM_IVS_S 0
1569 #define SCMD_NUM_IVS_M 0x7f
1570 #define SCMD_NUM_IVS_V(x) ((x) << SCMD_NUM_IVS_S)
1571 #define SCMD_NUM_IVS_G(x) \
1572 (((x) >> SCMD_NUM_IVS_S) & SCMD_NUM_IVS_M)
1574 /* EnbDbgId - If this is enabled upper 20 (63:44) bits if SeqNumber
1575 * (below) are used as Cid (connection id for debug status), these
1576 * bits are padded to zero for forming the 64 bit
1577 * sequence number for TLS
1579 #define SCMD_ENB_DBGID_S 31
1580 #define SCMD_ENB_DBGID_M 0x1
1581 #define SCMD_ENB_DBGID_V(x) ((x) << SCMD_ENB_DBGID_S)
1582 #define SCMD_ENB_DBGID_G(x) \
1583 (((x) >> SCMD_ENB_DBGID_S) & SCMD_ENB_DBGID_M)
1585 /* IV generation in SW. */
1586 #define SCMD_IV_GEN_CTRL_S 30
1587 #define SCMD_IV_GEN_CTRL_M 0x1
1588 #define SCMD_IV_GEN_CTRL_V(x) ((x) << SCMD_IV_GEN_CTRL_S)
1589 #define SCMD_IV_GEN_CTRL_G(x) \
1590 (((x) >> SCMD_IV_GEN_CTRL_S) & SCMD_IV_GEN_CTRL_M)
1591 #define SCMD_IV_GEN_CTRL_F SCMD_IV_GEN_CTRL_V(1U)
1594 #define SCMD_MORE_FRAGS_S 20
1595 #define SCMD_MORE_FRAGS_M 0x1
1596 #define SCMD_MORE_FRAGS_V(x) ((x) << SCMD_MORE_FRAGS_S)
1597 #define SCMD_MORE_FRAGS_G(x) (((x) >> SCMD_MORE_FRAGS_S) & SCMD_MORE_FRAGS_M)
1600 #define SCMD_LAST_FRAG_S 19
1601 #define SCMD_LAST_FRAG_M 0x1
1602 #define SCMD_LAST_FRAG_V(x) ((x) << SCMD_LAST_FRAG_S)
1603 #define SCMD_LAST_FRAG_G(x) (((x) >> SCMD_LAST_FRAG_S) & SCMD_LAST_FRAG_M)
1606 #define SCMD_TLS_COMPPDU_S 18
1607 #define SCMD_TLS_COMPPDU_M 0x1
1608 #define SCMD_TLS_COMPPDU_V(x) ((x) << SCMD_TLS_COMPPDU_S)
1609 #define SCMD_TLS_COMPPDU_G(x) (((x) >> SCMD_TLS_COMPPDU_S) & SCMD_TLS_COMPPDU_M)
1611 /* KeyCntxtInline - Key context inline after the scmd OR PayloadOnly*/
1612 #define SCMD_KEY_CTX_INLINE_S 17
1613 #define SCMD_KEY_CTX_INLINE_M 0x1
1614 #define SCMD_KEY_CTX_INLINE_V(x) ((x) << SCMD_KEY_CTX_INLINE_S)
1615 #define SCMD_KEY_CTX_INLINE_G(x) \
1616 (((x) >> SCMD_KEY_CTX_INLINE_S) & SCMD_KEY_CTX_INLINE_M)
1617 #define SCMD_KEY_CTX_INLINE_F SCMD_KEY_CTX_INLINE_V(1U)
1619 /* TLSFragEnable - 0: Host created TLS PDUs, 1: TLS Framgmentation in ASIC */
1620 #define SCMD_TLS_FRAG_ENABLE_S 16
1621 #define SCMD_TLS_FRAG_ENABLE_M 0x1
1622 #define SCMD_TLS_FRAG_ENABLE_V(x) ((x) << SCMD_TLS_FRAG_ENABLE_S)
1623 #define SCMD_TLS_FRAG_ENABLE_G(x) \
1624 (((x) >> SCMD_TLS_FRAG_ENABLE_S) & SCMD_TLS_FRAG_ENABLE_M)
1625 #define SCMD_TLS_FRAG_ENABLE_F SCMD_TLS_FRAG_ENABLE_V(1U)
1627 /* MacOnly - Only send the MAC and discard PDU. This is valid for hash only
1628 * modes, in this case TLS_TX will drop the PDU and only
1629 * send back the MAC bytes.
1631 #define SCMD_MAC_ONLY_S 15
1632 #define SCMD_MAC_ONLY_M 0x1
1633 #define SCMD_MAC_ONLY_V(x) ((x) << SCMD_MAC_ONLY_S)
1634 #define SCMD_MAC_ONLY_G(x) \
1635 (((x) >> SCMD_MAC_ONLY_S) & SCMD_MAC_ONLY_M)
1636 #define SCMD_MAC_ONLY_F SCMD_MAC_ONLY_V(1U)
1638 /* AadIVDrop - Drop the AAD and IV fields. Useful in protocols
1639 * which have complex AAD and IV formations Eg:AES-CCM
1641 #define SCMD_AADIVDROP_S 14
1642 #define SCMD_AADIVDROP_M 0x1
1643 #define SCMD_AADIVDROP_V(x) ((x) << SCMD_AADIVDROP_S)
1644 #define SCMD_AADIVDROP_G(x) \
1645 (((x) >> SCMD_AADIVDROP_S) & SCMD_AADIVDROP_M)
1646 #define SCMD_AADIVDROP_F SCMD_AADIVDROP_V(1U)
1648 /* HdrLength - Length of all headers excluding TLS header
1649 * present before start of crypto PDU/payload.
1651 #define SCMD_HDR_LEN_S 0
1652 #define SCMD_HDR_LEN_M 0x3fff
1653 #define SCMD_HDR_LEN_V(x) ((x) << SCMD_HDR_LEN_S)
1654 #define SCMD_HDR_LEN_G(x) \
1655 (((x) >> SCMD_HDR_LEN_S) & SCMD_HDR_LEN_M)
1657 struct cpl_tx_sec_pdu
{
1658 __be32 op_ivinsrtofst
;
1660 __be32 aadstart_cipherstop_hi
;
1661 __be32 cipherstop_lo_authinsert
;
1662 __be32 seqno_numivs
;
1663 __be32 ivgen_hdrlen
;
1667 #define CPL_TX_SEC_PDU_OPCODE_S 24
1668 #define CPL_TX_SEC_PDU_OPCODE_M 0xff
1669 #define CPL_TX_SEC_PDU_OPCODE_V(x) ((x) << CPL_TX_SEC_PDU_OPCODE_S)
1670 #define CPL_TX_SEC_PDU_OPCODE_G(x) \
1671 (((x) >> CPL_TX_SEC_PDU_OPCODE_S) & CPL_TX_SEC_PDU_OPCODE_M)
1674 #define CPL_TX_SEC_PDU_RXCHID_S 22
1675 #define CPL_TX_SEC_PDU_RXCHID_M 0x1
1676 #define CPL_TX_SEC_PDU_RXCHID_V(x) ((x) << CPL_TX_SEC_PDU_RXCHID_S)
1677 #define CPL_TX_SEC_PDU_RXCHID_G(x) \
1678 (((x) >> CPL_TX_SEC_PDU_RXCHID_S) & CPL_TX_SEC_PDU_RXCHID_M)
1679 #define CPL_TX_SEC_PDU_RXCHID_F CPL_TX_SEC_PDU_RXCHID_V(1U)
1682 #define CPL_TX_SEC_PDU_ACKFOLLOWS_S 21
1683 #define CPL_TX_SEC_PDU_ACKFOLLOWS_M 0x1
1684 #define CPL_TX_SEC_PDU_ACKFOLLOWS_V(x) ((x) << CPL_TX_SEC_PDU_ACKFOLLOWS_S)
1685 #define CPL_TX_SEC_PDU_ACKFOLLOWS_G(x) \
1686 (((x) >> CPL_TX_SEC_PDU_ACKFOLLOWS_S) & CPL_TX_SEC_PDU_ACKFOLLOWS_M)
1687 #define CPL_TX_SEC_PDU_ACKFOLLOWS_F CPL_TX_SEC_PDU_ACKFOLLOWS_V(1U)
1689 /* Loopback bit in cpl_tx_sec_pdu */
1690 #define CPL_TX_SEC_PDU_ULPTXLPBK_S 20
1691 #define CPL_TX_SEC_PDU_ULPTXLPBK_M 0x1
1692 #define CPL_TX_SEC_PDU_ULPTXLPBK_V(x) ((x) << CPL_TX_SEC_PDU_ULPTXLPBK_S)
1693 #define CPL_TX_SEC_PDU_ULPTXLPBK_G(x) \
1694 (((x) >> CPL_TX_SEC_PDU_ULPTXLPBK_S) & CPL_TX_SEC_PDU_ULPTXLPBK_M)
1695 #define CPL_TX_SEC_PDU_ULPTXLPBK_F CPL_TX_SEC_PDU_ULPTXLPBK_V(1U)
1697 /* Length of cpl header encapsulated */
1698 #define CPL_TX_SEC_PDU_CPLLEN_S 16
1699 #define CPL_TX_SEC_PDU_CPLLEN_M 0xf
1700 #define CPL_TX_SEC_PDU_CPLLEN_V(x) ((x) << CPL_TX_SEC_PDU_CPLLEN_S)
1701 #define CPL_TX_SEC_PDU_CPLLEN_G(x) \
1702 (((x) >> CPL_TX_SEC_PDU_CPLLEN_S) & CPL_TX_SEC_PDU_CPLLEN_M)
1705 #define CPL_TX_SEC_PDU_PLACEHOLDER_S 10
1706 #define CPL_TX_SEC_PDU_PLACEHOLDER_M 0x1
1707 #define CPL_TX_SEC_PDU_PLACEHOLDER_V(x) ((x) << CPL_TX_SEC_PDU_PLACEHOLDER_S)
1708 #define CPL_TX_SEC_PDU_PLACEHOLDER_G(x) \
1709 (((x) >> CPL_TX_SEC_PDU_PLACEHOLDER_S) & \
1710 CPL_TX_SEC_PDU_PLACEHOLDER_M)
1712 /* IvInsrtOffset: Insertion location for IV */
1713 #define CPL_TX_SEC_PDU_IVINSRTOFST_S 0
1714 #define CPL_TX_SEC_PDU_IVINSRTOFST_M 0x3ff
1715 #define CPL_TX_SEC_PDU_IVINSRTOFST_V(x) ((x) << CPL_TX_SEC_PDU_IVINSRTOFST_S)
1716 #define CPL_TX_SEC_PDU_IVINSRTOFST_G(x) \
1717 (((x) >> CPL_TX_SEC_PDU_IVINSRTOFST_S) & \
1718 CPL_TX_SEC_PDU_IVINSRTOFST_M)
1720 /* AadStartOffset: Offset in bytes for AAD start from
1721 * the first byte following the pkt headers (0-255 bytes)
1723 #define CPL_TX_SEC_PDU_AADSTART_S 24
1724 #define CPL_TX_SEC_PDU_AADSTART_M 0xff
1725 #define CPL_TX_SEC_PDU_AADSTART_V(x) ((x) << CPL_TX_SEC_PDU_AADSTART_S)
1726 #define CPL_TX_SEC_PDU_AADSTART_G(x) \
1727 (((x) >> CPL_TX_SEC_PDU_AADSTART_S) & \
1728 CPL_TX_SEC_PDU_AADSTART_M)
1730 /* AadStopOffset: offset in bytes for AAD stop/end from the first byte following
1731 * the pkt headers (0-511 bytes)
1733 #define CPL_TX_SEC_PDU_AADSTOP_S 15
1734 #define CPL_TX_SEC_PDU_AADSTOP_M 0x1ff
1735 #define CPL_TX_SEC_PDU_AADSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AADSTOP_S)
1736 #define CPL_TX_SEC_PDU_AADSTOP_G(x) \
1737 (((x) >> CPL_TX_SEC_PDU_AADSTOP_S) & CPL_TX_SEC_PDU_AADSTOP_M)
1739 /* CipherStartOffset: offset in bytes for encryption/decryption start from the
1740 * first byte following the pkt headers (0-1023 bytes)
1742 #define CPL_TX_SEC_PDU_CIPHERSTART_S 5
1743 #define CPL_TX_SEC_PDU_CIPHERSTART_M 0x3ff
1744 #define CPL_TX_SEC_PDU_CIPHERSTART_V(x) ((x) << CPL_TX_SEC_PDU_CIPHERSTART_S)
1745 #define CPL_TX_SEC_PDU_CIPHERSTART_G(x) \
1746 (((x) >> CPL_TX_SEC_PDU_CIPHERSTART_S) & \
1747 CPL_TX_SEC_PDU_CIPHERSTART_M)
1749 /* CipherStopOffset: offset in bytes for encryption/decryption end
1750 * from end of the payload of this command (0-511 bytes)
1752 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_S 0
1753 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_M 0x1f
1754 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_V(x) \
1755 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_HI_S)
1756 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_G(x) \
1757 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_HI_S) & \
1758 CPL_TX_SEC_PDU_CIPHERSTOP_HI_M)
1760 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_S 28
1761 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_M 0xf
1762 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_V(x) \
1763 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_LO_S)
1764 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_G(x) \
1765 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_LO_S) & \
1766 CPL_TX_SEC_PDU_CIPHERSTOP_LO_M)
1768 /* AuthStartOffset: offset in bytes for authentication start from
1769 * the first byte following the pkt headers (0-1023)
1771 #define CPL_TX_SEC_PDU_AUTHSTART_S 18
1772 #define CPL_TX_SEC_PDU_AUTHSTART_M 0x3ff
1773 #define CPL_TX_SEC_PDU_AUTHSTART_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTART_S)
1774 #define CPL_TX_SEC_PDU_AUTHSTART_G(x) \
1775 (((x) >> CPL_TX_SEC_PDU_AUTHSTART_S) & \
1776 CPL_TX_SEC_PDU_AUTHSTART_M)
1778 /* AuthStopOffset: offset in bytes for authentication
1779 * end from end of the payload of this command (0-511 Bytes)
1781 #define CPL_TX_SEC_PDU_AUTHSTOP_S 9
1782 #define CPL_TX_SEC_PDU_AUTHSTOP_M 0x1ff
1783 #define CPL_TX_SEC_PDU_AUTHSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTOP_S)
1784 #define CPL_TX_SEC_PDU_AUTHSTOP_G(x) \
1785 (((x) >> CPL_TX_SEC_PDU_AUTHSTOP_S) & \
1786 CPL_TX_SEC_PDU_AUTHSTOP_M)
1788 /* AuthInsrtOffset: offset in bytes for authentication insertion
1789 * from end of the payload of this command (0-511 bytes)
1791 #define CPL_TX_SEC_PDU_AUTHINSERT_S 0
1792 #define CPL_TX_SEC_PDU_AUTHINSERT_M 0x1ff
1793 #define CPL_TX_SEC_PDU_AUTHINSERT_V(x) ((x) << CPL_TX_SEC_PDU_AUTHINSERT_S)
1794 #define CPL_TX_SEC_PDU_AUTHINSERT_G(x) \
1795 (((x) >> CPL_TX_SEC_PDU_AUTHINSERT_S) & \
1796 CPL_TX_SEC_PDU_AUTHINSERT_M)
1798 struct cpl_rx_phys_dsgl
{
1800 __be32 pcirlxorder_to_noofsgentr
;
1801 struct rss_header rss_hdr_int
;
1804 #define CPL_RX_PHYS_DSGL_OPCODE_S 24
1805 #define CPL_RX_PHYS_DSGL_OPCODE_M 0xff
1806 #define CPL_RX_PHYS_DSGL_OPCODE_V(x) ((x) << CPL_RX_PHYS_DSGL_OPCODE_S)
1807 #define CPL_RX_PHYS_DSGL_OPCODE_G(x) \
1808 (((x) >> CPL_RX_PHYS_DSGL_OPCODE_S) & CPL_RX_PHYS_DSGL_OPCODE_M)
1810 #define CPL_RX_PHYS_DSGL_ISRDMA_S 23
1811 #define CPL_RX_PHYS_DSGL_ISRDMA_M 0x1
1812 #define CPL_RX_PHYS_DSGL_ISRDMA_V(x) ((x) << CPL_RX_PHYS_DSGL_ISRDMA_S)
1813 #define CPL_RX_PHYS_DSGL_ISRDMA_G(x) \
1814 (((x) >> CPL_RX_PHYS_DSGL_ISRDMA_S) & CPL_RX_PHYS_DSGL_ISRDMA_M)
1815 #define CPL_RX_PHYS_DSGL_ISRDMA_F CPL_RX_PHYS_DSGL_ISRDMA_V(1U)
1817 #define CPL_RX_PHYS_DSGL_RSVD1_S 20
1818 #define CPL_RX_PHYS_DSGL_RSVD1_M 0x7
1819 #define CPL_RX_PHYS_DSGL_RSVD1_V(x) ((x) << CPL_RX_PHYS_DSGL_RSVD1_S)
1820 #define CPL_RX_PHYS_DSGL_RSVD1_G(x) \
1821 (((x) >> CPL_RX_PHYS_DSGL_RSVD1_S) & \
1822 CPL_RX_PHYS_DSGL_RSVD1_M)
1824 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_S 31
1825 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_M 0x1
1826 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_V(x) \
1827 ((x) << CPL_RX_PHYS_DSGL_PCIRLXORDER_S)
1828 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_G(x) \
1829 (((x) >> CPL_RX_PHYS_DSGL_PCIRLXORDER_S) & \
1830 CPL_RX_PHYS_DSGL_PCIRLXORDER_M)
1831 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_F CPL_RX_PHYS_DSGL_PCIRLXORDER_V(1U)
1833 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_S 30
1834 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_M 0x1
1835 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_V(x) \
1836 ((x) << CPL_RX_PHYS_DSGL_PCINOSNOOP_S)
1837 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_G(x) \
1838 (((x) >> CPL_RX_PHYS_DSGL_PCINOSNOOP_S) & \
1839 CPL_RX_PHYS_DSGL_PCINOSNOOP_M)
1841 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_F CPL_RX_PHYS_DSGL_PCINOSNOOP_V(1U)
1843 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_S 29
1844 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_M 0x1
1845 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_V(x) \
1846 ((x) << CPL_RX_PHYS_DSGL_PCITPHNTENB_S)
1847 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_G(x) \
1848 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNTENB_S) & \
1849 CPL_RX_PHYS_DSGL_PCITPHNTENB_M)
1850 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_F CPL_RX_PHYS_DSGL_PCITPHNTENB_V(1U)
1852 #define CPL_RX_PHYS_DSGL_PCITPHNT_S 27
1853 #define CPL_RX_PHYS_DSGL_PCITPHNT_M 0x3
1854 #define CPL_RX_PHYS_DSGL_PCITPHNT_V(x) ((x) << CPL_RX_PHYS_DSGL_PCITPHNT_S)
1855 #define CPL_RX_PHYS_DSGL_PCITPHNT_G(x) \
1856 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNT_S) & \
1857 CPL_RX_PHYS_DSGL_PCITPHNT_M)
1859 #define CPL_RX_PHYS_DSGL_DCAID_S 16
1860 #define CPL_RX_PHYS_DSGL_DCAID_M 0x7ff
1861 #define CPL_RX_PHYS_DSGL_DCAID_V(x) ((x) << CPL_RX_PHYS_DSGL_DCAID_S)
1862 #define CPL_RX_PHYS_DSGL_DCAID_G(x) \
1863 (((x) >> CPL_RX_PHYS_DSGL_DCAID_S) & \
1864 CPL_RX_PHYS_DSGL_DCAID_M)
1866 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_S 0
1867 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_M 0xffff
1868 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_V(x) \
1869 ((x) << CPL_RX_PHYS_DSGL_NOOFSGENTR_S)
1870 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_G(x) \
1871 (((x) >> CPL_RX_PHYS_DSGL_NOOFSGENTR_S) & \
1872 CPL_RX_PHYS_DSGL_NOOFSGENTR_M)
1874 #endif /* __T4_MSG_H */