2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2009-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #ifndef _T4FW_INTERFACE_H_
36 #define _T4FW_INTERFACE_H_
39 FW_SUCCESS
= 0, /* completed successfully */
40 FW_EPERM
= 1, /* operation not permitted */
41 FW_ENOENT
= 2, /* no such file or directory */
42 FW_EIO
= 5, /* input/output error; hw bad */
43 FW_ENOEXEC
= 8, /* exec format error; inv microcode */
44 FW_EAGAIN
= 11, /* try again */
45 FW_ENOMEM
= 12, /* out of memory */
46 FW_EFAULT
= 14, /* bad address; fw bad */
47 FW_EBUSY
= 16, /* resource busy */
48 FW_EEXIST
= 17, /* file exists */
49 FW_ENODEV
= 19, /* no such device */
50 FW_EINVAL
= 22, /* invalid argument */
51 FW_ENOSPC
= 28, /* no space left on device */
52 FW_ENOSYS
= 38, /* functionality not implemented */
53 FW_ENODATA
= 61, /* no data available */
54 FW_EPROTO
= 71, /* protocol error */
55 FW_EADDRINUSE
= 98, /* address already in use */
56 FW_EADDRNOTAVAIL
= 99, /* cannot assigned requested address */
57 FW_ENETDOWN
= 100, /* network is down */
58 FW_ENETUNREACH
= 101, /* network is unreachable */
59 FW_ENOBUFS
= 105, /* no buffer space available */
60 FW_ETIMEDOUT
= 110, /* timeout */
61 FW_EINPROGRESS
= 115, /* fw internal */
62 FW_SCSI_ABORT_REQUESTED
= 128, /* */
63 FW_SCSI_ABORT_TIMEDOUT
= 129, /* */
64 FW_SCSI_ABORTED
= 130, /* */
65 FW_SCSI_CLOSE_REQUESTED
= 131, /* */
66 FW_ERR_LINK_DOWN
= 132, /* */
67 FW_RDEV_NOT_READY
= 133, /* */
68 FW_ERR_RDEV_LOST
= 134, /* */
69 FW_ERR_RDEV_LOGO
= 135, /* */
70 FW_FCOE_NO_XCHG
= 136, /* */
71 FW_SCSI_RSP_ERR
= 137, /* */
72 FW_ERR_RDEV_IMPL_LOGO
= 138, /* */
73 FW_SCSI_UNDER_FLOW_ERR
= 139, /* */
74 FW_SCSI_OVER_FLOW_ERR
= 140, /* */
75 FW_SCSI_DDP_ERR
= 141, /* DDP error*/
76 FW_SCSI_TASK_ERR
= 142, /* No SCSI tasks available */
79 #define FW_T4VF_SGE_BASE_ADDR 0x0000
80 #define FW_T4VF_MPS_BASE_ADDR 0x0100
81 #define FW_T4VF_PL_BASE_ADDR 0x0200
82 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240
83 #define FW_T4VF_CIM_BASE_ADDR 0x0300
89 FW_ETH_TX_PKT_WR
= 0x08,
90 FW_ETH_TX_EO_WR
= 0x1c,
91 FW_OFLD_CONNECTION_WR
= 0x2f,
93 FW_OFLD_TX_DATA_WR
= 0x0b,
95 FW_ETH_TX_PKT_VM_WR
= 0x11,
98 FW_RI_RDMA_WRITE_WR
= 0x14,
100 FW_RI_RDMA_READ_WR
= 0x16,
101 FW_RI_RECV_WR
= 0x17,
102 FW_RI_BIND_MW_WR
= 0x18,
103 FW_RI_FR_NSMR_WR
= 0x19,
104 FW_RI_FR_NSMR_TPTE_WR
= 0x20,
105 FW_RI_RDMA_WRITE_CMPL_WR
= 0x21,
106 FW_RI_INV_LSTAG_WR
= 0x1a,
107 FW_ISCSI_TX_DATA_WR
= 0x45,
108 FW_PTP_TX_PKT_WR
= 0x46,
109 FW_TLSTX_DATA_WR
= 0x68,
110 FW_CRYPTO_LOOKASIDE_WR
= 0X6d,
111 FW_LASTC2E_WR
= 0x70,
120 /* work request opcode (hi) */
121 #define FW_WR_OP_S 24
122 #define FW_WR_OP_M 0xff
123 #define FW_WR_OP_V(x) ((x) << FW_WR_OP_S)
124 #define FW_WR_OP_G(x) (((x) >> FW_WR_OP_S) & FW_WR_OP_M)
126 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */
127 #define FW_WR_ATOMIC_S 23
128 #define FW_WR_ATOMIC_V(x) ((x) << FW_WR_ATOMIC_S)
130 /* flush flag (hi) - firmware flushes flushable work request buffered
131 * in the flow context.
133 #define FW_WR_FLUSH_S 22
134 #define FW_WR_FLUSH_V(x) ((x) << FW_WR_FLUSH_S)
136 /* completion flag (hi) - firmware generates a cpl_fw6_ack */
137 #define FW_WR_COMPL_S 21
138 #define FW_WR_COMPL_V(x) ((x) << FW_WR_COMPL_S)
139 #define FW_WR_COMPL_F FW_WR_COMPL_V(1U)
141 /* work request immediate data length (hi) */
142 #define FW_WR_IMMDLEN_S 0
143 #define FW_WR_IMMDLEN_M 0xff
144 #define FW_WR_IMMDLEN_V(x) ((x) << FW_WR_IMMDLEN_S)
146 /* egress queue status update to associated ingress queue entry (lo) */
147 #define FW_WR_EQUIQ_S 31
148 #define FW_WR_EQUIQ_V(x) ((x) << FW_WR_EQUIQ_S)
149 #define FW_WR_EQUIQ_F FW_WR_EQUIQ_V(1U)
151 /* egress queue status update to egress queue status entry (lo) */
152 #define FW_WR_EQUEQ_S 30
153 #define FW_WR_EQUEQ_V(x) ((x) << FW_WR_EQUEQ_S)
154 #define FW_WR_EQUEQ_F FW_WR_EQUEQ_V(1U)
156 /* flow context identifier (lo) */
157 #define FW_WR_FLOWID_S 8
158 #define FW_WR_FLOWID_V(x) ((x) << FW_WR_FLOWID_S)
160 /* length in units of 16-bytes (lo) */
161 #define FW_WR_LEN16_S 0
162 #define FW_WR_LEN16_V(x) ((x) << FW_WR_LEN16_S)
164 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B
165 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327
167 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
168 enum fw_filter_wr_cookie
{
169 FW_FILTER_WR_SUCCESS
,
170 FW_FILTER_WR_FLT_ADDED
,
171 FW_FILTER_WR_FLT_DELETED
,
172 FW_FILTER_WR_SMT_TBL_FULL
,
176 struct fw_filter_wr
{
181 __be32 del_filter_to_l2tix
;
184 __u8 frag_to_ovlan_vldm
;
186 __be16 rx_chan_rx_rpl_iq
;
187 __be32 maci_to_matchtypem
;
208 struct fw_filter2_wr
{
213 __be32 del_filter_to_l2tix
;
216 __u8 frag_to_ovlan_vldm
;
218 __be16 rx_chan_rx_rpl_iq
;
219 __be32 maci_to_matchtypem
;
239 __u8 filter_type_swapmac
;
240 __u8 natmode_to_ulp_type
;
253 #define FW_FILTER_WR_TID_S 12
254 #define FW_FILTER_WR_TID_M 0xfffff
255 #define FW_FILTER_WR_TID_V(x) ((x) << FW_FILTER_WR_TID_S)
256 #define FW_FILTER_WR_TID_G(x) \
257 (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M)
259 #define FW_FILTER_WR_RQTYPE_S 11
260 #define FW_FILTER_WR_RQTYPE_M 0x1
261 #define FW_FILTER_WR_RQTYPE_V(x) ((x) << FW_FILTER_WR_RQTYPE_S)
262 #define FW_FILTER_WR_RQTYPE_G(x) \
263 (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M)
264 #define FW_FILTER_WR_RQTYPE_F FW_FILTER_WR_RQTYPE_V(1U)
266 #define FW_FILTER_WR_NOREPLY_S 10
267 #define FW_FILTER_WR_NOREPLY_M 0x1
268 #define FW_FILTER_WR_NOREPLY_V(x) ((x) << FW_FILTER_WR_NOREPLY_S)
269 #define FW_FILTER_WR_NOREPLY_G(x) \
270 (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M)
271 #define FW_FILTER_WR_NOREPLY_F FW_FILTER_WR_NOREPLY_V(1U)
273 #define FW_FILTER_WR_IQ_S 0
274 #define FW_FILTER_WR_IQ_M 0x3ff
275 #define FW_FILTER_WR_IQ_V(x) ((x) << FW_FILTER_WR_IQ_S)
276 #define FW_FILTER_WR_IQ_G(x) \
277 (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M)
279 #define FW_FILTER_WR_DEL_FILTER_S 31
280 #define FW_FILTER_WR_DEL_FILTER_M 0x1
281 #define FW_FILTER_WR_DEL_FILTER_V(x) ((x) << FW_FILTER_WR_DEL_FILTER_S)
282 #define FW_FILTER_WR_DEL_FILTER_G(x) \
283 (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M)
284 #define FW_FILTER_WR_DEL_FILTER_F FW_FILTER_WR_DEL_FILTER_V(1U)
286 #define FW_FILTER_WR_RPTTID_S 25
287 #define FW_FILTER_WR_RPTTID_M 0x1
288 #define FW_FILTER_WR_RPTTID_V(x) ((x) << FW_FILTER_WR_RPTTID_S)
289 #define FW_FILTER_WR_RPTTID_G(x) \
290 (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M)
291 #define FW_FILTER_WR_RPTTID_F FW_FILTER_WR_RPTTID_V(1U)
293 #define FW_FILTER_WR_DROP_S 24
294 #define FW_FILTER_WR_DROP_M 0x1
295 #define FW_FILTER_WR_DROP_V(x) ((x) << FW_FILTER_WR_DROP_S)
296 #define FW_FILTER_WR_DROP_G(x) \
297 (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M)
298 #define FW_FILTER_WR_DROP_F FW_FILTER_WR_DROP_V(1U)
300 #define FW_FILTER_WR_DIRSTEER_S 23
301 #define FW_FILTER_WR_DIRSTEER_M 0x1
302 #define FW_FILTER_WR_DIRSTEER_V(x) ((x) << FW_FILTER_WR_DIRSTEER_S)
303 #define FW_FILTER_WR_DIRSTEER_G(x) \
304 (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M)
305 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U)
307 #define FW_FILTER_WR_MASKHASH_S 22
308 #define FW_FILTER_WR_MASKHASH_M 0x1
309 #define FW_FILTER_WR_MASKHASH_V(x) ((x) << FW_FILTER_WR_MASKHASH_S)
310 #define FW_FILTER_WR_MASKHASH_G(x) \
311 (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M)
312 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U)
314 #define FW_FILTER_WR_DIRSTEERHASH_S 21
315 #define FW_FILTER_WR_DIRSTEERHASH_M 0x1
316 #define FW_FILTER_WR_DIRSTEERHASH_V(x) ((x) << FW_FILTER_WR_DIRSTEERHASH_S)
317 #define FW_FILTER_WR_DIRSTEERHASH_G(x) \
318 (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M)
319 #define FW_FILTER_WR_DIRSTEERHASH_F FW_FILTER_WR_DIRSTEERHASH_V(1U)
321 #define FW_FILTER_WR_LPBK_S 20
322 #define FW_FILTER_WR_LPBK_M 0x1
323 #define FW_FILTER_WR_LPBK_V(x) ((x) << FW_FILTER_WR_LPBK_S)
324 #define FW_FILTER_WR_LPBK_G(x) \
325 (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M)
326 #define FW_FILTER_WR_LPBK_F FW_FILTER_WR_LPBK_V(1U)
328 #define FW_FILTER_WR_DMAC_S 19
329 #define FW_FILTER_WR_DMAC_M 0x1
330 #define FW_FILTER_WR_DMAC_V(x) ((x) << FW_FILTER_WR_DMAC_S)
331 #define FW_FILTER_WR_DMAC_G(x) \
332 (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M)
333 #define FW_FILTER_WR_DMAC_F FW_FILTER_WR_DMAC_V(1U)
335 #define FW_FILTER_WR_SMAC_S 18
336 #define FW_FILTER_WR_SMAC_M 0x1
337 #define FW_FILTER_WR_SMAC_V(x) ((x) << FW_FILTER_WR_SMAC_S)
338 #define FW_FILTER_WR_SMAC_G(x) \
339 (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M)
340 #define FW_FILTER_WR_SMAC_F FW_FILTER_WR_SMAC_V(1U)
342 #define FW_FILTER_WR_INSVLAN_S 17
343 #define FW_FILTER_WR_INSVLAN_M 0x1
344 #define FW_FILTER_WR_INSVLAN_V(x) ((x) << FW_FILTER_WR_INSVLAN_S)
345 #define FW_FILTER_WR_INSVLAN_G(x) \
346 (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M)
347 #define FW_FILTER_WR_INSVLAN_F FW_FILTER_WR_INSVLAN_V(1U)
349 #define FW_FILTER_WR_RMVLAN_S 16
350 #define FW_FILTER_WR_RMVLAN_M 0x1
351 #define FW_FILTER_WR_RMVLAN_V(x) ((x) << FW_FILTER_WR_RMVLAN_S)
352 #define FW_FILTER_WR_RMVLAN_G(x) \
353 (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M)
354 #define FW_FILTER_WR_RMVLAN_F FW_FILTER_WR_RMVLAN_V(1U)
356 #define FW_FILTER_WR_HITCNTS_S 15
357 #define FW_FILTER_WR_HITCNTS_M 0x1
358 #define FW_FILTER_WR_HITCNTS_V(x) ((x) << FW_FILTER_WR_HITCNTS_S)
359 #define FW_FILTER_WR_HITCNTS_G(x) \
360 (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M)
361 #define FW_FILTER_WR_HITCNTS_F FW_FILTER_WR_HITCNTS_V(1U)
363 #define FW_FILTER_WR_TXCHAN_S 13
364 #define FW_FILTER_WR_TXCHAN_M 0x3
365 #define FW_FILTER_WR_TXCHAN_V(x) ((x) << FW_FILTER_WR_TXCHAN_S)
366 #define FW_FILTER_WR_TXCHAN_G(x) \
367 (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M)
369 #define FW_FILTER_WR_PRIO_S 12
370 #define FW_FILTER_WR_PRIO_M 0x1
371 #define FW_FILTER_WR_PRIO_V(x) ((x) << FW_FILTER_WR_PRIO_S)
372 #define FW_FILTER_WR_PRIO_G(x) \
373 (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M)
374 #define FW_FILTER_WR_PRIO_F FW_FILTER_WR_PRIO_V(1U)
376 #define FW_FILTER_WR_L2TIX_S 0
377 #define FW_FILTER_WR_L2TIX_M 0xfff
378 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S)
379 #define FW_FILTER_WR_L2TIX_G(x) \
380 (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M)
382 #define FW_FILTER_WR_FRAG_S 7
383 #define FW_FILTER_WR_FRAG_M 0x1
384 #define FW_FILTER_WR_FRAG_V(x) ((x) << FW_FILTER_WR_FRAG_S)
385 #define FW_FILTER_WR_FRAG_G(x) \
386 (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M)
387 #define FW_FILTER_WR_FRAG_F FW_FILTER_WR_FRAG_V(1U)
389 #define FW_FILTER_WR_FRAGM_S 6
390 #define FW_FILTER_WR_FRAGM_M 0x1
391 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S)
392 #define FW_FILTER_WR_FRAGM_G(x) \
393 (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M)
394 #define FW_FILTER_WR_FRAGM_F FW_FILTER_WR_FRAGM_V(1U)
396 #define FW_FILTER_WR_IVLAN_VLD_S 5
397 #define FW_FILTER_WR_IVLAN_VLD_M 0x1
398 #define FW_FILTER_WR_IVLAN_VLD_V(x) ((x) << FW_FILTER_WR_IVLAN_VLD_S)
399 #define FW_FILTER_WR_IVLAN_VLD_G(x) \
400 (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M)
401 #define FW_FILTER_WR_IVLAN_VLD_F FW_FILTER_WR_IVLAN_VLD_V(1U)
403 #define FW_FILTER_WR_OVLAN_VLD_S 4
404 #define FW_FILTER_WR_OVLAN_VLD_M 0x1
405 #define FW_FILTER_WR_OVLAN_VLD_V(x) ((x) << FW_FILTER_WR_OVLAN_VLD_S)
406 #define FW_FILTER_WR_OVLAN_VLD_G(x) \
407 (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M)
408 #define FW_FILTER_WR_OVLAN_VLD_F FW_FILTER_WR_OVLAN_VLD_V(1U)
410 #define FW_FILTER_WR_IVLAN_VLDM_S 3
411 #define FW_FILTER_WR_IVLAN_VLDM_M 0x1
412 #define FW_FILTER_WR_IVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_IVLAN_VLDM_S)
413 #define FW_FILTER_WR_IVLAN_VLDM_G(x) \
414 (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M)
415 #define FW_FILTER_WR_IVLAN_VLDM_F FW_FILTER_WR_IVLAN_VLDM_V(1U)
417 #define FW_FILTER_WR_OVLAN_VLDM_S 2
418 #define FW_FILTER_WR_OVLAN_VLDM_M 0x1
419 #define FW_FILTER_WR_OVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_OVLAN_VLDM_S)
420 #define FW_FILTER_WR_OVLAN_VLDM_G(x) \
421 (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M)
422 #define FW_FILTER_WR_OVLAN_VLDM_F FW_FILTER_WR_OVLAN_VLDM_V(1U)
424 #define FW_FILTER_WR_RX_CHAN_S 15
425 #define FW_FILTER_WR_RX_CHAN_M 0x1
426 #define FW_FILTER_WR_RX_CHAN_V(x) ((x) << FW_FILTER_WR_RX_CHAN_S)
427 #define FW_FILTER_WR_RX_CHAN_G(x) \
428 (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M)
429 #define FW_FILTER_WR_RX_CHAN_F FW_FILTER_WR_RX_CHAN_V(1U)
431 #define FW_FILTER_WR_RX_RPL_IQ_S 0
432 #define FW_FILTER_WR_RX_RPL_IQ_M 0x3ff
433 #define FW_FILTER_WR_RX_RPL_IQ_V(x) ((x) << FW_FILTER_WR_RX_RPL_IQ_S)
434 #define FW_FILTER_WR_RX_RPL_IQ_G(x) \
435 (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M)
437 #define FW_FILTER2_WR_FILTER_TYPE_S 1
438 #define FW_FILTER2_WR_FILTER_TYPE_M 0x1
439 #define FW_FILTER2_WR_FILTER_TYPE_V(x) ((x) << FW_FILTER2_WR_FILTER_TYPE_S)
440 #define FW_FILTER2_WR_FILTER_TYPE_G(x) \
441 (((x) >> FW_FILTER2_WR_FILTER_TYPE_S) & FW_FILTER2_WR_FILTER_TYPE_M)
442 #define FW_FILTER2_WR_FILTER_TYPE_F FW_FILTER2_WR_FILTER_TYPE_V(1U)
444 #define FW_FILTER2_WR_NATMODE_S 5
445 #define FW_FILTER2_WR_NATMODE_M 0x7
446 #define FW_FILTER2_WR_NATMODE_V(x) ((x) << FW_FILTER2_WR_NATMODE_S)
447 #define FW_FILTER2_WR_NATMODE_G(x) \
448 (((x) >> FW_FILTER2_WR_NATMODE_S) & FW_FILTER2_WR_NATMODE_M)
450 #define FW_FILTER2_WR_NATFLAGCHECK_S 4
451 #define FW_FILTER2_WR_NATFLAGCHECK_M 0x1
452 #define FW_FILTER2_WR_NATFLAGCHECK_V(x) ((x) << FW_FILTER2_WR_NATFLAGCHECK_S)
453 #define FW_FILTER2_WR_NATFLAGCHECK_G(x) \
454 (((x) >> FW_FILTER2_WR_NATFLAGCHECK_S) & FW_FILTER2_WR_NATFLAGCHECK_M)
455 #define FW_FILTER2_WR_NATFLAGCHECK_F FW_FILTER2_WR_NATFLAGCHECK_V(1U)
457 #define FW_FILTER2_WR_ULP_TYPE_S 0
458 #define FW_FILTER2_WR_ULP_TYPE_M 0xf
459 #define FW_FILTER2_WR_ULP_TYPE_V(x) ((x) << FW_FILTER2_WR_ULP_TYPE_S)
460 #define FW_FILTER2_WR_ULP_TYPE_G(x) \
461 (((x) >> FW_FILTER2_WR_ULP_TYPE_S) & FW_FILTER2_WR_ULP_TYPE_M)
463 #define FW_FILTER_WR_MACI_S 23
464 #define FW_FILTER_WR_MACI_M 0x1ff
465 #define FW_FILTER_WR_MACI_V(x) ((x) << FW_FILTER_WR_MACI_S)
466 #define FW_FILTER_WR_MACI_G(x) \
467 (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M)
469 #define FW_FILTER_WR_MACIM_S 14
470 #define FW_FILTER_WR_MACIM_M 0x1ff
471 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S)
472 #define FW_FILTER_WR_MACIM_G(x) \
473 (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M)
475 #define FW_FILTER_WR_FCOE_S 13
476 #define FW_FILTER_WR_FCOE_M 0x1
477 #define FW_FILTER_WR_FCOE_V(x) ((x) << FW_FILTER_WR_FCOE_S)
478 #define FW_FILTER_WR_FCOE_G(x) \
479 (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M)
480 #define FW_FILTER_WR_FCOE_F FW_FILTER_WR_FCOE_V(1U)
482 #define FW_FILTER_WR_FCOEM_S 12
483 #define FW_FILTER_WR_FCOEM_M 0x1
484 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S)
485 #define FW_FILTER_WR_FCOEM_G(x) \
486 (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M)
487 #define FW_FILTER_WR_FCOEM_F FW_FILTER_WR_FCOEM_V(1U)
489 #define FW_FILTER_WR_PORT_S 9
490 #define FW_FILTER_WR_PORT_M 0x7
491 #define FW_FILTER_WR_PORT_V(x) ((x) << FW_FILTER_WR_PORT_S)
492 #define FW_FILTER_WR_PORT_G(x) \
493 (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M)
495 #define FW_FILTER_WR_PORTM_S 6
496 #define FW_FILTER_WR_PORTM_M 0x7
497 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S)
498 #define FW_FILTER_WR_PORTM_G(x) \
499 (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M)
501 #define FW_FILTER_WR_MATCHTYPE_S 3
502 #define FW_FILTER_WR_MATCHTYPE_M 0x7
503 #define FW_FILTER_WR_MATCHTYPE_V(x) ((x) << FW_FILTER_WR_MATCHTYPE_S)
504 #define FW_FILTER_WR_MATCHTYPE_G(x) \
505 (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M)
507 #define FW_FILTER_WR_MATCHTYPEM_S 0
508 #define FW_FILTER_WR_MATCHTYPEM_M 0x7
509 #define FW_FILTER_WR_MATCHTYPEM_V(x) ((x) << FW_FILTER_WR_MATCHTYPEM_S)
510 #define FW_FILTER_WR_MATCHTYPEM_G(x) \
511 (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M)
519 #define FW_ULPTX_WR_DATA_S 28
520 #define FW_ULPTX_WR_DATA_M 0x1
521 #define FW_ULPTX_WR_DATA_V(x) ((x) << FW_ULPTX_WR_DATA_S)
522 #define FW_ULPTX_WR_DATA_G(x) \
523 (((x) >> FW_ULPTX_WR_DATA_S) & FW_ULPTX_WR_DATA_M)
524 #define FW_ULPTX_WR_DATA_F FW_ULPTX_WR_DATA_V(1U)
527 __be32 op_to_immdlen
;
532 struct fw_eth_tx_pkt_wr
{
534 __be32 equiq_to_len16
;
538 enum fw_eth_tx_eo_type
{
539 FW_ETH_TX_EO_TYPE_UDPSEG
= 0,
540 FW_ETH_TX_EO_TYPE_TCPSEG
,
543 struct fw_eth_tx_eo_wr
{
545 __be32 equiq_to_len16
;
548 struct fw_eth_tx_eo_udpseg
{
559 struct fw_eth_tx_eo_tcpseg
{
573 #define FW_ETH_TX_EO_WR_IMMDLEN_S 0
574 #define FW_ETH_TX_EO_WR_IMMDLEN_M 0x1ff
575 #define FW_ETH_TX_EO_WR_IMMDLEN_V(x) ((x) << FW_ETH_TX_EO_WR_IMMDLEN_S)
576 #define FW_ETH_TX_EO_WR_IMMDLEN_G(x) \
577 (((x) >> FW_ETH_TX_EO_WR_IMMDLEN_S) & FW_ETH_TX_EO_WR_IMMDLEN_M)
579 struct fw_ofld_connection_wr
{
585 struct fw_ofld_connection_le
{
591 union fw_ofld_connection_leip
{
592 struct fw_ofld_connection_le_ipv4
{
599 struct fw_ofld_connection_le_ipv6
{
607 struct fw_ofld_connection_tcb
{
608 __be32 t_state_to_astid
;
609 __be16 cplrxdataack_cplpassacceptrpl
;
621 #define FW_OFLD_CONNECTION_WR_VERSION_S 31
622 #define FW_OFLD_CONNECTION_WR_VERSION_M 0x1
623 #define FW_OFLD_CONNECTION_WR_VERSION_V(x) \
624 ((x) << FW_OFLD_CONNECTION_WR_VERSION_S)
625 #define FW_OFLD_CONNECTION_WR_VERSION_G(x) \
626 (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \
627 FW_OFLD_CONNECTION_WR_VERSION_M)
628 #define FW_OFLD_CONNECTION_WR_VERSION_F \
629 FW_OFLD_CONNECTION_WR_VERSION_V(1U)
631 #define FW_OFLD_CONNECTION_WR_CPL_S 30
632 #define FW_OFLD_CONNECTION_WR_CPL_M 0x1
633 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S)
634 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \
635 (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M)
636 #define FW_OFLD_CONNECTION_WR_CPL_F FW_OFLD_CONNECTION_WR_CPL_V(1U)
638 #define FW_OFLD_CONNECTION_WR_T_STATE_S 28
639 #define FW_OFLD_CONNECTION_WR_T_STATE_M 0xf
640 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x) \
641 ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S)
642 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x) \
643 (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \
644 FW_OFLD_CONNECTION_WR_T_STATE_M)
646 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S 24
647 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M 0xf
648 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x) \
649 ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S)
650 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x) \
651 (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \
652 FW_OFLD_CONNECTION_WR_RCV_SCALE_M)
654 #define FW_OFLD_CONNECTION_WR_ASTID_S 0
655 #define FW_OFLD_CONNECTION_WR_ASTID_M 0xffffff
656 #define FW_OFLD_CONNECTION_WR_ASTID_V(x) \
657 ((x) << FW_OFLD_CONNECTION_WR_ASTID_S)
658 #define FW_OFLD_CONNECTION_WR_ASTID_G(x) \
659 (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M)
661 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S 15
662 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M 0x1
663 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x) \
664 ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S)
665 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x) \
666 (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \
667 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M)
668 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F \
669 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U)
671 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S 14
672 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M 0x1
673 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x) \
674 ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S)
675 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x) \
676 (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \
677 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M)
678 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F \
679 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U)
681 enum fw_flowc_mnem_tcpstate
{
682 FW_FLOWC_MNEM_TCPSTATE_CLOSED
= 0, /* illegal */
683 FW_FLOWC_MNEM_TCPSTATE_LISTEN
= 1, /* illegal */
684 FW_FLOWC_MNEM_TCPSTATE_SYNSENT
= 2, /* illegal */
685 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED
= 3, /* illegal */
686 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED
= 4, /* default */
687 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT
= 5, /* got peer close already */
688 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1
= 6, /* haven't gotten ACK for FIN and
689 * will resend FIN - equiv ESTAB
691 FW_FLOWC_MNEM_TCPSTATE_CLOSING
= 7, /* haven't gotten ACK for FIN and
692 * will resend FIN but have
695 FW_FLOWC_MNEM_TCPSTATE_LASTACK
= 8, /* haven't gotten ACK for FIN and
696 * will resend FIN but have
699 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2
= 9, /* sent FIN and got FIN + ACK,
702 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT
= 10, /* not expected */
705 enum fw_flowc_mnem_eostate
{
706 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED
= 1, /* default */
707 /* graceful close, after sending outstanding payload */
708 FW_FLOWC_MNEM_EOSTATE_CLOSING
= 2,
712 FW_FLOWC_MNEM_PFNVFN
, /* PFN [15:8] VFN [7:0] */
716 FW_FLOWC_MNEM_SNDNXT
,
717 FW_FLOWC_MNEM_RCVNXT
,
718 FW_FLOWC_MNEM_SNDBUF
,
720 FW_FLOWC_MNEM_TXDATAPLEN_MAX
,
721 FW_FLOWC_MNEM_TCPSTATE
,
722 FW_FLOWC_MNEM_EOSTATE
,
723 FW_FLOWC_MNEM_SCHEDCLASS
,
724 FW_FLOWC_MNEM_DCBPRIO
,
725 FW_FLOWC_MNEM_SND_SCALE
,
726 FW_FLOWC_MNEM_RCV_SCALE
,
727 FW_FLOWC_MNEM_ULD_MODE
,
731 struct fw_flowc_mnemval
{
738 __be32 op_to_nparams
;
740 struct fw_flowc_mnemval mnemval
[0];
743 #define FW_FLOWC_WR_NPARAMS_S 0
744 #define FW_FLOWC_WR_NPARAMS_V(x) ((x) << FW_FLOWC_WR_NPARAMS_S)
746 struct fw_ofld_tx_data_wr
{
747 __be32 op_to_immdlen
;
750 __be32 tunnel_to_proxy
;
753 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_S 30
754 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_V(x) ((x) << FW_OFLD_TX_DATA_WR_ALIGNPLD_S)
755 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_F FW_OFLD_TX_DATA_WR_ALIGNPLD_V(1U)
757 #define FW_OFLD_TX_DATA_WR_SHOVE_S 29
758 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S)
759 #define FW_OFLD_TX_DATA_WR_SHOVE_F FW_OFLD_TX_DATA_WR_SHOVE_V(1U)
761 #define FW_OFLD_TX_DATA_WR_TUNNEL_S 19
762 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x) ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S)
764 #define FW_OFLD_TX_DATA_WR_SAVE_S 18
765 #define FW_OFLD_TX_DATA_WR_SAVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SAVE_S)
767 #define FW_OFLD_TX_DATA_WR_FLUSH_S 17
768 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x) ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S)
769 #define FW_OFLD_TX_DATA_WR_FLUSH_F FW_OFLD_TX_DATA_WR_FLUSH_V(1U)
771 #define FW_OFLD_TX_DATA_WR_URGENT_S 16
772 #define FW_OFLD_TX_DATA_WR_URGENT_V(x) ((x) << FW_OFLD_TX_DATA_WR_URGENT_S)
774 #define FW_OFLD_TX_DATA_WR_MORE_S 15
775 #define FW_OFLD_TX_DATA_WR_MORE_V(x) ((x) << FW_OFLD_TX_DATA_WR_MORE_S)
777 #define FW_OFLD_TX_DATA_WR_ULPMODE_S 10
778 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S)
780 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S 6
781 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x) \
782 ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S)
790 #define FW_CMD_WR_DMA_S 17
791 #define FW_CMD_WR_DMA_V(x) ((x) << FW_CMD_WR_DMA_S)
793 struct fw_eth_tx_pkt_vm_wr
{
795 __be32 equiq_to_len16
;
803 #define FW_CMD_MAX_TIMEOUT 10000
806 * If a host driver does a HELLO and discovers that there's already a MASTER
807 * selected, we may have to wait for that MASTER to finish issuing RESET,
808 * configuration and INITIALIZE commands. Also, there's a possibility that
809 * our own HELLO may get lost if it happens right as the MASTER is issuign a
810 * RESET command, so we need to be willing to make a few retries of our HELLO.
812 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
813 #define FW_CMD_HELLO_RETRIES 3
816 enum fw_cmd_opcodes
{
821 FW_INITIALIZE_CMD
= 0x06,
822 FW_CAPS_CONFIG_CMD
= 0x07,
823 FW_PARAMS_CMD
= 0x08,
826 FW_EQ_MNGT_CMD
= 0x11,
827 FW_EQ_ETH_CMD
= 0x12,
828 FW_EQ_CTRL_CMD
= 0x13,
829 FW_EQ_OFLD_CMD
= 0x21,
831 FW_VI_MAC_CMD
= 0x15,
832 FW_VI_RXMODE_CMD
= 0x16,
833 FW_VI_ENABLE_CMD
= 0x17,
834 FW_ACL_MAC_CMD
= 0x18,
835 FW_ACL_VLAN_CMD
= 0x19,
836 FW_VI_STATS_CMD
= 0x1a,
838 FW_PORT_STATS_CMD
= 0x1c,
839 FW_PORT_LB_STATS_CMD
= 0x1d,
840 FW_PORT_TRACE_CMD
= 0x1e,
841 FW_PORT_TRACE_MMAP_CMD
= 0x1f,
842 FW_RSS_IND_TBL_CMD
= 0x20,
843 FW_RSS_GLB_CONFIG_CMD
= 0x22,
844 FW_RSS_VI_CONFIG_CMD
= 0x23,
846 FW_DEVLOG_CMD
= 0x25,
850 FW_LASTC2E_CMD
= 0x40,
856 FW_CMD_CAP_PF
= 0x01,
857 FW_CMD_CAP_DMAQ
= 0x02,
858 FW_CMD_CAP_PORT
= 0x04,
859 FW_CMD_CAP_PORTPROMISC
= 0x08,
860 FW_CMD_CAP_PORTSTATS
= 0x10,
861 FW_CMD_CAP_VF
= 0x80,
865 * Generic command header flit0
872 #define FW_CMD_OP_S 24
873 #define FW_CMD_OP_M 0xff
874 #define FW_CMD_OP_V(x) ((x) << FW_CMD_OP_S)
875 #define FW_CMD_OP_G(x) (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M)
877 #define FW_CMD_REQUEST_S 23
878 #define FW_CMD_REQUEST_V(x) ((x) << FW_CMD_REQUEST_S)
879 #define FW_CMD_REQUEST_F FW_CMD_REQUEST_V(1U)
881 #define FW_CMD_READ_S 22
882 #define FW_CMD_READ_V(x) ((x) << FW_CMD_READ_S)
883 #define FW_CMD_READ_F FW_CMD_READ_V(1U)
885 #define FW_CMD_WRITE_S 21
886 #define FW_CMD_WRITE_V(x) ((x) << FW_CMD_WRITE_S)
887 #define FW_CMD_WRITE_F FW_CMD_WRITE_V(1U)
889 #define FW_CMD_EXEC_S 20
890 #define FW_CMD_EXEC_V(x) ((x) << FW_CMD_EXEC_S)
891 #define FW_CMD_EXEC_F FW_CMD_EXEC_V(1U)
893 #define FW_CMD_RAMASK_S 20
894 #define FW_CMD_RAMASK_V(x) ((x) << FW_CMD_RAMASK_S)
896 #define FW_CMD_RETVAL_S 8
897 #define FW_CMD_RETVAL_M 0xff
898 #define FW_CMD_RETVAL_V(x) ((x) << FW_CMD_RETVAL_S)
899 #define FW_CMD_RETVAL_G(x) (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M)
901 #define FW_CMD_LEN16_S 0
902 #define FW_CMD_LEN16_V(x) ((x) << FW_CMD_LEN16_S)
904 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
906 enum fw_ldst_addrspc
{
907 FW_LDST_ADDRSPC_FIRMWARE
= 0x0001,
908 FW_LDST_ADDRSPC_SGE_EGRC
= 0x0008,
909 FW_LDST_ADDRSPC_SGE_INGC
= 0x0009,
910 FW_LDST_ADDRSPC_SGE_FLMC
= 0x000a,
911 FW_LDST_ADDRSPC_SGE_CONMC
= 0x000b,
912 FW_LDST_ADDRSPC_TP_PIO
= 0x0010,
913 FW_LDST_ADDRSPC_TP_TM_PIO
= 0x0011,
914 FW_LDST_ADDRSPC_TP_MIB
= 0x0012,
915 FW_LDST_ADDRSPC_MDIO
= 0x0018,
916 FW_LDST_ADDRSPC_MPS
= 0x0020,
917 FW_LDST_ADDRSPC_FUNC
= 0x0028,
918 FW_LDST_ADDRSPC_FUNC_PCIE
= 0x0029,
919 FW_LDST_ADDRSPC_I2C
= 0x0038,
922 enum fw_ldst_mps_fid
{
927 enum fw_ldst_func_access_ctl
{
928 FW_LDST_FUNC_ACC_CTL_VIID
,
929 FW_LDST_FUNC_ACC_CTL_FID
932 enum fw_ldst_func_mod_index
{
937 __be32 op_to_addrspace
;
938 __be32 cycles_to_len16
;
940 struct fw_ldst_addrval
{
944 struct fw_ldst_idctxt
{
946 __be32 msg_ctxtflush
;
956 struct fw_ldst_mdio
{
962 struct fw_ldst_cim_rq
{
970 struct fw_ldst_mps_rplc
{
982 struct fw_ldst_mps_atrb
{
991 struct fw_ldst_func
{
999 struct fw_ldst_pcie
{
1009 struct fw_ldst_i2c_deprecated
{
1016 struct fw_ldst_i2c
{
1033 #define FW_LDST_CMD_ADDRSPACE_S 0
1034 #define FW_LDST_CMD_ADDRSPACE_V(x) ((x) << FW_LDST_CMD_ADDRSPACE_S)
1036 #define FW_LDST_CMD_MSG_S 31
1037 #define FW_LDST_CMD_MSG_V(x) ((x) << FW_LDST_CMD_MSG_S)
1039 #define FW_LDST_CMD_CTXTFLUSH_S 30
1040 #define FW_LDST_CMD_CTXTFLUSH_V(x) ((x) << FW_LDST_CMD_CTXTFLUSH_S)
1041 #define FW_LDST_CMD_CTXTFLUSH_F FW_LDST_CMD_CTXTFLUSH_V(1U)
1043 #define FW_LDST_CMD_PADDR_S 8
1044 #define FW_LDST_CMD_PADDR_V(x) ((x) << FW_LDST_CMD_PADDR_S)
1046 #define FW_LDST_CMD_MMD_S 0
1047 #define FW_LDST_CMD_MMD_V(x) ((x) << FW_LDST_CMD_MMD_S)
1049 #define FW_LDST_CMD_FID_S 15
1050 #define FW_LDST_CMD_FID_V(x) ((x) << FW_LDST_CMD_FID_S)
1052 #define FW_LDST_CMD_IDX_S 0
1053 #define FW_LDST_CMD_IDX_V(x) ((x) << FW_LDST_CMD_IDX_S)
1055 #define FW_LDST_CMD_RPLCPF_S 0
1056 #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S)
1058 #define FW_LDST_CMD_LC_S 4
1059 #define FW_LDST_CMD_LC_V(x) ((x) << FW_LDST_CMD_LC_S)
1060 #define FW_LDST_CMD_LC_F FW_LDST_CMD_LC_V(1U)
1062 #define FW_LDST_CMD_FN_S 0
1063 #define FW_LDST_CMD_FN_V(x) ((x) << FW_LDST_CMD_FN_S)
1065 #define FW_LDST_CMD_NACCESS_S 0
1066 #define FW_LDST_CMD_NACCESS_V(x) ((x) << FW_LDST_CMD_NACCESS_S)
1068 struct fw_reset_cmd
{
1070 __be32 retval_len16
;
1075 #define FW_RESET_CMD_HALT_S 31
1076 #define FW_RESET_CMD_HALT_M 0x1
1077 #define FW_RESET_CMD_HALT_V(x) ((x) << FW_RESET_CMD_HALT_S)
1078 #define FW_RESET_CMD_HALT_G(x) \
1079 (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M)
1080 #define FW_RESET_CMD_HALT_F FW_RESET_CMD_HALT_V(1U)
1082 enum fw_hellow_cmd
{
1083 fw_hello_cmd_stage_os
= 0x0
1086 struct fw_hello_cmd
{
1088 __be32 retval_len16
;
1089 __be32 err_to_clearinit
;
1093 #define FW_HELLO_CMD_ERR_S 31
1094 #define FW_HELLO_CMD_ERR_V(x) ((x) << FW_HELLO_CMD_ERR_S)
1095 #define FW_HELLO_CMD_ERR_F FW_HELLO_CMD_ERR_V(1U)
1097 #define FW_HELLO_CMD_INIT_S 30
1098 #define FW_HELLO_CMD_INIT_V(x) ((x) << FW_HELLO_CMD_INIT_S)
1099 #define FW_HELLO_CMD_INIT_F FW_HELLO_CMD_INIT_V(1U)
1101 #define FW_HELLO_CMD_MASTERDIS_S 29
1102 #define FW_HELLO_CMD_MASTERDIS_V(x) ((x) << FW_HELLO_CMD_MASTERDIS_S)
1104 #define FW_HELLO_CMD_MASTERFORCE_S 28
1105 #define FW_HELLO_CMD_MASTERFORCE_V(x) ((x) << FW_HELLO_CMD_MASTERFORCE_S)
1107 #define FW_HELLO_CMD_MBMASTER_S 24
1108 #define FW_HELLO_CMD_MBMASTER_M 0xfU
1109 #define FW_HELLO_CMD_MBMASTER_V(x) ((x) << FW_HELLO_CMD_MBMASTER_S)
1110 #define FW_HELLO_CMD_MBMASTER_G(x) \
1111 (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M)
1113 #define FW_HELLO_CMD_MBASYNCNOTINT_S 23
1114 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S)
1116 #define FW_HELLO_CMD_MBASYNCNOT_S 20
1117 #define FW_HELLO_CMD_MBASYNCNOT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOT_S)
1119 #define FW_HELLO_CMD_STAGE_S 17
1120 #define FW_HELLO_CMD_STAGE_V(x) ((x) << FW_HELLO_CMD_STAGE_S)
1122 #define FW_HELLO_CMD_CLEARINIT_S 16
1123 #define FW_HELLO_CMD_CLEARINIT_V(x) ((x) << FW_HELLO_CMD_CLEARINIT_S)
1124 #define FW_HELLO_CMD_CLEARINIT_F FW_HELLO_CMD_CLEARINIT_V(1U)
1128 __be32 retval_len16
;
1132 struct fw_initialize_cmd
{
1134 __be32 retval_len16
;
1138 enum fw_caps_config_hm
{
1139 FW_CAPS_CONFIG_HM_PCIE
= 0x00000001,
1140 FW_CAPS_CONFIG_HM_PL
= 0x00000002,
1141 FW_CAPS_CONFIG_HM_SGE
= 0x00000004,
1142 FW_CAPS_CONFIG_HM_CIM
= 0x00000008,
1143 FW_CAPS_CONFIG_HM_ULPTX
= 0x00000010,
1144 FW_CAPS_CONFIG_HM_TP
= 0x00000020,
1145 FW_CAPS_CONFIG_HM_ULPRX
= 0x00000040,
1146 FW_CAPS_CONFIG_HM_PMRX
= 0x00000080,
1147 FW_CAPS_CONFIG_HM_PMTX
= 0x00000100,
1148 FW_CAPS_CONFIG_HM_MC
= 0x00000200,
1149 FW_CAPS_CONFIG_HM_LE
= 0x00000400,
1150 FW_CAPS_CONFIG_HM_MPS
= 0x00000800,
1151 FW_CAPS_CONFIG_HM_XGMAC
= 0x00001000,
1152 FW_CAPS_CONFIG_HM_CPLSWITCH
= 0x00002000,
1153 FW_CAPS_CONFIG_HM_T4DBG
= 0x00004000,
1154 FW_CAPS_CONFIG_HM_MI
= 0x00008000,
1155 FW_CAPS_CONFIG_HM_I2CM
= 0x00010000,
1156 FW_CAPS_CONFIG_HM_NCSI
= 0x00020000,
1157 FW_CAPS_CONFIG_HM_SMB
= 0x00040000,
1158 FW_CAPS_CONFIG_HM_MA
= 0x00080000,
1159 FW_CAPS_CONFIG_HM_EDRAM
= 0x00100000,
1160 FW_CAPS_CONFIG_HM_PMU
= 0x00200000,
1161 FW_CAPS_CONFIG_HM_UART
= 0x00400000,
1162 FW_CAPS_CONFIG_HM_SF
= 0x00800000,
1165 enum fw_caps_config_nbm
{
1166 FW_CAPS_CONFIG_NBM_IPMI
= 0x00000001,
1167 FW_CAPS_CONFIG_NBM_NCSI
= 0x00000002,
1170 enum fw_caps_config_link
{
1171 FW_CAPS_CONFIG_LINK_PPP
= 0x00000001,
1172 FW_CAPS_CONFIG_LINK_QFC
= 0x00000002,
1173 FW_CAPS_CONFIG_LINK_DCBX
= 0x00000004,
1176 enum fw_caps_config_switch
{
1177 FW_CAPS_CONFIG_SWITCH_INGRESS
= 0x00000001,
1178 FW_CAPS_CONFIG_SWITCH_EGRESS
= 0x00000002,
1181 enum fw_caps_config_nic
{
1182 FW_CAPS_CONFIG_NIC
= 0x00000001,
1183 FW_CAPS_CONFIG_NIC_VM
= 0x00000002,
1184 FW_CAPS_CONFIG_NIC_HASHFILTER
= 0x00000020,
1185 FW_CAPS_CONFIG_NIC_ETHOFLD
= 0x00000040,
1188 enum fw_caps_config_ofld
{
1189 FW_CAPS_CONFIG_OFLD
= 0x00000001,
1192 enum fw_caps_config_rdma
{
1193 FW_CAPS_CONFIG_RDMA_RDDP
= 0x00000001,
1194 FW_CAPS_CONFIG_RDMA_RDMAC
= 0x00000002,
1197 enum fw_caps_config_iscsi
{
1198 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU
= 0x00000001,
1199 FW_CAPS_CONFIG_ISCSI_TARGET_PDU
= 0x00000002,
1200 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD
= 0x00000004,
1201 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD
= 0x00000008,
1204 enum fw_caps_config_crypto
{
1205 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE
= 0x00000001,
1206 FW_CAPS_CONFIG_TLS_INLINE
= 0x00000002,
1207 FW_CAPS_CONFIG_IPSEC_INLINE
= 0x00000004,
1210 enum fw_caps_config_fcoe
{
1211 FW_CAPS_CONFIG_FCOE_INITIATOR
= 0x00000001,
1212 FW_CAPS_CONFIG_FCOE_TARGET
= 0x00000002,
1213 FW_CAPS_CONFIG_FCOE_CTRL_OFLD
= 0x00000004,
1216 enum fw_memtype_cf
{
1217 FW_MEMTYPE_CF_EDC0
= 0x0,
1218 FW_MEMTYPE_CF_EDC1
= 0x1,
1219 FW_MEMTYPE_CF_EXTMEM
= 0x2,
1220 FW_MEMTYPE_CF_FLASH
= 0x4,
1221 FW_MEMTYPE_CF_INTERNAL
= 0x5,
1222 FW_MEMTYPE_CF_EXTMEM1
= 0x6,
1223 FW_MEMTYPE_CF_HMA
= 0x7,
1226 struct fw_caps_config_cmd
{
1228 __be32 cfvalid_to_len16
;
1246 #define FW_CAPS_CONFIG_CMD_CFVALID_S 27
1247 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S)
1248 #define FW_CAPS_CONFIG_CMD_CFVALID_F FW_CAPS_CONFIG_CMD_CFVALID_V(1U)
1250 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S 24
1251 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x) \
1252 ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S)
1254 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S 16
1255 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x) \
1256 ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S)
1259 * params command mnemonics
1261 enum fw_params_mnem
{
1262 FW_PARAMS_MNEM_DEV
= 1, /* device params */
1263 FW_PARAMS_MNEM_PFVF
= 2, /* function params */
1264 FW_PARAMS_MNEM_REG
= 3, /* limited register access */
1265 FW_PARAMS_MNEM_DMAQ
= 4, /* dma queue params */
1266 FW_PARAMS_MNEM_CHNET
= 5, /* chnet params */
1274 #define FW_PARAMS_PARAM_FILTER_MODE_S 16
1275 #define FW_PARAMS_PARAM_FILTER_MODE_M 0xffff
1276 #define FW_PARAMS_PARAM_FILTER_MODE_V(x) \
1277 ((x) << FW_PARAMS_PARAM_FILTER_MODE_S)
1278 #define FW_PARAMS_PARAM_FILTER_MODE_G(x) \
1279 (((x) >> FW_PARAMS_PARAM_FILTER_MODE_S) & \
1280 FW_PARAMS_PARAM_FILTER_MODE_M)
1282 #define FW_PARAMS_PARAM_FILTER_MASK_S 0
1283 #define FW_PARAMS_PARAM_FILTER_MASK_M 0xffff
1284 #define FW_PARAMS_PARAM_FILTER_MASK_V(x) \
1285 ((x) << FW_PARAMS_PARAM_FILTER_MASK_S)
1286 #define FW_PARAMS_PARAM_FILTER_MASK_G(x) \
1287 (((x) >> FW_PARAMS_PARAM_FILTER_MASK_S) & \
1288 FW_PARAMS_PARAM_FILTER_MASK_M)
1290 enum fw_params_param_dev
{
1291 FW_PARAMS_PARAM_DEV_CCLK
= 0x00, /* chip core clock in khz */
1292 FW_PARAMS_PARAM_DEV_PORTVEC
= 0x01, /* the port vector */
1293 FW_PARAMS_PARAM_DEV_NTID
= 0x02, /* reads the number of TIDs
1294 * allocated by the device's
1297 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ
= 0x03,
1298 FW_PARAMS_PARAM_DEV_INTVER_NIC
= 0x04,
1299 FW_PARAMS_PARAM_DEV_INTVER_VNIC
= 0x05,
1300 FW_PARAMS_PARAM_DEV_INTVER_OFLD
= 0x06,
1301 FW_PARAMS_PARAM_DEV_INTVER_RI
= 0x07,
1302 FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU
= 0x08,
1303 FW_PARAMS_PARAM_DEV_INTVER_ISCSI
= 0x09,
1304 FW_PARAMS_PARAM_DEV_INTVER_FCOE
= 0x0A,
1305 FW_PARAMS_PARAM_DEV_FWREV
= 0x0B,
1306 FW_PARAMS_PARAM_DEV_TPREV
= 0x0C,
1307 FW_PARAMS_PARAM_DEV_CF
= 0x0D,
1308 FW_PARAMS_PARAM_DEV_PHYFW
= 0x0F,
1309 FW_PARAMS_PARAM_DEV_DIAG
= 0x11,
1310 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP
= 0x13, /* max supported QP IRD/ORD */
1311 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER
= 0x14, /* max supported adap IRD */
1312 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL
= 0x17,
1313 FW_PARAMS_PARAM_DEV_FWCACHE
= 0x18,
1314 FW_PARAMS_PARAM_DEV_SCFGREV
= 0x1A,
1315 FW_PARAMS_PARAM_DEV_VPDREV
= 0x1B,
1316 FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR
= 0x1C,
1317 FW_PARAMS_PARAM_DEV_FILTER2_WR
= 0x1D,
1318 FW_PARAMS_PARAM_DEV_MPSBGMAP
= 0x1E,
1319 FW_PARAMS_PARAM_DEV_TPCHMAP
= 0x1F,
1320 FW_PARAMS_PARAM_DEV_HMA_SIZE
= 0x20,
1321 FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM
= 0x21,
1322 FW_PARAMS_PARAM_DEV_PPOD_EDRAM
= 0x23,
1323 FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR
= 0x24,
1324 FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN
= 0x27,
1325 FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD
= 0x28,
1326 FW_PARAMS_PARAM_DEV_DBQ_TIMER
= 0x29,
1327 FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK
= 0x2A,
1328 FW_PARAMS_PARAM_DEV_NUM_TM_CLASS
= 0x2B,
1329 FW_PARAMS_PARAM_DEV_FILTER
= 0x2E,
1333 * physical and virtual function parameters
1335 enum fw_params_param_pfvf
{
1336 FW_PARAMS_PARAM_PFVF_RWXCAPS
= 0x00,
1337 FW_PARAMS_PARAM_PFVF_ROUTE_START
= 0x01,
1338 FW_PARAMS_PARAM_PFVF_ROUTE_END
= 0x02,
1339 FW_PARAMS_PARAM_PFVF_CLIP_START
= 0x03,
1340 FW_PARAMS_PARAM_PFVF_CLIP_END
= 0x04,
1341 FW_PARAMS_PARAM_PFVF_FILTER_START
= 0x05,
1342 FW_PARAMS_PARAM_PFVF_FILTER_END
= 0x06,
1343 FW_PARAMS_PARAM_PFVF_SERVER_START
= 0x07,
1344 FW_PARAMS_PARAM_PFVF_SERVER_END
= 0x08,
1345 FW_PARAMS_PARAM_PFVF_TDDP_START
= 0x09,
1346 FW_PARAMS_PARAM_PFVF_TDDP_END
= 0x0A,
1347 FW_PARAMS_PARAM_PFVF_ISCSI_START
= 0x0B,
1348 FW_PARAMS_PARAM_PFVF_ISCSI_END
= 0x0C,
1349 FW_PARAMS_PARAM_PFVF_STAG_START
= 0x0D,
1350 FW_PARAMS_PARAM_PFVF_STAG_END
= 0x0E,
1351 FW_PARAMS_PARAM_PFVF_RQ_START
= 0x1F,
1352 FW_PARAMS_PARAM_PFVF_RQ_END
= 0x10,
1353 FW_PARAMS_PARAM_PFVF_PBL_START
= 0x11,
1354 FW_PARAMS_PARAM_PFVF_PBL_END
= 0x12,
1355 FW_PARAMS_PARAM_PFVF_L2T_START
= 0x13,
1356 FW_PARAMS_PARAM_PFVF_L2T_END
= 0x14,
1357 FW_PARAMS_PARAM_PFVF_SQRQ_START
= 0x15,
1358 FW_PARAMS_PARAM_PFVF_SQRQ_END
= 0x16,
1359 FW_PARAMS_PARAM_PFVF_CQ_START
= 0x17,
1360 FW_PARAMS_PARAM_PFVF_CQ_END
= 0x18,
1361 FW_PARAMS_PARAM_PFVF_SRQ_START
= 0x19,
1362 FW_PARAMS_PARAM_PFVF_SRQ_END
= 0x1A,
1363 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH
= 0x20,
1364 FW_PARAMS_PARAM_PFVF_VIID
= 0x24,
1365 FW_PARAMS_PARAM_PFVF_CPMASK
= 0x25,
1366 FW_PARAMS_PARAM_PFVF_OCQ_START
= 0x26,
1367 FW_PARAMS_PARAM_PFVF_OCQ_END
= 0x27,
1368 FW_PARAMS_PARAM_PFVF_CONM_MAP
= 0x28,
1369 FW_PARAMS_PARAM_PFVF_IQFLINT_START
= 0x29,
1370 FW_PARAMS_PARAM_PFVF_IQFLINT_END
= 0x2A,
1371 FW_PARAMS_PARAM_PFVF_EQ_START
= 0x2B,
1372 FW_PARAMS_PARAM_PFVF_EQ_END
= 0x2C,
1373 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START
= 0x2D,
1374 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END
= 0x2E,
1375 FW_PARAMS_PARAM_PFVF_ETHOFLD_START
= 0x2F,
1376 FW_PARAMS_PARAM_PFVF_ETHOFLD_END
= 0x30,
1377 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP
= 0x31,
1378 FW_PARAMS_PARAM_PFVF_HPFILTER_START
= 0x32,
1379 FW_PARAMS_PARAM_PFVF_HPFILTER_END
= 0x33,
1380 FW_PARAMS_PARAM_PFVF_TLS_START
= 0x34,
1381 FW_PARAMS_PARAM_PFVF_TLS_END
= 0x35,
1382 FW_PARAMS_PARAM_PFVF_RAWF_START
= 0x36,
1383 FW_PARAMS_PARAM_PFVF_RAWF_END
= 0x37,
1384 FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE
= 0x39,
1385 FW_PARAMS_PARAM_PFVF_PORT_CAPS32
= 0x3A,
1386 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START
= 0x3B,
1387 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END
= 0x3C,
1388 FW_PARAMS_PARAM_PFVF_LINK_STATE
= 0x40,
1391 /* Virtual link state as seen by the specified VF */
1392 enum vf_link_states
{
1393 FW_VF_LINK_STATE_AUTO
= 0x00,
1394 FW_VF_LINK_STATE_ENABLE
= 0x01,
1395 FW_VF_LINK_STATE_DISABLE
= 0x02,
1399 * dma queue parameters
1401 enum fw_params_param_dmaq
{
1402 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU
= 0x00,
1403 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH
= 0x01,
1404 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT
= 0x10,
1405 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL
= 0x11,
1406 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH
= 0x12,
1407 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH
= 0x13,
1408 FW_PARAMS_PARAM_DMAQ_EQ_TIMERIX
= 0x15,
1409 FW_PARAMS_PARAM_DMAQ_CONM_CTXT
= 0x20,
1412 enum fw_params_param_dev_phyfw
{
1413 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD
= 0x00,
1414 FW_PARAMS_PARAM_DEV_PHYFW_VERSION
= 0x01,
1417 enum fw_params_param_dev_diag
{
1418 FW_PARAM_DEV_DIAG_TMP
= 0x00,
1419 FW_PARAM_DEV_DIAG_VDD
= 0x01,
1420 FW_PARAM_DEV_DIAG_MAXTMPTHRESH
= 0x02,
1423 enum fw_params_param_dev_filter
{
1424 FW_PARAM_DEV_FILTER_VNIC_MODE
= 0x00,
1425 FW_PARAM_DEV_FILTER_MODE_MASK
= 0x01,
1428 enum fw_params_param_dev_fwcache
{
1429 FW_PARAM_DEV_FWCACHE_FLUSH
= 0x00,
1430 FW_PARAM_DEV_FWCACHE_FLUSHINV
= 0x01,
1433 #define FW_PARAMS_MNEM_S 24
1434 #define FW_PARAMS_MNEM_V(x) ((x) << FW_PARAMS_MNEM_S)
1436 #define FW_PARAMS_PARAM_X_S 16
1437 #define FW_PARAMS_PARAM_X_V(x) ((x) << FW_PARAMS_PARAM_X_S)
1439 #define FW_PARAMS_PARAM_Y_S 8
1440 #define FW_PARAMS_PARAM_Y_M 0xffU
1441 #define FW_PARAMS_PARAM_Y_V(x) ((x) << FW_PARAMS_PARAM_Y_S)
1442 #define FW_PARAMS_PARAM_Y_G(x) (((x) >> FW_PARAMS_PARAM_Y_S) &\
1443 FW_PARAMS_PARAM_Y_M)
1445 #define FW_PARAMS_PARAM_Z_S 0
1446 #define FW_PARAMS_PARAM_Z_M 0xffu
1447 #define FW_PARAMS_PARAM_Z_V(x) ((x) << FW_PARAMS_PARAM_Z_S)
1448 #define FW_PARAMS_PARAM_Z_G(x) (((x) >> FW_PARAMS_PARAM_Z_S) &\
1449 FW_PARAMS_PARAM_Z_M)
1451 #define FW_PARAMS_PARAM_XYZ_S 0
1452 #define FW_PARAMS_PARAM_XYZ_V(x) ((x) << FW_PARAMS_PARAM_XYZ_S)
1454 #define FW_PARAMS_PARAM_YZ_S 0
1455 #define FW_PARAMS_PARAM_YZ_V(x) ((x) << FW_PARAMS_PARAM_YZ_S)
1457 struct fw_params_cmd
{
1459 __be32 retval_len16
;
1460 struct fw_params_param
{
1466 #define FW_PARAMS_CMD_PFN_S 8
1467 #define FW_PARAMS_CMD_PFN_V(x) ((x) << FW_PARAMS_CMD_PFN_S)
1469 #define FW_PARAMS_CMD_VFN_S 0
1470 #define FW_PARAMS_CMD_VFN_V(x) ((x) << FW_PARAMS_CMD_VFN_S)
1472 struct fw_pfvf_cmd
{
1474 __be32 retval_len16
;
1475 __be32 niqflint_niq
;
1477 __be32 tc_to_nexactf
;
1478 __be32 r_caps_to_nethctrl
;
1484 #define FW_PFVF_CMD_PFN_S 8
1485 #define FW_PFVF_CMD_PFN_V(x) ((x) << FW_PFVF_CMD_PFN_S)
1487 #define FW_PFVF_CMD_VFN_S 0
1488 #define FW_PFVF_CMD_VFN_V(x) ((x) << FW_PFVF_CMD_VFN_S)
1490 #define FW_PFVF_CMD_NIQFLINT_S 20
1491 #define FW_PFVF_CMD_NIQFLINT_M 0xfff
1492 #define FW_PFVF_CMD_NIQFLINT_V(x) ((x) << FW_PFVF_CMD_NIQFLINT_S)
1493 #define FW_PFVF_CMD_NIQFLINT_G(x) \
1494 (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M)
1496 #define FW_PFVF_CMD_NIQ_S 0
1497 #define FW_PFVF_CMD_NIQ_M 0xfffff
1498 #define FW_PFVF_CMD_NIQ_V(x) ((x) << FW_PFVF_CMD_NIQ_S)
1499 #define FW_PFVF_CMD_NIQ_G(x) \
1500 (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M)
1502 #define FW_PFVF_CMD_TYPE_S 31
1503 #define FW_PFVF_CMD_TYPE_M 0x1
1504 #define FW_PFVF_CMD_TYPE_V(x) ((x) << FW_PFVF_CMD_TYPE_S)
1505 #define FW_PFVF_CMD_TYPE_G(x) \
1506 (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M)
1507 #define FW_PFVF_CMD_TYPE_F FW_PFVF_CMD_TYPE_V(1U)
1509 #define FW_PFVF_CMD_CMASK_S 24
1510 #define FW_PFVF_CMD_CMASK_M 0xf
1511 #define FW_PFVF_CMD_CMASK_V(x) ((x) << FW_PFVF_CMD_CMASK_S)
1512 #define FW_PFVF_CMD_CMASK_G(x) \
1513 (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M)
1515 #define FW_PFVF_CMD_PMASK_S 20
1516 #define FW_PFVF_CMD_PMASK_M 0xf
1517 #define FW_PFVF_CMD_PMASK_V(x) ((x) << FW_PFVF_CMD_PMASK_S)
1518 #define FW_PFVF_CMD_PMASK_G(x) \
1519 (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M)
1521 #define FW_PFVF_CMD_NEQ_S 0
1522 #define FW_PFVF_CMD_NEQ_M 0xfffff
1523 #define FW_PFVF_CMD_NEQ_V(x) ((x) << FW_PFVF_CMD_NEQ_S)
1524 #define FW_PFVF_CMD_NEQ_G(x) \
1525 (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M)
1527 #define FW_PFVF_CMD_TC_S 24
1528 #define FW_PFVF_CMD_TC_M 0xff
1529 #define FW_PFVF_CMD_TC_V(x) ((x) << FW_PFVF_CMD_TC_S)
1530 #define FW_PFVF_CMD_TC_G(x) (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M)
1532 #define FW_PFVF_CMD_NVI_S 16
1533 #define FW_PFVF_CMD_NVI_M 0xff
1534 #define FW_PFVF_CMD_NVI_V(x) ((x) << FW_PFVF_CMD_NVI_S)
1535 #define FW_PFVF_CMD_NVI_G(x) (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M)
1537 #define FW_PFVF_CMD_NEXACTF_S 0
1538 #define FW_PFVF_CMD_NEXACTF_M 0xffff
1539 #define FW_PFVF_CMD_NEXACTF_V(x) ((x) << FW_PFVF_CMD_NEXACTF_S)
1540 #define FW_PFVF_CMD_NEXACTF_G(x) \
1541 (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M)
1543 #define FW_PFVF_CMD_R_CAPS_S 24
1544 #define FW_PFVF_CMD_R_CAPS_M 0xff
1545 #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S)
1546 #define FW_PFVF_CMD_R_CAPS_G(x) \
1547 (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M)
1549 #define FW_PFVF_CMD_WX_CAPS_S 16
1550 #define FW_PFVF_CMD_WX_CAPS_M 0xff
1551 #define FW_PFVF_CMD_WX_CAPS_V(x) ((x) << FW_PFVF_CMD_WX_CAPS_S)
1552 #define FW_PFVF_CMD_WX_CAPS_G(x) \
1553 (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M)
1555 #define FW_PFVF_CMD_NETHCTRL_S 0
1556 #define FW_PFVF_CMD_NETHCTRL_M 0xffff
1557 #define FW_PFVF_CMD_NETHCTRL_V(x) ((x) << FW_PFVF_CMD_NETHCTRL_S)
1558 #define FW_PFVF_CMD_NETHCTRL_G(x) \
1559 (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M)
1562 FW_IQ_TYPE_FL_INT_CAP
,
1563 FW_IQ_TYPE_NO_FL_INT_CAP
1574 __be32 alloc_to_len16
;
1579 __be32 type_to_iqandstindex
;
1580 __be16 iqdroprss_to_iqesize
;
1583 __be32 iqns_to_fl0congen
;
1584 __be16 fl0dcaen_to_fl0cidxfthresh
;
1587 __be32 fl1cngchmap_to_fl1congen
;
1588 __be16 fl1dcaen_to_fl1cidxfthresh
;
1593 #define FW_IQ_CMD_PFN_S 8
1594 #define FW_IQ_CMD_PFN_V(x) ((x) << FW_IQ_CMD_PFN_S)
1596 #define FW_IQ_CMD_VFN_S 0
1597 #define FW_IQ_CMD_VFN_V(x) ((x) << FW_IQ_CMD_VFN_S)
1599 #define FW_IQ_CMD_ALLOC_S 31
1600 #define FW_IQ_CMD_ALLOC_V(x) ((x) << FW_IQ_CMD_ALLOC_S)
1601 #define FW_IQ_CMD_ALLOC_F FW_IQ_CMD_ALLOC_V(1U)
1603 #define FW_IQ_CMD_FREE_S 30
1604 #define FW_IQ_CMD_FREE_V(x) ((x) << FW_IQ_CMD_FREE_S)
1605 #define FW_IQ_CMD_FREE_F FW_IQ_CMD_FREE_V(1U)
1607 #define FW_IQ_CMD_MODIFY_S 29
1608 #define FW_IQ_CMD_MODIFY_V(x) ((x) << FW_IQ_CMD_MODIFY_S)
1609 #define FW_IQ_CMD_MODIFY_F FW_IQ_CMD_MODIFY_V(1U)
1611 #define FW_IQ_CMD_IQSTART_S 28
1612 #define FW_IQ_CMD_IQSTART_V(x) ((x) << FW_IQ_CMD_IQSTART_S)
1613 #define FW_IQ_CMD_IQSTART_F FW_IQ_CMD_IQSTART_V(1U)
1615 #define FW_IQ_CMD_IQSTOP_S 27
1616 #define FW_IQ_CMD_IQSTOP_V(x) ((x) << FW_IQ_CMD_IQSTOP_S)
1617 #define FW_IQ_CMD_IQSTOP_F FW_IQ_CMD_IQSTOP_V(1U)
1619 #define FW_IQ_CMD_TYPE_S 29
1620 #define FW_IQ_CMD_TYPE_V(x) ((x) << FW_IQ_CMD_TYPE_S)
1622 #define FW_IQ_CMD_IQASYNCH_S 28
1623 #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S)
1625 #define FW_IQ_CMD_VIID_S 16
1626 #define FW_IQ_CMD_VIID_V(x) ((x) << FW_IQ_CMD_VIID_S)
1628 #define FW_IQ_CMD_IQANDST_S 15
1629 #define FW_IQ_CMD_IQANDST_V(x) ((x) << FW_IQ_CMD_IQANDST_S)
1631 #define FW_IQ_CMD_IQANUS_S 14
1632 #define FW_IQ_CMD_IQANUS_V(x) ((x) << FW_IQ_CMD_IQANUS_S)
1634 #define FW_IQ_CMD_IQANUD_S 12
1635 #define FW_IQ_CMD_IQANUD_V(x) ((x) << FW_IQ_CMD_IQANUD_S)
1637 #define FW_IQ_CMD_IQANDSTINDEX_S 0
1638 #define FW_IQ_CMD_IQANDSTINDEX_V(x) ((x) << FW_IQ_CMD_IQANDSTINDEX_S)
1640 #define FW_IQ_CMD_IQDROPRSS_S 15
1641 #define FW_IQ_CMD_IQDROPRSS_V(x) ((x) << FW_IQ_CMD_IQDROPRSS_S)
1642 #define FW_IQ_CMD_IQDROPRSS_F FW_IQ_CMD_IQDROPRSS_V(1U)
1644 #define FW_IQ_CMD_IQGTSMODE_S 14
1645 #define FW_IQ_CMD_IQGTSMODE_V(x) ((x) << FW_IQ_CMD_IQGTSMODE_S)
1646 #define FW_IQ_CMD_IQGTSMODE_F FW_IQ_CMD_IQGTSMODE_V(1U)
1648 #define FW_IQ_CMD_IQPCIECH_S 12
1649 #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S)
1651 #define FW_IQ_CMD_IQDCAEN_S 11
1652 #define FW_IQ_CMD_IQDCAEN_V(x) ((x) << FW_IQ_CMD_IQDCAEN_S)
1654 #define FW_IQ_CMD_IQDCACPU_S 6
1655 #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S)
1657 #define FW_IQ_CMD_IQINTCNTTHRESH_S 4
1658 #define FW_IQ_CMD_IQINTCNTTHRESH_V(x) ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S)
1660 #define FW_IQ_CMD_IQO_S 3
1661 #define FW_IQ_CMD_IQO_V(x) ((x) << FW_IQ_CMD_IQO_S)
1662 #define FW_IQ_CMD_IQO_F FW_IQ_CMD_IQO_V(1U)
1664 #define FW_IQ_CMD_IQCPRIO_S 2
1665 #define FW_IQ_CMD_IQCPRIO_V(x) ((x) << FW_IQ_CMD_IQCPRIO_S)
1667 #define FW_IQ_CMD_IQESIZE_S 0
1668 #define FW_IQ_CMD_IQESIZE_V(x) ((x) << FW_IQ_CMD_IQESIZE_S)
1670 #define FW_IQ_CMD_IQNS_S 31
1671 #define FW_IQ_CMD_IQNS_V(x) ((x) << FW_IQ_CMD_IQNS_S)
1673 #define FW_IQ_CMD_IQRO_S 30
1674 #define FW_IQ_CMD_IQRO_V(x) ((x) << FW_IQ_CMD_IQRO_S)
1676 #define FW_IQ_CMD_IQFLINTIQHSEN_S 28
1677 #define FW_IQ_CMD_IQFLINTIQHSEN_V(x) ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S)
1679 #define FW_IQ_CMD_IQFLINTCONGEN_S 27
1680 #define FW_IQ_CMD_IQFLINTCONGEN_V(x) ((x) << FW_IQ_CMD_IQFLINTCONGEN_S)
1681 #define FW_IQ_CMD_IQFLINTCONGEN_F FW_IQ_CMD_IQFLINTCONGEN_V(1U)
1683 #define FW_IQ_CMD_IQFLINTISCSIC_S 26
1684 #define FW_IQ_CMD_IQFLINTISCSIC_V(x) ((x) << FW_IQ_CMD_IQFLINTISCSIC_S)
1686 #define FW_IQ_CMD_IQTYPE_S 24
1687 #define FW_IQ_CMD_IQTYPE_M 0x3
1688 #define FW_IQ_CMD_IQTYPE_V(x) ((x) << FW_IQ_CMD_IQTYPE_S)
1689 #define FW_IQ_CMD_IQTYPE_G(x) \
1690 (((x) >> FW_IQ_CMD_IQTYPE_S) & FW_IQ_CMD_IQTYPE_M)
1692 #define FW_IQ_CMD_FL0CNGCHMAP_S 20
1693 #define FW_IQ_CMD_FL0CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL0CNGCHMAP_S)
1695 #define FW_IQ_CMD_FL0CACHELOCK_S 15
1696 #define FW_IQ_CMD_FL0CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL0CACHELOCK_S)
1698 #define FW_IQ_CMD_FL0DBP_S 14
1699 #define FW_IQ_CMD_FL0DBP_V(x) ((x) << FW_IQ_CMD_FL0DBP_S)
1701 #define FW_IQ_CMD_FL0DATANS_S 13
1702 #define FW_IQ_CMD_FL0DATANS_V(x) ((x) << FW_IQ_CMD_FL0DATANS_S)
1704 #define FW_IQ_CMD_FL0DATARO_S 12
1705 #define FW_IQ_CMD_FL0DATARO_V(x) ((x) << FW_IQ_CMD_FL0DATARO_S)
1706 #define FW_IQ_CMD_FL0DATARO_F FW_IQ_CMD_FL0DATARO_V(1U)
1708 #define FW_IQ_CMD_FL0CONGCIF_S 11
1709 #define FW_IQ_CMD_FL0CONGCIF_V(x) ((x) << FW_IQ_CMD_FL0CONGCIF_S)
1710 #define FW_IQ_CMD_FL0CONGCIF_F FW_IQ_CMD_FL0CONGCIF_V(1U)
1712 #define FW_IQ_CMD_FL0ONCHIP_S 10
1713 #define FW_IQ_CMD_FL0ONCHIP_V(x) ((x) << FW_IQ_CMD_FL0ONCHIP_S)
1715 #define FW_IQ_CMD_FL0STATUSPGNS_S 9
1716 #define FW_IQ_CMD_FL0STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGNS_S)
1718 #define FW_IQ_CMD_FL0STATUSPGRO_S 8
1719 #define FW_IQ_CMD_FL0STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGRO_S)
1721 #define FW_IQ_CMD_FL0FETCHNS_S 7
1722 #define FW_IQ_CMD_FL0FETCHNS_V(x) ((x) << FW_IQ_CMD_FL0FETCHNS_S)
1724 #define FW_IQ_CMD_FL0FETCHRO_S 6
1725 #define FW_IQ_CMD_FL0FETCHRO_V(x) ((x) << FW_IQ_CMD_FL0FETCHRO_S)
1726 #define FW_IQ_CMD_FL0FETCHRO_F FW_IQ_CMD_FL0FETCHRO_V(1U)
1728 #define FW_IQ_CMD_FL0HOSTFCMODE_S 4
1729 #define FW_IQ_CMD_FL0HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S)
1731 #define FW_IQ_CMD_FL0CPRIO_S 3
1732 #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S)
1734 #define FW_IQ_CMD_FL0PADEN_S 2
1735 #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S)
1736 #define FW_IQ_CMD_FL0PADEN_F FW_IQ_CMD_FL0PADEN_V(1U)
1738 #define FW_IQ_CMD_FL0PACKEN_S 1
1739 #define FW_IQ_CMD_FL0PACKEN_V(x) ((x) << FW_IQ_CMD_FL0PACKEN_S)
1740 #define FW_IQ_CMD_FL0PACKEN_F FW_IQ_CMD_FL0PACKEN_V(1U)
1742 #define FW_IQ_CMD_FL0CONGEN_S 0
1743 #define FW_IQ_CMD_FL0CONGEN_V(x) ((x) << FW_IQ_CMD_FL0CONGEN_S)
1744 #define FW_IQ_CMD_FL0CONGEN_F FW_IQ_CMD_FL0CONGEN_V(1U)
1746 #define FW_IQ_CMD_FL0DCAEN_S 15
1747 #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S)
1749 #define FW_IQ_CMD_FL0DCACPU_S 10
1750 #define FW_IQ_CMD_FL0DCACPU_V(x) ((x) << FW_IQ_CMD_FL0DCACPU_S)
1752 #define FW_IQ_CMD_FL0FBMIN_S 7
1753 #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S)
1755 #define FW_IQ_CMD_FL0FBMAX_S 4
1756 #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S)
1758 #define FW_IQ_CMD_FL0CIDXFTHRESHO_S 3
1759 #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S)
1760 #define FW_IQ_CMD_FL0CIDXFTHRESHO_F FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U)
1762 #define FW_IQ_CMD_FL0CIDXFTHRESH_S 0
1763 #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S)
1765 #define FW_IQ_CMD_FL1CNGCHMAP_S 20
1766 #define FW_IQ_CMD_FL1CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL1CNGCHMAP_S)
1768 #define FW_IQ_CMD_FL1CACHELOCK_S 15
1769 #define FW_IQ_CMD_FL1CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL1CACHELOCK_S)
1771 #define FW_IQ_CMD_FL1DBP_S 14
1772 #define FW_IQ_CMD_FL1DBP_V(x) ((x) << FW_IQ_CMD_FL1DBP_S)
1774 #define FW_IQ_CMD_FL1DATANS_S 13
1775 #define FW_IQ_CMD_FL1DATANS_V(x) ((x) << FW_IQ_CMD_FL1DATANS_S)
1777 #define FW_IQ_CMD_FL1DATARO_S 12
1778 #define FW_IQ_CMD_FL1DATARO_V(x) ((x) << FW_IQ_CMD_FL1DATARO_S)
1780 #define FW_IQ_CMD_FL1CONGCIF_S 11
1781 #define FW_IQ_CMD_FL1CONGCIF_V(x) ((x) << FW_IQ_CMD_FL1CONGCIF_S)
1783 #define FW_IQ_CMD_FL1ONCHIP_S 10
1784 #define FW_IQ_CMD_FL1ONCHIP_V(x) ((x) << FW_IQ_CMD_FL1ONCHIP_S)
1786 #define FW_IQ_CMD_FL1STATUSPGNS_S 9
1787 #define FW_IQ_CMD_FL1STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGNS_S)
1789 #define FW_IQ_CMD_FL1STATUSPGRO_S 8
1790 #define FW_IQ_CMD_FL1STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGRO_S)
1792 #define FW_IQ_CMD_FL1FETCHNS_S 7
1793 #define FW_IQ_CMD_FL1FETCHNS_V(x) ((x) << FW_IQ_CMD_FL1FETCHNS_S)
1795 #define FW_IQ_CMD_FL1FETCHRO_S 6
1796 #define FW_IQ_CMD_FL1FETCHRO_V(x) ((x) << FW_IQ_CMD_FL1FETCHRO_S)
1798 #define FW_IQ_CMD_FL1HOSTFCMODE_S 4
1799 #define FW_IQ_CMD_FL1HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S)
1801 #define FW_IQ_CMD_FL1CPRIO_S 3
1802 #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S)
1804 #define FW_IQ_CMD_FL1PADEN_S 2
1805 #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S)
1806 #define FW_IQ_CMD_FL1PADEN_F FW_IQ_CMD_FL1PADEN_V(1U)
1808 #define FW_IQ_CMD_FL1PACKEN_S 1
1809 #define FW_IQ_CMD_FL1PACKEN_V(x) ((x) << FW_IQ_CMD_FL1PACKEN_S)
1810 #define FW_IQ_CMD_FL1PACKEN_F FW_IQ_CMD_FL1PACKEN_V(1U)
1812 #define FW_IQ_CMD_FL1CONGEN_S 0
1813 #define FW_IQ_CMD_FL1CONGEN_V(x) ((x) << FW_IQ_CMD_FL1CONGEN_S)
1814 #define FW_IQ_CMD_FL1CONGEN_F FW_IQ_CMD_FL1CONGEN_V(1U)
1816 #define FW_IQ_CMD_FL1DCAEN_S 15
1817 #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S)
1819 #define FW_IQ_CMD_FL1DCACPU_S 10
1820 #define FW_IQ_CMD_FL1DCACPU_V(x) ((x) << FW_IQ_CMD_FL1DCACPU_S)
1822 #define FW_IQ_CMD_FL1FBMIN_S 7
1823 #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S)
1825 #define FW_IQ_CMD_FL1FBMAX_S 4
1826 #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S)
1828 #define FW_IQ_CMD_FL1CIDXFTHRESHO_S 3
1829 #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S)
1830 #define FW_IQ_CMD_FL1CIDXFTHRESHO_F FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U)
1832 #define FW_IQ_CMD_FL1CIDXFTHRESH_S 0
1833 #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S)
1835 struct fw_eq_eth_cmd
{
1837 __be32 alloc_to_len16
;
1839 __be32 physeqid_pkd
;
1840 __be32 fetchszm_to_iqid
;
1841 __be32 dcaen_to_eqsize
;
1843 __be32 autoequiqe_to_viid
;
1844 __be32 timeren_timerix
;
1848 #define FW_EQ_ETH_CMD_PFN_S 8
1849 #define FW_EQ_ETH_CMD_PFN_V(x) ((x) << FW_EQ_ETH_CMD_PFN_S)
1851 #define FW_EQ_ETH_CMD_VFN_S 0
1852 #define FW_EQ_ETH_CMD_VFN_V(x) ((x) << FW_EQ_ETH_CMD_VFN_S)
1854 #define FW_EQ_ETH_CMD_ALLOC_S 31
1855 #define FW_EQ_ETH_CMD_ALLOC_V(x) ((x) << FW_EQ_ETH_CMD_ALLOC_S)
1856 #define FW_EQ_ETH_CMD_ALLOC_F FW_EQ_ETH_CMD_ALLOC_V(1U)
1858 #define FW_EQ_ETH_CMD_FREE_S 30
1859 #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S)
1860 #define FW_EQ_ETH_CMD_FREE_F FW_EQ_ETH_CMD_FREE_V(1U)
1862 #define FW_EQ_ETH_CMD_MODIFY_S 29
1863 #define FW_EQ_ETH_CMD_MODIFY_V(x) ((x) << FW_EQ_ETH_CMD_MODIFY_S)
1864 #define FW_EQ_ETH_CMD_MODIFY_F FW_EQ_ETH_CMD_MODIFY_V(1U)
1866 #define FW_EQ_ETH_CMD_EQSTART_S 28
1867 #define FW_EQ_ETH_CMD_EQSTART_V(x) ((x) << FW_EQ_ETH_CMD_EQSTART_S)
1868 #define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U)
1870 #define FW_EQ_ETH_CMD_EQSTOP_S 27
1871 #define FW_EQ_ETH_CMD_EQSTOP_V(x) ((x) << FW_EQ_ETH_CMD_EQSTOP_S)
1872 #define FW_EQ_ETH_CMD_EQSTOP_F FW_EQ_ETH_CMD_EQSTOP_V(1U)
1874 #define FW_EQ_ETH_CMD_EQID_S 0
1875 #define FW_EQ_ETH_CMD_EQID_M 0xfffff
1876 #define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S)
1877 #define FW_EQ_ETH_CMD_EQID_G(x) \
1878 (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M)
1880 #define FW_EQ_ETH_CMD_PHYSEQID_S 0
1881 #define FW_EQ_ETH_CMD_PHYSEQID_M 0xfffff
1882 #define FW_EQ_ETH_CMD_PHYSEQID_V(x) ((x) << FW_EQ_ETH_CMD_PHYSEQID_S)
1883 #define FW_EQ_ETH_CMD_PHYSEQID_G(x) \
1884 (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M)
1886 #define FW_EQ_ETH_CMD_FETCHSZM_S 26
1887 #define FW_EQ_ETH_CMD_FETCHSZM_V(x) ((x) << FW_EQ_ETH_CMD_FETCHSZM_S)
1888 #define FW_EQ_ETH_CMD_FETCHSZM_F FW_EQ_ETH_CMD_FETCHSZM_V(1U)
1890 #define FW_EQ_ETH_CMD_STATUSPGNS_S 25
1891 #define FW_EQ_ETH_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S)
1893 #define FW_EQ_ETH_CMD_STATUSPGRO_S 24
1894 #define FW_EQ_ETH_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S)
1896 #define FW_EQ_ETH_CMD_FETCHNS_S 23
1897 #define FW_EQ_ETH_CMD_FETCHNS_V(x) ((x) << FW_EQ_ETH_CMD_FETCHNS_S)
1899 #define FW_EQ_ETH_CMD_FETCHRO_S 22
1900 #define FW_EQ_ETH_CMD_FETCHRO_V(x) ((x) << FW_EQ_ETH_CMD_FETCHRO_S)
1901 #define FW_EQ_ETH_CMD_FETCHRO_F FW_EQ_ETH_CMD_FETCHRO_V(1U)
1903 #define FW_EQ_ETH_CMD_HOSTFCMODE_S 20
1904 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S)
1906 #define FW_EQ_ETH_CMD_CPRIO_S 19
1907 #define FW_EQ_ETH_CMD_CPRIO_V(x) ((x) << FW_EQ_ETH_CMD_CPRIO_S)
1909 #define FW_EQ_ETH_CMD_ONCHIP_S 18
1910 #define FW_EQ_ETH_CMD_ONCHIP_V(x) ((x) << FW_EQ_ETH_CMD_ONCHIP_S)
1912 #define FW_EQ_ETH_CMD_PCIECHN_S 16
1913 #define FW_EQ_ETH_CMD_PCIECHN_V(x) ((x) << FW_EQ_ETH_CMD_PCIECHN_S)
1915 #define FW_EQ_ETH_CMD_IQID_S 0
1916 #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S)
1918 #define FW_EQ_ETH_CMD_DCAEN_S 31
1919 #define FW_EQ_ETH_CMD_DCAEN_V(x) ((x) << FW_EQ_ETH_CMD_DCAEN_S)
1921 #define FW_EQ_ETH_CMD_DCACPU_S 26
1922 #define FW_EQ_ETH_CMD_DCACPU_V(x) ((x) << FW_EQ_ETH_CMD_DCACPU_S)
1924 #define FW_EQ_ETH_CMD_FBMIN_S 23
1925 #define FW_EQ_ETH_CMD_FBMIN_V(x) ((x) << FW_EQ_ETH_CMD_FBMIN_S)
1927 #define FW_EQ_ETH_CMD_FBMAX_S 20
1928 #define FW_EQ_ETH_CMD_FBMAX_V(x) ((x) << FW_EQ_ETH_CMD_FBMAX_S)
1930 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S 19
1931 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S)
1933 #define FW_EQ_ETH_CMD_CIDXFTHRESH_S 16
1934 #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S)
1936 #define FW_EQ_ETH_CMD_EQSIZE_S 0
1937 #define FW_EQ_ETH_CMD_EQSIZE_V(x) ((x) << FW_EQ_ETH_CMD_EQSIZE_S)
1939 #define FW_EQ_ETH_CMD_AUTOEQUIQE_S 31
1940 #define FW_EQ_ETH_CMD_AUTOEQUIQE_V(x) ((x) << FW_EQ_ETH_CMD_AUTOEQUIQE_S)
1941 #define FW_EQ_ETH_CMD_AUTOEQUIQE_F FW_EQ_ETH_CMD_AUTOEQUIQE_V(1U)
1943 #define FW_EQ_ETH_CMD_AUTOEQUEQE_S 30
1944 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x) ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S)
1945 #define FW_EQ_ETH_CMD_AUTOEQUEQE_F FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U)
1947 #define FW_EQ_ETH_CMD_VIID_S 16
1948 #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S)
1950 #define FW_EQ_ETH_CMD_TIMEREN_S 3
1951 #define FW_EQ_ETH_CMD_TIMEREN_M 0x1
1952 #define FW_EQ_ETH_CMD_TIMEREN_V(x) ((x) << FW_EQ_ETH_CMD_TIMEREN_S)
1953 #define FW_EQ_ETH_CMD_TIMEREN_G(x) \
1954 (((x) >> FW_EQ_ETH_CMD_TIMEREN_S) & FW_EQ_ETH_CMD_TIMEREN_M)
1955 #define FW_EQ_ETH_CMD_TIMEREN_F FW_EQ_ETH_CMD_TIMEREN_V(1U)
1957 #define FW_EQ_ETH_CMD_TIMERIX_S 0
1958 #define FW_EQ_ETH_CMD_TIMERIX_M 0x7
1959 #define FW_EQ_ETH_CMD_TIMERIX_V(x) ((x) << FW_EQ_ETH_CMD_TIMERIX_S)
1960 #define FW_EQ_ETH_CMD_TIMERIX_G(x) \
1961 (((x) >> FW_EQ_ETH_CMD_TIMERIX_S) & FW_EQ_ETH_CMD_TIMERIX_M)
1963 struct fw_eq_ctrl_cmd
{
1965 __be32 alloc_to_len16
;
1966 __be32 cmpliqid_eqid
;
1967 __be32 physeqid_pkd
;
1968 __be32 fetchszm_to_iqid
;
1969 __be32 dcaen_to_eqsize
;
1973 #define FW_EQ_CTRL_CMD_PFN_S 8
1974 #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S)
1976 #define FW_EQ_CTRL_CMD_VFN_S 0
1977 #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S)
1979 #define FW_EQ_CTRL_CMD_ALLOC_S 31
1980 #define FW_EQ_CTRL_CMD_ALLOC_V(x) ((x) << FW_EQ_CTRL_CMD_ALLOC_S)
1981 #define FW_EQ_CTRL_CMD_ALLOC_F FW_EQ_CTRL_CMD_ALLOC_V(1U)
1983 #define FW_EQ_CTRL_CMD_FREE_S 30
1984 #define FW_EQ_CTRL_CMD_FREE_V(x) ((x) << FW_EQ_CTRL_CMD_FREE_S)
1985 #define FW_EQ_CTRL_CMD_FREE_F FW_EQ_CTRL_CMD_FREE_V(1U)
1987 #define FW_EQ_CTRL_CMD_MODIFY_S 29
1988 #define FW_EQ_CTRL_CMD_MODIFY_V(x) ((x) << FW_EQ_CTRL_CMD_MODIFY_S)
1989 #define FW_EQ_CTRL_CMD_MODIFY_F FW_EQ_CTRL_CMD_MODIFY_V(1U)
1991 #define FW_EQ_CTRL_CMD_EQSTART_S 28
1992 #define FW_EQ_CTRL_CMD_EQSTART_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTART_S)
1993 #define FW_EQ_CTRL_CMD_EQSTART_F FW_EQ_CTRL_CMD_EQSTART_V(1U)
1995 #define FW_EQ_CTRL_CMD_EQSTOP_S 27
1996 #define FW_EQ_CTRL_CMD_EQSTOP_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTOP_S)
1997 #define FW_EQ_CTRL_CMD_EQSTOP_F FW_EQ_CTRL_CMD_EQSTOP_V(1U)
1999 #define FW_EQ_CTRL_CMD_CMPLIQID_S 20
2000 #define FW_EQ_CTRL_CMD_CMPLIQID_V(x) ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S)
2002 #define FW_EQ_CTRL_CMD_EQID_S 0
2003 #define FW_EQ_CTRL_CMD_EQID_M 0xfffff
2004 #define FW_EQ_CTRL_CMD_EQID_V(x) ((x) << FW_EQ_CTRL_CMD_EQID_S)
2005 #define FW_EQ_CTRL_CMD_EQID_G(x) \
2006 (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M)
2008 #define FW_EQ_CTRL_CMD_PHYSEQID_S 0
2009 #define FW_EQ_CTRL_CMD_PHYSEQID_M 0xfffff
2010 #define FW_EQ_CTRL_CMD_PHYSEQID_G(x) \
2011 (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M)
2013 #define FW_EQ_CTRL_CMD_FETCHSZM_S 26
2014 #define FW_EQ_CTRL_CMD_FETCHSZM_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S)
2015 #define FW_EQ_CTRL_CMD_FETCHSZM_F FW_EQ_CTRL_CMD_FETCHSZM_V(1U)
2017 #define FW_EQ_CTRL_CMD_STATUSPGNS_S 25
2018 #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S)
2019 #define FW_EQ_CTRL_CMD_STATUSPGNS_F FW_EQ_CTRL_CMD_STATUSPGNS_V(1U)
2021 #define FW_EQ_CTRL_CMD_STATUSPGRO_S 24
2022 #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S)
2023 #define FW_EQ_CTRL_CMD_STATUSPGRO_F FW_EQ_CTRL_CMD_STATUSPGRO_V(1U)
2025 #define FW_EQ_CTRL_CMD_FETCHNS_S 23
2026 #define FW_EQ_CTRL_CMD_FETCHNS_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHNS_S)
2027 #define FW_EQ_CTRL_CMD_FETCHNS_F FW_EQ_CTRL_CMD_FETCHNS_V(1U)
2029 #define FW_EQ_CTRL_CMD_FETCHRO_S 22
2030 #define FW_EQ_CTRL_CMD_FETCHRO_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHRO_S)
2031 #define FW_EQ_CTRL_CMD_FETCHRO_F FW_EQ_CTRL_CMD_FETCHRO_V(1U)
2033 #define FW_EQ_CTRL_CMD_HOSTFCMODE_S 20
2034 #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S)
2036 #define FW_EQ_CTRL_CMD_CPRIO_S 19
2037 #define FW_EQ_CTRL_CMD_CPRIO_V(x) ((x) << FW_EQ_CTRL_CMD_CPRIO_S)
2039 #define FW_EQ_CTRL_CMD_ONCHIP_S 18
2040 #define FW_EQ_CTRL_CMD_ONCHIP_V(x) ((x) << FW_EQ_CTRL_CMD_ONCHIP_S)
2042 #define FW_EQ_CTRL_CMD_PCIECHN_S 16
2043 #define FW_EQ_CTRL_CMD_PCIECHN_V(x) ((x) << FW_EQ_CTRL_CMD_PCIECHN_S)
2045 #define FW_EQ_CTRL_CMD_IQID_S 0
2046 #define FW_EQ_CTRL_CMD_IQID_V(x) ((x) << FW_EQ_CTRL_CMD_IQID_S)
2048 #define FW_EQ_CTRL_CMD_DCAEN_S 31
2049 #define FW_EQ_CTRL_CMD_DCAEN_V(x) ((x) << FW_EQ_CTRL_CMD_DCAEN_S)
2051 #define FW_EQ_CTRL_CMD_DCACPU_S 26
2052 #define FW_EQ_CTRL_CMD_DCACPU_V(x) ((x) << FW_EQ_CTRL_CMD_DCACPU_S)
2054 #define FW_EQ_CTRL_CMD_FBMIN_S 23
2055 #define FW_EQ_CTRL_CMD_FBMIN_V(x) ((x) << FW_EQ_CTRL_CMD_FBMIN_S)
2057 #define FW_EQ_CTRL_CMD_FBMAX_S 20
2058 #define FW_EQ_CTRL_CMD_FBMAX_V(x) ((x) << FW_EQ_CTRL_CMD_FBMAX_S)
2060 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S 19
2061 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x) \
2062 ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S)
2064 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S 16
2065 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S)
2067 #define FW_EQ_CTRL_CMD_EQSIZE_S 0
2068 #define FW_EQ_CTRL_CMD_EQSIZE_V(x) ((x) << FW_EQ_CTRL_CMD_EQSIZE_S)
2070 struct fw_eq_ofld_cmd
{
2072 __be32 alloc_to_len16
;
2074 __be32 physeqid_pkd
;
2075 __be32 fetchszm_to_iqid
;
2076 __be32 dcaen_to_eqsize
;
2080 #define FW_EQ_OFLD_CMD_PFN_S 8
2081 #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S)
2083 #define FW_EQ_OFLD_CMD_VFN_S 0
2084 #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S)
2086 #define FW_EQ_OFLD_CMD_ALLOC_S 31
2087 #define FW_EQ_OFLD_CMD_ALLOC_V(x) ((x) << FW_EQ_OFLD_CMD_ALLOC_S)
2088 #define FW_EQ_OFLD_CMD_ALLOC_F FW_EQ_OFLD_CMD_ALLOC_V(1U)
2090 #define FW_EQ_OFLD_CMD_FREE_S 30
2091 #define FW_EQ_OFLD_CMD_FREE_V(x) ((x) << FW_EQ_OFLD_CMD_FREE_S)
2092 #define FW_EQ_OFLD_CMD_FREE_F FW_EQ_OFLD_CMD_FREE_V(1U)
2094 #define FW_EQ_OFLD_CMD_MODIFY_S 29
2095 #define FW_EQ_OFLD_CMD_MODIFY_V(x) ((x) << FW_EQ_OFLD_CMD_MODIFY_S)
2096 #define FW_EQ_OFLD_CMD_MODIFY_F FW_EQ_OFLD_CMD_MODIFY_V(1U)
2098 #define FW_EQ_OFLD_CMD_EQSTART_S 28
2099 #define FW_EQ_OFLD_CMD_EQSTART_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTART_S)
2100 #define FW_EQ_OFLD_CMD_EQSTART_F FW_EQ_OFLD_CMD_EQSTART_V(1U)
2102 #define FW_EQ_OFLD_CMD_EQSTOP_S 27
2103 #define FW_EQ_OFLD_CMD_EQSTOP_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTOP_S)
2104 #define FW_EQ_OFLD_CMD_EQSTOP_F FW_EQ_OFLD_CMD_EQSTOP_V(1U)
2106 #define FW_EQ_OFLD_CMD_EQID_S 0
2107 #define FW_EQ_OFLD_CMD_EQID_M 0xfffff
2108 #define FW_EQ_OFLD_CMD_EQID_V(x) ((x) << FW_EQ_OFLD_CMD_EQID_S)
2109 #define FW_EQ_OFLD_CMD_EQID_G(x) \
2110 (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M)
2112 #define FW_EQ_OFLD_CMD_PHYSEQID_S 0
2113 #define FW_EQ_OFLD_CMD_PHYSEQID_M 0xfffff
2114 #define FW_EQ_OFLD_CMD_PHYSEQID_G(x) \
2115 (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M)
2117 #define FW_EQ_OFLD_CMD_FETCHSZM_S 26
2118 #define FW_EQ_OFLD_CMD_FETCHSZM_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S)
2120 #define FW_EQ_OFLD_CMD_STATUSPGNS_S 25
2121 #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S)
2123 #define FW_EQ_OFLD_CMD_STATUSPGRO_S 24
2124 #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S)
2126 #define FW_EQ_OFLD_CMD_FETCHNS_S 23
2127 #define FW_EQ_OFLD_CMD_FETCHNS_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHNS_S)
2129 #define FW_EQ_OFLD_CMD_FETCHRO_S 22
2130 #define FW_EQ_OFLD_CMD_FETCHRO_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHRO_S)
2131 #define FW_EQ_OFLD_CMD_FETCHRO_F FW_EQ_OFLD_CMD_FETCHRO_V(1U)
2133 #define FW_EQ_OFLD_CMD_HOSTFCMODE_S 20
2134 #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S)
2136 #define FW_EQ_OFLD_CMD_CPRIO_S 19
2137 #define FW_EQ_OFLD_CMD_CPRIO_V(x) ((x) << FW_EQ_OFLD_CMD_CPRIO_S)
2139 #define FW_EQ_OFLD_CMD_ONCHIP_S 18
2140 #define FW_EQ_OFLD_CMD_ONCHIP_V(x) ((x) << FW_EQ_OFLD_CMD_ONCHIP_S)
2142 #define FW_EQ_OFLD_CMD_PCIECHN_S 16
2143 #define FW_EQ_OFLD_CMD_PCIECHN_V(x) ((x) << FW_EQ_OFLD_CMD_PCIECHN_S)
2145 #define FW_EQ_OFLD_CMD_IQID_S 0
2146 #define FW_EQ_OFLD_CMD_IQID_V(x) ((x) << FW_EQ_OFLD_CMD_IQID_S)
2148 #define FW_EQ_OFLD_CMD_DCAEN_S 31
2149 #define FW_EQ_OFLD_CMD_DCAEN_V(x) ((x) << FW_EQ_OFLD_CMD_DCAEN_S)
2151 #define FW_EQ_OFLD_CMD_DCACPU_S 26
2152 #define FW_EQ_OFLD_CMD_DCACPU_V(x) ((x) << FW_EQ_OFLD_CMD_DCACPU_S)
2154 #define FW_EQ_OFLD_CMD_FBMIN_S 23
2155 #define FW_EQ_OFLD_CMD_FBMIN_V(x) ((x) << FW_EQ_OFLD_CMD_FBMIN_S)
2157 #define FW_EQ_OFLD_CMD_FBMAX_S 20
2158 #define FW_EQ_OFLD_CMD_FBMAX_V(x) ((x) << FW_EQ_OFLD_CMD_FBMAX_S)
2160 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S 19
2161 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x) \
2162 ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S)
2164 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S 16
2165 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S)
2167 #define FW_EQ_OFLD_CMD_EQSIZE_S 0
2168 #define FW_EQ_OFLD_CMD_EQSIZE_V(x) ((x) << FW_EQ_OFLD_CMD_EQSIZE_S)
2171 * Macros for VIID parsing:
2172 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
2175 #define FW_VIID_PFN_S 8
2176 #define FW_VIID_PFN_M 0x7
2177 #define FW_VIID_PFN_G(x) (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M)
2179 #define FW_VIID_VIVLD_S 7
2180 #define FW_VIID_VIVLD_M 0x1
2181 #define FW_VIID_VIVLD_G(x) (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M)
2183 #define FW_VIID_VIN_S 0
2184 #define FW_VIID_VIN_M 0x7F
2185 #define FW_VIID_VIN_G(x) (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M)
2189 __be32 alloc_to_len16
;
2205 #define FW_VI_CMD_PFN_S 8
2206 #define FW_VI_CMD_PFN_V(x) ((x) << FW_VI_CMD_PFN_S)
2208 #define FW_VI_CMD_VFN_S 0
2209 #define FW_VI_CMD_VFN_V(x) ((x) << FW_VI_CMD_VFN_S)
2211 #define FW_VI_CMD_ALLOC_S 31
2212 #define FW_VI_CMD_ALLOC_V(x) ((x) << FW_VI_CMD_ALLOC_S)
2213 #define FW_VI_CMD_ALLOC_F FW_VI_CMD_ALLOC_V(1U)
2215 #define FW_VI_CMD_FREE_S 30
2216 #define FW_VI_CMD_FREE_V(x) ((x) << FW_VI_CMD_FREE_S)
2217 #define FW_VI_CMD_FREE_F FW_VI_CMD_FREE_V(1U)
2219 #define FW_VI_CMD_VFVLD_S 24
2220 #define FW_VI_CMD_VFVLD_M 0x1
2221 #define FW_VI_CMD_VFVLD_V(x) ((x) << FW_VI_CMD_VFVLD_S)
2222 #define FW_VI_CMD_VFVLD_G(x) \
2223 (((x) >> FW_VI_CMD_VFVLD_S) & FW_VI_CMD_VFVLD_M)
2224 #define FW_VI_CMD_VFVLD_F FW_VI_CMD_VFVLD_V(1U)
2226 #define FW_VI_CMD_VIN_S 16
2227 #define FW_VI_CMD_VIN_M 0xff
2228 #define FW_VI_CMD_VIN_V(x) ((x) << FW_VI_CMD_VIN_S)
2229 #define FW_VI_CMD_VIN_G(x) \
2230 (((x) >> FW_VI_CMD_VIN_S) & FW_VI_CMD_VIN_M)
2232 #define FW_VI_CMD_VIID_S 0
2233 #define FW_VI_CMD_VIID_M 0xfff
2234 #define FW_VI_CMD_VIID_V(x) ((x) << FW_VI_CMD_VIID_S)
2235 #define FW_VI_CMD_VIID_G(x) (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M)
2237 #define FW_VI_CMD_PORTID_S 4
2238 #define FW_VI_CMD_PORTID_M 0xf
2239 #define FW_VI_CMD_PORTID_V(x) ((x) << FW_VI_CMD_PORTID_S)
2240 #define FW_VI_CMD_PORTID_G(x) \
2241 (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M)
2243 #define FW_VI_CMD_RSSSIZE_S 0
2244 #define FW_VI_CMD_RSSSIZE_M 0x7ff
2245 #define FW_VI_CMD_RSSSIZE_G(x) \
2246 (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M)
2248 /* Special VI_MAC command index ids */
2249 #define FW_VI_MAC_ADD_MAC 0x3FF
2250 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
2251 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD
2252 #define FW_VI_MAC_ID_BASED_FREE 0x3FC
2253 #define FW_CLS_TCAM_NUM_ENTRIES 336
2255 enum fw_vi_mac_smac
{
2256 FW_VI_MAC_MPS_TCAM_ENTRY
,
2257 FW_VI_MAC_MPS_TCAM_ONLY
,
2259 FW_VI_MAC_SMT_AND_MPSTCAM
2262 enum fw_vi_mac_result
{
2263 FW_VI_MAC_R_SUCCESS
,
2264 FW_VI_MAC_R_F_NONEXISTENT_NOMEM
,
2265 FW_VI_MAC_R_SMAC_FAIL
,
2266 FW_VI_MAC_R_F_ACL_CHECK
2269 enum fw_vi_mac_entry_types
{
2270 FW_VI_MAC_TYPE_EXACTMAC
,
2271 FW_VI_MAC_TYPE_HASHVEC
,
2273 FW_VI_MAC_TYPE_EXACTMAC_VNI
,
2276 struct fw_vi_mac_cmd
{
2278 __be32 freemacs_to_len16
;
2280 struct fw_vi_mac_exact
{
2281 __be16 valid_to_idx
;
2284 struct fw_vi_mac_hash
{
2287 struct fw_vi_mac_raw
{
2294 struct fw_vi_mac_vni
{
2295 __be16 valid_to_idx
;
2298 __u8 macaddr_mask
[6];
2299 __be32 lookup_type_to_vni
;
2300 __be32 vni_mask_pkd
;
2305 #define FW_VI_MAC_CMD_SMTID_S 12
2306 #define FW_VI_MAC_CMD_SMTID_M 0xff
2307 #define FW_VI_MAC_CMD_SMTID_V(x) ((x) << FW_VI_MAC_CMD_SMTID_S)
2308 #define FW_VI_MAC_CMD_SMTID_G(x) \
2309 (((x) >> FW_VI_MAC_CMD_SMTID_S) & FW_VI_MAC_CMD_SMTID_M)
2311 #define FW_VI_MAC_CMD_VIID_S 0
2312 #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S)
2314 #define FW_VI_MAC_CMD_FREEMACS_S 31
2315 #define FW_VI_MAC_CMD_FREEMACS_V(x) ((x) << FW_VI_MAC_CMD_FREEMACS_S)
2317 #define FW_VI_MAC_CMD_ENTRY_TYPE_S 23
2318 #define FW_VI_MAC_CMD_ENTRY_TYPE_M 0x7
2319 #define FW_VI_MAC_CMD_ENTRY_TYPE_V(x) ((x) << FW_VI_MAC_CMD_ENTRY_TYPE_S)
2320 #define FW_VI_MAC_CMD_ENTRY_TYPE_G(x) \
2321 (((x) >> FW_VI_MAC_CMD_ENTRY_TYPE_S) & FW_VI_MAC_CMD_ENTRY_TYPE_M)
2323 #define FW_VI_MAC_CMD_HASHVECEN_S 23
2324 #define FW_VI_MAC_CMD_HASHVECEN_V(x) ((x) << FW_VI_MAC_CMD_HASHVECEN_S)
2325 #define FW_VI_MAC_CMD_HASHVECEN_F FW_VI_MAC_CMD_HASHVECEN_V(1U)
2327 #define FW_VI_MAC_CMD_HASHUNIEN_S 22
2328 #define FW_VI_MAC_CMD_HASHUNIEN_V(x) ((x) << FW_VI_MAC_CMD_HASHUNIEN_S)
2330 #define FW_VI_MAC_CMD_VALID_S 15
2331 #define FW_VI_MAC_CMD_VALID_V(x) ((x) << FW_VI_MAC_CMD_VALID_S)
2332 #define FW_VI_MAC_CMD_VALID_F FW_VI_MAC_CMD_VALID_V(1U)
2334 #define FW_VI_MAC_CMD_PRIO_S 12
2335 #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S)
2337 #define FW_VI_MAC_CMD_SMAC_RESULT_S 10
2338 #define FW_VI_MAC_CMD_SMAC_RESULT_M 0x3
2339 #define FW_VI_MAC_CMD_SMAC_RESULT_V(x) ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S)
2340 #define FW_VI_MAC_CMD_SMAC_RESULT_G(x) \
2341 (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M)
2343 #define FW_VI_MAC_CMD_IDX_S 0
2344 #define FW_VI_MAC_CMD_IDX_M 0x3ff
2345 #define FW_VI_MAC_CMD_IDX_V(x) ((x) << FW_VI_MAC_CMD_IDX_S)
2346 #define FW_VI_MAC_CMD_IDX_G(x) \
2347 (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M)
2349 #define FW_VI_MAC_CMD_RAW_IDX_S 16
2350 #define FW_VI_MAC_CMD_RAW_IDX_M 0xffff
2351 #define FW_VI_MAC_CMD_RAW_IDX_V(x) ((x) << FW_VI_MAC_CMD_RAW_IDX_S)
2352 #define FW_VI_MAC_CMD_RAW_IDX_G(x) \
2353 (((x) >> FW_VI_MAC_CMD_RAW_IDX_S) & FW_VI_MAC_CMD_RAW_IDX_M)
2355 #define FW_VI_MAC_CMD_LOOKUP_TYPE_S 31
2356 #define FW_VI_MAC_CMD_LOOKUP_TYPE_M 0x1
2357 #define FW_VI_MAC_CMD_LOOKUP_TYPE_V(x) ((x) << FW_VI_MAC_CMD_LOOKUP_TYPE_S)
2358 #define FW_VI_MAC_CMD_LOOKUP_TYPE_G(x) \
2359 (((x) >> FW_VI_MAC_CMD_LOOKUP_TYPE_S) & FW_VI_MAC_CMD_LOOKUP_TYPE_M)
2360 #define FW_VI_MAC_CMD_LOOKUP_TYPE_F FW_VI_MAC_CMD_LOOKUP_TYPE_V(1U)
2362 #define FW_VI_MAC_CMD_DIP_HIT_S 30
2363 #define FW_VI_MAC_CMD_DIP_HIT_M 0x1
2364 #define FW_VI_MAC_CMD_DIP_HIT_V(x) ((x) << FW_VI_MAC_CMD_DIP_HIT_S)
2365 #define FW_VI_MAC_CMD_DIP_HIT_G(x) \
2366 (((x) >> FW_VI_MAC_CMD_DIP_HIT_S) & FW_VI_MAC_CMD_DIP_HIT_M)
2367 #define FW_VI_MAC_CMD_DIP_HIT_F FW_VI_MAC_CMD_DIP_HIT_V(1U)
2369 #define FW_VI_MAC_CMD_VNI_S 0
2370 #define FW_VI_MAC_CMD_VNI_M 0xffffff
2371 #define FW_VI_MAC_CMD_VNI_V(x) ((x) << FW_VI_MAC_CMD_VNI_S)
2372 #define FW_VI_MAC_CMD_VNI_G(x) \
2373 (((x) >> FW_VI_MAC_CMD_VNI_S) & FW_VI_MAC_CMD_VNI_M)
2375 #define FW_VI_MAC_CMD_VNI_MASK_S 0
2376 #define FW_VI_MAC_CMD_VNI_MASK_M 0xffffff
2377 #define FW_VI_MAC_CMD_VNI_MASK_V(x) ((x) << FW_VI_MAC_CMD_VNI_MASK_S)
2378 #define FW_VI_MAC_CMD_VNI_MASK_G(x) \
2379 (((x) >> FW_VI_MAC_CMD_VNI_MASK_S) & FW_VI_MAC_CMD_VNI_MASK_M)
2381 #define FW_RXMODE_MTU_NO_CHG 65535
2383 struct fw_vi_rxmode_cmd
{
2385 __be32 retval_len16
;
2386 __be32 mtu_to_vlanexen
;
2390 #define FW_VI_RXMODE_CMD_VIID_S 0
2391 #define FW_VI_RXMODE_CMD_VIID_V(x) ((x) << FW_VI_RXMODE_CMD_VIID_S)
2393 #define FW_VI_RXMODE_CMD_MTU_S 16
2394 #define FW_VI_RXMODE_CMD_MTU_M 0xffff
2395 #define FW_VI_RXMODE_CMD_MTU_V(x) ((x) << FW_VI_RXMODE_CMD_MTU_S)
2397 #define FW_VI_RXMODE_CMD_PROMISCEN_S 14
2398 #define FW_VI_RXMODE_CMD_PROMISCEN_M 0x3
2399 #define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S)
2401 #define FW_VI_RXMODE_CMD_ALLMULTIEN_S 12
2402 #define FW_VI_RXMODE_CMD_ALLMULTIEN_M 0x3
2403 #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x) \
2404 ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S)
2406 #define FW_VI_RXMODE_CMD_BROADCASTEN_S 10
2407 #define FW_VI_RXMODE_CMD_BROADCASTEN_M 0x3
2408 #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x) \
2409 ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S)
2411 #define FW_VI_RXMODE_CMD_VLANEXEN_S 8
2412 #define FW_VI_RXMODE_CMD_VLANEXEN_M 0x3
2413 #define FW_VI_RXMODE_CMD_VLANEXEN_V(x) ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S)
2415 struct fw_vi_enable_cmd
{
2417 __be32 ien_to_len16
;
2423 #define FW_VI_ENABLE_CMD_VIID_S 0
2424 #define FW_VI_ENABLE_CMD_VIID_V(x) ((x) << FW_VI_ENABLE_CMD_VIID_S)
2426 #define FW_VI_ENABLE_CMD_IEN_S 31
2427 #define FW_VI_ENABLE_CMD_IEN_V(x) ((x) << FW_VI_ENABLE_CMD_IEN_S)
2429 #define FW_VI_ENABLE_CMD_EEN_S 30
2430 #define FW_VI_ENABLE_CMD_EEN_V(x) ((x) << FW_VI_ENABLE_CMD_EEN_S)
2432 #define FW_VI_ENABLE_CMD_LED_S 29
2433 #define FW_VI_ENABLE_CMD_LED_V(x) ((x) << FW_VI_ENABLE_CMD_LED_S)
2434 #define FW_VI_ENABLE_CMD_LED_F FW_VI_ENABLE_CMD_LED_V(1U)
2436 #define FW_VI_ENABLE_CMD_DCB_INFO_S 28
2437 #define FW_VI_ENABLE_CMD_DCB_INFO_V(x) ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S)
2439 /* VI VF stats offset definitions */
2440 #define VI_VF_NUM_STATS 16
2441 enum fw_vi_stats_vf_index
{
2442 FW_VI_VF_STAT_TX_BCAST_BYTES_IX
,
2443 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX
,
2444 FW_VI_VF_STAT_TX_MCAST_BYTES_IX
,
2445 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX
,
2446 FW_VI_VF_STAT_TX_UCAST_BYTES_IX
,
2447 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX
,
2448 FW_VI_VF_STAT_TX_DROP_FRAMES_IX
,
2449 FW_VI_VF_STAT_TX_OFLD_BYTES_IX
,
2450 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX
,
2451 FW_VI_VF_STAT_RX_BCAST_BYTES_IX
,
2452 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX
,
2453 FW_VI_VF_STAT_RX_MCAST_BYTES_IX
,
2454 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX
,
2455 FW_VI_VF_STAT_RX_UCAST_BYTES_IX
,
2456 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX
,
2457 FW_VI_VF_STAT_RX_ERR_FRAMES_IX
2460 /* VI PF stats offset definitions */
2461 #define VI_PF_NUM_STATS 17
2462 enum fw_vi_stats_pf_index
{
2463 FW_VI_PF_STAT_TX_BCAST_BYTES_IX
,
2464 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX
,
2465 FW_VI_PF_STAT_TX_MCAST_BYTES_IX
,
2466 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX
,
2467 FW_VI_PF_STAT_TX_UCAST_BYTES_IX
,
2468 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX
,
2469 FW_VI_PF_STAT_TX_OFLD_BYTES_IX
,
2470 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX
,
2471 FW_VI_PF_STAT_RX_BYTES_IX
,
2472 FW_VI_PF_STAT_RX_FRAMES_IX
,
2473 FW_VI_PF_STAT_RX_BCAST_BYTES_IX
,
2474 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX
,
2475 FW_VI_PF_STAT_RX_MCAST_BYTES_IX
,
2476 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX
,
2477 FW_VI_PF_STAT_RX_UCAST_BYTES_IX
,
2478 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX
,
2479 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
2482 struct fw_vi_stats_cmd
{
2484 __be32 retval_len16
;
2486 struct fw_vi_stats_ctl
{
2497 struct fw_vi_stats_pf
{
2498 __be64 tx_bcast_bytes
;
2499 __be64 tx_bcast_frames
;
2500 __be64 tx_mcast_bytes
;
2501 __be64 tx_mcast_frames
;
2502 __be64 tx_ucast_bytes
;
2503 __be64 tx_ucast_frames
;
2504 __be64 tx_offload_bytes
;
2505 __be64 tx_offload_frames
;
2507 __be64 rx_pf_frames
;
2508 __be64 rx_bcast_bytes
;
2509 __be64 rx_bcast_frames
;
2510 __be64 rx_mcast_bytes
;
2511 __be64 rx_mcast_frames
;
2512 __be64 rx_ucast_bytes
;
2513 __be64 rx_ucast_frames
;
2514 __be64 rx_err_frames
;
2516 struct fw_vi_stats_vf
{
2517 __be64 tx_bcast_bytes
;
2518 __be64 tx_bcast_frames
;
2519 __be64 tx_mcast_bytes
;
2520 __be64 tx_mcast_frames
;
2521 __be64 tx_ucast_bytes
;
2522 __be64 tx_ucast_frames
;
2523 __be64 tx_drop_frames
;
2524 __be64 tx_offload_bytes
;
2525 __be64 tx_offload_frames
;
2526 __be64 rx_bcast_bytes
;
2527 __be64 rx_bcast_frames
;
2528 __be64 rx_mcast_bytes
;
2529 __be64 rx_mcast_frames
;
2530 __be64 rx_ucast_bytes
;
2531 __be64 rx_ucast_frames
;
2532 __be64 rx_err_frames
;
2537 #define FW_VI_STATS_CMD_VIID_S 0
2538 #define FW_VI_STATS_CMD_VIID_V(x) ((x) << FW_VI_STATS_CMD_VIID_S)
2540 #define FW_VI_STATS_CMD_NSTATS_S 12
2541 #define FW_VI_STATS_CMD_NSTATS_V(x) ((x) << FW_VI_STATS_CMD_NSTATS_S)
2543 #define FW_VI_STATS_CMD_IX_S 0
2544 #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S)
2546 struct fw_acl_mac_cmd
{
2561 #define FW_ACL_MAC_CMD_PFN_S 8
2562 #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S)
2564 #define FW_ACL_MAC_CMD_VFN_S 0
2565 #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S)
2567 #define FW_ACL_MAC_CMD_EN_S 31
2568 #define FW_ACL_MAC_CMD_EN_V(x) ((x) << FW_ACL_MAC_CMD_EN_S)
2570 struct fw_acl_vlan_cmd
{
2579 #define FW_ACL_VLAN_CMD_PFN_S 8
2580 #define FW_ACL_VLAN_CMD_PFN_V(x) ((x) << FW_ACL_VLAN_CMD_PFN_S)
2582 #define FW_ACL_VLAN_CMD_VFN_S 0
2583 #define FW_ACL_VLAN_CMD_VFN_V(x) ((x) << FW_ACL_VLAN_CMD_VFN_S)
2585 #define FW_ACL_VLAN_CMD_EN_S 31
2586 #define FW_ACL_VLAN_CMD_EN_M 0x1
2587 #define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S)
2588 #define FW_ACL_VLAN_CMD_EN_G(x) \
2589 (((x) >> S_FW_ACL_VLAN_CMD_EN_S) & FW_ACL_VLAN_CMD_EN_M)
2590 #define FW_ACL_VLAN_CMD_EN_F FW_ACL_VLAN_CMD_EN_V(1U)
2592 #define FW_ACL_VLAN_CMD_DROPNOVLAN_S 7
2593 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S)
2594 #define FW_ACL_VLAN_CMD_DROPNOVLAN_F FW_ACL_VLAN_CMD_DROPNOVLAN_V(1U)
2596 #define FW_ACL_VLAN_CMD_FM_S 6
2597 #define FW_ACL_VLAN_CMD_FM_M 0x1
2598 #define FW_ACL_VLAN_CMD_FM_V(x) ((x) << FW_ACL_VLAN_CMD_FM_S)
2599 #define FW_ACL_VLAN_CMD_FM_G(x) \
2600 (((x) >> FW_ACL_VLAN_CMD_FM_S) & FW_ACL_VLAN_CMD_FM_M)
2601 #define FW_ACL_VLAN_CMD_FM_F FW_ACL_VLAN_CMD_FM_V(1U)
2603 /* old 16-bit port capabilities bitmap (fw_port_cap16_t) */
2605 FW_PORT_CAP_SPEED_100M
= 0x0001,
2606 FW_PORT_CAP_SPEED_1G
= 0x0002,
2607 FW_PORT_CAP_SPEED_25G
= 0x0004,
2608 FW_PORT_CAP_SPEED_10G
= 0x0008,
2609 FW_PORT_CAP_SPEED_40G
= 0x0010,
2610 FW_PORT_CAP_SPEED_100G
= 0x0020,
2611 FW_PORT_CAP_FC_RX
= 0x0040,
2612 FW_PORT_CAP_FC_TX
= 0x0080,
2613 FW_PORT_CAP_ANEG
= 0x0100,
2614 FW_PORT_CAP_MDIAUTO
= 0x0200,
2615 FW_PORT_CAP_MDISTRAIGHT
= 0x0400,
2616 FW_PORT_CAP_FEC_RS
= 0x0800,
2617 FW_PORT_CAP_FEC_BASER_RS
= 0x1000,
2618 FW_PORT_CAP_FORCE_PAUSE
= 0x2000,
2619 FW_PORT_CAP_802_3_PAUSE
= 0x4000,
2620 FW_PORT_CAP_802_3_ASM_DIR
= 0x8000,
2623 #define FW_PORT_CAP_SPEED_S 0
2624 #define FW_PORT_CAP_SPEED_M 0x3f
2625 #define FW_PORT_CAP_SPEED_V(x) ((x) << FW_PORT_CAP_SPEED_S)
2626 #define FW_PORT_CAP_SPEED_G(x) \
2627 (((x) >> FW_PORT_CAP_SPEED_S) & FW_PORT_CAP_SPEED_M)
2630 FW_PORT_CAP_MDI_UNCHANGED
,
2631 FW_PORT_CAP_MDI_AUTO
,
2632 FW_PORT_CAP_MDI_F_STRAIGHT
,
2633 FW_PORT_CAP_MDI_F_CROSSOVER
2636 #define FW_PORT_CAP_MDI_S 9
2637 #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S)
2639 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
2640 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL
2641 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL
2642 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL
2643 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL
2644 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL
2645 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL
2646 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL
2647 #define FW_PORT_CAP32_SPEED_200G 0x00000080UL
2648 #define FW_PORT_CAP32_SPEED_400G 0x00000100UL
2649 #define FW_PORT_CAP32_SPEED_RESERVED1 0x00000200UL
2650 #define FW_PORT_CAP32_SPEED_RESERVED2 0x00000400UL
2651 #define FW_PORT_CAP32_SPEED_RESERVED3 0x00000800UL
2652 #define FW_PORT_CAP32_RESERVED1 0x0000f000UL
2653 #define FW_PORT_CAP32_FC_RX 0x00010000UL
2654 #define FW_PORT_CAP32_FC_TX 0x00020000UL
2655 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
2656 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
2657 #define FW_PORT_CAP32_ANEG 0x00100000UL
2658 #define FW_PORT_CAP32_MDIAUTO 0x00200000UL
2659 #define FW_PORT_CAP32_MDISTRAIGHT 0x00400000UL
2660 #define FW_PORT_CAP32_FEC_RS 0x00800000UL
2661 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
2662 #define FW_PORT_CAP32_FEC_RESERVED1 0x02000000UL
2663 #define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL
2664 #define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL
2665 #define FW_PORT_CAP32_FORCE_PAUSE 0x10000000UL
2666 #define FW_PORT_CAP32_RESERVED2 0xe0000000UL
2668 #define FW_PORT_CAP32_SPEED_S 0
2669 #define FW_PORT_CAP32_SPEED_M 0xfff
2670 #define FW_PORT_CAP32_SPEED_V(x) ((x) << FW_PORT_CAP32_SPEED_S)
2671 #define FW_PORT_CAP32_SPEED_G(x) \
2672 (((x) >> FW_PORT_CAP32_SPEED_S) & FW_PORT_CAP32_SPEED_M)
2674 #define FW_PORT_CAP32_FC_S 16
2675 #define FW_PORT_CAP32_FC_M 0x3
2676 #define FW_PORT_CAP32_FC_V(x) ((x) << FW_PORT_CAP32_FC_S)
2677 #define FW_PORT_CAP32_FC_G(x) \
2678 (((x) >> FW_PORT_CAP32_FC_S) & FW_PORT_CAP32_FC_M)
2680 #define FW_PORT_CAP32_802_3_S 18
2681 #define FW_PORT_CAP32_802_3_M 0x3
2682 #define FW_PORT_CAP32_802_3_V(x) ((x) << FW_PORT_CAP32_802_3_S)
2683 #define FW_PORT_CAP32_802_3_G(x) \
2684 (((x) >> FW_PORT_CAP32_802_3_S) & FW_PORT_CAP32_802_3_M)
2686 #define FW_PORT_CAP32_ANEG_S 20
2687 #define FW_PORT_CAP32_ANEG_M 0x1
2688 #define FW_PORT_CAP32_ANEG_V(x) ((x) << FW_PORT_CAP32_ANEG_S)
2689 #define FW_PORT_CAP32_ANEG_G(x) \
2690 (((x) >> FW_PORT_CAP32_ANEG_S) & FW_PORT_CAP32_ANEG_M)
2692 enum fw_port_mdi32
{
2693 FW_PORT_CAP32_MDI_UNCHANGED
,
2694 FW_PORT_CAP32_MDI_AUTO
,
2695 FW_PORT_CAP32_MDI_F_STRAIGHT
,
2696 FW_PORT_CAP32_MDI_F_CROSSOVER
2699 #define FW_PORT_CAP32_MDI_S 21
2700 #define FW_PORT_CAP32_MDI_M 3
2701 #define FW_PORT_CAP32_MDI_V(x) ((x) << FW_PORT_CAP32_MDI_S)
2702 #define FW_PORT_CAP32_MDI_G(x) \
2703 (((x) >> FW_PORT_CAP32_MDI_S) & FW_PORT_CAP32_MDI_M)
2705 #define FW_PORT_CAP32_FEC_S 23
2706 #define FW_PORT_CAP32_FEC_M 0x1f
2707 #define FW_PORT_CAP32_FEC_V(x) ((x) << FW_PORT_CAP32_FEC_S)
2708 #define FW_PORT_CAP32_FEC_G(x) \
2709 (((x) >> FW_PORT_CAP32_FEC_S) & FW_PORT_CAP32_FEC_M)
2711 /* macros to isolate various 32-bit Port Capabilities sub-fields */
2712 #define CAP32_SPEED(__cap32) \
2713 (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) & __cap32)
2715 #define CAP32_FEC(__cap32) \
2716 (FW_PORT_CAP32_FEC_V(FW_PORT_CAP32_FEC_M) & __cap32)
2718 enum fw_port_action
{
2719 FW_PORT_ACTION_L1_CFG
= 0x0001,
2720 FW_PORT_ACTION_L2_CFG
= 0x0002,
2721 FW_PORT_ACTION_GET_PORT_INFO
= 0x0003,
2722 FW_PORT_ACTION_L2_PPP_CFG
= 0x0004,
2723 FW_PORT_ACTION_L2_DCB_CFG
= 0x0005,
2724 FW_PORT_ACTION_DCB_READ_TRANS
= 0x0006,
2725 FW_PORT_ACTION_DCB_READ_RECV
= 0x0007,
2726 FW_PORT_ACTION_DCB_READ_DET
= 0x0008,
2727 FW_PORT_ACTION_L1_CFG32
= 0x0009,
2728 FW_PORT_ACTION_GET_PORT_INFO32
= 0x000a,
2729 FW_PORT_ACTION_LOW_PWR_TO_NORMAL
= 0x0010,
2730 FW_PORT_ACTION_L1_LOW_PWR_EN
= 0x0011,
2731 FW_PORT_ACTION_L2_WOL_MODE_EN
= 0x0012,
2732 FW_PORT_ACTION_LPBK_TO_NORMAL
= 0x0020,
2733 FW_PORT_ACTION_L1_LPBK
= 0x0021,
2734 FW_PORT_ACTION_L1_PMA_LPBK
= 0x0022,
2735 FW_PORT_ACTION_L1_PCS_LPBK
= 0x0023,
2736 FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK
= 0x0024,
2737 FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK
= 0x0025,
2738 FW_PORT_ACTION_PHY_RESET
= 0x0040,
2739 FW_PORT_ACTION_PMA_RESET
= 0x0041,
2740 FW_PORT_ACTION_PCS_RESET
= 0x0042,
2741 FW_PORT_ACTION_PHYXS_RESET
= 0x0043,
2742 FW_PORT_ACTION_DTEXS_REEST
= 0x0044,
2743 FW_PORT_ACTION_AN_RESET
= 0x0045
2746 enum fw_port_l2cfg_ctlbf
{
2747 FW_PORT_L2_CTLBF_OVLAN0
= 0x01,
2748 FW_PORT_L2_CTLBF_OVLAN1
= 0x02,
2749 FW_PORT_L2_CTLBF_OVLAN2
= 0x04,
2750 FW_PORT_L2_CTLBF_OVLAN3
= 0x08,
2751 FW_PORT_L2_CTLBF_IVLAN
= 0x10,
2752 FW_PORT_L2_CTLBF_TXIPG
= 0x20
2755 enum fw_port_dcb_versions
{
2756 FW_PORT_DCB_VER_UNKNOWN
,
2757 FW_PORT_DCB_VER_CEE1D0
,
2758 FW_PORT_DCB_VER_CEE1D01
,
2759 FW_PORT_DCB_VER_IEEE
,
2760 FW_PORT_DCB_VER_AUTO
= 7
2763 enum fw_port_dcb_cfg
{
2764 FW_PORT_DCB_CFG_PG
= 0x01,
2765 FW_PORT_DCB_CFG_PFC
= 0x02,
2766 FW_PORT_DCB_CFG_APPL
= 0x04
2769 enum fw_port_dcb_cfg_rc
{
2770 FW_PORT_DCB_CFG_SUCCESS
= 0x0,
2771 FW_PORT_DCB_CFG_ERROR
= 0x1
2774 enum fw_port_dcb_type
{
2775 FW_PORT_DCB_TYPE_PGID
= 0x00,
2776 FW_PORT_DCB_TYPE_PGRATE
= 0x01,
2777 FW_PORT_DCB_TYPE_PRIORATE
= 0x02,
2778 FW_PORT_DCB_TYPE_PFC
= 0x03,
2779 FW_PORT_DCB_TYPE_APP_ID
= 0x04,
2780 FW_PORT_DCB_TYPE_CONTROL
= 0x05,
2783 enum fw_port_dcb_feature_state
{
2784 FW_PORT_DCB_FEATURE_STATE_PENDING
= 0x0,
2785 FW_PORT_DCB_FEATURE_STATE_SUCCESS
= 0x1,
2786 FW_PORT_DCB_FEATURE_STATE_ERROR
= 0x2,
2787 FW_PORT_DCB_FEATURE_STATE_TIMEOUT
= 0x3,
2790 struct fw_port_cmd
{
2791 __be32 op_to_portid
;
2792 __be32 action_to_len16
;
2794 struct fw_port_l1cfg
{
2798 struct fw_port_l2cfg
{
2800 __u8 ovlan3_to_ivlan0
;
2802 __be16 txipg_force_pinfo
;
2813 struct fw_port_info
{
2814 __be32 lstatus_to_modtype
;
2825 struct fw_port_diags
{
2831 struct fw_port_dcb_pgid
{
2838 struct fw_port_dcb_pgrate
{
2842 __u8 num_tcs_supported
;
2846 struct fw_port_dcb_priorate
{
2850 __u8 strict_priorate
[8];
2852 struct fw_port_dcb_pfc
{
2859 struct fw_port_app_priority
{
2868 struct fw_port_dcb_control
{
2871 __be16 dcb_version_to_app_state
;
2876 struct fw_port_l1cfg32
{
2880 struct fw_port_info32
{
2881 __be32 lstatus32_to_cbllen32
;
2882 __be32 auxlinfo32_mtu32
;
2891 #define FW_PORT_CMD_READ_S 22
2892 #define FW_PORT_CMD_READ_V(x) ((x) << FW_PORT_CMD_READ_S)
2893 #define FW_PORT_CMD_READ_F FW_PORT_CMD_READ_V(1U)
2895 #define FW_PORT_CMD_PORTID_S 0
2896 #define FW_PORT_CMD_PORTID_M 0xf
2897 #define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S)
2898 #define FW_PORT_CMD_PORTID_G(x) \
2899 (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M)
2901 #define FW_PORT_CMD_ACTION_S 16
2902 #define FW_PORT_CMD_ACTION_M 0xffff
2903 #define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S)
2904 #define FW_PORT_CMD_ACTION_G(x) \
2905 (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M)
2907 #define FW_PORT_CMD_OVLAN3_S 7
2908 #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S)
2910 #define FW_PORT_CMD_OVLAN2_S 6
2911 #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S)
2913 #define FW_PORT_CMD_OVLAN1_S 5
2914 #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S)
2916 #define FW_PORT_CMD_OVLAN0_S 4
2917 #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S)
2919 #define FW_PORT_CMD_IVLAN0_S 3
2920 #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S)
2922 #define FW_PORT_CMD_TXIPG_S 3
2923 #define FW_PORT_CMD_TXIPG_V(x) ((x) << FW_PORT_CMD_TXIPG_S)
2925 #define FW_PORT_CMD_LSTATUS_S 31
2926 #define FW_PORT_CMD_LSTATUS_M 0x1
2927 #define FW_PORT_CMD_LSTATUS_V(x) ((x) << FW_PORT_CMD_LSTATUS_S)
2928 #define FW_PORT_CMD_LSTATUS_G(x) \
2929 (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M)
2930 #define FW_PORT_CMD_LSTATUS_F FW_PORT_CMD_LSTATUS_V(1U)
2932 #define FW_PORT_CMD_LSPEED_S 24
2933 #define FW_PORT_CMD_LSPEED_M 0x3f
2934 #define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S)
2935 #define FW_PORT_CMD_LSPEED_G(x) \
2936 (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M)
2938 #define FW_PORT_CMD_TXPAUSE_S 23
2939 #define FW_PORT_CMD_TXPAUSE_V(x) ((x) << FW_PORT_CMD_TXPAUSE_S)
2940 #define FW_PORT_CMD_TXPAUSE_F FW_PORT_CMD_TXPAUSE_V(1U)
2942 #define FW_PORT_CMD_RXPAUSE_S 22
2943 #define FW_PORT_CMD_RXPAUSE_V(x) ((x) << FW_PORT_CMD_RXPAUSE_S)
2944 #define FW_PORT_CMD_RXPAUSE_F FW_PORT_CMD_RXPAUSE_V(1U)
2946 #define FW_PORT_CMD_MDIOCAP_S 21
2947 #define FW_PORT_CMD_MDIOCAP_V(x) ((x) << FW_PORT_CMD_MDIOCAP_S)
2948 #define FW_PORT_CMD_MDIOCAP_F FW_PORT_CMD_MDIOCAP_V(1U)
2950 #define FW_PORT_CMD_MDIOADDR_S 16
2951 #define FW_PORT_CMD_MDIOADDR_M 0x1f
2952 #define FW_PORT_CMD_MDIOADDR_G(x) \
2953 (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M)
2955 #define FW_PORT_CMD_LPTXPAUSE_S 15
2956 #define FW_PORT_CMD_LPTXPAUSE_V(x) ((x) << FW_PORT_CMD_LPTXPAUSE_S)
2957 #define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U)
2959 #define FW_PORT_CMD_LPRXPAUSE_S 14
2960 #define FW_PORT_CMD_LPRXPAUSE_V(x) ((x) << FW_PORT_CMD_LPRXPAUSE_S)
2961 #define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U)
2963 #define FW_PORT_CMD_PTYPE_S 8
2964 #define FW_PORT_CMD_PTYPE_M 0x1f
2965 #define FW_PORT_CMD_PTYPE_G(x) \
2966 (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M)
2968 #define FW_PORT_CMD_LINKDNRC_S 5
2969 #define FW_PORT_CMD_LINKDNRC_M 0x7
2970 #define FW_PORT_CMD_LINKDNRC_G(x) \
2971 (((x) >> FW_PORT_CMD_LINKDNRC_S) & FW_PORT_CMD_LINKDNRC_M)
2973 #define FW_PORT_CMD_MODTYPE_S 0
2974 #define FW_PORT_CMD_MODTYPE_M 0x1f
2975 #define FW_PORT_CMD_MODTYPE_V(x) ((x) << FW_PORT_CMD_MODTYPE_S)
2976 #define FW_PORT_CMD_MODTYPE_G(x) \
2977 (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M)
2979 #define FW_PORT_CMD_DCBXDIS_S 7
2980 #define FW_PORT_CMD_DCBXDIS_V(x) ((x) << FW_PORT_CMD_DCBXDIS_S)
2981 #define FW_PORT_CMD_DCBXDIS_F FW_PORT_CMD_DCBXDIS_V(1U)
2983 #define FW_PORT_CMD_APPLY_S 7
2984 #define FW_PORT_CMD_APPLY_V(x) ((x) << FW_PORT_CMD_APPLY_S)
2985 #define FW_PORT_CMD_APPLY_F FW_PORT_CMD_APPLY_V(1U)
2987 #define FW_PORT_CMD_ALL_SYNCD_S 7
2988 #define FW_PORT_CMD_ALL_SYNCD_V(x) ((x) << FW_PORT_CMD_ALL_SYNCD_S)
2989 #define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U)
2991 #define FW_PORT_CMD_DCB_VERSION_S 12
2992 #define FW_PORT_CMD_DCB_VERSION_M 0x7
2993 #define FW_PORT_CMD_DCB_VERSION_G(x) \
2994 (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M)
2996 #define FW_PORT_CMD_LSTATUS32_S 31
2997 #define FW_PORT_CMD_LSTATUS32_M 0x1
2998 #define FW_PORT_CMD_LSTATUS32_V(x) ((x) << FW_PORT_CMD_LSTATUS32_S)
2999 #define FW_PORT_CMD_LSTATUS32_G(x) \
3000 (((x) >> FW_PORT_CMD_LSTATUS32_S) & FW_PORT_CMD_LSTATUS32_M)
3001 #define FW_PORT_CMD_LSTATUS32_F FW_PORT_CMD_LSTATUS32_V(1U)
3003 #define FW_PORT_CMD_LINKDNRC32_S 28
3004 #define FW_PORT_CMD_LINKDNRC32_M 0x7
3005 #define FW_PORT_CMD_LINKDNRC32_V(x) ((x) << FW_PORT_CMD_LINKDNRC32_S)
3006 #define FW_PORT_CMD_LINKDNRC32_G(x) \
3007 (((x) >> FW_PORT_CMD_LINKDNRC32_S) & FW_PORT_CMD_LINKDNRC32_M)
3009 #define FW_PORT_CMD_DCBXDIS32_S 27
3010 #define FW_PORT_CMD_DCBXDIS32_M 0x1
3011 #define FW_PORT_CMD_DCBXDIS32_V(x) ((x) << FW_PORT_CMD_DCBXDIS32_S)
3012 #define FW_PORT_CMD_DCBXDIS32_G(x) \
3013 (((x) >> FW_PORT_CMD_DCBXDIS32_S) & FW_PORT_CMD_DCBXDIS32_M)
3014 #define FW_PORT_CMD_DCBXDIS32_F FW_PORT_CMD_DCBXDIS32_V(1U)
3016 #define FW_PORT_CMD_MDIOCAP32_S 26
3017 #define FW_PORT_CMD_MDIOCAP32_M 0x1
3018 #define FW_PORT_CMD_MDIOCAP32_V(x) ((x) << FW_PORT_CMD_MDIOCAP32_S)
3019 #define FW_PORT_CMD_MDIOCAP32_G(x) \
3020 (((x) >> FW_PORT_CMD_MDIOCAP32_S) & FW_PORT_CMD_MDIOCAP32_M)
3021 #define FW_PORT_CMD_MDIOCAP32_F FW_PORT_CMD_MDIOCAP32_V(1U)
3023 #define FW_PORT_CMD_MDIOADDR32_S 21
3024 #define FW_PORT_CMD_MDIOADDR32_M 0x1f
3025 #define FW_PORT_CMD_MDIOADDR32_V(x) ((x) << FW_PORT_CMD_MDIOADDR32_S)
3026 #define FW_PORT_CMD_MDIOADDR32_G(x) \
3027 (((x) >> FW_PORT_CMD_MDIOADDR32_S) & FW_PORT_CMD_MDIOADDR32_M)
3029 #define FW_PORT_CMD_PORTTYPE32_S 13
3030 #define FW_PORT_CMD_PORTTYPE32_M 0xff
3031 #define FW_PORT_CMD_PORTTYPE32_V(x) ((x) << FW_PORT_CMD_PORTTYPE32_S)
3032 #define FW_PORT_CMD_PORTTYPE32_G(x) \
3033 (((x) >> FW_PORT_CMD_PORTTYPE32_S) & FW_PORT_CMD_PORTTYPE32_M)
3035 #define FW_PORT_CMD_MODTYPE32_S 8
3036 #define FW_PORT_CMD_MODTYPE32_M 0x1f
3037 #define FW_PORT_CMD_MODTYPE32_V(x) ((x) << FW_PORT_CMD_MODTYPE32_S)
3038 #define FW_PORT_CMD_MODTYPE32_G(x) \
3039 (((x) >> FW_PORT_CMD_MODTYPE32_S) & FW_PORT_CMD_MODTYPE32_M)
3041 #define FW_PORT_CMD_CBLLEN32_S 0
3042 #define FW_PORT_CMD_CBLLEN32_M 0xff
3043 #define FW_PORT_CMD_CBLLEN32_V(x) ((x) << FW_PORT_CMD_CBLLEN32_S)
3044 #define FW_PORT_CMD_CBLLEN32_G(x) \
3045 (((x) >> FW_PORT_CMD_CBLLEN32_S) & FW_PORT_CMD_CBLLEN32_M)
3047 #define FW_PORT_CMD_AUXLINFO32_S 24
3048 #define FW_PORT_CMD_AUXLINFO32_M 0xff
3049 #define FW_PORT_CMD_AUXLINFO32_V(x) ((x) << FW_PORT_CMD_AUXLINFO32_S)
3050 #define FW_PORT_CMD_AUXLINFO32_G(x) \
3051 (((x) >> FW_PORT_CMD_AUXLINFO32_S) & FW_PORT_CMD_AUXLINFO32_M)
3053 #define FW_PORT_AUXLINFO32_KX4_S 2
3054 #define FW_PORT_AUXLINFO32_KX4_M 0x1
3055 #define FW_PORT_AUXLINFO32_KX4_V(x) \
3056 ((x) << FW_PORT_AUXLINFO32_KX4_S)
3057 #define FW_PORT_AUXLINFO32_KX4_G(x) \
3058 (((x) >> FW_PORT_AUXLINFO32_KX4_S) & FW_PORT_AUXLINFO32_KX4_M)
3059 #define FW_PORT_AUXLINFO32_KX4_F FW_PORT_AUXLINFO32_KX4_V(1U)
3061 #define FW_PORT_AUXLINFO32_KR_S 1
3062 #define FW_PORT_AUXLINFO32_KR_M 0x1
3063 #define FW_PORT_AUXLINFO32_KR_V(x) \
3064 ((x) << FW_PORT_AUXLINFO32_KR_S)
3065 #define FW_PORT_AUXLINFO32_KR_G(x) \
3066 (((x) >> FW_PORT_AUXLINFO32_KR_S) & FW_PORT_AUXLINFO32_KR_M)
3067 #define FW_PORT_AUXLINFO32_KR_F FW_PORT_AUXLINFO32_KR_V(1U)
3069 #define FW_PORT_CMD_MTU32_S 0
3070 #define FW_PORT_CMD_MTU32_M 0xffff
3071 #define FW_PORT_CMD_MTU32_V(x) ((x) << FW_PORT_CMD_MTU32_S)
3072 #define FW_PORT_CMD_MTU32_G(x) \
3073 (((x) >> FW_PORT_CMD_MTU32_S) & FW_PORT_CMD_MTU32_M)
3076 FW_PORT_TYPE_FIBER_XFI
,
3077 FW_PORT_TYPE_FIBER_XAUI
,
3078 FW_PORT_TYPE_BT_SGMII
,
3079 FW_PORT_TYPE_BT_XFI
,
3080 FW_PORT_TYPE_BT_XAUI
,
3087 FW_PORT_TYPE_BP4_AP
,
3088 FW_PORT_TYPE_QSFP_10G
,
3091 FW_PORT_TYPE_BP40_BA
,
3092 FW_PORT_TYPE_KR4_100G
,
3093 FW_PORT_TYPE_CR4_QSFP
,
3094 FW_PORT_TYPE_CR_QSFP
,
3095 FW_PORT_TYPE_CR2_QSFP
,
3097 FW_PORT_TYPE_KR_SFP28
,
3098 FW_PORT_TYPE_KR_XLAUI
,
3100 FW_PORT_TYPE_NONE
= FW_PORT_CMD_PTYPE_M
3103 enum fw_port_module_type
{
3104 FW_PORT_MOD_TYPE_NA
,
3105 FW_PORT_MOD_TYPE_LR
,
3106 FW_PORT_MOD_TYPE_SR
,
3107 FW_PORT_MOD_TYPE_ER
,
3108 FW_PORT_MOD_TYPE_TWINAX_PASSIVE
,
3109 FW_PORT_MOD_TYPE_TWINAX_ACTIVE
,
3110 FW_PORT_MOD_TYPE_LRM
,
3111 FW_PORT_MOD_TYPE_ERROR
= FW_PORT_CMD_MODTYPE_M
- 3,
3112 FW_PORT_MOD_TYPE_UNKNOWN
= FW_PORT_CMD_MODTYPE_M
- 2,
3113 FW_PORT_MOD_TYPE_NOTSUPPORTED
= FW_PORT_CMD_MODTYPE_M
- 1,
3115 FW_PORT_MOD_TYPE_NONE
= FW_PORT_CMD_MODTYPE_M
3118 enum fw_port_mod_sub_type
{
3119 FW_PORT_MOD_SUB_TYPE_NA
,
3120 FW_PORT_MOD_SUB_TYPE_MV88E114X
= 0x1,
3121 FW_PORT_MOD_SUB_TYPE_TN8022
= 0x2,
3122 FW_PORT_MOD_SUB_TYPE_AQ1202
= 0x3,
3123 FW_PORT_MOD_SUB_TYPE_88x3120
= 0x4,
3124 FW_PORT_MOD_SUB_TYPE_BCM84834
= 0x5,
3125 FW_PORT_MOD_SUB_TYPE_BT_VSC8634
= 0x8,
3127 /* The following will never been in the VPD. They are TWINAX cable
3128 * lengths decoded from SFP+ module i2c PROMs. These should
3129 * almost certainly go somewhere else ...
3131 FW_PORT_MOD_SUB_TYPE_TWINAX_1
= 0x9,
3132 FW_PORT_MOD_SUB_TYPE_TWINAX_3
= 0xA,
3133 FW_PORT_MOD_SUB_TYPE_TWINAX_5
= 0xB,
3134 FW_PORT_MOD_SUB_TYPE_TWINAX_7
= 0xC,
3137 enum fw_port_stats_tx_index
{
3138 FW_STAT_TX_PORT_BYTES_IX
= 0,
3139 FW_STAT_TX_PORT_FRAMES_IX
,
3140 FW_STAT_TX_PORT_BCAST_IX
,
3141 FW_STAT_TX_PORT_MCAST_IX
,
3142 FW_STAT_TX_PORT_UCAST_IX
,
3143 FW_STAT_TX_PORT_ERROR_IX
,
3144 FW_STAT_TX_PORT_64B_IX
,
3145 FW_STAT_TX_PORT_65B_127B_IX
,
3146 FW_STAT_TX_PORT_128B_255B_IX
,
3147 FW_STAT_TX_PORT_256B_511B_IX
,
3148 FW_STAT_TX_PORT_512B_1023B_IX
,
3149 FW_STAT_TX_PORT_1024B_1518B_IX
,
3150 FW_STAT_TX_PORT_1519B_MAX_IX
,
3151 FW_STAT_TX_PORT_DROP_IX
,
3152 FW_STAT_TX_PORT_PAUSE_IX
,
3153 FW_STAT_TX_PORT_PPP0_IX
,
3154 FW_STAT_TX_PORT_PPP1_IX
,
3155 FW_STAT_TX_PORT_PPP2_IX
,
3156 FW_STAT_TX_PORT_PPP3_IX
,
3157 FW_STAT_TX_PORT_PPP4_IX
,
3158 FW_STAT_TX_PORT_PPP5_IX
,
3159 FW_STAT_TX_PORT_PPP6_IX
,
3160 FW_STAT_TX_PORT_PPP7_IX
,
3161 FW_NUM_PORT_TX_STATS
3164 enum fw_port_stat_rx_index
{
3165 FW_STAT_RX_PORT_BYTES_IX
= 0,
3166 FW_STAT_RX_PORT_FRAMES_IX
,
3167 FW_STAT_RX_PORT_BCAST_IX
,
3168 FW_STAT_RX_PORT_MCAST_IX
,
3169 FW_STAT_RX_PORT_UCAST_IX
,
3170 FW_STAT_RX_PORT_MTU_ERROR_IX
,
3171 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX
,
3172 FW_STAT_RX_PORT_CRC_ERROR_IX
,
3173 FW_STAT_RX_PORT_LEN_ERROR_IX
,
3174 FW_STAT_RX_PORT_SYM_ERROR_IX
,
3175 FW_STAT_RX_PORT_64B_IX
,
3176 FW_STAT_RX_PORT_65B_127B_IX
,
3177 FW_STAT_RX_PORT_128B_255B_IX
,
3178 FW_STAT_RX_PORT_256B_511B_IX
,
3179 FW_STAT_RX_PORT_512B_1023B_IX
,
3180 FW_STAT_RX_PORT_1024B_1518B_IX
,
3181 FW_STAT_RX_PORT_1519B_MAX_IX
,
3182 FW_STAT_RX_PORT_PAUSE_IX
,
3183 FW_STAT_RX_PORT_PPP0_IX
,
3184 FW_STAT_RX_PORT_PPP1_IX
,
3185 FW_STAT_RX_PORT_PPP2_IX
,
3186 FW_STAT_RX_PORT_PPP3_IX
,
3187 FW_STAT_RX_PORT_PPP4_IX
,
3188 FW_STAT_RX_PORT_PPP5_IX
,
3189 FW_STAT_RX_PORT_PPP6_IX
,
3190 FW_STAT_RX_PORT_PPP7_IX
,
3191 FW_STAT_RX_PORT_LESS_64B_IX
,
3192 FW_STAT_RX_PORT_MAC_ERROR_IX
,
3193 FW_NUM_PORT_RX_STATS
3197 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS)
3199 struct fw_port_stats_cmd
{
3200 __be32 op_to_portid
;
3201 __be32 retval_len16
;
3202 union fw_port_stats
{
3203 struct fw_port_stats_ctl
{
3215 struct fw_port_stats_all
{
3224 __be64 tx_128b_255b
;
3225 __be64 tx_256b_511b
;
3226 __be64 tx_512b_1023b
;
3227 __be64 tx_1024b_1518b
;
3228 __be64 tx_1519b_max
;
3244 __be64 rx_mtu_error
;
3245 __be64 rx_mtu_crc_error
;
3246 __be64 rx_crc_error
;
3247 __be64 rx_len_error
;
3248 __be64 rx_sym_error
;
3251 __be64 rx_128b_255b
;
3252 __be64 rx_256b_511b
;
3253 __be64 rx_512b_1023b
;
3254 __be64 rx_1024b_1518b
;
3255 __be64 rx_1519b_max
;
3272 /* port loopback stats */
3273 #define FW_NUM_LB_STATS 16
3274 enum fw_port_lb_stats_index
{
3275 FW_STAT_LB_PORT_BYTES_IX
,
3276 FW_STAT_LB_PORT_FRAMES_IX
,
3277 FW_STAT_LB_PORT_BCAST_IX
,
3278 FW_STAT_LB_PORT_MCAST_IX
,
3279 FW_STAT_LB_PORT_UCAST_IX
,
3280 FW_STAT_LB_PORT_ERROR_IX
,
3281 FW_STAT_LB_PORT_64B_IX
,
3282 FW_STAT_LB_PORT_65B_127B_IX
,
3283 FW_STAT_LB_PORT_128B_255B_IX
,
3284 FW_STAT_LB_PORT_256B_511B_IX
,
3285 FW_STAT_LB_PORT_512B_1023B_IX
,
3286 FW_STAT_LB_PORT_1024B_1518B_IX
,
3287 FW_STAT_LB_PORT_1519B_MAX_IX
,
3288 FW_STAT_LB_PORT_DROP_FRAMES_IX
3291 struct fw_port_lb_stats_cmd
{
3292 __be32 op_to_lbport
;
3293 __be32 retval_len16
;
3294 union fw_port_lb_stats
{
3295 struct fw_port_lb_stats_ctl
{
3307 struct fw_port_lb_stats_all
{
3316 __be64 tx_128b_255b
;
3317 __be64 tx_256b_511b
;
3318 __be64 tx_512b_1023b
;
3319 __be64 tx_1024b_1518b
;
3320 __be64 tx_1519b_max
;
3329 FW_PTP_SC_INIT_TIMER
= 0x00,
3330 FW_PTP_SC_TX_TYPE
= 0x01,
3332 FW_PTP_SC_RXTIME_STAMP
= 0x08,
3333 FW_PTP_SC_RDRX_TYPE
= 0x09,
3335 FW_PTP_SC_ADJ_FREQ
= 0x10,
3336 FW_PTP_SC_ADJ_TIME
= 0x11,
3337 FW_PTP_SC_ADJ_FTIME
= 0x12,
3338 FW_PTP_SC_WALL_CLOCK
= 0x13,
3339 FW_PTP_SC_GET_TIME
= 0x14,
3340 FW_PTP_SC_SET_TIME
= 0x15,
3344 __be32 op_to_portid
;
3345 __be32 retval_len16
;
3351 struct fw_ptp_init
{
3369 #define FW_PTP_CMD_PORTID_S 0
3370 #define FW_PTP_CMD_PORTID_M 0xf
3371 #define FW_PTP_CMD_PORTID_V(x) ((x) << FW_PTP_CMD_PORTID_S)
3372 #define FW_PTP_CMD_PORTID_G(x) \
3373 (((x) >> FW_PTP_CMD_PORTID_S) & FW_PTP_CMD_PORTID_M)
3375 struct fw_rss_ind_tbl_cmd
{
3377 __be32 retval_len16
;
3385 __be32 iq12_to_iq14
;
3386 __be32 iq15_to_iq17
;
3387 __be32 iq18_to_iq20
;
3388 __be32 iq21_to_iq23
;
3389 __be32 iq24_to_iq26
;
3390 __be32 iq27_to_iq29
;
3395 #define FW_RSS_IND_TBL_CMD_VIID_S 0
3396 #define FW_RSS_IND_TBL_CMD_VIID_V(x) ((x) << FW_RSS_IND_TBL_CMD_VIID_S)
3398 #define FW_RSS_IND_TBL_CMD_IQ0_S 20
3399 #define FW_RSS_IND_TBL_CMD_IQ0_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ0_S)
3401 #define FW_RSS_IND_TBL_CMD_IQ1_S 10
3402 #define FW_RSS_IND_TBL_CMD_IQ1_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ1_S)
3404 #define FW_RSS_IND_TBL_CMD_IQ2_S 0
3405 #define FW_RSS_IND_TBL_CMD_IQ2_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ2_S)
3407 struct fw_rss_glb_config_cmd
{
3409 __be32 retval_len16
;
3410 union fw_rss_glb_config
{
3411 struct fw_rss_glb_config_manual
{
3417 struct fw_rss_glb_config_basicvirtual
{
3419 __be32 synmapen_to_hashtoeplitz
;
3426 #define FW_RSS_GLB_CONFIG_CMD_MODE_S 28
3427 #define FW_RSS_GLB_CONFIG_CMD_MODE_M 0xf
3428 #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S)
3429 #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \
3430 (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M)
3432 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0
3433 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
3435 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S 8
3436 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x) \
3437 ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S)
3438 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F \
3439 FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U)
3441 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S 7
3442 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x) \
3443 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S)
3444 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F \
3445 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U)
3447 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S 6
3448 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x) \
3449 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S)
3450 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F \
3451 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U)
3453 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S 5
3454 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x) \
3455 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S)
3456 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F \
3457 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U)
3459 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S 4
3460 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x) \
3461 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S)
3462 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F \
3463 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U)
3465 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S 3
3466 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x) \
3467 ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S)
3468 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F \
3469 FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U)
3471 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S 2
3472 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x) \
3473 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S)
3474 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F \
3475 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U)
3477 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S 1
3478 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x) \
3479 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S)
3480 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F \
3481 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U)
3483 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S 0
3484 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \
3485 ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S)
3486 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F \
3487 FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U)
3489 struct fw_rss_vi_config_cmd
{
3491 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
3492 __be32 retval_len16
;
3493 union fw_rss_vi_config
{
3494 struct fw_rss_vi_config_manual
{
3499 struct fw_rss_vi_config_basicvirtual
{
3501 __be32 defaultq_to_udpen
;
3508 #define FW_RSS_VI_CONFIG_CMD_VIID_S 0
3509 #define FW_RSS_VI_CONFIG_CMD_VIID_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S)
3511 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S 16
3512 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M 0x3ff
3513 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x) \
3514 ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S)
3515 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x) \
3516 (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \
3517 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M)
3519 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S 4
3520 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x) \
3521 ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S)
3522 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F \
3523 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U)
3525 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S 3
3526 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x) \
3527 ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S)
3528 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F \
3529 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U)
3531 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S 2
3532 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x) \
3533 ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S)
3534 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F \
3535 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U)
3537 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S 1
3538 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x) \
3539 ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S)
3540 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F \
3541 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U)
3543 #define FW_RSS_VI_CONFIG_CMD_UDPEN_S 0
3544 #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S)
3545 #define FW_RSS_VI_CONFIG_CMD_UDPEN_F FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U)
3548 FW_SCHED_SC_PARAMS
= 1,
3551 struct fw_sched_cmd
{
3553 __be32 retval_len16
;
3555 struct fw_sched_config
{
3563 struct fw_sched_params
{
3582 struct fw_clip_cmd
{
3584 __be32 alloc_to_len16
;
3590 #define FW_CLIP_CMD_ALLOC_S 31
3591 #define FW_CLIP_CMD_ALLOC_V(x) ((x) << FW_CLIP_CMD_ALLOC_S)
3592 #define FW_CLIP_CMD_ALLOC_F FW_CLIP_CMD_ALLOC_V(1U)
3594 #define FW_CLIP_CMD_FREE_S 30
3595 #define FW_CLIP_CMD_FREE_V(x) ((x) << FW_CLIP_CMD_FREE_S)
3596 #define FW_CLIP_CMD_FREE_F FW_CLIP_CMD_FREE_V(1U)
3598 enum fw_error_type
{
3599 FW_ERROR_TYPE_EXCEPTION
= 0x0,
3600 FW_ERROR_TYPE_HWMODULE
= 0x1,
3601 FW_ERROR_TYPE_WR
= 0x2,
3602 FW_ERROR_TYPE_ACL
= 0x3,
3605 struct fw_error_cmd
{
3609 struct fw_error_exception
{
3612 struct fw_error_hwmodule
{
3616 struct fw_error_wr
{
3622 struct fw_error_acl
{
3633 struct fw_debug_cmd
{
3637 struct fw_debug_assert
{
3643 u8 filename_8_15
[8];
3646 struct fw_debug_prt
{
3649 __be32 dprtstrparam0
;
3650 __be32 dprtstrparam1
;
3651 __be32 dprtstrparam2
;
3652 __be32 dprtstrparam3
;
3657 #define FW_DEBUG_CMD_TYPE_S 0
3658 #define FW_DEBUG_CMD_TYPE_M 0xff
3659 #define FW_DEBUG_CMD_TYPE_G(x) \
3660 (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M)
3664 __be32 retval_len16
;
3665 __be32 mode_to_pcie_params
;
3667 __be32 addr_size_pkd
;
3669 __be64 phy_address
[5];
3672 #define FW_HMA_CMD_MODE_S 31
3673 #define FW_HMA_CMD_MODE_M 0x1
3674 #define FW_HMA_CMD_MODE_V(x) ((x) << FW_HMA_CMD_MODE_S)
3675 #define FW_HMA_CMD_MODE_G(x) \
3676 (((x) >> FW_HMA_CMD_MODE_S) & FW_HMA_CMD_MODE_M)
3677 #define FW_HMA_CMD_MODE_F FW_HMA_CMD_MODE_V(1U)
3679 #define FW_HMA_CMD_SOC_S 30
3680 #define FW_HMA_CMD_SOC_M 0x1
3681 #define FW_HMA_CMD_SOC_V(x) ((x) << FW_HMA_CMD_SOC_S)
3682 #define FW_HMA_CMD_SOC_G(x) (((x) >> FW_HMA_CMD_SOC_S) & FW_HMA_CMD_SOC_M)
3683 #define FW_HMA_CMD_SOC_F FW_HMA_CMD_SOC_V(1U)
3685 #define FW_HMA_CMD_EOC_S 29
3686 #define FW_HMA_CMD_EOC_M 0x1
3687 #define FW_HMA_CMD_EOC_V(x) ((x) << FW_HMA_CMD_EOC_S)
3688 #define FW_HMA_CMD_EOC_G(x) (((x) >> FW_HMA_CMD_EOC_S) & FW_HMA_CMD_EOC_M)
3689 #define FW_HMA_CMD_EOC_F FW_HMA_CMD_EOC_V(1U)
3691 #define FW_HMA_CMD_PCIE_PARAMS_S 0
3692 #define FW_HMA_CMD_PCIE_PARAMS_M 0x7ffffff
3693 #define FW_HMA_CMD_PCIE_PARAMS_V(x) ((x) << FW_HMA_CMD_PCIE_PARAMS_S)
3694 #define FW_HMA_CMD_PCIE_PARAMS_G(x) \
3695 (((x) >> FW_HMA_CMD_PCIE_PARAMS_S) & FW_HMA_CMD_PCIE_PARAMS_M)
3697 #define FW_HMA_CMD_NADDR_S 12
3698 #define FW_HMA_CMD_NADDR_M 0x3f
3699 #define FW_HMA_CMD_NADDR_V(x) ((x) << FW_HMA_CMD_NADDR_S)
3700 #define FW_HMA_CMD_NADDR_G(x) \
3701 (((x) >> FW_HMA_CMD_NADDR_S) & FW_HMA_CMD_NADDR_M)
3703 #define FW_HMA_CMD_SIZE_S 0
3704 #define FW_HMA_CMD_SIZE_M 0xfff
3705 #define FW_HMA_CMD_SIZE_V(x) ((x) << FW_HMA_CMD_SIZE_S)
3706 #define FW_HMA_CMD_SIZE_G(x) \
3707 (((x) >> FW_HMA_CMD_SIZE_S) & FW_HMA_CMD_SIZE_M)
3709 #define FW_HMA_CMD_ADDR_SIZE_S 11
3710 #define FW_HMA_CMD_ADDR_SIZE_M 0x1fffff
3711 #define FW_HMA_CMD_ADDR_SIZE_V(x) ((x) << FW_HMA_CMD_ADDR_SIZE_S)
3712 #define FW_HMA_CMD_ADDR_SIZE_G(x) \
3713 (((x) >> FW_HMA_CMD_ADDR_SIZE_S) & FW_HMA_CMD_ADDR_SIZE_M)
3716 PCIE_FW_EVAL_CRASH
= 0,
3719 #define PCIE_FW_ERR_S 31
3720 #define PCIE_FW_ERR_V(x) ((x) << PCIE_FW_ERR_S)
3721 #define PCIE_FW_ERR_F PCIE_FW_ERR_V(1U)
3723 #define PCIE_FW_INIT_S 30
3724 #define PCIE_FW_INIT_V(x) ((x) << PCIE_FW_INIT_S)
3725 #define PCIE_FW_INIT_F PCIE_FW_INIT_V(1U)
3727 #define PCIE_FW_HALT_S 29
3728 #define PCIE_FW_HALT_V(x) ((x) << PCIE_FW_HALT_S)
3729 #define PCIE_FW_HALT_F PCIE_FW_HALT_V(1U)
3731 #define PCIE_FW_EVAL_S 24
3732 #define PCIE_FW_EVAL_M 0x7
3733 #define PCIE_FW_EVAL_G(x) (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M)
3735 #define PCIE_FW_MASTER_VLD_S 15
3736 #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S)
3737 #define PCIE_FW_MASTER_VLD_F PCIE_FW_MASTER_VLD_V(1U)
3739 #define PCIE_FW_MASTER_S 12
3740 #define PCIE_FW_MASTER_M 0x7
3741 #define PCIE_FW_MASTER_V(x) ((x) << PCIE_FW_MASTER_S)
3742 #define PCIE_FW_MASTER_G(x) (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M)
3746 u8 chip
; /* terminator chip type */
3747 __be16 len512
; /* bin length in units of 512-bytes */
3748 __be32 fw_ver
; /* firmware version */
3749 __be32 tp_microcode_ver
;
3754 u8 intfver_iscsipdu
;
3762 __be32 reserved6
[23];
3771 #define FW_HDR_FW_VER_MAJOR_S 24
3772 #define FW_HDR_FW_VER_MAJOR_M 0xff
3773 #define FW_HDR_FW_VER_MAJOR_V(x) \
3774 ((x) << FW_HDR_FW_VER_MAJOR_S)
3775 #define FW_HDR_FW_VER_MAJOR_G(x) \
3776 (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M)
3778 #define FW_HDR_FW_VER_MINOR_S 16
3779 #define FW_HDR_FW_VER_MINOR_M 0xff
3780 #define FW_HDR_FW_VER_MINOR_V(x) \
3781 ((x) << FW_HDR_FW_VER_MINOR_S)
3782 #define FW_HDR_FW_VER_MINOR_G(x) \
3783 (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M)
3785 #define FW_HDR_FW_VER_MICRO_S 8
3786 #define FW_HDR_FW_VER_MICRO_M 0xff
3787 #define FW_HDR_FW_VER_MICRO_V(x) \
3788 ((x) << FW_HDR_FW_VER_MICRO_S)
3789 #define FW_HDR_FW_VER_MICRO_G(x) \
3790 (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M)
3792 #define FW_HDR_FW_VER_BUILD_S 0
3793 #define FW_HDR_FW_VER_BUILD_M 0xff
3794 #define FW_HDR_FW_VER_BUILD_V(x) \
3795 ((x) << FW_HDR_FW_VER_BUILD_S)
3796 #define FW_HDR_FW_VER_BUILD_G(x) \
3797 (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M)
3799 enum fw_hdr_intfver
{
3800 FW_HDR_INTFVER_NIC
= 0x00,
3801 FW_HDR_INTFVER_VNIC
= 0x00,
3802 FW_HDR_INTFVER_OFLD
= 0x00,
3803 FW_HDR_INTFVER_RI
= 0x00,
3804 FW_HDR_INTFVER_ISCSIPDU
= 0x00,
3805 FW_HDR_INTFVER_ISCSI
= 0x00,
3806 FW_HDR_INTFVER_FCOEPDU
= 0x00,
3807 FW_HDR_INTFVER_FCOE
= 0x00,
3811 FW_HDR_FLAGS_RESET_HALT
= 0x00000001,
3814 /* length of the formatting string */
3815 #define FW_DEVLOG_FMT_LEN 192
3817 /* maximum number of the formatting string parameters */
3818 #define FW_DEVLOG_FMT_PARAMS_NUM 8
3820 /* priority levels */
3821 enum fw_devlog_level
{
3822 FW_DEVLOG_LEVEL_EMERG
= 0x0,
3823 FW_DEVLOG_LEVEL_CRIT
= 0x1,
3824 FW_DEVLOG_LEVEL_ERR
= 0x2,
3825 FW_DEVLOG_LEVEL_NOTICE
= 0x3,
3826 FW_DEVLOG_LEVEL_INFO
= 0x4,
3827 FW_DEVLOG_LEVEL_DEBUG
= 0x5,
3828 FW_DEVLOG_LEVEL_MAX
= 0x5,
3831 /* facilities that may send a log message */
3832 enum fw_devlog_facility
{
3833 FW_DEVLOG_FACILITY_CORE
= 0x00,
3834 FW_DEVLOG_FACILITY_CF
= 0x01,
3835 FW_DEVLOG_FACILITY_SCHED
= 0x02,
3836 FW_DEVLOG_FACILITY_TIMER
= 0x04,
3837 FW_DEVLOG_FACILITY_RES
= 0x06,
3838 FW_DEVLOG_FACILITY_HW
= 0x08,
3839 FW_DEVLOG_FACILITY_FLR
= 0x10,
3840 FW_DEVLOG_FACILITY_DMAQ
= 0x12,
3841 FW_DEVLOG_FACILITY_PHY
= 0x14,
3842 FW_DEVLOG_FACILITY_MAC
= 0x16,
3843 FW_DEVLOG_FACILITY_PORT
= 0x18,
3844 FW_DEVLOG_FACILITY_VI
= 0x1A,
3845 FW_DEVLOG_FACILITY_FILTER
= 0x1C,
3846 FW_DEVLOG_FACILITY_ACL
= 0x1E,
3847 FW_DEVLOG_FACILITY_TM
= 0x20,
3848 FW_DEVLOG_FACILITY_QFC
= 0x22,
3849 FW_DEVLOG_FACILITY_DCB
= 0x24,
3850 FW_DEVLOG_FACILITY_ETH
= 0x26,
3851 FW_DEVLOG_FACILITY_OFLD
= 0x28,
3852 FW_DEVLOG_FACILITY_RI
= 0x2A,
3853 FW_DEVLOG_FACILITY_ISCSI
= 0x2C,
3854 FW_DEVLOG_FACILITY_FCOE
= 0x2E,
3855 FW_DEVLOG_FACILITY_FOISCSI
= 0x30,
3856 FW_DEVLOG_FACILITY_FOFCOE
= 0x32,
3857 FW_DEVLOG_FACILITY_CHNET
= 0x34,
3858 FW_DEVLOG_FACILITY_MAX
= 0x34,
3861 /* log message format */
3862 struct fw_devlog_e
{
3868 __u8 fmt
[FW_DEVLOG_FMT_LEN
];
3869 __be32 params
[FW_DEVLOG_FMT_PARAMS_NUM
];
3870 __be32 reserved3
[4];
3873 struct fw_devlog_cmd
{
3875 __be32 retval_len16
;
3878 __be32 memtype_devlog_memaddr16_devlog
;
3879 __be32 memsize_devlog
;
3883 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S 28
3884 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M 0xf
3885 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x) \
3886 (((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \
3887 FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M)
3889 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S 0
3890 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M 0xfffffff
3891 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x) \
3892 (((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \
3893 FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M)
3895 /* P C I E F W P F 7 R E G I S T E R */
3897 /* PF7 stores the Firmware Device Log parameters which allows Host Drivers to
3898 * access the "devlog" which needing to contact firmware. The encoding is
3899 * mostly the same as that returned by the DEVLOG command except for the size
3900 * which is encoded as the number of entries in multiples-1 of 128 here rather
3901 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128
3902 * and 15 means 2048. This of course in turn constrains the allowed values
3903 * for the devlog size ...
3905 #define PCIE_FW_PF_DEVLOG 7
3907 #define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28
3908 #define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf
3909 #define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \
3910 ((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S)
3911 #define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \
3912 (((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \
3913 PCIE_FW_PF_DEVLOG_NENTRIES128_M)
3915 #define PCIE_FW_PF_DEVLOG_ADDR16_S 4
3916 #define PCIE_FW_PF_DEVLOG_ADDR16_M 0xffffff
3917 #define PCIE_FW_PF_DEVLOG_ADDR16_V(x) ((x) << PCIE_FW_PF_DEVLOG_ADDR16_S)
3918 #define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \
3919 (((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M)
3921 #define PCIE_FW_PF_DEVLOG_MEMTYPE_S 0
3922 #define PCIE_FW_PF_DEVLOG_MEMTYPE_M 0xf
3923 #define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x) ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S)
3924 #define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \
3925 (((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M)
3927 #define MAX_IMM_OFLD_TX_DATA_WR_LEN (0xff + sizeof(struct fw_ofld_tx_data_wr))
3929 struct fw_crypto_lookaside_wr
{
3930 __be32 op_to_cctx_size
;
3933 __be32 rx_chid_to_rx_q_id
;
3935 __be32 pld_size_hash_size
;
3939 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_S 24
3940 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_M 0xff
3941 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_V(x) \
3942 ((x) << FW_CRYPTO_LOOKASIDE_WR_OPCODE_S)
3943 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_G(x) \
3944 (((x) >> FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) & \
3945 FW_CRYPTO_LOOKASIDE_WR_OPCODE_M)
3947 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_S 23
3948 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_M 0x1
3949 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_V(x) \
3950 ((x) << FW_CRYPTO_LOOKASIDE_WR_COMPL_S)
3951 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_G(x) \
3952 (((x) >> FW_CRYPTO_LOOKASIDE_WR_COMPL_S) & \
3953 FW_CRYPTO_LOOKASIDE_WR_COMPL_M)
3954 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_F FW_CRYPTO_LOOKASIDE_WR_COMPL_V(1U)
3956 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S 15
3957 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M 0xff
3958 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_V(x) \
3959 ((x) << FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S)
3960 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_G(x) \
3961 (((x) >> FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) & \
3962 FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M)
3964 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S 5
3965 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M 0x3
3966 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_V(x) \
3967 ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S)
3968 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_G(x) \
3969 (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) & \
3970 FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M)
3972 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S 0
3973 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M 0x1f
3974 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_V(x) \
3975 ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S)
3976 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_G(x) \
3977 (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) & \
3978 FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M)
3980 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_S 0
3981 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_M 0xff
3982 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_V(x) \
3983 ((x) << FW_CRYPTO_LOOKASIDE_WR_LEN16_S)
3984 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_G(x) \
3985 (((x) >> FW_CRYPTO_LOOKASIDE_WR_LEN16_S) & \
3986 FW_CRYPTO_LOOKASIDE_WR_LEN16_M)
3988 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S 29
3989 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M 0x3
3990 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_V(x) \
3991 ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S)
3992 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_G(x) \
3993 (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) & \
3994 FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M)
3996 #define FW_CRYPTO_LOOKASIDE_WR_LCB_S 27
3997 #define FW_CRYPTO_LOOKASIDE_WR_LCB_M 0x3
3998 #define FW_CRYPTO_LOOKASIDE_WR_LCB_V(x) \
3999 ((x) << FW_CRYPTO_LOOKASIDE_WR_LCB_S)
4000 #define FW_CRYPTO_LOOKASIDE_WR_LCB_G(x) \
4001 (((x) >> FW_CRYPTO_LOOKASIDE_WR_LCB_S) & FW_CRYPTO_LOOKASIDE_WR_LCB_M)
4003 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_S 25
4004 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_M 0x3
4005 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_V(x) \
4006 ((x) << FW_CRYPTO_LOOKASIDE_WR_PHASH_S)
4007 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_G(x) \
4008 (((x) >> FW_CRYPTO_LOOKASIDE_WR_PHASH_S) & \
4009 FW_CRYPTO_LOOKASIDE_WR_PHASH_M)
4011 #define FW_CRYPTO_LOOKASIDE_WR_IV_S 23
4012 #define FW_CRYPTO_LOOKASIDE_WR_IV_M 0x3
4013 #define FW_CRYPTO_LOOKASIDE_WR_IV_V(x) \
4014 ((x) << FW_CRYPTO_LOOKASIDE_WR_IV_S)
4015 #define FW_CRYPTO_LOOKASIDE_WR_IV_G(x) \
4016 (((x) >> FW_CRYPTO_LOOKASIDE_WR_IV_S) & FW_CRYPTO_LOOKASIDE_WR_IV_M)
4018 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_S 15
4019 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_M 0xff
4020 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_V(x) \
4021 ((x) << FW_CRYPTO_LOOKASIDE_WR_FQIDX_S)
4022 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_G(x) \
4023 (((x) >> FW_CRYPTO_LOOKASIDE_WR_FQIDX_S) & \
4024 FW_CRYPTO_LOOKASIDE_WR_FQIDX_M)
4026 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_S 10
4027 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_M 0x3
4028 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_V(x) \
4029 ((x) << FW_CRYPTO_LOOKASIDE_WR_TX_CH_S)
4030 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_G(x) \
4031 (((x) >> FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) & \
4032 FW_CRYPTO_LOOKASIDE_WR_TX_CH_M)
4034 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S 0
4035 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M 0x3ff
4036 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_V(x) \
4037 ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S)
4038 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_G(x) \
4039 (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) & \
4040 FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M)
4042 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S 24
4043 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M 0xff
4044 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_V(x) \
4045 ((x) << FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S)
4046 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_G(x) \
4047 (((x) >> FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) & \
4048 FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M)
4050 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S 17
4051 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M 0x7f
4052 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_V(x) \
4053 ((x) << FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S)
4054 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_G(x) \
4055 (((x) >> FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) & \
4056 FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M)
4058 struct fw_tlstx_data_wr
{
4059 __be32 op_to_immdlen
;
4060 __be32 flowid_len16
;
4062 __be32 lsodisable_to_flags
;
4064 __be32 ctxloc_to_exp
;
4066 __be16 adjustedplen_pkd
;
4067 __be16 expinplenmax_pkd
;
4068 u8 pdusinplenmax_pkd
;
4072 #define FW_TLSTX_DATA_WR_OPCODE_S 24
4073 #define FW_TLSTX_DATA_WR_OPCODE_M 0xff
4074 #define FW_TLSTX_DATA_WR_OPCODE_V(x) ((x) << FW_TLSTX_DATA_WR_OPCODE_S)
4075 #define FW_TLSTX_DATA_WR_OPCODE_G(x) \
4076 (((x) >> FW_TLSTX_DATA_WR_OPCODE_S) & FW_TLSTX_DATA_WR_OPCODE_M)
4078 #define FW_TLSTX_DATA_WR_COMPL_S 21
4079 #define FW_TLSTX_DATA_WR_COMPL_M 0x1
4080 #define FW_TLSTX_DATA_WR_COMPL_V(x) ((x) << FW_TLSTX_DATA_WR_COMPL_S)
4081 #define FW_TLSTX_DATA_WR_COMPL_G(x) \
4082 (((x) >> FW_TLSTX_DATA_WR_COMPL_S) & FW_TLSTX_DATA_WR_COMPL_M)
4083 #define FW_TLSTX_DATA_WR_COMPL_F FW_TLSTX_DATA_WR_COMPL_V(1U)
4085 #define FW_TLSTX_DATA_WR_IMMDLEN_S 0
4086 #define FW_TLSTX_DATA_WR_IMMDLEN_M 0xff
4087 #define FW_TLSTX_DATA_WR_IMMDLEN_V(x) ((x) << FW_TLSTX_DATA_WR_IMMDLEN_S)
4088 #define FW_TLSTX_DATA_WR_IMMDLEN_G(x) \
4089 (((x) >> FW_TLSTX_DATA_WR_IMMDLEN_S) & FW_TLSTX_DATA_WR_IMMDLEN_M)
4091 #define FW_TLSTX_DATA_WR_FLOWID_S 8
4092 #define FW_TLSTX_DATA_WR_FLOWID_M 0xfffff
4093 #define FW_TLSTX_DATA_WR_FLOWID_V(x) ((x) << FW_TLSTX_DATA_WR_FLOWID_S)
4094 #define FW_TLSTX_DATA_WR_FLOWID_G(x) \
4095 (((x) >> FW_TLSTX_DATA_WR_FLOWID_S) & FW_TLSTX_DATA_WR_FLOWID_M)
4097 #define FW_TLSTX_DATA_WR_LEN16_S 0
4098 #define FW_TLSTX_DATA_WR_LEN16_M 0xff
4099 #define FW_TLSTX_DATA_WR_LEN16_V(x) ((x) << FW_TLSTX_DATA_WR_LEN16_S)
4100 #define FW_TLSTX_DATA_WR_LEN16_G(x) \
4101 (((x) >> FW_TLSTX_DATA_WR_LEN16_S) & FW_TLSTX_DATA_WR_LEN16_M)
4103 #define FW_TLSTX_DATA_WR_LSODISABLE_S 31
4104 #define FW_TLSTX_DATA_WR_LSODISABLE_M 0x1
4105 #define FW_TLSTX_DATA_WR_LSODISABLE_V(x) \
4106 ((x) << FW_TLSTX_DATA_WR_LSODISABLE_S)
4107 #define FW_TLSTX_DATA_WR_LSODISABLE_G(x) \
4108 (((x) >> FW_TLSTX_DATA_WR_LSODISABLE_S) & FW_TLSTX_DATA_WR_LSODISABLE_M)
4109 #define FW_TLSTX_DATA_WR_LSODISABLE_F FW_TLSTX_DATA_WR_LSODISABLE_V(1U)
4111 #define FW_TLSTX_DATA_WR_ALIGNPLD_S 30
4112 #define FW_TLSTX_DATA_WR_ALIGNPLD_M 0x1
4113 #define FW_TLSTX_DATA_WR_ALIGNPLD_V(x) ((x) << FW_TLSTX_DATA_WR_ALIGNPLD_S)
4114 #define FW_TLSTX_DATA_WR_ALIGNPLD_G(x) \
4115 (((x) >> FW_TLSTX_DATA_WR_ALIGNPLD_S) & FW_TLSTX_DATA_WR_ALIGNPLD_M)
4116 #define FW_TLSTX_DATA_WR_ALIGNPLD_F FW_TLSTX_DATA_WR_ALIGNPLD_V(1U)
4118 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S 29
4119 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_M 0x1
4120 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_V(x) \
4121 ((x) << FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S)
4122 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_G(x) \
4123 (((x) >> FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S) & \
4124 FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_M)
4125 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_F FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_V(1U)
4127 #define FW_TLSTX_DATA_WR_FLAGS_S 0
4128 #define FW_TLSTX_DATA_WR_FLAGS_M 0xfffffff
4129 #define FW_TLSTX_DATA_WR_FLAGS_V(x) ((x) << FW_TLSTX_DATA_WR_FLAGS_S)
4130 #define FW_TLSTX_DATA_WR_FLAGS_G(x) \
4131 (((x) >> FW_TLSTX_DATA_WR_FLAGS_S) & FW_TLSTX_DATA_WR_FLAGS_M)
4133 #define FW_TLSTX_DATA_WR_CTXLOC_S 30
4134 #define FW_TLSTX_DATA_WR_CTXLOC_M 0x3
4135 #define FW_TLSTX_DATA_WR_CTXLOC_V(x) ((x) << FW_TLSTX_DATA_WR_CTXLOC_S)
4136 #define FW_TLSTX_DATA_WR_CTXLOC_G(x) \
4137 (((x) >> FW_TLSTX_DATA_WR_CTXLOC_S) & FW_TLSTX_DATA_WR_CTXLOC_M)
4139 #define FW_TLSTX_DATA_WR_IVDSGL_S 29
4140 #define FW_TLSTX_DATA_WR_IVDSGL_M 0x1
4141 #define FW_TLSTX_DATA_WR_IVDSGL_V(x) ((x) << FW_TLSTX_DATA_WR_IVDSGL_S)
4142 #define FW_TLSTX_DATA_WR_IVDSGL_G(x) \
4143 (((x) >> FW_TLSTX_DATA_WR_IVDSGL_S) & FW_TLSTX_DATA_WR_IVDSGL_M)
4144 #define FW_TLSTX_DATA_WR_IVDSGL_F FW_TLSTX_DATA_WR_IVDSGL_V(1U)
4146 #define FW_TLSTX_DATA_WR_KEYSIZE_S 24
4147 #define FW_TLSTX_DATA_WR_KEYSIZE_M 0x1f
4148 #define FW_TLSTX_DATA_WR_KEYSIZE_V(x) ((x) << FW_TLSTX_DATA_WR_KEYSIZE_S)
4149 #define FW_TLSTX_DATA_WR_KEYSIZE_G(x) \
4150 (((x) >> FW_TLSTX_DATA_WR_KEYSIZE_S) & FW_TLSTX_DATA_WR_KEYSIZE_M)
4152 #define FW_TLSTX_DATA_WR_NUMIVS_S 14
4153 #define FW_TLSTX_DATA_WR_NUMIVS_M 0xff
4154 #define FW_TLSTX_DATA_WR_NUMIVS_V(x) ((x) << FW_TLSTX_DATA_WR_NUMIVS_S)
4155 #define FW_TLSTX_DATA_WR_NUMIVS_G(x) \
4156 (((x) >> FW_TLSTX_DATA_WR_NUMIVS_S) & FW_TLSTX_DATA_WR_NUMIVS_M)
4158 #define FW_TLSTX_DATA_WR_EXP_S 0
4159 #define FW_TLSTX_DATA_WR_EXP_M 0x3fff
4160 #define FW_TLSTX_DATA_WR_EXP_V(x) ((x) << FW_TLSTX_DATA_WR_EXP_S)
4161 #define FW_TLSTX_DATA_WR_EXP_G(x) \
4162 (((x) >> FW_TLSTX_DATA_WR_EXP_S) & FW_TLSTX_DATA_WR_EXP_M)
4164 #define FW_TLSTX_DATA_WR_ADJUSTEDPLEN_S 1
4165 #define FW_TLSTX_DATA_WR_ADJUSTEDPLEN_V(x) \
4166 ((x) << FW_TLSTX_DATA_WR_ADJUSTEDPLEN_S)
4168 #define FW_TLSTX_DATA_WR_EXPINPLENMAX_S 4
4169 #define FW_TLSTX_DATA_WR_EXPINPLENMAX_V(x) \
4170 ((x) << FW_TLSTX_DATA_WR_EXPINPLENMAX_S)
4172 #define FW_TLSTX_DATA_WR_PDUSINPLENMAX_S 2
4173 #define FW_TLSTX_DATA_WR_PDUSINPLENMAX_V(x) \
4174 ((x) << FW_TLSTX_DATA_WR_PDUSINPLENMAX_S)
4176 #endif /* _T4FW_INTERFACE_H_ */