drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2009-2014 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #ifndef _T4FW_INTERFACE_H_
  36 #define _T4FW_INTERFACE_H_
  37
  38 enum fw_retval {
  39         FW_SUCCESS              = 0,    /* completed sucessfully */
  40         FW_EPERM                = 1,    /* operation not permitted */
  41         FW_ENOENT               = 2,    /* no such file or directory */
  42         FW_EIO                  = 5,    /* input/output error; hw bad */
  43         FW_ENOEXEC              = 8,    /* exec format error; inv microcode */
  44         FW_EAGAIN               = 11,   /* try again */
  45         FW_ENOMEM               = 12,   /* out of memory */
  46         FW_EFAULT               = 14,   /* bad address; fw bad */
  47         FW_EBUSY                = 16,   /* resource busy */
  48         FW_EEXIST               = 17,   /* file exists */
  49         FW_ENODEV               = 19,   /* no such device */
  50         FW_EINVAL               = 22,   /* invalid argument */
  51         FW_ENOSPC               = 28,   /* no space left on device */
  52         FW_ENOSYS               = 38,   /* functionality not implemented */
  53         FW_ENODATA              = 61,   /* no data available */
  54         FW_EPROTO               = 71,   /* protocol error */
  55         FW_EADDRINUSE           = 98,   /* address already in use */
  56         FW_EADDRNOTAVAIL        = 99,   /* cannot assigned requested address */
  57         FW_ENETDOWN             = 100,  /* network is down */
  58         FW_ENETUNREACH          = 101,  /* network is unreachable */
  59         FW_ENOBUFS              = 105,  /* no buffer space available */
  60         FW_ETIMEDOUT            = 110,  /* timeout */
  61         FW_EINPROGRESS          = 115,  /* fw internal */
  62         FW_SCSI_ABORT_REQUESTED = 128,  /* */
  63         FW_SCSI_ABORT_TIMEDOUT  = 129,  /* */
  64         FW_SCSI_ABORTED         = 130,  /* */
  65         FW_SCSI_CLOSE_REQUESTED = 131,  /* */
  66         FW_ERR_LINK_DOWN        = 132,  /* */
  67         FW_RDEV_NOT_READY       = 133,  /* */
  68         FW_ERR_RDEV_LOST        = 134,  /* */
  69         FW_ERR_RDEV_LOGO        = 135,  /* */
  70         FW_FCOE_NO_XCHG         = 136,  /* */
  71         FW_SCSI_RSP_ERR         = 137,  /* */
  72         FW_ERR_RDEV_IMPL_LOGO   = 138,  /* */
  73         FW_SCSI_UNDER_FLOW_ERR  = 139,  /* */
  74         FW_SCSI_OVER_FLOW_ERR   = 140,  /* */
  75         FW_SCSI_DDP_ERR         = 141,  /* DDP error*/
  76         FW_SCSI_TASK_ERR        = 142,  /* No SCSI tasks available */
  77 };
  78
  79 #define FW_T4VF_SGE_BASE_ADDR      0x0000
  80 #define FW_T4VF_MPS_BASE_ADDR      0x0100
  81 #define FW_T4VF_PL_BASE_ADDR       0x0200
  82 #define FW_T4VF_MBDATA_BASE_ADDR   0x0240
  83 #define FW_T4VF_CIM_BASE_ADDR      0x0300
  84
  85 enum fw_wr_opcodes {
  86         FW_FILTER_WR                   = 0x02,
  87         FW_ULPTX_WR                    = 0x04,
  88         FW_TP_WR                       = 0x05,
  89         FW_ETH_TX_PKT_WR               = 0x08,
  90         FW_OFLD_CONNECTION_WR          = 0x2f,
  91         FW_FLOWC_WR                    = 0x0a,
  92         FW_OFLD_TX_DATA_WR             = 0x0b,
  93         FW_CMD_WR                      = 0x10,
  94         FW_ETH_TX_PKT_VM_WR            = 0x11,
  95         FW_RI_RES_WR                   = 0x0c,
  96         FW_RI_INIT_WR                  = 0x0d,
  97         FW_RI_RDMA_WRITE_WR            = 0x14,
  98         FW_RI_SEND_WR                  = 0x15,
  99         FW_RI_RDMA_READ_WR             = 0x16,
 100         FW_RI_RECV_WR                  = 0x17,
 101         FW_RI_BIND_MW_WR               = 0x18,
 102         FW_RI_FR_NSMR_WR               = 0x19,
 103         FW_RI_INV_LSTAG_WR             = 0x1a,
 104         FW_LASTC2E_WR                  = 0x40
 105 };
 106
 107 struct fw_wr_hdr {
 108         __be32 hi;
 109         __be32 lo;
 110 };
 111
 112 /* work request opcode (hi) */
 113 #define FW_WR_OP_S      24
 114 #define FW_WR_OP_M      0xff
 115 #define FW_WR_OP_V(x)   ((x) << FW_WR_OP_S)
 116 #define FW_WR_OP_G(x)   (((x) >> FW_WR_OP_S) & FW_WR_OP_M)
 117
 118 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */
 119 #define FW_WR_ATOMIC_S          23
 120 #define FW_WR_ATOMIC_V(x)       ((x) << FW_WR_ATOMIC_S)
 121
 122 /* flush flag (hi) - firmware flushes flushable work request buffered
 123  * in the flow context.
 124  */
 125 #define FW_WR_FLUSH_S     22
 126 #define FW_WR_FLUSH_V(x)  ((x) << FW_WR_FLUSH_S)
 127
 128 /* completion flag (hi) - firmware generates a cpl_fw6_ack */
 129 #define FW_WR_COMPL_S     21
 130 #define FW_WR_COMPL_V(x)  ((x) << FW_WR_COMPL_S)
 131 #define FW_WR_COMPL_F     FW_WR_COMPL_V(1U)
 132
 133 /* work request immediate data length (hi) */
 134 #define FW_WR_IMMDLEN_S 0
 135 #define FW_WR_IMMDLEN_M 0xff
 136 #define FW_WR_IMMDLEN_V(x)      ((x) << FW_WR_IMMDLEN_S)
 137
 138 /* egress queue status update to associated ingress queue entry (lo) */
 139 #define FW_WR_EQUIQ_S           31
 140 #define FW_WR_EQUIQ_V(x)        ((x) << FW_WR_EQUIQ_S)
 141 #define FW_WR_EQUIQ_F           FW_WR_EQUIQ_V(1U)
 142
 143 /* egress queue status update to egress queue status entry (lo) */
 144 #define FW_WR_EQUEQ_S           30
 145 #define FW_WR_EQUEQ_V(x)        ((x) << FW_WR_EQUEQ_S)
 146 #define FW_WR_EQUEQ_F           FW_WR_EQUEQ_V(1U)
 147
 148 /* flow context identifier (lo) */
 149 #define FW_WR_FLOWID_S          8
 150 #define FW_WR_FLOWID_V(x)       ((x) << FW_WR_FLOWID_S)
 151
 152 /* length in units of 16-bytes (lo) */
 153 #define FW_WR_LEN16_S           0
 154 #define FW_WR_LEN16_V(x)        ((x) << FW_WR_LEN16_S)
 155
 156 #define HW_TPL_FR_MT_PR_IV_P_FC         0X32B
 157 #define HW_TPL_FR_MT_PR_OV_P_FC         0X327
 158
 159 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
 160 enum fw_filter_wr_cookie {
 161         FW_FILTER_WR_SUCCESS,
 162         FW_FILTER_WR_FLT_ADDED,
 163         FW_FILTER_WR_FLT_DELETED,
 164         FW_FILTER_WR_SMT_TBL_FULL,
 165         FW_FILTER_WR_EINVAL,
 166 };
 167
 168 struct fw_filter_wr {
 169         __be32 op_pkd;
 170         __be32 len16_pkd;
 171         __be64 r3;
 172         __be32 tid_to_iq;
 173         __be32 del_filter_to_l2tix;
 174         __be16 ethtype;
 175         __be16 ethtypem;
 176         __u8   frag_to_ovlan_vldm;
 177         __u8   smac_sel;
 178         __be16 rx_chan_rx_rpl_iq;
 179         __be32 maci_to_matchtypem;
 180         __u8   ptcl;
 181         __u8   ptclm;
 182         __u8   ttyp;
 183         __u8   ttypm;
 184         __be16 ivlan;
 185         __be16 ivlanm;
 186         __be16 ovlan;
 187         __be16 ovlanm;
 188         __u8   lip[16];
 189         __u8   lipm[16];
 190         __u8   fip[16];
 191         __u8   fipm[16];
 192         __be16 lp;
 193         __be16 lpm;
 194         __be16 fp;
 195         __be16 fpm;
 196         __be16 r7;
 197         __u8   sma[6];
 198 };
 199
 200 #define FW_FILTER_WR_TID_S      12
 201 #define FW_FILTER_WR_TID_M      0xfffff
 202 #define FW_FILTER_WR_TID_V(x)   ((x) << FW_FILTER_WR_TID_S)
 203 #define FW_FILTER_WR_TID_G(x)   \
 204         (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M)
 205
 206 #define FW_FILTER_WR_RQTYPE_S           11
 207 #define FW_FILTER_WR_RQTYPE_M           0x1
 208 #define FW_FILTER_WR_RQTYPE_V(x)        ((x) << FW_FILTER_WR_RQTYPE_S)
 209 #define FW_FILTER_WR_RQTYPE_G(x)        \
 210         (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M)
 211 #define FW_FILTER_WR_RQTYPE_F   FW_FILTER_WR_RQTYPE_V(1U)
 212
 213 #define FW_FILTER_WR_NOREPLY_S          10
 214 #define FW_FILTER_WR_NOREPLY_M          0x1
 215 #define FW_FILTER_WR_NOREPLY_V(x)       ((x) << FW_FILTER_WR_NOREPLY_S)
 216 #define FW_FILTER_WR_NOREPLY_G(x)       \
 217         (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M)
 218 #define FW_FILTER_WR_NOREPLY_F  FW_FILTER_WR_NOREPLY_V(1U)
 219
 220 #define FW_FILTER_WR_IQ_S       0
 221 #define FW_FILTER_WR_IQ_M       0x3ff
 222 #define FW_FILTER_WR_IQ_V(x)    ((x) << FW_FILTER_WR_IQ_S)
 223 #define FW_FILTER_WR_IQ_G(x)    \
 224         (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M)
 225
 226 #define FW_FILTER_WR_DEL_FILTER_S       31
 227 #define FW_FILTER_WR_DEL_FILTER_M       0x1
 228 #define FW_FILTER_WR_DEL_FILTER_V(x)    ((x) << FW_FILTER_WR_DEL_FILTER_S)
 229 #define FW_FILTER_WR_DEL_FILTER_G(x)    \
 230         (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M)
 231 #define FW_FILTER_WR_DEL_FILTER_F       FW_FILTER_WR_DEL_FILTER_V(1U)
 232
 233 #define FW_FILTER_WR_RPTTID_S           25
 234 #define FW_FILTER_WR_RPTTID_M           0x1
 235 #define FW_FILTER_WR_RPTTID_V(x)        ((x) << FW_FILTER_WR_RPTTID_S)
 236 #define FW_FILTER_WR_RPTTID_G(x)        \
 237         (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M)
 238 #define FW_FILTER_WR_RPTTID_F   FW_FILTER_WR_RPTTID_V(1U)
 239
 240 #define FW_FILTER_WR_DROP_S     24
 241 #define FW_FILTER_WR_DROP_M     0x1
 242 #define FW_FILTER_WR_DROP_V(x)  ((x) << FW_FILTER_WR_DROP_S)
 243 #define FW_FILTER_WR_DROP_G(x)  \
 244         (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M)
 245 #define FW_FILTER_WR_DROP_F     FW_FILTER_WR_DROP_V(1U)
 246
 247 #define FW_FILTER_WR_DIRSTEER_S         23
 248 #define FW_FILTER_WR_DIRSTEER_M         0x1
 249 #define FW_FILTER_WR_DIRSTEER_V(x)      ((x) << FW_FILTER_WR_DIRSTEER_S)
 250 #define FW_FILTER_WR_DIRSTEER_G(x)      \
 251         (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M)
 252 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U)
 253
 254 #define FW_FILTER_WR_MASKHASH_S         22
 255 #define FW_FILTER_WR_MASKHASH_M         0x1
 256 #define FW_FILTER_WR_MASKHASH_V(x)      ((x) << FW_FILTER_WR_MASKHASH_S)
 257 #define FW_FILTER_WR_MASKHASH_G(x)      \
 258         (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M)
 259 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U)
 260
 261 #define FW_FILTER_WR_DIRSTEERHASH_S     21
 262 #define FW_FILTER_WR_DIRSTEERHASH_M     0x1
 263 #define FW_FILTER_WR_DIRSTEERHASH_V(x)  ((x) << FW_FILTER_WR_DIRSTEERHASH_S)
 264 #define FW_FILTER_WR_DIRSTEERHASH_G(x)  \
 265         (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M)
 266 #define FW_FILTER_WR_DIRSTEERHASH_F     FW_FILTER_WR_DIRSTEERHASH_V(1U)
 267
 268 #define FW_FILTER_WR_LPBK_S     20
 269 #define FW_FILTER_WR_LPBK_M     0x1
 270 #define FW_FILTER_WR_LPBK_V(x)  ((x) << FW_FILTER_WR_LPBK_S)
 271 #define FW_FILTER_WR_LPBK_G(x)  \
 272         (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M)
 273 #define FW_FILTER_WR_LPBK_F     FW_FILTER_WR_LPBK_V(1U)
 274
 275 #define FW_FILTER_WR_DMAC_S     19
 276 #define FW_FILTER_WR_DMAC_M     0x1
 277 #define FW_FILTER_WR_DMAC_V(x)  ((x) << FW_FILTER_WR_DMAC_S)
 278 #define FW_FILTER_WR_DMAC_G(x)  \
 279         (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M)
 280 #define FW_FILTER_WR_DMAC_F     FW_FILTER_WR_DMAC_V(1U)
 281
 282 #define FW_FILTER_WR_SMAC_S     18
 283 #define FW_FILTER_WR_SMAC_M     0x1
 284 #define FW_FILTER_WR_SMAC_V(x)  ((x) << FW_FILTER_WR_SMAC_S)
 285 #define FW_FILTER_WR_SMAC_G(x)  \
 286         (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M)
 287 #define FW_FILTER_WR_SMAC_F     FW_FILTER_WR_SMAC_V(1U)
 288
 289 #define FW_FILTER_WR_INSVLAN_S          17
 290 #define FW_FILTER_WR_INSVLAN_M          0x1
 291 #define FW_FILTER_WR_INSVLAN_V(x)       ((x) << FW_FILTER_WR_INSVLAN_S)
 292 #define FW_FILTER_WR_INSVLAN_G(x)       \
 293         (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M)
 294 #define FW_FILTER_WR_INSVLAN_F  FW_FILTER_WR_INSVLAN_V(1U)
 295
 296 #define FW_FILTER_WR_RMVLAN_S           16
 297 #define FW_FILTER_WR_RMVLAN_M           0x1
 298 #define FW_FILTER_WR_RMVLAN_V(x)        ((x) << FW_FILTER_WR_RMVLAN_S)
 299 #define FW_FILTER_WR_RMVLAN_G(x)        \
 300         (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M)
 301 #define FW_FILTER_WR_RMVLAN_F   FW_FILTER_WR_RMVLAN_V(1U)
 302
 303 #define FW_FILTER_WR_HITCNTS_S          15
 304 #define FW_FILTER_WR_HITCNTS_M          0x1
 305 #define FW_FILTER_WR_HITCNTS_V(x)       ((x) << FW_FILTER_WR_HITCNTS_S)
 306 #define FW_FILTER_WR_HITCNTS_G(x)       \
 307         (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M)
 308 #define FW_FILTER_WR_HITCNTS_F  FW_FILTER_WR_HITCNTS_V(1U)
 309
 310 #define FW_FILTER_WR_TXCHAN_S           13
 311 #define FW_FILTER_WR_TXCHAN_M           0x3
 312 #define FW_FILTER_WR_TXCHAN_V(x)        ((x) << FW_FILTER_WR_TXCHAN_S)
 313 #define FW_FILTER_WR_TXCHAN_G(x)        \
 314         (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M)
 315
 316 #define FW_FILTER_WR_PRIO_S     12
 317 #define FW_FILTER_WR_PRIO_M     0x1
 318 #define FW_FILTER_WR_PRIO_V(x)  ((x) << FW_FILTER_WR_PRIO_S)
 319 #define FW_FILTER_WR_PRIO_G(x)  \
 320         (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M)
 321 #define FW_FILTER_WR_PRIO_F     FW_FILTER_WR_PRIO_V(1U)
 322
 323 #define FW_FILTER_WR_L2TIX_S    0
 324 #define FW_FILTER_WR_L2TIX_M    0xfff
 325 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S)
 326 #define FW_FILTER_WR_L2TIX_G(x) \
 327         (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M)
 328
 329 #define FW_FILTER_WR_FRAG_S     7
 330 #define FW_FILTER_WR_FRAG_M     0x1
 331 #define FW_FILTER_WR_FRAG_V(x)  ((x) << FW_FILTER_WR_FRAG_S)
 332 #define FW_FILTER_WR_FRAG_G(x)  \
 333         (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M)
 334 #define FW_FILTER_WR_FRAG_F     FW_FILTER_WR_FRAG_V(1U)
 335
 336 #define FW_FILTER_WR_FRAGM_S    6
 337 #define FW_FILTER_WR_FRAGM_M    0x1
 338 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S)
 339 #define FW_FILTER_WR_FRAGM_G(x) \
 340         (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M)
 341 #define FW_FILTER_WR_FRAGM_F    FW_FILTER_WR_FRAGM_V(1U)
 342
 343 #define FW_FILTER_WR_IVLAN_VLD_S        5
 344 #define FW_FILTER_WR_IVLAN_VLD_M        0x1
 345 #define FW_FILTER_WR_IVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_IVLAN_VLD_S)
 346 #define FW_FILTER_WR_IVLAN_VLD_G(x)     \
 347         (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M)
 348 #define FW_FILTER_WR_IVLAN_VLD_F        FW_FILTER_WR_IVLAN_VLD_V(1U)
 349
 350 #define FW_FILTER_WR_OVLAN_VLD_S        4
 351 #define FW_FILTER_WR_OVLAN_VLD_M        0x1
 352 #define FW_FILTER_WR_OVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_OVLAN_VLD_S)
 353 #define FW_FILTER_WR_OVLAN_VLD_G(x)     \
 354         (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M)
 355 #define FW_FILTER_WR_OVLAN_VLD_F        FW_FILTER_WR_OVLAN_VLD_V(1U)
 356
 357 #define FW_FILTER_WR_IVLAN_VLDM_S       3
 358 #define FW_FILTER_WR_IVLAN_VLDM_M       0x1
 359 #define FW_FILTER_WR_IVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_IVLAN_VLDM_S)
 360 #define FW_FILTER_WR_IVLAN_VLDM_G(x)    \
 361         (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M)
 362 #define FW_FILTER_WR_IVLAN_VLDM_F       FW_FILTER_WR_IVLAN_VLDM_V(1U)
 363
 364 #define FW_FILTER_WR_OVLAN_VLDM_S       2
 365 #define FW_FILTER_WR_OVLAN_VLDM_M       0x1
 366 #define FW_FILTER_WR_OVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_OVLAN_VLDM_S)
 367 #define FW_FILTER_WR_OVLAN_VLDM_G(x)    \
 368         (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M)
 369 #define FW_FILTER_WR_OVLAN_VLDM_F       FW_FILTER_WR_OVLAN_VLDM_V(1U)
 370
 371 #define FW_FILTER_WR_RX_CHAN_S          15
 372 #define FW_FILTER_WR_RX_CHAN_M          0x1
 373 #define FW_FILTER_WR_RX_CHAN_V(x)       ((x) << FW_FILTER_WR_RX_CHAN_S)
 374 #define FW_FILTER_WR_RX_CHAN_G(x)       \
 375         (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M)
 376 #define FW_FILTER_WR_RX_CHAN_F  FW_FILTER_WR_RX_CHAN_V(1U)
 377
 378 #define FW_FILTER_WR_RX_RPL_IQ_S        0
 379 #define FW_FILTER_WR_RX_RPL_IQ_M        0x3ff
 380 #define FW_FILTER_WR_RX_RPL_IQ_V(x)     ((x) << FW_FILTER_WR_RX_RPL_IQ_S)
 381 #define FW_FILTER_WR_RX_RPL_IQ_G(x)     \
 382         (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M)
 383
 384 #define FW_FILTER_WR_MACI_S     23
 385 #define FW_FILTER_WR_MACI_M     0x1ff
 386 #define FW_FILTER_WR_MACI_V(x)  ((x) << FW_FILTER_WR_MACI_S)
 387 #define FW_FILTER_WR_MACI_G(x)  \
 388         (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M)
 389
 390 #define FW_FILTER_WR_MACIM_S    14
 391 #define FW_FILTER_WR_MACIM_M    0x1ff
 392 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S)
 393 #define FW_FILTER_WR_MACIM_G(x) \
 394         (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M)
 395
 396 #define FW_FILTER_WR_FCOE_S     13
 397 #define FW_FILTER_WR_FCOE_M     0x1
 398 #define FW_FILTER_WR_FCOE_V(x)  ((x) << FW_FILTER_WR_FCOE_S)
 399 #define FW_FILTER_WR_FCOE_G(x)  \
 400         (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M)
 401 #define FW_FILTER_WR_FCOE_F     FW_FILTER_WR_FCOE_V(1U)
 402
 403 #define FW_FILTER_WR_FCOEM_S    12
 404 #define FW_FILTER_WR_FCOEM_M    0x1
 405 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S)
 406 #define FW_FILTER_WR_FCOEM_G(x) \
 407         (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M)
 408 #define FW_FILTER_WR_FCOEM_F    FW_FILTER_WR_FCOEM_V(1U)
 409
 410 #define FW_FILTER_WR_PORT_S     9
 411 #define FW_FILTER_WR_PORT_M     0x7
 412 #define FW_FILTER_WR_PORT_V(x)  ((x) << FW_FILTER_WR_PORT_S)
 413 #define FW_FILTER_WR_PORT_G(x)  \
 414         (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M)
 415
 416 #define FW_FILTER_WR_PORTM_S    6
 417 #define FW_FILTER_WR_PORTM_M    0x7
 418 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S)
 419 #define FW_FILTER_WR_PORTM_G(x) \
 420         (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M)
 421
 422 #define FW_FILTER_WR_MATCHTYPE_S        3
 423 #define FW_FILTER_WR_MATCHTYPE_M        0x7
 424 #define FW_FILTER_WR_MATCHTYPE_V(x)     ((x) << FW_FILTER_WR_MATCHTYPE_S)
 425 #define FW_FILTER_WR_MATCHTYPE_G(x)     \
 426         (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M)
 427
 428 #define FW_FILTER_WR_MATCHTYPEM_S       0
 429 #define FW_FILTER_WR_MATCHTYPEM_M       0x7
 430 #define FW_FILTER_WR_MATCHTYPEM_V(x)    ((x) << FW_FILTER_WR_MATCHTYPEM_S)
 431 #define FW_FILTER_WR_MATCHTYPEM_G(x)    \
 432         (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M)
 433
 434 struct fw_ulptx_wr {
 435         __be32 op_to_compl;
 436         __be32 flowid_len16;
 437         u64 cookie;
 438 };
 439
 440 struct fw_tp_wr {
 441         __be32 op_to_immdlen;
 442         __be32 flowid_len16;
 443         u64 cookie;
 444 };
 445
 446 struct fw_eth_tx_pkt_wr {
 447         __be32 op_immdlen;
 448         __be32 equiq_to_len16;
 449         __be64 r3;
 450 };
 451
 452 struct fw_ofld_connection_wr {
 453         __be32 op_compl;
 454         __be32 len16_pkd;
 455         __u64  cookie;
 456         __be64 r2;
 457         __be64 r3;
 458         struct fw_ofld_connection_le {
 459                 __be32 version_cpl;
 460                 __be32 filter;
 461                 __be32 r1;
 462                 __be16 lport;
 463                 __be16 pport;
 464                 union fw_ofld_connection_leip {
 465                         struct fw_ofld_connection_le_ipv4 {
 466                                 __be32 pip;
 467                                 __be32 lip;
 468                                 __be64 r0;
 469                                 __be64 r1;
 470                                 __be64 r2;
 471                         } ipv4;
 472                         struct fw_ofld_connection_le_ipv6 {
 473                                 __be64 pip_hi;
 474                                 __be64 pip_lo;
 475                                 __be64 lip_hi;
 476                                 __be64 lip_lo;
 477                         } ipv6;
 478                 } u;
 479         } le;
 480         struct fw_ofld_connection_tcb {
 481                 __be32 t_state_to_astid;
 482                 __be16 cplrxdataack_cplpassacceptrpl;
 483                 __be16 rcv_adv;
 484                 __be32 rcv_nxt;
 485                 __be32 tx_max;
 486                 __be64 opt0;
 487                 __be32 opt2;
 488                 __be32 r1;
 489                 __be64 r2;
 490                 __be64 r3;
 491         } tcb;
 492 };
 493
 494 #define FW_OFLD_CONNECTION_WR_VERSION_S                31
 495 #define FW_OFLD_CONNECTION_WR_VERSION_M                0x1
 496 #define FW_OFLD_CONNECTION_WR_VERSION_V(x)     \
 497         ((x) << FW_OFLD_CONNECTION_WR_VERSION_S)
 498 #define FW_OFLD_CONNECTION_WR_VERSION_G(x)     \
 499         (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \
 500         FW_OFLD_CONNECTION_WR_VERSION_M)
 501 #define FW_OFLD_CONNECTION_WR_VERSION_F        \
 502         FW_OFLD_CONNECTION_WR_VERSION_V(1U)
 503
 504 #define FW_OFLD_CONNECTION_WR_CPL_S    30
 505 #define FW_OFLD_CONNECTION_WR_CPL_M    0x1
 506 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S)
 507 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \
 508         (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M)
 509 #define FW_OFLD_CONNECTION_WR_CPL_F    FW_OFLD_CONNECTION_WR_CPL_V(1U)
 510
 511 #define FW_OFLD_CONNECTION_WR_T_STATE_S                28
 512 #define FW_OFLD_CONNECTION_WR_T_STATE_M                0xf
 513 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x)     \
 514         ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S)
 515 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x)     \
 516         (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \
 517         FW_OFLD_CONNECTION_WR_T_STATE_M)
 518
 519 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S      24
 520 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M      0xf
 521 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x)   \
 522         ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S)
 523 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x)   \
 524         (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \
 525         FW_OFLD_CONNECTION_WR_RCV_SCALE_M)
 526
 527 #define FW_OFLD_CONNECTION_WR_ASTID_S          0
 528 #define FW_OFLD_CONNECTION_WR_ASTID_M          0xffffff
 529 #define FW_OFLD_CONNECTION_WR_ASTID_V(x)       \
 530         ((x) << FW_OFLD_CONNECTION_WR_ASTID_S)
 531 #define FW_OFLD_CONNECTION_WR_ASTID_G(x)       \
 532         (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M)
 533
 534 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S   15
 535 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M   0x1
 536 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x)        \
 537         ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S)
 538 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x)        \
 539         (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \
 540         FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M)
 541 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F   \
 542         FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U)
 543
 544 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S       14
 545 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M       0x1
 546 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x)    \
 547         ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S)
 548 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x)    \
 549         (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \
 550         FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M)
 551 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F       \
 552         FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U)
 553
 554 enum fw_flowc_mnem {
 555         FW_FLOWC_MNEM_PFNVFN,           /* PFN [15:8] VFN [7:0] */
 556         FW_FLOWC_MNEM_CH,
 557         FW_FLOWC_MNEM_PORT,
 558         FW_FLOWC_MNEM_IQID,
 559         FW_FLOWC_MNEM_SNDNXT,
 560         FW_FLOWC_MNEM_RCVNXT,
 561         FW_FLOWC_MNEM_SNDBUF,
 562         FW_FLOWC_MNEM_MSS,
 563 };
 564
 565 struct fw_flowc_mnemval {
 566         u8 mnemonic;
 567         u8 r4[3];
 568         __be32 val;
 569 };
 570
 571 struct fw_flowc_wr {
 572         __be32 op_to_nparams;
 573         __be32 flowid_len16;
 574         struct fw_flowc_mnemval mnemval[0];
 575 };
 576
 577 #define FW_FLOWC_WR_NPARAMS_S           0
 578 #define FW_FLOWC_WR_NPARAMS_V(x)        ((x) << FW_FLOWC_WR_NPARAMS_S)
 579
 580 struct fw_ofld_tx_data_wr {
 581         __be32 op_to_immdlen;
 582         __be32 flowid_len16;
 583         __be32 plen;
 584         __be32 tunnel_to_proxy;
 585 };
 586
 587 #define FW_OFLD_TX_DATA_WR_TUNNEL_S     19
 588 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x)  ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S)
 589
 590 #define FW_OFLD_TX_DATA_WR_SAVE_S       18
 591 #define FW_OFLD_TX_DATA_WR_SAVE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_SAVE_S)
 592
 593 #define FW_OFLD_TX_DATA_WR_FLUSH_S      17
 594 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x)   ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S)
 595 #define FW_OFLD_TX_DATA_WR_FLUSH_F      FW_OFLD_TX_DATA_WR_FLUSH_V(1U)
 596
 597 #define FW_OFLD_TX_DATA_WR_URGENT_S     16
 598 #define FW_OFLD_TX_DATA_WR_URGENT_V(x)  ((x) << FW_OFLD_TX_DATA_WR_URGENT_S)
 599
 600 #define FW_OFLD_TX_DATA_WR_MORE_S       15
 601 #define FW_OFLD_TX_DATA_WR_MORE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_MORE_S)
 602
 603 #define FW_OFLD_TX_DATA_WR_SHOVE_S      14
 604 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x)   ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S)
 605 #define FW_OFLD_TX_DATA_WR_SHOVE_F      FW_OFLD_TX_DATA_WR_SHOVE_V(1U)
 606
 607 #define FW_OFLD_TX_DATA_WR_ULPMODE_S    10
 608 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S)
 609
 610 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S         6
 611 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x)      \
 612         ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S)
 613
 614 struct fw_cmd_wr {
 615         __be32 op_dma;
 616         __be32 len16_pkd;
 617         __be64 cookie_daddr;
 618 };
 619
 620 #define FW_CMD_WR_DMA_S         17
 621 #define FW_CMD_WR_DMA_V(x)      ((x) << FW_CMD_WR_DMA_S)
 622
 623 struct fw_eth_tx_pkt_vm_wr {
 624         __be32 op_immdlen;
 625         __be32 equiq_to_len16;
 626         __be32 r3[2];
 627         u8 ethmacdst[6];
 628         u8 ethmacsrc[6];
 629         __be16 ethtype;
 630         __be16 vlantci;
 631 };
 632
 633 #define FW_CMD_MAX_TIMEOUT 10000
 634
 635 /*
 636  * If a host driver does a HELLO and discovers that there's already a MASTER
 637  * selected, we may have to wait for that MASTER to finish issuing RESET,
 638  * configuration and INITIALIZE commands.  Also, there's a possibility that
 639  * our own HELLO may get lost if it happens right as the MASTER is issuign a
 640  * RESET command, so we need to be willing to make a few retries of our HELLO.
 641  */
 642 #define FW_CMD_HELLO_TIMEOUT    (3 * FW_CMD_MAX_TIMEOUT)
 643 #define FW_CMD_HELLO_RETRIES    3
 644
 645
 646 enum fw_cmd_opcodes {
 647         FW_LDST_CMD                    = 0x01,
 648         FW_RESET_CMD                   = 0x03,
 649         FW_HELLO_CMD                   = 0x04,
 650         FW_BYE_CMD                     = 0x05,
 651         FW_INITIALIZE_CMD              = 0x06,
 652         FW_CAPS_CONFIG_CMD             = 0x07,
 653         FW_PARAMS_CMD                  = 0x08,
 654         FW_PFVF_CMD                    = 0x09,
 655         FW_IQ_CMD                      = 0x10,
 656         FW_EQ_MNGT_CMD                 = 0x11,
 657         FW_EQ_ETH_CMD                  = 0x12,
 658         FW_EQ_CTRL_CMD                 = 0x13,
 659         FW_EQ_OFLD_CMD                 = 0x21,
 660         FW_VI_CMD                      = 0x14,
 661         FW_VI_MAC_CMD                  = 0x15,
 662         FW_VI_RXMODE_CMD               = 0x16,
 663         FW_VI_ENABLE_CMD               = 0x17,
 664         FW_ACL_MAC_CMD                 = 0x18,
 665         FW_ACL_VLAN_CMD                = 0x19,
 666         FW_VI_STATS_CMD                = 0x1a,
 667         FW_PORT_CMD                    = 0x1b,
 668         FW_PORT_STATS_CMD              = 0x1c,
 669         FW_PORT_LB_STATS_CMD           = 0x1d,
 670         FW_PORT_TRACE_CMD              = 0x1e,
 671         FW_PORT_TRACE_MMAP_CMD         = 0x1f,
 672         FW_RSS_IND_TBL_CMD             = 0x20,
 673         FW_RSS_GLB_CONFIG_CMD          = 0x22,
 674         FW_RSS_VI_CONFIG_CMD           = 0x23,
 675         FW_CLIP_CMD                    = 0x28,
 676         FW_LASTC2E_CMD                 = 0x40,
 677         FW_ERROR_CMD                   = 0x80,
 678         FW_DEBUG_CMD                   = 0x81,
 679 };
 680
 681 enum fw_cmd_cap {
 682         FW_CMD_CAP_PF                  = 0x01,
 683         FW_CMD_CAP_DMAQ                = 0x02,
 684         FW_CMD_CAP_PORT                = 0x04,
 685         FW_CMD_CAP_PORTPROMISC         = 0x08,
 686         FW_CMD_CAP_PORTSTATS           = 0x10,
 687         FW_CMD_CAP_VF                  = 0x80,
 688 };
 689
 690 /*
 691  * Generic command header flit0
 692  */
 693 struct fw_cmd_hdr {
 694         __be32 hi;
 695         __be32 lo;
 696 };
 697
 698 #define FW_CMD_OP_S             24
 699 #define FW_CMD_OP_M             0xff
 700 #define FW_CMD_OP_V(x)          ((x) << FW_CMD_OP_S)
 701 #define FW_CMD_OP_G(x)          (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M)
 702
 703 #define FW_CMD_REQUEST_S        23
 704 #define FW_CMD_REQUEST_V(x)     ((x) << FW_CMD_REQUEST_S)
 705 #define FW_CMD_REQUEST_F        FW_CMD_REQUEST_V(1U)
 706
 707 #define FW_CMD_READ_S           22
 708 #define FW_CMD_READ_V(x)        ((x) << FW_CMD_READ_S)
 709 #define FW_CMD_READ_F           FW_CMD_READ_V(1U)
 710
 711 #define FW_CMD_WRITE_S          21
 712 #define FW_CMD_WRITE_V(x)       ((x) << FW_CMD_WRITE_S)
 713 #define FW_CMD_WRITE_F          FW_CMD_WRITE_V(1U)
 714
 715 #define FW_CMD_EXEC_S           20
 716 #define FW_CMD_EXEC_V(x)        ((x) << FW_CMD_EXEC_S)
 717 #define FW_CMD_EXEC_F           FW_CMD_EXEC_V(1U)
 718
 719 #define FW_CMD_RAMASK_S         20
 720 #define FW_CMD_RAMASK_V(x)      ((x) << FW_CMD_RAMASK_S)
 721
 722 #define FW_CMD_RETVAL_S         8
 723 #define FW_CMD_RETVAL_M         0xff
 724 #define FW_CMD_RETVAL_V(x)      ((x) << FW_CMD_RETVAL_S)
 725 #define FW_CMD_RETVAL_G(x)      (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M)
 726
 727 #define FW_CMD_LEN16_S          0
 728 #define FW_CMD_LEN16_V(x)       ((x) << FW_CMD_LEN16_S)
 729
 730 #define FW_LEN16(fw_struct)     FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
 731
 732 enum fw_ldst_addrspc {
 733         FW_LDST_ADDRSPC_FIRMWARE  = 0x0001,
 734         FW_LDST_ADDRSPC_SGE_EGRC  = 0x0008,
 735         FW_LDST_ADDRSPC_SGE_INGC  = 0x0009,
 736         FW_LDST_ADDRSPC_SGE_FLMC  = 0x000a,
 737         FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
 738         FW_LDST_ADDRSPC_TP_PIO    = 0x0010,
 739         FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
 740         FW_LDST_ADDRSPC_TP_MIB    = 0x0012,
 741         FW_LDST_ADDRSPC_MDIO      = 0x0018,
 742         FW_LDST_ADDRSPC_MPS       = 0x0020,
 743         FW_LDST_ADDRSPC_FUNC      = 0x0028,
 744         FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
 745 };
 746
 747 enum fw_ldst_mps_fid {
 748         FW_LDST_MPS_ATRB,
 749         FW_LDST_MPS_RPLC
 750 };
 751
 752 enum fw_ldst_func_access_ctl {
 753         FW_LDST_FUNC_ACC_CTL_VIID,
 754         FW_LDST_FUNC_ACC_CTL_FID
 755 };
 756
 757 enum fw_ldst_func_mod_index {
 758         FW_LDST_FUNC_MPS
 759 };
 760
 761 struct fw_ldst_cmd {
 762         __be32 op_to_addrspace;
 763 #define FW_LDST_CMD_ADDRSPACE_S         0
 764 #define FW_LDST_CMD_ADDRSPACE_V(x)      ((x) << FW_LDST_CMD_ADDRSPACE_S)
 765         __be32 cycles_to_len16;
 766         union fw_ldst {
 767                 struct fw_ldst_addrval {
 768                         __be32 addr;
 769                         __be32 val;
 770                 } addrval;
 771                 struct fw_ldst_idctxt {
 772                         __be32 physid;
 773                         __be32 msg_pkd;
 774                         __be32 ctxt_data7;
 775                         __be32 ctxt_data6;
 776                         __be32 ctxt_data5;
 777                         __be32 ctxt_data4;
 778                         __be32 ctxt_data3;
 779                         __be32 ctxt_data2;
 780                         __be32 ctxt_data1;
 781                         __be32 ctxt_data0;
 782                 } idctxt;
 783                 struct fw_ldst_mdio {
 784                         __be16 paddr_mmd;
 785                         __be16 raddr;
 786                         __be16 vctl;
 787                         __be16 rval;
 788                 } mdio;
 789                 struct fw_ldst_mps {
 790                         __be16 fid_ctl;
 791                         __be16 rplcpf_pkd;
 792                         __be32 rplc127_96;
 793                         __be32 rplc95_64;
 794                         __be32 rplc63_32;
 795                         __be32 rplc31_0;
 796                         __be32 atrb;
 797                         __be16 vlan[16];
 798                 } mps;
 799                 struct fw_ldst_func {
 800                         u8 access_ctl;
 801                         u8 mod_index;
 802                         __be16 ctl_id;
 803                         __be32 offset;
 804                         __be64 data0;
 805                         __be64 data1;
 806                 } func;
 807                 struct fw_ldst_pcie {
 808                         u8 ctrl_to_fn;
 809                         u8 bnum;
 810                         u8 r;
 811                         u8 ext_r;
 812                         u8 select_naccess;
 813                         u8 pcie_fn;
 814                         __be16 nset_pkd;
 815                         __be32 data[12];
 816                 } pcie;
 817         } u;
 818 };
 819
 820 #define FW_LDST_CMD_MSG_S       31
 821 #define FW_LDST_CMD_MSG_V(x)    ((x) << FW_LDST_CMD_MSG_S)
 822
 823 #define FW_LDST_CMD_PADDR_S     8
 824 #define FW_LDST_CMD_PADDR_V(x)  ((x) << FW_LDST_CMD_PADDR_S)
 825
 826 #define FW_LDST_CMD_MMD_S       0
 827 #define FW_LDST_CMD_MMD_V(x)    ((x) << FW_LDST_CMD_MMD_S)
 828
 829 #define FW_LDST_CMD_FID_S       15
 830 #define FW_LDST_CMD_FID_V(x)    ((x) << FW_LDST_CMD_FID_S)
 831
 832 #define FW_LDST_CMD_CTL_S       0
 833 #define FW_LDST_CMD_CTL_V(x)    ((x) << FW_LDST_CMD_CTL_S)
 834
 835 #define FW_LDST_CMD_RPLCPF_S    0
 836 #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S)
 837
 838 #define FW_LDST_CMD_LC_S        4
 839 #define FW_LDST_CMD_LC_V(x)     ((x) << FW_LDST_CMD_LC_S)
 840 #define FW_LDST_CMD_LC_F        FW_LDST_CMD_LC_V(1U)
 841
 842 #define FW_LDST_CMD_FN_S        0
 843 #define FW_LDST_CMD_FN_V(x)     ((x) << FW_LDST_CMD_FN_S)
 844
 845 #define FW_LDST_CMD_NACCESS_S           0
 846 #define FW_LDST_CMD_NACCESS_V(x)        ((x) << FW_LDST_CMD_NACCESS_S)
 847
 848 struct fw_reset_cmd {
 849         __be32 op_to_write;
 850         __be32 retval_len16;
 851         __be32 val;
 852         __be32 halt_pkd;
 853 };
 854
 855 #define FW_RESET_CMD_HALT_S     31
 856 #define FW_RESET_CMD_HALT_M     0x1
 857 #define FW_RESET_CMD_HALT_V(x)  ((x) << FW_RESET_CMD_HALT_S)
 858 #define FW_RESET_CMD_HALT_G(x)  \
 859         (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M)
 860 #define FW_RESET_CMD_HALT_F     FW_RESET_CMD_HALT_V(1U)
 861
 862 enum fw_hellow_cmd {
 863         fw_hello_cmd_stage_os           = 0x0
 864 };
 865
 866 struct fw_hello_cmd {
 867         __be32 op_to_write;
 868         __be32 retval_len16;
 869         __be32 err_to_clearinit;
 870         __be32 fwrev;
 871 };
 872
 873 #define FW_HELLO_CMD_ERR_S      31
 874 #define FW_HELLO_CMD_ERR_V(x)   ((x) << FW_HELLO_CMD_ERR_S)
 875 #define FW_HELLO_CMD_ERR_F      FW_HELLO_CMD_ERR_V(1U)
 876
 877 #define FW_HELLO_CMD_INIT_S     30
 878 #define FW_HELLO_CMD_INIT_V(x)  ((x) << FW_HELLO_CMD_INIT_S)
 879 #define FW_HELLO_CMD_INIT_F     FW_HELLO_CMD_INIT_V(1U)
 880
 881 #define FW_HELLO_CMD_MASTERDIS_S        29
 882 #define FW_HELLO_CMD_MASTERDIS_V(x)     ((x) << FW_HELLO_CMD_MASTERDIS_S)
 883
 884 #define FW_HELLO_CMD_MASTERFORCE_S      28
 885 #define FW_HELLO_CMD_MASTERFORCE_V(x)   ((x) << FW_HELLO_CMD_MASTERFORCE_S)
 886
 887 #define FW_HELLO_CMD_MBMASTER_S         24
 888 #define FW_HELLO_CMD_MBMASTER_M         0xfU
 889 #define FW_HELLO_CMD_MBMASTER_V(x)      ((x) << FW_HELLO_CMD_MBMASTER_S)
 890 #define FW_HELLO_CMD_MBMASTER_G(x)      \
 891         (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M)
 892
 893 #define FW_HELLO_CMD_MBASYNCNOTINT_S    23
 894 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S)
 895
 896 #define FW_HELLO_CMD_MBASYNCNOT_S       20
 897 #define FW_HELLO_CMD_MBASYNCNOT_V(x)    ((x) << FW_HELLO_CMD_MBASYNCNOT_S)
 898
 899 #define FW_HELLO_CMD_STAGE_S            17
 900 #define FW_HELLO_CMD_STAGE_V(x)         ((x) << FW_HELLO_CMD_STAGE_S)
 901
 902 #define FW_HELLO_CMD_CLEARINIT_S        16
 903 #define FW_HELLO_CMD_CLEARINIT_V(x)     ((x) << FW_HELLO_CMD_CLEARINIT_S)
 904 #define FW_HELLO_CMD_CLEARINIT_F        FW_HELLO_CMD_CLEARINIT_V(1U)
 905
 906 struct fw_bye_cmd {
 907         __be32 op_to_write;
 908         __be32 retval_len16;
 909         __be64 r3;
 910 };
 911
 912 struct fw_initialize_cmd {
 913         __be32 op_to_write;
 914         __be32 retval_len16;
 915         __be64 r3;
 916 };
 917
 918 enum fw_caps_config_hm {
 919         FW_CAPS_CONFIG_HM_PCIE          = 0x00000001,
 920         FW_CAPS_CONFIG_HM_PL            = 0x00000002,
 921         FW_CAPS_CONFIG_HM_SGE           = 0x00000004,
 922         FW_CAPS_CONFIG_HM_CIM           = 0x00000008,
 923         FW_CAPS_CONFIG_HM_ULPTX         = 0x00000010,
 924         FW_CAPS_CONFIG_HM_TP            = 0x00000020,
 925         FW_CAPS_CONFIG_HM_ULPRX         = 0x00000040,
 926         FW_CAPS_CONFIG_HM_PMRX          = 0x00000080,
 927         FW_CAPS_CONFIG_HM_PMTX          = 0x00000100,
 928         FW_CAPS_CONFIG_HM_MC            = 0x00000200,
 929         FW_CAPS_CONFIG_HM_LE            = 0x00000400,
 930         FW_CAPS_CONFIG_HM_MPS           = 0x00000800,
 931         FW_CAPS_CONFIG_HM_XGMAC         = 0x00001000,
 932         FW_CAPS_CONFIG_HM_CPLSWITCH     = 0x00002000,
 933         FW_CAPS_CONFIG_HM_T4DBG         = 0x00004000,
 934         FW_CAPS_CONFIG_HM_MI            = 0x00008000,
 935         FW_CAPS_CONFIG_HM_I2CM          = 0x00010000,
 936         FW_CAPS_CONFIG_HM_NCSI          = 0x00020000,
 937         FW_CAPS_CONFIG_HM_SMB           = 0x00040000,
 938         FW_CAPS_CONFIG_HM_MA            = 0x00080000,
 939         FW_CAPS_CONFIG_HM_EDRAM         = 0x00100000,
 940         FW_CAPS_CONFIG_HM_PMU           = 0x00200000,
 941         FW_CAPS_CONFIG_HM_UART          = 0x00400000,
 942         FW_CAPS_CONFIG_HM_SF            = 0x00800000,
 943 };
 944
 945 enum fw_caps_config_nbm {
 946         FW_CAPS_CONFIG_NBM_IPMI         = 0x00000001,
 947         FW_CAPS_CONFIG_NBM_NCSI         = 0x00000002,
 948 };
 949
 950 enum fw_caps_config_link {
 951         FW_CAPS_CONFIG_LINK_PPP         = 0x00000001,
 952         FW_CAPS_CONFIG_LINK_QFC         = 0x00000002,
 953         FW_CAPS_CONFIG_LINK_DCBX        = 0x00000004,
 954 };
 955
 956 enum fw_caps_config_switch {
 957         FW_CAPS_CONFIG_SWITCH_INGRESS   = 0x00000001,
 958         FW_CAPS_CONFIG_SWITCH_EGRESS    = 0x00000002,
 959 };
 960
 961 enum fw_caps_config_nic {
 962         FW_CAPS_CONFIG_NIC              = 0x00000001,
 963         FW_CAPS_CONFIG_NIC_VM           = 0x00000002,
 964 };
 965
 966 enum fw_caps_config_ofld {
 967         FW_CAPS_CONFIG_OFLD             = 0x00000001,
 968 };
 969
 970 enum fw_caps_config_rdma {
 971         FW_CAPS_CONFIG_RDMA_RDDP        = 0x00000001,
 972         FW_CAPS_CONFIG_RDMA_RDMAC       = 0x00000002,
 973 };
 974
 975 enum fw_caps_config_iscsi {
 976         FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
 977         FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
 978         FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
 979         FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
 980 };
 981
 982 enum fw_caps_config_fcoe {
 983         FW_CAPS_CONFIG_FCOE_INITIATOR   = 0x00000001,
 984         FW_CAPS_CONFIG_FCOE_TARGET      = 0x00000002,
 985         FW_CAPS_CONFIG_FCOE_CTRL_OFLD   = 0x00000004,
 986 };
 987
 988 enum fw_memtype_cf {
 989         FW_MEMTYPE_CF_EDC0              = 0x0,
 990         FW_MEMTYPE_CF_EDC1              = 0x1,
 991         FW_MEMTYPE_CF_EXTMEM            = 0x2,
 992         FW_MEMTYPE_CF_FLASH             = 0x4,
 993         FW_MEMTYPE_CF_INTERNAL          = 0x5,
 994 };
 995
 996 struct fw_caps_config_cmd {
 997         __be32 op_to_write;
 998         __be32 cfvalid_to_len16;
 999         __be32 r2;
1000         __be32 hwmbitmap;
1001         __be16 nbmcaps;
1002         __be16 linkcaps;
1003         __be16 switchcaps;
1004         __be16 r3;
1005         __be16 niccaps;
1006         __be16 ofldcaps;
1007         __be16 rdmacaps;
1008         __be16 r4;
1009         __be16 iscsicaps;
1010         __be16 fcoecaps;
1011         __be32 cfcsum;
1012         __be32 finiver;
1013         __be32 finicsum;
1014 };
1015
1016 #define FW_CAPS_CONFIG_CMD_CFVALID_S    27
1017 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S)
1018 #define FW_CAPS_CONFIG_CMD_CFVALID_F    FW_CAPS_CONFIG_CMD_CFVALID_V(1U)
1019
1020 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S         24
1021 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x)      \
1022         ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S)
1023
1024 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S      16
1025 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x)   \
1026         ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S)
1027
1028 /*
1029  * params command mnemonics
1030  */
1031 enum fw_params_mnem {
1032         FW_PARAMS_MNEM_DEV              = 1,    /* device params */
1033         FW_PARAMS_MNEM_PFVF             = 2,    /* function params */
1034         FW_PARAMS_MNEM_REG              = 3,    /* limited register access */
1035         FW_PARAMS_MNEM_DMAQ             = 4,    /* dma queue params */
1036         FW_PARAMS_MNEM_LAST
1037 };
1038
1039 /*
1040  * device parameters
1041  */
1042 enum fw_params_param_dev {
1043         FW_PARAMS_PARAM_DEV_CCLK        = 0x00, /* chip core clock in khz */
1044         FW_PARAMS_PARAM_DEV_PORTVEC     = 0x01, /* the port vector */
1045         FW_PARAMS_PARAM_DEV_NTID        = 0x02, /* reads the number of TIDs
1046                                                  * allocated by the device's
1047                                                  * Lookup Engine
1048                                                  */
1049         FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
1050         FW_PARAMS_PARAM_DEV_INTVER_NIC  = 0x04,
1051         FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
1052         FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
1053         FW_PARAMS_PARAM_DEV_INTVER_RI   = 0x07,
1054         FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
1055         FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
1056         FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
1057         FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
1058         FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
1059         FW_PARAMS_PARAM_DEV_CF = 0x0D,
1060         FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */
1061         FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */
1062         FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
1063 };
1064
1065 /*
1066  * physical and virtual function parameters
1067  */
1068 enum fw_params_param_pfvf {
1069         FW_PARAMS_PARAM_PFVF_RWXCAPS    = 0x00,
1070         FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
1071         FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
1072         FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
1073         FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
1074         FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
1075         FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
1076         FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
1077         FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
1078         FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
1079         FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
1080         FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
1081         FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
1082         FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
1083         FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
1084         FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
1085         FW_PARAMS_PARAM_PFVF_RQ_END     = 0x10,
1086         FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
1087         FW_PARAMS_PARAM_PFVF_PBL_END    = 0x12,
1088         FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
1089         FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
1090         FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
1091         FW_PARAMS_PARAM_PFVF_SQRQ_END   = 0x16,
1092         FW_PARAMS_PARAM_PFVF_CQ_START   = 0x17,
1093         FW_PARAMS_PARAM_PFVF_CQ_END     = 0x18,
1094         FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
1095         FW_PARAMS_PARAM_PFVF_VIID       = 0x24,
1096         FW_PARAMS_PARAM_PFVF_CPMASK     = 0x25,
1097         FW_PARAMS_PARAM_PFVF_OCQ_START  = 0x26,
1098         FW_PARAMS_PARAM_PFVF_OCQ_END    = 0x27,
1099         FW_PARAMS_PARAM_PFVF_CONM_MAP   = 0x28,
1100         FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
1101         FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
1102         FW_PARAMS_PARAM_PFVF_EQ_START   = 0x2B,
1103         FW_PARAMS_PARAM_PFVF_EQ_END     = 0x2C,
1104         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
1105         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
1106         FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
1107         FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31
1108 };
1109
1110 /*
1111  * dma queue parameters
1112  */
1113 enum fw_params_param_dmaq {
1114         FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
1115         FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
1116         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
1117         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
1118         FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
1119         FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
1120 };
1121
1122 #define FW_PARAMS_MNEM_S        24
1123 #define FW_PARAMS_MNEM_V(x)     ((x) << FW_PARAMS_MNEM_S)
1124
1125 #define FW_PARAMS_PARAM_X_S     16
1126 #define FW_PARAMS_PARAM_X_V(x)  ((x) << FW_PARAMS_PARAM_X_S)
1127
1128 #define FW_PARAMS_PARAM_Y_S     8
1129 #define FW_PARAMS_PARAM_Y_M     0xffU
1130 #define FW_PARAMS_PARAM_Y_V(x)  ((x) << FW_PARAMS_PARAM_Y_S)
1131 #define FW_PARAMS_PARAM_Y_G(x)  (((x) >> FW_PARAMS_PARAM_Y_S) &\
1132                 FW_PARAMS_PARAM_Y_M)
1133
1134 #define FW_PARAMS_PARAM_Z_S     0
1135 #define FW_PARAMS_PARAM_Z_M     0xffu
1136 #define FW_PARAMS_PARAM_Z_V(x)  ((x) << FW_PARAMS_PARAM_Z_S)
1137 #define FW_PARAMS_PARAM_Z_G(x)  (((x) >> FW_PARAMS_PARAM_Z_S) &\
1138                 FW_PARAMS_PARAM_Z_M)
1139
1140 #define FW_PARAMS_PARAM_XYZ_S           0
1141 #define FW_PARAMS_PARAM_XYZ_V(x)        ((x) << FW_PARAMS_PARAM_XYZ_S)
1142
1143 #define FW_PARAMS_PARAM_YZ_S            0
1144 #define FW_PARAMS_PARAM_YZ_V(x)         ((x) << FW_PARAMS_PARAM_YZ_S)
1145
1146 struct fw_params_cmd {
1147         __be32 op_to_vfn;
1148         __be32 retval_len16;
1149         struct fw_params_param {
1150                 __be32 mnem;
1151                 __be32 val;
1152         } param[7];
1153 };
1154
1155 #define FW_PARAMS_CMD_PFN_S     8
1156 #define FW_PARAMS_CMD_PFN_V(x)  ((x) << FW_PARAMS_CMD_PFN_S)
1157
1158 #define FW_PARAMS_CMD_VFN_S     0
1159 #define FW_PARAMS_CMD_VFN_V(x)  ((x) << FW_PARAMS_CMD_VFN_S)
1160
1161 struct fw_pfvf_cmd {
1162         __be32 op_to_vfn;
1163         __be32 retval_len16;
1164         __be32 niqflint_niq;
1165         __be32 type_to_neq;
1166         __be32 tc_to_nexactf;
1167         __be32 r_caps_to_nethctrl;
1168         __be16 nricq;
1169         __be16 nriqp;
1170         __be32 r4;
1171 };
1172
1173 #define FW_PFVF_CMD_PFN_S       8
1174 #define FW_PFVF_CMD_PFN_V(x)    ((x) << FW_PFVF_CMD_PFN_S)
1175
1176 #define FW_PFVF_CMD_VFN_S       0
1177 #define FW_PFVF_CMD_VFN_V(x)    ((x) << FW_PFVF_CMD_VFN_S)
1178
1179 #define FW_PFVF_CMD_NIQFLINT_S          20
1180 #define FW_PFVF_CMD_NIQFLINT_M          0xfff
1181 #define FW_PFVF_CMD_NIQFLINT_V(x)       ((x) << FW_PFVF_CMD_NIQFLINT_S)
1182 #define FW_PFVF_CMD_NIQFLINT_G(x)       \
1183         (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M)
1184
1185 #define FW_PFVF_CMD_NIQ_S       0
1186 #define FW_PFVF_CMD_NIQ_M       0xfffff
1187 #define FW_PFVF_CMD_NIQ_V(x)    ((x) << FW_PFVF_CMD_NIQ_S)
1188 #define FW_PFVF_CMD_NIQ_G(x)    \
1189         (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M)
1190
1191 #define FW_PFVF_CMD_TYPE_S      31
1192 #define FW_PFVF_CMD_TYPE_M      0x1
1193 #define FW_PFVF_CMD_TYPE_V(x)   ((x) << FW_PFVF_CMD_TYPE_S)
1194 #define FW_PFVF_CMD_TYPE_G(x)   \
1195         (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M)
1196 #define FW_PFVF_CMD_TYPE_F      FW_PFVF_CMD_TYPE_V(1U)
1197
1198 #define FW_PFVF_CMD_CMASK_S     24
1199 #define FW_PFVF_CMD_CMASK_M     0xf
1200 #define FW_PFVF_CMD_CMASK_V(x)  ((x) << FW_PFVF_CMD_CMASK_S)
1201 #define FW_PFVF_CMD_CMASK_G(x)  \
1202         (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M)
1203
1204 #define FW_PFVF_CMD_PMASK_S     20
1205 #define FW_PFVF_CMD_PMASK_M     0xf
1206 #define FW_PFVF_CMD_PMASK_V(x)  ((x) << FW_PFVF_CMD_PMASK_S)
1207 #define FW_PFVF_CMD_PMASK_G(x) \
1208         (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M)
1209
1210 #define FW_PFVF_CMD_NEQ_S       0
1211 #define FW_PFVF_CMD_NEQ_M       0xfffff
1212 #define FW_PFVF_CMD_NEQ_V(x)    ((x) << FW_PFVF_CMD_NEQ_S)
1213 #define FW_PFVF_CMD_NEQ_G(x)    \
1214         (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M)
1215
1216 #define FW_PFVF_CMD_TC_S        24
1217 #define FW_PFVF_CMD_TC_M        0xff
1218 #define FW_PFVF_CMD_TC_V(x)     ((x) << FW_PFVF_CMD_TC_S)
1219 #define FW_PFVF_CMD_TC_G(x)     (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M)
1220
1221 #define FW_PFVF_CMD_NVI_S       16
1222 #define FW_PFVF_CMD_NVI_M       0xff
1223 #define FW_PFVF_CMD_NVI_V(x)    ((x) << FW_PFVF_CMD_NVI_S)
1224 #define FW_PFVF_CMD_NVI_G(x)    (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M)
1225
1226 #define FW_PFVF_CMD_NEXACTF_S           0
1227 #define FW_PFVF_CMD_NEXACTF_M           0xffff
1228 #define FW_PFVF_CMD_NEXACTF_V(x)        ((x) << FW_PFVF_CMD_NEXACTF_S)
1229 #define FW_PFVF_CMD_NEXACTF_G(x)        \
1230         (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M)
1231
1232 #define FW_PFVF_CMD_R_CAPS_S    24
1233 #define FW_PFVF_CMD_R_CAPS_M    0xff
1234 #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S)
1235 #define FW_PFVF_CMD_R_CAPS_G(x) \
1236         (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M)
1237
1238 #define FW_PFVF_CMD_WX_CAPS_S           16
1239 #define FW_PFVF_CMD_WX_CAPS_M           0xff
1240 #define FW_PFVF_CMD_WX_CAPS_V(x)        ((x) << FW_PFVF_CMD_WX_CAPS_S)
1241 #define FW_PFVF_CMD_WX_CAPS_G(x)        \
1242         (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M)
1243
1244 #define FW_PFVF_CMD_NETHCTRL_S          0
1245 #define FW_PFVF_CMD_NETHCTRL_M          0xffff
1246 #define FW_PFVF_CMD_NETHCTRL_V(x)       ((x) << FW_PFVF_CMD_NETHCTRL_S)
1247 #define FW_PFVF_CMD_NETHCTRL_G(x)       \
1248         (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M)
1249
1250 enum fw_iq_type {
1251         FW_IQ_TYPE_FL_INT_CAP,
1252         FW_IQ_TYPE_NO_FL_INT_CAP
1253 };
1254
1255 struct fw_iq_cmd {
1256         __be32 op_to_vfn;
1257         __be32 alloc_to_len16;
1258         __be16 physiqid;
1259         __be16 iqid;
1260         __be16 fl0id;
1261         __be16 fl1id;
1262         __be32 type_to_iqandstindex;
1263         __be16 iqdroprss_to_iqesize;
1264         __be16 iqsize;
1265         __be64 iqaddr;
1266         __be32 iqns_to_fl0congen;
1267         __be16 fl0dcaen_to_fl0cidxfthresh;
1268         __be16 fl0size;
1269         __be64 fl0addr;
1270         __be32 fl1cngchmap_to_fl1congen;
1271         __be16 fl1dcaen_to_fl1cidxfthresh;
1272         __be16 fl1size;
1273         __be64 fl1addr;
1274 };
1275
1276 #define FW_IQ_CMD_PFN_S         8
1277 #define FW_IQ_CMD_PFN_V(x)      ((x) << FW_IQ_CMD_PFN_S)
1278
1279 #define FW_IQ_CMD_VFN_S         0
1280 #define FW_IQ_CMD_VFN_V(x)      ((x) << FW_IQ_CMD_VFN_S)
1281
1282 #define FW_IQ_CMD_ALLOC_S       31
1283 #define FW_IQ_CMD_ALLOC_V(x)    ((x) << FW_IQ_CMD_ALLOC_S)
1284 #define FW_IQ_CMD_ALLOC_F       FW_IQ_CMD_ALLOC_V(1U)
1285
1286 #define FW_IQ_CMD_FREE_S        30
1287 #define FW_IQ_CMD_FREE_V(x)     ((x) << FW_IQ_CMD_FREE_S)
1288 #define FW_IQ_CMD_FREE_F        FW_IQ_CMD_FREE_V(1U)
1289
1290 #define FW_IQ_CMD_MODIFY_S      29
1291 #define FW_IQ_CMD_MODIFY_V(x)   ((x) << FW_IQ_CMD_MODIFY_S)
1292 #define FW_IQ_CMD_MODIFY_F      FW_IQ_CMD_MODIFY_V(1U)
1293
1294 #define FW_IQ_CMD_IQSTART_S     28
1295 #define FW_IQ_CMD_IQSTART_V(x)  ((x) << FW_IQ_CMD_IQSTART_S)
1296 #define FW_IQ_CMD_IQSTART_F     FW_IQ_CMD_IQSTART_V(1U)
1297
1298 #define FW_IQ_CMD_IQSTOP_S      27
1299 #define FW_IQ_CMD_IQSTOP_V(x)   ((x) << FW_IQ_CMD_IQSTOP_S)
1300 #define FW_IQ_CMD_IQSTOP_F      FW_IQ_CMD_IQSTOP_V(1U)
1301
1302 #define FW_IQ_CMD_TYPE_S        29
1303 #define FW_IQ_CMD_TYPE_V(x)     ((x) << FW_IQ_CMD_TYPE_S)
1304
1305 #define FW_IQ_CMD_IQASYNCH_S    28
1306 #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S)
1307
1308 #define FW_IQ_CMD_VIID_S        16
1309 #define FW_IQ_CMD_VIID_V(x)     ((x) << FW_IQ_CMD_VIID_S)
1310
1311 #define FW_IQ_CMD_IQANDST_S     15
1312 #define FW_IQ_CMD_IQANDST_V(x)  ((x) << FW_IQ_CMD_IQANDST_S)
1313
1314 #define FW_IQ_CMD_IQANUS_S      14
1315 #define FW_IQ_CMD_IQANUS_V(x)   ((x) << FW_IQ_CMD_IQANUS_S)
1316
1317 #define FW_IQ_CMD_IQANUD_S      12
1318 #define FW_IQ_CMD_IQANUD_V(x)   ((x) << FW_IQ_CMD_IQANUD_S)
1319
1320 #define FW_IQ_CMD_IQANDSTINDEX_S        0
1321 #define FW_IQ_CMD_IQANDSTINDEX_V(x)     ((x) << FW_IQ_CMD_IQANDSTINDEX_S)
1322
1323 #define FW_IQ_CMD_IQDROPRSS_S           15
1324 #define FW_IQ_CMD_IQDROPRSS_V(x)        ((x) << FW_IQ_CMD_IQDROPRSS_S)
1325 #define FW_IQ_CMD_IQDROPRSS_F   FW_IQ_CMD_IQDROPRSS_V(1U)
1326
1327 #define FW_IQ_CMD_IQGTSMODE_S           14
1328 #define FW_IQ_CMD_IQGTSMODE_V(x)        ((x) << FW_IQ_CMD_IQGTSMODE_S)
1329 #define FW_IQ_CMD_IQGTSMODE_F           FW_IQ_CMD_IQGTSMODE_V(1U)
1330
1331 #define FW_IQ_CMD_IQPCIECH_S    12
1332 #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S)
1333
1334 #define FW_IQ_CMD_IQDCAEN_S     11
1335 #define FW_IQ_CMD_IQDCAEN_V(x)  ((x) << FW_IQ_CMD_IQDCAEN_S)
1336
1337 #define FW_IQ_CMD_IQDCACPU_S    6
1338 #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S)
1339
1340 #define FW_IQ_CMD_IQINTCNTTHRESH_S      4
1341 #define FW_IQ_CMD_IQINTCNTTHRESH_V(x)   ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S)
1342
1343 #define FW_IQ_CMD_IQO_S         3
1344 #define FW_IQ_CMD_IQO_V(x)      ((x) << FW_IQ_CMD_IQO_S)
1345 #define FW_IQ_CMD_IQO_F         FW_IQ_CMD_IQO_V(1U)
1346
1347 #define FW_IQ_CMD_IQCPRIO_S     2
1348 #define FW_IQ_CMD_IQCPRIO_V(x)  ((x) << FW_IQ_CMD_IQCPRIO_S)
1349
1350 #define FW_IQ_CMD_IQESIZE_S     0
1351 #define FW_IQ_CMD_IQESIZE_V(x)  ((x) << FW_IQ_CMD_IQESIZE_S)
1352
1353 #define FW_IQ_CMD_IQNS_S        31
1354 #define FW_IQ_CMD_IQNS_V(x)     ((x) << FW_IQ_CMD_IQNS_S)
1355
1356 #define FW_IQ_CMD_IQRO_S        30
1357 #define FW_IQ_CMD_IQRO_V(x)     ((x) << FW_IQ_CMD_IQRO_S)
1358
1359 #define FW_IQ_CMD_IQFLINTIQHSEN_S       28
1360 #define FW_IQ_CMD_IQFLINTIQHSEN_V(x)    ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S)
1361
1362 #define FW_IQ_CMD_IQFLINTCONGEN_S       27
1363 #define FW_IQ_CMD_IQFLINTCONGEN_V(x)    ((x) << FW_IQ_CMD_IQFLINTCONGEN_S)
1364
1365 #define FW_IQ_CMD_IQFLINTISCSIC_S       26
1366 #define FW_IQ_CMD_IQFLINTISCSIC_V(x)    ((x) << FW_IQ_CMD_IQFLINTISCSIC_S)
1367
1368 #define FW_IQ_CMD_FL0CNGCHMAP_S         20
1369 #define FW_IQ_CMD_FL0CNGCHMAP_V(x)      ((x) << FW_IQ_CMD_FL0CNGCHMAP_S)
1370
1371 #define FW_IQ_CMD_FL0CACHELOCK_S        15
1372 #define FW_IQ_CMD_FL0CACHELOCK_V(x)     ((x) << FW_IQ_CMD_FL0CACHELOCK_S)
1373
1374 #define FW_IQ_CMD_FL0DBP_S      14
1375 #define FW_IQ_CMD_FL0DBP_V(x)   ((x) << FW_IQ_CMD_FL0DBP_S)
1376
1377 #define FW_IQ_CMD_FL0DATANS_S           13
1378 #define FW_IQ_CMD_FL0DATANS_V(x)        ((x) << FW_IQ_CMD_FL0DATANS_S)
1379
1380 #define FW_IQ_CMD_FL0DATARO_S           12
1381 #define FW_IQ_CMD_FL0DATARO_V(x)        ((x) << FW_IQ_CMD_FL0DATARO_S)
1382 #define FW_IQ_CMD_FL0DATARO_F           FW_IQ_CMD_FL0DATARO_V(1U)
1383
1384 #define FW_IQ_CMD_FL0CONGCIF_S          11
1385 #define FW_IQ_CMD_FL0CONGCIF_V(x)       ((x) << FW_IQ_CMD_FL0CONGCIF_S)
1386
1387 #define FW_IQ_CMD_FL0ONCHIP_S           10
1388 #define FW_IQ_CMD_FL0ONCHIP_V(x)        ((x) << FW_IQ_CMD_FL0ONCHIP_S)
1389
1390 #define FW_IQ_CMD_FL0STATUSPGNS_S       9
1391 #define FW_IQ_CMD_FL0STATUSPGNS_V(x)    ((x) << FW_IQ_CMD_FL0STATUSPGNS_S)
1392
1393 #define FW_IQ_CMD_FL0STATUSPGRO_S       8
1394 #define FW_IQ_CMD_FL0STATUSPGRO_V(x)    ((x) << FW_IQ_CMD_FL0STATUSPGRO_S)
1395
1396 #define FW_IQ_CMD_FL0FETCHNS_S          7
1397 #define FW_IQ_CMD_FL0FETCHNS_V(x)       ((x) << FW_IQ_CMD_FL0FETCHNS_S)
1398
1399 #define FW_IQ_CMD_FL0FETCHRO_S          6
1400 #define FW_IQ_CMD_FL0FETCHRO_V(x)       ((x) << FW_IQ_CMD_FL0FETCHRO_S)
1401 #define FW_IQ_CMD_FL0FETCHRO_F          FW_IQ_CMD_FL0FETCHRO_V(1U)
1402
1403 #define FW_IQ_CMD_FL0HOSTFCMODE_S       4
1404 #define FW_IQ_CMD_FL0HOSTFCMODE_V(x)    ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S)
1405
1406 #define FW_IQ_CMD_FL0CPRIO_S    3
1407 #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S)
1408
1409 #define FW_IQ_CMD_FL0PADEN_S    2
1410 #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S)
1411 #define FW_IQ_CMD_FL0PADEN_F    FW_IQ_CMD_FL0PADEN_V(1U)
1412
1413 #define FW_IQ_CMD_FL0PACKEN_S           1
1414 #define FW_IQ_CMD_FL0PACKEN_V(x)        ((x) << FW_IQ_CMD_FL0PACKEN_S)
1415 #define FW_IQ_CMD_FL0PACKEN_F           FW_IQ_CMD_FL0PACKEN_V(1U)
1416
1417 #define FW_IQ_CMD_FL0CONGEN_S           0
1418 #define FW_IQ_CMD_FL0CONGEN_V(x)        ((x) << FW_IQ_CMD_FL0CONGEN_S)
1419 #define FW_IQ_CMD_FL0CONGEN_F           FW_IQ_CMD_FL0CONGEN_V(1U)
1420
1421 #define FW_IQ_CMD_FL0DCAEN_S    15
1422 #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S)
1423
1424 #define FW_IQ_CMD_FL0DCACPU_S           10
1425 #define FW_IQ_CMD_FL0DCACPU_V(x)        ((x) << FW_IQ_CMD_FL0DCACPU_S)
1426
1427 #define FW_IQ_CMD_FL0FBMIN_S    7
1428 #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S)
1429
1430 #define FW_IQ_CMD_FL0FBMAX_S    4
1431 #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S)
1432
1433 #define FW_IQ_CMD_FL0CIDXFTHRESHO_S     3
1434 #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x)  ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S)
1435 #define FW_IQ_CMD_FL0CIDXFTHRESHO_F     FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U)
1436
1437 #define FW_IQ_CMD_FL0CIDXFTHRESH_S      0
1438 #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x)   ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S)
1439
1440 #define FW_IQ_CMD_FL1CNGCHMAP_S         20
1441 #define FW_IQ_CMD_FL1CNGCHMAP_V(x)      ((x) << FW_IQ_CMD_FL1CNGCHMAP_S)
1442
1443 #define FW_IQ_CMD_FL1CACHELOCK_S        15
1444 #define FW_IQ_CMD_FL1CACHELOCK_V(x)     ((x) << FW_IQ_CMD_FL1CACHELOCK_S)
1445
1446 #define FW_IQ_CMD_FL1DBP_S      14
1447 #define FW_IQ_CMD_FL1DBP_V(x)   ((x) << FW_IQ_CMD_FL1DBP_S)
1448
1449 #define FW_IQ_CMD_FL1DATANS_S           13
1450 #define FW_IQ_CMD_FL1DATANS_V(x)        ((x) << FW_IQ_CMD_FL1DATANS_S)
1451
1452 #define FW_IQ_CMD_FL1DATARO_S           12
1453 #define FW_IQ_CMD_FL1DATARO_V(x)        ((x) << FW_IQ_CMD_FL1DATARO_S)
1454
1455 #define FW_IQ_CMD_FL1CONGCIF_S          11
1456 #define FW_IQ_CMD_FL1CONGCIF_V(x)       ((x) << FW_IQ_CMD_FL1CONGCIF_S)
1457
1458 #define FW_IQ_CMD_FL1ONCHIP_S           10
1459 #define FW_IQ_CMD_FL1ONCHIP_V(x)        ((x) << FW_IQ_CMD_FL1ONCHIP_S)
1460
1461 #define FW_IQ_CMD_FL1STATUSPGNS_S       9
1462 #define FW_IQ_CMD_FL1STATUSPGNS_V(x)    ((x) << FW_IQ_CMD_FL1STATUSPGNS_S)
1463
1464 #define FW_IQ_CMD_FL1STATUSPGRO_S       8
1465 #define FW_IQ_CMD_FL1STATUSPGRO_V(x)    ((x) << FW_IQ_CMD_FL1STATUSPGRO_S)
1466
1467 #define FW_IQ_CMD_FL1FETCHNS_S          7
1468 #define FW_IQ_CMD_FL1FETCHNS_V(x)       ((x) << FW_IQ_CMD_FL1FETCHNS_S)
1469
1470 #define FW_IQ_CMD_FL1FETCHRO_S          6
1471 #define FW_IQ_CMD_FL1FETCHRO_V(x)       ((x) << FW_IQ_CMD_FL1FETCHRO_S)
1472
1473 #define FW_IQ_CMD_FL1HOSTFCMODE_S       4
1474 #define FW_IQ_CMD_FL1HOSTFCMODE_V(x)    ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S)
1475
1476 #define FW_IQ_CMD_FL1CPRIO_S    3
1477 #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S)
1478
1479 #define FW_IQ_CMD_FL1PADEN_S    2
1480 #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S)
1481 #define FW_IQ_CMD_FL1PADEN_F    FW_IQ_CMD_FL1PADEN_V(1U)
1482
1483 #define FW_IQ_CMD_FL1PACKEN_S           1
1484 #define FW_IQ_CMD_FL1PACKEN_V(x)        ((x) << FW_IQ_CMD_FL1PACKEN_S)
1485 #define FW_IQ_CMD_FL1PACKEN_F   FW_IQ_CMD_FL1PACKEN_V(1U)
1486
1487 #define FW_IQ_CMD_FL1CONGEN_S           0
1488 #define FW_IQ_CMD_FL1CONGEN_V(x)        ((x) << FW_IQ_CMD_FL1CONGEN_S)
1489 #define FW_IQ_CMD_FL1CONGEN_F   FW_IQ_CMD_FL1CONGEN_V(1U)
1490
1491 #define FW_IQ_CMD_FL1DCAEN_S    15
1492 #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S)
1493
1494 #define FW_IQ_CMD_FL1DCACPU_S           10
1495 #define FW_IQ_CMD_FL1DCACPU_V(x)        ((x) << FW_IQ_CMD_FL1DCACPU_S)
1496
1497 #define FW_IQ_CMD_FL1FBMIN_S    7
1498 #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S)
1499
1500 #define FW_IQ_CMD_FL1FBMAX_S    4
1501 #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S)
1502
1503 #define FW_IQ_CMD_FL1CIDXFTHRESHO_S     3
1504 #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x)  ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S)
1505 #define FW_IQ_CMD_FL1CIDXFTHRESHO_F     FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U)
1506
1507 #define FW_IQ_CMD_FL1CIDXFTHRESH_S      0
1508 #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x)   ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S)
1509
1510 struct fw_eq_eth_cmd {
1511         __be32 op_to_vfn;
1512         __be32 alloc_to_len16;
1513         __be32 eqid_pkd;
1514         __be32 physeqid_pkd;
1515         __be32 fetchszm_to_iqid;
1516         __be32 dcaen_to_eqsize;
1517         __be64 eqaddr;
1518         __be32 viid_pkd;
1519         __be32 r8_lo;
1520         __be64 r9;
1521 };
1522
1523 #define FW_EQ_ETH_CMD_PFN_S     8
1524 #define FW_EQ_ETH_CMD_PFN_V(x)  ((x) << FW_EQ_ETH_CMD_PFN_S)
1525
1526 #define FW_EQ_ETH_CMD_VFN_S     0
1527 #define FW_EQ_ETH_CMD_VFN_V(x)  ((x) << FW_EQ_ETH_CMD_VFN_S)
1528
1529 #define FW_EQ_ETH_CMD_ALLOC_S           31
1530 #define FW_EQ_ETH_CMD_ALLOC_V(x)        ((x) << FW_EQ_ETH_CMD_ALLOC_S)
1531 #define FW_EQ_ETH_CMD_ALLOC_F   FW_EQ_ETH_CMD_ALLOC_V(1U)
1532
1533 #define FW_EQ_ETH_CMD_FREE_S    30
1534 #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S)
1535 #define FW_EQ_ETH_CMD_FREE_F    FW_EQ_ETH_CMD_FREE_V(1U)
1536
1537 #define FW_EQ_ETH_CMD_MODIFY_S          29
1538 #define FW_EQ_ETH_CMD_MODIFY_V(x)       ((x) << FW_EQ_ETH_CMD_MODIFY_S)
1539 #define FW_EQ_ETH_CMD_MODIFY_F  FW_EQ_ETH_CMD_MODIFY_V(1U)
1540
1541 #define FW_EQ_ETH_CMD_EQSTART_S         28
1542 #define FW_EQ_ETH_CMD_EQSTART_V(x)      ((x) << FW_EQ_ETH_CMD_EQSTART_S)
1543 #define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U)
1544
1545 #define FW_EQ_ETH_CMD_EQSTOP_S          27
1546 #define FW_EQ_ETH_CMD_EQSTOP_V(x)       ((x) << FW_EQ_ETH_CMD_EQSTOP_S)
1547 #define FW_EQ_ETH_CMD_EQSTOP_F  FW_EQ_ETH_CMD_EQSTOP_V(1U)
1548
1549 #define FW_EQ_ETH_CMD_EQID_S    0
1550 #define FW_EQ_ETH_CMD_EQID_M    0xfffff
1551 #define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S)
1552 #define FW_EQ_ETH_CMD_EQID_G(x) \
1553         (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M)
1554
1555 #define FW_EQ_ETH_CMD_PHYSEQID_S        0
1556 #define FW_EQ_ETH_CMD_PHYSEQID_M        0xfffff
1557 #define FW_EQ_ETH_CMD_PHYSEQID_V(x)     ((x) << FW_EQ_ETH_CMD_PHYSEQID_S)
1558 #define FW_EQ_ETH_CMD_PHYSEQID_G(x)     \
1559         (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M)
1560
1561 #define FW_EQ_ETH_CMD_FETCHSZM_S        26
1562 #define FW_EQ_ETH_CMD_FETCHSZM_V(x)     ((x) << FW_EQ_ETH_CMD_FETCHSZM_S)
1563 #define FW_EQ_ETH_CMD_FETCHSZM_F        FW_EQ_ETH_CMD_FETCHSZM_V(1U)
1564
1565 #define FW_EQ_ETH_CMD_STATUSPGNS_S      25
1566 #define FW_EQ_ETH_CMD_STATUSPGNS_V(x)   ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S)
1567
1568 #define FW_EQ_ETH_CMD_STATUSPGRO_S      24
1569 #define FW_EQ_ETH_CMD_STATUSPGRO_V(x)   ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S)
1570
1571 #define FW_EQ_ETH_CMD_FETCHNS_S         23
1572 #define FW_EQ_ETH_CMD_FETCHNS_V(x)      ((x) << FW_EQ_ETH_CMD_FETCHNS_S)
1573
1574 #define FW_EQ_ETH_CMD_FETCHRO_S         22
1575 #define FW_EQ_ETH_CMD_FETCHRO_V(x)      ((x) << FW_EQ_ETH_CMD_FETCHRO_S)
1576
1577 #define FW_EQ_ETH_CMD_HOSTFCMODE_S      20
1578 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x)   ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S)
1579
1580 #define FW_EQ_ETH_CMD_CPRIO_S           19
1581 #define FW_EQ_ETH_CMD_CPRIO_V(x)        ((x) << FW_EQ_ETH_CMD_CPRIO_S)
1582
1583 #define FW_EQ_ETH_CMD_ONCHIP_S          18
1584 #define FW_EQ_ETH_CMD_ONCHIP_V(x)       ((x) << FW_EQ_ETH_CMD_ONCHIP_S)
1585
1586 #define FW_EQ_ETH_CMD_PCIECHN_S         16
1587 #define FW_EQ_ETH_CMD_PCIECHN_V(x)      ((x) << FW_EQ_ETH_CMD_PCIECHN_S)
1588
1589 #define FW_EQ_ETH_CMD_IQID_S    0
1590 #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S)
1591
1592 #define FW_EQ_ETH_CMD_DCAEN_S           31
1593 #define FW_EQ_ETH_CMD_DCAEN_V(x)        ((x) << FW_EQ_ETH_CMD_DCAEN_S)
1594
1595 #define FW_EQ_ETH_CMD_DCACPU_S          26
1596 #define FW_EQ_ETH_CMD_DCACPU_V(x)       ((x) << FW_EQ_ETH_CMD_DCACPU_S)
1597
1598 #define FW_EQ_ETH_CMD_FBMIN_S           23
1599 #define FW_EQ_ETH_CMD_FBMIN_V(x)        ((x) << FW_EQ_ETH_CMD_FBMIN_S)
1600
1601 #define FW_EQ_ETH_CMD_FBMAX_S           20
1602 #define FW_EQ_ETH_CMD_FBMAX_V(x)        ((x) << FW_EQ_ETH_CMD_FBMAX_S)
1603
1604 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S    19
1605 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S)
1606
1607 #define FW_EQ_ETH_CMD_CIDXFTHRESH_S     16
1608 #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x)  ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S)
1609
1610 #define FW_EQ_ETH_CMD_EQSIZE_S          0
1611 #define FW_EQ_ETH_CMD_EQSIZE_V(x)       ((x) << FW_EQ_ETH_CMD_EQSIZE_S)
1612
1613 #define FW_EQ_ETH_CMD_AUTOEQUEQE_S      30
1614 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x)   ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S)
1615 #define FW_EQ_ETH_CMD_AUTOEQUEQE_F      FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U)
1616
1617 #define FW_EQ_ETH_CMD_VIID_S    16
1618 #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S)
1619
1620 struct fw_eq_ctrl_cmd {
1621         __be32 op_to_vfn;
1622         __be32 alloc_to_len16;
1623         __be32 cmpliqid_eqid;
1624         __be32 physeqid_pkd;
1625         __be32 fetchszm_to_iqid;
1626         __be32 dcaen_to_eqsize;
1627         __be64 eqaddr;
1628 };
1629
1630 #define FW_EQ_CTRL_CMD_PFN_S    8
1631 #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S)
1632
1633 #define FW_EQ_CTRL_CMD_VFN_S    0
1634 #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S)
1635
1636 #define FW_EQ_CTRL_CMD_ALLOC_S          31
1637 #define FW_EQ_CTRL_CMD_ALLOC_V(x)       ((x) << FW_EQ_CTRL_CMD_ALLOC_S)
1638 #define FW_EQ_CTRL_CMD_ALLOC_F          FW_EQ_CTRL_CMD_ALLOC_V(1U)
1639
1640 #define FW_EQ_CTRL_CMD_FREE_S           30
1641 #define FW_EQ_CTRL_CMD_FREE_V(x)        ((x) << FW_EQ_CTRL_CMD_FREE_S)
1642 #define FW_EQ_CTRL_CMD_FREE_F           FW_EQ_CTRL_CMD_FREE_V(1U)
1643
1644 #define FW_EQ_CTRL_CMD_MODIFY_S         29
1645 #define FW_EQ_CTRL_CMD_MODIFY_V(x)      ((x) << FW_EQ_CTRL_CMD_MODIFY_S)
1646 #define FW_EQ_CTRL_CMD_MODIFY_F         FW_EQ_CTRL_CMD_MODIFY_V(1U)
1647
1648 #define FW_EQ_CTRL_CMD_EQSTART_S        28
1649 #define FW_EQ_CTRL_CMD_EQSTART_V(x)     ((x) << FW_EQ_CTRL_CMD_EQSTART_S)
1650 #define FW_EQ_CTRL_CMD_EQSTART_F        FW_EQ_CTRL_CMD_EQSTART_V(1U)
1651
1652 #define FW_EQ_CTRL_CMD_EQSTOP_S         27
1653 #define FW_EQ_CTRL_CMD_EQSTOP_V(x)      ((x) << FW_EQ_CTRL_CMD_EQSTOP_S)
1654 #define FW_EQ_CTRL_CMD_EQSTOP_F         FW_EQ_CTRL_CMD_EQSTOP_V(1U)
1655
1656 #define FW_EQ_CTRL_CMD_CMPLIQID_S       20
1657 #define FW_EQ_CTRL_CMD_CMPLIQID_V(x)    ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S)
1658
1659 #define FW_EQ_CTRL_CMD_EQID_S           0
1660 #define FW_EQ_CTRL_CMD_EQID_M           0xfffff
1661 #define FW_EQ_CTRL_CMD_EQID_V(x)        ((x) << FW_EQ_CTRL_CMD_EQID_S)
1662 #define FW_EQ_CTRL_CMD_EQID_G(x)        \
1663         (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M)
1664
1665 #define FW_EQ_CTRL_CMD_PHYSEQID_S       0
1666 #define FW_EQ_CTRL_CMD_PHYSEQID_M       0xfffff
1667 #define FW_EQ_CTRL_CMD_PHYSEQID_G(x)    \
1668         (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M)
1669
1670 #define FW_EQ_CTRL_CMD_FETCHSZM_S       26
1671 #define FW_EQ_CTRL_CMD_FETCHSZM_V(x)    ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S)
1672 #define FW_EQ_CTRL_CMD_FETCHSZM_F       FW_EQ_CTRL_CMD_FETCHSZM_V(1U)
1673
1674 #define FW_EQ_CTRL_CMD_STATUSPGNS_S     25
1675 #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x)  ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S)
1676 #define FW_EQ_CTRL_CMD_STATUSPGNS_F     FW_EQ_CTRL_CMD_STATUSPGNS_V(1U)
1677
1678 #define FW_EQ_CTRL_CMD_STATUSPGRO_S     24
1679 #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x)  ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S)
1680 #define FW_EQ_CTRL_CMD_STATUSPGRO_F     FW_EQ_CTRL_CMD_STATUSPGRO_V(1U)
1681
1682 #define FW_EQ_CTRL_CMD_FETCHNS_S        23
1683 #define FW_EQ_CTRL_CMD_FETCHNS_V(x)     ((x) << FW_EQ_CTRL_CMD_FETCHNS_S)
1684 #define FW_EQ_CTRL_CMD_FETCHNS_F        FW_EQ_CTRL_CMD_FETCHNS_V(1U)
1685
1686 #define FW_EQ_CTRL_CMD_FETCHRO_S        22
1687 #define FW_EQ_CTRL_CMD_FETCHRO_V(x)     ((x) << FW_EQ_CTRL_CMD_FETCHRO_S)
1688 #define FW_EQ_CTRL_CMD_FETCHRO_F        FW_EQ_CTRL_CMD_FETCHRO_V(1U)
1689
1690 #define FW_EQ_CTRL_CMD_HOSTFCMODE_S     20
1691 #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x)  ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S)
1692
1693 #define FW_EQ_CTRL_CMD_CPRIO_S          19
1694 #define FW_EQ_CTRL_CMD_CPRIO_V(x)       ((x) << FW_EQ_CTRL_CMD_CPRIO_S)
1695
1696 #define FW_EQ_CTRL_CMD_ONCHIP_S         18
1697 #define FW_EQ_CTRL_CMD_ONCHIP_V(x)      ((x) << FW_EQ_CTRL_CMD_ONCHIP_S)
1698
1699 #define FW_EQ_CTRL_CMD_PCIECHN_S        16
1700 #define FW_EQ_CTRL_CMD_PCIECHN_V(x)     ((x) << FW_EQ_CTRL_CMD_PCIECHN_S)
1701
1702 #define FW_EQ_CTRL_CMD_IQID_S           0
1703 #define FW_EQ_CTRL_CMD_IQID_V(x)        ((x) << FW_EQ_CTRL_CMD_IQID_S)
1704
1705 #define FW_EQ_CTRL_CMD_DCAEN_S          31
1706 #define FW_EQ_CTRL_CMD_DCAEN_V(x)       ((x) << FW_EQ_CTRL_CMD_DCAEN_S)
1707
1708 #define FW_EQ_CTRL_CMD_DCACPU_S         26
1709 #define FW_EQ_CTRL_CMD_DCACPU_V(x)      ((x) << FW_EQ_CTRL_CMD_DCACPU_S)
1710
1711 #define FW_EQ_CTRL_CMD_FBMIN_S          23
1712 #define FW_EQ_CTRL_CMD_FBMIN_V(x)       ((x) << FW_EQ_CTRL_CMD_FBMIN_S)
1713
1714 #define FW_EQ_CTRL_CMD_FBMAX_S          20
1715 #define FW_EQ_CTRL_CMD_FBMAX_V(x)       ((x) << FW_EQ_CTRL_CMD_FBMAX_S)
1716
1717 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S           19
1718 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x)        \
1719         ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S)
1720
1721 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S    16
1722 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S)
1723
1724 #define FW_EQ_CTRL_CMD_EQSIZE_S         0
1725 #define FW_EQ_CTRL_CMD_EQSIZE_V(x)      ((x) << FW_EQ_CTRL_CMD_EQSIZE_S)
1726
1727 struct fw_eq_ofld_cmd {
1728         __be32 op_to_vfn;
1729         __be32 alloc_to_len16;
1730         __be32 eqid_pkd;
1731         __be32 physeqid_pkd;
1732         __be32 fetchszm_to_iqid;
1733         __be32 dcaen_to_eqsize;
1734         __be64 eqaddr;
1735 };
1736
1737 #define FW_EQ_OFLD_CMD_PFN_S    8
1738 #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S)
1739
1740 #define FW_EQ_OFLD_CMD_VFN_S    0
1741 #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S)
1742
1743 #define FW_EQ_OFLD_CMD_ALLOC_S          31
1744 #define FW_EQ_OFLD_CMD_ALLOC_V(x)       ((x) << FW_EQ_OFLD_CMD_ALLOC_S)
1745 #define FW_EQ_OFLD_CMD_ALLOC_F          FW_EQ_OFLD_CMD_ALLOC_V(1U)
1746
1747 #define FW_EQ_OFLD_CMD_FREE_S           30
1748 #define FW_EQ_OFLD_CMD_FREE_V(x)        ((x) << FW_EQ_OFLD_CMD_FREE_S)
1749 #define FW_EQ_OFLD_CMD_FREE_F           FW_EQ_OFLD_CMD_FREE_V(1U)
1750
1751 #define FW_EQ_OFLD_CMD_MODIFY_S         29
1752 #define FW_EQ_OFLD_CMD_MODIFY_V(x)      ((x) << FW_EQ_OFLD_CMD_MODIFY_S)
1753 #define FW_EQ_OFLD_CMD_MODIFY_F         FW_EQ_OFLD_CMD_MODIFY_V(1U)
1754
1755 #define FW_EQ_OFLD_CMD_EQSTART_S        28
1756 #define FW_EQ_OFLD_CMD_EQSTART_V(x)     ((x) << FW_EQ_OFLD_CMD_EQSTART_S)
1757 #define FW_EQ_OFLD_CMD_EQSTART_F        FW_EQ_OFLD_CMD_EQSTART_V(1U)
1758
1759 #define FW_EQ_OFLD_CMD_EQSTOP_S         27
1760 #define FW_EQ_OFLD_CMD_EQSTOP_V(x)      ((x) << FW_EQ_OFLD_CMD_EQSTOP_S)
1761 #define FW_EQ_OFLD_CMD_EQSTOP_F         FW_EQ_OFLD_CMD_EQSTOP_V(1U)
1762
1763 #define FW_EQ_OFLD_CMD_EQID_S           0
1764 #define FW_EQ_OFLD_CMD_EQID_M           0xfffff
1765 #define FW_EQ_OFLD_CMD_EQID_V(x)        ((x) << FW_EQ_OFLD_CMD_EQID_S)
1766 #define FW_EQ_OFLD_CMD_EQID_G(x)        \
1767         (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M)
1768
1769 #define FW_EQ_OFLD_CMD_PHYSEQID_S       0
1770 #define FW_EQ_OFLD_CMD_PHYSEQID_M       0xfffff
1771 #define FW_EQ_OFLD_CMD_PHYSEQID_G(x)    \
1772         (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M)
1773
1774 #define FW_EQ_OFLD_CMD_FETCHSZM_S       26
1775 #define FW_EQ_OFLD_CMD_FETCHSZM_V(x)    ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S)
1776
1777 #define FW_EQ_OFLD_CMD_STATUSPGNS_S     25
1778 #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x)  ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S)
1779
1780 #define FW_EQ_OFLD_CMD_STATUSPGRO_S     24
1781 #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x)  ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S)
1782
1783 #define FW_EQ_OFLD_CMD_FETCHNS_S        23
1784 #define FW_EQ_OFLD_CMD_FETCHNS_V(x)     ((x) << FW_EQ_OFLD_CMD_FETCHNS_S)
1785
1786 #define FW_EQ_OFLD_CMD_FETCHRO_S        22
1787 #define FW_EQ_OFLD_CMD_FETCHRO_V(x)     ((x) << FW_EQ_OFLD_CMD_FETCHRO_S)
1788 #define FW_EQ_OFLD_CMD_FETCHRO_F        FW_EQ_OFLD_CMD_FETCHRO_V(1U)
1789
1790 #define FW_EQ_OFLD_CMD_HOSTFCMODE_S     20
1791 #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x)  ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S)
1792
1793 #define FW_EQ_OFLD_CMD_CPRIO_S          19
1794 #define FW_EQ_OFLD_CMD_CPRIO_V(x)       ((x) << FW_EQ_OFLD_CMD_CPRIO_S)
1795
1796 #define FW_EQ_OFLD_CMD_ONCHIP_S         18
1797 #define FW_EQ_OFLD_CMD_ONCHIP_V(x)      ((x) << FW_EQ_OFLD_CMD_ONCHIP_S)
1798
1799 #define FW_EQ_OFLD_CMD_PCIECHN_S        16
1800 #define FW_EQ_OFLD_CMD_PCIECHN_V(x)     ((x) << FW_EQ_OFLD_CMD_PCIECHN_S)
1801
1802 #define FW_EQ_OFLD_CMD_IQID_S           0
1803 #define FW_EQ_OFLD_CMD_IQID_V(x)        ((x) << FW_EQ_OFLD_CMD_IQID_S)
1804
1805 #define FW_EQ_OFLD_CMD_DCAEN_S          31
1806 #define FW_EQ_OFLD_CMD_DCAEN_V(x)       ((x) << FW_EQ_OFLD_CMD_DCAEN_S)
1807
1808 #define FW_EQ_OFLD_CMD_DCACPU_S         26
1809 #define FW_EQ_OFLD_CMD_DCACPU_V(x)      ((x) << FW_EQ_OFLD_CMD_DCACPU_S)
1810
1811 #define FW_EQ_OFLD_CMD_FBMIN_S          23
1812 #define FW_EQ_OFLD_CMD_FBMIN_V(x)       ((x) << FW_EQ_OFLD_CMD_FBMIN_S)
1813
1814 #define FW_EQ_OFLD_CMD_FBMAX_S          20
1815 #define FW_EQ_OFLD_CMD_FBMAX_V(x)       ((x) << FW_EQ_OFLD_CMD_FBMAX_S)
1816
1817 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S           19
1818 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x)        \
1819         ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S)
1820
1821 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S    16
1822 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S)
1823
1824 #define FW_EQ_OFLD_CMD_EQSIZE_S         0
1825 #define FW_EQ_OFLD_CMD_EQSIZE_V(x)      ((x) << FW_EQ_OFLD_CMD_EQSIZE_S)
1826
1827 /*
1828  * Macros for VIID parsing:
1829  * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
1830  */
1831
1832 #define FW_VIID_PFN_S           8
1833 #define FW_VIID_PFN_M           0x7
1834 #define FW_VIID_PFN_G(x)        (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M)
1835
1836 #define FW_VIID_VIVLD_S         7
1837 #define FW_VIID_VIVLD_M         0x1
1838 #define FW_VIID_VIVLD_G(x)      (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M)
1839
1840 #define FW_VIID_VIN_S           0
1841 #define FW_VIID_VIN_M           0x7F
1842 #define FW_VIID_VIN_G(x)        (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M)
1843
1844 struct fw_vi_cmd {
1845         __be32 op_to_vfn;
1846         __be32 alloc_to_len16;
1847         __be16 type_viid;
1848         u8 mac[6];
1849         u8 portid_pkd;
1850         u8 nmac;
1851         u8 nmac0[6];
1852         __be16 rsssize_pkd;
1853         u8 nmac1[6];
1854         __be16 idsiiq_pkd;
1855         u8 nmac2[6];
1856         __be16 idseiq_pkd;
1857         u8 nmac3[6];
1858         __be64 r9;
1859         __be64 r10;
1860 };
1861
1862 #define FW_VI_CMD_PFN_S         8
1863 #define FW_VI_CMD_PFN_V(x)      ((x) << FW_VI_CMD_PFN_S)
1864
1865 #define FW_VI_CMD_VFN_S         0
1866 #define FW_VI_CMD_VFN_V(x)      ((x) << FW_VI_CMD_VFN_S)
1867
1868 #define FW_VI_CMD_ALLOC_S       31
1869 #define FW_VI_CMD_ALLOC_V(x)    ((x) << FW_VI_CMD_ALLOC_S)
1870 #define FW_VI_CMD_ALLOC_F       FW_VI_CMD_ALLOC_V(1U)
1871
1872 #define FW_VI_CMD_FREE_S        30
1873 #define FW_VI_CMD_FREE_V(x)     ((x) << FW_VI_CMD_FREE_S)
1874 #define FW_VI_CMD_FREE_F        FW_VI_CMD_FREE_V(1U)
1875
1876 #define FW_VI_CMD_VIID_S        0
1877 #define FW_VI_CMD_VIID_M        0xfff
1878 #define FW_VI_CMD_VIID_V(x)     ((x) << FW_VI_CMD_VIID_S)
1879 #define FW_VI_CMD_VIID_G(x)     (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M)
1880
1881 #define FW_VI_CMD_PORTID_S      4
1882 #define FW_VI_CMD_PORTID_M      0xf
1883 #define FW_VI_CMD_PORTID_V(x)   ((x) << FW_VI_CMD_PORTID_S)
1884 #define FW_VI_CMD_PORTID_G(x)   \
1885         (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M)
1886
1887 #define FW_VI_CMD_RSSSIZE_S     0
1888 #define FW_VI_CMD_RSSSIZE_M     0x7ff
1889 #define FW_VI_CMD_RSSSIZE_G(x)  \
1890         (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M)
1891
1892 /* Special VI_MAC command index ids */
1893 #define FW_VI_MAC_ADD_MAC               0x3FF
1894 #define FW_VI_MAC_ADD_PERSIST_MAC       0x3FE
1895 #define FW_VI_MAC_MAC_BASED_FREE        0x3FD
1896 #define FW_CLS_TCAM_NUM_ENTRIES         336
1897
1898 enum fw_vi_mac_smac {
1899         FW_VI_MAC_MPS_TCAM_ENTRY,
1900         FW_VI_MAC_MPS_TCAM_ONLY,
1901         FW_VI_MAC_SMT_ONLY,
1902         FW_VI_MAC_SMT_AND_MPSTCAM
1903 };
1904
1905 enum fw_vi_mac_result {
1906         FW_VI_MAC_R_SUCCESS,
1907         FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
1908         FW_VI_MAC_R_SMAC_FAIL,
1909         FW_VI_MAC_R_F_ACL_CHECK
1910 };
1911
1912 struct fw_vi_mac_cmd {
1913         __be32 op_to_viid;
1914         __be32 freemacs_to_len16;
1915         union fw_vi_mac {
1916                 struct fw_vi_mac_exact {
1917                         __be16 valid_to_idx;
1918                         u8 macaddr[6];
1919                 } exact[7];
1920                 struct fw_vi_mac_hash {
1921                         __be64 hashvec;
1922                 } hash;
1923         } u;
1924 };
1925
1926 #define FW_VI_MAC_CMD_VIID_S    0
1927 #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S)
1928
1929 #define FW_VI_MAC_CMD_FREEMACS_S        31
1930 #define FW_VI_MAC_CMD_FREEMACS_V(x)     ((x) << FW_VI_MAC_CMD_FREEMACS_S)
1931
1932 #define FW_VI_MAC_CMD_HASHVECEN_S       23
1933 #define FW_VI_MAC_CMD_HASHVECEN_V(x)    ((x) << FW_VI_MAC_CMD_HASHVECEN_S)
1934 #define FW_VI_MAC_CMD_HASHVECEN_F       FW_VI_MAC_CMD_HASHVECEN_V(1U)
1935
1936 #define FW_VI_MAC_CMD_HASHUNIEN_S       22
1937 #define FW_VI_MAC_CMD_HASHUNIEN_V(x)    ((x) << FW_VI_MAC_CMD_HASHUNIEN_S)
1938
1939 #define FW_VI_MAC_CMD_VALID_S           15
1940 #define FW_VI_MAC_CMD_VALID_V(x)        ((x) << FW_VI_MAC_CMD_VALID_S)
1941 #define FW_VI_MAC_CMD_VALID_F   FW_VI_MAC_CMD_VALID_V(1U)
1942
1943 #define FW_VI_MAC_CMD_PRIO_S    12
1944 #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S)
1945
1946 #define FW_VI_MAC_CMD_SMAC_RESULT_S     10
1947 #define FW_VI_MAC_CMD_SMAC_RESULT_M     0x3
1948 #define FW_VI_MAC_CMD_SMAC_RESULT_V(x)  ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S)
1949 #define FW_VI_MAC_CMD_SMAC_RESULT_G(x)  \
1950         (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M)
1951
1952 #define FW_VI_MAC_CMD_IDX_S     0
1953 #define FW_VI_MAC_CMD_IDX_M     0x3ff
1954 #define FW_VI_MAC_CMD_IDX_V(x)  ((x) << FW_VI_MAC_CMD_IDX_S)
1955 #define FW_VI_MAC_CMD_IDX_G(x)  \
1956         (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M)
1957
1958 #define FW_RXMODE_MTU_NO_CHG    65535
1959
1960 struct fw_vi_rxmode_cmd {
1961         __be32 op_to_viid;
1962         __be32 retval_len16;
1963         __be32 mtu_to_vlanexen;
1964         __be32 r4_lo;
1965 };
1966
1967 #define FW_VI_RXMODE_CMD_VIID_S         0
1968 #define FW_VI_RXMODE_CMD_VIID_V(x)      ((x) << FW_VI_RXMODE_CMD_VIID_S)
1969
1970 #define FW_VI_RXMODE_CMD_MTU_S          16
1971 #define FW_VI_RXMODE_CMD_MTU_M          0xffff
1972 #define FW_VI_RXMODE_CMD_MTU_V(x)       ((x) << FW_VI_RXMODE_CMD_MTU_S)
1973
1974 #define FW_VI_RXMODE_CMD_PROMISCEN_S    14
1975 #define FW_VI_RXMODE_CMD_PROMISCEN_M    0x3
1976 #define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S)
1977
1978 #define FW_VI_RXMODE_CMD_ALLMULTIEN_S           12
1979 #define FW_VI_RXMODE_CMD_ALLMULTIEN_M           0x3
1980 #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x)        \
1981         ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S)
1982
1983 #define FW_VI_RXMODE_CMD_BROADCASTEN_S          10
1984 #define FW_VI_RXMODE_CMD_BROADCASTEN_M          0x3
1985 #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x)       \
1986         ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S)
1987
1988 #define FW_VI_RXMODE_CMD_VLANEXEN_S     8
1989 #define FW_VI_RXMODE_CMD_VLANEXEN_M     0x3
1990 #define FW_VI_RXMODE_CMD_VLANEXEN_V(x)  ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S)
1991
1992 struct fw_vi_enable_cmd {
1993         __be32 op_to_viid;
1994         __be32 ien_to_len16;
1995         __be16 blinkdur;
1996         __be16 r3;
1997         __be32 r4;
1998 };
1999
2000 #define FW_VI_ENABLE_CMD_VIID_S         0
2001 #define FW_VI_ENABLE_CMD_VIID_V(x)      ((x) << FW_VI_ENABLE_CMD_VIID_S)
2002
2003 #define FW_VI_ENABLE_CMD_IEN_S          31
2004 #define FW_VI_ENABLE_CMD_IEN_V(x)       ((x) << FW_VI_ENABLE_CMD_IEN_S)
2005
2006 #define FW_VI_ENABLE_CMD_EEN_S          30
2007 #define FW_VI_ENABLE_CMD_EEN_V(x)       ((x) << FW_VI_ENABLE_CMD_EEN_S)
2008
2009 #define FW_VI_ENABLE_CMD_LED_S          29
2010 #define FW_VI_ENABLE_CMD_LED_V(x)       ((x) << FW_VI_ENABLE_CMD_LED_S)
2011 #define FW_VI_ENABLE_CMD_LED_F  FW_VI_ENABLE_CMD_LED_V(1U)
2012
2013 #define FW_VI_ENABLE_CMD_DCB_INFO_S     28
2014 #define FW_VI_ENABLE_CMD_DCB_INFO_V(x)  ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S)
2015
2016 /* VI VF stats offset definitions */
2017 #define VI_VF_NUM_STATS 16
2018 enum fw_vi_stats_vf_index {
2019         FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
2020         FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
2021         FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
2022         FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
2023         FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
2024         FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
2025         FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
2026         FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
2027         FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
2028         FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
2029         FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
2030         FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
2031         FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
2032         FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
2033         FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
2034         FW_VI_VF_STAT_RX_ERR_FRAMES_IX
2035 };
2036
2037 /* VI PF stats offset definitions */
2038 #define VI_PF_NUM_STATS 17
2039 enum fw_vi_stats_pf_index {
2040         FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
2041         FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
2042         FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
2043         FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
2044         FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
2045         FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
2046         FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
2047         FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
2048         FW_VI_PF_STAT_RX_BYTES_IX,
2049         FW_VI_PF_STAT_RX_FRAMES_IX,
2050         FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
2051         FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
2052         FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
2053         FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
2054         FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
2055         FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
2056         FW_VI_PF_STAT_RX_ERR_FRAMES_IX
2057 };
2058
2059 struct fw_vi_stats_cmd {
2060         __be32 op_to_viid;
2061         __be32 retval_len16;
2062         union fw_vi_stats {
2063                 struct fw_vi_stats_ctl {
2064                         __be16 nstats_ix;
2065                         __be16 r6;
2066                         __be32 r7;
2067                         __be64 stat0;
2068                         __be64 stat1;
2069                         __be64 stat2;
2070                         __be64 stat3;
2071                         __be64 stat4;
2072                         __be64 stat5;
2073                 } ctl;
2074                 struct fw_vi_stats_pf {
2075                         __be64 tx_bcast_bytes;
2076                         __be64 tx_bcast_frames;
2077                         __be64 tx_mcast_bytes;
2078                         __be64 tx_mcast_frames;
2079                         __be64 tx_ucast_bytes;
2080                         __be64 tx_ucast_frames;
2081                         __be64 tx_offload_bytes;
2082                         __be64 tx_offload_frames;
2083                         __be64 rx_pf_bytes;
2084                         __be64 rx_pf_frames;
2085                         __be64 rx_bcast_bytes;
2086                         __be64 rx_bcast_frames;
2087                         __be64 rx_mcast_bytes;
2088                         __be64 rx_mcast_frames;
2089                         __be64 rx_ucast_bytes;
2090                         __be64 rx_ucast_frames;
2091                         __be64 rx_err_frames;
2092                 } pf;
2093                 struct fw_vi_stats_vf {
2094                         __be64 tx_bcast_bytes;
2095                         __be64 tx_bcast_frames;
2096                         __be64 tx_mcast_bytes;
2097                         __be64 tx_mcast_frames;
2098                         __be64 tx_ucast_bytes;
2099                         __be64 tx_ucast_frames;
2100                         __be64 tx_drop_frames;
2101                         __be64 tx_offload_bytes;
2102                         __be64 tx_offload_frames;
2103                         __be64 rx_bcast_bytes;
2104                         __be64 rx_bcast_frames;
2105                         __be64 rx_mcast_bytes;
2106                         __be64 rx_mcast_frames;
2107                         __be64 rx_ucast_bytes;
2108                         __be64 rx_ucast_frames;
2109                         __be64 rx_err_frames;
2110                 } vf;
2111         } u;
2112 };
2113
2114 #define FW_VI_STATS_CMD_VIID_S          0
2115 #define FW_VI_STATS_CMD_VIID_V(x)       ((x) << FW_VI_STATS_CMD_VIID_S)
2116
2117 #define FW_VI_STATS_CMD_NSTATS_S        12
2118 #define FW_VI_STATS_CMD_NSTATS_V(x)     ((x) << FW_VI_STATS_CMD_NSTATS_S)
2119
2120 #define FW_VI_STATS_CMD_IX_S    0
2121 #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S)
2122
2123 struct fw_acl_mac_cmd {
2124         __be32 op_to_vfn;
2125         __be32 en_to_len16;
2126         u8 nmac;
2127         u8 r3[7];
2128         __be16 r4;
2129         u8 macaddr0[6];
2130         __be16 r5;
2131         u8 macaddr1[6];
2132         __be16 r6;
2133         u8 macaddr2[6];
2134         __be16 r7;
2135         u8 macaddr3[6];
2136 };
2137
2138 #define FW_ACL_MAC_CMD_PFN_S    8
2139 #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S)
2140
2141 #define FW_ACL_MAC_CMD_VFN_S    0
2142 #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S)
2143
2144 #define FW_ACL_MAC_CMD_EN_S     31
2145 #define FW_ACL_MAC_CMD_EN_V(x)  ((x) << FW_ACL_MAC_CMD_EN_S)
2146
2147 struct fw_acl_vlan_cmd {
2148         __be32 op_to_vfn;
2149         __be32 en_to_len16;
2150         u8 nvlan;
2151         u8 dropnovlan_fm;
2152         u8 r3_lo[6];
2153         __be16 vlanid[16];
2154 };
2155
2156 #define FW_ACL_VLAN_CMD_PFN_S           8
2157 #define FW_ACL_VLAN_CMD_PFN_V(x)        ((x) << FW_ACL_VLAN_CMD_PFN_S)
2158
2159 #define FW_ACL_VLAN_CMD_VFN_S           0
2160 #define FW_ACL_VLAN_CMD_VFN_V(x)        ((x) << FW_ACL_VLAN_CMD_VFN_S)
2161
2162 #define FW_ACL_VLAN_CMD_EN_S    31
2163 #define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S)
2164
2165 #define FW_ACL_VLAN_CMD_DROPNOVLAN_S    7
2166 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S)
2167
2168 #define FW_ACL_VLAN_CMD_FM_S    6
2169 #define FW_ACL_VLAN_CMD_FM_V(x) ((x) << FW_ACL_VLAN_CMD_FM_S)
2170
2171 enum fw_port_cap {
2172         FW_PORT_CAP_SPEED_100M          = 0x0001,
2173         FW_PORT_CAP_SPEED_1G            = 0x0002,
2174         FW_PORT_CAP_SPEED_2_5G          = 0x0004,
2175         FW_PORT_CAP_SPEED_10G           = 0x0008,
2176         FW_PORT_CAP_SPEED_40G           = 0x0010,
2177         FW_PORT_CAP_SPEED_100G          = 0x0020,
2178         FW_PORT_CAP_FC_RX               = 0x0040,
2179         FW_PORT_CAP_FC_TX               = 0x0080,
2180         FW_PORT_CAP_ANEG                = 0x0100,
2181         FW_PORT_CAP_MDI_0               = 0x0200,
2182         FW_PORT_CAP_MDI_1               = 0x0400,
2183         FW_PORT_CAP_BEAN                = 0x0800,
2184         FW_PORT_CAP_PMA_LPBK            = 0x1000,
2185         FW_PORT_CAP_PCS_LPBK            = 0x2000,
2186         FW_PORT_CAP_PHYXS_LPBK          = 0x4000,
2187         FW_PORT_CAP_FAR_END_LPBK        = 0x8000,
2188 };
2189
2190 enum fw_port_mdi {
2191         FW_PORT_CAP_MDI_UNCHANGED,
2192         FW_PORT_CAP_MDI_AUTO,
2193         FW_PORT_CAP_MDI_F_STRAIGHT,
2194         FW_PORT_CAP_MDI_F_CROSSOVER
2195 };
2196
2197 #define FW_PORT_CAP_MDI_S 9
2198 #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S)
2199
2200 enum fw_port_action {
2201         FW_PORT_ACTION_L1_CFG           = 0x0001,
2202         FW_PORT_ACTION_L2_CFG           = 0x0002,
2203         FW_PORT_ACTION_GET_PORT_INFO    = 0x0003,
2204         FW_PORT_ACTION_L2_PPP_CFG       = 0x0004,
2205         FW_PORT_ACTION_L2_DCB_CFG       = 0x0005,
2206         FW_PORT_ACTION_DCB_READ_TRANS   = 0x0006,
2207         FW_PORT_ACTION_DCB_READ_RECV    = 0x0007,
2208         FW_PORT_ACTION_DCB_READ_DET     = 0x0008,
2209         FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
2210         FW_PORT_ACTION_L1_LOW_PWR_EN    = 0x0011,
2211         FW_PORT_ACTION_L2_WOL_MODE_EN   = 0x0012,
2212         FW_PORT_ACTION_LPBK_TO_NORMAL   = 0x0020,
2213         FW_PORT_ACTION_L1_LPBK          = 0x0021,
2214         FW_PORT_ACTION_L1_PMA_LPBK      = 0x0022,
2215         FW_PORT_ACTION_L1_PCS_LPBK      = 0x0023,
2216         FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
2217         FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
2218         FW_PORT_ACTION_PHY_RESET        = 0x0040,
2219         FW_PORT_ACTION_PMA_RESET        = 0x0041,
2220         FW_PORT_ACTION_PCS_RESET        = 0x0042,
2221         FW_PORT_ACTION_PHYXS_RESET      = 0x0043,
2222         FW_PORT_ACTION_DTEXS_REEST      = 0x0044,
2223         FW_PORT_ACTION_AN_RESET         = 0x0045
2224 };
2225
2226 enum fw_port_l2cfg_ctlbf {
2227         FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
2228         FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
2229         FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
2230         FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
2231         FW_PORT_L2_CTLBF_IVLAN  = 0x10,
2232         FW_PORT_L2_CTLBF_TXIPG  = 0x20
2233 };
2234
2235 enum fw_port_dcb_versions {
2236         FW_PORT_DCB_VER_UNKNOWN,
2237         FW_PORT_DCB_VER_CEE1D0,
2238         FW_PORT_DCB_VER_CEE1D01,
2239         FW_PORT_DCB_VER_IEEE,
2240         FW_PORT_DCB_VER_AUTO = 7
2241 };
2242
2243 enum fw_port_dcb_cfg {
2244         FW_PORT_DCB_CFG_PG      = 0x01,
2245         FW_PORT_DCB_CFG_PFC     = 0x02,
2246         FW_PORT_DCB_CFG_APPL    = 0x04
2247 };
2248
2249 enum fw_port_dcb_cfg_rc {
2250         FW_PORT_DCB_CFG_SUCCESS = 0x0,
2251         FW_PORT_DCB_CFG_ERROR   = 0x1
2252 };
2253
2254 enum fw_port_dcb_type {
2255         FW_PORT_DCB_TYPE_PGID           = 0x00,
2256         FW_PORT_DCB_TYPE_PGRATE         = 0x01,
2257         FW_PORT_DCB_TYPE_PRIORATE       = 0x02,
2258         FW_PORT_DCB_TYPE_PFC            = 0x03,
2259         FW_PORT_DCB_TYPE_APP_ID         = 0x04,
2260         FW_PORT_DCB_TYPE_CONTROL        = 0x05,
2261 };
2262
2263 enum fw_port_dcb_feature_state {
2264         FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
2265         FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
2266         FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
2267         FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
2268 };
2269
2270 struct fw_port_cmd {
2271         __be32 op_to_portid;
2272         __be32 action_to_len16;
2273         union fw_port {
2274                 struct fw_port_l1cfg {
2275                         __be32 rcap;
2276                         __be32 r;
2277                 } l1cfg;
2278                 struct fw_port_l2cfg {
2279                         __u8   ctlbf;
2280                         __u8   ovlan3_to_ivlan0;
2281                         __be16 ivlantype;
2282                         __be16 txipg_force_pinfo;
2283                         __be16 mtu;
2284                         __be16 ovlan0mask;
2285                         __be16 ovlan0type;
2286                         __be16 ovlan1mask;
2287                         __be16 ovlan1type;
2288                         __be16 ovlan2mask;
2289                         __be16 ovlan2type;
2290                         __be16 ovlan3mask;
2291                         __be16 ovlan3type;
2292                 } l2cfg;
2293                 struct fw_port_info {
2294                         __be32 lstatus_to_modtype;
2295                         __be16 pcap;
2296                         __be16 acap;
2297                         __be16 mtu;
2298                         __u8   cbllen;
2299                         __u8   auxlinfo;
2300                         __u8   dcbxdis_pkd;
2301                         __u8   r8_lo[3];
2302                         __be64 r9;
2303                 } info;
2304                 struct fw_port_diags {
2305                         __u8   diagop;
2306                         __u8   r[3];
2307                         __be32 diagval;
2308                 } diags;
2309                 union fw_port_dcb {
2310                         struct fw_port_dcb_pgid {
2311                                 __u8   type;
2312                                 __u8   apply_pkd;
2313                                 __u8   r10_lo[2];
2314                                 __be32 pgid;
2315                                 __be64 r11;
2316                         } pgid;
2317                         struct fw_port_dcb_pgrate {
2318                                 __u8   type;
2319                                 __u8   apply_pkd;
2320                                 __u8   r10_lo[5];
2321                                 __u8   num_tcs_supported;
2322                                 __u8   pgrate[8];
2323                                 __u8   tsa[8];
2324                         } pgrate;
2325                         struct fw_port_dcb_priorate {
2326                                 __u8   type;
2327                                 __u8   apply_pkd;
2328                                 __u8   r10_lo[6];
2329                                 __u8   strict_priorate[8];
2330                         } priorate;
2331                         struct fw_port_dcb_pfc {
2332                                 __u8   type;
2333                                 __u8   pfcen;
2334                                 __u8   r10[5];
2335                                 __u8   max_pfc_tcs;
2336                                 __be64 r11;
2337                         } pfc;
2338                         struct fw_port_app_priority {
2339                                 __u8   type;
2340                                 __u8   r10[2];
2341                                 __u8   idx;
2342                                 __u8   user_prio_map;
2343                                 __u8   sel_field;
2344                                 __be16 protocolid;
2345                                 __be64 r12;
2346                         } app_priority;
2347                         struct fw_port_dcb_control {
2348                                 __u8   type;
2349                                 __u8   all_syncd_pkd;
2350                                 __be16 dcb_version_to_app_state;
2351                                 __be32 r11;
2352                                 __be64 r12;
2353                         } control;
2354                 } dcb;
2355         } u;
2356 };
2357
2358 #define FW_PORT_CMD_READ_S      22
2359 #define FW_PORT_CMD_READ_V(x)   ((x) << FW_PORT_CMD_READ_S)
2360 #define FW_PORT_CMD_READ_F      FW_PORT_CMD_READ_V(1U)
2361
2362 #define FW_PORT_CMD_PORTID_S    0
2363 #define FW_PORT_CMD_PORTID_M    0xf
2364 #define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S)
2365 #define FW_PORT_CMD_PORTID_G(x) \
2366         (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M)
2367
2368 #define FW_PORT_CMD_ACTION_S    16
2369 #define FW_PORT_CMD_ACTION_M    0xffff
2370 #define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S)
2371 #define FW_PORT_CMD_ACTION_G(x) \
2372         (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M)
2373
2374 #define FW_PORT_CMD_OVLAN3_S    7
2375 #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S)
2376
2377 #define FW_PORT_CMD_OVLAN2_S    6
2378 #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S)
2379
2380 #define FW_PORT_CMD_OVLAN1_S    5
2381 #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S)
2382
2383 #define FW_PORT_CMD_OVLAN0_S    4
2384 #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S)
2385
2386 #define FW_PORT_CMD_IVLAN0_S    3
2387 #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S)
2388
2389 #define FW_PORT_CMD_TXIPG_S     3
2390 #define FW_PORT_CMD_TXIPG_V(x)  ((x) << FW_PORT_CMD_TXIPG_S)
2391
2392 #define FW_PORT_CMD_LSTATUS_S           31
2393 #define FW_PORT_CMD_LSTATUS_M           0x1
2394 #define FW_PORT_CMD_LSTATUS_V(x)        ((x) << FW_PORT_CMD_LSTATUS_S)
2395 #define FW_PORT_CMD_LSTATUS_G(x)        \
2396         (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M)
2397 #define FW_PORT_CMD_LSTATUS_F   FW_PORT_CMD_LSTATUS_V(1U)
2398
2399 #define FW_PORT_CMD_LSPEED_S    24
2400 #define FW_PORT_CMD_LSPEED_M    0x3f
2401 #define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S)
2402 #define FW_PORT_CMD_LSPEED_G(x) \
2403         (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M)
2404
2405 #define FW_PORT_CMD_TXPAUSE_S           23
2406 #define FW_PORT_CMD_TXPAUSE_V(x)        ((x) << FW_PORT_CMD_TXPAUSE_S)
2407 #define FW_PORT_CMD_TXPAUSE_F   FW_PORT_CMD_TXPAUSE_V(1U)
2408
2409 #define FW_PORT_CMD_RXPAUSE_S           22
2410 #define FW_PORT_CMD_RXPAUSE_V(x)        ((x) << FW_PORT_CMD_RXPAUSE_S)
2411 #define FW_PORT_CMD_RXPAUSE_F   FW_PORT_CMD_RXPAUSE_V(1U)
2412
2413 #define FW_PORT_CMD_MDIOCAP_S           21
2414 #define FW_PORT_CMD_MDIOCAP_V(x)        ((x) << FW_PORT_CMD_MDIOCAP_S)
2415 #define FW_PORT_CMD_MDIOCAP_F   FW_PORT_CMD_MDIOCAP_V(1U)
2416
2417 #define FW_PORT_CMD_MDIOADDR_S          16
2418 #define FW_PORT_CMD_MDIOADDR_M          0x1f
2419 #define FW_PORT_CMD_MDIOADDR_G(x)       \
2420         (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M)
2421
2422 #define FW_PORT_CMD_LPTXPAUSE_S         15
2423 #define FW_PORT_CMD_LPTXPAUSE_V(x)      ((x) << FW_PORT_CMD_LPTXPAUSE_S)
2424 #define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U)
2425
2426 #define FW_PORT_CMD_LPRXPAUSE_S         14
2427 #define FW_PORT_CMD_LPRXPAUSE_V(x)      ((x) << FW_PORT_CMD_LPRXPAUSE_S)
2428 #define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U)
2429
2430 #define FW_PORT_CMD_PTYPE_S     8
2431 #define FW_PORT_CMD_PTYPE_M     0x1f
2432 #define FW_PORT_CMD_PTYPE_G(x)  \
2433         (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M)
2434
2435 #define FW_PORT_CMD_MODTYPE_S           0
2436 #define FW_PORT_CMD_MODTYPE_M           0x1f
2437 #define FW_PORT_CMD_MODTYPE_V(x)        ((x) << FW_PORT_CMD_MODTYPE_S)
2438 #define FW_PORT_CMD_MODTYPE_G(x)        \
2439         (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M)
2440
2441 #define FW_PORT_CMD_DCBXDIS_S           7
2442 #define FW_PORT_CMD_DCBXDIS_V(x)        ((x) << FW_PORT_CMD_DCBXDIS_S)
2443 #define FW_PORT_CMD_DCBXDIS_F   FW_PORT_CMD_DCBXDIS_V(1U)
2444
2445 #define FW_PORT_CMD_APPLY_S     7
2446 #define FW_PORT_CMD_APPLY_V(x)  ((x) << FW_PORT_CMD_APPLY_S)
2447 #define FW_PORT_CMD_APPLY_F     FW_PORT_CMD_APPLY_V(1U)
2448
2449 #define FW_PORT_CMD_ALL_SYNCD_S         7
2450 #define FW_PORT_CMD_ALL_SYNCD_V(x)      ((x) << FW_PORT_CMD_ALL_SYNCD_S)
2451 #define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U)
2452
2453 #define FW_PORT_CMD_DCB_VERSION_S       12
2454 #define FW_PORT_CMD_DCB_VERSION_M       0x7
2455 #define FW_PORT_CMD_DCB_VERSION_G(x)    \
2456         (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M)
2457
2458 enum fw_port_type {
2459         FW_PORT_TYPE_FIBER_XFI,
2460         FW_PORT_TYPE_FIBER_XAUI,
2461         FW_PORT_TYPE_BT_SGMII,
2462         FW_PORT_TYPE_BT_XFI,
2463         FW_PORT_TYPE_BT_XAUI,
2464         FW_PORT_TYPE_KX4,
2465         FW_PORT_TYPE_CX4,
2466         FW_PORT_TYPE_KX,
2467         FW_PORT_TYPE_KR,
2468         FW_PORT_TYPE_SFP,
2469         FW_PORT_TYPE_BP_AP,
2470         FW_PORT_TYPE_BP4_AP,
2471         FW_PORT_TYPE_QSFP_10G,
2472         FW_PORT_TYPE_QSFP,
2473         FW_PORT_TYPE_BP40_BA,
2474
2475         FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M
2476 };
2477
2478 enum fw_port_module_type {
2479         FW_PORT_MOD_TYPE_NA,
2480         FW_PORT_MOD_TYPE_LR,
2481         FW_PORT_MOD_TYPE_SR,
2482         FW_PORT_MOD_TYPE_ER,
2483         FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
2484         FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
2485         FW_PORT_MOD_TYPE_LRM,
2486         FW_PORT_MOD_TYPE_ERROR          = FW_PORT_CMD_MODTYPE_M - 3,
2487         FW_PORT_MOD_TYPE_UNKNOWN        = FW_PORT_CMD_MODTYPE_M - 2,
2488         FW_PORT_MOD_TYPE_NOTSUPPORTED   = FW_PORT_CMD_MODTYPE_M - 1,
2489
2490         FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M
2491 };
2492
2493 enum fw_port_mod_sub_type {
2494         FW_PORT_MOD_SUB_TYPE_NA,
2495         FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
2496         FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
2497         FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
2498         FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
2499         FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
2500         FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
2501
2502         /* The following will never been in the VPD.  They are TWINAX cable
2503          * lengths decoded from SFP+ module i2c PROMs.  These should
2504          * almost certainly go somewhere else ...
2505          */
2506         FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
2507         FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
2508         FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
2509         FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
2510 };
2511
2512 /* port stats */
2513 #define FW_NUM_PORT_STATS 50
2514 #define FW_NUM_PORT_TX_STATS 23
2515 #define FW_NUM_PORT_RX_STATS 27
2516
2517 enum fw_port_stats_tx_index {
2518         FW_STAT_TX_PORT_BYTES_IX,
2519         FW_STAT_TX_PORT_FRAMES_IX,
2520         FW_STAT_TX_PORT_BCAST_IX,
2521         FW_STAT_TX_PORT_MCAST_IX,
2522         FW_STAT_TX_PORT_UCAST_IX,
2523         FW_STAT_TX_PORT_ERROR_IX,
2524         FW_STAT_TX_PORT_64B_IX,
2525         FW_STAT_TX_PORT_65B_127B_IX,
2526         FW_STAT_TX_PORT_128B_255B_IX,
2527         FW_STAT_TX_PORT_256B_511B_IX,
2528         FW_STAT_TX_PORT_512B_1023B_IX,
2529         FW_STAT_TX_PORT_1024B_1518B_IX,
2530         FW_STAT_TX_PORT_1519B_MAX_IX,
2531         FW_STAT_TX_PORT_DROP_IX,
2532         FW_STAT_TX_PORT_PAUSE_IX,
2533         FW_STAT_TX_PORT_PPP0_IX,
2534         FW_STAT_TX_PORT_PPP1_IX,
2535         FW_STAT_TX_PORT_PPP2_IX,
2536         FW_STAT_TX_PORT_PPP3_IX,
2537         FW_STAT_TX_PORT_PPP4_IX,
2538         FW_STAT_TX_PORT_PPP5_IX,
2539         FW_STAT_TX_PORT_PPP6_IX,
2540         FW_STAT_TX_PORT_PPP7_IX
2541 };
2542
2543 enum fw_port_stat_rx_index {
2544         FW_STAT_RX_PORT_BYTES_IX,
2545         FW_STAT_RX_PORT_FRAMES_IX,
2546         FW_STAT_RX_PORT_BCAST_IX,
2547         FW_STAT_RX_PORT_MCAST_IX,
2548         FW_STAT_RX_PORT_UCAST_IX,
2549         FW_STAT_RX_PORT_MTU_ERROR_IX,
2550         FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
2551         FW_STAT_RX_PORT_CRC_ERROR_IX,
2552         FW_STAT_RX_PORT_LEN_ERROR_IX,
2553         FW_STAT_RX_PORT_SYM_ERROR_IX,
2554         FW_STAT_RX_PORT_64B_IX,
2555         FW_STAT_RX_PORT_65B_127B_IX,
2556         FW_STAT_RX_PORT_128B_255B_IX,
2557         FW_STAT_RX_PORT_256B_511B_IX,
2558         FW_STAT_RX_PORT_512B_1023B_IX,
2559         FW_STAT_RX_PORT_1024B_1518B_IX,
2560         FW_STAT_RX_PORT_1519B_MAX_IX,
2561         FW_STAT_RX_PORT_PAUSE_IX,
2562         FW_STAT_RX_PORT_PPP0_IX,
2563         FW_STAT_RX_PORT_PPP1_IX,
2564         FW_STAT_RX_PORT_PPP2_IX,
2565         FW_STAT_RX_PORT_PPP3_IX,
2566         FW_STAT_RX_PORT_PPP4_IX,
2567         FW_STAT_RX_PORT_PPP5_IX,
2568         FW_STAT_RX_PORT_PPP6_IX,
2569         FW_STAT_RX_PORT_PPP7_IX,
2570         FW_STAT_RX_PORT_LESS_64B_IX
2571 };
2572
2573 struct fw_port_stats_cmd {
2574         __be32 op_to_portid;
2575         __be32 retval_len16;
2576         union fw_port_stats {
2577                 struct fw_port_stats_ctl {
2578                         u8 nstats_bg_bm;
2579                         u8 tx_ix;
2580                         __be16 r6;
2581                         __be32 r7;
2582                         __be64 stat0;
2583                         __be64 stat1;
2584                         __be64 stat2;
2585                         __be64 stat3;
2586                         __be64 stat4;
2587                         __be64 stat5;
2588                 } ctl;
2589                 struct fw_port_stats_all {
2590                         __be64 tx_bytes;
2591                         __be64 tx_frames;
2592                         __be64 tx_bcast;
2593                         __be64 tx_mcast;
2594                         __be64 tx_ucast;
2595                         __be64 tx_error;
2596                         __be64 tx_64b;
2597                         __be64 tx_65b_127b;
2598                         __be64 tx_128b_255b;
2599                         __be64 tx_256b_511b;
2600                         __be64 tx_512b_1023b;
2601                         __be64 tx_1024b_1518b;
2602                         __be64 tx_1519b_max;
2603                         __be64 tx_drop;
2604                         __be64 tx_pause;
2605                         __be64 tx_ppp0;
2606                         __be64 tx_ppp1;
2607                         __be64 tx_ppp2;
2608                         __be64 tx_ppp3;
2609                         __be64 tx_ppp4;
2610                         __be64 tx_ppp5;
2611                         __be64 tx_ppp6;
2612                         __be64 tx_ppp7;
2613                         __be64 rx_bytes;
2614                         __be64 rx_frames;
2615                         __be64 rx_bcast;
2616                         __be64 rx_mcast;
2617                         __be64 rx_ucast;
2618                         __be64 rx_mtu_error;
2619                         __be64 rx_mtu_crc_error;
2620                         __be64 rx_crc_error;
2621                         __be64 rx_len_error;
2622                         __be64 rx_sym_error;
2623                         __be64 rx_64b;
2624                         __be64 rx_65b_127b;
2625                         __be64 rx_128b_255b;
2626                         __be64 rx_256b_511b;
2627                         __be64 rx_512b_1023b;
2628                         __be64 rx_1024b_1518b;
2629                         __be64 rx_1519b_max;
2630                         __be64 rx_pause;
2631                         __be64 rx_ppp0;
2632                         __be64 rx_ppp1;
2633                         __be64 rx_ppp2;
2634                         __be64 rx_ppp3;
2635                         __be64 rx_ppp4;
2636                         __be64 rx_ppp5;
2637                         __be64 rx_ppp6;
2638                         __be64 rx_ppp7;
2639                         __be64 rx_less_64b;
2640                         __be64 rx_bg_drop;
2641                         __be64 rx_bg_trunc;
2642                 } all;
2643         } u;
2644 };
2645
2646 /* port loopback stats */
2647 #define FW_NUM_LB_STATS 16
2648 enum fw_port_lb_stats_index {
2649         FW_STAT_LB_PORT_BYTES_IX,
2650         FW_STAT_LB_PORT_FRAMES_IX,
2651         FW_STAT_LB_PORT_BCAST_IX,
2652         FW_STAT_LB_PORT_MCAST_IX,
2653         FW_STAT_LB_PORT_UCAST_IX,
2654         FW_STAT_LB_PORT_ERROR_IX,
2655         FW_STAT_LB_PORT_64B_IX,
2656         FW_STAT_LB_PORT_65B_127B_IX,
2657         FW_STAT_LB_PORT_128B_255B_IX,
2658         FW_STAT_LB_PORT_256B_511B_IX,
2659         FW_STAT_LB_PORT_512B_1023B_IX,
2660         FW_STAT_LB_PORT_1024B_1518B_IX,
2661         FW_STAT_LB_PORT_1519B_MAX_IX,
2662         FW_STAT_LB_PORT_DROP_FRAMES_IX
2663 };
2664
2665 struct fw_port_lb_stats_cmd {
2666         __be32 op_to_lbport;
2667         __be32 retval_len16;
2668         union fw_port_lb_stats {
2669                 struct fw_port_lb_stats_ctl {
2670                         u8 nstats_bg_bm;
2671                         u8 ix_pkd;
2672                         __be16 r6;
2673                         __be32 r7;
2674                         __be64 stat0;
2675                         __be64 stat1;
2676                         __be64 stat2;
2677                         __be64 stat3;
2678                         __be64 stat4;
2679                         __be64 stat5;
2680                 } ctl;
2681                 struct fw_port_lb_stats_all {
2682                         __be64 tx_bytes;
2683                         __be64 tx_frames;
2684                         __be64 tx_bcast;
2685                         __be64 tx_mcast;
2686                         __be64 tx_ucast;
2687                         __be64 tx_error;
2688                         __be64 tx_64b;
2689                         __be64 tx_65b_127b;
2690                         __be64 tx_128b_255b;
2691                         __be64 tx_256b_511b;
2692                         __be64 tx_512b_1023b;
2693                         __be64 tx_1024b_1518b;
2694                         __be64 tx_1519b_max;
2695                         __be64 rx_lb_drop;
2696                         __be64 rx_lb_trunc;
2697                 } all;
2698         } u;
2699 };
2700
2701 struct fw_rss_ind_tbl_cmd {
2702         __be32 op_to_viid;
2703         __be32 retval_len16;
2704         __be16 niqid;
2705         __be16 startidx;
2706         __be32 r3;
2707         __be32 iq0_to_iq2;
2708         __be32 iq3_to_iq5;
2709         __be32 iq6_to_iq8;
2710         __be32 iq9_to_iq11;
2711         __be32 iq12_to_iq14;
2712         __be32 iq15_to_iq17;
2713         __be32 iq18_to_iq20;
2714         __be32 iq21_to_iq23;
2715         __be32 iq24_to_iq26;
2716         __be32 iq27_to_iq29;
2717         __be32 iq30_iq31;
2718         __be32 r15_lo;
2719 };
2720
2721 #define FW_RSS_IND_TBL_CMD_VIID_S       0
2722 #define FW_RSS_IND_TBL_CMD_VIID_V(x)    ((x) << FW_RSS_IND_TBL_CMD_VIID_S)
2723
2724 #define FW_RSS_IND_TBL_CMD_IQ0_S        20
2725 #define FW_RSS_IND_TBL_CMD_IQ0_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ0_S)
2726
2727 #define FW_RSS_IND_TBL_CMD_IQ1_S        10
2728 #define FW_RSS_IND_TBL_CMD_IQ1_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ1_S)
2729
2730 #define FW_RSS_IND_TBL_CMD_IQ2_S        0
2731 #define FW_RSS_IND_TBL_CMD_IQ2_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ2_S)
2732
2733 struct fw_rss_glb_config_cmd {
2734         __be32 op_to_write;
2735         __be32 retval_len16;
2736         union fw_rss_glb_config {
2737                 struct fw_rss_glb_config_manual {
2738                         __be32 mode_pkd;
2739                         __be32 r3;
2740                         __be64 r4;
2741                         __be64 r5;
2742                 } manual;
2743                 struct fw_rss_glb_config_basicvirtual {
2744                         __be32 mode_pkd;
2745                         __be32 synmapen_to_hashtoeplitz;
2746                         __be64 r8;
2747                         __be64 r9;
2748                 } basicvirtual;
2749         } u;
2750 };
2751
2752 #define FW_RSS_GLB_CONFIG_CMD_MODE_S    28
2753 #define FW_RSS_GLB_CONFIG_CMD_MODE_M    0xf
2754 #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S)
2755 #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \
2756         (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M)
2757
2758 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL       0
2759 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
2760
2761 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S        8
2762 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x)     \
2763         ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S)
2764 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F        \
2765         FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U)
2766
2767 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S           7
2768 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x)        \
2769         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S)
2770 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F   \
2771         FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U)
2772
2773 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S           6
2774 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x)        \
2775         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S)
2776 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F   \
2777         FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U)
2778
2779 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S           5
2780 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x)        \
2781         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S)
2782 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F   \
2783         FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U)
2784
2785 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S           4
2786 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x)        \
2787         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S)
2788 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F   \
2789         FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U)
2790
2791 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S        3
2792 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x)     \
2793         ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S)
2794 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F        \
2795         FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U)
2796
2797 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S        2
2798 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x)     \
2799         ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S)
2800 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F        \
2801         FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U)
2802
2803 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S       1
2804 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x)    \
2805         ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S)
2806 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F       \
2807         FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U)
2808
2809 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S    0
2810 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \
2811         ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S)
2812 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F    \
2813         FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U)
2814
2815 struct fw_rss_vi_config_cmd {
2816         __be32 op_to_viid;
2817 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
2818         __be32 retval_len16;
2819         union fw_rss_vi_config {
2820                 struct fw_rss_vi_config_manual {
2821                         __be64 r3;
2822                         __be64 r4;
2823                         __be64 r5;
2824                 } manual;
2825                 struct fw_rss_vi_config_basicvirtual {
2826                         __be32 r6;
2827                         __be32 defaultq_to_udpen;
2828                         __be64 r9;
2829                         __be64 r10;
2830                 } basicvirtual;
2831         } u;
2832 };
2833
2834 #define FW_RSS_VI_CONFIG_CMD_VIID_S     0
2835 #define FW_RSS_VI_CONFIG_CMD_VIID_V(x)  ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S)
2836
2837 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S         16
2838 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M         0x3ff
2839 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x)      \
2840         ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S)
2841 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x)      \
2842         (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \
2843          FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M)
2844
2845 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S     4
2846 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x)  \
2847         ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S)
2848 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F     \
2849         FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U)
2850
2851 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S      3
2852 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x)   \
2853         ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S)
2854 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F      \
2855         FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U)
2856
2857 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S     2
2858 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x)  \
2859         ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S)
2860 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F     \
2861         FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U)
2862
2863 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S      1
2864 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x)   \
2865         ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S)
2866 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F      \
2867         FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U)
2868
2869 #define FW_RSS_VI_CONFIG_CMD_UDPEN_S    0
2870 #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S)
2871 #define FW_RSS_VI_CONFIG_CMD_UDPEN_F    FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U)
2872
2873 struct fw_clip_cmd {
2874         __be32 op_to_write;
2875         __be32 alloc_to_len16;
2876         __be64 ip_hi;
2877         __be64 ip_lo;
2878         __be32 r4[2];
2879 };
2880
2881 #define FW_CLIP_CMD_ALLOC_S     31
2882 #define FW_CLIP_CMD_ALLOC_V(x)  ((x) << FW_CLIP_CMD_ALLOC_S)
2883 #define FW_CLIP_CMD_ALLOC_F     FW_CLIP_CMD_ALLOC_V(1U)
2884
2885 #define FW_CLIP_CMD_FREE_S      30
2886 #define FW_CLIP_CMD_FREE_V(x)   ((x) << FW_CLIP_CMD_FREE_S)
2887 #define FW_CLIP_CMD_FREE_F      FW_CLIP_CMD_FREE_V(1U)
2888
2889 enum fw_error_type {
2890         FW_ERROR_TYPE_EXCEPTION         = 0x0,
2891         FW_ERROR_TYPE_HWMODULE          = 0x1,
2892         FW_ERROR_TYPE_WR                = 0x2,
2893         FW_ERROR_TYPE_ACL               = 0x3,
2894 };
2895
2896 struct fw_error_cmd {
2897         __be32 op_to_type;
2898         __be32 len16_pkd;
2899         union fw_error {
2900                 struct fw_error_exception {
2901                         __be32 info[6];
2902                 } exception;
2903                 struct fw_error_hwmodule {
2904                         __be32 regaddr;
2905                         __be32 regval;
2906                 } hwmodule;
2907                 struct fw_error_wr {
2908                         __be16 cidx;
2909                         __be16 pfn_vfn;
2910                         __be32 eqid;
2911                         u8 wrhdr[16];
2912                 } wr;
2913                 struct fw_error_acl {
2914                         __be16 cidx;
2915                         __be16 pfn_vfn;
2916                         __be32 eqid;
2917                         __be16 mv_pkd;
2918                         u8 val[6];
2919                         __be64 r4;
2920                 } acl;
2921         } u;
2922 };
2923
2924 struct fw_debug_cmd {
2925         __be32 op_type;
2926         __be32 len16_pkd;
2927         union fw_debug {
2928                 struct fw_debug_assert {
2929                         __be32 fcid;
2930                         __be32 line;
2931                         __be32 x;
2932                         __be32 y;
2933                         u8 filename_0_7[8];
2934                         u8 filename_8_15[8];
2935                         __be64 r3;
2936                 } assert;
2937                 struct fw_debug_prt {
2938                         __be16 dprtstridx;
2939                         __be16 r3[3];
2940                         __be32 dprtstrparam0;
2941                         __be32 dprtstrparam1;
2942                         __be32 dprtstrparam2;
2943                         __be32 dprtstrparam3;
2944                 } prt;
2945         } u;
2946 };
2947
2948 #define FW_DEBUG_CMD_TYPE_S     0
2949 #define FW_DEBUG_CMD_TYPE_M     0xff
2950 #define FW_DEBUG_CMD_TYPE_G(x)  \
2951         (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M)
2952
2953 #define PCIE_FW_ERR_S           31
2954 #define PCIE_FW_ERR_V(x)        ((x) << PCIE_FW_ERR_S)
2955 #define PCIE_FW_ERR_F           PCIE_FW_ERR_V(1U)
2956
2957 #define PCIE_FW_INIT_S          30
2958 #define PCIE_FW_INIT_V(x)       ((x) << PCIE_FW_INIT_S)
2959 #define PCIE_FW_INIT_F          PCIE_FW_INIT_V(1U)
2960
2961 #define PCIE_FW_HALT_S          29
2962 #define PCIE_FW_HALT_V(x)       ((x) << PCIE_FW_HALT_S)
2963 #define PCIE_FW_HALT_F          PCIE_FW_HALT_V(1U)
2964
2965 #define PCIE_FW_EVAL_S          24
2966 #define PCIE_FW_EVAL_M          0x7
2967 #define PCIE_FW_EVAL_G(x)       (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M)
2968
2969 #define PCIE_FW_MASTER_VLD_S    15
2970 #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S)
2971 #define PCIE_FW_MASTER_VLD_F    PCIE_FW_MASTER_VLD_V(1U)
2972
2973 #define PCIE_FW_MASTER_S        12
2974 #define PCIE_FW_MASTER_M        0x7
2975 #define PCIE_FW_MASTER_V(x)     ((x) << PCIE_FW_MASTER_S)
2976 #define PCIE_FW_MASTER_G(x)     (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M)
2977
2978 struct fw_hdr {
2979         u8 ver;
2980         u8 chip;                        /* terminator chip type */
2981         __be16  len512;                 /* bin length in units of 512-bytes */
2982         __be32  fw_ver;                 /* firmware version */
2983         __be32  tp_microcode_ver;
2984         u8 intfver_nic;
2985         u8 intfver_vnic;
2986         u8 intfver_ofld;
2987         u8 intfver_ri;
2988         u8 intfver_iscsipdu;
2989         u8 intfver_iscsi;
2990         u8 intfver_fcoepdu;
2991         u8 intfver_fcoe;
2992         __u32   reserved2;
2993         __u32   reserved3;
2994         __u32   reserved4;
2995         __be32  flags;
2996         __be32  reserved6[23];
2997 };
2998
2999 enum fw_hdr_chip {
3000         FW_HDR_CHIP_T4,
3001         FW_HDR_CHIP_T5
3002 };
3003
3004 #define FW_HDR_FW_VER_MAJOR_S   24
3005 #define FW_HDR_FW_VER_MAJOR_M   0xff
3006 #define FW_HDR_FW_VER_MAJOR_G(x) \
3007         (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M)
3008
3009 #define FW_HDR_FW_VER_MINOR_S   16
3010 #define FW_HDR_FW_VER_MINOR_M   0xff
3011 #define FW_HDR_FW_VER_MINOR_G(x) \
3012         (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M)
3013
3014 #define FW_HDR_FW_VER_MICRO_S   8
3015 #define FW_HDR_FW_VER_MICRO_M   0xff
3016 #define FW_HDR_FW_VER_MICRO_G(x) \
3017         (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M)
3018
3019 #define FW_HDR_FW_VER_BUILD_S   0
3020 #define FW_HDR_FW_VER_BUILD_M   0xff
3021 #define FW_HDR_FW_VER_BUILD_G(x) \
3022         (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M)
3023
3024 enum fw_hdr_intfver {
3025         FW_HDR_INTFVER_NIC      = 0x00,
3026         FW_HDR_INTFVER_VNIC     = 0x00,
3027         FW_HDR_INTFVER_OFLD     = 0x00,
3028         FW_HDR_INTFVER_RI       = 0x00,
3029         FW_HDR_INTFVER_ISCSIPDU = 0x00,
3030         FW_HDR_INTFVER_ISCSI    = 0x00,
3031         FW_HDR_INTFVER_FCOEPDU  = 0x00,
3032         FW_HDR_INTFVER_FCOE     = 0x00,
3033 };
3034
3035 enum fw_hdr_flags {
3036         FW_HDR_FLAGS_RESET_HALT = 0x00000001,
3037 };
3038
3039 #endif /* _T4FW_INTERFACE_H_ */