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Merge tag 'for-linus-4.15-rc3-tag' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / dec / tulip / dmfe.c
1 /*
2 A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
3 ethernet driver for Linux.
4 Copyright (C) 1997 Sten Wang
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 DAVICOM Web-Site: www.davicom.com.tw
17
18 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
19 Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
20
21 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
22
23 Marcelo Tosatti <marcelo@conectiva.com.br> :
24 Made it compile in 2.3 (device to net_device)
25
26 Alan Cox <alan@lxorguk.ukuu.org.uk> :
27 Cleaned up for kernel merge.
28 Removed the back compatibility support
29 Reformatted, fixing spelling etc as I went
30 Removed IRQ 0-15 assumption
31
32 Jeff Garzik <jgarzik@pobox.com> :
33 Updated to use new PCI driver API.
34 Resource usage cleanups.
35 Report driver version to user.
36
37 Tobias Ringstrom <tori@unhappy.mine.nu> :
38 Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
39 Andrew Morton and Frank Davis for the SMP safety fixes.
40
41 Vojtech Pavlik <vojtech@suse.cz> :
42 Cleaned up pointer arithmetics.
43 Fixed a lot of 64bit issues.
44 Cleaned up printk()s a bit.
45 Fixed some obvious big endian problems.
46
47 Tobias Ringstrom <tori@unhappy.mine.nu> :
48 Use time_after for jiffies calculation. Added ethtool
49 support. Updated PCI resource allocation. Do not
50 forget to unmap PCI mapped skbs.
51
52 Alan Cox <alan@lxorguk.ukuu.org.uk>
53 Added new PCI identifiers provided by Clear Zhang at ALi
54 for their 1563 ethernet device.
55
56 TODO
57
58 Check on 64 bit boxes.
59 Check and fix on big endian boxes.
60
61 Test and make sure PCI latency is now correct for all cases.
62 */
63
64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
65
66 #define DRV_NAME "dmfe"
67 #define DRV_VERSION "1.36.4"
68 #define DRV_RELDATE "2002-01-17"
69
70 #include <linux/module.h>
71 #include <linux/kernel.h>
72 #include <linux/string.h>
73 #include <linux/timer.h>
74 #include <linux/ptrace.h>
75 #include <linux/errno.h>
76 #include <linux/ioport.h>
77 #include <linux/interrupt.h>
78 #include <linux/pci.h>
79 #include <linux/dma-mapping.h>
80 #include <linux/init.h>
81 #include <linux/netdevice.h>
82 #include <linux/etherdevice.h>
83 #include <linux/ethtool.h>
84 #include <linux/skbuff.h>
85 #include <linux/delay.h>
86 #include <linux/spinlock.h>
87 #include <linux/crc32.h>
88 #include <linux/bitops.h>
89
90 #include <asm/processor.h>
91 #include <asm/io.h>
92 #include <asm/dma.h>
93 #include <linux/uaccess.h>
94 #include <asm/irq.h>
95
96 #ifdef CONFIG_TULIP_DM910X
97 #include <linux/of.h>
98 #endif
99
100
101 /* Board/System/Debug information/definition ---------------- */
102 #define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
103 #define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
104 #define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
105 #define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
106
107 #define DM9102_IO_SIZE 0x80
108 #define DM9102A_IO_SIZE 0x100
109 #define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
110 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
111 #define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
112 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
113 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
114 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
115 #define TX_BUF_ALLOC 0x600
116 #define RX_ALLOC_SIZE 0x620
117 #define DM910X_RESET 1
118 #define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
119 #define CR6_DEFAULT 0x00080000 /* HD */
120 #define CR7_DEFAULT 0x180c1
121 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
122 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
123 #define MAX_PACKET_SIZE 1514
124 #define DMFE_MAX_MULTICAST 14
125 #define RX_COPY_SIZE 100
126 #define MAX_CHECK_PACKET 0x8000
127 #define DM9801_NOISE_FLOOR 8
128 #define DM9802_NOISE_FLOOR 5
129
130 #define DMFE_WOL_LINKCHANGE 0x20000000
131 #define DMFE_WOL_SAMPLEPACKET 0x10000000
132 #define DMFE_WOL_MAGICPACKET 0x08000000
133
134
135 #define DMFE_10MHF 0
136 #define DMFE_100MHF 1
137 #define DMFE_10MFD 4
138 #define DMFE_100MFD 5
139 #define DMFE_AUTO 8
140 #define DMFE_1M_HPNA 0x10
141
142 #define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
143 #define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
144 #define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
145 #define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
146 #define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
147 #define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
148
149 #define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
150 #define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
151 #define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
152
153 #define dw32(reg, val) iowrite32(val, ioaddr + (reg))
154 #define dw16(reg, val) iowrite16(val, ioaddr + (reg))
155 #define dr32(reg) ioread32(ioaddr + (reg))
156 #define dr16(reg) ioread16(ioaddr + (reg))
157 #define dr8(reg) ioread8(ioaddr + (reg))
158
159 #define DMFE_DBUG(dbug_now, msg, value) \
160 do { \
161 if (dmfe_debug || (dbug_now)) \
162 pr_err("%s %lx\n", \
163 (msg), (long) (value)); \
164 } while (0)
165
166 #define SHOW_MEDIA_TYPE(mode) \
167 pr_info("Change Speed to %sMhz %s duplex\n" , \
168 (mode & 1) ? "100":"10", \
169 (mode & 4) ? "full":"half");
170
171
172 /* CR9 definition: SROM/MII */
173 #define CR9_SROM_READ 0x4800
174 #define CR9_SRCS 0x1
175 #define CR9_SRCLK 0x2
176 #define CR9_CRDOUT 0x8
177 #define SROM_DATA_0 0x0
178 #define SROM_DATA_1 0x4
179 #define PHY_DATA_1 0x20000
180 #define PHY_DATA_0 0x00000
181 #define MDCLKH 0x10000
182
183 #define PHY_POWER_DOWN 0x800
184
185 #define SROM_V41_CODE 0x14
186
187 #define __CHK_IO_SIZE(pci_id, dev_rev) \
188 (( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x30) ) ? \
189 DM9102A_IO_SIZE: DM9102_IO_SIZE)
190
191 #define CHK_IO_SIZE(pci_dev) \
192 (__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, \
193 (pci_dev)->revision))
194
195 /* Structure/enum declaration ------------------------------- */
196 struct tx_desc {
197 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
198 char *tx_buf_ptr; /* Data for us */
199 struct tx_desc *next_tx_desc;
200 } __attribute__(( aligned(32) ));
201
202 struct rx_desc {
203 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
204 struct sk_buff *rx_skb_ptr; /* Data for us */
205 struct rx_desc *next_rx_desc;
206 } __attribute__(( aligned(32) ));
207
208 struct dmfe_board_info {
209 u32 chip_id; /* Chip vendor/Device ID */
210 u8 chip_revision; /* Chip revision */
211 struct net_device *next_dev; /* next device */
212 struct pci_dev *pdev; /* PCI device */
213 spinlock_t lock;
214
215 void __iomem *ioaddr; /* I/O base address */
216 u32 cr0_data;
217 u32 cr5_data;
218 u32 cr6_data;
219 u32 cr7_data;
220 u32 cr15_data;
221
222 /* pointer for memory physical address */
223 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
224 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
225 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
226 dma_addr_t first_tx_desc_dma;
227 dma_addr_t first_rx_desc_dma;
228
229 /* descriptor pointer */
230 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
231 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
232 unsigned char *desc_pool_ptr; /* descriptor pool memory */
233 struct tx_desc *first_tx_desc;
234 struct tx_desc *tx_insert_ptr;
235 struct tx_desc *tx_remove_ptr;
236 struct rx_desc *first_rx_desc;
237 struct rx_desc *rx_insert_ptr;
238 struct rx_desc *rx_ready_ptr; /* packet come pointer */
239 unsigned long tx_packet_cnt; /* transmitted packet count */
240 unsigned long tx_queue_cnt; /* wait to send packet count */
241 unsigned long rx_avail_cnt; /* available rx descriptor count */
242 unsigned long interval_rx_cnt; /* rx packet count a callback time */
243
244 u16 HPNA_command; /* For HPNA register 16 */
245 u16 HPNA_timer; /* For HPNA remote device check */
246 u16 dbug_cnt;
247 u16 NIC_capability; /* NIC media capability */
248 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
249
250 u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
251 u8 chip_type; /* Keep DM9102A chip type */
252 u8 media_mode; /* user specify media mode */
253 u8 op_mode; /* real work media mode */
254 u8 phy_addr;
255 u8 wait_reset; /* Hardware failed, need to reset */
256 u8 dm910x_chk_mode; /* Operating mode check */
257 u8 first_in_callback; /* Flag to record state */
258 u8 wol_mode; /* user WOL settings */
259 struct timer_list timer;
260
261 /* Driver defined statistic counter */
262 unsigned long tx_fifo_underrun;
263 unsigned long tx_loss_carrier;
264 unsigned long tx_no_carrier;
265 unsigned long tx_late_collision;
266 unsigned long tx_excessive_collision;
267 unsigned long tx_jabber_timeout;
268 unsigned long reset_count;
269 unsigned long reset_cr8;
270 unsigned long reset_fatal;
271 unsigned long reset_TXtimeout;
272
273 /* NIC SROM data */
274 unsigned char srom[128];
275 };
276
277 enum dmfe_offsets {
278 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
279 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
280 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
281 DCR15 = 0x78
282 };
283
284 enum dmfe_CR6_bits {
285 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
286 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
287 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
288 };
289
290 /* Global variable declaration ----------------------------- */
291 static int printed_version;
292 static const char version[] =
293 "Davicom DM9xxx net driver, version " DRV_VERSION " (" DRV_RELDATE ")";
294
295 static int dmfe_debug;
296 static unsigned char dmfe_media_mode = DMFE_AUTO;
297 static u32 dmfe_cr6_user_set;
298
299 /* For module input parameter */
300 static int debug;
301 static u32 cr6set;
302 static unsigned char mode = 8;
303 static u8 chkmode = 1;
304 static u8 HPNA_mode; /* Default: Low Power/High Speed */
305 static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
306 static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
307 static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
308 static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
309 4: TX pause packet */
310
311
312 /* function declaration ------------------------------------- */
313 static int dmfe_open(struct net_device *);
314 static netdev_tx_t dmfe_start_xmit(struct sk_buff *, struct net_device *);
315 static int dmfe_stop(struct net_device *);
316 static void dmfe_set_filter_mode(struct net_device *);
317 static const struct ethtool_ops netdev_ethtool_ops;
318 static u16 read_srom_word(void __iomem *, int);
319 static irqreturn_t dmfe_interrupt(int , void *);
320 #ifdef CONFIG_NET_POLL_CONTROLLER
321 static void poll_dmfe (struct net_device *dev);
322 #endif
323 static void dmfe_descriptor_init(struct net_device *);
324 static void allocate_rx_buffer(struct net_device *);
325 static void update_cr6(u32, void __iomem *);
326 static void send_filter_frame(struct net_device *);
327 static void dm9132_id_table(struct net_device *);
328 static u16 dmfe_phy_read(void __iomem *, u8, u8, u32);
329 static void dmfe_phy_write(void __iomem *, u8, u8, u16, u32);
330 static void dmfe_phy_write_1bit(void __iomem *, u32);
331 static u16 dmfe_phy_read_1bit(void __iomem *);
332 static u8 dmfe_sense_speed(struct dmfe_board_info *);
333 static void dmfe_process_mode(struct dmfe_board_info *);
334 static void dmfe_timer(struct timer_list *);
335 static inline u32 cal_CRC(unsigned char *, unsigned int, u8);
336 static void dmfe_rx_packet(struct net_device *, struct dmfe_board_info *);
337 static void dmfe_free_tx_pkt(struct net_device *, struct dmfe_board_info *);
338 static void dmfe_reuse_skb(struct dmfe_board_info *, struct sk_buff *);
339 static void dmfe_dynamic_reset(struct net_device *);
340 static void dmfe_free_rxbuffer(struct dmfe_board_info *);
341 static void dmfe_init_dm910x(struct net_device *);
342 static void dmfe_parse_srom(struct dmfe_board_info *);
343 static void dmfe_program_DM9801(struct dmfe_board_info *, int);
344 static void dmfe_program_DM9802(struct dmfe_board_info *);
345 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
346 static void dmfe_set_phyxcer(struct dmfe_board_info *);
347
348 /* DM910X network board routine ---------------------------- */
349
350 static const struct net_device_ops netdev_ops = {
351 .ndo_open = dmfe_open,
352 .ndo_stop = dmfe_stop,
353 .ndo_start_xmit = dmfe_start_xmit,
354 .ndo_set_rx_mode = dmfe_set_filter_mode,
355 .ndo_set_mac_address = eth_mac_addr,
356 .ndo_validate_addr = eth_validate_addr,
357 #ifdef CONFIG_NET_POLL_CONTROLLER
358 .ndo_poll_controller = poll_dmfe,
359 #endif
360 };
361
362 /*
363 * Search DM910X board ,allocate space and register it
364 */
365
366 static int dmfe_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
367 {
368 struct dmfe_board_info *db; /* board information structure */
369 struct net_device *dev;
370 u32 pci_pmr;
371 int i, err;
372
373 DMFE_DBUG(0, "dmfe_init_one()", 0);
374
375 if (!printed_version++)
376 pr_info("%s\n", version);
377
378 /*
379 * SPARC on-board DM910x chips should be handled by the main
380 * tulip driver, except for early DM9100s.
381 */
382 #ifdef CONFIG_TULIP_DM910X
383 if ((ent->driver_data == PCI_DM9100_ID && pdev->revision >= 0x30) ||
384 ent->driver_data == PCI_DM9102_ID) {
385 struct device_node *dp = pci_device_to_OF_node(pdev);
386
387 if (dp && of_get_property(dp, "local-mac-address", NULL)) {
388 pr_info("skipping on-board DM910x (use tulip)\n");
389 return -ENODEV;
390 }
391 }
392 #endif
393
394 /* Init network device */
395 dev = alloc_etherdev(sizeof(*db));
396 if (dev == NULL)
397 return -ENOMEM;
398 SET_NETDEV_DEV(dev, &pdev->dev);
399
400 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
401 pr_warn("32-bit PCI DMA not available\n");
402 err = -ENODEV;
403 goto err_out_free;
404 }
405
406 /* Enable Master/IO access, Disable memory access */
407 err = pci_enable_device(pdev);
408 if (err)
409 goto err_out_free;
410
411 if (!pci_resource_start(pdev, 0)) {
412 pr_err("I/O base is zero\n");
413 err = -ENODEV;
414 goto err_out_disable;
415 }
416
417 if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev)) ) {
418 pr_err("Allocated I/O size too small\n");
419 err = -ENODEV;
420 goto err_out_disable;
421 }
422
423 #if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
424
425 /* Set Latency Timer 80h */
426 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
427 Need a PCI quirk.. */
428
429 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
430 #endif
431
432 if (pci_request_regions(pdev, DRV_NAME)) {
433 pr_err("Failed to request PCI regions\n");
434 err = -ENODEV;
435 goto err_out_disable;
436 }
437
438 /* Init system & device */
439 db = netdev_priv(dev);
440
441 /* Allocate Tx/Rx descriptor memory */
442 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) *
443 DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
444 if (!db->desc_pool_ptr) {
445 err = -ENOMEM;
446 goto err_out_res;
447 }
448
449 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC *
450 TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
451 if (!db->buf_pool_ptr) {
452 err = -ENOMEM;
453 goto err_out_free_desc;
454 }
455
456 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
457 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
458 db->buf_pool_start = db->buf_pool_ptr;
459 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
460
461 db->chip_id = ent->driver_data;
462 /* IO type range. */
463 db->ioaddr = pci_iomap(pdev, 0, 0);
464 if (!db->ioaddr) {
465 err = -ENOMEM;
466 goto err_out_free_buf;
467 }
468
469 db->chip_revision = pdev->revision;
470 db->wol_mode = 0;
471
472 db->pdev = pdev;
473
474 pci_set_drvdata(pdev, dev);
475 dev->netdev_ops = &netdev_ops;
476 dev->ethtool_ops = &netdev_ethtool_ops;
477 netif_carrier_off(dev);
478 spin_lock_init(&db->lock);
479
480 pci_read_config_dword(pdev, 0x50, &pci_pmr);
481 pci_pmr &= 0x70000;
482 if ( (pci_pmr == 0x10000) && (db->chip_revision == 0x31) )
483 db->chip_type = 1; /* DM9102A E3 */
484 else
485 db->chip_type = 0;
486
487 /* read 64 word srom data */
488 for (i = 0; i < 64; i++) {
489 ((__le16 *) db->srom)[i] =
490 cpu_to_le16(read_srom_word(db->ioaddr, i));
491 }
492
493 /* Set Node address */
494 for (i = 0; i < 6; i++)
495 dev->dev_addr[i] = db->srom[20 + i];
496
497 err = register_netdev (dev);
498 if (err)
499 goto err_out_unmap;
500
501 dev_info(&dev->dev, "Davicom DM%04lx at pci%s, %pM, irq %d\n",
502 ent->driver_data >> 16,
503 pci_name(pdev), dev->dev_addr, pdev->irq);
504
505 pci_set_master(pdev);
506
507 return 0;
508
509 err_out_unmap:
510 pci_iounmap(pdev, db->ioaddr);
511 err_out_free_buf:
512 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
513 db->buf_pool_ptr, db->buf_pool_dma_ptr);
514 err_out_free_desc:
515 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
516 db->desc_pool_ptr, db->desc_pool_dma_ptr);
517 err_out_res:
518 pci_release_regions(pdev);
519 err_out_disable:
520 pci_disable_device(pdev);
521 err_out_free:
522 free_netdev(dev);
523
524 return err;
525 }
526
527
528 static void dmfe_remove_one(struct pci_dev *pdev)
529 {
530 struct net_device *dev = pci_get_drvdata(pdev);
531 struct dmfe_board_info *db = netdev_priv(dev);
532
533 DMFE_DBUG(0, "dmfe_remove_one()", 0);
534
535 if (dev) {
536
537 unregister_netdev(dev);
538 pci_iounmap(db->pdev, db->ioaddr);
539 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
540 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
541 db->desc_pool_dma_ptr);
542 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
543 db->buf_pool_ptr, db->buf_pool_dma_ptr);
544 pci_release_regions(pdev);
545 free_netdev(dev); /* free board information */
546 }
547
548 DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
549 }
550
551
552 /*
553 * Open the interface.
554 * The interface is opened whenever "ifconfig" actives it.
555 */
556
557 static int dmfe_open(struct net_device *dev)
558 {
559 struct dmfe_board_info *db = netdev_priv(dev);
560 const int irq = db->pdev->irq;
561 int ret;
562
563 DMFE_DBUG(0, "dmfe_open", 0);
564
565 ret = request_irq(irq, dmfe_interrupt, IRQF_SHARED, dev->name, dev);
566 if (ret)
567 return ret;
568
569 /* system variable init */
570 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
571 db->tx_packet_cnt = 0;
572 db->tx_queue_cnt = 0;
573 db->rx_avail_cnt = 0;
574 db->wait_reset = 0;
575
576 db->first_in_callback = 0;
577 db->NIC_capability = 0xf; /* All capability*/
578 db->PHY_reg4 = 0x1e0;
579
580 /* CR6 operation mode decision */
581 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
582 (db->chip_revision >= 0x30) ) {
583 db->cr6_data |= DMFE_TXTH_256;
584 db->cr0_data = CR0_DEFAULT;
585 db->dm910x_chk_mode=4; /* Enter the normal mode */
586 } else {
587 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
588 db->cr0_data = 0;
589 db->dm910x_chk_mode = 1; /* Enter the check mode */
590 }
591
592 /* Initialize DM910X board */
593 dmfe_init_dm910x(dev);
594
595 /* Active System Interface */
596 netif_wake_queue(dev);
597
598 /* set and active a timer process */
599 timer_setup(&db->timer, dmfe_timer, 0);
600 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
601 add_timer(&db->timer);
602
603 return 0;
604 }
605
606
607 /* Initialize DM910X board
608 * Reset DM910X board
609 * Initialize TX/Rx descriptor chain structure
610 * Send the set-up frame
611 * Enable Tx/Rx machine
612 */
613
614 static void dmfe_init_dm910x(struct net_device *dev)
615 {
616 struct dmfe_board_info *db = netdev_priv(dev);
617 void __iomem *ioaddr = db->ioaddr;
618
619 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
620
621 /* Reset DM910x MAC controller */
622 dw32(DCR0, DM910X_RESET); /* RESET MAC */
623 udelay(100);
624 dw32(DCR0, db->cr0_data);
625 udelay(5);
626
627 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
628 db->phy_addr = 1;
629
630 /* Parser SROM and media mode */
631 dmfe_parse_srom(db);
632 db->media_mode = dmfe_media_mode;
633
634 /* RESET Phyxcer Chip by GPR port bit 7 */
635 dw32(DCR12, 0x180); /* Let bit 7 output port */
636 if (db->chip_id == PCI_DM9009_ID) {
637 dw32(DCR12, 0x80); /* Issue RESET signal */
638 mdelay(300); /* Delay 300 ms */
639 }
640 dw32(DCR12, 0x0); /* Clear RESET signal */
641
642 /* Process Phyxcer Media Mode */
643 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
644 dmfe_set_phyxcer(db);
645
646 /* Media Mode Process */
647 if ( !(db->media_mode & DMFE_AUTO) )
648 db->op_mode = db->media_mode; /* Force Mode */
649
650 /* Initialize Transmit/Receive descriptor and CR3/4 */
651 dmfe_descriptor_init(dev);
652
653 /* Init CR6 to program DM910x operation */
654 update_cr6(db->cr6_data, ioaddr);
655
656 /* Send setup frame */
657 if (db->chip_id == PCI_DM9132_ID)
658 dm9132_id_table(dev); /* DM9132 */
659 else
660 send_filter_frame(dev); /* DM9102/DM9102A */
661
662 /* Init CR7, interrupt active bit */
663 db->cr7_data = CR7_DEFAULT;
664 dw32(DCR7, db->cr7_data);
665
666 /* Init CR15, Tx jabber and Rx watchdog timer */
667 dw32(DCR15, db->cr15_data);
668
669 /* Enable DM910X Tx/Rx function */
670 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
671 update_cr6(db->cr6_data, ioaddr);
672 }
673
674
675 /*
676 * Hardware start transmission.
677 * Send a packet to media from the upper layer.
678 */
679
680 static netdev_tx_t dmfe_start_xmit(struct sk_buff *skb,
681 struct net_device *dev)
682 {
683 struct dmfe_board_info *db = netdev_priv(dev);
684 void __iomem *ioaddr = db->ioaddr;
685 struct tx_desc *txptr;
686 unsigned long flags;
687
688 DMFE_DBUG(0, "dmfe_start_xmit", 0);
689
690 /* Too large packet check */
691 if (skb->len > MAX_PACKET_SIZE) {
692 pr_err("big packet = %d\n", (u16)skb->len);
693 dev_kfree_skb_any(skb);
694 return NETDEV_TX_OK;
695 }
696
697 /* Resource flag check */
698 netif_stop_queue(dev);
699
700 spin_lock_irqsave(&db->lock, flags);
701
702 /* No Tx resource check, it never happen nromally */
703 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
704 spin_unlock_irqrestore(&db->lock, flags);
705 pr_err("No Tx resource %ld\n", db->tx_queue_cnt);
706 return NETDEV_TX_BUSY;
707 }
708
709 /* Disable NIC interrupt */
710 dw32(DCR7, 0);
711
712 /* transmit this packet */
713 txptr = db->tx_insert_ptr;
714 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
715 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
716
717 /* Point to next transmit free descriptor */
718 db->tx_insert_ptr = txptr->next_tx_desc;
719
720 /* Transmit Packet Process */
721 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
722 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
723 db->tx_packet_cnt++; /* Ready to send */
724 dw32(DCR1, 0x1); /* Issue Tx polling */
725 netif_trans_update(dev); /* saved time stamp */
726 } else {
727 db->tx_queue_cnt++; /* queue TX packet */
728 dw32(DCR1, 0x1); /* Issue Tx polling */
729 }
730
731 /* Tx resource check */
732 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
733 netif_wake_queue(dev);
734
735 /* Restore CR7 to enable interrupt */
736 spin_unlock_irqrestore(&db->lock, flags);
737 dw32(DCR7, db->cr7_data);
738
739 /* free this SKB */
740 dev_consume_skb_any(skb);
741
742 return NETDEV_TX_OK;
743 }
744
745
746 /*
747 * Stop the interface.
748 * The interface is stopped when it is brought.
749 */
750
751 static int dmfe_stop(struct net_device *dev)
752 {
753 struct dmfe_board_info *db = netdev_priv(dev);
754 void __iomem *ioaddr = db->ioaddr;
755
756 DMFE_DBUG(0, "dmfe_stop", 0);
757
758 /* disable system */
759 netif_stop_queue(dev);
760
761 /* deleted timer */
762 del_timer_sync(&db->timer);
763
764 /* Reset & stop DM910X board */
765 dw32(DCR0, DM910X_RESET);
766 udelay(100);
767 dmfe_phy_write(ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
768
769 /* free interrupt */
770 free_irq(db->pdev->irq, dev);
771
772 /* free allocated rx buffer */
773 dmfe_free_rxbuffer(db);
774
775 #if 0
776 /* show statistic counter */
777 printk("FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
778 db->tx_fifo_underrun, db->tx_excessive_collision,
779 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
780 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
781 db->reset_fatal, db->reset_TXtimeout);
782 #endif
783
784 return 0;
785 }
786
787
788 /*
789 * DM9102 insterrupt handler
790 * receive the packet to upper layer, free the transmitted packet
791 */
792
793 static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
794 {
795 struct net_device *dev = dev_id;
796 struct dmfe_board_info *db = netdev_priv(dev);
797 void __iomem *ioaddr = db->ioaddr;
798 unsigned long flags;
799
800 DMFE_DBUG(0, "dmfe_interrupt()", 0);
801
802 spin_lock_irqsave(&db->lock, flags);
803
804 /* Got DM910X status */
805 db->cr5_data = dr32(DCR5);
806 dw32(DCR5, db->cr5_data);
807 if ( !(db->cr5_data & 0xc1) ) {
808 spin_unlock_irqrestore(&db->lock, flags);
809 return IRQ_HANDLED;
810 }
811
812 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
813 dw32(DCR7, 0);
814
815 /* Check system status */
816 if (db->cr5_data & 0x2000) {
817 /* system bus error happen */
818 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
819 db->reset_fatal++;
820 db->wait_reset = 1; /* Need to RESET */
821 spin_unlock_irqrestore(&db->lock, flags);
822 return IRQ_HANDLED;
823 }
824
825 /* Received the coming packet */
826 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
827 dmfe_rx_packet(dev, db);
828
829 /* reallocate rx descriptor buffer */
830 if (db->rx_avail_cnt<RX_DESC_CNT)
831 allocate_rx_buffer(dev);
832
833 /* Free the transmitted descriptor */
834 if ( db->cr5_data & 0x01)
835 dmfe_free_tx_pkt(dev, db);
836
837 /* Mode Check */
838 if (db->dm910x_chk_mode & 0x2) {
839 db->dm910x_chk_mode = 0x4;
840 db->cr6_data |= 0x100;
841 update_cr6(db->cr6_data, ioaddr);
842 }
843
844 /* Restore CR7 to enable interrupt mask */
845 dw32(DCR7, db->cr7_data);
846
847 spin_unlock_irqrestore(&db->lock, flags);
848 return IRQ_HANDLED;
849 }
850
851
852 #ifdef CONFIG_NET_POLL_CONTROLLER
853 /*
854 * Polling 'interrupt' - used by things like netconsole to send skbs
855 * without having to re-enable interrupts. It's not called while
856 * the interrupt routine is executing.
857 */
858
859 static void poll_dmfe (struct net_device *dev)
860 {
861 struct dmfe_board_info *db = netdev_priv(dev);
862 const int irq = db->pdev->irq;
863
864 /* disable_irq here is not very nice, but with the lockless
865 interrupt handler we have no other choice. */
866 disable_irq(irq);
867 dmfe_interrupt (irq, dev);
868 enable_irq(irq);
869 }
870 #endif
871
872 /*
873 * Free TX resource after TX complete
874 */
875
876 static void dmfe_free_tx_pkt(struct net_device *dev, struct dmfe_board_info *db)
877 {
878 struct tx_desc *txptr;
879 void __iomem *ioaddr = db->ioaddr;
880 u32 tdes0;
881
882 txptr = db->tx_remove_ptr;
883 while(db->tx_packet_cnt) {
884 tdes0 = le32_to_cpu(txptr->tdes0);
885 if (tdes0 & 0x80000000)
886 break;
887
888 /* A packet sent completed */
889 db->tx_packet_cnt--;
890 dev->stats.tx_packets++;
891
892 /* Transmit statistic counter */
893 if ( tdes0 != 0x7fffffff ) {
894 dev->stats.collisions += (tdes0 >> 3) & 0xf;
895 dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
896 if (tdes0 & TDES0_ERR_MASK) {
897 dev->stats.tx_errors++;
898
899 if (tdes0 & 0x0002) { /* UnderRun */
900 db->tx_fifo_underrun++;
901 if ( !(db->cr6_data & CR6_SFT) ) {
902 db->cr6_data = db->cr6_data | CR6_SFT;
903 update_cr6(db->cr6_data, ioaddr);
904 }
905 }
906 if (tdes0 & 0x0100)
907 db->tx_excessive_collision++;
908 if (tdes0 & 0x0200)
909 db->tx_late_collision++;
910 if (tdes0 & 0x0400)
911 db->tx_no_carrier++;
912 if (tdes0 & 0x0800)
913 db->tx_loss_carrier++;
914 if (tdes0 & 0x4000)
915 db->tx_jabber_timeout++;
916 }
917 }
918
919 txptr = txptr->next_tx_desc;
920 }/* End of while */
921
922 /* Update TX remove pointer to next */
923 db->tx_remove_ptr = txptr;
924
925 /* Send the Tx packet in queue */
926 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
927 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
928 db->tx_packet_cnt++; /* Ready to send */
929 db->tx_queue_cnt--;
930 dw32(DCR1, 0x1); /* Issue Tx polling */
931 netif_trans_update(dev); /* saved time stamp */
932 }
933
934 /* Resource available check */
935 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
936 netif_wake_queue(dev); /* Active upper layer, send again */
937 }
938
939
940 /*
941 * Calculate the CRC valude of the Rx packet
942 * flag = 1 : return the reverse CRC (for the received packet CRC)
943 * 0 : return the normal CRC (for Hash Table index)
944 */
945
946 static inline u32 cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
947 {
948 u32 crc = crc32(~0, Data, Len);
949 if (flag) crc = ~crc;
950 return crc;
951 }
952
953
954 /*
955 * Receive the come packet and pass to upper layer
956 */
957
958 static void dmfe_rx_packet(struct net_device *dev, struct dmfe_board_info *db)
959 {
960 struct rx_desc *rxptr;
961 struct sk_buff *skb, *newskb;
962 int rxlen;
963 u32 rdes0;
964
965 rxptr = db->rx_ready_ptr;
966
967 while(db->rx_avail_cnt) {
968 rdes0 = le32_to_cpu(rxptr->rdes0);
969 if (rdes0 & 0x80000000) /* packet owner check */
970 break;
971
972 db->rx_avail_cnt--;
973 db->interval_rx_cnt++;
974
975 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2),
976 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
977
978 if ( (rdes0 & 0x300) != 0x300) {
979 /* A packet without First/Last flag */
980 /* reuse this SKB */
981 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
982 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
983 } else {
984 /* A packet with First/Last flag */
985 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
986
987 /* error summary bit check */
988 if (rdes0 & 0x8000) {
989 /* This is a error packet */
990 dev->stats.rx_errors++;
991 if (rdes0 & 1)
992 dev->stats.rx_fifo_errors++;
993 if (rdes0 & 2)
994 dev->stats.rx_crc_errors++;
995 if (rdes0 & 0x80)
996 dev->stats.rx_length_errors++;
997 }
998
999 if ( !(rdes0 & 0x8000) ||
1000 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
1001 skb = rxptr->rx_skb_ptr;
1002
1003 /* Received Packet CRC check need or not */
1004 if ( (db->dm910x_chk_mode & 1) &&
1005 (cal_CRC(skb->data, rxlen, 1) !=
1006 (*(u32 *) (skb->data+rxlen) ))) { /* FIXME (?) */
1007 /* Found a error received packet */
1008 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1009 db->dm910x_chk_mode = 3;
1010 } else {
1011 /* Good packet, send to upper layer */
1012 /* Shorst packet used new SKB */
1013 if ((rxlen < RX_COPY_SIZE) &&
1014 ((newskb = netdev_alloc_skb(dev, rxlen + 2))
1015 != NULL)) {
1016
1017 skb = newskb;
1018 /* size less than COPY_SIZE, allocate a rxlen SKB */
1019 skb_reserve(skb, 2); /* 16byte align */
1020 skb_copy_from_linear_data(rxptr->rx_skb_ptr,
1021 skb_put(skb, rxlen),
1022 rxlen);
1023 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1024 } else
1025 skb_put(skb, rxlen);
1026
1027 skb->protocol = eth_type_trans(skb, dev);
1028 netif_rx(skb);
1029 dev->stats.rx_packets++;
1030 dev->stats.rx_bytes += rxlen;
1031 }
1032 } else {
1033 /* Reuse SKB buffer when the packet is error */
1034 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
1035 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1036 }
1037 }
1038
1039 rxptr = rxptr->next_rx_desc;
1040 }
1041
1042 db->rx_ready_ptr = rxptr;
1043 }
1044
1045 /*
1046 * Set DM910X multicast address
1047 */
1048
1049 static void dmfe_set_filter_mode(struct net_device *dev)
1050 {
1051 struct dmfe_board_info *db = netdev_priv(dev);
1052 unsigned long flags;
1053 int mc_count = netdev_mc_count(dev);
1054
1055 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
1056 spin_lock_irqsave(&db->lock, flags);
1057
1058 if (dev->flags & IFF_PROMISC) {
1059 DMFE_DBUG(0, "Enable PROM Mode", 0);
1060 db->cr6_data |= CR6_PM | CR6_PBF;
1061 update_cr6(db->cr6_data, db->ioaddr);
1062 spin_unlock_irqrestore(&db->lock, flags);
1063 return;
1064 }
1065
1066 if (dev->flags & IFF_ALLMULTI || mc_count > DMFE_MAX_MULTICAST) {
1067 DMFE_DBUG(0, "Pass all multicast address", mc_count);
1068 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1069 db->cr6_data |= CR6_PAM;
1070 spin_unlock_irqrestore(&db->lock, flags);
1071 return;
1072 }
1073
1074 DMFE_DBUG(0, "Set multicast address", mc_count);
1075 if (db->chip_id == PCI_DM9132_ID)
1076 dm9132_id_table(dev); /* DM9132 */
1077 else
1078 send_filter_frame(dev); /* DM9102/DM9102A */
1079 spin_unlock_irqrestore(&db->lock, flags);
1080 }
1081
1082 /*
1083 * Ethtool interace
1084 */
1085
1086 static void dmfe_ethtool_get_drvinfo(struct net_device *dev,
1087 struct ethtool_drvinfo *info)
1088 {
1089 struct dmfe_board_info *np = netdev_priv(dev);
1090
1091 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1092 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1093 strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
1094 }
1095
1096 static int dmfe_ethtool_set_wol(struct net_device *dev,
1097 struct ethtool_wolinfo *wolinfo)
1098 {
1099 struct dmfe_board_info *db = netdev_priv(dev);
1100
1101 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST |
1102 WAKE_ARP | WAKE_MAGICSECURE))
1103 return -EOPNOTSUPP;
1104
1105 db->wol_mode = wolinfo->wolopts;
1106 return 0;
1107 }
1108
1109 static void dmfe_ethtool_get_wol(struct net_device *dev,
1110 struct ethtool_wolinfo *wolinfo)
1111 {
1112 struct dmfe_board_info *db = netdev_priv(dev);
1113
1114 wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
1115 wolinfo->wolopts = db->wol_mode;
1116 }
1117
1118
1119 static const struct ethtool_ops netdev_ethtool_ops = {
1120 .get_drvinfo = dmfe_ethtool_get_drvinfo,
1121 .get_link = ethtool_op_get_link,
1122 .set_wol = dmfe_ethtool_set_wol,
1123 .get_wol = dmfe_ethtool_get_wol,
1124 };
1125
1126 /*
1127 * A periodic timer routine
1128 * Dynamic media sense, allocate Rx buffer...
1129 */
1130
1131 static void dmfe_timer(struct timer_list *t)
1132 {
1133 struct dmfe_board_info *db = from_timer(db, t, timer);
1134 struct net_device *dev = pci_get_drvdata(db->pdev);
1135 void __iomem *ioaddr = db->ioaddr;
1136 u32 tmp_cr8;
1137 unsigned char tmp_cr12;
1138 unsigned long flags;
1139
1140 int link_ok, link_ok_phy;
1141
1142 DMFE_DBUG(0, "dmfe_timer()", 0);
1143 spin_lock_irqsave(&db->lock, flags);
1144
1145 /* Media mode process when Link OK before enter this route */
1146 if (db->first_in_callback == 0) {
1147 db->first_in_callback = 1;
1148 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1149 db->cr6_data &= ~0x40000;
1150 update_cr6(db->cr6_data, ioaddr);
1151 dmfe_phy_write(ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1152 db->cr6_data |= 0x40000;
1153 update_cr6(db->cr6_data, ioaddr);
1154 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1155 add_timer(&db->timer);
1156 spin_unlock_irqrestore(&db->lock, flags);
1157 return;
1158 }
1159 }
1160
1161
1162 /* Operating Mode Check */
1163 if ( (db->dm910x_chk_mode & 0x1) &&
1164 (dev->stats.rx_packets > MAX_CHECK_PACKET) )
1165 db->dm910x_chk_mode = 0x4;
1166
1167 /* Dynamic reset DM910X : system error or transmit time-out */
1168 tmp_cr8 = dr32(DCR8);
1169 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1170 db->reset_cr8++;
1171 db->wait_reset = 1;
1172 }
1173 db->interval_rx_cnt = 0;
1174
1175 /* TX polling kick monitor */
1176 if ( db->tx_packet_cnt &&
1177 time_after(jiffies, dev_trans_start(dev) + DMFE_TX_KICK) ) {
1178 dw32(DCR1, 0x1); /* Tx polling again */
1179
1180 /* TX Timeout */
1181 if (time_after(jiffies, dev_trans_start(dev) + DMFE_TX_TIMEOUT) ) {
1182 db->reset_TXtimeout++;
1183 db->wait_reset = 1;
1184 dev_warn(&dev->dev, "Tx timeout - resetting\n");
1185 }
1186 }
1187
1188 if (db->wait_reset) {
1189 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1190 db->reset_count++;
1191 dmfe_dynamic_reset(dev);
1192 db->first_in_callback = 0;
1193 db->timer.expires = DMFE_TIMER_WUT;
1194 add_timer(&db->timer);
1195 spin_unlock_irqrestore(&db->lock, flags);
1196 return;
1197 }
1198
1199 /* Link status check, Dynamic media type change */
1200 if (db->chip_id == PCI_DM9132_ID)
1201 tmp_cr12 = dr8(DCR9 + 3); /* DM9132 */
1202 else
1203 tmp_cr12 = dr8(DCR12); /* DM9102/DM9102A */
1204
1205 if ( ((db->chip_id == PCI_DM9102_ID) &&
1206 (db->chip_revision == 0x30)) ||
1207 ((db->chip_id == PCI_DM9132_ID) &&
1208 (db->chip_revision == 0x10)) ) {
1209 /* DM9102A Chip */
1210 if (tmp_cr12 & 2)
1211 link_ok = 0;
1212 else
1213 link_ok = 1;
1214 }
1215 else
1216 /*0x43 is used instead of 0x3 because bit 6 should represent
1217 link status of external PHY */
1218 link_ok = (tmp_cr12 & 0x43) ? 1 : 0;
1219
1220
1221 /* If chip reports that link is failed it could be because external
1222 PHY link status pin is not connected correctly to chip
1223 To be sure ask PHY too.
1224 */
1225
1226 /* need a dummy read because of PHY's register latch*/
1227 dmfe_phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
1228 link_ok_phy = (dmfe_phy_read (db->ioaddr,
1229 db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
1230
1231 if (link_ok_phy != link_ok) {
1232 DMFE_DBUG (0, "PHY and chip report different link status", 0);
1233 link_ok = link_ok | link_ok_phy;
1234 }
1235
1236 if ( !link_ok && netif_carrier_ok(dev)) {
1237 /* Link Failed */
1238 DMFE_DBUG(0, "Link Failed", tmp_cr12);
1239 netif_carrier_off(dev);
1240
1241 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1242 /* AUTO or force 1M Homerun/Longrun don't need */
1243 if ( !(db->media_mode & 0x38) )
1244 dmfe_phy_write(db->ioaddr, db->phy_addr,
1245 0, 0x1000, db->chip_id);
1246
1247 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1248 if (db->media_mode & DMFE_AUTO) {
1249 /* 10/100M link failed, used 1M Home-Net */
1250 db->cr6_data|=0x00040000; /* bit18=1, MII */
1251 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1252 update_cr6(db->cr6_data, ioaddr);
1253 }
1254 } else if (!netif_carrier_ok(dev)) {
1255
1256 DMFE_DBUG(0, "Link link OK", tmp_cr12);
1257
1258 /* Auto Sense Speed */
1259 if ( !(db->media_mode & DMFE_AUTO) || !dmfe_sense_speed(db)) {
1260 netif_carrier_on(dev);
1261 SHOW_MEDIA_TYPE(db->op_mode);
1262 }
1263
1264 dmfe_process_mode(db);
1265 }
1266
1267 /* HPNA remote command check */
1268 if (db->HPNA_command & 0xf00) {
1269 db->HPNA_timer--;
1270 if (!db->HPNA_timer)
1271 dmfe_HPNA_remote_cmd_chk(db);
1272 }
1273
1274 /* Timer active again */
1275 db->timer.expires = DMFE_TIMER_WUT;
1276 add_timer(&db->timer);
1277 spin_unlock_irqrestore(&db->lock, flags);
1278 }
1279
1280
1281 /*
1282 * Dynamic reset the DM910X board
1283 * Stop DM910X board
1284 * Free Tx/Rx allocated memory
1285 * Reset DM910X board
1286 * Re-initialize DM910X board
1287 */
1288
1289 static void dmfe_dynamic_reset(struct net_device *dev)
1290 {
1291 struct dmfe_board_info *db = netdev_priv(dev);
1292 void __iomem *ioaddr = db->ioaddr;
1293
1294 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1295
1296 /* Sopt MAC controller */
1297 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1298 update_cr6(db->cr6_data, ioaddr);
1299 dw32(DCR7, 0); /* Disable Interrupt */
1300 dw32(DCR5, dr32(DCR5));
1301
1302 /* Disable upper layer interface */
1303 netif_stop_queue(dev);
1304
1305 /* Free Rx Allocate buffer */
1306 dmfe_free_rxbuffer(db);
1307
1308 /* system variable init */
1309 db->tx_packet_cnt = 0;
1310 db->tx_queue_cnt = 0;
1311 db->rx_avail_cnt = 0;
1312 netif_carrier_off(dev);
1313 db->wait_reset = 0;
1314
1315 /* Re-initialize DM910X board */
1316 dmfe_init_dm910x(dev);
1317
1318 /* Restart upper layer interface */
1319 netif_wake_queue(dev);
1320 }
1321
1322
1323 /*
1324 * free all allocated rx buffer
1325 */
1326
1327 static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1328 {
1329 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
1330
1331 /* free allocated rx buffer */
1332 while (db->rx_avail_cnt) {
1333 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1334 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1335 db->rx_avail_cnt--;
1336 }
1337 }
1338
1339
1340 /*
1341 * Reuse the SK buffer
1342 */
1343
1344 static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1345 {
1346 struct rx_desc *rxptr = db->rx_insert_ptr;
1347
1348 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1349 rxptr->rx_skb_ptr = skb;
1350 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev,
1351 skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1352 wmb();
1353 rxptr->rdes0 = cpu_to_le32(0x80000000);
1354 db->rx_avail_cnt++;
1355 db->rx_insert_ptr = rxptr->next_rx_desc;
1356 } else
1357 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1358 }
1359
1360
1361 /*
1362 * Initialize transmit/Receive descriptor
1363 * Using Chain structure, and allocate Tx/Rx buffer
1364 */
1365
1366 static void dmfe_descriptor_init(struct net_device *dev)
1367 {
1368 struct dmfe_board_info *db = netdev_priv(dev);
1369 void __iomem *ioaddr = db->ioaddr;
1370 struct tx_desc *tmp_tx;
1371 struct rx_desc *tmp_rx;
1372 unsigned char *tmp_buf;
1373 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1374 dma_addr_t tmp_buf_dma;
1375 int i;
1376
1377 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1378
1379 /* tx descriptor start pointer */
1380 db->tx_insert_ptr = db->first_tx_desc;
1381 db->tx_remove_ptr = db->first_tx_desc;
1382 dw32(DCR4, db->first_tx_desc_dma); /* TX DESC address */
1383
1384 /* rx descriptor start pointer */
1385 db->first_rx_desc = (void *)db->first_tx_desc +
1386 sizeof(struct tx_desc) * TX_DESC_CNT;
1387
1388 db->first_rx_desc_dma = db->first_tx_desc_dma +
1389 sizeof(struct tx_desc) * TX_DESC_CNT;
1390 db->rx_insert_ptr = db->first_rx_desc;
1391 db->rx_ready_ptr = db->first_rx_desc;
1392 dw32(DCR3, db->first_rx_desc_dma); /* RX DESC address */
1393
1394 /* Init Transmit chain */
1395 tmp_buf = db->buf_pool_start;
1396 tmp_buf_dma = db->buf_pool_dma_start;
1397 tmp_tx_dma = db->first_tx_desc_dma;
1398 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1399 tmp_tx->tx_buf_ptr = tmp_buf;
1400 tmp_tx->tdes0 = cpu_to_le32(0);
1401 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1402 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1403 tmp_tx_dma += sizeof(struct tx_desc);
1404 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1405 tmp_tx->next_tx_desc = tmp_tx + 1;
1406 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1407 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1408 }
1409 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1410 tmp_tx->next_tx_desc = db->first_tx_desc;
1411
1412 /* Init Receive descriptor chain */
1413 tmp_rx_dma=db->first_rx_desc_dma;
1414 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1415 tmp_rx->rdes0 = cpu_to_le32(0);
1416 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1417 tmp_rx_dma += sizeof(struct rx_desc);
1418 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1419 tmp_rx->next_rx_desc = tmp_rx + 1;
1420 }
1421 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1422 tmp_rx->next_rx_desc = db->first_rx_desc;
1423
1424 /* pre-allocate Rx buffer */
1425 allocate_rx_buffer(dev);
1426 }
1427
1428
1429 /*
1430 * Update CR6 value
1431 * Firstly stop DM910X , then written value and start
1432 */
1433
1434 static void update_cr6(u32 cr6_data, void __iomem *ioaddr)
1435 {
1436 u32 cr6_tmp;
1437
1438 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1439 dw32(DCR6, cr6_tmp);
1440 udelay(5);
1441 dw32(DCR6, cr6_data);
1442 udelay(5);
1443 }
1444
1445
1446 /*
1447 * Send a setup frame for DM9132
1448 * This setup frame initialize DM910X address filter mode
1449 */
1450
1451 static void dm9132_id_table(struct net_device *dev)
1452 {
1453 struct dmfe_board_info *db = netdev_priv(dev);
1454 void __iomem *ioaddr = db->ioaddr + 0xc0;
1455 u16 *addrptr = (u16 *)dev->dev_addr;
1456 struct netdev_hw_addr *ha;
1457 u16 i, hash_table[4];
1458
1459 /* Node address */
1460 for (i = 0; i < 3; i++) {
1461 dw16(0, addrptr[i]);
1462 ioaddr += 4;
1463 }
1464
1465 /* Clear Hash Table */
1466 memset(hash_table, 0, sizeof(hash_table));
1467
1468 /* broadcast address */
1469 hash_table[3] = 0x8000;
1470
1471 /* the multicast address in Hash Table : 64 bits */
1472 netdev_for_each_mc_addr(ha, dev) {
1473 u32 hash_val = cal_CRC((char *)ha->addr, 6, 0) & 0x3f;
1474
1475 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1476 }
1477
1478 /* Write the hash table to MAC MD table */
1479 for (i = 0; i < 4; i++, ioaddr += 4)
1480 dw16(0, hash_table[i]);
1481 }
1482
1483
1484 /*
1485 * Send a setup frame for DM9102/DM9102A
1486 * This setup frame initialize DM910X address filter mode
1487 */
1488
1489 static void send_filter_frame(struct net_device *dev)
1490 {
1491 struct dmfe_board_info *db = netdev_priv(dev);
1492 struct netdev_hw_addr *ha;
1493 struct tx_desc *txptr;
1494 u16 * addrptr;
1495 u32 * suptr;
1496 int i;
1497
1498 DMFE_DBUG(0, "send_filter_frame()", 0);
1499
1500 txptr = db->tx_insert_ptr;
1501 suptr = (u32 *) txptr->tx_buf_ptr;
1502
1503 /* Node address */
1504 addrptr = (u16 *) dev->dev_addr;
1505 *suptr++ = addrptr[0];
1506 *suptr++ = addrptr[1];
1507 *suptr++ = addrptr[2];
1508
1509 /* broadcast address */
1510 *suptr++ = 0xffff;
1511 *suptr++ = 0xffff;
1512 *suptr++ = 0xffff;
1513
1514 /* fit the multicast address */
1515 netdev_for_each_mc_addr(ha, dev) {
1516 addrptr = (u16 *) ha->addr;
1517 *suptr++ = addrptr[0];
1518 *suptr++ = addrptr[1];
1519 *suptr++ = addrptr[2];
1520 }
1521
1522 for (i = netdev_mc_count(dev); i < 14; i++) {
1523 *suptr++ = 0xffff;
1524 *suptr++ = 0xffff;
1525 *suptr++ = 0xffff;
1526 }
1527
1528 /* prepare the setup frame */
1529 db->tx_insert_ptr = txptr->next_tx_desc;
1530 txptr->tdes1 = cpu_to_le32(0x890000c0);
1531
1532 /* Resource Check and Send the setup packet */
1533 if (!db->tx_packet_cnt) {
1534 void __iomem *ioaddr = db->ioaddr;
1535
1536 /* Resource Empty */
1537 db->tx_packet_cnt++;
1538 txptr->tdes0 = cpu_to_le32(0x80000000);
1539 update_cr6(db->cr6_data | 0x2000, ioaddr);
1540 dw32(DCR1, 0x1); /* Issue Tx polling */
1541 update_cr6(db->cr6_data, ioaddr);
1542 netif_trans_update(dev);
1543 } else
1544 db->tx_queue_cnt++; /* Put in TX queue */
1545 }
1546
1547
1548 /*
1549 * Allocate rx buffer,
1550 * As possible as allocate maxiumn Rx buffer
1551 */
1552
1553 static void allocate_rx_buffer(struct net_device *dev)
1554 {
1555 struct dmfe_board_info *db = netdev_priv(dev);
1556 struct rx_desc *rxptr;
1557 struct sk_buff *skb;
1558
1559 rxptr = db->rx_insert_ptr;
1560
1561 while(db->rx_avail_cnt < RX_DESC_CNT) {
1562 if ( ( skb = netdev_alloc_skb(dev, RX_ALLOC_SIZE) ) == NULL )
1563 break;
1564 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1565 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data,
1566 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1567 wmb();
1568 rxptr->rdes0 = cpu_to_le32(0x80000000);
1569 rxptr = rxptr->next_rx_desc;
1570 db->rx_avail_cnt++;
1571 }
1572
1573 db->rx_insert_ptr = rxptr;
1574 }
1575
1576 static void srom_clk_write(void __iomem *ioaddr, u32 data)
1577 {
1578 static const u32 cmd[] = {
1579 CR9_SROM_READ | CR9_SRCS,
1580 CR9_SROM_READ | CR9_SRCS | CR9_SRCLK,
1581 CR9_SROM_READ | CR9_SRCS
1582 };
1583 int i;
1584
1585 for (i = 0; i < ARRAY_SIZE(cmd); i++) {
1586 dw32(DCR9, data | cmd[i]);
1587 udelay(5);
1588 }
1589 }
1590
1591 /*
1592 * Read one word data from the serial ROM
1593 */
1594 static u16 read_srom_word(void __iomem *ioaddr, int offset)
1595 {
1596 u16 srom_data;
1597 int i;
1598
1599 dw32(DCR9, CR9_SROM_READ);
1600 udelay(5);
1601 dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1602 udelay(5);
1603
1604 /* Send the Read Command 110b */
1605 srom_clk_write(ioaddr, SROM_DATA_1);
1606 srom_clk_write(ioaddr, SROM_DATA_1);
1607 srom_clk_write(ioaddr, SROM_DATA_0);
1608
1609 /* Send the offset */
1610 for (i = 5; i >= 0; i--) {
1611 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1612 srom_clk_write(ioaddr, srom_data);
1613 }
1614
1615 dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1616 udelay(5);
1617
1618 for (i = 16; i > 0; i--) {
1619 dw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
1620 udelay(5);
1621 srom_data = (srom_data << 1) |
1622 ((dr32(DCR9) & CR9_CRDOUT) ? 1 : 0);
1623 dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1624 udelay(5);
1625 }
1626
1627 dw32(DCR9, CR9_SROM_READ);
1628 udelay(5);
1629 return srom_data;
1630 }
1631
1632
1633 /*
1634 * Auto sense the media mode
1635 */
1636
1637 static u8 dmfe_sense_speed(struct dmfe_board_info *db)
1638 {
1639 void __iomem *ioaddr = db->ioaddr;
1640 u8 ErrFlag = 0;
1641 u16 phy_mode;
1642
1643 /* CR6 bit18=0, select 10/100M */
1644 update_cr6(db->cr6_data & ~0x40000, ioaddr);
1645
1646 phy_mode = dmfe_phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1647 phy_mode = dmfe_phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1648
1649 if ( (phy_mode & 0x24) == 0x24 ) {
1650 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
1651 phy_mode = dmfe_phy_read(db->ioaddr,
1652 db->phy_addr, 7, db->chip_id) & 0xf000;
1653 else /* DM9102/DM9102A */
1654 phy_mode = dmfe_phy_read(db->ioaddr,
1655 db->phy_addr, 17, db->chip_id) & 0xf000;
1656 switch (phy_mode) {
1657 case 0x1000: db->op_mode = DMFE_10MHF; break;
1658 case 0x2000: db->op_mode = DMFE_10MFD; break;
1659 case 0x4000: db->op_mode = DMFE_100MHF; break;
1660 case 0x8000: db->op_mode = DMFE_100MFD; break;
1661 default: db->op_mode = DMFE_10MHF;
1662 ErrFlag = 1;
1663 break;
1664 }
1665 } else {
1666 db->op_mode = DMFE_10MHF;
1667 DMFE_DBUG(0, "Link Failed :", phy_mode);
1668 ErrFlag = 1;
1669 }
1670
1671 return ErrFlag;
1672 }
1673
1674
1675 /*
1676 * Set 10/100 phyxcer capability
1677 * AUTO mode : phyxcer register4 is NIC capability
1678 * Force mode: phyxcer register4 is the force media
1679 */
1680
1681 static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1682 {
1683 void __iomem *ioaddr = db->ioaddr;
1684 u16 phy_reg;
1685
1686 /* Select 10/100M phyxcer */
1687 db->cr6_data &= ~0x40000;
1688 update_cr6(db->cr6_data, ioaddr);
1689
1690 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1691 if (db->chip_id == PCI_DM9009_ID) {
1692 phy_reg = dmfe_phy_read(db->ioaddr,
1693 db->phy_addr, 18, db->chip_id) & ~0x1000;
1694
1695 dmfe_phy_write(db->ioaddr,
1696 db->phy_addr, 18, phy_reg, db->chip_id);
1697 }
1698
1699 /* Phyxcer capability setting */
1700 phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1701
1702 if (db->media_mode & DMFE_AUTO) {
1703 /* AUTO Mode */
1704 phy_reg |= db->PHY_reg4;
1705 } else {
1706 /* Force Mode */
1707 switch(db->media_mode) {
1708 case DMFE_10MHF: phy_reg |= 0x20; break;
1709 case DMFE_10MFD: phy_reg |= 0x40; break;
1710 case DMFE_100MHF: phy_reg |= 0x80; break;
1711 case DMFE_100MFD: phy_reg |= 0x100; break;
1712 }
1713 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1714 }
1715
1716 /* Write new capability to Phyxcer Reg4 */
1717 if ( !(phy_reg & 0x01e0)) {
1718 phy_reg|=db->PHY_reg4;
1719 db->media_mode|=DMFE_AUTO;
1720 }
1721 dmfe_phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1722
1723 /* Restart Auto-Negotiation */
1724 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1725 dmfe_phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1726 if ( !db->chip_type )
1727 dmfe_phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1728 }
1729
1730
1731 /*
1732 * Process op-mode
1733 * AUTO mode : PHY controller in Auto-negotiation Mode
1734 * Force mode: PHY controller in force mode with HUB
1735 * N-way force capability with SWITCH
1736 */
1737
1738 static void dmfe_process_mode(struct dmfe_board_info *db)
1739 {
1740 u16 phy_reg;
1741
1742 /* Full Duplex Mode Check */
1743 if (db->op_mode & 0x4)
1744 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1745 else
1746 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1747
1748 /* Transciver Selection */
1749 if (db->op_mode & 0x10) /* 1M HomePNA */
1750 db->cr6_data |= 0x40000;/* External MII select */
1751 else
1752 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1753
1754 update_cr6(db->cr6_data, db->ioaddr);
1755
1756 /* 10/100M phyxcer force mode need */
1757 if ( !(db->media_mode & 0x18)) {
1758 /* Forece Mode */
1759 phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1760 if ( !(phy_reg & 0x1) ) {
1761 /* parter without N-Way capability */
1762 phy_reg = 0x0;
1763 switch(db->op_mode) {
1764 case DMFE_10MHF: phy_reg = 0x0; break;
1765 case DMFE_10MFD: phy_reg = 0x100; break;
1766 case DMFE_100MHF: phy_reg = 0x2000; break;
1767 case DMFE_100MFD: phy_reg = 0x2100; break;
1768 }
1769 dmfe_phy_write(db->ioaddr,
1770 db->phy_addr, 0, phy_reg, db->chip_id);
1771 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1772 mdelay(20);
1773 dmfe_phy_write(db->ioaddr,
1774 db->phy_addr, 0, phy_reg, db->chip_id);
1775 }
1776 }
1777 }
1778
1779
1780 /*
1781 * Write a word to Phy register
1782 */
1783
1784 static void dmfe_phy_write(void __iomem *ioaddr, u8 phy_addr, u8 offset,
1785 u16 phy_data, u32 chip_id)
1786 {
1787 u16 i;
1788
1789 if (chip_id == PCI_DM9132_ID) {
1790 dw16(0x80 + offset * 4, phy_data);
1791 } else {
1792 /* DM9102/DM9102A Chip */
1793
1794 /* Send 33 synchronization clock to Phy controller */
1795 for (i = 0; i < 35; i++)
1796 dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
1797
1798 /* Send start command(01) to Phy */
1799 dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
1800 dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
1801
1802 /* Send write command(01) to Phy */
1803 dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
1804 dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
1805
1806 /* Send Phy address */
1807 for (i = 0x10; i > 0; i = i >> 1)
1808 dmfe_phy_write_1bit(ioaddr,
1809 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1810
1811 /* Send register address */
1812 for (i = 0x10; i > 0; i = i >> 1)
1813 dmfe_phy_write_1bit(ioaddr,
1814 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1815
1816 /* written trasnition */
1817 dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
1818 dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
1819
1820 /* Write a word data to PHY controller */
1821 for ( i = 0x8000; i > 0; i >>= 1)
1822 dmfe_phy_write_1bit(ioaddr,
1823 phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1824 }
1825 }
1826
1827
1828 /*
1829 * Read a word data from phy register
1830 */
1831
1832 static u16 dmfe_phy_read(void __iomem *ioaddr, u8 phy_addr, u8 offset, u32 chip_id)
1833 {
1834 int i;
1835 u16 phy_data;
1836
1837 if (chip_id == PCI_DM9132_ID) {
1838 /* DM9132 Chip */
1839 phy_data = dr16(0x80 + offset * 4);
1840 } else {
1841 /* DM9102/DM9102A Chip */
1842
1843 /* Send 33 synchronization clock to Phy controller */
1844 for (i = 0; i < 35; i++)
1845 dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
1846
1847 /* Send start command(01) to Phy */
1848 dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
1849 dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
1850
1851 /* Send read command(10) to Phy */
1852 dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
1853 dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
1854
1855 /* Send Phy address */
1856 for (i = 0x10; i > 0; i = i >> 1)
1857 dmfe_phy_write_1bit(ioaddr,
1858 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1859
1860 /* Send register address */
1861 for (i = 0x10; i > 0; i = i >> 1)
1862 dmfe_phy_write_1bit(ioaddr,
1863 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1864
1865 /* Skip transition state */
1866 dmfe_phy_read_1bit(ioaddr);
1867
1868 /* read 16bit data */
1869 for (phy_data = 0, i = 0; i < 16; i++) {
1870 phy_data <<= 1;
1871 phy_data |= dmfe_phy_read_1bit(ioaddr);
1872 }
1873 }
1874
1875 return phy_data;
1876 }
1877
1878
1879 /*
1880 * Write one bit data to Phy Controller
1881 */
1882
1883 static void dmfe_phy_write_1bit(void __iomem *ioaddr, u32 phy_data)
1884 {
1885 dw32(DCR9, phy_data); /* MII Clock Low */
1886 udelay(1);
1887 dw32(DCR9, phy_data | MDCLKH); /* MII Clock High */
1888 udelay(1);
1889 dw32(DCR9, phy_data); /* MII Clock Low */
1890 udelay(1);
1891 }
1892
1893
1894 /*
1895 * Read one bit phy data from PHY controller
1896 */
1897
1898 static u16 dmfe_phy_read_1bit(void __iomem *ioaddr)
1899 {
1900 u16 phy_data;
1901
1902 dw32(DCR9, 0x50000);
1903 udelay(1);
1904 phy_data = (dr32(DCR9) >> 19) & 0x1;
1905 dw32(DCR9, 0x40000);
1906 udelay(1);
1907
1908 return phy_data;
1909 }
1910
1911
1912 /*
1913 * Parser SROM and media mode
1914 */
1915
1916 static void dmfe_parse_srom(struct dmfe_board_info * db)
1917 {
1918 char * srom = db->srom;
1919 int dmfe_mode, tmp_reg;
1920
1921 DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
1922
1923 /* Init CR15 */
1924 db->cr15_data = CR15_DEFAULT;
1925
1926 /* Check SROM Version */
1927 if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
1928 /* SROM V4.01 */
1929 /* Get NIC support media mode */
1930 db->NIC_capability = le16_to_cpup((__le16 *) (srom + 34));
1931 db->PHY_reg4 = 0;
1932 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1933 switch( db->NIC_capability & tmp_reg ) {
1934 case 0x1: db->PHY_reg4 |= 0x0020; break;
1935 case 0x2: db->PHY_reg4 |= 0x0040; break;
1936 case 0x4: db->PHY_reg4 |= 0x0080; break;
1937 case 0x8: db->PHY_reg4 |= 0x0100; break;
1938 }
1939 }
1940
1941 /* Media Mode Force or not check */
1942 dmfe_mode = (le32_to_cpup((__le32 *) (srom + 34)) &
1943 le32_to_cpup((__le32 *) (srom + 36)));
1944 switch(dmfe_mode) {
1945 case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
1946 case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
1947 case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
1948 case 0x100:
1949 case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
1950 }
1951
1952 /* Special Function setting */
1953 /* VLAN function */
1954 if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
1955 db->cr15_data |= 0x40;
1956
1957 /* Flow Control */
1958 if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
1959 db->cr15_data |= 0x400;
1960
1961 /* TX pause packet */
1962 if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
1963 db->cr15_data |= 0x9800;
1964 }
1965
1966 /* Parse HPNA parameter */
1967 db->HPNA_command = 1;
1968
1969 /* Accept remote command or not */
1970 if (HPNA_rx_cmd == 0)
1971 db->HPNA_command |= 0x8000;
1972
1973 /* Issue remote command & operation mode */
1974 if (HPNA_tx_cmd == 1)
1975 switch(HPNA_mode) { /* Issue Remote Command */
1976 case 0: db->HPNA_command |= 0x0904; break;
1977 case 1: db->HPNA_command |= 0x0a00; break;
1978 case 2: db->HPNA_command |= 0x0506; break;
1979 case 3: db->HPNA_command |= 0x0602; break;
1980 }
1981 else
1982 switch(HPNA_mode) { /* Don't Issue */
1983 case 0: db->HPNA_command |= 0x0004; break;
1984 case 1: db->HPNA_command |= 0x0000; break;
1985 case 2: db->HPNA_command |= 0x0006; break;
1986 case 3: db->HPNA_command |= 0x0002; break;
1987 }
1988
1989 /* Check DM9801 or DM9802 present or not */
1990 db->HPNA_present = 0;
1991 update_cr6(db->cr6_data | 0x40000, db->ioaddr);
1992 tmp_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1993 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
1994 /* DM9801 or DM9802 present */
1995 db->HPNA_timer = 8;
1996 if ( dmfe_phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
1997 /* DM9801 HomeRun */
1998 db->HPNA_present = 1;
1999 dmfe_program_DM9801(db, tmp_reg);
2000 } else {
2001 /* DM9802 LongRun */
2002 db->HPNA_present = 2;
2003 dmfe_program_DM9802(db);
2004 }
2005 }
2006
2007 }
2008
2009
2010 /*
2011 * Init HomeRun DM9801
2012 */
2013
2014 static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
2015 {
2016 uint reg17, reg25;
2017
2018 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
2019 switch(HPNA_rev) {
2020 case 0xb900: /* DM9801 E3 */
2021 db->HPNA_command |= 0x1000;
2022 reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
2023 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
2024 reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2025 break;
2026 case 0xb901: /* DM9801 E4 */
2027 reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2028 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
2029 reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2030 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
2031 break;
2032 case 0xb902: /* DM9801 E5 */
2033 case 0xb903: /* DM9801 E6 */
2034 default:
2035 db->HPNA_command |= 0x1000;
2036 reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2037 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
2038 reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2039 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
2040 break;
2041 }
2042 dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2043 dmfe_phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
2044 dmfe_phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
2045 }
2046
2047
2048 /*
2049 * Init HomeRun DM9802
2050 */
2051
2052 static void dmfe_program_DM9802(struct dmfe_board_info * db)
2053 {
2054 uint phy_reg;
2055
2056 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
2057 dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2058 phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2059 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
2060 dmfe_phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
2061 }
2062
2063
2064 /*
2065 * Check remote HPNA power and speed status. If not correct,
2066 * issue command again.
2067 */
2068
2069 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
2070 {
2071 uint phy_reg;
2072
2073 /* Got remote device status */
2074 phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
2075 switch(phy_reg) {
2076 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
2077 case 0x20: phy_reg = 0x0900;break; /* LP/HS */
2078 case 0x40: phy_reg = 0x0600;break; /* HP/LS */
2079 case 0x60: phy_reg = 0x0500;break; /* HP/HS */
2080 }
2081
2082 /* Check remote device status match our setting ot not */
2083 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
2084 dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
2085 db->chip_id);
2086 db->HPNA_timer=8;
2087 } else
2088 db->HPNA_timer=600; /* Match, every 10 minutes, check */
2089 }
2090
2091
2092
2093 static const struct pci_device_id dmfe_pci_tbl[] = {
2094 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
2095 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
2096 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
2097 { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
2098 { 0, }
2099 };
2100 MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
2101
2102
2103 #ifdef CONFIG_PM
2104 static int dmfe_suspend(struct pci_dev *pci_dev, pm_message_t state)
2105 {
2106 struct net_device *dev = pci_get_drvdata(pci_dev);
2107 struct dmfe_board_info *db = netdev_priv(dev);
2108 void __iomem *ioaddr = db->ioaddr;
2109 u32 tmp;
2110
2111 /* Disable upper layer interface */
2112 netif_device_detach(dev);
2113
2114 /* Disable Tx/Rx */
2115 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);
2116 update_cr6(db->cr6_data, ioaddr);
2117
2118 /* Disable Interrupt */
2119 dw32(DCR7, 0);
2120 dw32(DCR5, dr32(DCR5));
2121
2122 /* Fre RX buffers */
2123 dmfe_free_rxbuffer(db);
2124
2125 /* Enable WOL */
2126 pci_read_config_dword(pci_dev, 0x40, &tmp);
2127 tmp &= ~(DMFE_WOL_LINKCHANGE|DMFE_WOL_MAGICPACKET);
2128
2129 if (db->wol_mode & WAKE_PHY)
2130 tmp |= DMFE_WOL_LINKCHANGE;
2131 if (db->wol_mode & WAKE_MAGIC)
2132 tmp |= DMFE_WOL_MAGICPACKET;
2133
2134 pci_write_config_dword(pci_dev, 0x40, tmp);
2135
2136 pci_enable_wake(pci_dev, PCI_D3hot, 1);
2137 pci_enable_wake(pci_dev, PCI_D3cold, 1);
2138
2139 /* Power down device*/
2140 pci_save_state(pci_dev);
2141 pci_set_power_state(pci_dev, pci_choose_state (pci_dev, state));
2142
2143 return 0;
2144 }
2145
2146 static int dmfe_resume(struct pci_dev *pci_dev)
2147 {
2148 struct net_device *dev = pci_get_drvdata(pci_dev);
2149 u32 tmp;
2150
2151 pci_set_power_state(pci_dev, PCI_D0);
2152 pci_restore_state(pci_dev);
2153
2154 /* Re-initialize DM910X board */
2155 dmfe_init_dm910x(dev);
2156
2157 /* Disable WOL */
2158 pci_read_config_dword(pci_dev, 0x40, &tmp);
2159
2160 tmp &= ~(DMFE_WOL_LINKCHANGE | DMFE_WOL_MAGICPACKET);
2161 pci_write_config_dword(pci_dev, 0x40, tmp);
2162
2163 pci_enable_wake(pci_dev, PCI_D3hot, 0);
2164 pci_enable_wake(pci_dev, PCI_D3cold, 0);
2165
2166 /* Restart upper layer interface */
2167 netif_device_attach(dev);
2168
2169 return 0;
2170 }
2171 #else
2172 #define dmfe_suspend NULL
2173 #define dmfe_resume NULL
2174 #endif
2175
2176 static struct pci_driver dmfe_driver = {
2177 .name = "dmfe",
2178 .id_table = dmfe_pci_tbl,
2179 .probe = dmfe_init_one,
2180 .remove = dmfe_remove_one,
2181 .suspend = dmfe_suspend,
2182 .resume = dmfe_resume
2183 };
2184
2185 MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
2186 MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
2187 MODULE_LICENSE("GPL");
2188 MODULE_VERSION(DRV_VERSION);
2189
2190 module_param(debug, int, 0);
2191 module_param(mode, byte, 0);
2192 module_param(cr6set, int, 0);
2193 module_param(chkmode, byte, 0);
2194 module_param(HPNA_mode, byte, 0);
2195 module_param(HPNA_rx_cmd, byte, 0);
2196 module_param(HPNA_tx_cmd, byte, 0);
2197 module_param(HPNA_NoiseFloor, byte, 0);
2198 module_param(SF_mode, byte, 0);
2199 MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
2200 MODULE_PARM_DESC(mode, "Davicom DM9xxx: "
2201 "Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2202
2203 MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function "
2204 "(bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
2205
2206 /* Description:
2207 * when user used insmod to add module, system invoked init_module()
2208 * to initialize and register.
2209 */
2210
2211 static int __init dmfe_init_module(void)
2212 {
2213 int rc;
2214
2215 pr_info("%s\n", version);
2216 printed_version = 1;
2217
2218 DMFE_DBUG(0, "init_module() ", debug);
2219
2220 if (debug)
2221 dmfe_debug = debug; /* set debug flag */
2222 if (cr6set)
2223 dmfe_cr6_user_set = cr6set;
2224
2225 switch(mode) {
2226 case DMFE_10MHF:
2227 case DMFE_100MHF:
2228 case DMFE_10MFD:
2229 case DMFE_100MFD:
2230 case DMFE_1M_HPNA:
2231 dmfe_media_mode = mode;
2232 break;
2233 default:dmfe_media_mode = DMFE_AUTO;
2234 break;
2235 }
2236
2237 if (HPNA_mode > 4)
2238 HPNA_mode = 0; /* Default: LP/HS */
2239 if (HPNA_rx_cmd > 1)
2240 HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
2241 if (HPNA_tx_cmd > 1)
2242 HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
2243 if (HPNA_NoiseFloor > 15)
2244 HPNA_NoiseFloor = 0;
2245
2246 rc = pci_register_driver(&dmfe_driver);
2247 if (rc < 0)
2248 return rc;
2249
2250 return 0;
2251 }
2252
2253
2254 /*
2255 * Description:
2256 * when user used rmmod to delete module, system invoked clean_module()
2257 * to un-register all registered services.
2258 */
2259
2260 static void __exit dmfe_cleanup_module(void)
2261 {
2262 DMFE_DBUG(0, "dmfe_cleanup_module() ", debug);
2263 pci_unregister_driver(&dmfe_driver);
2264 }
2265
2266 module_init(dmfe_init_module);
2267 module_exit(dmfe_cleanup_module);
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