drivers/net/ethernet/dnet.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Dave DNET Ethernet Controller driver
   4  *
   5  * Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
   6  */
   7 #ifndef _DNET_H
   8 #define _DNET_H
   9
  10 #define DRV_NAME                "dnet"
  11 #define DRV_VERSION             "0.9.1"
  12 #define PFX                             DRV_NAME ": "
  13
  14 /* Register access macros */
  15 #define dnet_writel(port, value, reg)   \
  16         writel((value), (port)->regs + DNET_##reg)
  17 #define dnet_readl(port, reg)   readl((port)->regs + DNET_##reg)
  18
  19 /* ALL DNET FIFO REGISTERS */
  20 #define DNET_RX_LEN_FIFO                0x000   /* RX_LEN_FIFO */
  21 #define DNET_RX_DATA_FIFO               0x004   /* RX_DATA_FIFO */
  22 #define DNET_TX_LEN_FIFO                0x008   /* TX_LEN_FIFO */
  23 #define DNET_TX_DATA_FIFO               0x00C   /* TX_DATA_FIFO */
  24
  25 /* ALL DNET CONTROL/STATUS REGISTERS OFFSETS */
  26 #define DNET_VERCAPS                    0x100   /* VERCAPS */
  27 #define DNET_INTR_SRC                   0x104   /* INTR_SRC */
  28 #define DNET_INTR_ENB                   0x108   /* INTR_ENB */
  29 #define DNET_RX_STATUS                  0x10C   /* RX_STATUS */
  30 #define DNET_TX_STATUS                  0x110   /* TX_STATUS */
  31 #define DNET_RX_FRAMES_CNT              0x114   /* RX_FRAMES_CNT */
  32 #define DNET_TX_FRAMES_CNT              0x118   /* TX_FRAMES_CNT */
  33 #define DNET_RX_FIFO_TH                 0x11C   /* RX_FIFO_TH */
  34 #define DNET_TX_FIFO_TH                 0x120   /* TX_FIFO_TH */
  35 #define DNET_SYS_CTL                    0x124   /* SYS_CTL */
  36 #define DNET_PAUSE_TMR                  0x128   /* PAUSE_TMR */
  37 #define DNET_RX_FIFO_WCNT               0x12C   /* RX_FIFO_WCNT */
  38 #define DNET_TX_FIFO_WCNT               0x130   /* TX_FIFO_WCNT */
  39
  40 /* ALL DNET MAC REGISTERS */
  41 #define DNET_MACREG_DATA                0x200   /* Mac-Reg Data */
  42 #define DNET_MACREG_ADDR                0x204   /* Mac-Reg Addr  */
  43
  44 /* ALL DNET RX STATISTICS COUNTERS  */
  45 #define DNET_RX_PKT_IGNR_CNT            0x300
  46 #define DNET_RX_LEN_CHK_ERR_CNT         0x304
  47 #define DNET_RX_LNG_FRM_CNT             0x308
  48 #define DNET_RX_SHRT_FRM_CNT            0x30C
  49 #define DNET_RX_IPG_VIOL_CNT            0x310
  50 #define DNET_RX_CRC_ERR_CNT             0x314
  51 #define DNET_RX_OK_PKT_CNT              0x318
  52 #define DNET_RX_CTL_FRM_CNT             0x31C
  53 #define DNET_RX_PAUSE_FRM_CNT           0x320
  54 #define DNET_RX_MULTICAST_CNT           0x324
  55 #define DNET_RX_BROADCAST_CNT           0x328
  56 #define DNET_RX_VLAN_TAG_CNT            0x32C
  57 #define DNET_RX_PRE_SHRINK_CNT          0x330
  58 #define DNET_RX_DRIB_NIB_CNT            0x334
  59 #define DNET_RX_UNSUP_OPCD_CNT          0x338
  60 #define DNET_RX_BYTE_CNT                0x33C
  61
  62 /* DNET TX STATISTICS COUNTERS */
  63 #define DNET_TX_UNICAST_CNT             0x400
  64 #define DNET_TX_PAUSE_FRM_CNT           0x404
  65 #define DNET_TX_MULTICAST_CNT           0x408
  66 #define DNET_TX_BRDCAST_CNT             0x40C
  67 #define DNET_TX_VLAN_TAG_CNT            0x410
  68 #define DNET_TX_BAD_FCS_CNT             0x414
  69 #define DNET_TX_JUMBO_CNT               0x418
  70 #define DNET_TX_BYTE_CNT                0x41C
  71
  72 /* SOME INTERNAL MAC-CORE REGISTER */
  73 #define DNET_INTERNAL_MODE_REG          0x0
  74 #define DNET_INTERNAL_RXTX_CONTROL_REG  0x2
  75 #define DNET_INTERNAL_MAX_PKT_SIZE_REG  0x4
  76 #define DNET_INTERNAL_IGP_REG           0x8
  77 #define DNET_INTERNAL_MAC_ADDR_0_REG    0xa
  78 #define DNET_INTERNAL_MAC_ADDR_1_REG    0xc
  79 #define DNET_INTERNAL_MAC_ADDR_2_REG    0xe
  80 #define DNET_INTERNAL_TX_RX_STS_REG     0x12
  81 #define DNET_INTERNAL_GMII_MNG_CTL_REG  0x14
  82 #define DNET_INTERNAL_GMII_MNG_DAT_REG  0x16
  83
  84 #define DNET_INTERNAL_GMII_MNG_CMD_FIN  (1 << 14)
  85
  86 #define DNET_INTERNAL_WRITE             (1 << 31)
  87
  88 /* MAC-CORE REGISTER FIELDS */
  89
  90 /* MAC-CORE MODE REGISTER FIELDS */
  91 #define DNET_INTERNAL_MODE_GBITEN                       (1 << 0)
  92 #define DNET_INTERNAL_MODE_FCEN                         (1 << 1)
  93 #define DNET_INTERNAL_MODE_RXEN                         (1 << 2)
  94 #define DNET_INTERNAL_MODE_TXEN                         (1 << 3)
  95
  96 /* MAC-CORE RXTX CONTROL REGISTER FIELDS */
  97 #define DNET_INTERNAL_RXTX_CONTROL_RXSHORTFRAME         (1 << 8)
  98 #define DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST          (1 << 7)
  99 #define DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST          (1 << 4)
 100 #define DNET_INTERNAL_RXTX_CONTROL_RXPAUSE              (1 << 3)
 101 #define DNET_INTERNAL_RXTX_CONTROL_DISTXFCS             (1 << 2)
 102 #define DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS            (1 << 1)
 103 #define DNET_INTERNAL_RXTX_CONTROL_ENPROMISC            (1 << 0)
 104 #define DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL          (1 << 6)
 105 #define DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP        (1 << 5)
 106
 107 /* SYSTEM CONTROL REGISTER FIELDS */
 108 #define DNET_SYS_CTL_IGNORENEXTPKT                      (1 << 0)
 109 #define DNET_SYS_CTL_SENDPAUSE                          (1 << 2)
 110 #define DNET_SYS_CTL_RXFIFOFLUSH                        (1 << 3)
 111 #define DNET_SYS_CTL_TXFIFOFLUSH                        (1 << 4)
 112
 113 /* TX STATUS REGISTER FIELDS */
 114 #define DNET_TX_STATUS_FIFO_ALMOST_EMPTY                (1 << 2)
 115 #define DNET_TX_STATUS_FIFO_ALMOST_FULL                 (1 << 1)
 116
 117 /* INTERRUPT SOURCE REGISTER FIELDS */
 118 #define DNET_INTR_SRC_TX_PKTSENT                        (1 << 0)
 119 #define DNET_INTR_SRC_TX_FIFOAF                         (1 << 1)
 120 #define DNET_INTR_SRC_TX_FIFOAE                         (1 << 2)
 121 #define DNET_INTR_SRC_TX_DISCFRM                        (1 << 3)
 122 #define DNET_INTR_SRC_TX_FIFOFULL                       (1 << 4)
 123 #define DNET_INTR_SRC_RX_CMDFIFOAF                      (1 << 8)
 124 #define DNET_INTR_SRC_RX_CMDFIFOFF                      (1 << 9)
 125 #define DNET_INTR_SRC_RX_DATAFIFOFF                     (1 << 10)
 126 #define DNET_INTR_SRC_TX_SUMMARY                        (1 << 16)
 127 #define DNET_INTR_SRC_RX_SUMMARY                        (1 << 17)
 128 #define DNET_INTR_SRC_PHY                               (1 << 19)
 129
 130 /* INTERRUPT ENABLE REGISTER FIELDS */
 131 #define DNET_INTR_ENB_TX_PKTSENT                        (1 << 0)
 132 #define DNET_INTR_ENB_TX_FIFOAF                         (1 << 1)
 133 #define DNET_INTR_ENB_TX_FIFOAE                         (1 << 2)
 134 #define DNET_INTR_ENB_TX_DISCFRM                        (1 << 3)
 135 #define DNET_INTR_ENB_TX_FIFOFULL                       (1 << 4)
 136 #define DNET_INTR_ENB_RX_PKTRDY                         (1 << 8)
 137 #define DNET_INTR_ENB_RX_FIFOAF                         (1 << 9)
 138 #define DNET_INTR_ENB_RX_FIFOERR                        (1 << 10)
 139 #define DNET_INTR_ENB_RX_ERROR                          (1 << 11)
 140 #define DNET_INTR_ENB_RX_FIFOFULL                       (1 << 12)
 141 #define DNET_INTR_ENB_RX_FIFOAE                         (1 << 13)
 142 #define DNET_INTR_ENB_TX_SUMMARY                        (1 << 16)
 143 #define DNET_INTR_ENB_RX_SUMMARY                        (1 << 17)
 144 #define DNET_INTR_ENB_GLOBAL_ENABLE                     (1 << 18)
 145
 146 /* default values:
 147  * almost empty = less than one full sized ethernet frame (no jumbo) inside
 148  * the fifo almost full = can write less than one full sized ethernet frame
 149  * (no jumbo) inside the fifo
 150  */
 151 #define DNET_CFG_TX_FIFO_FULL_THRES     25
 152 #define DNET_CFG_RX_FIFO_FULL_THRES     20
 153
 154 /*
 155  * Capabilities. Used by the driver to know the capabilities that the ethernet
 156  * controller inside the FPGA have.
 157  */
 158
 159 #define DNET_HAS_MDIO           (1 << 0)
 160 #define DNET_HAS_IRQ            (1 << 1)
 161 #define DNET_HAS_GIGABIT        (1 << 2)
 162 #define DNET_HAS_DMA            (1 << 3)
 163
 164 #define DNET_HAS_MII            (1 << 4) /* or GMII */
 165 #define DNET_HAS_RMII           (1 << 5) /* or RGMII */
 166
 167 #define DNET_CAPS_MASK          0xFFFF
 168
 169 #define DNET_FIFO_SIZE          1024 /* 1K x 32 bit */
 170 #define DNET_FIFO_TX_DATA_AF_TH (DNET_FIFO_SIZE - 384) /* 384 = 1536 / 4 */
 171 #define DNET_FIFO_TX_DATA_AE_TH 384
 172
 173 #define DNET_FIFO_RX_CMD_AF_TH  (1 << 16) /* just one frame inside the FIFO */
 174
 175 /*
 176  * Hardware-collected statistics.
 177  */
 178 struct dnet_stats {
 179         u32 rx_pkt_ignr;
 180         u32 rx_len_chk_err;
 181         u32 rx_lng_frm;
 182         u32 rx_shrt_frm;
 183         u32 rx_ipg_viol;
 184         u32 rx_crc_err;
 185         u32 rx_ok_pkt;
 186         u32 rx_ctl_frm;
 187         u32 rx_pause_frm;
 188         u32 rx_multicast;
 189         u32 rx_broadcast;
 190         u32 rx_vlan_tag;
 191         u32 rx_pre_shrink;
 192         u32 rx_drib_nib;
 193         u32 rx_unsup_opcd;
 194         u32 rx_byte;
 195         u32 tx_unicast;
 196         u32 tx_pause_frm;
 197         u32 tx_multicast;
 198         u32 tx_brdcast;
 199         u32 tx_vlan_tag;
 200         u32 tx_bad_fcs;
 201         u32 tx_jumbo;
 202         u32 tx_byte;
 203 };
 204
 205 struct dnet {
 206         void __iomem                    *regs;
 207         spinlock_t                      lock;
 208         struct platform_device          *pdev;
 209         struct net_device               *dev;
 210         struct dnet_stats               hw_stats;
 211         unsigned int                    capabilities; /* read from FPGA */
 212         struct napi_struct              napi;
 213
 214         /* PHY stuff */
 215         struct mii_bus                  *mii_bus;
 216         unsigned int                    link;
 217         unsigned int                    speed;
 218         unsigned int                    duplex;
 219 };
 220
 221 #endif /* _DNET_H */