2 * Copyright (C) 2005 - 2013 Emulex
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@emulex.com
15 * Costa Mesa, CA 92626
18 #include <linux/module.h>
22 static struct be_cmd_priv_map cmd_priv_map
[] = {
24 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG
,
26 BE_PRIV_LNKMGMT
| BE_PRIV_VHADM
|
27 BE_PRIV_DEVCFG
| BE_PRIV_DEVSEC
30 OPCODE_COMMON_GET_FLOW_CONTROL
,
32 BE_PRIV_LNKQUERY
| BE_PRIV_VHADM
|
33 BE_PRIV_DEVCFG
| BE_PRIV_DEVSEC
36 OPCODE_COMMON_SET_FLOW_CONTROL
,
38 BE_PRIV_LNKMGMT
| BE_PRIV_VHADM
|
39 BE_PRIV_DEVCFG
| BE_PRIV_DEVSEC
42 OPCODE_ETH_GET_PPORT_STATS
,
44 BE_PRIV_LNKMGMT
| BE_PRIV_VHADM
|
45 BE_PRIV_DEVCFG
| BE_PRIV_DEVSEC
48 OPCODE_COMMON_GET_PHY_DETAILS
,
50 BE_PRIV_LNKMGMT
| BE_PRIV_VHADM
|
51 BE_PRIV_DEVCFG
| BE_PRIV_DEVSEC
55 static bool be_cmd_allowed(struct be_adapter
*adapter
, u8 opcode
,
59 int num_entries
= sizeof(cmd_priv_map
)/sizeof(struct be_cmd_priv_map
);
60 u32 cmd_privileges
= adapter
->cmd_privileges
;
62 for (i
= 0; i
< num_entries
; i
++)
63 if (opcode
== cmd_priv_map
[i
].opcode
&&
64 subsystem
== cmd_priv_map
[i
].subsystem
)
65 if (!(cmd_privileges
& cmd_priv_map
[i
].priv_mask
))
71 static inline void *embedded_payload(struct be_mcc_wrb
*wrb
)
73 return wrb
->payload
.embedded_payload
;
76 static void be_mcc_notify(struct be_adapter
*adapter
)
78 struct be_queue_info
*mccq
= &adapter
->mcc_obj
.q
;
81 if (be_error(adapter
))
84 val
|= mccq
->id
& DB_MCCQ_RING_ID_MASK
;
85 val
|= 1 << DB_MCCQ_NUM_POSTED_SHIFT
;
88 iowrite32(val
, adapter
->db
+ DB_MCCQ_OFFSET
);
91 /* To check if valid bit is set, check the entire word as we don't know
92 * the endianness of the data (old entry is host endian while a new entry is
94 static inline bool be_mcc_compl_is_new(struct be_mcc_compl
*compl)
98 if (compl->flags
!= 0) {
99 flags
= le32_to_cpu(compl->flags
);
100 if (flags
& CQE_FLAGS_VALID_MASK
) {
101 compl->flags
= flags
;
108 /* Need to reset the entire word that houses the valid bit */
109 static inline void be_mcc_compl_use(struct be_mcc_compl
*compl)
114 static struct be_cmd_resp_hdr
*be_decode_resp_hdr(u32 tag0
, u32 tag1
)
119 addr
= ((addr
<< 16) << 16) | tag0
;
123 static int be_mcc_compl_process(struct be_adapter
*adapter
,
124 struct be_mcc_compl
*compl)
126 u16 compl_status
, extd_status
;
127 struct be_cmd_resp_hdr
*resp_hdr
;
128 u8 opcode
= 0, subsystem
= 0;
130 /* Just swap the status to host endian; mcc tag is opaquely copied
132 be_dws_le_to_cpu(compl, 4);
134 compl_status
= (compl->status
>> CQE_STATUS_COMPL_SHIFT
) &
135 CQE_STATUS_COMPL_MASK
;
137 resp_hdr
= be_decode_resp_hdr(compl->tag0
, compl->tag1
);
140 opcode
= resp_hdr
->opcode
;
141 subsystem
= resp_hdr
->subsystem
;
144 if (((opcode
== OPCODE_COMMON_WRITE_FLASHROM
) ||
145 (opcode
== OPCODE_COMMON_WRITE_OBJECT
)) &&
146 (subsystem
== CMD_SUBSYSTEM_COMMON
)) {
147 adapter
->flash_status
= compl_status
;
148 complete(&adapter
->flash_compl
);
151 if (compl_status
== MCC_STATUS_SUCCESS
) {
152 if (((opcode
== OPCODE_ETH_GET_STATISTICS
) ||
153 (opcode
== OPCODE_ETH_GET_PPORT_STATS
)) &&
154 (subsystem
== CMD_SUBSYSTEM_ETH
)) {
155 be_parse_stats(adapter
);
156 adapter
->stats_cmd_sent
= false;
158 if (opcode
== OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES
&&
159 subsystem
== CMD_SUBSYSTEM_COMMON
) {
160 struct be_cmd_resp_get_cntl_addnl_attribs
*resp
=
162 adapter
->drv_stats
.be_on_die_temperature
=
163 resp
->on_die_temperature
;
166 if (opcode
== OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES
)
167 adapter
->be_get_temp_freq
= 0;
169 if (compl_status
== MCC_STATUS_NOT_SUPPORTED
||
170 compl_status
== MCC_STATUS_ILLEGAL_REQUEST
)
173 if (compl_status
== MCC_STATUS_UNAUTHORIZED_REQUEST
) {
174 dev_warn(&adapter
->pdev
->dev
,
175 "VF is not privileged to issue opcode %d-%d\n",
178 extd_status
= (compl->status
>> CQE_STATUS_EXTD_SHIFT
) &
179 CQE_STATUS_EXTD_MASK
;
180 dev_err(&adapter
->pdev
->dev
,
181 "opcode %d-%d failed:status %d-%d\n",
182 opcode
, subsystem
, compl_status
, extd_status
);
189 /* Link state evt is a string of bytes; no need for endian swapping */
190 static void be_async_link_state_process(struct be_adapter
*adapter
,
191 struct be_async_event_link_state
*evt
)
193 /* When link status changes, link speed must be re-queried from FW */
194 adapter
->phy
.link_speed
= -1;
196 /* Ignore physical link event */
197 if (lancer_chip(adapter
) &&
198 !(evt
->port_link_status
& LOGICAL_LINK_STATUS_MASK
))
201 /* For the initial link status do not rely on the ASYNC event as
202 * it may not be received in some cases.
204 if (adapter
->flags
& BE_FLAGS_LINK_STATUS_INIT
)
205 be_link_status_update(adapter
, evt
->port_link_status
);
208 /* Grp5 CoS Priority evt */
209 static void be_async_grp5_cos_priority_process(struct be_adapter
*adapter
,
210 struct be_async_event_grp5_cos_priority
*evt
)
213 adapter
->vlan_prio_bmap
= evt
->available_priority_bmap
;
214 adapter
->recommended_prio
&= ~VLAN_PRIO_MASK
;
215 adapter
->recommended_prio
=
216 evt
->reco_default_priority
<< VLAN_PRIO_SHIFT
;
220 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
221 static void be_async_grp5_qos_speed_process(struct be_adapter
*adapter
,
222 struct be_async_event_grp5_qos_link_speed
*evt
)
224 if (adapter
->phy
.link_speed
>= 0 &&
225 evt
->physical_port
== adapter
->port_num
)
226 adapter
->phy
.link_speed
= le16_to_cpu(evt
->qos_link_speed
) * 10;
230 static void be_async_grp5_pvid_state_process(struct be_adapter
*adapter
,
231 struct be_async_event_grp5_pvid_state
*evt
)
234 adapter
->pvid
= le16_to_cpu(evt
->tag
) & VLAN_VID_MASK
;
239 static void be_async_grp5_evt_process(struct be_adapter
*adapter
,
240 u32 trailer
, struct be_mcc_compl
*evt
)
244 event_type
= (trailer
>> ASYNC_TRAILER_EVENT_TYPE_SHIFT
) &
245 ASYNC_TRAILER_EVENT_TYPE_MASK
;
247 switch (event_type
) {
248 case ASYNC_EVENT_COS_PRIORITY
:
249 be_async_grp5_cos_priority_process(adapter
,
250 (struct be_async_event_grp5_cos_priority
*)evt
);
252 case ASYNC_EVENT_QOS_SPEED
:
253 be_async_grp5_qos_speed_process(adapter
,
254 (struct be_async_event_grp5_qos_link_speed
*)evt
);
256 case ASYNC_EVENT_PVID_STATE
:
257 be_async_grp5_pvid_state_process(adapter
,
258 (struct be_async_event_grp5_pvid_state
*)evt
);
261 dev_warn(&adapter
->pdev
->dev
, "Unknown grp5 event 0x%x!\n",
267 static void be_async_dbg_evt_process(struct be_adapter
*adapter
,
268 u32 trailer
, struct be_mcc_compl
*cmp
)
271 struct be_async_event_qnq
*evt
= (struct be_async_event_qnq
*) cmp
;
273 event_type
= (trailer
>> ASYNC_TRAILER_EVENT_TYPE_SHIFT
) &
274 ASYNC_TRAILER_EVENT_TYPE_MASK
;
276 switch (event_type
) {
277 case ASYNC_DEBUG_EVENT_TYPE_QNQ
:
279 adapter
->qnq_vid
= le16_to_cpu(evt
->vlan_tag
);
280 adapter
->flags
|= BE_FLAGS_QNQ_ASYNC_EVT_RCVD
;
283 dev_warn(&adapter
->pdev
->dev
, "Unknown debug event 0x%x!\n",
289 static inline bool is_link_state_evt(u32 trailer
)
291 return ((trailer
>> ASYNC_TRAILER_EVENT_CODE_SHIFT
) &
292 ASYNC_TRAILER_EVENT_CODE_MASK
) ==
293 ASYNC_EVENT_CODE_LINK_STATE
;
296 static inline bool is_grp5_evt(u32 trailer
)
298 return (((trailer
>> ASYNC_TRAILER_EVENT_CODE_SHIFT
) &
299 ASYNC_TRAILER_EVENT_CODE_MASK
) ==
300 ASYNC_EVENT_CODE_GRP_5
);
303 static inline bool is_dbg_evt(u32 trailer
)
305 return (((trailer
>> ASYNC_TRAILER_EVENT_CODE_SHIFT
) &
306 ASYNC_TRAILER_EVENT_CODE_MASK
) ==
307 ASYNC_EVENT_CODE_QNQ
);
310 static struct be_mcc_compl
*be_mcc_compl_get(struct be_adapter
*adapter
)
312 struct be_queue_info
*mcc_cq
= &adapter
->mcc_obj
.cq
;
313 struct be_mcc_compl
*compl = queue_tail_node(mcc_cq
);
315 if (be_mcc_compl_is_new(compl)) {
316 queue_tail_inc(mcc_cq
);
322 void be_async_mcc_enable(struct be_adapter
*adapter
)
324 spin_lock_bh(&adapter
->mcc_cq_lock
);
326 be_cq_notify(adapter
, adapter
->mcc_obj
.cq
.id
, true, 0);
327 adapter
->mcc_obj
.rearm_cq
= true;
329 spin_unlock_bh(&adapter
->mcc_cq_lock
);
332 void be_async_mcc_disable(struct be_adapter
*adapter
)
334 spin_lock_bh(&adapter
->mcc_cq_lock
);
336 adapter
->mcc_obj
.rearm_cq
= false;
337 be_cq_notify(adapter
, adapter
->mcc_obj
.cq
.id
, false, 0);
339 spin_unlock_bh(&adapter
->mcc_cq_lock
);
342 int be_process_mcc(struct be_adapter
*adapter
)
344 struct be_mcc_compl
*compl;
345 int num
= 0, status
= 0;
346 struct be_mcc_obj
*mcc_obj
= &adapter
->mcc_obj
;
348 spin_lock(&adapter
->mcc_cq_lock
);
349 while ((compl = be_mcc_compl_get(adapter
))) {
350 if (compl->flags
& CQE_FLAGS_ASYNC_MASK
) {
351 /* Interpret flags as an async trailer */
352 if (is_link_state_evt(compl->flags
))
353 be_async_link_state_process(adapter
,
354 (struct be_async_event_link_state
*) compl);
355 else if (is_grp5_evt(compl->flags
))
356 be_async_grp5_evt_process(adapter
,
357 compl->flags
, compl);
358 else if (is_dbg_evt(compl->flags
))
359 be_async_dbg_evt_process(adapter
,
360 compl->flags
, compl);
361 } else if (compl->flags
& CQE_FLAGS_COMPLETED_MASK
) {
362 status
= be_mcc_compl_process(adapter
, compl);
363 atomic_dec(&mcc_obj
->q
.used
);
365 be_mcc_compl_use(compl);
370 be_cq_notify(adapter
, mcc_obj
->cq
.id
, mcc_obj
->rearm_cq
, num
);
372 spin_unlock(&adapter
->mcc_cq_lock
);
376 /* Wait till no more pending mcc requests are present */
377 static int be_mcc_wait_compl(struct be_adapter
*adapter
)
379 #define mcc_timeout 120000 /* 12s timeout */
381 struct be_mcc_obj
*mcc_obj
= &adapter
->mcc_obj
;
383 for (i
= 0; i
< mcc_timeout
; i
++) {
384 if (be_error(adapter
))
388 status
= be_process_mcc(adapter
);
391 if (atomic_read(&mcc_obj
->q
.used
) == 0)
395 if (i
== mcc_timeout
) {
396 dev_err(&adapter
->pdev
->dev
, "FW not responding\n");
397 adapter
->fw_timeout
= true;
403 /* Notify MCC requests and wait for completion */
404 static int be_mcc_notify_wait(struct be_adapter
*adapter
)
407 struct be_mcc_wrb
*wrb
;
408 struct be_mcc_obj
*mcc_obj
= &adapter
->mcc_obj
;
409 u16 index
= mcc_obj
->q
.head
;
410 struct be_cmd_resp_hdr
*resp
;
412 index_dec(&index
, mcc_obj
->q
.len
);
413 wrb
= queue_index_node(&mcc_obj
->q
, index
);
415 resp
= be_decode_resp_hdr(wrb
->tag0
, wrb
->tag1
);
417 be_mcc_notify(adapter
);
419 status
= be_mcc_wait_compl(adapter
);
423 status
= resp
->status
;
428 static int be_mbox_db_ready_wait(struct be_adapter
*adapter
, void __iomem
*db
)
434 if (be_error(adapter
))
437 ready
= ioread32(db
);
438 if (ready
== 0xffffffff)
441 ready
&= MPU_MAILBOX_DB_RDY_MASK
;
446 dev_err(&adapter
->pdev
->dev
, "FW not responding\n");
447 adapter
->fw_timeout
= true;
448 be_detect_error(adapter
);
460 * Insert the mailbox address into the doorbell in two steps
461 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
463 static int be_mbox_notify_wait(struct be_adapter
*adapter
)
467 void __iomem
*db
= adapter
->db
+ MPU_MAILBOX_DB_OFFSET
;
468 struct be_dma_mem
*mbox_mem
= &adapter
->mbox_mem
;
469 struct be_mcc_mailbox
*mbox
= mbox_mem
->va
;
470 struct be_mcc_compl
*compl = &mbox
->compl;
472 /* wait for ready to be set */
473 status
= be_mbox_db_ready_wait(adapter
, db
);
477 val
|= MPU_MAILBOX_DB_HI_MASK
;
478 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
479 val
|= (upper_32_bits(mbox_mem
->dma
) >> 2) << 2;
482 /* wait for ready to be set */
483 status
= be_mbox_db_ready_wait(adapter
, db
);
488 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
489 val
|= (u32
)(mbox_mem
->dma
>> 4) << 2;
492 status
= be_mbox_db_ready_wait(adapter
, db
);
496 /* A cq entry has been made now */
497 if (be_mcc_compl_is_new(compl)) {
498 status
= be_mcc_compl_process(adapter
, &mbox
->compl);
499 be_mcc_compl_use(compl);
503 dev_err(&adapter
->pdev
->dev
, "invalid mailbox completion\n");
509 static u16
be_POST_stage_get(struct be_adapter
*adapter
)
513 if (BEx_chip(adapter
))
514 sem
= ioread32(adapter
->csr
+ SLIPORT_SEMAPHORE_OFFSET_BEx
);
516 pci_read_config_dword(adapter
->pdev
,
517 SLIPORT_SEMAPHORE_OFFSET_SH
, &sem
);
519 return sem
& POST_STAGE_MASK
;
522 int lancer_wait_ready(struct be_adapter
*adapter
)
524 #define SLIPORT_READY_TIMEOUT 30
528 for (i
= 0; i
< SLIPORT_READY_TIMEOUT
; i
++) {
529 sliport_status
= ioread32(adapter
->db
+ SLIPORT_STATUS_OFFSET
);
530 if (sliport_status
& SLIPORT_STATUS_RDY_MASK
)
536 if (i
== SLIPORT_READY_TIMEOUT
)
542 static bool lancer_provisioning_error(struct be_adapter
*adapter
)
544 u32 sliport_status
= 0, sliport_err1
= 0, sliport_err2
= 0;
545 sliport_status
= ioread32(adapter
->db
+ SLIPORT_STATUS_OFFSET
);
546 if (sliport_status
& SLIPORT_STATUS_ERR_MASK
) {
547 sliport_err1
= ioread32(adapter
->db
+
548 SLIPORT_ERROR1_OFFSET
);
549 sliport_err2
= ioread32(adapter
->db
+
550 SLIPORT_ERROR2_OFFSET
);
552 if (sliport_err1
== SLIPORT_ERROR_NO_RESOURCE1
&&
553 sliport_err2
== SLIPORT_ERROR_NO_RESOURCE2
)
559 int lancer_test_and_set_rdy_state(struct be_adapter
*adapter
)
562 u32 sliport_status
, err
, reset_needed
;
565 resource_error
= lancer_provisioning_error(adapter
);
569 status
= lancer_wait_ready(adapter
);
571 sliport_status
= ioread32(adapter
->db
+ SLIPORT_STATUS_OFFSET
);
572 err
= sliport_status
& SLIPORT_STATUS_ERR_MASK
;
573 reset_needed
= sliport_status
& SLIPORT_STATUS_RN_MASK
;
574 if (err
&& reset_needed
) {
575 iowrite32(SLI_PORT_CONTROL_IP_MASK
,
576 adapter
->db
+ SLIPORT_CONTROL_OFFSET
);
578 /* check adapter has corrected the error */
579 status
= lancer_wait_ready(adapter
);
580 sliport_status
= ioread32(adapter
->db
+
581 SLIPORT_STATUS_OFFSET
);
582 sliport_status
&= (SLIPORT_STATUS_ERR_MASK
|
583 SLIPORT_STATUS_RN_MASK
);
584 if (status
|| sliport_status
)
586 } else if (err
|| reset_needed
) {
590 /* Stop error recovery if error is not recoverable.
591 * No resource error is temporary errors and will go away
592 * when PF provisions resources.
594 resource_error
= lancer_provisioning_error(adapter
);
601 int be_fw_wait_ready(struct be_adapter
*adapter
)
604 int status
, timeout
= 0;
605 struct device
*dev
= &adapter
->pdev
->dev
;
607 if (lancer_chip(adapter
)) {
608 status
= lancer_wait_ready(adapter
);
613 stage
= be_POST_stage_get(adapter
);
614 if (stage
== POST_STAGE_ARMFW_RDY
)
617 dev_info(dev
, "Waiting for POST, %ds elapsed\n",
619 if (msleep_interruptible(2000)) {
620 dev_err(dev
, "Waiting for POST aborted\n");
624 } while (timeout
< 60);
626 dev_err(dev
, "POST timeout; stage=0x%x\n", stage
);
631 static inline struct be_sge
*nonembedded_sgl(struct be_mcc_wrb
*wrb
)
633 return &wrb
->payload
.sgl
[0];
637 /* Don't touch the hdr after it's prepared */
638 /* mem will be NULL for embedded commands */
639 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr
*req_hdr
,
640 u8 subsystem
, u8 opcode
, int cmd_len
,
641 struct be_mcc_wrb
*wrb
, struct be_dma_mem
*mem
)
644 unsigned long addr
= (unsigned long)req_hdr
;
647 req_hdr
->opcode
= opcode
;
648 req_hdr
->subsystem
= subsystem
;
649 req_hdr
->request_length
= cpu_to_le32(cmd_len
- sizeof(*req_hdr
));
650 req_hdr
->version
= 0;
652 wrb
->tag0
= req_addr
& 0xFFFFFFFF;
653 wrb
->tag1
= upper_32_bits(req_addr
);
655 wrb
->payload_length
= cmd_len
;
657 wrb
->embedded
|= (1 & MCC_WRB_SGE_CNT_MASK
) <<
658 MCC_WRB_SGE_CNT_SHIFT
;
659 sge
= nonembedded_sgl(wrb
);
660 sge
->pa_hi
= cpu_to_le32(upper_32_bits(mem
->dma
));
661 sge
->pa_lo
= cpu_to_le32(mem
->dma
& 0xFFFFFFFF);
662 sge
->len
= cpu_to_le32(mem
->size
);
664 wrb
->embedded
|= MCC_WRB_EMBEDDED_MASK
;
665 be_dws_cpu_to_le(wrb
, 8);
668 static void be_cmd_page_addrs_prepare(struct phys_addr
*pages
, u32 max_pages
,
669 struct be_dma_mem
*mem
)
671 int i
, buf_pages
= min(PAGES_4K_SPANNED(mem
->va
, mem
->size
), max_pages
);
672 u64 dma
= (u64
)mem
->dma
;
674 for (i
= 0; i
< buf_pages
; i
++) {
675 pages
[i
].lo
= cpu_to_le32(dma
& 0xFFFFFFFF);
676 pages
[i
].hi
= cpu_to_le32(upper_32_bits(dma
));
681 /* Converts interrupt delay in microseconds to multiplier value */
682 static u32
eq_delay_to_mult(u32 usec_delay
)
684 #define MAX_INTR_RATE 651042
685 const u32 round
= 10;
691 u32 interrupt_rate
= 1000000 / usec_delay
;
692 /* Max delay, corresponding to the lowest interrupt rate */
693 if (interrupt_rate
== 0)
696 multiplier
= (MAX_INTR_RATE
- interrupt_rate
) * round
;
697 multiplier
/= interrupt_rate
;
698 /* Round the multiplier to the closest value.*/
699 multiplier
= (multiplier
+ round
/2) / round
;
700 multiplier
= min(multiplier
, (u32
)1023);
706 static inline struct be_mcc_wrb
*wrb_from_mbox(struct be_adapter
*adapter
)
708 struct be_dma_mem
*mbox_mem
= &adapter
->mbox_mem
;
709 struct be_mcc_wrb
*wrb
710 = &((struct be_mcc_mailbox
*)(mbox_mem
->va
))->wrb
;
711 memset(wrb
, 0, sizeof(*wrb
));
715 static struct be_mcc_wrb
*wrb_from_mccq(struct be_adapter
*adapter
)
717 struct be_queue_info
*mccq
= &adapter
->mcc_obj
.q
;
718 struct be_mcc_wrb
*wrb
;
723 if (atomic_read(&mccq
->used
) >= mccq
->len
)
726 wrb
= queue_head_node(mccq
);
727 queue_head_inc(mccq
);
728 atomic_inc(&mccq
->used
);
729 memset(wrb
, 0, sizeof(*wrb
));
733 /* Tell fw we're about to start firing cmds by writing a
734 * special pattern across the wrb hdr; uses mbox
736 int be_cmd_fw_init(struct be_adapter
*adapter
)
741 if (lancer_chip(adapter
))
744 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
747 wrb
= (u8
*)wrb_from_mbox(adapter
);
757 status
= be_mbox_notify_wait(adapter
);
759 mutex_unlock(&adapter
->mbox_lock
);
763 /* Tell fw we're done with firing cmds by writing a
764 * special pattern across the wrb hdr; uses mbox
766 int be_cmd_fw_clean(struct be_adapter
*adapter
)
771 if (lancer_chip(adapter
))
774 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
777 wrb
= (u8
*)wrb_from_mbox(adapter
);
787 status
= be_mbox_notify_wait(adapter
);
789 mutex_unlock(&adapter
->mbox_lock
);
793 int be_cmd_eq_create(struct be_adapter
*adapter
,
794 struct be_queue_info
*eq
, int eq_delay
)
796 struct be_mcc_wrb
*wrb
;
797 struct be_cmd_req_eq_create
*req
;
798 struct be_dma_mem
*q_mem
= &eq
->dma_mem
;
801 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
804 wrb
= wrb_from_mbox(adapter
);
805 req
= embedded_payload(wrb
);
807 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
808 OPCODE_COMMON_EQ_CREATE
, sizeof(*req
), wrb
, NULL
);
810 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
812 AMAP_SET_BITS(struct amap_eq_context
, valid
, req
->context
, 1);
814 AMAP_SET_BITS(struct amap_eq_context
, size
, req
->context
, 0);
815 AMAP_SET_BITS(struct amap_eq_context
, count
, req
->context
,
816 __ilog2_u32(eq
->len
/256));
817 AMAP_SET_BITS(struct amap_eq_context
, delaymult
, req
->context
,
818 eq_delay_to_mult(eq_delay
));
819 be_dws_cpu_to_le(req
->context
, sizeof(req
->context
));
821 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
823 status
= be_mbox_notify_wait(adapter
);
825 struct be_cmd_resp_eq_create
*resp
= embedded_payload(wrb
);
826 eq
->id
= le16_to_cpu(resp
->eq_id
);
830 mutex_unlock(&adapter
->mbox_lock
);
835 int be_cmd_mac_addr_query(struct be_adapter
*adapter
, u8
*mac_addr
,
836 bool permanent
, u32 if_handle
, u32 pmac_id
)
838 struct be_mcc_wrb
*wrb
;
839 struct be_cmd_req_mac_query
*req
;
842 spin_lock_bh(&adapter
->mcc_lock
);
844 wrb
= wrb_from_mccq(adapter
);
849 req
= embedded_payload(wrb
);
851 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
852 OPCODE_COMMON_NTWK_MAC_QUERY
, sizeof(*req
), wrb
, NULL
);
853 req
->type
= MAC_ADDRESS_TYPE_NETWORK
;
857 req
->if_id
= cpu_to_le16((u16
) if_handle
);
858 req
->pmac_id
= cpu_to_le32(pmac_id
);
862 status
= be_mcc_notify_wait(adapter
);
864 struct be_cmd_resp_mac_query
*resp
= embedded_payload(wrb
);
865 memcpy(mac_addr
, resp
->mac
.addr
, ETH_ALEN
);
869 spin_unlock_bh(&adapter
->mcc_lock
);
873 /* Uses synchronous MCCQ */
874 int be_cmd_pmac_add(struct be_adapter
*adapter
, u8
*mac_addr
,
875 u32 if_id
, u32
*pmac_id
, u32 domain
)
877 struct be_mcc_wrb
*wrb
;
878 struct be_cmd_req_pmac_add
*req
;
881 spin_lock_bh(&adapter
->mcc_lock
);
883 wrb
= wrb_from_mccq(adapter
);
888 req
= embedded_payload(wrb
);
890 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
891 OPCODE_COMMON_NTWK_PMAC_ADD
, sizeof(*req
), wrb
, NULL
);
893 req
->hdr
.domain
= domain
;
894 req
->if_id
= cpu_to_le32(if_id
);
895 memcpy(req
->mac_address
, mac_addr
, ETH_ALEN
);
897 status
= be_mcc_notify_wait(adapter
);
899 struct be_cmd_resp_pmac_add
*resp
= embedded_payload(wrb
);
900 *pmac_id
= le32_to_cpu(resp
->pmac_id
);
904 spin_unlock_bh(&adapter
->mcc_lock
);
906 if (status
== MCC_STATUS_UNAUTHORIZED_REQUEST
)
912 /* Uses synchronous MCCQ */
913 int be_cmd_pmac_del(struct be_adapter
*adapter
, u32 if_id
, int pmac_id
, u32 dom
)
915 struct be_mcc_wrb
*wrb
;
916 struct be_cmd_req_pmac_del
*req
;
922 spin_lock_bh(&adapter
->mcc_lock
);
924 wrb
= wrb_from_mccq(adapter
);
929 req
= embedded_payload(wrb
);
931 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
932 OPCODE_COMMON_NTWK_PMAC_DEL
, sizeof(*req
), wrb
, NULL
);
934 req
->hdr
.domain
= dom
;
935 req
->if_id
= cpu_to_le32(if_id
);
936 req
->pmac_id
= cpu_to_le32(pmac_id
);
938 status
= be_mcc_notify_wait(adapter
);
941 spin_unlock_bh(&adapter
->mcc_lock
);
946 int be_cmd_cq_create(struct be_adapter
*adapter
, struct be_queue_info
*cq
,
947 struct be_queue_info
*eq
, bool no_delay
, int coalesce_wm
)
949 struct be_mcc_wrb
*wrb
;
950 struct be_cmd_req_cq_create
*req
;
951 struct be_dma_mem
*q_mem
= &cq
->dma_mem
;
955 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
958 wrb
= wrb_from_mbox(adapter
);
959 req
= embedded_payload(wrb
);
960 ctxt
= &req
->context
;
962 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
963 OPCODE_COMMON_CQ_CREATE
, sizeof(*req
), wrb
, NULL
);
965 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
967 if (BEx_chip(adapter
)) {
968 AMAP_SET_BITS(struct amap_cq_context_be
, coalescwm
, ctxt
,
970 AMAP_SET_BITS(struct amap_cq_context_be
, nodelay
,
972 AMAP_SET_BITS(struct amap_cq_context_be
, count
, ctxt
,
973 __ilog2_u32(cq
->len
/256));
974 AMAP_SET_BITS(struct amap_cq_context_be
, valid
, ctxt
, 1);
975 AMAP_SET_BITS(struct amap_cq_context_be
, eventable
, ctxt
, 1);
976 AMAP_SET_BITS(struct amap_cq_context_be
, eqid
, ctxt
, eq
->id
);
978 req
->hdr
.version
= 2;
979 req
->page_size
= 1; /* 1 for 4K */
980 AMAP_SET_BITS(struct amap_cq_context_v2
, nodelay
, ctxt
,
982 AMAP_SET_BITS(struct amap_cq_context_v2
, count
, ctxt
,
983 __ilog2_u32(cq
->len
/256));
984 AMAP_SET_BITS(struct amap_cq_context_v2
, valid
, ctxt
, 1);
985 AMAP_SET_BITS(struct amap_cq_context_v2
, eventable
,
987 AMAP_SET_BITS(struct amap_cq_context_v2
, eqid
,
991 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
993 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
995 status
= be_mbox_notify_wait(adapter
);
997 struct be_cmd_resp_cq_create
*resp
= embedded_payload(wrb
);
998 cq
->id
= le16_to_cpu(resp
->cq_id
);
1002 mutex_unlock(&adapter
->mbox_lock
);
1007 static u32
be_encoded_q_len(int q_len
)
1009 u32 len_encoded
= fls(q_len
); /* log2(len) + 1 */
1010 if (len_encoded
== 16)
1015 static int be_cmd_mccq_ext_create(struct be_adapter
*adapter
,
1016 struct be_queue_info
*mccq
,
1017 struct be_queue_info
*cq
)
1019 struct be_mcc_wrb
*wrb
;
1020 struct be_cmd_req_mcc_ext_create
*req
;
1021 struct be_dma_mem
*q_mem
= &mccq
->dma_mem
;
1025 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
1028 wrb
= wrb_from_mbox(adapter
);
1029 req
= embedded_payload(wrb
);
1030 ctxt
= &req
->context
;
1032 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1033 OPCODE_COMMON_MCC_CREATE_EXT
, sizeof(*req
), wrb
, NULL
);
1035 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
1036 if (lancer_chip(adapter
)) {
1037 req
->hdr
.version
= 1;
1038 req
->cq_id
= cpu_to_le16(cq
->id
);
1040 AMAP_SET_BITS(struct amap_mcc_context_lancer
, ring_size
, ctxt
,
1041 be_encoded_q_len(mccq
->len
));
1042 AMAP_SET_BITS(struct amap_mcc_context_lancer
, valid
, ctxt
, 1);
1043 AMAP_SET_BITS(struct amap_mcc_context_lancer
, async_cq_id
,
1045 AMAP_SET_BITS(struct amap_mcc_context_lancer
, async_cq_valid
,
1049 AMAP_SET_BITS(struct amap_mcc_context_be
, valid
, ctxt
, 1);
1050 AMAP_SET_BITS(struct amap_mcc_context_be
, ring_size
, ctxt
,
1051 be_encoded_q_len(mccq
->len
));
1052 AMAP_SET_BITS(struct amap_mcc_context_be
, cq_id
, ctxt
, cq
->id
);
1055 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
1056 req
->async_event_bitmap
[0] = cpu_to_le32(0x00000022);
1057 req
->async_event_bitmap
[0] |= cpu_to_le32(1 << ASYNC_EVENT_CODE_QNQ
);
1058 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
1060 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
1062 status
= be_mbox_notify_wait(adapter
);
1064 struct be_cmd_resp_mcc_create
*resp
= embedded_payload(wrb
);
1065 mccq
->id
= le16_to_cpu(resp
->id
);
1066 mccq
->created
= true;
1068 mutex_unlock(&adapter
->mbox_lock
);
1073 static int be_cmd_mccq_org_create(struct be_adapter
*adapter
,
1074 struct be_queue_info
*mccq
,
1075 struct be_queue_info
*cq
)
1077 struct be_mcc_wrb
*wrb
;
1078 struct be_cmd_req_mcc_create
*req
;
1079 struct be_dma_mem
*q_mem
= &mccq
->dma_mem
;
1083 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
1086 wrb
= wrb_from_mbox(adapter
);
1087 req
= embedded_payload(wrb
);
1088 ctxt
= &req
->context
;
1090 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1091 OPCODE_COMMON_MCC_CREATE
, sizeof(*req
), wrb
, NULL
);
1093 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
1095 AMAP_SET_BITS(struct amap_mcc_context_be
, valid
, ctxt
, 1);
1096 AMAP_SET_BITS(struct amap_mcc_context_be
, ring_size
, ctxt
,
1097 be_encoded_q_len(mccq
->len
));
1098 AMAP_SET_BITS(struct amap_mcc_context_be
, cq_id
, ctxt
, cq
->id
);
1100 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
1102 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
1104 status
= be_mbox_notify_wait(adapter
);
1106 struct be_cmd_resp_mcc_create
*resp
= embedded_payload(wrb
);
1107 mccq
->id
= le16_to_cpu(resp
->id
);
1108 mccq
->created
= true;
1111 mutex_unlock(&adapter
->mbox_lock
);
1115 int be_cmd_mccq_create(struct be_adapter
*adapter
,
1116 struct be_queue_info
*mccq
,
1117 struct be_queue_info
*cq
)
1121 status
= be_cmd_mccq_ext_create(adapter
, mccq
, cq
);
1122 if (status
&& !lancer_chip(adapter
)) {
1123 dev_warn(&adapter
->pdev
->dev
, "Upgrade to F/W ver 2.102.235.0 "
1124 "or newer to avoid conflicting priorities between NIC "
1125 "and FCoE traffic");
1126 status
= be_cmd_mccq_org_create(adapter
, mccq
, cq
);
1131 int be_cmd_txq_create(struct be_adapter
*adapter
, struct be_tx_obj
*txo
)
1133 struct be_mcc_wrb
*wrb
;
1134 struct be_cmd_req_eth_tx_create
*req
;
1135 struct be_queue_info
*txq
= &txo
->q
;
1136 struct be_queue_info
*cq
= &txo
->cq
;
1137 struct be_dma_mem
*q_mem
= &txq
->dma_mem
;
1138 int status
, ver
= 0;
1140 spin_lock_bh(&adapter
->mcc_lock
);
1142 wrb
= wrb_from_mccq(adapter
);
1148 req
= embedded_payload(wrb
);
1150 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
1151 OPCODE_ETH_TX_CREATE
, sizeof(*req
), wrb
, NULL
);
1153 if (lancer_chip(adapter
)) {
1154 req
->hdr
.version
= 1;
1155 req
->if_id
= cpu_to_le16(adapter
->if_handle
);
1156 } else if (BEx_chip(adapter
)) {
1157 if (adapter
->function_caps
& BE_FUNCTION_CAPS_SUPER_NIC
)
1158 req
->hdr
.version
= 2;
1159 } else { /* For SH */
1160 req
->hdr
.version
= 2;
1163 req
->num_pages
= PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
);
1164 req
->ulp_num
= BE_ULP1_NUM
;
1165 req
->type
= BE_ETH_TX_RING_TYPE_STANDARD
;
1166 req
->cq_id
= cpu_to_le16(cq
->id
);
1167 req
->queue_size
= be_encoded_q_len(txq
->len
);
1168 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
1170 ver
= req
->hdr
.version
;
1172 status
= be_mcc_notify_wait(adapter
);
1174 struct be_cmd_resp_eth_tx_create
*resp
= embedded_payload(wrb
);
1175 txq
->id
= le16_to_cpu(resp
->cid
);
1177 txo
->db_offset
= le32_to_cpu(resp
->db_offset
);
1179 txo
->db_offset
= DB_TXULP1_OFFSET
;
1180 txq
->created
= true;
1184 spin_unlock_bh(&adapter
->mcc_lock
);
1190 int be_cmd_rxq_create(struct be_adapter
*adapter
,
1191 struct be_queue_info
*rxq
, u16 cq_id
, u16 frag_size
,
1192 u32 if_id
, u32 rss
, u8
*rss_id
)
1194 struct be_mcc_wrb
*wrb
;
1195 struct be_cmd_req_eth_rx_create
*req
;
1196 struct be_dma_mem
*q_mem
= &rxq
->dma_mem
;
1199 spin_lock_bh(&adapter
->mcc_lock
);
1201 wrb
= wrb_from_mccq(adapter
);
1206 req
= embedded_payload(wrb
);
1208 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
1209 OPCODE_ETH_RX_CREATE
, sizeof(*req
), wrb
, NULL
);
1211 req
->cq_id
= cpu_to_le16(cq_id
);
1212 req
->frag_size
= fls(frag_size
) - 1;
1214 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
1215 req
->interface_id
= cpu_to_le32(if_id
);
1216 req
->max_frame_size
= cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE
);
1217 req
->rss_queue
= cpu_to_le32(rss
);
1219 status
= be_mcc_notify_wait(adapter
);
1221 struct be_cmd_resp_eth_rx_create
*resp
= embedded_payload(wrb
);
1222 rxq
->id
= le16_to_cpu(resp
->id
);
1223 rxq
->created
= true;
1224 *rss_id
= resp
->rss_id
;
1228 spin_unlock_bh(&adapter
->mcc_lock
);
1232 /* Generic destroyer function for all types of queues
1235 int be_cmd_q_destroy(struct be_adapter
*adapter
, struct be_queue_info
*q
,
1238 struct be_mcc_wrb
*wrb
;
1239 struct be_cmd_req_q_destroy
*req
;
1240 u8 subsys
= 0, opcode
= 0;
1243 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
1246 wrb
= wrb_from_mbox(adapter
);
1247 req
= embedded_payload(wrb
);
1249 switch (queue_type
) {
1251 subsys
= CMD_SUBSYSTEM_COMMON
;
1252 opcode
= OPCODE_COMMON_EQ_DESTROY
;
1255 subsys
= CMD_SUBSYSTEM_COMMON
;
1256 opcode
= OPCODE_COMMON_CQ_DESTROY
;
1259 subsys
= CMD_SUBSYSTEM_ETH
;
1260 opcode
= OPCODE_ETH_TX_DESTROY
;
1263 subsys
= CMD_SUBSYSTEM_ETH
;
1264 opcode
= OPCODE_ETH_RX_DESTROY
;
1267 subsys
= CMD_SUBSYSTEM_COMMON
;
1268 opcode
= OPCODE_COMMON_MCC_DESTROY
;
1274 be_wrb_cmd_hdr_prepare(&req
->hdr
, subsys
, opcode
, sizeof(*req
), wrb
,
1276 req
->id
= cpu_to_le16(q
->id
);
1278 status
= be_mbox_notify_wait(adapter
);
1281 mutex_unlock(&adapter
->mbox_lock
);
1286 int be_cmd_rxq_destroy(struct be_adapter
*adapter
, struct be_queue_info
*q
)
1288 struct be_mcc_wrb
*wrb
;
1289 struct be_cmd_req_q_destroy
*req
;
1292 spin_lock_bh(&adapter
->mcc_lock
);
1294 wrb
= wrb_from_mccq(adapter
);
1299 req
= embedded_payload(wrb
);
1301 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
1302 OPCODE_ETH_RX_DESTROY
, sizeof(*req
), wrb
, NULL
);
1303 req
->id
= cpu_to_le16(q
->id
);
1305 status
= be_mcc_notify_wait(adapter
);
1309 spin_unlock_bh(&adapter
->mcc_lock
);
1313 /* Create an rx filtering policy configuration on an i/f
1316 int be_cmd_if_create(struct be_adapter
*adapter
, u32 cap_flags
, u32 en_flags
,
1317 u32
*if_handle
, u32 domain
)
1319 struct be_mcc_wrb
*wrb
;
1320 struct be_cmd_req_if_create
*req
;
1323 spin_lock_bh(&adapter
->mcc_lock
);
1325 wrb
= wrb_from_mccq(adapter
);
1330 req
= embedded_payload(wrb
);
1332 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1333 OPCODE_COMMON_NTWK_INTERFACE_CREATE
, sizeof(*req
), wrb
, NULL
);
1334 req
->hdr
.domain
= domain
;
1335 req
->capability_flags
= cpu_to_le32(cap_flags
);
1336 req
->enable_flags
= cpu_to_le32(en_flags
);
1338 req
->pmac_invalid
= true;
1340 status
= be_mcc_notify_wait(adapter
);
1342 struct be_cmd_resp_if_create
*resp
= embedded_payload(wrb
);
1343 *if_handle
= le32_to_cpu(resp
->interface_id
);
1345 /* Hack to retrieve VF's pmac-id on BE3 */
1346 if (BE3_chip(adapter
) && !be_physfn(adapter
))
1347 adapter
->pmac_id
[0] = le32_to_cpu(resp
->pmac_id
);
1351 spin_unlock_bh(&adapter
->mcc_lock
);
1356 int be_cmd_if_destroy(struct be_adapter
*adapter
, int interface_id
, u32 domain
)
1358 struct be_mcc_wrb
*wrb
;
1359 struct be_cmd_req_if_destroy
*req
;
1362 if (interface_id
== -1)
1365 spin_lock_bh(&adapter
->mcc_lock
);
1367 wrb
= wrb_from_mccq(adapter
);
1372 req
= embedded_payload(wrb
);
1374 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1375 OPCODE_COMMON_NTWK_INTERFACE_DESTROY
, sizeof(*req
), wrb
, NULL
);
1376 req
->hdr
.domain
= domain
;
1377 req
->interface_id
= cpu_to_le32(interface_id
);
1379 status
= be_mcc_notify_wait(adapter
);
1381 spin_unlock_bh(&adapter
->mcc_lock
);
1385 /* Get stats is a non embedded command: the request is not embedded inside
1386 * WRB but is a separate dma memory block
1387 * Uses asynchronous MCC
1389 int be_cmd_get_stats(struct be_adapter
*adapter
, struct be_dma_mem
*nonemb_cmd
)
1391 struct be_mcc_wrb
*wrb
;
1392 struct be_cmd_req_hdr
*hdr
;
1395 spin_lock_bh(&adapter
->mcc_lock
);
1397 wrb
= wrb_from_mccq(adapter
);
1402 hdr
= nonemb_cmd
->va
;
1404 be_wrb_cmd_hdr_prepare(hdr
, CMD_SUBSYSTEM_ETH
,
1405 OPCODE_ETH_GET_STATISTICS
, nonemb_cmd
->size
, wrb
, nonemb_cmd
);
1407 /* version 1 of the cmd is not supported only by BE2 */
1408 if (!BE2_chip(adapter
))
1411 be_mcc_notify(adapter
);
1412 adapter
->stats_cmd_sent
= true;
1415 spin_unlock_bh(&adapter
->mcc_lock
);
1420 int lancer_cmd_get_pport_stats(struct be_adapter
*adapter
,
1421 struct be_dma_mem
*nonemb_cmd
)
1424 struct be_mcc_wrb
*wrb
;
1425 struct lancer_cmd_req_pport_stats
*req
;
1428 if (!be_cmd_allowed(adapter
, OPCODE_ETH_GET_PPORT_STATS
,
1432 spin_lock_bh(&adapter
->mcc_lock
);
1434 wrb
= wrb_from_mccq(adapter
);
1439 req
= nonemb_cmd
->va
;
1441 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
1442 OPCODE_ETH_GET_PPORT_STATS
, nonemb_cmd
->size
, wrb
,
1445 req
->cmd_params
.params
.pport_num
= cpu_to_le16(adapter
->hba_port_num
);
1446 req
->cmd_params
.params
.reset_stats
= 0;
1448 be_mcc_notify(adapter
);
1449 adapter
->stats_cmd_sent
= true;
1452 spin_unlock_bh(&adapter
->mcc_lock
);
1456 static int be_mac_to_link_speed(int mac_speed
)
1458 switch (mac_speed
) {
1459 case PHY_LINK_SPEED_ZERO
:
1461 case PHY_LINK_SPEED_10MBPS
:
1463 case PHY_LINK_SPEED_100MBPS
:
1465 case PHY_LINK_SPEED_1GBPS
:
1467 case PHY_LINK_SPEED_10GBPS
:
1469 case PHY_LINK_SPEED_20GBPS
:
1471 case PHY_LINK_SPEED_25GBPS
:
1473 case PHY_LINK_SPEED_40GBPS
:
1479 /* Uses synchronous mcc
1480 * Returns link_speed in Mbps
1482 int be_cmd_link_status_query(struct be_adapter
*adapter
, u16
*link_speed
,
1483 u8
*link_status
, u32 dom
)
1485 struct be_mcc_wrb
*wrb
;
1486 struct be_cmd_req_link_status
*req
;
1489 spin_lock_bh(&adapter
->mcc_lock
);
1492 *link_status
= LINK_DOWN
;
1494 wrb
= wrb_from_mccq(adapter
);
1499 req
= embedded_payload(wrb
);
1501 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1502 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY
, sizeof(*req
), wrb
, NULL
);
1504 /* version 1 of the cmd is not supported only by BE2 */
1505 if (!BE2_chip(adapter
))
1506 req
->hdr
.version
= 1;
1508 req
->hdr
.domain
= dom
;
1510 status
= be_mcc_notify_wait(adapter
);
1512 struct be_cmd_resp_link_status
*resp
= embedded_payload(wrb
);
1514 *link_speed
= resp
->link_speed
?
1515 le16_to_cpu(resp
->link_speed
) * 10 :
1516 be_mac_to_link_speed(resp
->mac_speed
);
1518 if (!resp
->logical_link_status
)
1522 *link_status
= resp
->logical_link_status
;
1526 spin_unlock_bh(&adapter
->mcc_lock
);
1530 /* Uses synchronous mcc */
1531 int be_cmd_get_die_temperature(struct be_adapter
*adapter
)
1533 struct be_mcc_wrb
*wrb
;
1534 struct be_cmd_req_get_cntl_addnl_attribs
*req
;
1537 spin_lock_bh(&adapter
->mcc_lock
);
1539 wrb
= wrb_from_mccq(adapter
);
1544 req
= embedded_payload(wrb
);
1546 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1547 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES
, sizeof(*req
),
1550 be_mcc_notify(adapter
);
1553 spin_unlock_bh(&adapter
->mcc_lock
);
1557 /* Uses synchronous mcc */
1558 int be_cmd_get_reg_len(struct be_adapter
*adapter
, u32
*log_size
)
1560 struct be_mcc_wrb
*wrb
;
1561 struct be_cmd_req_get_fat
*req
;
1564 spin_lock_bh(&adapter
->mcc_lock
);
1566 wrb
= wrb_from_mccq(adapter
);
1571 req
= embedded_payload(wrb
);
1573 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1574 OPCODE_COMMON_MANAGE_FAT
, sizeof(*req
), wrb
, NULL
);
1575 req
->fat_operation
= cpu_to_le32(QUERY_FAT
);
1576 status
= be_mcc_notify_wait(adapter
);
1578 struct be_cmd_resp_get_fat
*resp
= embedded_payload(wrb
);
1579 if (log_size
&& resp
->log_size
)
1580 *log_size
= le32_to_cpu(resp
->log_size
) -
1584 spin_unlock_bh(&adapter
->mcc_lock
);
1588 void be_cmd_get_regs(struct be_adapter
*adapter
, u32 buf_len
, void *buf
)
1590 struct be_dma_mem get_fat_cmd
;
1591 struct be_mcc_wrb
*wrb
;
1592 struct be_cmd_req_get_fat
*req
;
1593 u32 offset
= 0, total_size
, buf_size
,
1594 log_offset
= sizeof(u32
), payload_len
;
1600 total_size
= buf_len
;
1602 get_fat_cmd
.size
= sizeof(struct be_cmd_req_get_fat
) + 60*1024;
1603 get_fat_cmd
.va
= pci_alloc_consistent(adapter
->pdev
,
1606 if (!get_fat_cmd
.va
) {
1608 dev_err(&adapter
->pdev
->dev
,
1609 "Memory allocation failure while retrieving FAT data\n");
1613 spin_lock_bh(&adapter
->mcc_lock
);
1615 while (total_size
) {
1616 buf_size
= min(total_size
, (u32
)60*1024);
1617 total_size
-= buf_size
;
1619 wrb
= wrb_from_mccq(adapter
);
1624 req
= get_fat_cmd
.va
;
1626 payload_len
= sizeof(struct be_cmd_req_get_fat
) + buf_size
;
1627 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1628 OPCODE_COMMON_MANAGE_FAT
, payload_len
, wrb
,
1631 req
->fat_operation
= cpu_to_le32(RETRIEVE_FAT
);
1632 req
->read_log_offset
= cpu_to_le32(log_offset
);
1633 req
->read_log_length
= cpu_to_le32(buf_size
);
1634 req
->data_buffer_size
= cpu_to_le32(buf_size
);
1636 status
= be_mcc_notify_wait(adapter
);
1638 struct be_cmd_resp_get_fat
*resp
= get_fat_cmd
.va
;
1639 memcpy(buf
+ offset
,
1641 le32_to_cpu(resp
->read_log_length
));
1643 dev_err(&adapter
->pdev
->dev
, "FAT Table Retrieve error\n");
1647 log_offset
+= buf_size
;
1650 pci_free_consistent(adapter
->pdev
, get_fat_cmd
.size
,
1653 spin_unlock_bh(&adapter
->mcc_lock
);
1656 /* Uses synchronous mcc */
1657 int be_cmd_get_fw_ver(struct be_adapter
*adapter
, char *fw_ver
,
1660 struct be_mcc_wrb
*wrb
;
1661 struct be_cmd_req_get_fw_version
*req
;
1664 spin_lock_bh(&adapter
->mcc_lock
);
1666 wrb
= wrb_from_mccq(adapter
);
1672 req
= embedded_payload(wrb
);
1674 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1675 OPCODE_COMMON_GET_FW_VERSION
, sizeof(*req
), wrb
, NULL
);
1676 status
= be_mcc_notify_wait(adapter
);
1678 struct be_cmd_resp_get_fw_version
*resp
= embedded_payload(wrb
);
1679 strcpy(fw_ver
, resp
->firmware_version_string
);
1681 strcpy(fw_on_flash
, resp
->fw_on_flash_version_string
);
1684 spin_unlock_bh(&adapter
->mcc_lock
);
1688 /* set the EQ delay interval of an EQ to specified value
1691 int be_cmd_modify_eqd(struct be_adapter
*adapter
, u32 eq_id
, u32 eqd
)
1693 struct be_mcc_wrb
*wrb
;
1694 struct be_cmd_req_modify_eq_delay
*req
;
1697 spin_lock_bh(&adapter
->mcc_lock
);
1699 wrb
= wrb_from_mccq(adapter
);
1704 req
= embedded_payload(wrb
);
1706 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1707 OPCODE_COMMON_MODIFY_EQ_DELAY
, sizeof(*req
), wrb
, NULL
);
1709 req
->num_eq
= cpu_to_le32(1);
1710 req
->delay
[0].eq_id
= cpu_to_le32(eq_id
);
1711 req
->delay
[0].phase
= 0;
1712 req
->delay
[0].delay_multiplier
= cpu_to_le32(eqd
);
1714 be_mcc_notify(adapter
);
1717 spin_unlock_bh(&adapter
->mcc_lock
);
1721 /* Uses sycnhronous mcc */
1722 int be_cmd_vlan_config(struct be_adapter
*adapter
, u32 if_id
, u16
*vtag_array
,
1723 u32 num
, bool untagged
, bool promiscuous
)
1725 struct be_mcc_wrb
*wrb
;
1726 struct be_cmd_req_vlan_config
*req
;
1729 spin_lock_bh(&adapter
->mcc_lock
);
1731 wrb
= wrb_from_mccq(adapter
);
1736 req
= embedded_payload(wrb
);
1738 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1739 OPCODE_COMMON_NTWK_VLAN_CONFIG
, sizeof(*req
), wrb
, NULL
);
1741 req
->interface_id
= if_id
;
1742 req
->promiscuous
= promiscuous
;
1743 req
->untagged
= untagged
;
1744 req
->num_vlan
= num
;
1746 memcpy(req
->normal_vlan
, vtag_array
,
1747 req
->num_vlan
* sizeof(vtag_array
[0]));
1750 status
= be_mcc_notify_wait(adapter
);
1753 spin_unlock_bh(&adapter
->mcc_lock
);
1757 int be_cmd_rx_filter(struct be_adapter
*adapter
, u32 flags
, u32 value
)
1759 struct be_mcc_wrb
*wrb
;
1760 struct be_dma_mem
*mem
= &adapter
->rx_filter
;
1761 struct be_cmd_req_rx_filter
*req
= mem
->va
;
1764 spin_lock_bh(&adapter
->mcc_lock
);
1766 wrb
= wrb_from_mccq(adapter
);
1771 memset(req
, 0, sizeof(*req
));
1772 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1773 OPCODE_COMMON_NTWK_RX_FILTER
, sizeof(*req
),
1776 req
->if_id
= cpu_to_le32(adapter
->if_handle
);
1777 if (flags
& IFF_PROMISC
) {
1778 req
->if_flags_mask
= cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS
|
1779 BE_IF_FLAGS_VLAN_PROMISCUOUS
|
1780 BE_IF_FLAGS_MCAST_PROMISCUOUS
);
1782 req
->if_flags
= cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS
|
1783 BE_IF_FLAGS_VLAN_PROMISCUOUS
|
1784 BE_IF_FLAGS_MCAST_PROMISCUOUS
);
1785 } else if (flags
& IFF_ALLMULTI
) {
1786 req
->if_flags_mask
= req
->if_flags
=
1787 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS
);
1789 struct netdev_hw_addr
*ha
;
1792 req
->if_flags_mask
= req
->if_flags
=
1793 cpu_to_le32(BE_IF_FLAGS_MULTICAST
);
1795 /* Reset mcast promisc mode if already set by setting mask
1796 * and not setting flags field
1798 req
->if_flags_mask
|=
1799 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS
&
1800 adapter
->if_cap_flags
);
1802 req
->mcast_num
= cpu_to_le32(netdev_mc_count(adapter
->netdev
));
1803 netdev_for_each_mc_addr(ha
, adapter
->netdev
)
1804 memcpy(req
->mcast_mac
[i
++].byte
, ha
->addr
, ETH_ALEN
);
1807 status
= be_mcc_notify_wait(adapter
);
1809 spin_unlock_bh(&adapter
->mcc_lock
);
1813 /* Uses synchrounous mcc */
1814 int be_cmd_set_flow_control(struct be_adapter
*adapter
, u32 tx_fc
, u32 rx_fc
)
1816 struct be_mcc_wrb
*wrb
;
1817 struct be_cmd_req_set_flow_control
*req
;
1820 if (!be_cmd_allowed(adapter
, OPCODE_COMMON_SET_FLOW_CONTROL
,
1821 CMD_SUBSYSTEM_COMMON
))
1824 spin_lock_bh(&adapter
->mcc_lock
);
1826 wrb
= wrb_from_mccq(adapter
);
1831 req
= embedded_payload(wrb
);
1833 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1834 OPCODE_COMMON_SET_FLOW_CONTROL
, sizeof(*req
), wrb
, NULL
);
1836 req
->tx_flow_control
= cpu_to_le16((u16
)tx_fc
);
1837 req
->rx_flow_control
= cpu_to_le16((u16
)rx_fc
);
1839 status
= be_mcc_notify_wait(adapter
);
1842 spin_unlock_bh(&adapter
->mcc_lock
);
1847 int be_cmd_get_flow_control(struct be_adapter
*adapter
, u32
*tx_fc
, u32
*rx_fc
)
1849 struct be_mcc_wrb
*wrb
;
1850 struct be_cmd_req_get_flow_control
*req
;
1853 if (!be_cmd_allowed(adapter
, OPCODE_COMMON_GET_FLOW_CONTROL
,
1854 CMD_SUBSYSTEM_COMMON
))
1857 spin_lock_bh(&adapter
->mcc_lock
);
1859 wrb
= wrb_from_mccq(adapter
);
1864 req
= embedded_payload(wrb
);
1866 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1867 OPCODE_COMMON_GET_FLOW_CONTROL
, sizeof(*req
), wrb
, NULL
);
1869 status
= be_mcc_notify_wait(adapter
);
1871 struct be_cmd_resp_get_flow_control
*resp
=
1872 embedded_payload(wrb
);
1873 *tx_fc
= le16_to_cpu(resp
->tx_flow_control
);
1874 *rx_fc
= le16_to_cpu(resp
->rx_flow_control
);
1878 spin_unlock_bh(&adapter
->mcc_lock
);
1883 int be_cmd_query_fw_cfg(struct be_adapter
*adapter
, u32
*port_num
,
1884 u32
*mode
, u32
*caps
, u16
*asic_rev
)
1886 struct be_mcc_wrb
*wrb
;
1887 struct be_cmd_req_query_fw_cfg
*req
;
1890 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
1893 wrb
= wrb_from_mbox(adapter
);
1894 req
= embedded_payload(wrb
);
1896 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1897 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG
, sizeof(*req
), wrb
, NULL
);
1899 status
= be_mbox_notify_wait(adapter
);
1901 struct be_cmd_resp_query_fw_cfg
*resp
= embedded_payload(wrb
);
1902 *port_num
= le32_to_cpu(resp
->phys_port
);
1903 *mode
= le32_to_cpu(resp
->function_mode
);
1904 *caps
= le32_to_cpu(resp
->function_caps
);
1905 *asic_rev
= le32_to_cpu(resp
->asic_revision
) & 0xFF;
1908 mutex_unlock(&adapter
->mbox_lock
);
1913 int be_cmd_reset_function(struct be_adapter
*adapter
)
1915 struct be_mcc_wrb
*wrb
;
1916 struct be_cmd_req_hdr
*req
;
1919 if (lancer_chip(adapter
)) {
1920 status
= lancer_wait_ready(adapter
);
1922 iowrite32(SLI_PORT_CONTROL_IP_MASK
,
1923 adapter
->db
+ SLIPORT_CONTROL_OFFSET
);
1924 status
= lancer_test_and_set_rdy_state(adapter
);
1927 dev_err(&adapter
->pdev
->dev
,
1928 "Adapter in non recoverable error\n");
1933 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
1936 wrb
= wrb_from_mbox(adapter
);
1937 req
= embedded_payload(wrb
);
1939 be_wrb_cmd_hdr_prepare(req
, CMD_SUBSYSTEM_COMMON
,
1940 OPCODE_COMMON_FUNCTION_RESET
, sizeof(*req
), wrb
, NULL
);
1942 status
= be_mbox_notify_wait(adapter
);
1944 mutex_unlock(&adapter
->mbox_lock
);
1948 int be_cmd_rss_config(struct be_adapter
*adapter
, u8
*rsstable
,
1949 u32 rss_hash_opts
, u16 table_size
)
1951 struct be_mcc_wrb
*wrb
;
1952 struct be_cmd_req_rss_config
*req
;
1953 u32 myhash
[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
1954 0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
1955 0x3ea83c02, 0x4a110304};
1958 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
1961 wrb
= wrb_from_mbox(adapter
);
1962 req
= embedded_payload(wrb
);
1964 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
1965 OPCODE_ETH_RSS_CONFIG
, sizeof(*req
), wrb
, NULL
);
1967 req
->if_id
= cpu_to_le32(adapter
->if_handle
);
1968 req
->enable_rss
= cpu_to_le16(rss_hash_opts
);
1969 req
->cpu_table_size_log2
= cpu_to_le16(fls(table_size
) - 1);
1971 if (lancer_chip(adapter
) || skyhawk_chip(adapter
))
1972 req
->hdr
.version
= 1;
1974 memcpy(req
->cpu_table
, rsstable
, table_size
);
1975 memcpy(req
->hash
, myhash
, sizeof(myhash
));
1976 be_dws_cpu_to_le(req
->hash
, sizeof(req
->hash
));
1978 status
= be_mbox_notify_wait(adapter
);
1980 mutex_unlock(&adapter
->mbox_lock
);
1985 int be_cmd_set_beacon_state(struct be_adapter
*adapter
, u8 port_num
,
1986 u8 bcn
, u8 sts
, u8 state
)
1988 struct be_mcc_wrb
*wrb
;
1989 struct be_cmd_req_enable_disable_beacon
*req
;
1992 spin_lock_bh(&adapter
->mcc_lock
);
1994 wrb
= wrb_from_mccq(adapter
);
1999 req
= embedded_payload(wrb
);
2001 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2002 OPCODE_COMMON_ENABLE_DISABLE_BEACON
, sizeof(*req
), wrb
, NULL
);
2004 req
->port_num
= port_num
;
2005 req
->beacon_state
= state
;
2006 req
->beacon_duration
= bcn
;
2007 req
->status_duration
= sts
;
2009 status
= be_mcc_notify_wait(adapter
);
2012 spin_unlock_bh(&adapter
->mcc_lock
);
2017 int be_cmd_get_beacon_state(struct be_adapter
*adapter
, u8 port_num
, u32
*state
)
2019 struct be_mcc_wrb
*wrb
;
2020 struct be_cmd_req_get_beacon_state
*req
;
2023 spin_lock_bh(&adapter
->mcc_lock
);
2025 wrb
= wrb_from_mccq(adapter
);
2030 req
= embedded_payload(wrb
);
2032 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2033 OPCODE_COMMON_GET_BEACON_STATE
, sizeof(*req
), wrb
, NULL
);
2035 req
->port_num
= port_num
;
2037 status
= be_mcc_notify_wait(adapter
);
2039 struct be_cmd_resp_get_beacon_state
*resp
=
2040 embedded_payload(wrb
);
2041 *state
= resp
->beacon_state
;
2045 spin_unlock_bh(&adapter
->mcc_lock
);
2049 int lancer_cmd_write_object(struct be_adapter
*adapter
, struct be_dma_mem
*cmd
,
2050 u32 data_size
, u32 data_offset
,
2051 const char *obj_name
, u32
*data_written
,
2052 u8
*change_status
, u8
*addn_status
)
2054 struct be_mcc_wrb
*wrb
;
2055 struct lancer_cmd_req_write_object
*req
;
2056 struct lancer_cmd_resp_write_object
*resp
;
2060 spin_lock_bh(&adapter
->mcc_lock
);
2061 adapter
->flash_status
= 0;
2063 wrb
= wrb_from_mccq(adapter
);
2069 req
= embedded_payload(wrb
);
2071 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2072 OPCODE_COMMON_WRITE_OBJECT
,
2073 sizeof(struct lancer_cmd_req_write_object
), wrb
,
2076 ctxt
= &req
->context
;
2077 AMAP_SET_BITS(struct amap_lancer_write_obj_context
,
2078 write_length
, ctxt
, data_size
);
2081 AMAP_SET_BITS(struct amap_lancer_write_obj_context
,
2084 AMAP_SET_BITS(struct amap_lancer_write_obj_context
,
2087 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
2088 req
->write_offset
= cpu_to_le32(data_offset
);
2089 strcpy(req
->object_name
, obj_name
);
2090 req
->descriptor_count
= cpu_to_le32(1);
2091 req
->buf_len
= cpu_to_le32(data_size
);
2092 req
->addr_low
= cpu_to_le32((cmd
->dma
+
2093 sizeof(struct lancer_cmd_req_write_object
))
2095 req
->addr_high
= cpu_to_le32(upper_32_bits(cmd
->dma
+
2096 sizeof(struct lancer_cmd_req_write_object
)));
2098 be_mcc_notify(adapter
);
2099 spin_unlock_bh(&adapter
->mcc_lock
);
2101 if (!wait_for_completion_timeout(&adapter
->flash_compl
,
2102 msecs_to_jiffies(60000)))
2105 status
= adapter
->flash_status
;
2107 resp
= embedded_payload(wrb
);
2109 *data_written
= le32_to_cpu(resp
->actual_write_len
);
2110 *change_status
= resp
->change_status
;
2112 *addn_status
= resp
->additional_status
;
2118 spin_unlock_bh(&adapter
->mcc_lock
);
2122 int lancer_cmd_read_object(struct be_adapter
*adapter
, struct be_dma_mem
*cmd
,
2123 u32 data_size
, u32 data_offset
, const char *obj_name
,
2124 u32
*data_read
, u32
*eof
, u8
*addn_status
)
2126 struct be_mcc_wrb
*wrb
;
2127 struct lancer_cmd_req_read_object
*req
;
2128 struct lancer_cmd_resp_read_object
*resp
;
2131 spin_lock_bh(&adapter
->mcc_lock
);
2133 wrb
= wrb_from_mccq(adapter
);
2139 req
= embedded_payload(wrb
);
2141 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2142 OPCODE_COMMON_READ_OBJECT
,
2143 sizeof(struct lancer_cmd_req_read_object
), wrb
,
2146 req
->desired_read_len
= cpu_to_le32(data_size
);
2147 req
->read_offset
= cpu_to_le32(data_offset
);
2148 strcpy(req
->object_name
, obj_name
);
2149 req
->descriptor_count
= cpu_to_le32(1);
2150 req
->buf_len
= cpu_to_le32(data_size
);
2151 req
->addr_low
= cpu_to_le32((cmd
->dma
& 0xFFFFFFFF));
2152 req
->addr_high
= cpu_to_le32(upper_32_bits(cmd
->dma
));
2154 status
= be_mcc_notify_wait(adapter
);
2156 resp
= embedded_payload(wrb
);
2158 *data_read
= le32_to_cpu(resp
->actual_read_len
);
2159 *eof
= le32_to_cpu(resp
->eof
);
2161 *addn_status
= resp
->additional_status
;
2165 spin_unlock_bh(&adapter
->mcc_lock
);
2169 int be_cmd_write_flashrom(struct be_adapter
*adapter
, struct be_dma_mem
*cmd
,
2170 u32 flash_type
, u32 flash_opcode
, u32 buf_size
)
2172 struct be_mcc_wrb
*wrb
;
2173 struct be_cmd_write_flashrom
*req
;
2176 spin_lock_bh(&adapter
->mcc_lock
);
2177 adapter
->flash_status
= 0;
2179 wrb
= wrb_from_mccq(adapter
);
2186 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2187 OPCODE_COMMON_WRITE_FLASHROM
, cmd
->size
, wrb
, cmd
);
2189 req
->params
.op_type
= cpu_to_le32(flash_type
);
2190 req
->params
.op_code
= cpu_to_le32(flash_opcode
);
2191 req
->params
.data_buf_size
= cpu_to_le32(buf_size
);
2193 be_mcc_notify(adapter
);
2194 spin_unlock_bh(&adapter
->mcc_lock
);
2196 if (!wait_for_completion_timeout(&adapter
->flash_compl
,
2197 msecs_to_jiffies(40000)))
2200 status
= adapter
->flash_status
;
2205 spin_unlock_bh(&adapter
->mcc_lock
);
2209 int be_cmd_get_flash_crc(struct be_adapter
*adapter
, u8
*flashed_crc
,
2212 struct be_mcc_wrb
*wrb
;
2213 struct be_cmd_read_flash_crc
*req
;
2216 spin_lock_bh(&adapter
->mcc_lock
);
2218 wrb
= wrb_from_mccq(adapter
);
2223 req
= embedded_payload(wrb
);
2225 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2226 OPCODE_COMMON_READ_FLASHROM
, sizeof(*req
),
2229 req
->params
.op_type
= cpu_to_le32(OPTYPE_REDBOOT
);
2230 req
->params
.op_code
= cpu_to_le32(FLASHROM_OPER_REPORT
);
2231 req
->params
.offset
= cpu_to_le32(offset
);
2232 req
->params
.data_buf_size
= cpu_to_le32(0x4);
2234 status
= be_mcc_notify_wait(adapter
);
2236 memcpy(flashed_crc
, req
->crc
, 4);
2239 spin_unlock_bh(&adapter
->mcc_lock
);
2243 int be_cmd_enable_magic_wol(struct be_adapter
*adapter
, u8
*mac
,
2244 struct be_dma_mem
*nonemb_cmd
)
2246 struct be_mcc_wrb
*wrb
;
2247 struct be_cmd_req_acpi_wol_magic_config
*req
;
2250 spin_lock_bh(&adapter
->mcc_lock
);
2252 wrb
= wrb_from_mccq(adapter
);
2257 req
= nonemb_cmd
->va
;
2259 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
2260 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG
, sizeof(*req
), wrb
,
2262 memcpy(req
->magic_mac
, mac
, ETH_ALEN
);
2264 status
= be_mcc_notify_wait(adapter
);
2267 spin_unlock_bh(&adapter
->mcc_lock
);
2271 int be_cmd_set_loopback(struct be_adapter
*adapter
, u8 port_num
,
2272 u8 loopback_type
, u8 enable
)
2274 struct be_mcc_wrb
*wrb
;
2275 struct be_cmd_req_set_lmode
*req
;
2278 spin_lock_bh(&adapter
->mcc_lock
);
2280 wrb
= wrb_from_mccq(adapter
);
2286 req
= embedded_payload(wrb
);
2288 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_LOWLEVEL
,
2289 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE
, sizeof(*req
), wrb
,
2292 req
->src_port
= port_num
;
2293 req
->dest_port
= port_num
;
2294 req
->loopback_type
= loopback_type
;
2295 req
->loopback_state
= enable
;
2297 status
= be_mcc_notify_wait(adapter
);
2299 spin_unlock_bh(&adapter
->mcc_lock
);
2303 int be_cmd_loopback_test(struct be_adapter
*adapter
, u32 port_num
,
2304 u32 loopback_type
, u32 pkt_size
, u32 num_pkts
, u64 pattern
)
2306 struct be_mcc_wrb
*wrb
;
2307 struct be_cmd_req_loopback_test
*req
;
2310 spin_lock_bh(&adapter
->mcc_lock
);
2312 wrb
= wrb_from_mccq(adapter
);
2318 req
= embedded_payload(wrb
);
2320 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_LOWLEVEL
,
2321 OPCODE_LOWLEVEL_LOOPBACK_TEST
, sizeof(*req
), wrb
, NULL
);
2322 req
->hdr
.timeout
= cpu_to_le32(4);
2324 req
->pattern
= cpu_to_le64(pattern
);
2325 req
->src_port
= cpu_to_le32(port_num
);
2326 req
->dest_port
= cpu_to_le32(port_num
);
2327 req
->pkt_size
= cpu_to_le32(pkt_size
);
2328 req
->num_pkts
= cpu_to_le32(num_pkts
);
2329 req
->loopback_type
= cpu_to_le32(loopback_type
);
2331 status
= be_mcc_notify_wait(adapter
);
2333 struct be_cmd_resp_loopback_test
*resp
= embedded_payload(wrb
);
2334 status
= le32_to_cpu(resp
->status
);
2338 spin_unlock_bh(&adapter
->mcc_lock
);
2342 int be_cmd_ddr_dma_test(struct be_adapter
*adapter
, u64 pattern
,
2343 u32 byte_cnt
, struct be_dma_mem
*cmd
)
2345 struct be_mcc_wrb
*wrb
;
2346 struct be_cmd_req_ddrdma_test
*req
;
2350 spin_lock_bh(&adapter
->mcc_lock
);
2352 wrb
= wrb_from_mccq(adapter
);
2358 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_LOWLEVEL
,
2359 OPCODE_LOWLEVEL_HOST_DDR_DMA
, cmd
->size
, wrb
, cmd
);
2361 req
->pattern
= cpu_to_le64(pattern
);
2362 req
->byte_count
= cpu_to_le32(byte_cnt
);
2363 for (i
= 0; i
< byte_cnt
; i
++) {
2364 req
->snd_buff
[i
] = (u8
)(pattern
>> (j
*8));
2370 status
= be_mcc_notify_wait(adapter
);
2373 struct be_cmd_resp_ddrdma_test
*resp
;
2375 if ((memcmp(resp
->rcv_buff
, req
->snd_buff
, byte_cnt
) != 0) ||
2382 spin_unlock_bh(&adapter
->mcc_lock
);
2386 int be_cmd_get_seeprom_data(struct be_adapter
*adapter
,
2387 struct be_dma_mem
*nonemb_cmd
)
2389 struct be_mcc_wrb
*wrb
;
2390 struct be_cmd_req_seeprom_read
*req
;
2393 spin_lock_bh(&adapter
->mcc_lock
);
2395 wrb
= wrb_from_mccq(adapter
);
2400 req
= nonemb_cmd
->va
;
2402 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2403 OPCODE_COMMON_SEEPROM_READ
, sizeof(*req
), wrb
,
2406 status
= be_mcc_notify_wait(adapter
);
2409 spin_unlock_bh(&adapter
->mcc_lock
);
2413 int be_cmd_get_phy_info(struct be_adapter
*adapter
)
2415 struct be_mcc_wrb
*wrb
;
2416 struct be_cmd_req_get_phy_info
*req
;
2417 struct be_dma_mem cmd
;
2420 if (!be_cmd_allowed(adapter
, OPCODE_COMMON_GET_PHY_DETAILS
,
2421 CMD_SUBSYSTEM_COMMON
))
2424 spin_lock_bh(&adapter
->mcc_lock
);
2426 wrb
= wrb_from_mccq(adapter
);
2431 cmd
.size
= sizeof(struct be_cmd_req_get_phy_info
);
2432 cmd
.va
= pci_alloc_consistent(adapter
->pdev
, cmd
.size
,
2435 dev_err(&adapter
->pdev
->dev
, "Memory alloc failure\n");
2442 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2443 OPCODE_COMMON_GET_PHY_DETAILS
, sizeof(*req
),
2446 status
= be_mcc_notify_wait(adapter
);
2448 struct be_phy_info
*resp_phy_info
=
2449 cmd
.va
+ sizeof(struct be_cmd_req_hdr
);
2450 adapter
->phy
.phy_type
= le16_to_cpu(resp_phy_info
->phy_type
);
2451 adapter
->phy
.interface_type
=
2452 le16_to_cpu(resp_phy_info
->interface_type
);
2453 adapter
->phy
.auto_speeds_supported
=
2454 le16_to_cpu(resp_phy_info
->auto_speeds_supported
);
2455 adapter
->phy
.fixed_speeds_supported
=
2456 le16_to_cpu(resp_phy_info
->fixed_speeds_supported
);
2457 adapter
->phy
.misc_params
=
2458 le32_to_cpu(resp_phy_info
->misc_params
);
2460 if (BE2_chip(adapter
)) {
2461 adapter
->phy
.fixed_speeds_supported
=
2462 BE_SUPPORTED_SPEED_10GBPS
|
2463 BE_SUPPORTED_SPEED_1GBPS
;
2466 pci_free_consistent(adapter
->pdev
, cmd
.size
,
2469 spin_unlock_bh(&adapter
->mcc_lock
);
2473 int be_cmd_set_qos(struct be_adapter
*adapter
, u32 bps
, u32 domain
)
2475 struct be_mcc_wrb
*wrb
;
2476 struct be_cmd_req_set_qos
*req
;
2479 spin_lock_bh(&adapter
->mcc_lock
);
2481 wrb
= wrb_from_mccq(adapter
);
2487 req
= embedded_payload(wrb
);
2489 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2490 OPCODE_COMMON_SET_QOS
, sizeof(*req
), wrb
, NULL
);
2492 req
->hdr
.domain
= domain
;
2493 req
->valid_bits
= cpu_to_le32(BE_QOS_BITS_NIC
);
2494 req
->max_bps_nic
= cpu_to_le32(bps
);
2496 status
= be_mcc_notify_wait(adapter
);
2499 spin_unlock_bh(&adapter
->mcc_lock
);
2503 int be_cmd_get_cntl_attributes(struct be_adapter
*adapter
)
2505 struct be_mcc_wrb
*wrb
;
2506 struct be_cmd_req_cntl_attribs
*req
;
2507 struct be_cmd_resp_cntl_attribs
*resp
;
2509 int payload_len
= max(sizeof(*req
), sizeof(*resp
));
2510 struct mgmt_controller_attrib
*attribs
;
2511 struct be_dma_mem attribs_cmd
;
2513 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
2516 memset(&attribs_cmd
, 0, sizeof(struct be_dma_mem
));
2517 attribs_cmd
.size
= sizeof(struct be_cmd_resp_cntl_attribs
);
2518 attribs_cmd
.va
= pci_alloc_consistent(adapter
->pdev
, attribs_cmd
.size
,
2520 if (!attribs_cmd
.va
) {
2521 dev_err(&adapter
->pdev
->dev
,
2522 "Memory allocation failure\n");
2527 wrb
= wrb_from_mbox(adapter
);
2532 req
= attribs_cmd
.va
;
2534 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2535 OPCODE_COMMON_GET_CNTL_ATTRIBUTES
, payload_len
, wrb
,
2538 status
= be_mbox_notify_wait(adapter
);
2540 attribs
= attribs_cmd
.va
+ sizeof(struct be_cmd_resp_hdr
);
2541 adapter
->hba_port_num
= attribs
->hba_attribs
.phy_port
;
2545 mutex_unlock(&adapter
->mbox_lock
);
2547 pci_free_consistent(adapter
->pdev
, attribs_cmd
.size
,
2548 attribs_cmd
.va
, attribs_cmd
.dma
);
2553 int be_cmd_req_native_mode(struct be_adapter
*adapter
)
2555 struct be_mcc_wrb
*wrb
;
2556 struct be_cmd_req_set_func_cap
*req
;
2559 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
2562 wrb
= wrb_from_mbox(adapter
);
2568 req
= embedded_payload(wrb
);
2570 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2571 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP
, sizeof(*req
), wrb
, NULL
);
2573 req
->valid_cap_flags
= cpu_to_le32(CAPABILITY_SW_TIMESTAMPS
|
2574 CAPABILITY_BE3_NATIVE_ERX_API
);
2575 req
->cap_flags
= cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API
);
2577 status
= be_mbox_notify_wait(adapter
);
2579 struct be_cmd_resp_set_func_cap
*resp
= embedded_payload(wrb
);
2580 adapter
->be3_native
= le32_to_cpu(resp
->cap_flags
) &
2581 CAPABILITY_BE3_NATIVE_ERX_API
;
2582 if (!adapter
->be3_native
)
2583 dev_warn(&adapter
->pdev
->dev
,
2584 "adapter not in advanced mode\n");
2587 mutex_unlock(&adapter
->mbox_lock
);
2591 /* Get privilege(s) for a function */
2592 int be_cmd_get_fn_privileges(struct be_adapter
*adapter
, u32
*privilege
,
2595 struct be_mcc_wrb
*wrb
;
2596 struct be_cmd_req_get_fn_privileges
*req
;
2599 spin_lock_bh(&adapter
->mcc_lock
);
2601 wrb
= wrb_from_mccq(adapter
);
2607 req
= embedded_payload(wrb
);
2609 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2610 OPCODE_COMMON_GET_FN_PRIVILEGES
, sizeof(*req
),
2613 req
->hdr
.domain
= domain
;
2615 status
= be_mcc_notify_wait(adapter
);
2617 struct be_cmd_resp_get_fn_privileges
*resp
=
2618 embedded_payload(wrb
);
2619 *privilege
= le32_to_cpu(resp
->privilege_mask
);
2623 spin_unlock_bh(&adapter
->mcc_lock
);
2627 /* Set privilege(s) for a function */
2628 int be_cmd_set_fn_privileges(struct be_adapter
*adapter
, u32 privileges
,
2631 struct be_mcc_wrb
*wrb
;
2632 struct be_cmd_req_set_fn_privileges
*req
;
2635 spin_lock_bh(&adapter
->mcc_lock
);
2637 wrb
= wrb_from_mccq(adapter
);
2643 req
= embedded_payload(wrb
);
2644 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2645 OPCODE_COMMON_SET_FN_PRIVILEGES
, sizeof(*req
),
2647 req
->hdr
.domain
= domain
;
2648 if (lancer_chip(adapter
))
2649 req
->privileges_lancer
= cpu_to_le32(privileges
);
2651 req
->privileges
= cpu_to_le32(privileges
);
2653 status
= be_mcc_notify_wait(adapter
);
2655 spin_unlock_bh(&adapter
->mcc_lock
);
2659 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
2660 * pmac_id_valid: false => pmac_id or MAC address is requested.
2661 * If pmac_id is returned, pmac_id_valid is returned as true
2663 int be_cmd_get_mac_from_list(struct be_adapter
*adapter
, u8
*mac
,
2664 bool *pmac_id_valid
, u32
*pmac_id
, u8 domain
)
2666 struct be_mcc_wrb
*wrb
;
2667 struct be_cmd_req_get_mac_list
*req
;
2670 struct be_dma_mem get_mac_list_cmd
;
2673 memset(&get_mac_list_cmd
, 0, sizeof(struct be_dma_mem
));
2674 get_mac_list_cmd
.size
= sizeof(struct be_cmd_resp_get_mac_list
);
2675 get_mac_list_cmd
.va
= pci_alloc_consistent(adapter
->pdev
,
2676 get_mac_list_cmd
.size
,
2677 &get_mac_list_cmd
.dma
);
2679 if (!get_mac_list_cmd
.va
) {
2680 dev_err(&adapter
->pdev
->dev
,
2681 "Memory allocation failure during GET_MAC_LIST\n");
2685 spin_lock_bh(&adapter
->mcc_lock
);
2687 wrb
= wrb_from_mccq(adapter
);
2693 req
= get_mac_list_cmd
.va
;
2695 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2696 OPCODE_COMMON_GET_MAC_LIST
,
2697 get_mac_list_cmd
.size
, wrb
, &get_mac_list_cmd
);
2698 req
->hdr
.domain
= domain
;
2699 req
->mac_type
= MAC_ADDRESS_TYPE_NETWORK
;
2700 if (*pmac_id_valid
) {
2701 req
->mac_id
= cpu_to_le32(*pmac_id
);
2702 req
->iface_id
= cpu_to_le16(adapter
->if_handle
);
2703 req
->perm_override
= 0;
2705 req
->perm_override
= 1;
2708 status
= be_mcc_notify_wait(adapter
);
2710 struct be_cmd_resp_get_mac_list
*resp
=
2711 get_mac_list_cmd
.va
;
2713 if (*pmac_id_valid
) {
2714 memcpy(mac
, resp
->macid_macaddr
.mac_addr_id
.macaddr
,
2719 mac_count
= resp
->true_mac_count
+ resp
->pseudo_mac_count
;
2720 /* Mac list returned could contain one or more active mac_ids
2721 * or one or more true or pseudo permanant mac addresses.
2722 * If an active mac_id is present, return first active mac_id
2725 for (i
= 0; i
< mac_count
; i
++) {
2726 struct get_list_macaddr
*mac_entry
;
2730 mac_entry
= &resp
->macaddr_list
[i
];
2731 mac_addr_size
= le16_to_cpu(mac_entry
->mac_addr_size
);
2732 /* mac_id is a 32 bit value and mac_addr size
2735 if (mac_addr_size
== sizeof(u32
)) {
2736 *pmac_id_valid
= true;
2737 mac_id
= mac_entry
->mac_addr_id
.s_mac_id
.mac_id
;
2738 *pmac_id
= le32_to_cpu(mac_id
);
2742 /* If no active mac_id found, return first mac addr */
2743 *pmac_id_valid
= false;
2744 memcpy(mac
, resp
->macaddr_list
[0].mac_addr_id
.macaddr
,
2749 spin_unlock_bh(&adapter
->mcc_lock
);
2750 pci_free_consistent(adapter
->pdev
, get_mac_list_cmd
.size
,
2751 get_mac_list_cmd
.va
, get_mac_list_cmd
.dma
);
2755 int be_cmd_get_active_mac(struct be_adapter
*adapter
, u32 curr_pmac_id
, u8
*mac
)
2759 if (BEx_chip(adapter
))
2760 return be_cmd_mac_addr_query(adapter
, mac
, false,
2761 adapter
->if_handle
, curr_pmac_id
);
2763 /* Fetch the MAC address using pmac_id */
2764 return be_cmd_get_mac_from_list(adapter
, mac
, &active
,
2768 int be_cmd_get_perm_mac(struct be_adapter
*adapter
, u8
*mac
)
2771 bool pmac_valid
= false;
2773 memset(mac
, 0, ETH_ALEN
);
2775 if (BEx_chip(adapter
)) {
2776 if (be_physfn(adapter
))
2777 status
= be_cmd_mac_addr_query(adapter
, mac
, true, 0,
2780 status
= be_cmd_mac_addr_query(adapter
, mac
, false,
2781 adapter
->if_handle
, 0);
2783 status
= be_cmd_get_mac_from_list(adapter
, mac
, &pmac_valid
,
2790 /* Uses synchronous MCCQ */
2791 int be_cmd_set_mac_list(struct be_adapter
*adapter
, u8
*mac_array
,
2792 u8 mac_count
, u32 domain
)
2794 struct be_mcc_wrb
*wrb
;
2795 struct be_cmd_req_set_mac_list
*req
;
2797 struct be_dma_mem cmd
;
2799 memset(&cmd
, 0, sizeof(struct be_dma_mem
));
2800 cmd
.size
= sizeof(struct be_cmd_req_set_mac_list
);
2801 cmd
.va
= dma_alloc_coherent(&adapter
->pdev
->dev
, cmd
.size
,
2802 &cmd
.dma
, GFP_KERNEL
);
2806 spin_lock_bh(&adapter
->mcc_lock
);
2808 wrb
= wrb_from_mccq(adapter
);
2815 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2816 OPCODE_COMMON_SET_MAC_LIST
, sizeof(*req
),
2819 req
->hdr
.domain
= domain
;
2820 req
->mac_count
= mac_count
;
2822 memcpy(req
->mac
, mac_array
, ETH_ALEN
*mac_count
);
2824 status
= be_mcc_notify_wait(adapter
);
2827 dma_free_coherent(&adapter
->pdev
->dev
, cmd
.size
,
2829 spin_unlock_bh(&adapter
->mcc_lock
);
2833 /* Wrapper to delete any active MACs and provision the new mac.
2834 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
2835 * current list are active.
2837 int be_cmd_set_mac(struct be_adapter
*adapter
, u8
*mac
, int if_id
, u32 dom
)
2839 bool active_mac
= false;
2840 u8 old_mac
[ETH_ALEN
];
2844 status
= be_cmd_get_mac_from_list(adapter
, old_mac
, &active_mac
,
2846 if (!status
&& active_mac
)
2847 be_cmd_pmac_del(adapter
, if_id
, pmac_id
, dom
);
2849 return be_cmd_set_mac_list(adapter
, mac
, mac
? 1 : 0, dom
);
2852 int be_cmd_set_hsw_config(struct be_adapter
*adapter
, u16 pvid
,
2853 u32 domain
, u16 intf_id
)
2855 struct be_mcc_wrb
*wrb
;
2856 struct be_cmd_req_set_hsw_config
*req
;
2860 spin_lock_bh(&adapter
->mcc_lock
);
2862 wrb
= wrb_from_mccq(adapter
);
2868 req
= embedded_payload(wrb
);
2869 ctxt
= &req
->context
;
2871 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2872 OPCODE_COMMON_SET_HSW_CONFIG
, sizeof(*req
), wrb
, NULL
);
2874 req
->hdr
.domain
= domain
;
2875 AMAP_SET_BITS(struct amap_set_hsw_context
, interface_id
, ctxt
, intf_id
);
2877 AMAP_SET_BITS(struct amap_set_hsw_context
, pvid_valid
, ctxt
, 1);
2878 AMAP_SET_BITS(struct amap_set_hsw_context
, pvid
, ctxt
, pvid
);
2881 be_dws_cpu_to_le(req
->context
, sizeof(req
->context
));
2882 status
= be_mcc_notify_wait(adapter
);
2885 spin_unlock_bh(&adapter
->mcc_lock
);
2889 /* Get Hyper switch config */
2890 int be_cmd_get_hsw_config(struct be_adapter
*adapter
, u16
*pvid
,
2891 u32 domain
, u16 intf_id
)
2893 struct be_mcc_wrb
*wrb
;
2894 struct be_cmd_req_get_hsw_config
*req
;
2899 spin_lock_bh(&adapter
->mcc_lock
);
2901 wrb
= wrb_from_mccq(adapter
);
2907 req
= embedded_payload(wrb
);
2908 ctxt
= &req
->context
;
2910 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2911 OPCODE_COMMON_GET_HSW_CONFIG
, sizeof(*req
), wrb
, NULL
);
2913 req
->hdr
.domain
= domain
;
2914 AMAP_SET_BITS(struct amap_get_hsw_req_context
, interface_id
, ctxt
,
2916 AMAP_SET_BITS(struct amap_get_hsw_req_context
, pvid_valid
, ctxt
, 1);
2917 be_dws_cpu_to_le(req
->context
, sizeof(req
->context
));
2919 status
= be_mcc_notify_wait(adapter
);
2921 struct be_cmd_resp_get_hsw_config
*resp
=
2922 embedded_payload(wrb
);
2923 be_dws_le_to_cpu(&resp
->context
,
2924 sizeof(resp
->context
));
2925 vid
= AMAP_GET_BITS(struct amap_get_hsw_resp_context
,
2926 pvid
, &resp
->context
);
2927 *pvid
= le16_to_cpu(vid
);
2931 spin_unlock_bh(&adapter
->mcc_lock
);
2935 int be_cmd_get_acpi_wol_cap(struct be_adapter
*adapter
)
2937 struct be_mcc_wrb
*wrb
;
2938 struct be_cmd_req_acpi_wol_magic_config_v1
*req
;
2940 int payload_len
= sizeof(*req
);
2941 struct be_dma_mem cmd
;
2943 if (!be_cmd_allowed(adapter
, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG
,
2947 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
2950 memset(&cmd
, 0, sizeof(struct be_dma_mem
));
2951 cmd
.size
= sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1
);
2952 cmd
.va
= pci_alloc_consistent(adapter
->pdev
, cmd
.size
,
2955 dev_err(&adapter
->pdev
->dev
,
2956 "Memory allocation failure\n");
2961 wrb
= wrb_from_mbox(adapter
);
2969 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
2970 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG
,
2971 payload_len
, wrb
, &cmd
);
2973 req
->hdr
.version
= 1;
2974 req
->query_options
= BE_GET_WOL_CAP
;
2976 status
= be_mbox_notify_wait(adapter
);
2978 struct be_cmd_resp_acpi_wol_magic_config_v1
*resp
;
2979 resp
= (struct be_cmd_resp_acpi_wol_magic_config_v1
*) cmd
.va
;
2981 /* the command could succeed misleadingly on old f/w
2982 * which is not aware of the V1 version. fake an error. */
2983 if (resp
->hdr
.response_length
< payload_len
) {
2987 adapter
->wol_cap
= resp
->wol_settings
;
2990 mutex_unlock(&adapter
->mbox_lock
);
2992 pci_free_consistent(adapter
->pdev
, cmd
.size
, cmd
.va
, cmd
.dma
);
2996 int be_cmd_get_ext_fat_capabilites(struct be_adapter
*adapter
,
2997 struct be_dma_mem
*cmd
)
2999 struct be_mcc_wrb
*wrb
;
3000 struct be_cmd_req_get_ext_fat_caps
*req
;
3003 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
3006 wrb
= wrb_from_mbox(adapter
);
3013 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3014 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES
,
3015 cmd
->size
, wrb
, cmd
);
3016 req
->parameter_type
= cpu_to_le32(1);
3018 status
= be_mbox_notify_wait(adapter
);
3020 mutex_unlock(&adapter
->mbox_lock
);
3024 int be_cmd_set_ext_fat_capabilites(struct be_adapter
*adapter
,
3025 struct be_dma_mem
*cmd
,
3026 struct be_fat_conf_params
*configs
)
3028 struct be_mcc_wrb
*wrb
;
3029 struct be_cmd_req_set_ext_fat_caps
*req
;
3032 spin_lock_bh(&adapter
->mcc_lock
);
3034 wrb
= wrb_from_mccq(adapter
);
3041 memcpy(&req
->set_params
, configs
, sizeof(struct be_fat_conf_params
));
3042 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3043 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES
,
3044 cmd
->size
, wrb
, cmd
);
3046 status
= be_mcc_notify_wait(adapter
);
3048 spin_unlock_bh(&adapter
->mcc_lock
);
3052 int be_cmd_query_port_name(struct be_adapter
*adapter
, u8
*port_name
)
3054 struct be_mcc_wrb
*wrb
;
3055 struct be_cmd_req_get_port_name
*req
;
3058 if (!lancer_chip(adapter
)) {
3059 *port_name
= adapter
->hba_port_num
+ '0';
3063 spin_lock_bh(&adapter
->mcc_lock
);
3065 wrb
= wrb_from_mccq(adapter
);
3071 req
= embedded_payload(wrb
);
3073 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3074 OPCODE_COMMON_GET_PORT_NAME
, sizeof(*req
), wrb
,
3076 req
->hdr
.version
= 1;
3078 status
= be_mcc_notify_wait(adapter
);
3080 struct be_cmd_resp_get_port_name
*resp
= embedded_payload(wrb
);
3081 *port_name
= resp
->port_name
[adapter
->hba_port_num
];
3083 *port_name
= adapter
->hba_port_num
+ '0';
3086 spin_unlock_bh(&adapter
->mcc_lock
);
3090 static struct be_nic_resource_desc
*be_get_nic_desc(u8
*buf
, u32 desc_count
,
3093 struct be_nic_resource_desc
*desc
= (struct be_nic_resource_desc
*)buf
;
3096 for (i
= 0; i
< desc_count
; i
++) {
3097 desc
->desc_len
= desc
->desc_len
? : RESOURCE_DESC_SIZE
;
3098 if (((void *)desc
+ desc
->desc_len
) >
3099 (void *)(buf
+ max_buf_size
))
3102 if (desc
->desc_type
== NIC_RESOURCE_DESC_TYPE_V0
||
3103 desc
->desc_type
== NIC_RESOURCE_DESC_TYPE_V1
)
3106 desc
= (void *)desc
+ desc
->desc_len
;
3113 int be_cmd_get_func_config(struct be_adapter
*adapter
)
3115 struct be_mcc_wrb
*wrb
;
3116 struct be_cmd_req_get_func_config
*req
;
3118 struct be_dma_mem cmd
;
3120 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
3123 memset(&cmd
, 0, sizeof(struct be_dma_mem
));
3124 cmd
.size
= sizeof(struct be_cmd_resp_get_func_config
);
3125 cmd
.va
= pci_alloc_consistent(adapter
->pdev
, cmd
.size
,
3128 dev_err(&adapter
->pdev
->dev
, "Memory alloc failure\n");
3133 wrb
= wrb_from_mbox(adapter
);
3141 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3142 OPCODE_COMMON_GET_FUNC_CONFIG
,
3143 cmd
.size
, wrb
, &cmd
);
3145 if (skyhawk_chip(adapter
))
3146 req
->hdr
.version
= 1;
3148 status
= be_mbox_notify_wait(adapter
);
3150 struct be_cmd_resp_get_func_config
*resp
= cmd
.va
;
3151 u32 desc_count
= le32_to_cpu(resp
->desc_count
);
3152 struct be_nic_resource_desc
*desc
;
3154 desc
= be_get_nic_desc(resp
->func_param
, desc_count
,
3155 sizeof(resp
->func_param
));
3161 adapter
->pf_number
= desc
->pf_num
;
3162 adapter
->max_pmac_cnt
= le16_to_cpu(desc
->unicast_mac_count
);
3163 adapter
->max_vlans
= le16_to_cpu(desc
->vlan_count
);
3164 adapter
->max_mcast_mac
= le16_to_cpu(desc
->mcast_mac_count
);
3165 adapter
->max_tx_queues
= le16_to_cpu(desc
->txq_count
);
3166 adapter
->max_rss_queues
= le16_to_cpu(desc
->rssq_count
);
3167 adapter
->max_rx_queues
= le16_to_cpu(desc
->rq_count
);
3169 adapter
->max_event_queues
= le16_to_cpu(desc
->eq_count
);
3170 adapter
->if_cap_flags
= le32_to_cpu(desc
->cap_flags
);
3173 mutex_unlock(&adapter
->mbox_lock
);
3175 pci_free_consistent(adapter
->pdev
, cmd
.size
, cmd
.va
, cmd
.dma
);
3180 static int be_cmd_get_profile_config_mbox(struct be_adapter
*adapter
,
3181 u8 domain
, struct be_dma_mem
*cmd
)
3183 struct be_mcc_wrb
*wrb
;
3184 struct be_cmd_req_get_profile_config
*req
;
3187 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
3189 wrb
= wrb_from_mbox(adapter
);
3192 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3193 OPCODE_COMMON_GET_PROFILE_CONFIG
,
3194 cmd
->size
, wrb
, cmd
);
3196 req
->type
= ACTIVE_PROFILE_TYPE
;
3197 req
->hdr
.domain
= domain
;
3198 if (!lancer_chip(adapter
))
3199 req
->hdr
.version
= 1;
3201 status
= be_mbox_notify_wait(adapter
);
3203 mutex_unlock(&adapter
->mbox_lock
);
3208 static int be_cmd_get_profile_config_mccq(struct be_adapter
*adapter
,
3209 u8 domain
, struct be_dma_mem
*cmd
)
3211 struct be_mcc_wrb
*wrb
;
3212 struct be_cmd_req_get_profile_config
*req
;
3215 spin_lock_bh(&adapter
->mcc_lock
);
3217 wrb
= wrb_from_mccq(adapter
);
3224 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3225 OPCODE_COMMON_GET_PROFILE_CONFIG
,
3226 cmd
->size
, wrb
, cmd
);
3228 req
->type
= ACTIVE_PROFILE_TYPE
;
3229 req
->hdr
.domain
= domain
;
3230 if (!lancer_chip(adapter
))
3231 req
->hdr
.version
= 1;
3233 status
= be_mcc_notify_wait(adapter
);
3236 spin_unlock_bh(&adapter
->mcc_lock
);
3240 /* Uses sync mcc, if MCCQ is already created otherwise mbox */
3241 int be_cmd_get_profile_config(struct be_adapter
*adapter
, u32
*cap_flags
,
3242 u16
*txq_count
, u8 domain
)
3244 struct be_queue_info
*mccq
= &adapter
->mcc_obj
.q
;
3245 struct be_dma_mem cmd
;
3248 memset(&cmd
, 0, sizeof(struct be_dma_mem
));
3249 if (!lancer_chip(adapter
))
3250 cmd
.size
= sizeof(struct be_cmd_resp_get_profile_config_v1
);
3252 cmd
.size
= sizeof(struct be_cmd_resp_get_profile_config
);
3253 cmd
.va
= pci_alloc_consistent(adapter
->pdev
, cmd
.size
,
3256 dev_err(&adapter
->pdev
->dev
, "Memory alloc failure\n");
3261 status
= be_cmd_get_profile_config_mbox(adapter
, domain
, &cmd
);
3263 status
= be_cmd_get_profile_config_mccq(adapter
, domain
, &cmd
);
3265 struct be_cmd_resp_get_profile_config
*resp
= cmd
.va
;
3266 u32 desc_count
= le32_to_cpu(resp
->desc_count
);
3267 struct be_nic_resource_desc
*desc
;
3269 desc
= be_get_nic_desc(resp
->func_param
, desc_count
,
3270 sizeof(resp
->func_param
));
3277 *cap_flags
= le32_to_cpu(desc
->cap_flags
);
3279 *txq_count
= le32_to_cpu(desc
->txq_count
);
3283 pci_free_consistent(adapter
->pdev
, cmd
.size
,
3289 int be_cmd_set_profile_config(struct be_adapter
*adapter
, u32 bps
,
3292 struct be_mcc_wrb
*wrb
;
3293 struct be_cmd_req_set_profile_config
*req
;
3296 spin_lock_bh(&adapter
->mcc_lock
);
3298 wrb
= wrb_from_mccq(adapter
);
3304 req
= embedded_payload(wrb
);
3306 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3307 OPCODE_COMMON_SET_PROFILE_CONFIG
, sizeof(*req
),
3310 req
->hdr
.domain
= domain
;
3311 req
->desc_count
= cpu_to_le32(1);
3313 req
->nic_desc
.desc_type
= NIC_RESOURCE_DESC_TYPE_V0
;
3314 req
->nic_desc
.desc_len
= RESOURCE_DESC_SIZE
;
3315 req
->nic_desc
.flags
= (1 << QUN
) | (1 << IMM
) | (1 << NOSV
);
3316 req
->nic_desc
.pf_num
= adapter
->pf_number
;
3317 req
->nic_desc
.vf_num
= domain
;
3319 /* Mark fields invalid */
3320 req
->nic_desc
.unicast_mac_count
= 0xFFFF;
3321 req
->nic_desc
.mcc_count
= 0xFFFF;
3322 req
->nic_desc
.vlan_count
= 0xFFFF;
3323 req
->nic_desc
.mcast_mac_count
= 0xFFFF;
3324 req
->nic_desc
.txq_count
= 0xFFFF;
3325 req
->nic_desc
.rq_count
= 0xFFFF;
3326 req
->nic_desc
.rssq_count
= 0xFFFF;
3327 req
->nic_desc
.lro_count
= 0xFFFF;
3328 req
->nic_desc
.cq_count
= 0xFFFF;
3329 req
->nic_desc
.toe_conn_count
= 0xFFFF;
3330 req
->nic_desc
.eq_count
= 0xFFFF;
3331 req
->nic_desc
.link_param
= 0xFF;
3332 req
->nic_desc
.bw_min
= 0xFFFFFFFF;
3333 req
->nic_desc
.acpi_params
= 0xFF;
3334 req
->nic_desc
.wol_param
= 0x0F;
3337 req
->nic_desc
.bw_min
= cpu_to_le32(bps
);
3338 req
->nic_desc
.bw_max
= cpu_to_le32(bps
);
3339 status
= be_mcc_notify_wait(adapter
);
3341 spin_unlock_bh(&adapter
->mcc_lock
);
3345 int be_cmd_get_if_id(struct be_adapter
*adapter
, struct be_vf_cfg
*vf_cfg
,
3348 struct be_mcc_wrb
*wrb
;
3349 struct be_cmd_req_get_iface_list
*req
;
3350 struct be_cmd_resp_get_iface_list
*resp
;
3353 spin_lock_bh(&adapter
->mcc_lock
);
3355 wrb
= wrb_from_mccq(adapter
);
3360 req
= embedded_payload(wrb
);
3362 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3363 OPCODE_COMMON_GET_IFACE_LIST
, sizeof(*resp
),
3365 req
->hdr
.domain
= vf_num
+ 1;
3367 status
= be_mcc_notify_wait(adapter
);
3369 resp
= (struct be_cmd_resp_get_iface_list
*)req
;
3370 vf_cfg
->if_handle
= le32_to_cpu(resp
->if_desc
.if_id
);
3374 spin_unlock_bh(&adapter
->mcc_lock
);
3378 static int lancer_wait_idle(struct be_adapter
*adapter
)
3380 #define SLIPORT_IDLE_TIMEOUT 30
3384 for (i
= 0; i
< SLIPORT_IDLE_TIMEOUT
; i
++) {
3385 reg_val
= ioread32(adapter
->db
+ PHYSDEV_CONTROL_OFFSET
);
3386 if ((reg_val
& PHYSDEV_CONTROL_INP_MASK
) == 0)
3392 if (i
== SLIPORT_IDLE_TIMEOUT
)
3398 int lancer_physdev_ctrl(struct be_adapter
*adapter
, u32 mask
)
3402 status
= lancer_wait_idle(adapter
);
3406 iowrite32(mask
, adapter
->db
+ PHYSDEV_CONTROL_OFFSET
);
3411 /* Routine to check whether dump image is present or not */
3412 bool dump_present(struct be_adapter
*adapter
)
3414 u32 sliport_status
= 0;
3416 sliport_status
= ioread32(adapter
->db
+ SLIPORT_STATUS_OFFSET
);
3417 return !!(sliport_status
& SLIPORT_STATUS_DIP_MASK
);
3420 int lancer_initiate_dump(struct be_adapter
*adapter
)
3424 /* give firmware reset and diagnostic dump */
3425 status
= lancer_physdev_ctrl(adapter
, PHYSDEV_CONTROL_FW_RESET_MASK
|
3426 PHYSDEV_CONTROL_DD_MASK
);
3428 dev_err(&adapter
->pdev
->dev
, "Firmware reset failed\n");
3432 status
= lancer_wait_idle(adapter
);
3436 if (!dump_present(adapter
)) {
3437 dev_err(&adapter
->pdev
->dev
, "Dump image not present\n");
3445 int be_cmd_enable_vf(struct be_adapter
*adapter
, u8 domain
)
3447 struct be_mcc_wrb
*wrb
;
3448 struct be_cmd_enable_disable_vf
*req
;
3451 if (!lancer_chip(adapter
))
3454 spin_lock_bh(&adapter
->mcc_lock
);
3456 wrb
= wrb_from_mccq(adapter
);
3462 req
= embedded_payload(wrb
);
3464 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3465 OPCODE_COMMON_ENABLE_DISABLE_VF
, sizeof(*req
),
3468 req
->hdr
.domain
= domain
;
3470 status
= be_mcc_notify_wait(adapter
);
3472 spin_unlock_bh(&adapter
->mcc_lock
);
3476 int be_cmd_intr_set(struct be_adapter
*adapter
, bool intr_enable
)
3478 struct be_mcc_wrb
*wrb
;
3479 struct be_cmd_req_intr_set
*req
;
3482 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
3485 wrb
= wrb_from_mbox(adapter
);
3487 req
= embedded_payload(wrb
);
3489 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3490 OPCODE_COMMON_SET_INTERRUPT_ENABLE
, sizeof(*req
),
3493 req
->intr_enabled
= intr_enable
;
3495 status
= be_mbox_notify_wait(adapter
);
3497 mutex_unlock(&adapter
->mbox_lock
);
3501 int be_roce_mcc_cmd(void *netdev_handle
, void *wrb_payload
,
3502 int wrb_payload_size
, u16
*cmd_status
, u16
*ext_status
)
3504 struct be_adapter
*adapter
= netdev_priv(netdev_handle
);
3505 struct be_mcc_wrb
*wrb
;
3506 struct be_cmd_req_hdr
*hdr
= (struct be_cmd_req_hdr
*) wrb_payload
;
3507 struct be_cmd_req_hdr
*req
;
3508 struct be_cmd_resp_hdr
*resp
;
3511 spin_lock_bh(&adapter
->mcc_lock
);
3513 wrb
= wrb_from_mccq(adapter
);
3518 req
= embedded_payload(wrb
);
3519 resp
= embedded_payload(wrb
);
3521 be_wrb_cmd_hdr_prepare(req
, hdr
->subsystem
,
3522 hdr
->opcode
, wrb_payload_size
, wrb
, NULL
);
3523 memcpy(req
, wrb_payload
, wrb_payload_size
);
3524 be_dws_cpu_to_le(req
, wrb_payload_size
);
3526 status
= be_mcc_notify_wait(adapter
);
3528 *cmd_status
= (status
& 0xffff);
3531 memcpy(wrb_payload
, resp
, sizeof(*resp
) + resp
->response_length
);
3532 be_dws_le_to_cpu(wrb_payload
, sizeof(*resp
) + resp
->response_length
);
3534 spin_unlock_bh(&adapter
->mcc_lock
);
3537 EXPORT_SYMBOL(be_roce_mcc_cmd
);