1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Faraday FTGMAC100 Gigabit Ethernet
5 * (C) Copyright 2009-2011 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11 #include <linux/clk.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/etherdevice.h>
14 #include <linux/ethtool.h>
15 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/netdevice.h>
20 #include <linux/of_mdio.h>
21 #include <linux/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/property.h>
24 #include <linux/crc32.h>
25 #include <linux/if_vlan.h>
26 #include <linux/of_net.h>
30 #include "ftgmac100.h"
32 #define DRV_NAME "ftgmac100"
33 #define DRV_VERSION "0.7"
35 /* Arbitrary values, I am not sure the HW has limits */
36 #define MAX_RX_QUEUE_ENTRIES 1024
37 #define MAX_TX_QUEUE_ENTRIES 1024
38 #define MIN_RX_QUEUE_ENTRIES 32
39 #define MIN_TX_QUEUE_ENTRIES 32
42 #define DEF_RX_QUEUE_ENTRIES 128
43 #define DEF_TX_QUEUE_ENTRIES 128
45 #define MAX_PKT_SIZE 1536
46 #define RX_BUF_SIZE MAX_PKT_SIZE /* must be smaller than 0x3fff */
48 /* Min number of tx ring entries before stopping queue */
49 #define TX_THRESHOLD (MAX_SKB_FRAGS + 1)
51 #define FTGMAC_100MHZ 100000000
52 #define FTGMAC_25MHZ 25000000
60 unsigned int rx_q_entries
;
61 struct ftgmac100_rxdes
*rxdes
;
63 struct sk_buff
**rx_skbs
;
64 unsigned int rx_pointer
;
65 u32 rxdes0_edorr_mask
;
68 unsigned int tx_q_entries
;
69 struct ftgmac100_txdes
*txdes
;
71 struct sk_buff
**tx_skbs
;
72 unsigned int tx_clean_pointer
;
73 unsigned int tx_pointer
;
74 u32 txdes0_edotr_mask
;
76 /* Used to signal the reset task of ring change request */
77 unsigned int new_rx_q_entries
;
78 unsigned int new_tx_q_entries
;
80 /* Scratch page to use when rx skb alloc fails */
82 dma_addr_t rx_scratch_dma
;
84 /* Component structures */
85 struct net_device
*netdev
;
87 struct ncsi_dev
*ndev
;
88 struct napi_struct napi
;
89 struct work_struct reset_task
;
90 struct mii_bus
*mii_bus
;
93 /* AST2500/AST2600 RMII ref clock gate */
101 /* Multicast filter settings */
105 /* Flow control settings */
111 bool need_mac_restart
;
115 static int ftgmac100_reset_mac(struct ftgmac100
*priv
, u32 maccr
)
117 struct net_device
*netdev
= priv
->netdev
;
120 /* NOTE: reset clears all registers */
121 iowrite32(maccr
, priv
->base
+ FTGMAC100_OFFSET_MACCR
);
122 iowrite32(maccr
| FTGMAC100_MACCR_SW_RST
,
123 priv
->base
+ FTGMAC100_OFFSET_MACCR
);
124 for (i
= 0; i
< 200; i
++) {
127 maccr
= ioread32(priv
->base
+ FTGMAC100_OFFSET_MACCR
);
128 if (!(maccr
& FTGMAC100_MACCR_SW_RST
))
134 netdev_err(netdev
, "Hardware reset failed\n");
138 static int ftgmac100_reset_and_config_mac(struct ftgmac100
*priv
)
142 switch (priv
->cur_speed
) {
144 case 0: /* no link */
148 maccr
|= FTGMAC100_MACCR_FAST_MODE
;
152 maccr
|= FTGMAC100_MACCR_GIGA_MODE
;
155 netdev_err(priv
->netdev
, "Unknown speed %d !\n",
160 /* (Re)initialize the queue pointers */
161 priv
->rx_pointer
= 0;
162 priv
->tx_clean_pointer
= 0;
163 priv
->tx_pointer
= 0;
165 /* The doc says reset twice with 10us interval */
166 if (ftgmac100_reset_mac(priv
, maccr
))
168 usleep_range(10, 1000);
169 return ftgmac100_reset_mac(priv
, maccr
);
172 static void ftgmac100_write_mac_addr(struct ftgmac100
*priv
, const u8
*mac
)
174 unsigned int maddr
= mac
[0] << 8 | mac
[1];
175 unsigned int laddr
= mac
[2] << 24 | mac
[3] << 16 | mac
[4] << 8 | mac
[5];
177 iowrite32(maddr
, priv
->base
+ FTGMAC100_OFFSET_MAC_MADR
);
178 iowrite32(laddr
, priv
->base
+ FTGMAC100_OFFSET_MAC_LADR
);
181 static void ftgmac100_initial_mac(struct ftgmac100
*priv
)
188 addr
= device_get_mac_address(priv
->dev
, mac
, ETH_ALEN
);
190 ether_addr_copy(priv
->netdev
->dev_addr
, mac
);
191 dev_info(priv
->dev
, "Read MAC address %pM from device tree\n",
196 m
= ioread32(priv
->base
+ FTGMAC100_OFFSET_MAC_MADR
);
197 l
= ioread32(priv
->base
+ FTGMAC100_OFFSET_MAC_LADR
);
199 mac
[0] = (m
>> 8) & 0xff;
201 mac
[2] = (l
>> 24) & 0xff;
202 mac
[3] = (l
>> 16) & 0xff;
203 mac
[4] = (l
>> 8) & 0xff;
206 if (is_valid_ether_addr(mac
)) {
207 ether_addr_copy(priv
->netdev
->dev_addr
, mac
);
208 dev_info(priv
->dev
, "Read MAC address %pM from chip\n", mac
);
210 eth_hw_addr_random(priv
->netdev
);
211 dev_info(priv
->dev
, "Generated random MAC address %pM\n",
212 priv
->netdev
->dev_addr
);
216 static int ftgmac100_set_mac_addr(struct net_device
*dev
, void *p
)
220 ret
= eth_prepare_mac_addr_change(dev
, p
);
224 eth_commit_mac_addr_change(dev
, p
);
225 ftgmac100_write_mac_addr(netdev_priv(dev
), dev
->dev_addr
);
230 static void ftgmac100_config_pause(struct ftgmac100
*priv
)
232 u32 fcr
= FTGMAC100_FCR_PAUSE_TIME(16);
234 /* Throttle tx queue when receiving pause frames */
236 fcr
|= FTGMAC100_FCR_FC_EN
;
238 /* Enables sending pause frames when the RX queue is past a
242 fcr
|= FTGMAC100_FCR_FCTHR_EN
;
244 iowrite32(fcr
, priv
->base
+ FTGMAC100_OFFSET_FCR
);
247 static void ftgmac100_init_hw(struct ftgmac100
*priv
)
249 u32 reg
, rfifo_sz
, tfifo_sz
;
251 /* Clear stale interrupts */
252 reg
= ioread32(priv
->base
+ FTGMAC100_OFFSET_ISR
);
253 iowrite32(reg
, priv
->base
+ FTGMAC100_OFFSET_ISR
);
255 /* Setup RX ring buffer base */
256 iowrite32(priv
->rxdes_dma
, priv
->base
+ FTGMAC100_OFFSET_RXR_BADR
);
258 /* Setup TX ring buffer base */
259 iowrite32(priv
->txdes_dma
, priv
->base
+ FTGMAC100_OFFSET_NPTXR_BADR
);
261 /* Configure RX buffer size */
262 iowrite32(FTGMAC100_RBSR_SIZE(RX_BUF_SIZE
),
263 priv
->base
+ FTGMAC100_OFFSET_RBSR
);
265 /* Set RX descriptor autopoll */
266 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1),
267 priv
->base
+ FTGMAC100_OFFSET_APTC
);
269 /* Write MAC address */
270 ftgmac100_write_mac_addr(priv
, priv
->netdev
->dev_addr
);
272 /* Write multicast filter */
273 iowrite32(priv
->maht0
, priv
->base
+ FTGMAC100_OFFSET_MAHT0
);
274 iowrite32(priv
->maht1
, priv
->base
+ FTGMAC100_OFFSET_MAHT1
);
276 /* Configure descriptor sizes and increase burst sizes according
277 * to values in Aspeed SDK. The FIFO arbitration is enabled and
278 * the thresholds set based on the recommended values in the
279 * AST2400 specification.
281 iowrite32(FTGMAC100_DBLAC_RXDES_SIZE(2) | /* 2*8 bytes RX descs */
282 FTGMAC100_DBLAC_TXDES_SIZE(2) | /* 2*8 bytes TX descs */
283 FTGMAC100_DBLAC_RXBURST_SIZE(3) | /* 512 bytes max RX bursts */
284 FTGMAC100_DBLAC_TXBURST_SIZE(3) | /* 512 bytes max TX bursts */
285 FTGMAC100_DBLAC_RX_THR_EN
| /* Enable fifo threshold arb */
286 FTGMAC100_DBLAC_RXFIFO_HTHR(6) | /* 6/8 of FIFO high threshold */
287 FTGMAC100_DBLAC_RXFIFO_LTHR(2), /* 2/8 of FIFO low threshold */
288 priv
->base
+ FTGMAC100_OFFSET_DBLAC
);
290 /* Interrupt mitigation configured for 1 interrupt/packet. HW interrupt
291 * mitigation doesn't seem to provide any benefit with NAPI so leave
294 iowrite32(FTGMAC100_ITC_RXINT_THR(1) |
295 FTGMAC100_ITC_TXINT_THR(1),
296 priv
->base
+ FTGMAC100_OFFSET_ITC
);
298 /* Configure FIFO sizes in the TPAFCR register */
299 reg
= ioread32(priv
->base
+ FTGMAC100_OFFSET_FEAR
);
300 rfifo_sz
= reg
& 0x00000007;
301 tfifo_sz
= (reg
>> 3) & 0x00000007;
302 reg
= ioread32(priv
->base
+ FTGMAC100_OFFSET_TPAFCR
);
304 reg
|= (tfifo_sz
<< 27);
305 reg
|= (rfifo_sz
<< 24);
306 iowrite32(reg
, priv
->base
+ FTGMAC100_OFFSET_TPAFCR
);
309 static void ftgmac100_start_hw(struct ftgmac100
*priv
)
311 u32 maccr
= ioread32(priv
->base
+ FTGMAC100_OFFSET_MACCR
);
313 /* Keep the original GMAC and FAST bits */
314 maccr
&= (FTGMAC100_MACCR_FAST_MODE
| FTGMAC100_MACCR_GIGA_MODE
);
316 /* Add all the main enable bits */
317 maccr
|= FTGMAC100_MACCR_TXDMA_EN
|
318 FTGMAC100_MACCR_RXDMA_EN
|
319 FTGMAC100_MACCR_TXMAC_EN
|
320 FTGMAC100_MACCR_RXMAC_EN
|
321 FTGMAC100_MACCR_CRC_APD
|
322 FTGMAC100_MACCR_PHY_LINK_LEVEL
|
323 FTGMAC100_MACCR_RX_RUNT
|
324 FTGMAC100_MACCR_RX_BROADPKT
;
326 /* Add other bits as needed */
327 if (priv
->cur_duplex
== DUPLEX_FULL
)
328 maccr
|= FTGMAC100_MACCR_FULLDUP
;
329 if (priv
->netdev
->flags
& IFF_PROMISC
)
330 maccr
|= FTGMAC100_MACCR_RX_ALL
;
331 if (priv
->netdev
->flags
& IFF_ALLMULTI
)
332 maccr
|= FTGMAC100_MACCR_RX_MULTIPKT
;
333 else if (netdev_mc_count(priv
->netdev
))
334 maccr
|= FTGMAC100_MACCR_HT_MULTI_EN
;
336 /* Vlan filtering enabled */
337 if (priv
->netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)
338 maccr
|= FTGMAC100_MACCR_RM_VLAN
;
341 iowrite32(maccr
, priv
->base
+ FTGMAC100_OFFSET_MACCR
);
344 static void ftgmac100_stop_hw(struct ftgmac100
*priv
)
346 iowrite32(0, priv
->base
+ FTGMAC100_OFFSET_MACCR
);
349 static void ftgmac100_calc_mc_hash(struct ftgmac100
*priv
)
351 struct netdev_hw_addr
*ha
;
355 netdev_for_each_mc_addr(ha
, priv
->netdev
) {
356 u32 crc_val
= ether_crc_le(ETH_ALEN
, ha
->addr
);
358 crc_val
= (~(crc_val
>> 2)) & 0x3f;
360 priv
->maht1
|= 1ul << (crc_val
- 32);
362 priv
->maht0
|= 1ul << (crc_val
);
366 static void ftgmac100_set_rx_mode(struct net_device
*netdev
)
368 struct ftgmac100
*priv
= netdev_priv(netdev
);
370 /* Setup the hash filter */
371 ftgmac100_calc_mc_hash(priv
);
373 /* Interface down ? that's all there is to do */
374 if (!netif_running(netdev
))
378 iowrite32(priv
->maht0
, priv
->base
+ FTGMAC100_OFFSET_MAHT0
);
379 iowrite32(priv
->maht1
, priv
->base
+ FTGMAC100_OFFSET_MAHT1
);
381 /* Reconfigure MACCR */
382 ftgmac100_start_hw(priv
);
385 static int ftgmac100_alloc_rx_buf(struct ftgmac100
*priv
, unsigned int entry
,
386 struct ftgmac100_rxdes
*rxdes
, gfp_t gfp
)
388 struct net_device
*netdev
= priv
->netdev
;
393 skb
= netdev_alloc_skb_ip_align(netdev
, RX_BUF_SIZE
);
394 if (unlikely(!skb
)) {
396 netdev_warn(netdev
, "failed to allocate rx skb\n");
398 map
= priv
->rx_scratch_dma
;
400 map
= dma_map_single(priv
->dev
, skb
->data
, RX_BUF_SIZE
,
402 if (unlikely(dma_mapping_error(priv
->dev
, map
))) {
404 netdev_err(netdev
, "failed to map rx page\n");
405 dev_kfree_skb_any(skb
);
406 map
= priv
->rx_scratch_dma
;
413 priv
->rx_skbs
[entry
] = skb
;
415 /* Store DMA address into RX desc */
416 rxdes
->rxdes3
= cpu_to_le32(map
);
418 /* Ensure the above is ordered vs clearing the OWN bit */
421 /* Clean status (which resets own bit) */
422 if (entry
== (priv
->rx_q_entries
- 1))
423 rxdes
->rxdes0
= cpu_to_le32(priv
->rxdes0_edorr_mask
);
430 static unsigned int ftgmac100_next_rx_pointer(struct ftgmac100
*priv
,
431 unsigned int pointer
)
433 return (pointer
+ 1) & (priv
->rx_q_entries
- 1);
436 static void ftgmac100_rx_packet_error(struct ftgmac100
*priv
, u32 status
)
438 struct net_device
*netdev
= priv
->netdev
;
440 if (status
& FTGMAC100_RXDES0_RX_ERR
)
441 netdev
->stats
.rx_errors
++;
443 if (status
& FTGMAC100_RXDES0_CRC_ERR
)
444 netdev
->stats
.rx_crc_errors
++;
446 if (status
& (FTGMAC100_RXDES0_FTL
|
447 FTGMAC100_RXDES0_RUNT
|
448 FTGMAC100_RXDES0_RX_ODD_NB
))
449 netdev
->stats
.rx_length_errors
++;
452 static bool ftgmac100_rx_packet(struct ftgmac100
*priv
, int *processed
)
454 struct net_device
*netdev
= priv
->netdev
;
455 struct ftgmac100_rxdes
*rxdes
;
457 unsigned int pointer
, size
;
458 u32 status
, csum_vlan
;
461 /* Grab next RX descriptor */
462 pointer
= priv
->rx_pointer
;
463 rxdes
= &priv
->rxdes
[pointer
];
465 /* Grab descriptor status */
466 status
= le32_to_cpu(rxdes
->rxdes0
);
468 /* Do we have a packet ? */
469 if (!(status
& FTGMAC100_RXDES0_RXPKT_RDY
))
472 /* Order subsequent reads with the test for the ready bit */
475 /* We don't cope with fragmented RX packets */
476 if (unlikely(!(status
& FTGMAC100_RXDES0_FRS
) ||
477 !(status
& FTGMAC100_RXDES0_LRS
)))
480 /* Grab received size and csum vlan field in the descriptor */
481 size
= status
& FTGMAC100_RXDES0_VDBC
;
482 csum_vlan
= le32_to_cpu(rxdes
->rxdes1
);
484 /* Any error (other than csum offload) flagged ? */
485 if (unlikely(status
& RXDES0_ANY_ERROR
)) {
486 /* Correct for incorrect flagging of runt packets
487 * with vlan tags... Just accept a runt packet that
488 * has been flagged as vlan and whose size is at
491 if ((status
& FTGMAC100_RXDES0_RUNT
) &&
492 (csum_vlan
& FTGMAC100_RXDES1_VLANTAG_AVAIL
) &&
494 status
&= ~FTGMAC100_RXDES0_RUNT
;
496 /* Any error still in there ? */
497 if (status
& RXDES0_ANY_ERROR
) {
498 ftgmac100_rx_packet_error(priv
, status
);
503 /* If the packet had no skb (failed to allocate earlier)
504 * then try to allocate one and skip
506 skb
= priv
->rx_skbs
[pointer
];
507 if (!unlikely(skb
)) {
508 ftgmac100_alloc_rx_buf(priv
, pointer
, rxdes
, GFP_ATOMIC
);
512 if (unlikely(status
& FTGMAC100_RXDES0_MULTICAST
))
513 netdev
->stats
.multicast
++;
515 /* If the HW found checksum errors, bounce it to software.
517 * If we didn't, we need to see if the packet was recognized
518 * by HW as one of the supported checksummed protocols before
519 * we accept the HW test results.
521 if (netdev
->features
& NETIF_F_RXCSUM
) {
522 u32 err_bits
= FTGMAC100_RXDES1_TCP_CHKSUM_ERR
|
523 FTGMAC100_RXDES1_UDP_CHKSUM_ERR
|
524 FTGMAC100_RXDES1_IP_CHKSUM_ERR
;
525 if ((csum_vlan
& err_bits
) ||
526 !(csum_vlan
& FTGMAC100_RXDES1_PROT_MASK
))
527 skb
->ip_summed
= CHECKSUM_NONE
;
529 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
532 /* Transfer received size to skb */
535 /* Extract vlan tag */
536 if ((netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
) &&
537 (csum_vlan
& FTGMAC100_RXDES1_VLANTAG_AVAIL
))
538 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
),
541 /* Tear down DMA mapping, do necessary cache management */
542 map
= le32_to_cpu(rxdes
->rxdes3
);
544 #if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU)
545 /* When we don't have an iommu, we can save cycles by not
546 * invalidating the cache for the part of the packet that
549 dma_unmap_single(priv
->dev
, map
, size
, DMA_FROM_DEVICE
);
551 dma_unmap_single(priv
->dev
, map
, RX_BUF_SIZE
, DMA_FROM_DEVICE
);
555 /* Resplenish rx ring */
556 ftgmac100_alloc_rx_buf(priv
, pointer
, rxdes
, GFP_ATOMIC
);
557 priv
->rx_pointer
= ftgmac100_next_rx_pointer(priv
, pointer
);
559 skb
->protocol
= eth_type_trans(skb
, netdev
);
561 netdev
->stats
.rx_packets
++;
562 netdev
->stats
.rx_bytes
+= size
;
564 /* push packet to protocol stack */
565 if (skb
->ip_summed
== CHECKSUM_NONE
)
566 netif_receive_skb(skb
);
568 napi_gro_receive(&priv
->napi
, skb
);
574 /* Clean rxdes0 (which resets own bit) */
575 rxdes
->rxdes0
= cpu_to_le32(status
& priv
->rxdes0_edorr_mask
);
576 priv
->rx_pointer
= ftgmac100_next_rx_pointer(priv
, pointer
);
577 netdev
->stats
.rx_dropped
++;
581 static u32
ftgmac100_base_tx_ctlstat(struct ftgmac100
*priv
,
584 if (index
== (priv
->tx_q_entries
- 1))
585 return priv
->txdes0_edotr_mask
;
590 static unsigned int ftgmac100_next_tx_pointer(struct ftgmac100
*priv
,
591 unsigned int pointer
)
593 return (pointer
+ 1) & (priv
->tx_q_entries
- 1);
596 static u32
ftgmac100_tx_buf_avail(struct ftgmac100
*priv
)
598 /* Returns the number of available slots in the TX queue
600 * This always leaves one free slot so we don't have to
601 * worry about empty vs. full, and this simplifies the
602 * test for ftgmac100_tx_buf_cleanable() below
604 return (priv
->tx_clean_pointer
- priv
->tx_pointer
- 1) &
605 (priv
->tx_q_entries
- 1);
608 static bool ftgmac100_tx_buf_cleanable(struct ftgmac100
*priv
)
610 return priv
->tx_pointer
!= priv
->tx_clean_pointer
;
613 static void ftgmac100_free_tx_packet(struct ftgmac100
*priv
,
614 unsigned int pointer
,
616 struct ftgmac100_txdes
*txdes
,
619 dma_addr_t map
= le32_to_cpu(txdes
->txdes3
);
622 if (ctl_stat
& FTGMAC100_TXDES0_FTS
) {
623 len
= skb_headlen(skb
);
624 dma_unmap_single(priv
->dev
, map
, len
, DMA_TO_DEVICE
);
626 len
= FTGMAC100_TXDES0_TXBUF_SIZE(ctl_stat
);
627 dma_unmap_page(priv
->dev
, map
, len
, DMA_TO_DEVICE
);
630 /* Free SKB on last segment */
631 if (ctl_stat
& FTGMAC100_TXDES0_LTS
)
633 priv
->tx_skbs
[pointer
] = NULL
;
636 static bool ftgmac100_tx_complete_packet(struct ftgmac100
*priv
)
638 struct net_device
*netdev
= priv
->netdev
;
639 struct ftgmac100_txdes
*txdes
;
641 unsigned int pointer
;
644 pointer
= priv
->tx_clean_pointer
;
645 txdes
= &priv
->txdes
[pointer
];
647 ctl_stat
= le32_to_cpu(txdes
->txdes0
);
648 if (ctl_stat
& FTGMAC100_TXDES0_TXDMA_OWN
)
651 skb
= priv
->tx_skbs
[pointer
];
652 netdev
->stats
.tx_packets
++;
653 netdev
->stats
.tx_bytes
+= skb
->len
;
654 ftgmac100_free_tx_packet(priv
, pointer
, skb
, txdes
, ctl_stat
);
655 txdes
->txdes0
= cpu_to_le32(ctl_stat
& priv
->txdes0_edotr_mask
);
657 priv
->tx_clean_pointer
= ftgmac100_next_tx_pointer(priv
, pointer
);
662 static void ftgmac100_tx_complete(struct ftgmac100
*priv
)
664 struct net_device
*netdev
= priv
->netdev
;
666 /* Process all completed packets */
667 while (ftgmac100_tx_buf_cleanable(priv
) &&
668 ftgmac100_tx_complete_packet(priv
))
671 /* Restart queue if needed */
673 if (unlikely(netif_queue_stopped(netdev
) &&
674 ftgmac100_tx_buf_avail(priv
) >= TX_THRESHOLD
)) {
675 struct netdev_queue
*txq
;
677 txq
= netdev_get_tx_queue(netdev
, 0);
678 __netif_tx_lock(txq
, smp_processor_id());
679 if (netif_queue_stopped(netdev
) &&
680 ftgmac100_tx_buf_avail(priv
) >= TX_THRESHOLD
)
681 netif_wake_queue(netdev
);
682 __netif_tx_unlock(txq
);
686 static bool ftgmac100_prep_tx_csum(struct sk_buff
*skb
, u32
*csum_vlan
)
688 if (skb
->protocol
== cpu_to_be16(ETH_P_IP
)) {
689 u8 ip_proto
= ip_hdr(skb
)->protocol
;
691 *csum_vlan
|= FTGMAC100_TXDES1_IP_CHKSUM
;
694 *csum_vlan
|= FTGMAC100_TXDES1_TCP_CHKSUM
;
697 *csum_vlan
|= FTGMAC100_TXDES1_UDP_CHKSUM
;
703 return skb_checksum_help(skb
) == 0;
706 static netdev_tx_t
ftgmac100_hard_start_xmit(struct sk_buff
*skb
,
707 struct net_device
*netdev
)
709 struct ftgmac100
*priv
= netdev_priv(netdev
);
710 struct ftgmac100_txdes
*txdes
, *first
;
711 unsigned int pointer
, nfrags
, len
, i
, j
;
712 u32 f_ctl_stat
, ctl_stat
, csum_vlan
;
715 /* The HW doesn't pad small frames */
716 if (eth_skb_pad(skb
)) {
717 netdev
->stats
.tx_dropped
++;
721 /* Reject oversize packets */
722 if (unlikely(skb
->len
> MAX_PKT_SIZE
)) {
724 netdev_dbg(netdev
, "tx packet too big\n");
728 /* Do we have a limit on #fragments ? I yet have to get a reply
729 * from Aspeed. If there's one I haven't hit it.
731 nfrags
= skb_shinfo(skb
)->nr_frags
;
733 /* Setup HW checksumming */
735 if (skb
->ip_summed
== CHECKSUM_PARTIAL
&&
736 !ftgmac100_prep_tx_csum(skb
, &csum_vlan
))
740 if (skb_vlan_tag_present(skb
)) {
741 csum_vlan
|= FTGMAC100_TXDES1_INS_VLANTAG
;
742 csum_vlan
|= skb_vlan_tag_get(skb
) & 0xffff;
746 len
= skb_headlen(skb
);
748 /* Map the packet head */
749 map
= dma_map_single(priv
->dev
, skb
->data
, len
, DMA_TO_DEVICE
);
750 if (dma_mapping_error(priv
->dev
, map
)) {
752 netdev_err(netdev
, "map tx packet head failed\n");
756 /* Grab the next free tx descriptor */
757 pointer
= priv
->tx_pointer
;
758 txdes
= first
= &priv
->txdes
[pointer
];
760 /* Setup it up with the packet head. Don't write the head to the
763 priv
->tx_skbs
[pointer
] = skb
;
764 f_ctl_stat
= ftgmac100_base_tx_ctlstat(priv
, pointer
);
765 f_ctl_stat
|= FTGMAC100_TXDES0_TXDMA_OWN
;
766 f_ctl_stat
|= FTGMAC100_TXDES0_TXBUF_SIZE(len
);
767 f_ctl_stat
|= FTGMAC100_TXDES0_FTS
;
769 f_ctl_stat
|= FTGMAC100_TXDES0_LTS
;
770 txdes
->txdes3
= cpu_to_le32(map
);
771 txdes
->txdes1
= cpu_to_le32(csum_vlan
);
773 /* Next descriptor */
774 pointer
= ftgmac100_next_tx_pointer(priv
, pointer
);
776 /* Add the fragments */
777 for (i
= 0; i
< nfrags
; i
++) {
778 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
780 len
= skb_frag_size(frag
);
783 map
= skb_frag_dma_map(priv
->dev
, frag
, 0, len
,
785 if (dma_mapping_error(priv
->dev
, map
))
788 /* Setup descriptor */
789 priv
->tx_skbs
[pointer
] = skb
;
790 txdes
= &priv
->txdes
[pointer
];
791 ctl_stat
= ftgmac100_base_tx_ctlstat(priv
, pointer
);
792 ctl_stat
|= FTGMAC100_TXDES0_TXDMA_OWN
;
793 ctl_stat
|= FTGMAC100_TXDES0_TXBUF_SIZE(len
);
794 if (i
== (nfrags
- 1))
795 ctl_stat
|= FTGMAC100_TXDES0_LTS
;
796 txdes
->txdes0
= cpu_to_le32(ctl_stat
);
798 txdes
->txdes3
= cpu_to_le32(map
);
801 pointer
= ftgmac100_next_tx_pointer(priv
, pointer
);
804 /* Order the previous packet and descriptor udpates
805 * before setting the OWN bit on the first descriptor.
808 first
->txdes0
= cpu_to_le32(f_ctl_stat
);
810 /* Update next TX pointer */
811 priv
->tx_pointer
= pointer
;
813 /* If there isn't enough room for all the fragments of a new packet
814 * in the TX ring, stop the queue. The sequence below is race free
815 * vs. a concurrent restart in ftgmac100_poll()
817 if (unlikely(ftgmac100_tx_buf_avail(priv
) < TX_THRESHOLD
)) {
818 netif_stop_queue(netdev
);
819 /* Order the queue stop with the test below */
821 if (ftgmac100_tx_buf_avail(priv
) >= TX_THRESHOLD
)
822 netif_wake_queue(netdev
);
825 /* Poke transmitter to read the updated TX descriptors */
826 iowrite32(1, priv
->base
+ FTGMAC100_OFFSET_NPTXPD
);
832 netdev_err(netdev
, "map tx fragment failed\n");
835 pointer
= priv
->tx_pointer
;
836 ftgmac100_free_tx_packet(priv
, pointer
, skb
, first
, f_ctl_stat
);
837 first
->txdes0
= cpu_to_le32(f_ctl_stat
& priv
->txdes0_edotr_mask
);
839 /* Then all fragments */
840 for (j
= 0; j
< i
; j
++) {
841 pointer
= ftgmac100_next_tx_pointer(priv
, pointer
);
842 txdes
= &priv
->txdes
[pointer
];
843 ctl_stat
= le32_to_cpu(txdes
->txdes0
);
844 ftgmac100_free_tx_packet(priv
, pointer
, skb
, txdes
, ctl_stat
);
845 txdes
->txdes0
= cpu_to_le32(ctl_stat
& priv
->txdes0_edotr_mask
);
848 /* This cannot be reached if we successfully mapped the
849 * last fragment, so we know ftgmac100_free_tx_packet()
850 * hasn't freed the skb yet.
853 /* Drop the packet */
854 dev_kfree_skb_any(skb
);
855 netdev
->stats
.tx_dropped
++;
860 static void ftgmac100_free_buffers(struct ftgmac100
*priv
)
864 /* Free all RX buffers */
865 for (i
= 0; i
< priv
->rx_q_entries
; i
++) {
866 struct ftgmac100_rxdes
*rxdes
= &priv
->rxdes
[i
];
867 struct sk_buff
*skb
= priv
->rx_skbs
[i
];
868 dma_addr_t map
= le32_to_cpu(rxdes
->rxdes3
);
873 priv
->rx_skbs
[i
] = NULL
;
874 dma_unmap_single(priv
->dev
, map
, RX_BUF_SIZE
, DMA_FROM_DEVICE
);
875 dev_kfree_skb_any(skb
);
878 /* Free all TX buffers */
879 for (i
= 0; i
< priv
->tx_q_entries
; i
++) {
880 struct ftgmac100_txdes
*txdes
= &priv
->txdes
[i
];
881 struct sk_buff
*skb
= priv
->tx_skbs
[i
];
885 ftgmac100_free_tx_packet(priv
, i
, skb
, txdes
,
886 le32_to_cpu(txdes
->txdes0
));
890 static void ftgmac100_free_rings(struct ftgmac100
*priv
)
892 /* Free skb arrays */
893 kfree(priv
->rx_skbs
);
894 kfree(priv
->tx_skbs
);
896 /* Free descriptors */
898 dma_free_coherent(priv
->dev
, MAX_RX_QUEUE_ENTRIES
*
899 sizeof(struct ftgmac100_rxdes
),
900 priv
->rxdes
, priv
->rxdes_dma
);
904 dma_free_coherent(priv
->dev
, MAX_TX_QUEUE_ENTRIES
*
905 sizeof(struct ftgmac100_txdes
),
906 priv
->txdes
, priv
->txdes_dma
);
909 /* Free scratch packet buffer */
910 if (priv
->rx_scratch
)
911 dma_free_coherent(priv
->dev
, RX_BUF_SIZE
,
912 priv
->rx_scratch
, priv
->rx_scratch_dma
);
915 static int ftgmac100_alloc_rings(struct ftgmac100
*priv
)
917 /* Allocate skb arrays */
918 priv
->rx_skbs
= kcalloc(MAX_RX_QUEUE_ENTRIES
, sizeof(void *),
922 priv
->tx_skbs
= kcalloc(MAX_TX_QUEUE_ENTRIES
, sizeof(void *),
927 /* Allocate descriptors */
928 priv
->rxdes
= dma_alloc_coherent(priv
->dev
,
929 MAX_RX_QUEUE_ENTRIES
* sizeof(struct ftgmac100_rxdes
),
930 &priv
->rxdes_dma
, GFP_KERNEL
);
933 priv
->txdes
= dma_alloc_coherent(priv
->dev
,
934 MAX_TX_QUEUE_ENTRIES
* sizeof(struct ftgmac100_txdes
),
935 &priv
->txdes_dma
, GFP_KERNEL
);
939 /* Allocate scratch packet buffer */
940 priv
->rx_scratch
= dma_alloc_coherent(priv
->dev
,
942 &priv
->rx_scratch_dma
,
944 if (!priv
->rx_scratch
)
950 static void ftgmac100_init_rings(struct ftgmac100
*priv
)
952 struct ftgmac100_rxdes
*rxdes
= NULL
;
953 struct ftgmac100_txdes
*txdes
= NULL
;
956 /* Update entries counts */
957 priv
->rx_q_entries
= priv
->new_rx_q_entries
;
958 priv
->tx_q_entries
= priv
->new_tx_q_entries
;
960 if (WARN_ON(priv
->rx_q_entries
< MIN_RX_QUEUE_ENTRIES
))
963 /* Initialize RX ring */
964 for (i
= 0; i
< priv
->rx_q_entries
; i
++) {
965 rxdes
= &priv
->rxdes
[i
];
967 rxdes
->rxdes3
= cpu_to_le32(priv
->rx_scratch_dma
);
969 /* Mark the end of the ring */
970 rxdes
->rxdes0
|= cpu_to_le32(priv
->rxdes0_edorr_mask
);
972 if (WARN_ON(priv
->tx_q_entries
< MIN_RX_QUEUE_ENTRIES
))
975 /* Initialize TX ring */
976 for (i
= 0; i
< priv
->tx_q_entries
; i
++) {
977 txdes
= &priv
->txdes
[i
];
980 txdes
->txdes0
|= cpu_to_le32(priv
->txdes0_edotr_mask
);
983 static int ftgmac100_alloc_rx_buffers(struct ftgmac100
*priv
)
987 for (i
= 0; i
< priv
->rx_q_entries
; i
++) {
988 struct ftgmac100_rxdes
*rxdes
= &priv
->rxdes
[i
];
990 if (ftgmac100_alloc_rx_buf(priv
, i
, rxdes
, GFP_KERNEL
))
996 static void ftgmac100_adjust_link(struct net_device
*netdev
)
998 struct ftgmac100
*priv
= netdev_priv(netdev
);
999 struct phy_device
*phydev
= netdev
->phydev
;
1000 bool tx_pause
, rx_pause
;
1003 /* We store "no link" as speed 0 */
1007 new_speed
= phydev
->speed
;
1009 /* Grab pause settings from PHY if configured to do so */
1010 if (priv
->aneg_pause
) {
1011 rx_pause
= tx_pause
= phydev
->pause
;
1012 if (phydev
->asym_pause
)
1013 tx_pause
= !rx_pause
;
1015 rx_pause
= priv
->rx_pause
;
1016 tx_pause
= priv
->tx_pause
;
1019 /* Link hasn't changed, do nothing */
1020 if (phydev
->speed
== priv
->cur_speed
&&
1021 phydev
->duplex
== priv
->cur_duplex
&&
1022 rx_pause
== priv
->rx_pause
&&
1023 tx_pause
== priv
->tx_pause
)
1026 /* Print status if we have a link or we had one and just lost it,
1027 * don't print otherwise.
1029 if (new_speed
|| priv
->cur_speed
)
1030 phy_print_status(phydev
);
1032 priv
->cur_speed
= new_speed
;
1033 priv
->cur_duplex
= phydev
->duplex
;
1034 priv
->rx_pause
= rx_pause
;
1035 priv
->tx_pause
= tx_pause
;
1037 /* Link is down, do nothing else */
1041 /* Disable all interrupts */
1042 iowrite32(0, priv
->base
+ FTGMAC100_OFFSET_IER
);
1044 /* Reset the adapter asynchronously */
1045 schedule_work(&priv
->reset_task
);
1048 static int ftgmac100_mii_probe(struct ftgmac100
*priv
, phy_interface_t intf
)
1050 struct net_device
*netdev
= priv
->netdev
;
1051 struct phy_device
*phydev
;
1053 phydev
= phy_find_first(priv
->mii_bus
);
1055 netdev_info(netdev
, "%s: no PHY found\n", netdev
->name
);
1059 phydev
= phy_connect(netdev
, phydev_name(phydev
),
1060 &ftgmac100_adjust_link
, intf
);
1062 if (IS_ERR(phydev
)) {
1063 netdev_err(netdev
, "%s: Could not attach to PHY\n", netdev
->name
);
1064 return PTR_ERR(phydev
);
1067 /* Indicate that we support PAUSE frames (see comment in
1068 * Documentation/networking/phy.rst)
1070 phy_support_asym_pause(phydev
);
1072 /* Display what we found */
1073 phy_attached_info(phydev
);
1078 static int ftgmac100_mdiobus_read(struct mii_bus
*bus
, int phy_addr
, int regnum
)
1080 struct net_device
*netdev
= bus
->priv
;
1081 struct ftgmac100
*priv
= netdev_priv(netdev
);
1085 phycr
= ioread32(priv
->base
+ FTGMAC100_OFFSET_PHYCR
);
1087 /* preserve MDC cycle threshold */
1088 phycr
&= FTGMAC100_PHYCR_MDC_CYCTHR_MASK
;
1090 phycr
|= FTGMAC100_PHYCR_PHYAD(phy_addr
) |
1091 FTGMAC100_PHYCR_REGAD(regnum
) |
1092 FTGMAC100_PHYCR_MIIRD
;
1094 iowrite32(phycr
, priv
->base
+ FTGMAC100_OFFSET_PHYCR
);
1096 for (i
= 0; i
< 10; i
++) {
1097 phycr
= ioread32(priv
->base
+ FTGMAC100_OFFSET_PHYCR
);
1099 if ((phycr
& FTGMAC100_PHYCR_MIIRD
) == 0) {
1102 data
= ioread32(priv
->base
+ FTGMAC100_OFFSET_PHYDATA
);
1103 return FTGMAC100_PHYDATA_MIIRDATA(data
);
1109 netdev_err(netdev
, "mdio read timed out\n");
1113 static int ftgmac100_mdiobus_write(struct mii_bus
*bus
, int phy_addr
,
1114 int regnum
, u16 value
)
1116 struct net_device
*netdev
= bus
->priv
;
1117 struct ftgmac100
*priv
= netdev_priv(netdev
);
1122 phycr
= ioread32(priv
->base
+ FTGMAC100_OFFSET_PHYCR
);
1124 /* preserve MDC cycle threshold */
1125 phycr
&= FTGMAC100_PHYCR_MDC_CYCTHR_MASK
;
1127 phycr
|= FTGMAC100_PHYCR_PHYAD(phy_addr
) |
1128 FTGMAC100_PHYCR_REGAD(regnum
) |
1129 FTGMAC100_PHYCR_MIIWR
;
1131 data
= FTGMAC100_PHYDATA_MIIWDATA(value
);
1133 iowrite32(data
, priv
->base
+ FTGMAC100_OFFSET_PHYDATA
);
1134 iowrite32(phycr
, priv
->base
+ FTGMAC100_OFFSET_PHYCR
);
1136 for (i
= 0; i
< 10; i
++) {
1137 phycr
= ioread32(priv
->base
+ FTGMAC100_OFFSET_PHYCR
);
1139 if ((phycr
& FTGMAC100_PHYCR_MIIWR
) == 0)
1145 netdev_err(netdev
, "mdio write timed out\n");
1149 static void ftgmac100_get_drvinfo(struct net_device
*netdev
,
1150 struct ethtool_drvinfo
*info
)
1152 strlcpy(info
->driver
, DRV_NAME
, sizeof(info
->driver
));
1153 strlcpy(info
->version
, DRV_VERSION
, sizeof(info
->version
));
1154 strlcpy(info
->bus_info
, dev_name(&netdev
->dev
), sizeof(info
->bus_info
));
1157 static void ftgmac100_get_ringparam(struct net_device
*netdev
,
1158 struct ethtool_ringparam
*ering
)
1160 struct ftgmac100
*priv
= netdev_priv(netdev
);
1162 memset(ering
, 0, sizeof(*ering
));
1163 ering
->rx_max_pending
= MAX_RX_QUEUE_ENTRIES
;
1164 ering
->tx_max_pending
= MAX_TX_QUEUE_ENTRIES
;
1165 ering
->rx_pending
= priv
->rx_q_entries
;
1166 ering
->tx_pending
= priv
->tx_q_entries
;
1169 static int ftgmac100_set_ringparam(struct net_device
*netdev
,
1170 struct ethtool_ringparam
*ering
)
1172 struct ftgmac100
*priv
= netdev_priv(netdev
);
1174 if (ering
->rx_pending
> MAX_RX_QUEUE_ENTRIES
||
1175 ering
->tx_pending
> MAX_TX_QUEUE_ENTRIES
||
1176 ering
->rx_pending
< MIN_RX_QUEUE_ENTRIES
||
1177 ering
->tx_pending
< MIN_TX_QUEUE_ENTRIES
||
1178 !is_power_of_2(ering
->rx_pending
) ||
1179 !is_power_of_2(ering
->tx_pending
))
1182 priv
->new_rx_q_entries
= ering
->rx_pending
;
1183 priv
->new_tx_q_entries
= ering
->tx_pending
;
1184 if (netif_running(netdev
))
1185 schedule_work(&priv
->reset_task
);
1190 static void ftgmac100_get_pauseparam(struct net_device
*netdev
,
1191 struct ethtool_pauseparam
*pause
)
1193 struct ftgmac100
*priv
= netdev_priv(netdev
);
1195 pause
->autoneg
= priv
->aneg_pause
;
1196 pause
->tx_pause
= priv
->tx_pause
;
1197 pause
->rx_pause
= priv
->rx_pause
;
1200 static int ftgmac100_set_pauseparam(struct net_device
*netdev
,
1201 struct ethtool_pauseparam
*pause
)
1203 struct ftgmac100
*priv
= netdev_priv(netdev
);
1204 struct phy_device
*phydev
= netdev
->phydev
;
1206 priv
->aneg_pause
= pause
->autoneg
;
1207 priv
->tx_pause
= pause
->tx_pause
;
1208 priv
->rx_pause
= pause
->rx_pause
;
1211 phy_set_asym_pause(phydev
, pause
->rx_pause
, pause
->tx_pause
);
1213 if (netif_running(netdev
)) {
1214 if (!(phydev
&& priv
->aneg_pause
))
1215 ftgmac100_config_pause(priv
);
1221 static const struct ethtool_ops ftgmac100_ethtool_ops
= {
1222 .get_drvinfo
= ftgmac100_get_drvinfo
,
1223 .get_link
= ethtool_op_get_link
,
1224 .get_link_ksettings
= phy_ethtool_get_link_ksettings
,
1225 .set_link_ksettings
= phy_ethtool_set_link_ksettings
,
1226 .nway_reset
= phy_ethtool_nway_reset
,
1227 .get_ringparam
= ftgmac100_get_ringparam
,
1228 .set_ringparam
= ftgmac100_set_ringparam
,
1229 .get_pauseparam
= ftgmac100_get_pauseparam
,
1230 .set_pauseparam
= ftgmac100_set_pauseparam
,
1233 static irqreturn_t
ftgmac100_interrupt(int irq
, void *dev_id
)
1235 struct net_device
*netdev
= dev_id
;
1236 struct ftgmac100
*priv
= netdev_priv(netdev
);
1237 unsigned int status
, new_mask
= FTGMAC100_INT_BAD
;
1239 /* Fetch and clear interrupt bits, process abnormal ones */
1240 status
= ioread32(priv
->base
+ FTGMAC100_OFFSET_ISR
);
1241 iowrite32(status
, priv
->base
+ FTGMAC100_OFFSET_ISR
);
1242 if (unlikely(status
& FTGMAC100_INT_BAD
)) {
1244 /* RX buffer unavailable */
1245 if (status
& FTGMAC100_INT_NO_RXBUF
)
1246 netdev
->stats
.rx_over_errors
++;
1248 /* received packet lost due to RX FIFO full */
1249 if (status
& FTGMAC100_INT_RPKT_LOST
)
1250 netdev
->stats
.rx_fifo_errors
++;
1252 /* sent packet lost due to excessive TX collision */
1253 if (status
& FTGMAC100_INT_XPKT_LOST
)
1254 netdev
->stats
.tx_fifo_errors
++;
1256 /* AHB error -> Reset the chip */
1257 if (status
& FTGMAC100_INT_AHB_ERR
) {
1258 if (net_ratelimit())
1260 "AHB bus error ! Resetting chip.\n");
1261 iowrite32(0, priv
->base
+ FTGMAC100_OFFSET_IER
);
1262 schedule_work(&priv
->reset_task
);
1266 /* We may need to restart the MAC after such errors, delay
1267 * this until after we have freed some Rx buffers though
1269 priv
->need_mac_restart
= true;
1271 /* Disable those errors until we restart */
1272 new_mask
&= ~status
;
1275 /* Only enable "bad" interrupts while NAPI is on */
1276 iowrite32(new_mask
, priv
->base
+ FTGMAC100_OFFSET_IER
);
1278 /* Schedule NAPI bh */
1279 napi_schedule_irqoff(&priv
->napi
);
1284 static bool ftgmac100_check_rx(struct ftgmac100
*priv
)
1286 struct ftgmac100_rxdes
*rxdes
= &priv
->rxdes
[priv
->rx_pointer
];
1288 /* Do we have a packet ? */
1289 return !!(rxdes
->rxdes0
& cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY
));
1292 static int ftgmac100_poll(struct napi_struct
*napi
, int budget
)
1294 struct ftgmac100
*priv
= container_of(napi
, struct ftgmac100
, napi
);
1298 /* Handle TX completions */
1299 if (ftgmac100_tx_buf_cleanable(priv
))
1300 ftgmac100_tx_complete(priv
);
1302 /* Handle RX packets */
1304 more
= ftgmac100_rx_packet(priv
, &work_done
);
1305 } while (more
&& work_done
< budget
);
1308 /* The interrupt is telling us to kick the MAC back to life
1309 * after an RX overflow
1311 if (unlikely(priv
->need_mac_restart
)) {
1312 ftgmac100_start_hw(priv
);
1314 /* Re-enable "bad" interrupts */
1315 iowrite32(FTGMAC100_INT_BAD
,
1316 priv
->base
+ FTGMAC100_OFFSET_IER
);
1319 /* As long as we are waiting for transmit packets to be
1320 * completed we keep NAPI going
1322 if (ftgmac100_tx_buf_cleanable(priv
))
1325 if (work_done
< budget
) {
1326 /* We are about to re-enable all interrupts. However
1327 * the HW has been latching RX/TX packet interrupts while
1328 * they were masked. So we clear them first, then we need
1329 * to re-check if there's something to process
1331 iowrite32(FTGMAC100_INT_RXTX
,
1332 priv
->base
+ FTGMAC100_OFFSET_ISR
);
1334 /* Push the above (and provides a barrier vs. subsequent
1335 * reads of the descriptor).
1337 ioread32(priv
->base
+ FTGMAC100_OFFSET_ISR
);
1339 /* Check RX and TX descriptors for more work to do */
1340 if (ftgmac100_check_rx(priv
) ||
1341 ftgmac100_tx_buf_cleanable(priv
))
1344 /* deschedule NAPI */
1345 napi_complete(napi
);
1347 /* enable all interrupts */
1348 iowrite32(FTGMAC100_INT_ALL
,
1349 priv
->base
+ FTGMAC100_OFFSET_IER
);
1355 static int ftgmac100_init_all(struct ftgmac100
*priv
, bool ignore_alloc_err
)
1359 /* Re-init descriptors (adjust queue sizes) */
1360 ftgmac100_init_rings(priv
);
1362 /* Realloc rx descriptors */
1363 err
= ftgmac100_alloc_rx_buffers(priv
);
1364 if (err
&& !ignore_alloc_err
)
1367 /* Reinit and restart HW */
1368 ftgmac100_init_hw(priv
);
1369 ftgmac100_config_pause(priv
);
1370 ftgmac100_start_hw(priv
);
1372 /* Re-enable the device */
1373 napi_enable(&priv
->napi
);
1374 netif_start_queue(priv
->netdev
);
1376 /* Enable all interrupts */
1377 iowrite32(FTGMAC100_INT_ALL
, priv
->base
+ FTGMAC100_OFFSET_IER
);
1382 static void ftgmac100_reset_task(struct work_struct
*work
)
1384 struct ftgmac100
*priv
= container_of(work
, struct ftgmac100
,
1386 struct net_device
*netdev
= priv
->netdev
;
1389 netdev_dbg(netdev
, "Resetting NIC...\n");
1391 /* Lock the world */
1394 mutex_lock(&netdev
->phydev
->lock
);
1396 mutex_lock(&priv
->mii_bus
->mdio_lock
);
1399 /* Check if the interface is still up */
1400 if (!netif_running(netdev
))
1403 /* Stop the network stack */
1404 netif_trans_update(netdev
);
1405 napi_disable(&priv
->napi
);
1406 netif_tx_disable(netdev
);
1408 /* Stop and reset the MAC */
1409 ftgmac100_stop_hw(priv
);
1410 err
= ftgmac100_reset_and_config_mac(priv
);
1412 /* Not much we can do ... it might come back... */
1413 netdev_err(netdev
, "attempting to continue...\n");
1416 /* Free all rx and tx buffers */
1417 ftgmac100_free_buffers(priv
);
1419 /* Setup everything again and restart chip */
1420 ftgmac100_init_all(priv
, true);
1422 netdev_dbg(netdev
, "Reset done !\n");
1425 mutex_unlock(&priv
->mii_bus
->mdio_lock
);
1427 mutex_unlock(&netdev
->phydev
->lock
);
1431 static int ftgmac100_open(struct net_device
*netdev
)
1433 struct ftgmac100
*priv
= netdev_priv(netdev
);
1436 /* Allocate ring buffers */
1437 err
= ftgmac100_alloc_rings(priv
);
1439 netdev_err(netdev
, "Failed to allocate descriptors\n");
1443 /* When using NC-SI we force the speed to 100Mbit/s full duplex,
1445 * Otherwise we leave it set to 0 (no link), the link
1446 * message from the PHY layer will handle setting it up to
1447 * something else if needed.
1449 if (priv
->use_ncsi
) {
1450 priv
->cur_duplex
= DUPLEX_FULL
;
1451 priv
->cur_speed
= SPEED_100
;
1453 priv
->cur_duplex
= 0;
1454 priv
->cur_speed
= 0;
1457 /* Reset the hardware */
1458 err
= ftgmac100_reset_and_config_mac(priv
);
1462 /* Initialize NAPI */
1463 netif_napi_add(netdev
, &priv
->napi
, ftgmac100_poll
, 64);
1465 /* Grab our interrupt */
1466 err
= request_irq(netdev
->irq
, ftgmac100_interrupt
, 0, netdev
->name
, netdev
);
1468 netdev_err(netdev
, "failed to request irq %d\n", netdev
->irq
);
1472 /* Start things up */
1473 err
= ftgmac100_init_all(priv
, false);
1475 netdev_err(netdev
, "Failed to allocate packet buffers\n");
1479 if (netdev
->phydev
) {
1480 /* If we have a PHY, start polling */
1481 phy_start(netdev
->phydev
);
1482 } else if (priv
->use_ncsi
) {
1483 /* If using NC-SI, set our carrier on and start the stack */
1484 netif_carrier_on(netdev
);
1486 /* Start the NCSI device */
1487 err
= ncsi_start_dev(priv
->ndev
);
1495 napi_disable(&priv
->napi
);
1496 netif_stop_queue(netdev
);
1498 ftgmac100_free_buffers(priv
);
1499 free_irq(netdev
->irq
, netdev
);
1501 netif_napi_del(&priv
->napi
);
1503 iowrite32(0, priv
->base
+ FTGMAC100_OFFSET_IER
);
1504 ftgmac100_free_rings(priv
);
1508 static int ftgmac100_stop(struct net_device
*netdev
)
1510 struct ftgmac100
*priv
= netdev_priv(netdev
);
1512 /* Note about the reset task: We are called with the rtnl lock
1513 * held, so we are synchronized against the core of the reset
1514 * task. We must not try to synchronously cancel it otherwise
1515 * we can deadlock. But since it will test for netif_running()
1516 * which has already been cleared by the net core, we don't
1517 * anything special to do.
1520 /* disable all interrupts */
1521 iowrite32(0, priv
->base
+ FTGMAC100_OFFSET_IER
);
1523 netif_stop_queue(netdev
);
1524 napi_disable(&priv
->napi
);
1525 netif_napi_del(&priv
->napi
);
1527 phy_stop(netdev
->phydev
);
1528 else if (priv
->use_ncsi
)
1529 ncsi_stop_dev(priv
->ndev
);
1531 ftgmac100_stop_hw(priv
);
1532 free_irq(netdev
->irq
, netdev
);
1533 ftgmac100_free_buffers(priv
);
1534 ftgmac100_free_rings(priv
);
1540 static int ftgmac100_do_ioctl(struct net_device
*netdev
, struct ifreq
*ifr
, int cmd
)
1542 if (!netdev
->phydev
)
1545 return phy_mii_ioctl(netdev
->phydev
, ifr
, cmd
);
1548 static void ftgmac100_tx_timeout(struct net_device
*netdev
)
1550 struct ftgmac100
*priv
= netdev_priv(netdev
);
1552 /* Disable all interrupts */
1553 iowrite32(0, priv
->base
+ FTGMAC100_OFFSET_IER
);
1555 /* Do the reset outside of interrupt context */
1556 schedule_work(&priv
->reset_task
);
1559 static int ftgmac100_set_features(struct net_device
*netdev
,
1560 netdev_features_t features
)
1562 struct ftgmac100
*priv
= netdev_priv(netdev
);
1563 netdev_features_t changed
= netdev
->features
^ features
;
1565 if (!netif_running(netdev
))
1568 /* Update the vlan filtering bit */
1569 if (changed
& NETIF_F_HW_VLAN_CTAG_RX
) {
1572 maccr
= ioread32(priv
->base
+ FTGMAC100_OFFSET_MACCR
);
1573 if (priv
->netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)
1574 maccr
|= FTGMAC100_MACCR_RM_VLAN
;
1576 maccr
&= ~FTGMAC100_MACCR_RM_VLAN
;
1577 iowrite32(maccr
, priv
->base
+ FTGMAC100_OFFSET_MACCR
);
1583 #ifdef CONFIG_NET_POLL_CONTROLLER
1584 static void ftgmac100_poll_controller(struct net_device
*netdev
)
1586 unsigned long flags
;
1588 local_irq_save(flags
);
1589 ftgmac100_interrupt(netdev
->irq
, netdev
);
1590 local_irq_restore(flags
);
1594 static const struct net_device_ops ftgmac100_netdev_ops
= {
1595 .ndo_open
= ftgmac100_open
,
1596 .ndo_stop
= ftgmac100_stop
,
1597 .ndo_start_xmit
= ftgmac100_hard_start_xmit
,
1598 .ndo_set_mac_address
= ftgmac100_set_mac_addr
,
1599 .ndo_validate_addr
= eth_validate_addr
,
1600 .ndo_do_ioctl
= ftgmac100_do_ioctl
,
1601 .ndo_tx_timeout
= ftgmac100_tx_timeout
,
1602 .ndo_set_rx_mode
= ftgmac100_set_rx_mode
,
1603 .ndo_set_features
= ftgmac100_set_features
,
1604 #ifdef CONFIG_NET_POLL_CONTROLLER
1605 .ndo_poll_controller
= ftgmac100_poll_controller
,
1607 .ndo_vlan_rx_add_vid
= ncsi_vlan_rx_add_vid
,
1608 .ndo_vlan_rx_kill_vid
= ncsi_vlan_rx_kill_vid
,
1611 static int ftgmac100_setup_mdio(struct net_device
*netdev
)
1613 struct ftgmac100
*priv
= netdev_priv(netdev
);
1614 struct platform_device
*pdev
= to_platform_device(priv
->dev
);
1615 phy_interface_t phy_intf
= PHY_INTERFACE_MODE_RGMII
;
1616 struct device_node
*np
= pdev
->dev
.of_node
;
1620 /* initialize mdio bus */
1621 priv
->mii_bus
= mdiobus_alloc();
1625 if (of_device_is_compatible(np
, "aspeed,ast2400-mac") ||
1626 of_device_is_compatible(np
, "aspeed,ast2500-mac")) {
1627 /* The AST2600 has a separate MDIO controller */
1629 /* For the AST2400 and AST2500 this driver only supports the
1630 * old MDIO interface
1632 reg
= ioread32(priv
->base
+ FTGMAC100_OFFSET_REVR
);
1633 reg
&= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE
;
1634 iowrite32(reg
, priv
->base
+ FTGMAC100_OFFSET_REVR
);
1637 /* Get PHY mode from device-tree */
1639 /* Default to RGMII. It's a gigabit part after all */
1640 err
= of_get_phy_mode(np
, &phy_intf
);
1642 phy_intf
= PHY_INTERFACE_MODE_RGMII
;
1644 /* Aspeed only supports these. I don't know about other IP
1645 * block vendors so I'm going to just let them through for
1646 * now. Note that this is only a warning if for some obscure
1647 * reason the DT really means to lie about it or it's a newer
1648 * part we don't know about.
1650 * On the Aspeed SoC there are additionally straps and SCU
1651 * control bits that could tell us what the interface is
1652 * (or allow us to configure it while the IP block is held
1653 * in reset). For now I chose to keep this driver away from
1654 * those SoC specific bits and assume the device-tree is
1655 * right and the SCU has been configured properly by pinmux
1658 if (priv
->is_aspeed
&&
1659 phy_intf
!= PHY_INTERFACE_MODE_RMII
&&
1660 phy_intf
!= PHY_INTERFACE_MODE_RGMII
&&
1661 phy_intf
!= PHY_INTERFACE_MODE_RGMII_ID
&&
1662 phy_intf
!= PHY_INTERFACE_MODE_RGMII_RXID
&&
1663 phy_intf
!= PHY_INTERFACE_MODE_RGMII_TXID
) {
1665 "Unsupported PHY mode %s !\n",
1666 phy_modes(phy_intf
));
1670 priv
->mii_bus
->name
= "ftgmac100_mdio";
1671 snprintf(priv
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%s-%d",
1672 pdev
->name
, pdev
->id
);
1673 priv
->mii_bus
->parent
= priv
->dev
;
1674 priv
->mii_bus
->priv
= priv
->netdev
;
1675 priv
->mii_bus
->read
= ftgmac100_mdiobus_read
;
1676 priv
->mii_bus
->write
= ftgmac100_mdiobus_write
;
1678 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1679 priv
->mii_bus
->irq
[i
] = PHY_POLL
;
1681 err
= mdiobus_register(priv
->mii_bus
);
1683 dev_err(priv
->dev
, "Cannot register MDIO bus!\n");
1684 goto err_register_mdiobus
;
1687 err
= ftgmac100_mii_probe(priv
, phy_intf
);
1689 dev_err(priv
->dev
, "MII Probe failed!\n");
1696 mdiobus_unregister(priv
->mii_bus
);
1697 err_register_mdiobus
:
1698 mdiobus_free(priv
->mii_bus
);
1702 static void ftgmac100_destroy_mdio(struct net_device
*netdev
)
1704 struct ftgmac100
*priv
= netdev_priv(netdev
);
1706 if (!netdev
->phydev
)
1709 phy_disconnect(netdev
->phydev
);
1710 mdiobus_unregister(priv
->mii_bus
);
1711 mdiobus_free(priv
->mii_bus
);
1714 static void ftgmac100_ncsi_handler(struct ncsi_dev
*nd
)
1716 if (unlikely(nd
->state
!= ncsi_dev_state_functional
))
1719 netdev_dbg(nd
->dev
, "NCSI interface %s\n",
1720 nd
->link_up
? "up" : "down");
1723 static int ftgmac100_setup_clk(struct ftgmac100
*priv
)
1728 clk
= devm_clk_get(priv
->dev
, NULL
/* MACCLK */);
1730 return PTR_ERR(clk
);
1732 rc
= clk_prepare_enable(priv
->clk
);
1736 /* Aspeed specifies a 100MHz clock is required for up to
1737 * 1000Mbit link speeds. As NCSI is limited to 100Mbit, 25MHz
1740 rc
= clk_set_rate(priv
->clk
, priv
->use_ncsi
? FTGMAC_25MHZ
:
1745 /* RCLK is for RMII, typically used for NCSI. Optional because its not
1746 * necessary if it's the AST2400 MAC, or the MAC is configured for
1747 * RGMII, or the controller is not an ASPEED-based controller.
1749 priv
->rclk
= devm_clk_get_optional(priv
->dev
, "RCLK");
1750 rc
= clk_prepare_enable(priv
->rclk
);
1755 clk_disable_unprepare(priv
->clk
);
1760 static int ftgmac100_probe(struct platform_device
*pdev
)
1762 struct resource
*res
;
1764 struct net_device
*netdev
;
1765 struct ftgmac100
*priv
;
1766 struct device_node
*np
;
1772 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1776 irq
= platform_get_irq(pdev
, 0);
1780 /* setup net_device */
1781 netdev
= alloc_etherdev(sizeof(*priv
));
1784 goto err_alloc_etherdev
;
1787 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
1789 netdev
->ethtool_ops
= &ftgmac100_ethtool_ops
;
1790 netdev
->netdev_ops
= &ftgmac100_netdev_ops
;
1791 netdev
->watchdog_timeo
= 5 * HZ
;
1793 platform_set_drvdata(pdev
, netdev
);
1795 /* setup private data */
1796 priv
= netdev_priv(netdev
);
1797 priv
->netdev
= netdev
;
1798 priv
->dev
= &pdev
->dev
;
1799 INIT_WORK(&priv
->reset_task
, ftgmac100_reset_task
);
1802 priv
->res
= request_mem_region(res
->start
, resource_size(res
),
1803 dev_name(&pdev
->dev
));
1805 dev_err(&pdev
->dev
, "Could not reserve memory region\n");
1810 priv
->base
= ioremap(res
->start
, resource_size(res
));
1812 dev_err(&pdev
->dev
, "Failed to ioremap ethernet registers\n");
1820 priv
->tx_pause
= true;
1821 priv
->rx_pause
= true;
1822 priv
->aneg_pause
= true;
1824 /* MAC address from chip or random one */
1825 ftgmac100_initial_mac(priv
);
1827 np
= pdev
->dev
.of_node
;
1828 if (np
&& (of_device_is_compatible(np
, "aspeed,ast2400-mac") ||
1829 of_device_is_compatible(np
, "aspeed,ast2500-mac") ||
1830 of_device_is_compatible(np
, "aspeed,ast2600-mac"))) {
1831 priv
->rxdes0_edorr_mask
= BIT(30);
1832 priv
->txdes0_edotr_mask
= BIT(30);
1833 priv
->is_aspeed
= true;
1835 priv
->rxdes0_edorr_mask
= BIT(15);
1836 priv
->txdes0_edotr_mask
= BIT(15);
1839 if (np
&& of_get_property(np
, "use-ncsi", NULL
)) {
1840 if (!IS_ENABLED(CONFIG_NET_NCSI
)) {
1841 dev_err(&pdev
->dev
, "NCSI stack not enabled\n");
1845 dev_info(&pdev
->dev
, "Using NCSI interface\n");
1846 priv
->use_ncsi
= true;
1847 priv
->ndev
= ncsi_register_dev(netdev
, ftgmac100_ncsi_handler
);
1850 } else if (np
&& of_get_property(np
, "phy-handle", NULL
)) {
1851 struct phy_device
*phy
;
1853 phy
= of_phy_get_and_connect(priv
->netdev
, np
,
1854 &ftgmac100_adjust_link
);
1856 dev_err(&pdev
->dev
, "Failed to connect to phy\n");
1857 goto err_setup_mdio
;
1860 /* Indicate that we support PAUSE frames (see comment in
1861 * Documentation/networking/phy.txt)
1863 phy_support_asym_pause(phy
);
1865 /* Display what we found */
1866 phy_attached_info(phy
);
1867 } else if (np
&& !of_get_child_by_name(np
, "mdio")) {
1868 /* Support legacy ASPEED devicetree descriptions that decribe a
1869 * MAC with an embedded MDIO controller but have no "mdio"
1870 * child node. Automatically scan the MDIO bus for available
1873 priv
->use_ncsi
= false;
1874 err
= ftgmac100_setup_mdio(netdev
);
1876 goto err_setup_mdio
;
1879 if (priv
->is_aspeed
) {
1880 err
= ftgmac100_setup_clk(priv
);
1885 /* Default ring sizes */
1886 priv
->rx_q_entries
= priv
->new_rx_q_entries
= DEF_RX_QUEUE_ENTRIES
;
1887 priv
->tx_q_entries
= priv
->new_tx_q_entries
= DEF_TX_QUEUE_ENTRIES
;
1889 /* Base feature set */
1890 netdev
->hw_features
= NETIF_F_RXCSUM
| NETIF_F_HW_CSUM
|
1891 NETIF_F_GRO
| NETIF_F_SG
| NETIF_F_HW_VLAN_CTAG_RX
|
1892 NETIF_F_HW_VLAN_CTAG_TX
;
1895 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
1897 /* AST2400 doesn't have working HW checksum generation */
1898 if (np
&& (of_device_is_compatible(np
, "aspeed,ast2400-mac")))
1899 netdev
->hw_features
&= ~NETIF_F_HW_CSUM
;
1900 if (np
&& of_get_property(np
, "no-hw-checksum", NULL
))
1901 netdev
->hw_features
&= ~(NETIF_F_HW_CSUM
| NETIF_F_RXCSUM
);
1902 netdev
->features
|= netdev
->hw_features
;
1904 /* register network device */
1905 err
= register_netdev(netdev
);
1907 dev_err(&pdev
->dev
, "Failed to register netdev\n");
1908 goto err_register_netdev
;
1911 netdev_info(netdev
, "irq %d, mapped at %p\n", netdev
->irq
, priv
->base
);
1915 err_register_netdev
:
1916 clk_disable_unprepare(priv
->rclk
);
1917 clk_disable_unprepare(priv
->clk
);
1919 ftgmac100_destroy_mdio(netdev
);
1921 iounmap(priv
->base
);
1923 release_resource(priv
->res
);
1925 free_netdev(netdev
);
1930 static int ftgmac100_remove(struct platform_device
*pdev
)
1932 struct net_device
*netdev
;
1933 struct ftgmac100
*priv
;
1935 netdev
= platform_get_drvdata(pdev
);
1936 priv
= netdev_priv(netdev
);
1938 unregister_netdev(netdev
);
1940 clk_disable_unprepare(priv
->rclk
);
1941 clk_disable_unprepare(priv
->clk
);
1943 /* There's a small chance the reset task will have been re-queued,
1944 * during stop, make sure it's gone before we free the structure.
1946 cancel_work_sync(&priv
->reset_task
);
1948 ftgmac100_destroy_mdio(netdev
);
1950 iounmap(priv
->base
);
1951 release_resource(priv
->res
);
1953 netif_napi_del(&priv
->napi
);
1954 free_netdev(netdev
);
1958 static const struct of_device_id ftgmac100_of_match
[] = {
1959 { .compatible
= "faraday,ftgmac100" },
1962 MODULE_DEVICE_TABLE(of
, ftgmac100_of_match
);
1964 static struct platform_driver ftgmac100_driver
= {
1965 .probe
= ftgmac100_probe
,
1966 .remove
= ftgmac100_remove
,
1969 .of_match_table
= ftgmac100_of_match
,
1972 module_platform_driver(ftgmac100_driver
);
1974 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
1975 MODULE_DESCRIPTION("FTGMAC100 driver");
1976 MODULE_LICENSE("GPL");