2 * Faraday FTGMAC100 Gigabit Ethernet
4 * (C) Copyright 2009-2011 Faraday Technology
5 * Po-Yu Chuang <ratbert@faraday-tech.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24 #include <linux/clk.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/etherdevice.h>
27 #include <linux/ethtool.h>
28 #include <linux/interrupt.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
33 #include <linux/phy.h>
34 #include <linux/platform_device.h>
35 #include <linux/property.h>
36 #include <linux/crc32.h>
37 #include <linux/if_vlan.h>
38 #include <linux/of_net.h>
42 #include "ftgmac100.h"
44 #define DRV_NAME "ftgmac100"
45 #define DRV_VERSION "0.7"
47 /* Arbitrary values, I am not sure the HW has limits */
48 #define MAX_RX_QUEUE_ENTRIES 1024
49 #define MAX_TX_QUEUE_ENTRIES 1024
50 #define MIN_RX_QUEUE_ENTRIES 32
51 #define MIN_TX_QUEUE_ENTRIES 32
54 #define DEF_RX_QUEUE_ENTRIES 128
55 #define DEF_TX_QUEUE_ENTRIES 128
57 #define MAX_PKT_SIZE 1536
58 #define RX_BUF_SIZE MAX_PKT_SIZE /* must be smaller than 0x3fff */
60 /* Min number of tx ring entries before stopping queue */
61 #define TX_THRESHOLD (MAX_SKB_FRAGS + 1)
63 #define FTGMAC_100MHZ 100000000
64 #define FTGMAC_25MHZ 25000000
72 unsigned int rx_q_entries
;
73 struct ftgmac100_rxdes
*rxdes
;
75 struct sk_buff
**rx_skbs
;
76 unsigned int rx_pointer
;
77 u32 rxdes0_edorr_mask
;
80 unsigned int tx_q_entries
;
81 struct ftgmac100_txdes
*txdes
;
83 struct sk_buff
**tx_skbs
;
84 unsigned int tx_clean_pointer
;
85 unsigned int tx_pointer
;
86 u32 txdes0_edotr_mask
;
88 /* Used to signal the reset task of ring change request */
89 unsigned int new_rx_q_entries
;
90 unsigned int new_tx_q_entries
;
92 /* Scratch page to use when rx skb alloc fails */
94 dma_addr_t rx_scratch_dma
;
96 /* Component structures */
97 struct net_device
*netdev
;
99 struct ncsi_dev
*ndev
;
100 struct napi_struct napi
;
101 struct work_struct reset_task
;
102 struct mii_bus
*mii_bus
;
105 /* Link management */
110 /* Multicast filter settings */
114 /* Flow control settings */
120 bool need_mac_restart
;
124 static int ftgmac100_reset_mac(struct ftgmac100
*priv
, u32 maccr
)
126 struct net_device
*netdev
= priv
->netdev
;
129 /* NOTE: reset clears all registers */
130 iowrite32(maccr
, priv
->base
+ FTGMAC100_OFFSET_MACCR
);
131 iowrite32(maccr
| FTGMAC100_MACCR_SW_RST
,
132 priv
->base
+ FTGMAC100_OFFSET_MACCR
);
133 for (i
= 0; i
< 200; i
++) {
136 maccr
= ioread32(priv
->base
+ FTGMAC100_OFFSET_MACCR
);
137 if (!(maccr
& FTGMAC100_MACCR_SW_RST
))
143 netdev_err(netdev
, "Hardware reset failed\n");
147 static int ftgmac100_reset_and_config_mac(struct ftgmac100
*priv
)
151 switch (priv
->cur_speed
) {
153 case 0: /* no link */
157 maccr
|= FTGMAC100_MACCR_FAST_MODE
;
161 maccr
|= FTGMAC100_MACCR_GIGA_MODE
;
164 netdev_err(priv
->netdev
, "Unknown speed %d !\n",
169 /* (Re)initialize the queue pointers */
170 priv
->rx_pointer
= 0;
171 priv
->tx_clean_pointer
= 0;
172 priv
->tx_pointer
= 0;
174 /* The doc says reset twice with 10us interval */
175 if (ftgmac100_reset_mac(priv
, maccr
))
177 usleep_range(10, 1000);
178 return ftgmac100_reset_mac(priv
, maccr
);
181 static void ftgmac100_write_mac_addr(struct ftgmac100
*priv
, const u8
*mac
)
183 unsigned int maddr
= mac
[0] << 8 | mac
[1];
184 unsigned int laddr
= mac
[2] << 24 | mac
[3] << 16 | mac
[4] << 8 | mac
[5];
186 iowrite32(maddr
, priv
->base
+ FTGMAC100_OFFSET_MAC_MADR
);
187 iowrite32(laddr
, priv
->base
+ FTGMAC100_OFFSET_MAC_LADR
);
190 static void ftgmac100_initial_mac(struct ftgmac100
*priv
)
197 addr
= device_get_mac_address(priv
->dev
, mac
, ETH_ALEN
);
199 ether_addr_copy(priv
->netdev
->dev_addr
, mac
);
200 dev_info(priv
->dev
, "Read MAC address %pM from device tree\n",
205 m
= ioread32(priv
->base
+ FTGMAC100_OFFSET_MAC_MADR
);
206 l
= ioread32(priv
->base
+ FTGMAC100_OFFSET_MAC_LADR
);
208 mac
[0] = (m
>> 8) & 0xff;
210 mac
[2] = (l
>> 24) & 0xff;
211 mac
[3] = (l
>> 16) & 0xff;
212 mac
[4] = (l
>> 8) & 0xff;
215 if (is_valid_ether_addr(mac
)) {
216 ether_addr_copy(priv
->netdev
->dev_addr
, mac
);
217 dev_info(priv
->dev
, "Read MAC address %pM from chip\n", mac
);
219 eth_hw_addr_random(priv
->netdev
);
220 dev_info(priv
->dev
, "Generated random MAC address %pM\n",
221 priv
->netdev
->dev_addr
);
225 static int ftgmac100_set_mac_addr(struct net_device
*dev
, void *p
)
229 ret
= eth_prepare_mac_addr_change(dev
, p
);
233 eth_commit_mac_addr_change(dev
, p
);
234 ftgmac100_write_mac_addr(netdev_priv(dev
), dev
->dev_addr
);
239 static void ftgmac100_config_pause(struct ftgmac100
*priv
)
241 u32 fcr
= FTGMAC100_FCR_PAUSE_TIME(16);
243 /* Throttle tx queue when receiving pause frames */
245 fcr
|= FTGMAC100_FCR_FC_EN
;
247 /* Enables sending pause frames when the RX queue is past a
251 fcr
|= FTGMAC100_FCR_FCTHR_EN
;
253 iowrite32(fcr
, priv
->base
+ FTGMAC100_OFFSET_FCR
);
256 static void ftgmac100_init_hw(struct ftgmac100
*priv
)
258 u32 reg
, rfifo_sz
, tfifo_sz
;
260 /* Clear stale interrupts */
261 reg
= ioread32(priv
->base
+ FTGMAC100_OFFSET_ISR
);
262 iowrite32(reg
, priv
->base
+ FTGMAC100_OFFSET_ISR
);
264 /* Setup RX ring buffer base */
265 iowrite32(priv
->rxdes_dma
, priv
->base
+ FTGMAC100_OFFSET_RXR_BADR
);
267 /* Setup TX ring buffer base */
268 iowrite32(priv
->txdes_dma
, priv
->base
+ FTGMAC100_OFFSET_NPTXR_BADR
);
270 /* Configure RX buffer size */
271 iowrite32(FTGMAC100_RBSR_SIZE(RX_BUF_SIZE
),
272 priv
->base
+ FTGMAC100_OFFSET_RBSR
);
274 /* Set RX descriptor autopoll */
275 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1),
276 priv
->base
+ FTGMAC100_OFFSET_APTC
);
278 /* Write MAC address */
279 ftgmac100_write_mac_addr(priv
, priv
->netdev
->dev_addr
);
281 /* Write multicast filter */
282 iowrite32(priv
->maht0
, priv
->base
+ FTGMAC100_OFFSET_MAHT0
);
283 iowrite32(priv
->maht1
, priv
->base
+ FTGMAC100_OFFSET_MAHT1
);
285 /* Configure descriptor sizes and increase burst sizes according
286 * to values in Aspeed SDK. The FIFO arbitration is enabled and
287 * the thresholds set based on the recommended values in the
288 * AST2400 specification.
290 iowrite32(FTGMAC100_DBLAC_RXDES_SIZE(2) | /* 2*8 bytes RX descs */
291 FTGMAC100_DBLAC_TXDES_SIZE(2) | /* 2*8 bytes TX descs */
292 FTGMAC100_DBLAC_RXBURST_SIZE(3) | /* 512 bytes max RX bursts */
293 FTGMAC100_DBLAC_TXBURST_SIZE(3) | /* 512 bytes max TX bursts */
294 FTGMAC100_DBLAC_RX_THR_EN
| /* Enable fifo threshold arb */
295 FTGMAC100_DBLAC_RXFIFO_HTHR(6) | /* 6/8 of FIFO high threshold */
296 FTGMAC100_DBLAC_RXFIFO_LTHR(2), /* 2/8 of FIFO low threshold */
297 priv
->base
+ FTGMAC100_OFFSET_DBLAC
);
299 /* Interrupt mitigation configured for 1 interrupt/packet. HW interrupt
300 * mitigation doesn't seem to provide any benefit with NAPI so leave
303 iowrite32(FTGMAC100_ITC_RXINT_THR(1) |
304 FTGMAC100_ITC_TXINT_THR(1),
305 priv
->base
+ FTGMAC100_OFFSET_ITC
);
307 /* Configure FIFO sizes in the TPAFCR register */
308 reg
= ioread32(priv
->base
+ FTGMAC100_OFFSET_FEAR
);
309 rfifo_sz
= reg
& 0x00000007;
310 tfifo_sz
= (reg
>> 3) & 0x00000007;
311 reg
= ioread32(priv
->base
+ FTGMAC100_OFFSET_TPAFCR
);
313 reg
|= (tfifo_sz
<< 27);
314 reg
|= (rfifo_sz
<< 24);
315 iowrite32(reg
, priv
->base
+ FTGMAC100_OFFSET_TPAFCR
);
318 static void ftgmac100_start_hw(struct ftgmac100
*priv
)
320 u32 maccr
= ioread32(priv
->base
+ FTGMAC100_OFFSET_MACCR
);
322 /* Keep the original GMAC and FAST bits */
323 maccr
&= (FTGMAC100_MACCR_FAST_MODE
| FTGMAC100_MACCR_GIGA_MODE
);
325 /* Add all the main enable bits */
326 maccr
|= FTGMAC100_MACCR_TXDMA_EN
|
327 FTGMAC100_MACCR_RXDMA_EN
|
328 FTGMAC100_MACCR_TXMAC_EN
|
329 FTGMAC100_MACCR_RXMAC_EN
|
330 FTGMAC100_MACCR_CRC_APD
|
331 FTGMAC100_MACCR_PHY_LINK_LEVEL
|
332 FTGMAC100_MACCR_RX_RUNT
|
333 FTGMAC100_MACCR_RX_BROADPKT
;
335 /* Add other bits as needed */
336 if (priv
->cur_duplex
== DUPLEX_FULL
)
337 maccr
|= FTGMAC100_MACCR_FULLDUP
;
338 if (priv
->netdev
->flags
& IFF_PROMISC
)
339 maccr
|= FTGMAC100_MACCR_RX_ALL
;
340 if (priv
->netdev
->flags
& IFF_ALLMULTI
)
341 maccr
|= FTGMAC100_MACCR_RX_MULTIPKT
;
342 else if (netdev_mc_count(priv
->netdev
))
343 maccr
|= FTGMAC100_MACCR_HT_MULTI_EN
;
345 /* Vlan filtering enabled */
346 if (priv
->netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)
347 maccr
|= FTGMAC100_MACCR_RM_VLAN
;
350 iowrite32(maccr
, priv
->base
+ FTGMAC100_OFFSET_MACCR
);
353 static void ftgmac100_stop_hw(struct ftgmac100
*priv
)
355 iowrite32(0, priv
->base
+ FTGMAC100_OFFSET_MACCR
);
358 static void ftgmac100_calc_mc_hash(struct ftgmac100
*priv
)
360 struct netdev_hw_addr
*ha
;
364 netdev_for_each_mc_addr(ha
, priv
->netdev
) {
365 u32 crc_val
= ether_crc_le(ETH_ALEN
, ha
->addr
);
367 crc_val
= (~(crc_val
>> 2)) & 0x3f;
369 priv
->maht1
|= 1ul << (crc_val
- 32);
371 priv
->maht0
|= 1ul << (crc_val
);
375 static void ftgmac100_set_rx_mode(struct net_device
*netdev
)
377 struct ftgmac100
*priv
= netdev_priv(netdev
);
379 /* Setup the hash filter */
380 ftgmac100_calc_mc_hash(priv
);
382 /* Interface down ? that's all there is to do */
383 if (!netif_running(netdev
))
387 iowrite32(priv
->maht0
, priv
->base
+ FTGMAC100_OFFSET_MAHT0
);
388 iowrite32(priv
->maht1
, priv
->base
+ FTGMAC100_OFFSET_MAHT1
);
390 /* Reconfigure MACCR */
391 ftgmac100_start_hw(priv
);
394 static int ftgmac100_alloc_rx_buf(struct ftgmac100
*priv
, unsigned int entry
,
395 struct ftgmac100_rxdes
*rxdes
, gfp_t gfp
)
397 struct net_device
*netdev
= priv
->netdev
;
402 skb
= netdev_alloc_skb_ip_align(netdev
, RX_BUF_SIZE
);
403 if (unlikely(!skb
)) {
405 netdev_warn(netdev
, "failed to allocate rx skb\n");
407 map
= priv
->rx_scratch_dma
;
409 map
= dma_map_single(priv
->dev
, skb
->data
, RX_BUF_SIZE
,
411 if (unlikely(dma_mapping_error(priv
->dev
, map
))) {
413 netdev_err(netdev
, "failed to map rx page\n");
414 dev_kfree_skb_any(skb
);
415 map
= priv
->rx_scratch_dma
;
422 priv
->rx_skbs
[entry
] = skb
;
424 /* Store DMA address into RX desc */
425 rxdes
->rxdes3
= cpu_to_le32(map
);
427 /* Ensure the above is ordered vs clearing the OWN bit */
430 /* Clean status (which resets own bit) */
431 if (entry
== (priv
->rx_q_entries
- 1))
432 rxdes
->rxdes0
= cpu_to_le32(priv
->rxdes0_edorr_mask
);
439 static unsigned int ftgmac100_next_rx_pointer(struct ftgmac100
*priv
,
440 unsigned int pointer
)
442 return (pointer
+ 1) & (priv
->rx_q_entries
- 1);
445 static void ftgmac100_rx_packet_error(struct ftgmac100
*priv
, u32 status
)
447 struct net_device
*netdev
= priv
->netdev
;
449 if (status
& FTGMAC100_RXDES0_RX_ERR
)
450 netdev
->stats
.rx_errors
++;
452 if (status
& FTGMAC100_RXDES0_CRC_ERR
)
453 netdev
->stats
.rx_crc_errors
++;
455 if (status
& (FTGMAC100_RXDES0_FTL
|
456 FTGMAC100_RXDES0_RUNT
|
457 FTGMAC100_RXDES0_RX_ODD_NB
))
458 netdev
->stats
.rx_length_errors
++;
461 static bool ftgmac100_rx_packet(struct ftgmac100
*priv
, int *processed
)
463 struct net_device
*netdev
= priv
->netdev
;
464 struct ftgmac100_rxdes
*rxdes
;
466 unsigned int pointer
, size
;
467 u32 status
, csum_vlan
;
470 /* Grab next RX descriptor */
471 pointer
= priv
->rx_pointer
;
472 rxdes
= &priv
->rxdes
[pointer
];
474 /* Grab descriptor status */
475 status
= le32_to_cpu(rxdes
->rxdes0
);
477 /* Do we have a packet ? */
478 if (!(status
& FTGMAC100_RXDES0_RXPKT_RDY
))
481 /* Order subsequent reads with the test for the ready bit */
484 /* We don't cope with fragmented RX packets */
485 if (unlikely(!(status
& FTGMAC100_RXDES0_FRS
) ||
486 !(status
& FTGMAC100_RXDES0_LRS
)))
489 /* Grab received size and csum vlan field in the descriptor */
490 size
= status
& FTGMAC100_RXDES0_VDBC
;
491 csum_vlan
= le32_to_cpu(rxdes
->rxdes1
);
493 /* Any error (other than csum offload) flagged ? */
494 if (unlikely(status
& RXDES0_ANY_ERROR
)) {
495 /* Correct for incorrect flagging of runt packets
496 * with vlan tags... Just accept a runt packet that
497 * has been flagged as vlan and whose size is at
500 if ((status
& FTGMAC100_RXDES0_RUNT
) &&
501 (csum_vlan
& FTGMAC100_RXDES1_VLANTAG_AVAIL
) &&
503 status
&= ~FTGMAC100_RXDES0_RUNT
;
505 /* Any error still in there ? */
506 if (status
& RXDES0_ANY_ERROR
) {
507 ftgmac100_rx_packet_error(priv
, status
);
512 /* If the packet had no skb (failed to allocate earlier)
513 * then try to allocate one and skip
515 skb
= priv
->rx_skbs
[pointer
];
516 if (!unlikely(skb
)) {
517 ftgmac100_alloc_rx_buf(priv
, pointer
, rxdes
, GFP_ATOMIC
);
521 if (unlikely(status
& FTGMAC100_RXDES0_MULTICAST
))
522 netdev
->stats
.multicast
++;
524 /* If the HW found checksum errors, bounce it to software.
526 * If we didn't, we need to see if the packet was recognized
527 * by HW as one of the supported checksummed protocols before
528 * we accept the HW test results.
530 if (netdev
->features
& NETIF_F_RXCSUM
) {
531 u32 err_bits
= FTGMAC100_RXDES1_TCP_CHKSUM_ERR
|
532 FTGMAC100_RXDES1_UDP_CHKSUM_ERR
|
533 FTGMAC100_RXDES1_IP_CHKSUM_ERR
;
534 if ((csum_vlan
& err_bits
) ||
535 !(csum_vlan
& FTGMAC100_RXDES1_PROT_MASK
))
536 skb
->ip_summed
= CHECKSUM_NONE
;
538 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
541 /* Transfer received size to skb */
544 /* Extract vlan tag */
545 if ((netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
) &&
546 (csum_vlan
& FTGMAC100_RXDES1_VLANTAG_AVAIL
))
547 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
),
550 /* Tear down DMA mapping, do necessary cache management */
551 map
= le32_to_cpu(rxdes
->rxdes3
);
553 #if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU)
554 /* When we don't have an iommu, we can save cycles by not
555 * invalidating the cache for the part of the packet that
558 dma_unmap_single(priv
->dev
, map
, size
, DMA_FROM_DEVICE
);
560 dma_unmap_single(priv
->dev
, map
, RX_BUF_SIZE
, DMA_FROM_DEVICE
);
564 /* Resplenish rx ring */
565 ftgmac100_alloc_rx_buf(priv
, pointer
, rxdes
, GFP_ATOMIC
);
566 priv
->rx_pointer
= ftgmac100_next_rx_pointer(priv
, pointer
);
568 skb
->protocol
= eth_type_trans(skb
, netdev
);
570 netdev
->stats
.rx_packets
++;
571 netdev
->stats
.rx_bytes
+= size
;
573 /* push packet to protocol stack */
574 if (skb
->ip_summed
== CHECKSUM_NONE
)
575 netif_receive_skb(skb
);
577 napi_gro_receive(&priv
->napi
, skb
);
583 /* Clean rxdes0 (which resets own bit) */
584 rxdes
->rxdes0
= cpu_to_le32(status
& priv
->rxdes0_edorr_mask
);
585 priv
->rx_pointer
= ftgmac100_next_rx_pointer(priv
, pointer
);
586 netdev
->stats
.rx_dropped
++;
590 static u32
ftgmac100_base_tx_ctlstat(struct ftgmac100
*priv
,
593 if (index
== (priv
->tx_q_entries
- 1))
594 return priv
->txdes0_edotr_mask
;
599 static unsigned int ftgmac100_next_tx_pointer(struct ftgmac100
*priv
,
600 unsigned int pointer
)
602 return (pointer
+ 1) & (priv
->tx_q_entries
- 1);
605 static u32
ftgmac100_tx_buf_avail(struct ftgmac100
*priv
)
607 /* Returns the number of available slots in the TX queue
609 * This always leaves one free slot so we don't have to
610 * worry about empty vs. full, and this simplifies the
611 * test for ftgmac100_tx_buf_cleanable() below
613 return (priv
->tx_clean_pointer
- priv
->tx_pointer
- 1) &
614 (priv
->tx_q_entries
- 1);
617 static bool ftgmac100_tx_buf_cleanable(struct ftgmac100
*priv
)
619 return priv
->tx_pointer
!= priv
->tx_clean_pointer
;
622 static void ftgmac100_free_tx_packet(struct ftgmac100
*priv
,
623 unsigned int pointer
,
625 struct ftgmac100_txdes
*txdes
,
628 dma_addr_t map
= le32_to_cpu(txdes
->txdes3
);
631 if (ctl_stat
& FTGMAC100_TXDES0_FTS
) {
632 len
= skb_headlen(skb
);
633 dma_unmap_single(priv
->dev
, map
, len
, DMA_TO_DEVICE
);
635 len
= FTGMAC100_TXDES0_TXBUF_SIZE(ctl_stat
);
636 dma_unmap_page(priv
->dev
, map
, len
, DMA_TO_DEVICE
);
639 /* Free SKB on last segment */
640 if (ctl_stat
& FTGMAC100_TXDES0_LTS
)
642 priv
->tx_skbs
[pointer
] = NULL
;
645 static bool ftgmac100_tx_complete_packet(struct ftgmac100
*priv
)
647 struct net_device
*netdev
= priv
->netdev
;
648 struct ftgmac100_txdes
*txdes
;
650 unsigned int pointer
;
653 pointer
= priv
->tx_clean_pointer
;
654 txdes
= &priv
->txdes
[pointer
];
656 ctl_stat
= le32_to_cpu(txdes
->txdes0
);
657 if (ctl_stat
& FTGMAC100_TXDES0_TXDMA_OWN
)
660 skb
= priv
->tx_skbs
[pointer
];
661 netdev
->stats
.tx_packets
++;
662 netdev
->stats
.tx_bytes
+= skb
->len
;
663 ftgmac100_free_tx_packet(priv
, pointer
, skb
, txdes
, ctl_stat
);
664 txdes
->txdes0
= cpu_to_le32(ctl_stat
& priv
->txdes0_edotr_mask
);
666 priv
->tx_clean_pointer
= ftgmac100_next_tx_pointer(priv
, pointer
);
671 static void ftgmac100_tx_complete(struct ftgmac100
*priv
)
673 struct net_device
*netdev
= priv
->netdev
;
675 /* Process all completed packets */
676 while (ftgmac100_tx_buf_cleanable(priv
) &&
677 ftgmac100_tx_complete_packet(priv
))
680 /* Restart queue if needed */
682 if (unlikely(netif_queue_stopped(netdev
) &&
683 ftgmac100_tx_buf_avail(priv
) >= TX_THRESHOLD
)) {
684 struct netdev_queue
*txq
;
686 txq
= netdev_get_tx_queue(netdev
, 0);
687 __netif_tx_lock(txq
, smp_processor_id());
688 if (netif_queue_stopped(netdev
) &&
689 ftgmac100_tx_buf_avail(priv
) >= TX_THRESHOLD
)
690 netif_wake_queue(netdev
);
691 __netif_tx_unlock(txq
);
695 static bool ftgmac100_prep_tx_csum(struct sk_buff
*skb
, u32
*csum_vlan
)
697 if (skb
->protocol
== cpu_to_be16(ETH_P_IP
)) {
698 u8 ip_proto
= ip_hdr(skb
)->protocol
;
700 *csum_vlan
|= FTGMAC100_TXDES1_IP_CHKSUM
;
703 *csum_vlan
|= FTGMAC100_TXDES1_TCP_CHKSUM
;
706 *csum_vlan
|= FTGMAC100_TXDES1_UDP_CHKSUM
;
712 return skb_checksum_help(skb
) == 0;
715 static netdev_tx_t
ftgmac100_hard_start_xmit(struct sk_buff
*skb
,
716 struct net_device
*netdev
)
718 struct ftgmac100
*priv
= netdev_priv(netdev
);
719 struct ftgmac100_txdes
*txdes
, *first
;
720 unsigned int pointer
, nfrags
, len
, i
, j
;
721 u32 f_ctl_stat
, ctl_stat
, csum_vlan
;
724 /* The HW doesn't pad small frames */
725 if (eth_skb_pad(skb
)) {
726 netdev
->stats
.tx_dropped
++;
730 /* Reject oversize packets */
731 if (unlikely(skb
->len
> MAX_PKT_SIZE
)) {
733 netdev_dbg(netdev
, "tx packet too big\n");
737 /* Do we have a limit on #fragments ? I yet have to get a reply
738 * from Aspeed. If there's one I haven't hit it.
740 nfrags
= skb_shinfo(skb
)->nr_frags
;
743 len
= skb_headlen(skb
);
745 /* Map the packet head */
746 map
= dma_map_single(priv
->dev
, skb
->data
, len
, DMA_TO_DEVICE
);
747 if (dma_mapping_error(priv
->dev
, map
)) {
749 netdev_err(netdev
, "map tx packet head failed\n");
753 /* Grab the next free tx descriptor */
754 pointer
= priv
->tx_pointer
;
755 txdes
= first
= &priv
->txdes
[pointer
];
757 /* Setup it up with the packet head. Don't write the head to the
760 priv
->tx_skbs
[pointer
] = skb
;
761 f_ctl_stat
= ftgmac100_base_tx_ctlstat(priv
, pointer
);
762 f_ctl_stat
|= FTGMAC100_TXDES0_TXDMA_OWN
;
763 f_ctl_stat
|= FTGMAC100_TXDES0_TXBUF_SIZE(len
);
764 f_ctl_stat
|= FTGMAC100_TXDES0_FTS
;
766 f_ctl_stat
|= FTGMAC100_TXDES0_LTS
;
767 txdes
->txdes3
= cpu_to_le32(map
);
769 /* Setup HW checksumming */
771 if (skb
->ip_summed
== CHECKSUM_PARTIAL
&&
772 !ftgmac100_prep_tx_csum(skb
, &csum_vlan
))
776 if (skb_vlan_tag_present(skb
)) {
777 csum_vlan
|= FTGMAC100_TXDES1_INS_VLANTAG
;
778 csum_vlan
|= skb_vlan_tag_get(skb
) & 0xffff;
781 txdes
->txdes1
= cpu_to_le32(csum_vlan
);
783 /* Next descriptor */
784 pointer
= ftgmac100_next_tx_pointer(priv
, pointer
);
786 /* Add the fragments */
787 for (i
= 0; i
< nfrags
; i
++) {
788 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
793 map
= skb_frag_dma_map(priv
->dev
, frag
, 0, len
,
795 if (dma_mapping_error(priv
->dev
, map
))
798 /* Setup descriptor */
799 priv
->tx_skbs
[pointer
] = skb
;
800 txdes
= &priv
->txdes
[pointer
];
801 ctl_stat
= ftgmac100_base_tx_ctlstat(priv
, pointer
);
802 ctl_stat
|= FTGMAC100_TXDES0_TXDMA_OWN
;
803 ctl_stat
|= FTGMAC100_TXDES0_TXBUF_SIZE(len
);
804 if (i
== (nfrags
- 1))
805 ctl_stat
|= FTGMAC100_TXDES0_LTS
;
806 txdes
->txdes0
= cpu_to_le32(ctl_stat
);
808 txdes
->txdes3
= cpu_to_le32(map
);
811 pointer
= ftgmac100_next_tx_pointer(priv
, pointer
);
814 /* Order the previous packet and descriptor udpates
815 * before setting the OWN bit on the first descriptor.
818 first
->txdes0
= cpu_to_le32(f_ctl_stat
);
820 /* Update next TX pointer */
821 priv
->tx_pointer
= pointer
;
823 /* If there isn't enough room for all the fragments of a new packet
824 * in the TX ring, stop the queue. The sequence below is race free
825 * vs. a concurrent restart in ftgmac100_poll()
827 if (unlikely(ftgmac100_tx_buf_avail(priv
) < TX_THRESHOLD
)) {
828 netif_stop_queue(netdev
);
829 /* Order the queue stop with the test below */
831 if (ftgmac100_tx_buf_avail(priv
) >= TX_THRESHOLD
)
832 netif_wake_queue(netdev
);
835 /* Poke transmitter to read the updated TX descriptors */
836 iowrite32(1, priv
->base
+ FTGMAC100_OFFSET_NPTXPD
);
842 netdev_err(netdev
, "map tx fragment failed\n");
845 pointer
= priv
->tx_pointer
;
846 ftgmac100_free_tx_packet(priv
, pointer
, skb
, first
, f_ctl_stat
);
847 first
->txdes0
= cpu_to_le32(f_ctl_stat
& priv
->txdes0_edotr_mask
);
849 /* Then all fragments */
850 for (j
= 0; j
< i
; j
++) {
851 pointer
= ftgmac100_next_tx_pointer(priv
, pointer
);
852 txdes
= &priv
->txdes
[pointer
];
853 ctl_stat
= le32_to_cpu(txdes
->txdes0
);
854 ftgmac100_free_tx_packet(priv
, pointer
, skb
, txdes
, ctl_stat
);
855 txdes
->txdes0
= cpu_to_le32(ctl_stat
& priv
->txdes0_edotr_mask
);
858 /* This cannot be reached if we successfully mapped the
859 * last fragment, so we know ftgmac100_free_tx_packet()
860 * hasn't freed the skb yet.
863 /* Drop the packet */
864 dev_kfree_skb_any(skb
);
865 netdev
->stats
.tx_dropped
++;
870 static void ftgmac100_free_buffers(struct ftgmac100
*priv
)
874 /* Free all RX buffers */
875 for (i
= 0; i
< priv
->rx_q_entries
; i
++) {
876 struct ftgmac100_rxdes
*rxdes
= &priv
->rxdes
[i
];
877 struct sk_buff
*skb
= priv
->rx_skbs
[i
];
878 dma_addr_t map
= le32_to_cpu(rxdes
->rxdes3
);
883 priv
->rx_skbs
[i
] = NULL
;
884 dma_unmap_single(priv
->dev
, map
, RX_BUF_SIZE
, DMA_FROM_DEVICE
);
885 dev_kfree_skb_any(skb
);
888 /* Free all TX buffers */
889 for (i
= 0; i
< priv
->tx_q_entries
; i
++) {
890 struct ftgmac100_txdes
*txdes
= &priv
->txdes
[i
];
891 struct sk_buff
*skb
= priv
->tx_skbs
[i
];
895 ftgmac100_free_tx_packet(priv
, i
, skb
, txdes
,
896 le32_to_cpu(txdes
->txdes0
));
900 static void ftgmac100_free_rings(struct ftgmac100
*priv
)
902 /* Free skb arrays */
903 kfree(priv
->rx_skbs
);
904 kfree(priv
->tx_skbs
);
906 /* Free descriptors */
908 dma_free_coherent(priv
->dev
, MAX_RX_QUEUE_ENTRIES
*
909 sizeof(struct ftgmac100_rxdes
),
910 priv
->rxdes
, priv
->rxdes_dma
);
914 dma_free_coherent(priv
->dev
, MAX_TX_QUEUE_ENTRIES
*
915 sizeof(struct ftgmac100_txdes
),
916 priv
->txdes
, priv
->txdes_dma
);
919 /* Free scratch packet buffer */
920 if (priv
->rx_scratch
)
921 dma_free_coherent(priv
->dev
, RX_BUF_SIZE
,
922 priv
->rx_scratch
, priv
->rx_scratch_dma
);
925 static int ftgmac100_alloc_rings(struct ftgmac100
*priv
)
927 /* Allocate skb arrays */
928 priv
->rx_skbs
= kcalloc(MAX_RX_QUEUE_ENTRIES
, sizeof(void *),
932 priv
->tx_skbs
= kcalloc(MAX_TX_QUEUE_ENTRIES
, sizeof(void *),
937 /* Allocate descriptors */
938 priv
->rxdes
= dma_alloc_coherent(priv
->dev
,
939 MAX_RX_QUEUE_ENTRIES
* sizeof(struct ftgmac100_rxdes
),
940 &priv
->rxdes_dma
, GFP_KERNEL
);
943 priv
->txdes
= dma_alloc_coherent(priv
->dev
,
944 MAX_TX_QUEUE_ENTRIES
* sizeof(struct ftgmac100_txdes
),
945 &priv
->txdes_dma
, GFP_KERNEL
);
949 /* Allocate scratch packet buffer */
950 priv
->rx_scratch
= dma_alloc_coherent(priv
->dev
,
952 &priv
->rx_scratch_dma
,
954 if (!priv
->rx_scratch
)
960 static void ftgmac100_init_rings(struct ftgmac100
*priv
)
962 struct ftgmac100_rxdes
*rxdes
= NULL
;
963 struct ftgmac100_txdes
*txdes
= NULL
;
966 /* Update entries counts */
967 priv
->rx_q_entries
= priv
->new_rx_q_entries
;
968 priv
->tx_q_entries
= priv
->new_tx_q_entries
;
970 if (WARN_ON(priv
->rx_q_entries
< MIN_RX_QUEUE_ENTRIES
))
973 /* Initialize RX ring */
974 for (i
= 0; i
< priv
->rx_q_entries
; i
++) {
975 rxdes
= &priv
->rxdes
[i
];
977 rxdes
->rxdes3
= cpu_to_le32(priv
->rx_scratch_dma
);
979 /* Mark the end of the ring */
980 rxdes
->rxdes0
|= cpu_to_le32(priv
->rxdes0_edorr_mask
);
982 if (WARN_ON(priv
->tx_q_entries
< MIN_RX_QUEUE_ENTRIES
))
985 /* Initialize TX ring */
986 for (i
= 0; i
< priv
->tx_q_entries
; i
++) {
987 txdes
= &priv
->txdes
[i
];
990 txdes
->txdes0
|= cpu_to_le32(priv
->txdes0_edotr_mask
);
993 static int ftgmac100_alloc_rx_buffers(struct ftgmac100
*priv
)
997 for (i
= 0; i
< priv
->rx_q_entries
; i
++) {
998 struct ftgmac100_rxdes
*rxdes
= &priv
->rxdes
[i
];
1000 if (ftgmac100_alloc_rx_buf(priv
, i
, rxdes
, GFP_KERNEL
))
1006 static void ftgmac100_adjust_link(struct net_device
*netdev
)
1008 struct ftgmac100
*priv
= netdev_priv(netdev
);
1009 struct phy_device
*phydev
= netdev
->phydev
;
1010 bool tx_pause
, rx_pause
;
1013 /* We store "no link" as speed 0 */
1017 new_speed
= phydev
->speed
;
1019 /* Grab pause settings from PHY if configured to do so */
1020 if (priv
->aneg_pause
) {
1021 rx_pause
= tx_pause
= phydev
->pause
;
1022 if (phydev
->asym_pause
)
1023 tx_pause
= !rx_pause
;
1025 rx_pause
= priv
->rx_pause
;
1026 tx_pause
= priv
->tx_pause
;
1029 /* Link hasn't changed, do nothing */
1030 if (phydev
->speed
== priv
->cur_speed
&&
1031 phydev
->duplex
== priv
->cur_duplex
&&
1032 rx_pause
== priv
->rx_pause
&&
1033 tx_pause
== priv
->tx_pause
)
1036 /* Print status if we have a link or we had one and just lost it,
1037 * don't print otherwise.
1039 if (new_speed
|| priv
->cur_speed
)
1040 phy_print_status(phydev
);
1042 priv
->cur_speed
= new_speed
;
1043 priv
->cur_duplex
= phydev
->duplex
;
1044 priv
->rx_pause
= rx_pause
;
1045 priv
->tx_pause
= tx_pause
;
1047 /* Link is down, do nothing else */
1051 /* Disable all interrupts */
1052 iowrite32(0, priv
->base
+ FTGMAC100_OFFSET_IER
);
1054 /* Reset the adapter asynchronously */
1055 schedule_work(&priv
->reset_task
);
1058 static int ftgmac100_mii_probe(struct ftgmac100
*priv
, phy_interface_t intf
)
1060 struct net_device
*netdev
= priv
->netdev
;
1061 struct phy_device
*phydev
;
1063 phydev
= phy_find_first(priv
->mii_bus
);
1065 netdev_info(netdev
, "%s: no PHY found\n", netdev
->name
);
1069 phydev
= phy_connect(netdev
, phydev_name(phydev
),
1070 &ftgmac100_adjust_link
, intf
);
1072 if (IS_ERR(phydev
)) {
1073 netdev_err(netdev
, "%s: Could not attach to PHY\n", netdev
->name
);
1074 return PTR_ERR(phydev
);
1077 /* Indicate that we support PAUSE frames (see comment in
1078 * Documentation/networking/phy.txt)
1080 phy_support_asym_pause(phydev
);
1082 /* Display what we found */
1083 phy_attached_info(phydev
);
1088 static int ftgmac100_mdiobus_read(struct mii_bus
*bus
, int phy_addr
, int regnum
)
1090 struct net_device
*netdev
= bus
->priv
;
1091 struct ftgmac100
*priv
= netdev_priv(netdev
);
1095 phycr
= ioread32(priv
->base
+ FTGMAC100_OFFSET_PHYCR
);
1097 /* preserve MDC cycle threshold */
1098 phycr
&= FTGMAC100_PHYCR_MDC_CYCTHR_MASK
;
1100 phycr
|= FTGMAC100_PHYCR_PHYAD(phy_addr
) |
1101 FTGMAC100_PHYCR_REGAD(regnum
) |
1102 FTGMAC100_PHYCR_MIIRD
;
1104 iowrite32(phycr
, priv
->base
+ FTGMAC100_OFFSET_PHYCR
);
1106 for (i
= 0; i
< 10; i
++) {
1107 phycr
= ioread32(priv
->base
+ FTGMAC100_OFFSET_PHYCR
);
1109 if ((phycr
& FTGMAC100_PHYCR_MIIRD
) == 0) {
1112 data
= ioread32(priv
->base
+ FTGMAC100_OFFSET_PHYDATA
);
1113 return FTGMAC100_PHYDATA_MIIRDATA(data
);
1119 netdev_err(netdev
, "mdio read timed out\n");
1123 static int ftgmac100_mdiobus_write(struct mii_bus
*bus
, int phy_addr
,
1124 int regnum
, u16 value
)
1126 struct net_device
*netdev
= bus
->priv
;
1127 struct ftgmac100
*priv
= netdev_priv(netdev
);
1132 phycr
= ioread32(priv
->base
+ FTGMAC100_OFFSET_PHYCR
);
1134 /* preserve MDC cycle threshold */
1135 phycr
&= FTGMAC100_PHYCR_MDC_CYCTHR_MASK
;
1137 phycr
|= FTGMAC100_PHYCR_PHYAD(phy_addr
) |
1138 FTGMAC100_PHYCR_REGAD(regnum
) |
1139 FTGMAC100_PHYCR_MIIWR
;
1141 data
= FTGMAC100_PHYDATA_MIIWDATA(value
);
1143 iowrite32(data
, priv
->base
+ FTGMAC100_OFFSET_PHYDATA
);
1144 iowrite32(phycr
, priv
->base
+ FTGMAC100_OFFSET_PHYCR
);
1146 for (i
= 0; i
< 10; i
++) {
1147 phycr
= ioread32(priv
->base
+ FTGMAC100_OFFSET_PHYCR
);
1149 if ((phycr
& FTGMAC100_PHYCR_MIIWR
) == 0)
1155 netdev_err(netdev
, "mdio write timed out\n");
1159 static void ftgmac100_get_drvinfo(struct net_device
*netdev
,
1160 struct ethtool_drvinfo
*info
)
1162 strlcpy(info
->driver
, DRV_NAME
, sizeof(info
->driver
));
1163 strlcpy(info
->version
, DRV_VERSION
, sizeof(info
->version
));
1164 strlcpy(info
->bus_info
, dev_name(&netdev
->dev
), sizeof(info
->bus_info
));
1167 static void ftgmac100_get_ringparam(struct net_device
*netdev
,
1168 struct ethtool_ringparam
*ering
)
1170 struct ftgmac100
*priv
= netdev_priv(netdev
);
1172 memset(ering
, 0, sizeof(*ering
));
1173 ering
->rx_max_pending
= MAX_RX_QUEUE_ENTRIES
;
1174 ering
->tx_max_pending
= MAX_TX_QUEUE_ENTRIES
;
1175 ering
->rx_pending
= priv
->rx_q_entries
;
1176 ering
->tx_pending
= priv
->tx_q_entries
;
1179 static int ftgmac100_set_ringparam(struct net_device
*netdev
,
1180 struct ethtool_ringparam
*ering
)
1182 struct ftgmac100
*priv
= netdev_priv(netdev
);
1184 if (ering
->rx_pending
> MAX_RX_QUEUE_ENTRIES
||
1185 ering
->tx_pending
> MAX_TX_QUEUE_ENTRIES
||
1186 ering
->rx_pending
< MIN_RX_QUEUE_ENTRIES
||
1187 ering
->tx_pending
< MIN_TX_QUEUE_ENTRIES
||
1188 !is_power_of_2(ering
->rx_pending
) ||
1189 !is_power_of_2(ering
->tx_pending
))
1192 priv
->new_rx_q_entries
= ering
->rx_pending
;
1193 priv
->new_tx_q_entries
= ering
->tx_pending
;
1194 if (netif_running(netdev
))
1195 schedule_work(&priv
->reset_task
);
1200 static void ftgmac100_get_pauseparam(struct net_device
*netdev
,
1201 struct ethtool_pauseparam
*pause
)
1203 struct ftgmac100
*priv
= netdev_priv(netdev
);
1205 pause
->autoneg
= priv
->aneg_pause
;
1206 pause
->tx_pause
= priv
->tx_pause
;
1207 pause
->rx_pause
= priv
->rx_pause
;
1210 static int ftgmac100_set_pauseparam(struct net_device
*netdev
,
1211 struct ethtool_pauseparam
*pause
)
1213 struct ftgmac100
*priv
= netdev_priv(netdev
);
1214 struct phy_device
*phydev
= netdev
->phydev
;
1216 priv
->aneg_pause
= pause
->autoneg
;
1217 priv
->tx_pause
= pause
->tx_pause
;
1218 priv
->rx_pause
= pause
->rx_pause
;
1221 phy_set_asym_pause(phydev
, pause
->rx_pause
, pause
->tx_pause
);
1223 if (netif_running(netdev
)) {
1224 if (!(phydev
&& priv
->aneg_pause
))
1225 ftgmac100_config_pause(priv
);
1231 static const struct ethtool_ops ftgmac100_ethtool_ops
= {
1232 .get_drvinfo
= ftgmac100_get_drvinfo
,
1233 .get_link
= ethtool_op_get_link
,
1234 .get_link_ksettings
= phy_ethtool_get_link_ksettings
,
1235 .set_link_ksettings
= phy_ethtool_set_link_ksettings
,
1236 .nway_reset
= phy_ethtool_nway_reset
,
1237 .get_ringparam
= ftgmac100_get_ringparam
,
1238 .set_ringparam
= ftgmac100_set_ringparam
,
1239 .get_pauseparam
= ftgmac100_get_pauseparam
,
1240 .set_pauseparam
= ftgmac100_set_pauseparam
,
1243 static irqreturn_t
ftgmac100_interrupt(int irq
, void *dev_id
)
1245 struct net_device
*netdev
= dev_id
;
1246 struct ftgmac100
*priv
= netdev_priv(netdev
);
1247 unsigned int status
, new_mask
= FTGMAC100_INT_BAD
;
1249 /* Fetch and clear interrupt bits, process abnormal ones */
1250 status
= ioread32(priv
->base
+ FTGMAC100_OFFSET_ISR
);
1251 iowrite32(status
, priv
->base
+ FTGMAC100_OFFSET_ISR
);
1252 if (unlikely(status
& FTGMAC100_INT_BAD
)) {
1254 /* RX buffer unavailable */
1255 if (status
& FTGMAC100_INT_NO_RXBUF
)
1256 netdev
->stats
.rx_over_errors
++;
1258 /* received packet lost due to RX FIFO full */
1259 if (status
& FTGMAC100_INT_RPKT_LOST
)
1260 netdev
->stats
.rx_fifo_errors
++;
1262 /* sent packet lost due to excessive TX collision */
1263 if (status
& FTGMAC100_INT_XPKT_LOST
)
1264 netdev
->stats
.tx_fifo_errors
++;
1266 /* AHB error -> Reset the chip */
1267 if (status
& FTGMAC100_INT_AHB_ERR
) {
1268 if (net_ratelimit())
1270 "AHB bus error ! Resetting chip.\n");
1271 iowrite32(0, priv
->base
+ FTGMAC100_OFFSET_IER
);
1272 schedule_work(&priv
->reset_task
);
1276 /* We may need to restart the MAC after such errors, delay
1277 * this until after we have freed some Rx buffers though
1279 priv
->need_mac_restart
= true;
1281 /* Disable those errors until we restart */
1282 new_mask
&= ~status
;
1285 /* Only enable "bad" interrupts while NAPI is on */
1286 iowrite32(new_mask
, priv
->base
+ FTGMAC100_OFFSET_IER
);
1288 /* Schedule NAPI bh */
1289 napi_schedule_irqoff(&priv
->napi
);
1294 static bool ftgmac100_check_rx(struct ftgmac100
*priv
)
1296 struct ftgmac100_rxdes
*rxdes
= &priv
->rxdes
[priv
->rx_pointer
];
1298 /* Do we have a packet ? */
1299 return !!(rxdes
->rxdes0
& cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY
));
1302 static int ftgmac100_poll(struct napi_struct
*napi
, int budget
)
1304 struct ftgmac100
*priv
= container_of(napi
, struct ftgmac100
, napi
);
1308 /* Handle TX completions */
1309 if (ftgmac100_tx_buf_cleanable(priv
))
1310 ftgmac100_tx_complete(priv
);
1312 /* Handle RX packets */
1314 more
= ftgmac100_rx_packet(priv
, &work_done
);
1315 } while (more
&& work_done
< budget
);
1318 /* The interrupt is telling us to kick the MAC back to life
1319 * after an RX overflow
1321 if (unlikely(priv
->need_mac_restart
)) {
1322 ftgmac100_start_hw(priv
);
1324 /* Re-enable "bad" interrupts */
1325 iowrite32(FTGMAC100_INT_BAD
,
1326 priv
->base
+ FTGMAC100_OFFSET_IER
);
1329 /* As long as we are waiting for transmit packets to be
1330 * completed we keep NAPI going
1332 if (ftgmac100_tx_buf_cleanable(priv
))
1335 if (work_done
< budget
) {
1336 /* We are about to re-enable all interrupts. However
1337 * the HW has been latching RX/TX packet interrupts while
1338 * they were masked. So we clear them first, then we need
1339 * to re-check if there's something to process
1341 iowrite32(FTGMAC100_INT_RXTX
,
1342 priv
->base
+ FTGMAC100_OFFSET_ISR
);
1344 /* Push the above (and provides a barrier vs. subsequent
1345 * reads of the descriptor).
1347 ioread32(priv
->base
+ FTGMAC100_OFFSET_ISR
);
1349 /* Check RX and TX descriptors for more work to do */
1350 if (ftgmac100_check_rx(priv
) ||
1351 ftgmac100_tx_buf_cleanable(priv
))
1354 /* deschedule NAPI */
1355 napi_complete(napi
);
1357 /* enable all interrupts */
1358 iowrite32(FTGMAC100_INT_ALL
,
1359 priv
->base
+ FTGMAC100_OFFSET_IER
);
1365 static int ftgmac100_init_all(struct ftgmac100
*priv
, bool ignore_alloc_err
)
1369 /* Re-init descriptors (adjust queue sizes) */
1370 ftgmac100_init_rings(priv
);
1372 /* Realloc rx descriptors */
1373 err
= ftgmac100_alloc_rx_buffers(priv
);
1374 if (err
&& !ignore_alloc_err
)
1377 /* Reinit and restart HW */
1378 ftgmac100_init_hw(priv
);
1379 ftgmac100_config_pause(priv
);
1380 ftgmac100_start_hw(priv
);
1382 /* Re-enable the device */
1383 napi_enable(&priv
->napi
);
1384 netif_start_queue(priv
->netdev
);
1386 /* Enable all interrupts */
1387 iowrite32(FTGMAC100_INT_ALL
, priv
->base
+ FTGMAC100_OFFSET_IER
);
1392 static void ftgmac100_reset_task(struct work_struct
*work
)
1394 struct ftgmac100
*priv
= container_of(work
, struct ftgmac100
,
1396 struct net_device
*netdev
= priv
->netdev
;
1399 netdev_dbg(netdev
, "Resetting NIC...\n");
1401 /* Lock the world */
1404 mutex_lock(&netdev
->phydev
->lock
);
1406 mutex_lock(&priv
->mii_bus
->mdio_lock
);
1409 /* Check if the interface is still up */
1410 if (!netif_running(netdev
))
1413 /* Stop the network stack */
1414 netif_trans_update(netdev
);
1415 napi_disable(&priv
->napi
);
1416 netif_tx_disable(netdev
);
1418 /* Stop and reset the MAC */
1419 ftgmac100_stop_hw(priv
);
1420 err
= ftgmac100_reset_and_config_mac(priv
);
1422 /* Not much we can do ... it might come back... */
1423 netdev_err(netdev
, "attempting to continue...\n");
1426 /* Free all rx and tx buffers */
1427 ftgmac100_free_buffers(priv
);
1429 /* Setup everything again and restart chip */
1430 ftgmac100_init_all(priv
, true);
1432 netdev_dbg(netdev
, "Reset done !\n");
1435 mutex_unlock(&priv
->mii_bus
->mdio_lock
);
1437 mutex_unlock(&netdev
->phydev
->lock
);
1441 static int ftgmac100_open(struct net_device
*netdev
)
1443 struct ftgmac100
*priv
= netdev_priv(netdev
);
1446 /* Allocate ring buffers */
1447 err
= ftgmac100_alloc_rings(priv
);
1449 netdev_err(netdev
, "Failed to allocate descriptors\n");
1453 /* When using NC-SI we force the speed to 100Mbit/s full duplex,
1455 * Otherwise we leave it set to 0 (no link), the link
1456 * message from the PHY layer will handle setting it up to
1457 * something else if needed.
1459 if (priv
->use_ncsi
) {
1460 priv
->cur_duplex
= DUPLEX_FULL
;
1461 priv
->cur_speed
= SPEED_100
;
1463 priv
->cur_duplex
= 0;
1464 priv
->cur_speed
= 0;
1467 /* Reset the hardware */
1468 err
= ftgmac100_reset_and_config_mac(priv
);
1472 /* Initialize NAPI */
1473 netif_napi_add(netdev
, &priv
->napi
, ftgmac100_poll
, 64);
1475 /* Grab our interrupt */
1476 err
= request_irq(netdev
->irq
, ftgmac100_interrupt
, 0, netdev
->name
, netdev
);
1478 netdev_err(netdev
, "failed to request irq %d\n", netdev
->irq
);
1482 /* Start things up */
1483 err
= ftgmac100_init_all(priv
, false);
1485 netdev_err(netdev
, "Failed to allocate packet buffers\n");
1489 if (netdev
->phydev
) {
1490 /* If we have a PHY, start polling */
1491 phy_start(netdev
->phydev
);
1492 } else if (priv
->use_ncsi
) {
1493 /* If using NC-SI, set our carrier on and start the stack */
1494 netif_carrier_on(netdev
);
1496 /* Start the NCSI device */
1497 err
= ncsi_start_dev(priv
->ndev
);
1505 napi_disable(&priv
->napi
);
1506 netif_stop_queue(netdev
);
1508 ftgmac100_free_buffers(priv
);
1509 free_irq(netdev
->irq
, netdev
);
1511 netif_napi_del(&priv
->napi
);
1513 iowrite32(0, priv
->base
+ FTGMAC100_OFFSET_IER
);
1514 ftgmac100_free_rings(priv
);
1518 static int ftgmac100_stop(struct net_device
*netdev
)
1520 struct ftgmac100
*priv
= netdev_priv(netdev
);
1522 /* Note about the reset task: We are called with the rtnl lock
1523 * held, so we are synchronized against the core of the reset
1524 * task. We must not try to synchronously cancel it otherwise
1525 * we can deadlock. But since it will test for netif_running()
1526 * which has already been cleared by the net core, we don't
1527 * anything special to do.
1530 /* disable all interrupts */
1531 iowrite32(0, priv
->base
+ FTGMAC100_OFFSET_IER
);
1533 netif_stop_queue(netdev
);
1534 napi_disable(&priv
->napi
);
1535 netif_napi_del(&priv
->napi
);
1537 phy_stop(netdev
->phydev
);
1538 else if (priv
->use_ncsi
)
1539 ncsi_stop_dev(priv
->ndev
);
1541 ftgmac100_stop_hw(priv
);
1542 free_irq(netdev
->irq
, netdev
);
1543 ftgmac100_free_buffers(priv
);
1544 ftgmac100_free_rings(priv
);
1550 static int ftgmac100_do_ioctl(struct net_device
*netdev
, struct ifreq
*ifr
, int cmd
)
1552 if (!netdev
->phydev
)
1555 return phy_mii_ioctl(netdev
->phydev
, ifr
, cmd
);
1558 static void ftgmac100_tx_timeout(struct net_device
*netdev
)
1560 struct ftgmac100
*priv
= netdev_priv(netdev
);
1562 /* Disable all interrupts */
1563 iowrite32(0, priv
->base
+ FTGMAC100_OFFSET_IER
);
1565 /* Do the reset outside of interrupt context */
1566 schedule_work(&priv
->reset_task
);
1569 static int ftgmac100_set_features(struct net_device
*netdev
,
1570 netdev_features_t features
)
1572 struct ftgmac100
*priv
= netdev_priv(netdev
);
1573 netdev_features_t changed
= netdev
->features
^ features
;
1575 if (!netif_running(netdev
))
1578 /* Update the vlan filtering bit */
1579 if (changed
& NETIF_F_HW_VLAN_CTAG_RX
) {
1582 maccr
= ioread32(priv
->base
+ FTGMAC100_OFFSET_MACCR
);
1583 if (priv
->netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)
1584 maccr
|= FTGMAC100_MACCR_RM_VLAN
;
1586 maccr
&= ~FTGMAC100_MACCR_RM_VLAN
;
1587 iowrite32(maccr
, priv
->base
+ FTGMAC100_OFFSET_MACCR
);
1593 #ifdef CONFIG_NET_POLL_CONTROLLER
1594 static void ftgmac100_poll_controller(struct net_device
*netdev
)
1596 unsigned long flags
;
1598 local_irq_save(flags
);
1599 ftgmac100_interrupt(netdev
->irq
, netdev
);
1600 local_irq_restore(flags
);
1604 static const struct net_device_ops ftgmac100_netdev_ops
= {
1605 .ndo_open
= ftgmac100_open
,
1606 .ndo_stop
= ftgmac100_stop
,
1607 .ndo_start_xmit
= ftgmac100_hard_start_xmit
,
1608 .ndo_set_mac_address
= ftgmac100_set_mac_addr
,
1609 .ndo_validate_addr
= eth_validate_addr
,
1610 .ndo_do_ioctl
= ftgmac100_do_ioctl
,
1611 .ndo_tx_timeout
= ftgmac100_tx_timeout
,
1612 .ndo_set_rx_mode
= ftgmac100_set_rx_mode
,
1613 .ndo_set_features
= ftgmac100_set_features
,
1614 #ifdef CONFIG_NET_POLL_CONTROLLER
1615 .ndo_poll_controller
= ftgmac100_poll_controller
,
1617 .ndo_vlan_rx_add_vid
= ncsi_vlan_rx_add_vid
,
1618 .ndo_vlan_rx_kill_vid
= ncsi_vlan_rx_kill_vid
,
1621 static int ftgmac100_setup_mdio(struct net_device
*netdev
)
1623 struct ftgmac100
*priv
= netdev_priv(netdev
);
1624 struct platform_device
*pdev
= to_platform_device(priv
->dev
);
1625 int phy_intf
= PHY_INTERFACE_MODE_RGMII
;
1626 struct device_node
*np
= pdev
->dev
.of_node
;
1630 /* initialize mdio bus */
1631 priv
->mii_bus
= mdiobus_alloc();
1635 if (priv
->is_aspeed
) {
1636 /* This driver supports the old MDIO interface */
1637 reg
= ioread32(priv
->base
+ FTGMAC100_OFFSET_REVR
);
1638 reg
&= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE
;
1639 iowrite32(reg
, priv
->base
+ FTGMAC100_OFFSET_REVR
);
1642 /* Get PHY mode from device-tree */
1644 /* Default to RGMII. It's a gigabit part after all */
1645 phy_intf
= of_get_phy_mode(np
);
1647 phy_intf
= PHY_INTERFACE_MODE_RGMII
;
1649 /* Aspeed only supports these. I don't know about other IP
1650 * block vendors so I'm going to just let them through for
1651 * now. Note that this is only a warning if for some obscure
1652 * reason the DT really means to lie about it or it's a newer
1653 * part we don't know about.
1655 * On the Aspeed SoC there are additionally straps and SCU
1656 * control bits that could tell us what the interface is
1657 * (or allow us to configure it while the IP block is held
1658 * in reset). For now I chose to keep this driver away from
1659 * those SoC specific bits and assume the device-tree is
1660 * right and the SCU has been configured properly by pinmux
1663 if (priv
->is_aspeed
&&
1664 phy_intf
!= PHY_INTERFACE_MODE_RMII
&&
1665 phy_intf
!= PHY_INTERFACE_MODE_RGMII
&&
1666 phy_intf
!= PHY_INTERFACE_MODE_RGMII_ID
&&
1667 phy_intf
!= PHY_INTERFACE_MODE_RGMII_RXID
&&
1668 phy_intf
!= PHY_INTERFACE_MODE_RGMII_TXID
) {
1670 "Unsupported PHY mode %s !\n",
1671 phy_modes(phy_intf
));
1675 priv
->mii_bus
->name
= "ftgmac100_mdio";
1676 snprintf(priv
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%s-%d",
1677 pdev
->name
, pdev
->id
);
1678 priv
->mii_bus
->parent
= priv
->dev
;
1679 priv
->mii_bus
->priv
= priv
->netdev
;
1680 priv
->mii_bus
->read
= ftgmac100_mdiobus_read
;
1681 priv
->mii_bus
->write
= ftgmac100_mdiobus_write
;
1683 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1684 priv
->mii_bus
->irq
[i
] = PHY_POLL
;
1686 err
= mdiobus_register(priv
->mii_bus
);
1688 dev_err(priv
->dev
, "Cannot register MDIO bus!\n");
1689 goto err_register_mdiobus
;
1692 err
= ftgmac100_mii_probe(priv
, phy_intf
);
1694 dev_err(priv
->dev
, "MII Probe failed!\n");
1701 mdiobus_unregister(priv
->mii_bus
);
1702 err_register_mdiobus
:
1703 mdiobus_free(priv
->mii_bus
);
1707 static void ftgmac100_destroy_mdio(struct net_device
*netdev
)
1709 struct ftgmac100
*priv
= netdev_priv(netdev
);
1711 if (!netdev
->phydev
)
1714 phy_disconnect(netdev
->phydev
);
1715 mdiobus_unregister(priv
->mii_bus
);
1716 mdiobus_free(priv
->mii_bus
);
1719 static void ftgmac100_ncsi_handler(struct ncsi_dev
*nd
)
1721 if (unlikely(nd
->state
!= ncsi_dev_state_functional
))
1724 netdev_dbg(nd
->dev
, "NCSI interface %s\n",
1725 nd
->link_up
? "up" : "down");
1728 static void ftgmac100_setup_clk(struct ftgmac100
*priv
)
1730 priv
->clk
= devm_clk_get(priv
->dev
, NULL
);
1731 if (IS_ERR(priv
->clk
))
1734 clk_prepare_enable(priv
->clk
);
1736 /* Aspeed specifies a 100MHz clock is required for up to
1737 * 1000Mbit link speeds. As NCSI is limited to 100Mbit, 25MHz
1740 clk_set_rate(priv
->clk
, priv
->use_ncsi
? FTGMAC_25MHZ
:
1744 static int ftgmac100_probe(struct platform_device
*pdev
)
1746 struct resource
*res
;
1748 struct net_device
*netdev
;
1749 struct ftgmac100
*priv
;
1750 struct device_node
*np
;
1756 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1760 irq
= platform_get_irq(pdev
, 0);
1764 /* setup net_device */
1765 netdev
= alloc_etherdev(sizeof(*priv
));
1768 goto err_alloc_etherdev
;
1771 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
1773 netdev
->ethtool_ops
= &ftgmac100_ethtool_ops
;
1774 netdev
->netdev_ops
= &ftgmac100_netdev_ops
;
1775 netdev
->watchdog_timeo
= 5 * HZ
;
1777 platform_set_drvdata(pdev
, netdev
);
1779 /* setup private data */
1780 priv
= netdev_priv(netdev
);
1781 priv
->netdev
= netdev
;
1782 priv
->dev
= &pdev
->dev
;
1783 INIT_WORK(&priv
->reset_task
, ftgmac100_reset_task
);
1786 priv
->res
= request_mem_region(res
->start
, resource_size(res
),
1787 dev_name(&pdev
->dev
));
1789 dev_err(&pdev
->dev
, "Could not reserve memory region\n");
1794 priv
->base
= ioremap(res
->start
, resource_size(res
));
1796 dev_err(&pdev
->dev
, "Failed to ioremap ethernet registers\n");
1804 priv
->tx_pause
= true;
1805 priv
->rx_pause
= true;
1806 priv
->aneg_pause
= true;
1808 /* MAC address from chip or random one */
1809 ftgmac100_initial_mac(priv
);
1811 np
= pdev
->dev
.of_node
;
1812 if (np
&& (of_device_is_compatible(np
, "aspeed,ast2400-mac") ||
1813 of_device_is_compatible(np
, "aspeed,ast2500-mac"))) {
1814 priv
->rxdes0_edorr_mask
= BIT(30);
1815 priv
->txdes0_edotr_mask
= BIT(30);
1816 priv
->is_aspeed
= true;
1818 priv
->rxdes0_edorr_mask
= BIT(15);
1819 priv
->txdes0_edotr_mask
= BIT(15);
1822 if (np
&& of_get_property(np
, "use-ncsi", NULL
)) {
1823 if (!IS_ENABLED(CONFIG_NET_NCSI
)) {
1824 dev_err(&pdev
->dev
, "NCSI stack not enabled\n");
1828 dev_info(&pdev
->dev
, "Using NCSI interface\n");
1829 priv
->use_ncsi
= true;
1830 priv
->ndev
= ncsi_register_dev(netdev
, ftgmac100_ncsi_handler
);
1834 priv
->use_ncsi
= false;
1835 err
= ftgmac100_setup_mdio(netdev
);
1837 goto err_setup_mdio
;
1840 if (priv
->is_aspeed
)
1841 ftgmac100_setup_clk(priv
);
1843 /* Default ring sizes */
1844 priv
->rx_q_entries
= priv
->new_rx_q_entries
= DEF_RX_QUEUE_ENTRIES
;
1845 priv
->tx_q_entries
= priv
->new_tx_q_entries
= DEF_TX_QUEUE_ENTRIES
;
1847 /* Base feature set */
1848 netdev
->hw_features
= NETIF_F_RXCSUM
| NETIF_F_HW_CSUM
|
1849 NETIF_F_GRO
| NETIF_F_SG
| NETIF_F_HW_VLAN_CTAG_RX
|
1850 NETIF_F_HW_VLAN_CTAG_TX
;
1853 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
1855 /* AST2400 doesn't have working HW checksum generation */
1856 if (np
&& (of_device_is_compatible(np
, "aspeed,ast2400-mac")))
1857 netdev
->hw_features
&= ~NETIF_F_HW_CSUM
;
1858 if (np
&& of_get_property(np
, "no-hw-checksum", NULL
))
1859 netdev
->hw_features
&= ~(NETIF_F_HW_CSUM
| NETIF_F_RXCSUM
);
1860 netdev
->features
|= netdev
->hw_features
;
1862 /* register network device */
1863 err
= register_netdev(netdev
);
1865 dev_err(&pdev
->dev
, "Failed to register netdev\n");
1866 goto err_register_netdev
;
1869 netdev_info(netdev
, "irq %d, mapped at %p\n", netdev
->irq
, priv
->base
);
1874 err_register_netdev
:
1875 ftgmac100_destroy_mdio(netdev
);
1877 iounmap(priv
->base
);
1879 release_resource(priv
->res
);
1881 free_netdev(netdev
);
1886 static int ftgmac100_remove(struct platform_device
*pdev
)
1888 struct net_device
*netdev
;
1889 struct ftgmac100
*priv
;
1891 netdev
= platform_get_drvdata(pdev
);
1892 priv
= netdev_priv(netdev
);
1894 unregister_netdev(netdev
);
1896 clk_disable_unprepare(priv
->clk
);
1898 /* There's a small chance the reset task will have been re-queued,
1899 * during stop, make sure it's gone before we free the structure.
1901 cancel_work_sync(&priv
->reset_task
);
1903 ftgmac100_destroy_mdio(netdev
);
1905 iounmap(priv
->base
);
1906 release_resource(priv
->res
);
1908 netif_napi_del(&priv
->napi
);
1909 free_netdev(netdev
);
1913 static const struct of_device_id ftgmac100_of_match
[] = {
1914 { .compatible
= "faraday,ftgmac100" },
1917 MODULE_DEVICE_TABLE(of
, ftgmac100_of_match
);
1919 static struct platform_driver ftgmac100_driver
= {
1920 .probe
= ftgmac100_probe
,
1921 .remove
= ftgmac100_remove
,
1924 .of_match_table
= ftgmac100_of_match
,
1927 module_platform_driver(ftgmac100_driver
);
1929 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
1930 MODULE_DESCRIPTION("FTGMAC100 driver");
1931 MODULE_LICENSE("GPL");