]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blob - drivers/net/ethernet/freescale/fec.c
projects / mirror_ubuntu-hirsute-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge remote-tracking branch 'regulator/topic/palmas' into v3.9-rc8
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / freescale / fec.c
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 *
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/spinlock.h>
39 #include <linux/workqueue.h>
40 #include <linux/bitops.h>
41 #include <linux/io.h>
42 #include <linux/irq.h>
43 #include <linux/clk.h>
44 #include <linux/platform_device.h>
45 #include <linux/phy.h>
46 #include <linux/fec.h>
47 #include <linux/of.h>
48 #include <linux/of_device.h>
49 #include <linux/of_gpio.h>
50 #include <linux/of_net.h>
51 #include <linux/pinctrl/consumer.h>
52 #include <linux/regulator/consumer.h>
53
54 #include <asm/cacheflush.h>
55
56 #ifndef CONFIG_ARM
57 #include <asm/coldfire.h>
58 #include <asm/mcfsim.h>
59 #endif
60
61 #include "fec.h"
62
63 #if defined(CONFIG_ARM)
64 #define FEC_ALIGNMENT 0xf
65 #else
66 #define FEC_ALIGNMENT 0x3
67 #endif
68
69 #define DRIVER_NAME "fec"
70 #define FEC_NAPI_WEIGHT 64
71
72 /* Pause frame feild and FIFO threshold */
73 #define FEC_ENET_FCE (1 << 5)
74 #define FEC_ENET_RSEM_V 0x84
75 #define FEC_ENET_RSFL_V 16
76 #define FEC_ENET_RAEM_V 0x8
77 #define FEC_ENET_RAFL_V 0x8
78 #define FEC_ENET_OPD_V 0xFFF0
79
80 /* Controller is ENET-MAC */
81 #define FEC_QUIRK_ENET_MAC (1 << 0)
82 /* Controller needs driver to swap frame */
83 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
84 /* Controller uses gasket */
85 #define FEC_QUIRK_USE_GASKET (1 << 2)
86 /* Controller has GBIT support */
87 #define FEC_QUIRK_HAS_GBIT (1 << 3)
88 /* Controller has extend desc buffer */
89 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
90
91 static struct platform_device_id fec_devtype[] = {
92 {
93 /* keep it for coldfire */
94 .name = DRIVER_NAME,
95 .driver_data = 0,
96 }, {
97 .name = "imx25-fec",
98 .driver_data = FEC_QUIRK_USE_GASKET,
99 }, {
100 .name = "imx27-fec",
101 .driver_data = 0,
102 }, {
103 .name = "imx28-fec",
104 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
105 }, {
106 .name = "imx6q-fec",
107 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
108 FEC_QUIRK_HAS_BUFDESC_EX,
109 }, {
110 /* sentinel */
111 }
112 };
113 MODULE_DEVICE_TABLE(platform, fec_devtype);
114
115 enum imx_fec_type {
116 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
117 IMX27_FEC, /* runs on i.mx27/35/51 */
118 IMX28_FEC,
119 IMX6Q_FEC,
120 };
121
122 static const struct of_device_id fec_dt_ids[] = {
123 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
124 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
125 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
126 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
127 { /* sentinel */ }
128 };
129 MODULE_DEVICE_TABLE(of, fec_dt_ids);
130
131 static unsigned char macaddr[ETH_ALEN];
132 module_param_array(macaddr, byte, NULL, 0);
133 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
134
135 #if defined(CONFIG_M5272)
136 /*
137 * Some hardware gets it MAC address out of local flash memory.
138 * if this is non-zero then assume it is the address to get MAC from.
139 */
140 #if defined(CONFIG_NETtel)
141 #define FEC_FLASHMAC 0xf0006006
142 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
143 #define FEC_FLASHMAC 0xf0006000
144 #elif defined(CONFIG_CANCam)
145 #define FEC_FLASHMAC 0xf0020000
146 #elif defined (CONFIG_M5272C3)
147 #define FEC_FLASHMAC (0xffe04000 + 4)
148 #elif defined(CONFIG_MOD5272)
149 #define FEC_FLASHMAC 0xffc0406b
150 #else
151 #define FEC_FLASHMAC 0
152 #endif
153 #endif /* CONFIG_M5272 */
154
155 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
156 #error "FEC: descriptor ring size constants too large"
157 #endif
158
159 /* Interrupt events/masks. */
160 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
161 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
162 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
163 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
164 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
165 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
166 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
167 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
168 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
169 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
170
171 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
172 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
173
174 /* The FEC stores dest/src/type, data, and checksum for receive packets.
175 */
176 #define PKT_MAXBUF_SIZE 1518
177 #define PKT_MINBUF_SIZE 64
178 #define PKT_MAXBLR_SIZE 1520
179
180 /*
181 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
182 * size bits. Other FEC hardware does not, so we need to take that into
183 * account when setting it.
184 */
185 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
186 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
187 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
188 #else
189 #define OPT_FRAME_SIZE 0
190 #endif
191
192 /* FEC MII MMFR bits definition */
193 #define FEC_MMFR_ST (1 << 30)
194 #define FEC_MMFR_OP_READ (2 << 28)
195 #define FEC_MMFR_OP_WRITE (1 << 28)
196 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
197 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
198 #define FEC_MMFR_TA (2 << 16)
199 #define FEC_MMFR_DATA(v) (v & 0xffff)
200
201 #define FEC_MII_TIMEOUT 30000 /* us */
202
203 /* Transmitter timeout */
204 #define TX_TIMEOUT (2 * HZ)
205
206 #define FEC_PAUSE_FLAG_AUTONEG 0x1
207 #define FEC_PAUSE_FLAG_ENABLE 0x2
208
209 static int mii_cnt;
210
211 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex)
212 {
213 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
214 if (is_ex)
215 return (struct bufdesc *)(ex + 1);
216 else
217 return bdp + 1;
218 }
219
220 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex)
221 {
222 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
223 if (is_ex)
224 return (struct bufdesc *)(ex - 1);
225 else
226 return bdp - 1;
227 }
228
229 static void *swap_buffer(void *bufaddr, int len)
230 {
231 int i;
232 unsigned int *buf = bufaddr;
233
234 for (i = 0; i < (len + 3) / 4; i++, buf++)
235 *buf = cpu_to_be32(*buf);
236
237 return bufaddr;
238 }
239
240 static netdev_tx_t
241 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
242 {
243 struct fec_enet_private *fep = netdev_priv(ndev);
244 const struct platform_device_id *id_entry =
245 platform_get_device_id(fep->pdev);
246 struct bufdesc *bdp;
247 void *bufaddr;
248 unsigned short status;
249 unsigned int index;
250
251 if (!fep->link) {
252 /* Link is down or autonegotiation is in progress. */
253 return NETDEV_TX_BUSY;
254 }
255
256 /* Fill in a Tx ring entry */
257 bdp = fep->cur_tx;
258
259 status = bdp->cbd_sc;
260
261 if (status & BD_ENET_TX_READY) {
262 /* Ooops. All transmit buffers are full. Bail out.
263 * This should not happen, since ndev->tbusy should be set.
264 */
265 printk("%s: tx queue full!.\n", ndev->name);
266 return NETDEV_TX_BUSY;
267 }
268
269 /* Clear all of the status flags */
270 status &= ~BD_ENET_TX_STATS;
271
272 /* Set buffer length and buffer pointer */
273 bufaddr = skb->data;
274 bdp->cbd_datlen = skb->len;
275
276 /*
277 * On some FEC implementations data must be aligned on
278 * 4-byte boundaries. Use bounce buffers to copy data
279 * and get it aligned. Ugh.
280 */
281 if (fep->bufdesc_ex)
282 index = (struct bufdesc_ex *)bdp -
283 (struct bufdesc_ex *)fep->tx_bd_base;
284 else
285 index = bdp - fep->tx_bd_base;
286
287 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
288 memcpy(fep->tx_bounce[index], skb->data, skb->len);
289 bufaddr = fep->tx_bounce[index];
290 }
291
292 /*
293 * Some design made an incorrect assumption on endian mode of
294 * the system that it's running on. As the result, driver has to
295 * swap every frame going to and coming from the controller.
296 */
297 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
298 swap_buffer(bufaddr, skb->len);
299
300 /* Save skb pointer */
301 fep->tx_skbuff[index] = skb;
302
303 /* Push the data cache so the CPM does not get stale memory
304 * data.
305 */
306 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
307 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
308
309 /* Send it on its way. Tell FEC it's ready, interrupt when done,
310 * it's the last BD of the frame, and to put the CRC on the end.
311 */
312 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
313 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
314 bdp->cbd_sc = status;
315
316 if (fep->bufdesc_ex) {
317
318 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
319 ebdp->cbd_bdu = 0;
320 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
321 fep->hwts_tx_en)) {
322 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
323 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
324 } else {
325
326 ebdp->cbd_esc = BD_ENET_TX_INT;
327 }
328 }
329 /* If this was the last BD in the ring, start at the beginning again. */
330 if (status & BD_ENET_TX_WRAP)
331 bdp = fep->tx_bd_base;
332 else
333 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
334
335 fep->cur_tx = bdp;
336
337 if (fep->cur_tx == fep->dirty_tx)
338 netif_stop_queue(ndev);
339
340 /* Trigger transmission start */
341 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
342
343 skb_tx_timestamp(skb);
344
345 return NETDEV_TX_OK;
346 }
347
348 /* Init RX & TX buffer descriptors
349 */
350 static void fec_enet_bd_init(struct net_device *dev)
351 {
352 struct fec_enet_private *fep = netdev_priv(dev);
353 struct bufdesc *bdp;
354 unsigned int i;
355
356 /* Initialize the receive buffer descriptors. */
357 bdp = fep->rx_bd_base;
358 for (i = 0; i < RX_RING_SIZE; i++) {
359
360 /* Initialize the BD for every fragment in the page. */
361 if (bdp->cbd_bufaddr)
362 bdp->cbd_sc = BD_ENET_RX_EMPTY;
363 else
364 bdp->cbd_sc = 0;
365 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
366 }
367
368 /* Set the last buffer to wrap */
369 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
370 bdp->cbd_sc |= BD_SC_WRAP;
371
372 fep->cur_rx = fep->rx_bd_base;
373
374 /* ...and the same for transmit */
375 bdp = fep->tx_bd_base;
376 fep->cur_tx = bdp;
377 for (i = 0; i < TX_RING_SIZE; i++) {
378
379 /* Initialize the BD for every fragment in the page. */
380 bdp->cbd_sc = 0;
381 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
382 dev_kfree_skb_any(fep->tx_skbuff[i]);
383 fep->tx_skbuff[i] = NULL;
384 }
385 bdp->cbd_bufaddr = 0;
386 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
387 }
388
389 /* Set the last buffer to wrap */
390 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
391 bdp->cbd_sc |= BD_SC_WRAP;
392 fep->dirty_tx = bdp;
393 }
394
395 /* This function is called to start or restart the FEC during a link
396 * change. This only happens when switching between half and full
397 * duplex.
398 */
399 static void
400 fec_restart(struct net_device *ndev, int duplex)
401 {
402 struct fec_enet_private *fep = netdev_priv(ndev);
403 const struct platform_device_id *id_entry =
404 platform_get_device_id(fep->pdev);
405 int i;
406 u32 temp_mac[2];
407 u32 rcntl = OPT_FRAME_SIZE | 0x04;
408 u32 ecntl = 0x2; /* ETHEREN */
409
410 /* Whack a reset. We should wait for this. */
411 writel(1, fep->hwp + FEC_ECNTRL);
412 udelay(10);
413
414 /*
415 * enet-mac reset will reset mac address registers too,
416 * so need to reconfigure it.
417 */
418 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
419 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
420 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
421 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
422 }
423
424 /* Clear any outstanding interrupt. */
425 writel(0xffc00000, fep->hwp + FEC_IEVENT);
426
427 /* Reset all multicast. */
428 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
429 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
430 #ifndef CONFIG_M5272
431 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
432 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
433 #endif
434
435 /* Set maximum receive buffer size. */
436 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
437
438 fec_enet_bd_init(ndev);
439
440 /* Set receive and transmit descriptor base. */
441 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
442 if (fep->bufdesc_ex)
443 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
444 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
445 else
446 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
447 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
448
449
450 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
451 if (fep->tx_skbuff[i]) {
452 dev_kfree_skb_any(fep->tx_skbuff[i]);
453 fep->tx_skbuff[i] = NULL;
454 }
455 }
456
457 /* Enable MII mode */
458 if (duplex) {
459 /* FD enable */
460 writel(0x04, fep->hwp + FEC_X_CNTRL);
461 } else {
462 /* No Rcv on Xmit */
463 rcntl |= 0x02;
464 writel(0x0, fep->hwp + FEC_X_CNTRL);
465 }
466
467 fep->full_duplex = duplex;
468
469 /* Set MII speed */
470 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
471
472 /*
473 * The phy interface and speed need to get configured
474 * differently on enet-mac.
475 */
476 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
477 /* Enable flow control and length check */
478 rcntl |= 0x40000000 | 0x00000020;
479
480 /* RGMII, RMII or MII */
481 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
482 rcntl |= (1 << 6);
483 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
484 rcntl |= (1 << 8);
485 else
486 rcntl &= ~(1 << 8);
487
488 /* 1G, 100M or 10M */
489 if (fep->phy_dev) {
490 if (fep->phy_dev->speed == SPEED_1000)
491 ecntl |= (1 << 5);
492 else if (fep->phy_dev->speed == SPEED_100)
493 rcntl &= ~(1 << 9);
494 else
495 rcntl |= (1 << 9);
496 }
497 } else {
498 #ifdef FEC_MIIGSK_ENR
499 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
500 u32 cfgr;
501 /* disable the gasket and wait */
502 writel(0, fep->hwp + FEC_MIIGSK_ENR);
503 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
504 udelay(1);
505
506 /*
507 * configure the gasket:
508 * RMII, 50 MHz, no loopback, no echo
509 * MII, 25 MHz, no loopback, no echo
510 */
511 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
512 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
513 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
514 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
515 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
516
517 /* re-enable the gasket */
518 writel(2, fep->hwp + FEC_MIIGSK_ENR);
519 }
520 #endif
521 }
522
523 /* enable pause frame*/
524 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
525 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
526 fep->phy_dev && fep->phy_dev->pause)) {
527 rcntl |= FEC_ENET_FCE;
528
529 /* set FIFO thresh hold parameter to reduce overrun */
530 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
531 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
532 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
533 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
534
535 /* OPD */
536 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
537 } else {
538 rcntl &= ~FEC_ENET_FCE;
539 }
540
541 writel(rcntl, fep->hwp + FEC_R_CNTRL);
542
543 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
544 /* enable ENET endian swap */
545 ecntl |= (1 << 8);
546 /* enable ENET store and forward mode */
547 writel(1 << 8, fep->hwp + FEC_X_WMRK);
548 }
549
550 if (fep->bufdesc_ex)
551 ecntl |= (1 << 4);
552
553 /* And last, enable the transmit and receive processing */
554 writel(ecntl, fep->hwp + FEC_ECNTRL);
555 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
556
557 if (fep->bufdesc_ex)
558 fec_ptp_start_cyclecounter(ndev);
559
560 /* Enable interrupts we wish to service */
561 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
562 }
563
564 static void
565 fec_stop(struct net_device *ndev)
566 {
567 struct fec_enet_private *fep = netdev_priv(ndev);
568 const struct platform_device_id *id_entry =
569 platform_get_device_id(fep->pdev);
570 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
571
572 /* We cannot expect a graceful transmit stop without link !!! */
573 if (fep->link) {
574 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
575 udelay(10);
576 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
577 printk("fec_stop : Graceful transmit stop did not complete !\n");
578 }
579
580 /* Whack a reset. We should wait for this. */
581 writel(1, fep->hwp + FEC_ECNTRL);
582 udelay(10);
583 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
584 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
585
586 /* We have to keep ENET enabled to have MII interrupt stay working */
587 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
588 writel(2, fep->hwp + FEC_ECNTRL);
589 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
590 }
591 }
592
593
594 static void
595 fec_timeout(struct net_device *ndev)
596 {
597 struct fec_enet_private *fep = netdev_priv(ndev);
598
599 ndev->stats.tx_errors++;
600
601 fec_restart(ndev, fep->full_duplex);
602 netif_wake_queue(ndev);
603 }
604
605 static void
606 fec_enet_tx(struct net_device *ndev)
607 {
608 struct fec_enet_private *fep;
609 struct bufdesc *bdp;
610 unsigned short status;
611 struct sk_buff *skb;
612 int index = 0;
613
614 fep = netdev_priv(ndev);
615 bdp = fep->dirty_tx;
616
617 /* get next bdp of dirty_tx */
618 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
619 bdp = fep->tx_bd_base;
620 else
621 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
622
623 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
624
625 /* current queue is empty */
626 if (bdp == fep->cur_tx)
627 break;
628
629 if (fep->bufdesc_ex)
630 index = (struct bufdesc_ex *)bdp -
631 (struct bufdesc_ex *)fep->tx_bd_base;
632 else
633 index = bdp - fep->tx_bd_base;
634
635 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
636 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
637 bdp->cbd_bufaddr = 0;
638
639 skb = fep->tx_skbuff[index];
640
641 /* Check for errors. */
642 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
643 BD_ENET_TX_RL | BD_ENET_TX_UN |
644 BD_ENET_TX_CSL)) {
645 ndev->stats.tx_errors++;
646 if (status & BD_ENET_TX_HB) /* No heartbeat */
647 ndev->stats.tx_heartbeat_errors++;
648 if (status & BD_ENET_TX_LC) /* Late collision */
649 ndev->stats.tx_window_errors++;
650 if (status & BD_ENET_TX_RL) /* Retrans limit */
651 ndev->stats.tx_aborted_errors++;
652 if (status & BD_ENET_TX_UN) /* Underrun */
653 ndev->stats.tx_fifo_errors++;
654 if (status & BD_ENET_TX_CSL) /* Carrier lost */
655 ndev->stats.tx_carrier_errors++;
656 } else {
657 ndev->stats.tx_packets++;
658 }
659
660 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
661 fep->bufdesc_ex) {
662 struct skb_shared_hwtstamps shhwtstamps;
663 unsigned long flags;
664 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
665
666 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
667 spin_lock_irqsave(&fep->tmreg_lock, flags);
668 shhwtstamps.hwtstamp = ns_to_ktime(
669 timecounter_cyc2time(&fep->tc, ebdp->ts));
670 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
671 skb_tstamp_tx(skb, &shhwtstamps);
672 }
673
674 if (status & BD_ENET_TX_READY)
675 printk("HEY! Enet xmit interrupt and TX_READY.\n");
676
677 /* Deferred means some collisions occurred during transmit,
678 * but we eventually sent the packet OK.
679 */
680 if (status & BD_ENET_TX_DEF)
681 ndev->stats.collisions++;
682
683 /* Free the sk buffer associated with this last transmit */
684 dev_kfree_skb_any(skb);
685 fep->tx_skbuff[index] = NULL;
686
687 fep->dirty_tx = bdp;
688
689 /* Update pointer to next buffer descriptor to be transmitted */
690 if (status & BD_ENET_TX_WRAP)
691 bdp = fep->tx_bd_base;
692 else
693 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
694
695 /* Since we have freed up a buffer, the ring is no longer full
696 */
697 if (fep->dirty_tx != fep->cur_tx) {
698 if (netif_queue_stopped(ndev))
699 netif_wake_queue(ndev);
700 }
701 }
702 return;
703 }
704
705
706 /* During a receive, the cur_rx points to the current incoming buffer.
707 * When we update through the ring, if the next incoming buffer has
708 * not been given to the system, we just set the empty indicator,
709 * effectively tossing the packet.
710 */
711 static int
712 fec_enet_rx(struct net_device *ndev, int budget)
713 {
714 struct fec_enet_private *fep = netdev_priv(ndev);
715 const struct platform_device_id *id_entry =
716 platform_get_device_id(fep->pdev);
717 struct bufdesc *bdp;
718 unsigned short status;
719 struct sk_buff *skb;
720 ushort pkt_len;
721 __u8 *data;
722 int pkt_received = 0;
723
724 #ifdef CONFIG_M532x
725 flush_cache_all();
726 #endif
727
728 /* First, grab all of the stats for the incoming packet.
729 * These get messed up if we get called due to a busy condition.
730 */
731 bdp = fep->cur_rx;
732
733 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
734
735 if (pkt_received >= budget)
736 break;
737 pkt_received++;
738
739 /* Since we have allocated space to hold a complete frame,
740 * the last indicator should be set.
741 */
742 if ((status & BD_ENET_RX_LAST) == 0)
743 printk("FEC ENET: rcv is not +last\n");
744
745 if (!fep->opened)
746 goto rx_processing_done;
747
748 /* Check for errors. */
749 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
750 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
751 ndev->stats.rx_errors++;
752 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
753 /* Frame too long or too short. */
754 ndev->stats.rx_length_errors++;
755 }
756 if (status & BD_ENET_RX_NO) /* Frame alignment */
757 ndev->stats.rx_frame_errors++;
758 if (status & BD_ENET_RX_CR) /* CRC Error */
759 ndev->stats.rx_crc_errors++;
760 if (status & BD_ENET_RX_OV) /* FIFO overrun */
761 ndev->stats.rx_fifo_errors++;
762 }
763
764 /* Report late collisions as a frame error.
765 * On this error, the BD is closed, but we don't know what we
766 * have in the buffer. So, just drop this frame on the floor.
767 */
768 if (status & BD_ENET_RX_CL) {
769 ndev->stats.rx_errors++;
770 ndev->stats.rx_frame_errors++;
771 goto rx_processing_done;
772 }
773
774 /* Process the incoming frame. */
775 ndev->stats.rx_packets++;
776 pkt_len = bdp->cbd_datlen;
777 ndev->stats.rx_bytes += pkt_len;
778 data = (__u8*)__va(bdp->cbd_bufaddr);
779
780 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
781 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
782
783 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
784 swap_buffer(data, pkt_len);
785
786 /* This does 16 byte alignment, exactly what we need.
787 * The packet length includes FCS, but we don't want to
788 * include that when passing upstream as it messes up
789 * bridging applications.
790 */
791 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
792
793 if (unlikely(!skb)) {
794 printk("%s: Memory squeeze, dropping packet.\n",
795 ndev->name);
796 ndev->stats.rx_dropped++;
797 } else {
798 skb_reserve(skb, NET_IP_ALIGN);
799 skb_put(skb, pkt_len - 4); /* Make room */
800 skb_copy_to_linear_data(skb, data, pkt_len - 4);
801 skb->protocol = eth_type_trans(skb, ndev);
802
803 /* Get receive timestamp from the skb */
804 if (fep->hwts_rx_en && fep->bufdesc_ex) {
805 struct skb_shared_hwtstamps *shhwtstamps =
806 skb_hwtstamps(skb);
807 unsigned long flags;
808 struct bufdesc_ex *ebdp =
809 (struct bufdesc_ex *)bdp;
810
811 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
812
813 spin_lock_irqsave(&fep->tmreg_lock, flags);
814 shhwtstamps->hwtstamp = ns_to_ktime(
815 timecounter_cyc2time(&fep->tc, ebdp->ts));
816 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
817 }
818
819 if (!skb_defer_rx_timestamp(skb))
820 napi_gro_receive(&fep->napi, skb);
821 }
822
823 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
824 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
825 rx_processing_done:
826 /* Clear the status flags for this buffer */
827 status &= ~BD_ENET_RX_STATS;
828
829 /* Mark the buffer empty */
830 status |= BD_ENET_RX_EMPTY;
831 bdp->cbd_sc = status;
832
833 if (fep->bufdesc_ex) {
834 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
835
836 ebdp->cbd_esc = BD_ENET_RX_INT;
837 ebdp->cbd_prot = 0;
838 ebdp->cbd_bdu = 0;
839 }
840
841 /* Update BD pointer to next entry */
842 if (status & BD_ENET_RX_WRAP)
843 bdp = fep->rx_bd_base;
844 else
845 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
846 /* Doing this here will keep the FEC running while we process
847 * incoming frames. On a heavily loaded network, we should be
848 * able to keep up at the expense of system resources.
849 */
850 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
851 }
852 fep->cur_rx = bdp;
853
854 return pkt_received;
855 }
856
857 static irqreturn_t
858 fec_enet_interrupt(int irq, void *dev_id)
859 {
860 struct net_device *ndev = dev_id;
861 struct fec_enet_private *fep = netdev_priv(ndev);
862 uint int_events;
863 irqreturn_t ret = IRQ_NONE;
864
865 do {
866 int_events = readl(fep->hwp + FEC_IEVENT);
867 writel(int_events, fep->hwp + FEC_IEVENT);
868
869 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
870 ret = IRQ_HANDLED;
871
872 /* Disable the RX interrupt */
873 if (napi_schedule_prep(&fep->napi)) {
874 writel(FEC_RX_DISABLED_IMASK,
875 fep->hwp + FEC_IMASK);
876 __napi_schedule(&fep->napi);
877 }
878 }
879
880 if (int_events & FEC_ENET_MII) {
881 ret = IRQ_HANDLED;
882 complete(&fep->mdio_done);
883 }
884 } while (int_events);
885
886 return ret;
887 }
888
889 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
890 {
891 struct net_device *ndev = napi->dev;
892 int pkts = fec_enet_rx(ndev, budget);
893 struct fec_enet_private *fep = netdev_priv(ndev);
894
895 fec_enet_tx(ndev);
896
897 if (pkts < budget) {
898 napi_complete(napi);
899 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
900 }
901 return pkts;
902 }
903
904 /* ------------------------------------------------------------------------- */
905 static void fec_get_mac(struct net_device *ndev)
906 {
907 struct fec_enet_private *fep = netdev_priv(ndev);
908 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
909 unsigned char *iap, tmpaddr[ETH_ALEN];
910
911 /*
912 * try to get mac address in following order:
913 *
914 * 1) module parameter via kernel command line in form
915 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
916 */
917 iap = macaddr;
918
919 #ifdef CONFIG_OF
920 /*
921 * 2) from device tree data
922 */
923 if (!is_valid_ether_addr(iap)) {
924 struct device_node *np = fep->pdev->dev.of_node;
925 if (np) {
926 const char *mac = of_get_mac_address(np);
927 if (mac)
928 iap = (unsigned char *) mac;
929 }
930 }
931 #endif
932
933 /*
934 * 3) from flash or fuse (via platform data)
935 */
936 if (!is_valid_ether_addr(iap)) {
937 #ifdef CONFIG_M5272
938 if (FEC_FLASHMAC)
939 iap = (unsigned char *)FEC_FLASHMAC;
940 #else
941 if (pdata)
942 iap = (unsigned char *)&pdata->mac;
943 #endif
944 }
945
946 /*
947 * 4) FEC mac registers set by bootloader
948 */
949 if (!is_valid_ether_addr(iap)) {
950 *((unsigned long *) &tmpaddr[0]) =
951 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
952 *((unsigned short *) &tmpaddr[4]) =
953 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
954 iap = &tmpaddr[0];
955 }
956
957 memcpy(ndev->dev_addr, iap, ETH_ALEN);
958
959 /* Adjust MAC if using macaddr */
960 if (iap == macaddr)
961 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
962 }
963
964 /* ------------------------------------------------------------------------- */
965
966 /*
967 * Phy section
968 */
969 static void fec_enet_adjust_link(struct net_device *ndev)
970 {
971 struct fec_enet_private *fep = netdev_priv(ndev);
972 struct phy_device *phy_dev = fep->phy_dev;
973 unsigned long flags;
974
975 int status_change = 0;
976
977 spin_lock_irqsave(&fep->hw_lock, flags);
978
979 /* Prevent a state halted on mii error */
980 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
981 phy_dev->state = PHY_RESUMING;
982 goto spin_unlock;
983 }
984
985 if (phy_dev->link) {
986 if (!fep->link) {
987 fep->link = phy_dev->link;
988 status_change = 1;
989 }
990
991 if (fep->full_duplex != phy_dev->duplex)
992 status_change = 1;
993
994 if (phy_dev->speed != fep->speed) {
995 fep->speed = phy_dev->speed;
996 status_change = 1;
997 }
998
999 /* if any of the above changed restart the FEC */
1000 if (status_change)
1001 fec_restart(ndev, phy_dev->duplex);
1002 } else {
1003 if (fep->link) {
1004 fec_stop(ndev);
1005 fep->link = phy_dev->link;
1006 status_change = 1;
1007 }
1008 }
1009
1010 spin_unlock:
1011 spin_unlock_irqrestore(&fep->hw_lock, flags);
1012
1013 if (status_change)
1014 phy_print_status(phy_dev);
1015 }
1016
1017 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1018 {
1019 struct fec_enet_private *fep = bus->priv;
1020 unsigned long time_left;
1021
1022 fep->mii_timeout = 0;
1023 init_completion(&fep->mdio_done);
1024
1025 /* start a read op */
1026 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1027 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1028 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1029
1030 /* wait for end of transfer */
1031 time_left = wait_for_completion_timeout(&fep->mdio_done,
1032 usecs_to_jiffies(FEC_MII_TIMEOUT));
1033 if (time_left == 0) {
1034 fep->mii_timeout = 1;
1035 printk(KERN_ERR "FEC: MDIO read timeout\n");
1036 return -ETIMEDOUT;
1037 }
1038
1039 /* return value */
1040 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1041 }
1042
1043 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1044 u16 value)
1045 {
1046 struct fec_enet_private *fep = bus->priv;
1047 unsigned long time_left;
1048
1049 fep->mii_timeout = 0;
1050 init_completion(&fep->mdio_done);
1051
1052 /* start a write op */
1053 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1054 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1055 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1056 fep->hwp + FEC_MII_DATA);
1057
1058 /* wait for end of transfer */
1059 time_left = wait_for_completion_timeout(&fep->mdio_done,
1060 usecs_to_jiffies(FEC_MII_TIMEOUT));
1061 if (time_left == 0) {
1062 fep->mii_timeout = 1;
1063 printk(KERN_ERR "FEC: MDIO write timeout\n");
1064 return -ETIMEDOUT;
1065 }
1066
1067 return 0;
1068 }
1069
1070 static int fec_enet_mdio_reset(struct mii_bus *bus)
1071 {
1072 return 0;
1073 }
1074
1075 static int fec_enet_mii_probe(struct net_device *ndev)
1076 {
1077 struct fec_enet_private *fep = netdev_priv(ndev);
1078 const struct platform_device_id *id_entry =
1079 platform_get_device_id(fep->pdev);
1080 struct phy_device *phy_dev = NULL;
1081 char mdio_bus_id[MII_BUS_ID_SIZE];
1082 char phy_name[MII_BUS_ID_SIZE + 3];
1083 int phy_id;
1084 int dev_id = fep->dev_id;
1085
1086 fep->phy_dev = NULL;
1087
1088 /* check for attached phy */
1089 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1090 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1091 continue;
1092 if (fep->mii_bus->phy_map[phy_id] == NULL)
1093 continue;
1094 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1095 continue;
1096 if (dev_id--)
1097 continue;
1098 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1099 break;
1100 }
1101
1102 if (phy_id >= PHY_MAX_ADDR) {
1103 printk(KERN_INFO
1104 "%s: no PHY, assuming direct connection to switch\n",
1105 ndev->name);
1106 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1107 phy_id = 0;
1108 }
1109
1110 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1111 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1112 fep->phy_interface);
1113 if (IS_ERR(phy_dev)) {
1114 printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name);
1115 return PTR_ERR(phy_dev);
1116 }
1117
1118 /* mask with MAC supported features */
1119 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1120 phy_dev->supported &= PHY_GBIT_FEATURES;
1121 phy_dev->supported |= SUPPORTED_Pause;
1122 }
1123 else
1124 phy_dev->supported &= PHY_BASIC_FEATURES;
1125
1126 phy_dev->advertising = phy_dev->supported;
1127
1128 fep->phy_dev = phy_dev;
1129 fep->link = 0;
1130 fep->full_duplex = 0;
1131
1132 printk(KERN_INFO
1133 "%s: Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1134 ndev->name,
1135 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1136 fep->phy_dev->irq);
1137
1138 return 0;
1139 }
1140
1141 static int fec_enet_mii_init(struct platform_device *pdev)
1142 {
1143 static struct mii_bus *fec0_mii_bus;
1144 struct net_device *ndev = platform_get_drvdata(pdev);
1145 struct fec_enet_private *fep = netdev_priv(ndev);
1146 const struct platform_device_id *id_entry =
1147 platform_get_device_id(fep->pdev);
1148 int err = -ENXIO, i;
1149
1150 /*
1151 * The dual fec interfaces are not equivalent with enet-mac.
1152 * Here are the differences:
1153 *
1154 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1155 * - fec0 acts as the 1588 time master while fec1 is slave
1156 * - external phys can only be configured by fec0
1157 *
1158 * That is to say fec1 can not work independently. It only works
1159 * when fec0 is working. The reason behind this design is that the
1160 * second interface is added primarily for Switch mode.
1161 *
1162 * Because of the last point above, both phys are attached on fec0
1163 * mdio interface in board design, and need to be configured by
1164 * fec0 mii_bus.
1165 */
1166 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1167 /* fec1 uses fec0 mii_bus */
1168 if (mii_cnt && fec0_mii_bus) {
1169 fep->mii_bus = fec0_mii_bus;
1170 mii_cnt++;
1171 return 0;
1172 }
1173 return -ENOENT;
1174 }
1175
1176 fep->mii_timeout = 0;
1177
1178 /*
1179 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1180 *
1181 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1182 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1183 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1184 * document.
1185 */
1186 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
1187 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1188 fep->phy_speed--;
1189 fep->phy_speed <<= 1;
1190 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1191
1192 fep->mii_bus = mdiobus_alloc();
1193 if (fep->mii_bus == NULL) {
1194 err = -ENOMEM;
1195 goto err_out;
1196 }
1197
1198 fep->mii_bus->name = "fec_enet_mii_bus";
1199 fep->mii_bus->read = fec_enet_mdio_read;
1200 fep->mii_bus->write = fec_enet_mdio_write;
1201 fep->mii_bus->reset = fec_enet_mdio_reset;
1202 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1203 pdev->name, fep->dev_id + 1);
1204 fep->mii_bus->priv = fep;
1205 fep->mii_bus->parent = &pdev->dev;
1206
1207 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1208 if (!fep->mii_bus->irq) {
1209 err = -ENOMEM;
1210 goto err_out_free_mdiobus;
1211 }
1212
1213 for (i = 0; i < PHY_MAX_ADDR; i++)
1214 fep->mii_bus->irq[i] = PHY_POLL;
1215
1216 if (mdiobus_register(fep->mii_bus))
1217 goto err_out_free_mdio_irq;
1218
1219 mii_cnt++;
1220
1221 /* save fec0 mii_bus */
1222 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1223 fec0_mii_bus = fep->mii_bus;
1224
1225 return 0;
1226
1227 err_out_free_mdio_irq:
1228 kfree(fep->mii_bus->irq);
1229 err_out_free_mdiobus:
1230 mdiobus_free(fep->mii_bus);
1231 err_out:
1232 return err;
1233 }
1234
1235 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1236 {
1237 if (--mii_cnt == 0) {
1238 mdiobus_unregister(fep->mii_bus);
1239 kfree(fep->mii_bus->irq);
1240 mdiobus_free(fep->mii_bus);
1241 }
1242 }
1243
1244 static int fec_enet_get_settings(struct net_device *ndev,
1245 struct ethtool_cmd *cmd)
1246 {
1247 struct fec_enet_private *fep = netdev_priv(ndev);
1248 struct phy_device *phydev = fep->phy_dev;
1249
1250 if (!phydev)
1251 return -ENODEV;
1252
1253 return phy_ethtool_gset(phydev, cmd);
1254 }
1255
1256 static int fec_enet_set_settings(struct net_device *ndev,
1257 struct ethtool_cmd *cmd)
1258 {
1259 struct fec_enet_private *fep = netdev_priv(ndev);
1260 struct phy_device *phydev = fep->phy_dev;
1261
1262 if (!phydev)
1263 return -ENODEV;
1264
1265 return phy_ethtool_sset(phydev, cmd);
1266 }
1267
1268 static void fec_enet_get_drvinfo(struct net_device *ndev,
1269 struct ethtool_drvinfo *info)
1270 {
1271 struct fec_enet_private *fep = netdev_priv(ndev);
1272
1273 strlcpy(info->driver, fep->pdev->dev.driver->name,
1274 sizeof(info->driver));
1275 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1276 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1277 }
1278
1279 static int fec_enet_get_ts_info(struct net_device *ndev,
1280 struct ethtool_ts_info *info)
1281 {
1282 struct fec_enet_private *fep = netdev_priv(ndev);
1283
1284 if (fep->bufdesc_ex) {
1285
1286 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1287 SOF_TIMESTAMPING_RX_SOFTWARE |
1288 SOF_TIMESTAMPING_SOFTWARE |
1289 SOF_TIMESTAMPING_TX_HARDWARE |
1290 SOF_TIMESTAMPING_RX_HARDWARE |
1291 SOF_TIMESTAMPING_RAW_HARDWARE;
1292 if (fep->ptp_clock)
1293 info->phc_index = ptp_clock_index(fep->ptp_clock);
1294 else
1295 info->phc_index = -1;
1296
1297 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1298 (1 << HWTSTAMP_TX_ON);
1299
1300 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1301 (1 << HWTSTAMP_FILTER_ALL);
1302 return 0;
1303 } else {
1304 return ethtool_op_get_ts_info(ndev, info);
1305 }
1306 }
1307
1308 static void fec_enet_get_pauseparam(struct net_device *ndev,
1309 struct ethtool_pauseparam *pause)
1310 {
1311 struct fec_enet_private *fep = netdev_priv(ndev);
1312
1313 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1314 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1315 pause->rx_pause = pause->tx_pause;
1316 }
1317
1318 static int fec_enet_set_pauseparam(struct net_device *ndev,
1319 struct ethtool_pauseparam *pause)
1320 {
1321 struct fec_enet_private *fep = netdev_priv(ndev);
1322
1323 if (pause->tx_pause != pause->rx_pause) {
1324 netdev_info(ndev,
1325 "hardware only support enable/disable both tx and rx");
1326 return -EINVAL;
1327 }
1328
1329 fep->pause_flag = 0;
1330
1331 /* tx pause must be same as rx pause */
1332 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1333 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1334
1335 if (pause->rx_pause || pause->autoneg) {
1336 fep->phy_dev->supported |= ADVERTISED_Pause;
1337 fep->phy_dev->advertising |= ADVERTISED_Pause;
1338 } else {
1339 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1340 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1341 }
1342
1343 if (pause->autoneg) {
1344 if (netif_running(ndev))
1345 fec_stop(ndev);
1346 phy_start_aneg(fep->phy_dev);
1347 }
1348 if (netif_running(ndev))
1349 fec_restart(ndev, 0);
1350
1351 return 0;
1352 }
1353
1354 static const struct ethtool_ops fec_enet_ethtool_ops = {
1355 .get_pauseparam = fec_enet_get_pauseparam,
1356 .set_pauseparam = fec_enet_set_pauseparam,
1357 .get_settings = fec_enet_get_settings,
1358 .set_settings = fec_enet_set_settings,
1359 .get_drvinfo = fec_enet_get_drvinfo,
1360 .get_link = ethtool_op_get_link,
1361 .get_ts_info = fec_enet_get_ts_info,
1362 };
1363
1364 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1365 {
1366 struct fec_enet_private *fep = netdev_priv(ndev);
1367 struct phy_device *phydev = fep->phy_dev;
1368
1369 if (!netif_running(ndev))
1370 return -EINVAL;
1371
1372 if (!phydev)
1373 return -ENODEV;
1374
1375 if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex)
1376 return fec_ptp_ioctl(ndev, rq, cmd);
1377
1378 return phy_mii_ioctl(phydev, rq, cmd);
1379 }
1380
1381 static void fec_enet_free_buffers(struct net_device *ndev)
1382 {
1383 struct fec_enet_private *fep = netdev_priv(ndev);
1384 unsigned int i;
1385 struct sk_buff *skb;
1386 struct bufdesc *bdp;
1387
1388 bdp = fep->rx_bd_base;
1389 for (i = 0; i < RX_RING_SIZE; i++) {
1390 skb = fep->rx_skbuff[i];
1391
1392 if (bdp->cbd_bufaddr)
1393 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1394 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1395 if (skb)
1396 dev_kfree_skb(skb);
1397 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1398 }
1399
1400 bdp = fep->tx_bd_base;
1401 for (i = 0; i < TX_RING_SIZE; i++)
1402 kfree(fep->tx_bounce[i]);
1403 }
1404
1405 static int fec_enet_alloc_buffers(struct net_device *ndev)
1406 {
1407 struct fec_enet_private *fep = netdev_priv(ndev);
1408 unsigned int i;
1409 struct sk_buff *skb;
1410 struct bufdesc *bdp;
1411
1412 bdp = fep->rx_bd_base;
1413 for (i = 0; i < RX_RING_SIZE; i++) {
1414 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1415 if (!skb) {
1416 fec_enet_free_buffers(ndev);
1417 return -ENOMEM;
1418 }
1419 fep->rx_skbuff[i] = skb;
1420
1421 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1422 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1423 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1424
1425 if (fep->bufdesc_ex) {
1426 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1427 ebdp->cbd_esc = BD_ENET_RX_INT;
1428 }
1429
1430 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1431 }
1432
1433 /* Set the last buffer to wrap. */
1434 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1435 bdp->cbd_sc |= BD_SC_WRAP;
1436
1437 bdp = fep->tx_bd_base;
1438 for (i = 0; i < TX_RING_SIZE; i++) {
1439 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1440
1441 bdp->cbd_sc = 0;
1442 bdp->cbd_bufaddr = 0;
1443
1444 if (fep->bufdesc_ex) {
1445 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1446 ebdp->cbd_esc = BD_ENET_RX_INT;
1447 }
1448
1449 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1450 }
1451
1452 /* Set the last buffer to wrap. */
1453 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1454 bdp->cbd_sc |= BD_SC_WRAP;
1455
1456 return 0;
1457 }
1458
1459 static int
1460 fec_enet_open(struct net_device *ndev)
1461 {
1462 struct fec_enet_private *fep = netdev_priv(ndev);
1463 int ret;
1464
1465 napi_enable(&fep->napi);
1466
1467 /* I should reset the ring buffers here, but I don't yet know
1468 * a simple way to do that.
1469 */
1470
1471 ret = fec_enet_alloc_buffers(ndev);
1472 if (ret)
1473 return ret;
1474
1475 /* Probe and connect to PHY when open the interface */
1476 ret = fec_enet_mii_probe(ndev);
1477 if (ret) {
1478 fec_enet_free_buffers(ndev);
1479 return ret;
1480 }
1481 phy_start(fep->phy_dev);
1482 netif_start_queue(ndev);
1483 fep->opened = 1;
1484 return 0;
1485 }
1486
1487 static int
1488 fec_enet_close(struct net_device *ndev)
1489 {
1490 struct fec_enet_private *fep = netdev_priv(ndev);
1491
1492 /* Don't know what to do yet. */
1493 napi_disable(&fep->napi);
1494 fep->opened = 0;
1495 netif_stop_queue(ndev);
1496 fec_stop(ndev);
1497
1498 if (fep->phy_dev) {
1499 phy_stop(fep->phy_dev);
1500 phy_disconnect(fep->phy_dev);
1501 }
1502
1503 fec_enet_free_buffers(ndev);
1504
1505 return 0;
1506 }
1507
1508 /* Set or clear the multicast filter for this adaptor.
1509 * Skeleton taken from sunlance driver.
1510 * The CPM Ethernet implementation allows Multicast as well as individual
1511 * MAC address filtering. Some of the drivers check to make sure it is
1512 * a group multicast address, and discard those that are not. I guess I
1513 * will do the same for now, but just remove the test if you want
1514 * individual filtering as well (do the upper net layers want or support
1515 * this kind of feature?).
1516 */
1517
1518 #define HASH_BITS 6 /* #bits in hash */
1519 #define CRC32_POLY 0xEDB88320
1520
1521 static void set_multicast_list(struct net_device *ndev)
1522 {
1523 struct fec_enet_private *fep = netdev_priv(ndev);
1524 struct netdev_hw_addr *ha;
1525 unsigned int i, bit, data, crc, tmp;
1526 unsigned char hash;
1527
1528 if (ndev->flags & IFF_PROMISC) {
1529 tmp = readl(fep->hwp + FEC_R_CNTRL);
1530 tmp |= 0x8;
1531 writel(tmp, fep->hwp + FEC_R_CNTRL);
1532 return;
1533 }
1534
1535 tmp = readl(fep->hwp + FEC_R_CNTRL);
1536 tmp &= ~0x8;
1537 writel(tmp, fep->hwp + FEC_R_CNTRL);
1538
1539 if (ndev->flags & IFF_ALLMULTI) {
1540 /* Catch all multicast addresses, so set the
1541 * filter to all 1's
1542 */
1543 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1544 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1545
1546 return;
1547 }
1548
1549 /* Clear filter and add the addresses in hash register
1550 */
1551 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1552 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1553
1554 netdev_for_each_mc_addr(ha, ndev) {
1555 /* calculate crc32 value of mac address */
1556 crc = 0xffffffff;
1557
1558 for (i = 0; i < ndev->addr_len; i++) {
1559 data = ha->addr[i];
1560 for (bit = 0; bit < 8; bit++, data >>= 1) {
1561 crc = (crc >> 1) ^
1562 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1563 }
1564 }
1565
1566 /* only upper 6 bits (HASH_BITS) are used
1567 * which point to specific bit in he hash registers
1568 */
1569 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1570
1571 if (hash > 31) {
1572 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1573 tmp |= 1 << (hash - 32);
1574 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1575 } else {
1576 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1577 tmp |= 1 << hash;
1578 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1579 }
1580 }
1581 }
1582
1583 /* Set a MAC change in hardware. */
1584 static int
1585 fec_set_mac_address(struct net_device *ndev, void *p)
1586 {
1587 struct fec_enet_private *fep = netdev_priv(ndev);
1588 struct sockaddr *addr = p;
1589
1590 if (!is_valid_ether_addr(addr->sa_data))
1591 return -EADDRNOTAVAIL;
1592
1593 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1594
1595 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1596 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1597 fep->hwp + FEC_ADDR_LOW);
1598 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1599 fep->hwp + FEC_ADDR_HIGH);
1600 return 0;
1601 }
1602
1603 #ifdef CONFIG_NET_POLL_CONTROLLER
1604 /**
1605 * fec_poll_controller - FEC Poll controller function
1606 * @dev: The FEC network adapter
1607 *
1608 * Polled functionality used by netconsole and others in non interrupt mode
1609 *
1610 */
1611 void fec_poll_controller(struct net_device *dev)
1612 {
1613 int i;
1614 struct fec_enet_private *fep = netdev_priv(dev);
1615
1616 for (i = 0; i < FEC_IRQ_NUM; i++) {
1617 if (fep->irq[i] > 0) {
1618 disable_irq(fep->irq[i]);
1619 fec_enet_interrupt(fep->irq[i], dev);
1620 enable_irq(fep->irq[i]);
1621 }
1622 }
1623 }
1624 #endif
1625
1626 static const struct net_device_ops fec_netdev_ops = {
1627 .ndo_open = fec_enet_open,
1628 .ndo_stop = fec_enet_close,
1629 .ndo_start_xmit = fec_enet_start_xmit,
1630 .ndo_set_rx_mode = set_multicast_list,
1631 .ndo_change_mtu = eth_change_mtu,
1632 .ndo_validate_addr = eth_validate_addr,
1633 .ndo_tx_timeout = fec_timeout,
1634 .ndo_set_mac_address = fec_set_mac_address,
1635 .ndo_do_ioctl = fec_enet_ioctl,
1636 #ifdef CONFIG_NET_POLL_CONTROLLER
1637 .ndo_poll_controller = fec_poll_controller,
1638 #endif
1639 };
1640
1641 /*
1642 * XXX: We need to clean up on failure exits here.
1643 *
1644 */
1645 static int fec_enet_init(struct net_device *ndev)
1646 {
1647 struct fec_enet_private *fep = netdev_priv(ndev);
1648 struct bufdesc *cbd_base;
1649
1650 /* Allocate memory for buffer descriptors. */
1651 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1652 GFP_KERNEL);
1653 if (!cbd_base) {
1654 printk("FEC: allocate descriptor memory failed?\n");
1655 return -ENOMEM;
1656 }
1657
1658 memset(cbd_base, 0, PAGE_SIZE);
1659 spin_lock_init(&fep->hw_lock);
1660
1661 fep->netdev = ndev;
1662
1663 /* Get the Ethernet address */
1664 fec_get_mac(ndev);
1665
1666 /* Set receive and transmit descriptor base. */
1667 fep->rx_bd_base = cbd_base;
1668 if (fep->bufdesc_ex)
1669 fep->tx_bd_base = (struct bufdesc *)
1670 (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE);
1671 else
1672 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1673
1674 /* The FEC Ethernet specific entries in the device structure */
1675 ndev->watchdog_timeo = TX_TIMEOUT;
1676 ndev->netdev_ops = &fec_netdev_ops;
1677 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1678
1679 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
1680 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT);
1681
1682 fec_restart(ndev, 0);
1683
1684 return 0;
1685 }
1686
1687 #ifdef CONFIG_OF
1688 static int fec_get_phy_mode_dt(struct platform_device *pdev)
1689 {
1690 struct device_node *np = pdev->dev.of_node;
1691
1692 if (np)
1693 return of_get_phy_mode(np);
1694
1695 return -ENODEV;
1696 }
1697
1698 static void fec_reset_phy(struct platform_device *pdev)
1699 {
1700 int err, phy_reset;
1701 int msec = 1;
1702 struct device_node *np = pdev->dev.of_node;
1703
1704 if (!np)
1705 return;
1706
1707 of_property_read_u32(np, "phy-reset-duration", &msec);
1708 /* A sane reset duration should not be longer than 1s */
1709 if (msec > 1000)
1710 msec = 1;
1711
1712 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
1713 if (!gpio_is_valid(phy_reset))
1714 return;
1715
1716 err = devm_gpio_request_one(&pdev->dev, phy_reset,
1717 GPIOF_OUT_INIT_LOW, "phy-reset");
1718 if (err) {
1719 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
1720 return;
1721 }
1722 msleep(msec);
1723 gpio_set_value(phy_reset, 1);
1724 }
1725 #else /* CONFIG_OF */
1726 static int fec_get_phy_mode_dt(struct platform_device *pdev)
1727 {
1728 return -ENODEV;
1729 }
1730
1731 static void fec_reset_phy(struct platform_device *pdev)
1732 {
1733 /*
1734 * In case of platform probe, the reset has been done
1735 * by machine code.
1736 */
1737 }
1738 #endif /* CONFIG_OF */
1739
1740 static int
1741 fec_probe(struct platform_device *pdev)
1742 {
1743 struct fec_enet_private *fep;
1744 struct fec_platform_data *pdata;
1745 struct net_device *ndev;
1746 int i, irq, ret = 0;
1747 struct resource *r;
1748 const struct of_device_id *of_id;
1749 static int dev_id;
1750 struct pinctrl *pinctrl;
1751 struct regulator *reg_phy;
1752
1753 of_id = of_match_device(fec_dt_ids, &pdev->dev);
1754 if (of_id)
1755 pdev->id_entry = of_id->data;
1756
1757 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1758 if (!r)
1759 return -ENXIO;
1760
1761 r = request_mem_region(r->start, resource_size(r), pdev->name);
1762 if (!r)
1763 return -EBUSY;
1764
1765 /* Init network device */
1766 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1767 if (!ndev) {
1768 ret = -ENOMEM;
1769 goto failed_alloc_etherdev;
1770 }
1771
1772 SET_NETDEV_DEV(ndev, &pdev->dev);
1773
1774 /* setup board info structure */
1775 fep = netdev_priv(ndev);
1776
1777 /* default enable pause frame auto negotiation */
1778 if (pdev->id_entry &&
1779 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
1780 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
1781
1782 fep->hwp = ioremap(r->start, resource_size(r));
1783 fep->pdev = pdev;
1784 fep->dev_id = dev_id++;
1785
1786 fep->bufdesc_ex = 0;
1787
1788 if (!fep->hwp) {
1789 ret = -ENOMEM;
1790 goto failed_ioremap;
1791 }
1792
1793 platform_set_drvdata(pdev, ndev);
1794
1795 ret = fec_get_phy_mode_dt(pdev);
1796 if (ret < 0) {
1797 pdata = pdev->dev.platform_data;
1798 if (pdata)
1799 fep->phy_interface = pdata->phy;
1800 else
1801 fep->phy_interface = PHY_INTERFACE_MODE_MII;
1802 } else {
1803 fep->phy_interface = ret;
1804 }
1805
1806 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1807 if (IS_ERR(pinctrl)) {
1808 ret = PTR_ERR(pinctrl);
1809 goto failed_pin;
1810 }
1811
1812 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1813 if (IS_ERR(fep->clk_ipg)) {
1814 ret = PTR_ERR(fep->clk_ipg);
1815 goto failed_clk;
1816 }
1817
1818 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1819 if (IS_ERR(fep->clk_ahb)) {
1820 ret = PTR_ERR(fep->clk_ahb);
1821 goto failed_clk;
1822 }
1823
1824 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
1825 fep->bufdesc_ex =
1826 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
1827 if (IS_ERR(fep->clk_ptp)) {
1828 ret = PTR_ERR(fep->clk_ptp);
1829 fep->bufdesc_ex = 0;
1830 }
1831
1832 clk_prepare_enable(fep->clk_ahb);
1833 clk_prepare_enable(fep->clk_ipg);
1834 if (!IS_ERR(fep->clk_ptp))
1835 clk_prepare_enable(fep->clk_ptp);
1836
1837 reg_phy = devm_regulator_get(&pdev->dev, "phy");
1838 if (!IS_ERR(reg_phy)) {
1839 ret = regulator_enable(reg_phy);
1840 if (ret) {
1841 dev_err(&pdev->dev,
1842 "Failed to enable phy regulator: %d\n", ret);
1843 goto failed_regulator;
1844 }
1845 }
1846
1847 fec_reset_phy(pdev);
1848
1849 if (fep->bufdesc_ex)
1850 fec_ptp_init(ndev, pdev);
1851
1852 ret = fec_enet_init(ndev);
1853 if (ret)
1854 goto failed_init;
1855
1856 for (i = 0; i < FEC_IRQ_NUM; i++) {
1857 irq = platform_get_irq(pdev, i);
1858 if (irq < 0) {
1859 if (i)
1860 break;
1861 ret = irq;
1862 goto failed_irq;
1863 }
1864 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1865 if (ret) {
1866 while (--i >= 0) {
1867 irq = platform_get_irq(pdev, i);
1868 free_irq(irq, ndev);
1869 }
1870 goto failed_irq;
1871 }
1872 }
1873
1874 ret = fec_enet_mii_init(pdev);
1875 if (ret)
1876 goto failed_mii_init;
1877
1878 /* Carrier starts down, phylib will bring it up */
1879 netif_carrier_off(ndev);
1880
1881 ret = register_netdev(ndev);
1882 if (ret)
1883 goto failed_register;
1884
1885 return 0;
1886
1887 failed_register:
1888 fec_enet_mii_remove(fep);
1889 failed_mii_init:
1890 failed_init:
1891 for (i = 0; i < FEC_IRQ_NUM; i++) {
1892 irq = platform_get_irq(pdev, i);
1893 if (irq > 0)
1894 free_irq(irq, ndev);
1895 }
1896 failed_irq:
1897 failed_regulator:
1898 clk_disable_unprepare(fep->clk_ahb);
1899 clk_disable_unprepare(fep->clk_ipg);
1900 if (!IS_ERR(fep->clk_ptp))
1901 clk_disable_unprepare(fep->clk_ptp);
1902 failed_pin:
1903 failed_clk:
1904 iounmap(fep->hwp);
1905 failed_ioremap:
1906 free_netdev(ndev);
1907 failed_alloc_etherdev:
1908 release_mem_region(r->start, resource_size(r));
1909
1910 return ret;
1911 }
1912
1913 static int
1914 fec_drv_remove(struct platform_device *pdev)
1915 {
1916 struct net_device *ndev = platform_get_drvdata(pdev);
1917 struct fec_enet_private *fep = netdev_priv(ndev);
1918 struct resource *r;
1919 int i;
1920
1921 unregister_netdev(ndev);
1922 fec_enet_mii_remove(fep);
1923 del_timer_sync(&fep->time_keep);
1924 clk_disable_unprepare(fep->clk_ptp);
1925 if (fep->ptp_clock)
1926 ptp_clock_unregister(fep->ptp_clock);
1927 clk_disable_unprepare(fep->clk_ahb);
1928 clk_disable_unprepare(fep->clk_ipg);
1929 for (i = 0; i < FEC_IRQ_NUM; i++) {
1930 int irq = platform_get_irq(pdev, i);
1931 if (irq > 0)
1932 free_irq(irq, ndev);
1933 }
1934 iounmap(fep->hwp);
1935 free_netdev(ndev);
1936
1937 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1938 BUG_ON(!r);
1939 release_mem_region(r->start, resource_size(r));
1940
1941 platform_set_drvdata(pdev, NULL);
1942
1943 return 0;
1944 }
1945
1946 #ifdef CONFIG_PM
1947 static int
1948 fec_suspend(struct device *dev)
1949 {
1950 struct net_device *ndev = dev_get_drvdata(dev);
1951 struct fec_enet_private *fep = netdev_priv(ndev);
1952
1953 if (netif_running(ndev)) {
1954 fec_stop(ndev);
1955 netif_device_detach(ndev);
1956 }
1957 clk_disable_unprepare(fep->clk_ahb);
1958 clk_disable_unprepare(fep->clk_ipg);
1959
1960 return 0;
1961 }
1962
1963 static int
1964 fec_resume(struct device *dev)
1965 {
1966 struct net_device *ndev = dev_get_drvdata(dev);
1967 struct fec_enet_private *fep = netdev_priv(ndev);
1968
1969 clk_prepare_enable(fep->clk_ahb);
1970 clk_prepare_enable(fep->clk_ipg);
1971 if (netif_running(ndev)) {
1972 fec_restart(ndev, fep->full_duplex);
1973 netif_device_attach(ndev);
1974 }
1975
1976 return 0;
1977 }
1978
1979 static const struct dev_pm_ops fec_pm_ops = {
1980 .suspend = fec_suspend,
1981 .resume = fec_resume,
1982 .freeze = fec_suspend,
1983 .thaw = fec_resume,
1984 .poweroff = fec_suspend,
1985 .restore = fec_resume,
1986 };
1987 #endif
1988
1989 static struct platform_driver fec_driver = {
1990 .driver = {
1991 .name = DRIVER_NAME,
1992 .owner = THIS_MODULE,
1993 #ifdef CONFIG_PM
1994 .pm = &fec_pm_ops,
1995 #endif
1996 .of_match_table = fec_dt_ids,
1997 },
1998 .id_table = fec_devtype,
1999 .probe = fec_probe,
2000 .remove = fec_drv_remove,
2001 };
2002
2003 module_platform_driver(fec_driver);
2004
2005 MODULE_LICENSE("GPL");
Ubuntu Hirsute Linux kernel mirror