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[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / freescale / fec_main.c
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 *
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/ptrace.h>
29 #include <linux/errno.h>
30 #include <linux/ioport.h>
31 #include <linux/slab.h>
32 #include <linux/interrupt.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/in.h>
38 #include <linux/ip.h>
39 #include <net/ip.h>
40 #include <net/tso.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/icmp.h>
44 #include <linux/spinlock.h>
45 #include <linux/workqueue.h>
46 #include <linux/bitops.h>
47 #include <linux/io.h>
48 #include <linux/irq.h>
49 #include <linux/clk.h>
50 #include <linux/platform_device.h>
51 #include <linux/phy.h>
52 #include <linux/fec.h>
53 #include <linux/of.h>
54 #include <linux/of_device.h>
55 #include <linux/of_gpio.h>
56 #include <linux/of_mdio.h>
57 #include <linux/of_net.h>
58 #include <linux/regulator/consumer.h>
59 #include <linux/if_vlan.h>
60 #include <linux/pinctrl/consumer.h>
61 #include <linux/prefetch.h>
62
63 #include <asm/cacheflush.h>
64
65 #include "fec.h"
66
67 static void set_multicast_list(struct net_device *ndev);
68 static void fec_enet_itr_coal_init(struct net_device *ndev);
69
70 #define DRIVER_NAME "fec"
71
72 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
73
74 /* Pause frame feild and FIFO threshold */
75 #define FEC_ENET_FCE (1 << 5)
76 #define FEC_ENET_RSEM_V 0x84
77 #define FEC_ENET_RSFL_V 16
78 #define FEC_ENET_RAEM_V 0x8
79 #define FEC_ENET_RAFL_V 0x8
80 #define FEC_ENET_OPD_V 0xFFF0
81 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */
82
83 static struct platform_device_id fec_devtype[] = {
84 {
85 /* keep it for coldfire */
86 .name = DRIVER_NAME,
87 .driver_data = 0,
88 }, {
89 .name = "imx25-fec",
90 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_HAS_RACC,
91 }, {
92 .name = "imx27-fec",
93 .driver_data = FEC_QUIRK_HAS_RACC,
94 }, {
95 .name = "imx28-fec",
96 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
97 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC,
98 }, {
99 .name = "imx6q-fec",
100 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
101 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
102 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
103 FEC_QUIRK_HAS_RACC,
104 }, {
105 .name = "mvf600-fec",
106 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
107 }, {
108 .name = "imx6sx-fec",
109 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
110 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
111 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
112 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
113 FEC_QUIRK_HAS_RACC,
114 }, {
115 /* sentinel */
116 }
117 };
118 MODULE_DEVICE_TABLE(platform, fec_devtype);
119
120 enum imx_fec_type {
121 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
122 IMX27_FEC, /* runs on i.mx27/35/51 */
123 IMX28_FEC,
124 IMX6Q_FEC,
125 MVF600_FEC,
126 IMX6SX_FEC,
127 };
128
129 static const struct of_device_id fec_dt_ids[] = {
130 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
131 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
132 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
133 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
134 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
135 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
136 { /* sentinel */ }
137 };
138 MODULE_DEVICE_TABLE(of, fec_dt_ids);
139
140 static unsigned char macaddr[ETH_ALEN];
141 module_param_array(macaddr, byte, NULL, 0);
142 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
143
144 #if defined(CONFIG_M5272)
145 /*
146 * Some hardware gets it MAC address out of local flash memory.
147 * if this is non-zero then assume it is the address to get MAC from.
148 */
149 #if defined(CONFIG_NETtel)
150 #define FEC_FLASHMAC 0xf0006006
151 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
152 #define FEC_FLASHMAC 0xf0006000
153 #elif defined(CONFIG_CANCam)
154 #define FEC_FLASHMAC 0xf0020000
155 #elif defined (CONFIG_M5272C3)
156 #define FEC_FLASHMAC (0xffe04000 + 4)
157 #elif defined(CONFIG_MOD5272)
158 #define FEC_FLASHMAC 0xffc0406b
159 #else
160 #define FEC_FLASHMAC 0
161 #endif
162 #endif /* CONFIG_M5272 */
163
164 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
165 */
166 #define PKT_MAXBUF_SIZE 1522
167 #define PKT_MINBUF_SIZE 64
168 #define PKT_MAXBLR_SIZE 1536
169
170 /* FEC receive acceleration */
171 #define FEC_RACC_IPDIS (1 << 1)
172 #define FEC_RACC_PRODIS (1 << 2)
173 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
174
175 /*
176 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
177 * size bits. Other FEC hardware does not, so we need to take that into
178 * account when setting it.
179 */
180 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
181 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
182 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
183 #else
184 #define OPT_FRAME_SIZE 0
185 #endif
186
187 /* FEC MII MMFR bits definition */
188 #define FEC_MMFR_ST (1 << 30)
189 #define FEC_MMFR_OP_READ (2 << 28)
190 #define FEC_MMFR_OP_WRITE (1 << 28)
191 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
192 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
193 #define FEC_MMFR_TA (2 << 16)
194 #define FEC_MMFR_DATA(v) (v & 0xffff)
195 /* FEC ECR bits definition */
196 #define FEC_ECR_MAGICEN (1 << 2)
197 #define FEC_ECR_SLEEP (1 << 3)
198
199 #define FEC_MII_TIMEOUT 30000 /* us */
200
201 /* Transmitter timeout */
202 #define TX_TIMEOUT (2 * HZ)
203
204 #define FEC_PAUSE_FLAG_AUTONEG 0x1
205 #define FEC_PAUSE_FLAG_ENABLE 0x2
206 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
207 #define FEC_WOL_FLAG_ENABLE (0x1 << 1)
208 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
209
210 #define COPYBREAK_DEFAULT 256
211
212 #define TSO_HEADER_SIZE 128
213 /* Max number of allowed TCP segments for software TSO */
214 #define FEC_MAX_TSO_SEGS 100
215 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
216
217 #define IS_TSO_HEADER(txq, addr) \
218 ((addr >= txq->tso_hdrs_dma) && \
219 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
220
221 static int mii_cnt;
222
223 static inline
224 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
225 struct fec_enet_private *fep,
226 int queue_id)
227 {
228 struct bufdesc *new_bd = bdp + 1;
229 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
230 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
231 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
232 struct bufdesc_ex *ex_base;
233 struct bufdesc *base;
234 int ring_size;
235
236 if (bdp >= txq->tx_bd_base) {
237 base = txq->tx_bd_base;
238 ring_size = txq->tx_ring_size;
239 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
240 } else {
241 base = rxq->rx_bd_base;
242 ring_size = rxq->rx_ring_size;
243 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
244 }
245
246 if (fep->bufdesc_ex)
247 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
248 ex_base : ex_new_bd);
249 else
250 return (new_bd >= (base + ring_size)) ?
251 base : new_bd;
252 }
253
254 static inline
255 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
256 struct fec_enet_private *fep,
257 int queue_id)
258 {
259 struct bufdesc *new_bd = bdp - 1;
260 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
261 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
262 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
263 struct bufdesc_ex *ex_base;
264 struct bufdesc *base;
265 int ring_size;
266
267 if (bdp >= txq->tx_bd_base) {
268 base = txq->tx_bd_base;
269 ring_size = txq->tx_ring_size;
270 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
271 } else {
272 base = rxq->rx_bd_base;
273 ring_size = rxq->rx_ring_size;
274 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
275 }
276
277 if (fep->bufdesc_ex)
278 return (struct bufdesc *)((ex_new_bd < ex_base) ?
279 (ex_new_bd + ring_size) : ex_new_bd);
280 else
281 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
282 }
283
284 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
285 struct fec_enet_private *fep)
286 {
287 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
288 }
289
290 static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep,
291 struct fec_enet_priv_tx_q *txq)
292 {
293 int entries;
294
295 entries = ((const char *)txq->dirty_tx -
296 (const char *)txq->cur_tx) / fep->bufdesc_size - 1;
297
298 return entries > 0 ? entries : entries + txq->tx_ring_size;
299 }
300
301 static void swap_buffer(void *bufaddr, int len)
302 {
303 int i;
304 unsigned int *buf = bufaddr;
305
306 for (i = 0; i < len; i += 4, buf++)
307 swab32s(buf);
308 }
309
310 static void swap_buffer2(void *dst_buf, void *src_buf, int len)
311 {
312 int i;
313 unsigned int *src = src_buf;
314 unsigned int *dst = dst_buf;
315
316 for (i = 0; i < len; i += 4, src++, dst++)
317 *dst = swab32p(src);
318 }
319
320 static void fec_dump(struct net_device *ndev)
321 {
322 struct fec_enet_private *fep = netdev_priv(ndev);
323 struct bufdesc *bdp;
324 struct fec_enet_priv_tx_q *txq;
325 int index = 0;
326
327 netdev_info(ndev, "TX ring dump\n");
328 pr_info("Nr SC addr len SKB\n");
329
330 txq = fep->tx_queue[0];
331 bdp = txq->tx_bd_base;
332
333 do {
334 pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p\n",
335 index,
336 bdp == txq->cur_tx ? 'S' : ' ',
337 bdp == txq->dirty_tx ? 'H' : ' ',
338 bdp->cbd_sc, bdp->cbd_bufaddr, bdp->cbd_datlen,
339 txq->tx_skbuff[index]);
340 bdp = fec_enet_get_nextdesc(bdp, fep, 0);
341 index++;
342 } while (bdp != txq->tx_bd_base);
343 }
344
345 static inline bool is_ipv4_pkt(struct sk_buff *skb)
346 {
347 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
348 }
349
350 static int
351 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
352 {
353 /* Only run for packets requiring a checksum. */
354 if (skb->ip_summed != CHECKSUM_PARTIAL)
355 return 0;
356
357 if (unlikely(skb_cow_head(skb, 0)))
358 return -1;
359
360 if (is_ipv4_pkt(skb))
361 ip_hdr(skb)->check = 0;
362 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
363
364 return 0;
365 }
366
367 static int
368 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
369 struct sk_buff *skb,
370 struct net_device *ndev)
371 {
372 struct fec_enet_private *fep = netdev_priv(ndev);
373 struct bufdesc *bdp = txq->cur_tx;
374 struct bufdesc_ex *ebdp;
375 int nr_frags = skb_shinfo(skb)->nr_frags;
376 unsigned short queue = skb_get_queue_mapping(skb);
377 int frag, frag_len;
378 unsigned short status;
379 unsigned int estatus = 0;
380 skb_frag_t *this_frag;
381 unsigned int index;
382 void *bufaddr;
383 dma_addr_t addr;
384 int i;
385
386 for (frag = 0; frag < nr_frags; frag++) {
387 this_frag = &skb_shinfo(skb)->frags[frag];
388 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
389 ebdp = (struct bufdesc_ex *)bdp;
390
391 status = bdp->cbd_sc;
392 status &= ~BD_ENET_TX_STATS;
393 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
394 frag_len = skb_shinfo(skb)->frags[frag].size;
395
396 /* Handle the last BD specially */
397 if (frag == nr_frags - 1) {
398 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
399 if (fep->bufdesc_ex) {
400 estatus |= BD_ENET_TX_INT;
401 if (unlikely(skb_shinfo(skb)->tx_flags &
402 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
403 estatus |= BD_ENET_TX_TS;
404 }
405 }
406
407 if (fep->bufdesc_ex) {
408 if (fep->quirks & FEC_QUIRK_HAS_AVB)
409 estatus |= FEC_TX_BD_FTYPE(queue);
410 if (skb->ip_summed == CHECKSUM_PARTIAL)
411 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
412 ebdp->cbd_bdu = 0;
413 ebdp->cbd_esc = estatus;
414 }
415
416 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
417
418 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
419 if (((unsigned long) bufaddr) & fep->tx_align ||
420 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
421 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
422 bufaddr = txq->tx_bounce[index];
423
424 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
425 swap_buffer(bufaddr, frag_len);
426 }
427
428 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
429 DMA_TO_DEVICE);
430 if (dma_mapping_error(&fep->pdev->dev, addr)) {
431 dev_kfree_skb_any(skb);
432 if (net_ratelimit())
433 netdev_err(ndev, "Tx DMA memory map failed\n");
434 goto dma_mapping_error;
435 }
436
437 bdp->cbd_bufaddr = addr;
438 bdp->cbd_datlen = frag_len;
439 bdp->cbd_sc = status;
440 }
441
442 txq->cur_tx = bdp;
443
444 return 0;
445
446 dma_mapping_error:
447 bdp = txq->cur_tx;
448 for (i = 0; i < frag; i++) {
449 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
450 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
451 bdp->cbd_datlen, DMA_TO_DEVICE);
452 }
453 return NETDEV_TX_OK;
454 }
455
456 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
457 struct sk_buff *skb, struct net_device *ndev)
458 {
459 struct fec_enet_private *fep = netdev_priv(ndev);
460 int nr_frags = skb_shinfo(skb)->nr_frags;
461 struct bufdesc *bdp, *last_bdp;
462 void *bufaddr;
463 dma_addr_t addr;
464 unsigned short status;
465 unsigned short buflen;
466 unsigned short queue;
467 unsigned int estatus = 0;
468 unsigned int index;
469 int entries_free;
470 int ret;
471
472 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
473 if (entries_free < MAX_SKB_FRAGS + 1) {
474 dev_kfree_skb_any(skb);
475 if (net_ratelimit())
476 netdev_err(ndev, "NOT enough BD for SG!\n");
477 return NETDEV_TX_OK;
478 }
479
480 /* Protocol checksum off-load for TCP and UDP. */
481 if (fec_enet_clear_csum(skb, ndev)) {
482 dev_kfree_skb_any(skb);
483 return NETDEV_TX_OK;
484 }
485
486 /* Fill in a Tx ring entry */
487 bdp = txq->cur_tx;
488 status = bdp->cbd_sc;
489 status &= ~BD_ENET_TX_STATS;
490
491 /* Set buffer length and buffer pointer */
492 bufaddr = skb->data;
493 buflen = skb_headlen(skb);
494
495 queue = skb_get_queue_mapping(skb);
496 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
497 if (((unsigned long) bufaddr) & fep->tx_align ||
498 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
499 memcpy(txq->tx_bounce[index], skb->data, buflen);
500 bufaddr = txq->tx_bounce[index];
501
502 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
503 swap_buffer(bufaddr, buflen);
504 }
505
506 /* Push the data cache so the CPM does not get stale memory data. */
507 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
508 if (dma_mapping_error(&fep->pdev->dev, addr)) {
509 dev_kfree_skb_any(skb);
510 if (net_ratelimit())
511 netdev_err(ndev, "Tx DMA memory map failed\n");
512 return NETDEV_TX_OK;
513 }
514
515 if (nr_frags) {
516 ret = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
517 if (ret)
518 return ret;
519 } else {
520 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
521 if (fep->bufdesc_ex) {
522 estatus = BD_ENET_TX_INT;
523 if (unlikely(skb_shinfo(skb)->tx_flags &
524 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
525 estatus |= BD_ENET_TX_TS;
526 }
527 }
528
529 if (fep->bufdesc_ex) {
530
531 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
532
533 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
534 fep->hwts_tx_en))
535 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
536
537 if (fep->quirks & FEC_QUIRK_HAS_AVB)
538 estatus |= FEC_TX_BD_FTYPE(queue);
539
540 if (skb->ip_summed == CHECKSUM_PARTIAL)
541 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
542
543 ebdp->cbd_bdu = 0;
544 ebdp->cbd_esc = estatus;
545 }
546
547 last_bdp = txq->cur_tx;
548 index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep);
549 /* Save skb pointer */
550 txq->tx_skbuff[index] = skb;
551
552 bdp->cbd_datlen = buflen;
553 bdp->cbd_bufaddr = addr;
554
555 /* Send it on its way. Tell FEC it's ready, interrupt when done,
556 * it's the last BD of the frame, and to put the CRC on the end.
557 */
558 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
559 bdp->cbd_sc = status;
560
561 /* If this was the last BD in the ring, start at the beginning again. */
562 bdp = fec_enet_get_nextdesc(last_bdp, fep, queue);
563
564 skb_tx_timestamp(skb);
565
566 txq->cur_tx = bdp;
567
568 /* Trigger transmission start */
569 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
570
571 return 0;
572 }
573
574 static int
575 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
576 struct net_device *ndev,
577 struct bufdesc *bdp, int index, char *data,
578 int size, bool last_tcp, bool is_last)
579 {
580 struct fec_enet_private *fep = netdev_priv(ndev);
581 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
582 unsigned short queue = skb_get_queue_mapping(skb);
583 unsigned short status;
584 unsigned int estatus = 0;
585 dma_addr_t addr;
586
587 status = bdp->cbd_sc;
588 status &= ~BD_ENET_TX_STATS;
589
590 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
591
592 if (((unsigned long) data) & fep->tx_align ||
593 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
594 memcpy(txq->tx_bounce[index], data, size);
595 data = txq->tx_bounce[index];
596
597 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
598 swap_buffer(data, size);
599 }
600
601 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
602 if (dma_mapping_error(&fep->pdev->dev, addr)) {
603 dev_kfree_skb_any(skb);
604 if (net_ratelimit())
605 netdev_err(ndev, "Tx DMA memory map failed\n");
606 return NETDEV_TX_BUSY;
607 }
608
609 bdp->cbd_datlen = size;
610 bdp->cbd_bufaddr = addr;
611
612 if (fep->bufdesc_ex) {
613 if (fep->quirks & FEC_QUIRK_HAS_AVB)
614 estatus |= FEC_TX_BD_FTYPE(queue);
615 if (skb->ip_summed == CHECKSUM_PARTIAL)
616 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
617 ebdp->cbd_bdu = 0;
618 ebdp->cbd_esc = estatus;
619 }
620
621 /* Handle the last BD specially */
622 if (last_tcp)
623 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
624 if (is_last) {
625 status |= BD_ENET_TX_INTR;
626 if (fep->bufdesc_ex)
627 ebdp->cbd_esc |= BD_ENET_TX_INT;
628 }
629
630 bdp->cbd_sc = status;
631
632 return 0;
633 }
634
635 static int
636 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
637 struct sk_buff *skb, struct net_device *ndev,
638 struct bufdesc *bdp, int index)
639 {
640 struct fec_enet_private *fep = netdev_priv(ndev);
641 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
642 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
643 unsigned short queue = skb_get_queue_mapping(skb);
644 void *bufaddr;
645 unsigned long dmabuf;
646 unsigned short status;
647 unsigned int estatus = 0;
648
649 status = bdp->cbd_sc;
650 status &= ~BD_ENET_TX_STATS;
651 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
652
653 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
654 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
655 if (((unsigned long)bufaddr) & fep->tx_align ||
656 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
657 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
658 bufaddr = txq->tx_bounce[index];
659
660 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
661 swap_buffer(bufaddr, hdr_len);
662
663 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
664 hdr_len, DMA_TO_DEVICE);
665 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
666 dev_kfree_skb_any(skb);
667 if (net_ratelimit())
668 netdev_err(ndev, "Tx DMA memory map failed\n");
669 return NETDEV_TX_BUSY;
670 }
671 }
672
673 bdp->cbd_bufaddr = dmabuf;
674 bdp->cbd_datlen = hdr_len;
675
676 if (fep->bufdesc_ex) {
677 if (fep->quirks & FEC_QUIRK_HAS_AVB)
678 estatus |= FEC_TX_BD_FTYPE(queue);
679 if (skb->ip_summed == CHECKSUM_PARTIAL)
680 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
681 ebdp->cbd_bdu = 0;
682 ebdp->cbd_esc = estatus;
683 }
684
685 bdp->cbd_sc = status;
686
687 return 0;
688 }
689
690 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
691 struct sk_buff *skb,
692 struct net_device *ndev)
693 {
694 struct fec_enet_private *fep = netdev_priv(ndev);
695 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
696 int total_len, data_left;
697 struct bufdesc *bdp = txq->cur_tx;
698 unsigned short queue = skb_get_queue_mapping(skb);
699 struct tso_t tso;
700 unsigned int index = 0;
701 int ret;
702
703 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) {
704 dev_kfree_skb_any(skb);
705 if (net_ratelimit())
706 netdev_err(ndev, "NOT enough BD for TSO!\n");
707 return NETDEV_TX_OK;
708 }
709
710 /* Protocol checksum off-load for TCP and UDP. */
711 if (fec_enet_clear_csum(skb, ndev)) {
712 dev_kfree_skb_any(skb);
713 return NETDEV_TX_OK;
714 }
715
716 /* Initialize the TSO handler, and prepare the first payload */
717 tso_start(skb, &tso);
718
719 total_len = skb->len - hdr_len;
720 while (total_len > 0) {
721 char *hdr;
722
723 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
724 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
725 total_len -= data_left;
726
727 /* prepare packet headers: MAC + IP + TCP */
728 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
729 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
730 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
731 if (ret)
732 goto err_release;
733
734 while (data_left > 0) {
735 int size;
736
737 size = min_t(int, tso.size, data_left);
738 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
739 index = fec_enet_get_bd_index(txq->tx_bd_base,
740 bdp, fep);
741 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
742 bdp, index,
743 tso.data, size,
744 size == data_left,
745 total_len == 0);
746 if (ret)
747 goto err_release;
748
749 data_left -= size;
750 tso_build_data(skb, &tso, size);
751 }
752
753 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
754 }
755
756 /* Save skb pointer */
757 txq->tx_skbuff[index] = skb;
758
759 skb_tx_timestamp(skb);
760 txq->cur_tx = bdp;
761
762 /* Trigger transmission start */
763 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
764 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
765 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
766 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
767 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)))
768 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
769
770 return 0;
771
772 err_release:
773 /* TODO: Release all used data descriptors for TSO */
774 return ret;
775 }
776
777 static netdev_tx_t
778 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
779 {
780 struct fec_enet_private *fep = netdev_priv(ndev);
781 int entries_free;
782 unsigned short queue;
783 struct fec_enet_priv_tx_q *txq;
784 struct netdev_queue *nq;
785 int ret;
786
787 queue = skb_get_queue_mapping(skb);
788 txq = fep->tx_queue[queue];
789 nq = netdev_get_tx_queue(ndev, queue);
790
791 if (skb_is_gso(skb))
792 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
793 else
794 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
795 if (ret)
796 return ret;
797
798 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
799 if (entries_free <= txq->tx_stop_threshold)
800 netif_tx_stop_queue(nq);
801
802 return NETDEV_TX_OK;
803 }
804
805 /* Init RX & TX buffer descriptors
806 */
807 static void fec_enet_bd_init(struct net_device *dev)
808 {
809 struct fec_enet_private *fep = netdev_priv(dev);
810 struct fec_enet_priv_tx_q *txq;
811 struct fec_enet_priv_rx_q *rxq;
812 struct bufdesc *bdp;
813 unsigned int i;
814 unsigned int q;
815
816 for (q = 0; q < fep->num_rx_queues; q++) {
817 /* Initialize the receive buffer descriptors. */
818 rxq = fep->rx_queue[q];
819 bdp = rxq->rx_bd_base;
820
821 for (i = 0; i < rxq->rx_ring_size; i++) {
822
823 /* Initialize the BD for every fragment in the page. */
824 if (bdp->cbd_bufaddr)
825 bdp->cbd_sc = BD_ENET_RX_EMPTY;
826 else
827 bdp->cbd_sc = 0;
828 bdp = fec_enet_get_nextdesc(bdp, fep, q);
829 }
830
831 /* Set the last buffer to wrap */
832 bdp = fec_enet_get_prevdesc(bdp, fep, q);
833 bdp->cbd_sc |= BD_SC_WRAP;
834
835 rxq->cur_rx = rxq->rx_bd_base;
836 }
837
838 for (q = 0; q < fep->num_tx_queues; q++) {
839 /* ...and the same for transmit */
840 txq = fep->tx_queue[q];
841 bdp = txq->tx_bd_base;
842 txq->cur_tx = bdp;
843
844 for (i = 0; i < txq->tx_ring_size; i++) {
845 /* Initialize the BD for every fragment in the page. */
846 bdp->cbd_sc = 0;
847 if (txq->tx_skbuff[i]) {
848 dev_kfree_skb_any(txq->tx_skbuff[i]);
849 txq->tx_skbuff[i] = NULL;
850 }
851 bdp->cbd_bufaddr = 0;
852 bdp = fec_enet_get_nextdesc(bdp, fep, q);
853 }
854
855 /* Set the last buffer to wrap */
856 bdp = fec_enet_get_prevdesc(bdp, fep, q);
857 bdp->cbd_sc |= BD_SC_WRAP;
858 txq->dirty_tx = bdp;
859 }
860 }
861
862 static void fec_enet_active_rxring(struct net_device *ndev)
863 {
864 struct fec_enet_private *fep = netdev_priv(ndev);
865 int i;
866
867 for (i = 0; i < fep->num_rx_queues; i++)
868 writel(0, fep->hwp + FEC_R_DES_ACTIVE(i));
869 }
870
871 static void fec_enet_enable_ring(struct net_device *ndev)
872 {
873 struct fec_enet_private *fep = netdev_priv(ndev);
874 struct fec_enet_priv_tx_q *txq;
875 struct fec_enet_priv_rx_q *rxq;
876 int i;
877
878 for (i = 0; i < fep->num_rx_queues; i++) {
879 rxq = fep->rx_queue[i];
880 writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i));
881 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
882
883 /* enable DMA1/2 */
884 if (i)
885 writel(RCMR_MATCHEN | RCMR_CMP(i),
886 fep->hwp + FEC_RCMR(i));
887 }
888
889 for (i = 0; i < fep->num_tx_queues; i++) {
890 txq = fep->tx_queue[i];
891 writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i));
892
893 /* enable DMA1/2 */
894 if (i)
895 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
896 fep->hwp + FEC_DMA_CFG(i));
897 }
898 }
899
900 static void fec_enet_reset_skb(struct net_device *ndev)
901 {
902 struct fec_enet_private *fep = netdev_priv(ndev);
903 struct fec_enet_priv_tx_q *txq;
904 int i, j;
905
906 for (i = 0; i < fep->num_tx_queues; i++) {
907 txq = fep->tx_queue[i];
908
909 for (j = 0; j < txq->tx_ring_size; j++) {
910 if (txq->tx_skbuff[j]) {
911 dev_kfree_skb_any(txq->tx_skbuff[j]);
912 txq->tx_skbuff[j] = NULL;
913 }
914 }
915 }
916 }
917
918 /*
919 * This function is called to start or restart the FEC during a link
920 * change, transmit timeout, or to reconfigure the FEC. The network
921 * packet processing for this device must be stopped before this call.
922 */
923 static void
924 fec_restart(struct net_device *ndev)
925 {
926 struct fec_enet_private *fep = netdev_priv(ndev);
927 u32 val;
928 u32 temp_mac[2];
929 u32 rcntl = OPT_FRAME_SIZE | 0x04;
930 u32 ecntl = 0x2; /* ETHEREN */
931
932 /* Whack a reset. We should wait for this.
933 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
934 * instead of reset MAC itself.
935 */
936 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
937 writel(0, fep->hwp + FEC_ECNTRL);
938 } else {
939 writel(1, fep->hwp + FEC_ECNTRL);
940 udelay(10);
941 }
942
943 /*
944 * enet-mac reset will reset mac address registers too,
945 * so need to reconfigure it.
946 */
947 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
948 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
949 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
950 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
951 }
952
953 /* Clear any outstanding interrupt. */
954 writel(0xffffffff, fep->hwp + FEC_IEVENT);
955
956 fec_enet_bd_init(ndev);
957
958 fec_enet_enable_ring(ndev);
959
960 /* Reset tx SKB buffers. */
961 fec_enet_reset_skb(ndev);
962
963 /* Enable MII mode */
964 if (fep->full_duplex == DUPLEX_FULL) {
965 /* FD enable */
966 writel(0x04, fep->hwp + FEC_X_CNTRL);
967 } else {
968 /* No Rcv on Xmit */
969 rcntl |= 0x02;
970 writel(0x0, fep->hwp + FEC_X_CNTRL);
971 }
972
973 /* Set MII speed */
974 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
975
976 #if !defined(CONFIG_M5272)
977 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
978 /* set RX checksum */
979 val = readl(fep->hwp + FEC_RACC);
980 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
981 val |= FEC_RACC_OPTIONS;
982 else
983 val &= ~FEC_RACC_OPTIONS;
984 writel(val, fep->hwp + FEC_RACC);
985 }
986 #endif
987
988 /*
989 * The phy interface and speed need to get configured
990 * differently on enet-mac.
991 */
992 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
993 /* Enable flow control and length check */
994 rcntl |= 0x40000000 | 0x00000020;
995
996 /* RGMII, RMII or MII */
997 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
998 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
999 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
1000 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
1001 rcntl |= (1 << 6);
1002 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1003 rcntl |= (1 << 8);
1004 else
1005 rcntl &= ~(1 << 8);
1006
1007 /* 1G, 100M or 10M */
1008 if (fep->phy_dev) {
1009 if (fep->phy_dev->speed == SPEED_1000)
1010 ecntl |= (1 << 5);
1011 else if (fep->phy_dev->speed == SPEED_100)
1012 rcntl &= ~(1 << 9);
1013 else
1014 rcntl |= (1 << 9);
1015 }
1016 } else {
1017 #ifdef FEC_MIIGSK_ENR
1018 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1019 u32 cfgr;
1020 /* disable the gasket and wait */
1021 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1022 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1023 udelay(1);
1024
1025 /*
1026 * configure the gasket:
1027 * RMII, 50 MHz, no loopback, no echo
1028 * MII, 25 MHz, no loopback, no echo
1029 */
1030 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1031 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1032 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
1033 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1034 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1035
1036 /* re-enable the gasket */
1037 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1038 }
1039 #endif
1040 }
1041
1042 #if !defined(CONFIG_M5272)
1043 /* enable pause frame*/
1044 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1045 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1046 fep->phy_dev && fep->phy_dev->pause)) {
1047 rcntl |= FEC_ENET_FCE;
1048
1049 /* set FIFO threshold parameter to reduce overrun */
1050 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1051 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1052 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1053 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1054
1055 /* OPD */
1056 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1057 } else {
1058 rcntl &= ~FEC_ENET_FCE;
1059 }
1060 #endif /* !defined(CONFIG_M5272) */
1061
1062 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1063
1064 /* Setup multicast filter. */
1065 set_multicast_list(ndev);
1066 #ifndef CONFIG_M5272
1067 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1068 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1069 #endif
1070
1071 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1072 /* enable ENET endian swap */
1073 ecntl |= (1 << 8);
1074 /* enable ENET store and forward mode */
1075 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1076 }
1077
1078 if (fep->bufdesc_ex)
1079 ecntl |= (1 << 4);
1080
1081 #ifndef CONFIG_M5272
1082 /* Enable the MIB statistic event counters */
1083 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1084 #endif
1085
1086 /* And last, enable the transmit and receive processing */
1087 writel(ecntl, fep->hwp + FEC_ECNTRL);
1088 fec_enet_active_rxring(ndev);
1089
1090 if (fep->bufdesc_ex)
1091 fec_ptp_start_cyclecounter(ndev);
1092
1093 /* Enable interrupts we wish to service */
1094 if (fep->link)
1095 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1096 else
1097 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1098
1099 /* Init the interrupt coalescing */
1100 fec_enet_itr_coal_init(ndev);
1101
1102 }
1103
1104 static void
1105 fec_stop(struct net_device *ndev)
1106 {
1107 struct fec_enet_private *fep = netdev_priv(ndev);
1108 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1109 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1110 u32 val;
1111
1112 /* We cannot expect a graceful transmit stop without link !!! */
1113 if (fep->link) {
1114 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1115 udelay(10);
1116 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1117 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1118 }
1119
1120 /* Whack a reset. We should wait for this.
1121 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1122 * instead of reset MAC itself.
1123 */
1124 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1125 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1126 writel(0, fep->hwp + FEC_ECNTRL);
1127 } else {
1128 writel(1, fep->hwp + FEC_ECNTRL);
1129 udelay(10);
1130 }
1131 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1132 } else {
1133 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1134 val = readl(fep->hwp + FEC_ECNTRL);
1135 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1136 writel(val, fep->hwp + FEC_ECNTRL);
1137
1138 if (pdata && pdata->sleep_mode_enable)
1139 pdata->sleep_mode_enable(true);
1140 }
1141 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1142
1143 /* We have to keep ENET enabled to have MII interrupt stay working */
1144 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1145 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1146 writel(2, fep->hwp + FEC_ECNTRL);
1147 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1148 }
1149 }
1150
1151
1152 static void
1153 fec_timeout(struct net_device *ndev)
1154 {
1155 struct fec_enet_private *fep = netdev_priv(ndev);
1156
1157 fec_dump(ndev);
1158
1159 ndev->stats.tx_errors++;
1160
1161 schedule_work(&fep->tx_timeout_work);
1162 }
1163
1164 static void fec_enet_timeout_work(struct work_struct *work)
1165 {
1166 struct fec_enet_private *fep =
1167 container_of(work, struct fec_enet_private, tx_timeout_work);
1168 struct net_device *ndev = fep->netdev;
1169
1170 rtnl_lock();
1171 if (netif_device_present(ndev) || netif_running(ndev)) {
1172 napi_disable(&fep->napi);
1173 netif_tx_lock_bh(ndev);
1174 fec_restart(ndev);
1175 netif_wake_queue(ndev);
1176 netif_tx_unlock_bh(ndev);
1177 napi_enable(&fep->napi);
1178 }
1179 rtnl_unlock();
1180 }
1181
1182 static void
1183 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1184 struct skb_shared_hwtstamps *hwtstamps)
1185 {
1186 unsigned long flags;
1187 u64 ns;
1188
1189 spin_lock_irqsave(&fep->tmreg_lock, flags);
1190 ns = timecounter_cyc2time(&fep->tc, ts);
1191 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1192
1193 memset(hwtstamps, 0, sizeof(*hwtstamps));
1194 hwtstamps->hwtstamp = ns_to_ktime(ns);
1195 }
1196
1197 static void
1198 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1199 {
1200 struct fec_enet_private *fep;
1201 struct bufdesc *bdp;
1202 unsigned short status;
1203 struct sk_buff *skb;
1204 struct fec_enet_priv_tx_q *txq;
1205 struct netdev_queue *nq;
1206 int index = 0;
1207 int entries_free;
1208
1209 fep = netdev_priv(ndev);
1210
1211 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1212
1213 txq = fep->tx_queue[queue_id];
1214 /* get next bdp of dirty_tx */
1215 nq = netdev_get_tx_queue(ndev, queue_id);
1216 bdp = txq->dirty_tx;
1217
1218 /* get next bdp of dirty_tx */
1219 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1220
1221 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
1222
1223 /* current queue is empty */
1224 if (bdp == txq->cur_tx)
1225 break;
1226
1227 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
1228
1229 skb = txq->tx_skbuff[index];
1230 txq->tx_skbuff[index] = NULL;
1231 if (!IS_TSO_HEADER(txq, bdp->cbd_bufaddr))
1232 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1233 bdp->cbd_datlen, DMA_TO_DEVICE);
1234 bdp->cbd_bufaddr = 0;
1235 if (!skb) {
1236 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1237 continue;
1238 }
1239
1240 /* Check for errors. */
1241 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1242 BD_ENET_TX_RL | BD_ENET_TX_UN |
1243 BD_ENET_TX_CSL)) {
1244 ndev->stats.tx_errors++;
1245 if (status & BD_ENET_TX_HB) /* No heartbeat */
1246 ndev->stats.tx_heartbeat_errors++;
1247 if (status & BD_ENET_TX_LC) /* Late collision */
1248 ndev->stats.tx_window_errors++;
1249 if (status & BD_ENET_TX_RL) /* Retrans limit */
1250 ndev->stats.tx_aborted_errors++;
1251 if (status & BD_ENET_TX_UN) /* Underrun */
1252 ndev->stats.tx_fifo_errors++;
1253 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1254 ndev->stats.tx_carrier_errors++;
1255 } else {
1256 ndev->stats.tx_packets++;
1257 ndev->stats.tx_bytes += skb->len;
1258 }
1259
1260 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1261 fep->bufdesc_ex) {
1262 struct skb_shared_hwtstamps shhwtstamps;
1263 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1264
1265 fec_enet_hwtstamp(fep, ebdp->ts, &shhwtstamps);
1266 skb_tstamp_tx(skb, &shhwtstamps);
1267 }
1268
1269 /* Deferred means some collisions occurred during transmit,
1270 * but we eventually sent the packet OK.
1271 */
1272 if (status & BD_ENET_TX_DEF)
1273 ndev->stats.collisions++;
1274
1275 /* Free the sk buffer associated with this last transmit */
1276 dev_kfree_skb_any(skb);
1277
1278 txq->dirty_tx = bdp;
1279
1280 /* Update pointer to next buffer descriptor to be transmitted */
1281 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1282
1283 /* Since we have freed up a buffer, the ring is no longer full
1284 */
1285 if (netif_queue_stopped(ndev)) {
1286 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
1287 if (entries_free >= txq->tx_wake_threshold)
1288 netif_tx_wake_queue(nq);
1289 }
1290 }
1291
1292 /* ERR006538: Keep the transmitter going */
1293 if (bdp != txq->cur_tx &&
1294 readl(fep->hwp + FEC_X_DES_ACTIVE(queue_id)) == 0)
1295 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue_id));
1296 }
1297
1298 static void
1299 fec_enet_tx(struct net_device *ndev)
1300 {
1301 struct fec_enet_private *fep = netdev_priv(ndev);
1302 u16 queue_id;
1303 /* First process class A queue, then Class B and Best Effort queue */
1304 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1305 clear_bit(queue_id, &fep->work_tx);
1306 fec_enet_tx_queue(ndev, queue_id);
1307 }
1308 return;
1309 }
1310
1311 static int
1312 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1313 {
1314 struct fec_enet_private *fep = netdev_priv(ndev);
1315 int off;
1316
1317 off = ((unsigned long)skb->data) & fep->rx_align;
1318 if (off)
1319 skb_reserve(skb, fep->rx_align + 1 - off);
1320
1321 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1322 FEC_ENET_RX_FRSIZE - fep->rx_align,
1323 DMA_FROM_DEVICE);
1324 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
1325 if (net_ratelimit())
1326 netdev_err(ndev, "Rx DMA memory map failed\n");
1327 return -ENOMEM;
1328 }
1329
1330 return 0;
1331 }
1332
1333 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1334 struct bufdesc *bdp, u32 length, bool swap)
1335 {
1336 struct fec_enet_private *fep = netdev_priv(ndev);
1337 struct sk_buff *new_skb;
1338
1339 if (length > fep->rx_copybreak)
1340 return false;
1341
1342 new_skb = netdev_alloc_skb(ndev, length);
1343 if (!new_skb)
1344 return false;
1345
1346 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
1347 FEC_ENET_RX_FRSIZE - fep->rx_align,
1348 DMA_FROM_DEVICE);
1349 if (!swap)
1350 memcpy(new_skb->data, (*skb)->data, length);
1351 else
1352 swap_buffer2(new_skb->data, (*skb)->data, length);
1353 *skb = new_skb;
1354
1355 return true;
1356 }
1357
1358 /* During a receive, the cur_rx points to the current incoming buffer.
1359 * When we update through the ring, if the next incoming buffer has
1360 * not been given to the system, we just set the empty indicator,
1361 * effectively tossing the packet.
1362 */
1363 static int
1364 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1365 {
1366 struct fec_enet_private *fep = netdev_priv(ndev);
1367 struct fec_enet_priv_rx_q *rxq;
1368 struct bufdesc *bdp;
1369 unsigned short status;
1370 struct sk_buff *skb_new = NULL;
1371 struct sk_buff *skb;
1372 ushort pkt_len;
1373 __u8 *data;
1374 int pkt_received = 0;
1375 struct bufdesc_ex *ebdp = NULL;
1376 bool vlan_packet_rcvd = false;
1377 u16 vlan_tag;
1378 int index = 0;
1379 bool is_copybreak;
1380 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1381
1382 #ifdef CONFIG_M532x
1383 flush_cache_all();
1384 #endif
1385 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1386 rxq = fep->rx_queue[queue_id];
1387
1388 /* First, grab all of the stats for the incoming packet.
1389 * These get messed up if we get called due to a busy condition.
1390 */
1391 bdp = rxq->cur_rx;
1392
1393 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
1394
1395 if (pkt_received >= budget)
1396 break;
1397 pkt_received++;
1398
1399 /* Since we have allocated space to hold a complete frame,
1400 * the last indicator should be set.
1401 */
1402 if ((status & BD_ENET_RX_LAST) == 0)
1403 netdev_err(ndev, "rcv is not +last\n");
1404
1405
1406 /* Check for errors. */
1407 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1408 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
1409 ndev->stats.rx_errors++;
1410 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1411 /* Frame too long or too short. */
1412 ndev->stats.rx_length_errors++;
1413 }
1414 if (status & BD_ENET_RX_NO) /* Frame alignment */
1415 ndev->stats.rx_frame_errors++;
1416 if (status & BD_ENET_RX_CR) /* CRC Error */
1417 ndev->stats.rx_crc_errors++;
1418 if (status & BD_ENET_RX_OV) /* FIFO overrun */
1419 ndev->stats.rx_fifo_errors++;
1420 }
1421
1422 /* Report late collisions as a frame error.
1423 * On this error, the BD is closed, but we don't know what we
1424 * have in the buffer. So, just drop this frame on the floor.
1425 */
1426 if (status & BD_ENET_RX_CL) {
1427 ndev->stats.rx_errors++;
1428 ndev->stats.rx_frame_errors++;
1429 goto rx_processing_done;
1430 }
1431
1432 /* Process the incoming frame. */
1433 ndev->stats.rx_packets++;
1434 pkt_len = bdp->cbd_datlen;
1435 ndev->stats.rx_bytes += pkt_len;
1436
1437 index = fec_enet_get_bd_index(rxq->rx_bd_base, bdp, fep);
1438 skb = rxq->rx_skbuff[index];
1439
1440 /* The packet length includes FCS, but we don't want to
1441 * include that when passing upstream as it messes up
1442 * bridging applications.
1443 */
1444 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1445 need_swap);
1446 if (!is_copybreak) {
1447 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1448 if (unlikely(!skb_new)) {
1449 ndev->stats.rx_dropped++;
1450 goto rx_processing_done;
1451 }
1452 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1453 FEC_ENET_RX_FRSIZE - fep->rx_align,
1454 DMA_FROM_DEVICE);
1455 }
1456
1457 prefetch(skb->data - NET_IP_ALIGN);
1458 skb_put(skb, pkt_len - 4);
1459 data = skb->data;
1460 if (!is_copybreak && need_swap)
1461 swap_buffer(data, pkt_len);
1462
1463 /* Extract the enhanced buffer descriptor */
1464 ebdp = NULL;
1465 if (fep->bufdesc_ex)
1466 ebdp = (struct bufdesc_ex *)bdp;
1467
1468 /* If this is a VLAN packet remove the VLAN Tag */
1469 vlan_packet_rcvd = false;
1470 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1471 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
1472 /* Push and remove the vlan tag */
1473 struct vlan_hdr *vlan_header =
1474 (struct vlan_hdr *) (data + ETH_HLEN);
1475 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1476
1477 vlan_packet_rcvd = true;
1478
1479 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1480 skb_pull(skb, VLAN_HLEN);
1481 }
1482
1483 skb->protocol = eth_type_trans(skb, ndev);
1484
1485 /* Get receive timestamp from the skb */
1486 if (fep->hwts_rx_en && fep->bufdesc_ex)
1487 fec_enet_hwtstamp(fep, ebdp->ts,
1488 skb_hwtstamps(skb));
1489
1490 if (fep->bufdesc_ex &&
1491 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1492 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1493 /* don't check it */
1494 skb->ip_summed = CHECKSUM_UNNECESSARY;
1495 } else {
1496 skb_checksum_none_assert(skb);
1497 }
1498 }
1499
1500 /* Handle received VLAN packets */
1501 if (vlan_packet_rcvd)
1502 __vlan_hwaccel_put_tag(skb,
1503 htons(ETH_P_8021Q),
1504 vlan_tag);
1505
1506 napi_gro_receive(&fep->napi, skb);
1507
1508 if (is_copybreak) {
1509 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1510 FEC_ENET_RX_FRSIZE - fep->rx_align,
1511 DMA_FROM_DEVICE);
1512 } else {
1513 rxq->rx_skbuff[index] = skb_new;
1514 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1515 }
1516
1517 rx_processing_done:
1518 /* Clear the status flags for this buffer */
1519 status &= ~BD_ENET_RX_STATS;
1520
1521 /* Mark the buffer empty */
1522 status |= BD_ENET_RX_EMPTY;
1523 bdp->cbd_sc = status;
1524
1525 if (fep->bufdesc_ex) {
1526 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1527
1528 ebdp->cbd_esc = BD_ENET_RX_INT;
1529 ebdp->cbd_prot = 0;
1530 ebdp->cbd_bdu = 0;
1531 }
1532
1533 /* Update BD pointer to next entry */
1534 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1535
1536 /* Doing this here will keep the FEC running while we process
1537 * incoming frames. On a heavily loaded network, we should be
1538 * able to keep up at the expense of system resources.
1539 */
1540 writel(0, fep->hwp + FEC_R_DES_ACTIVE(queue_id));
1541 }
1542 rxq->cur_rx = bdp;
1543 return pkt_received;
1544 }
1545
1546 static int
1547 fec_enet_rx(struct net_device *ndev, int budget)
1548 {
1549 int pkt_received = 0;
1550 u16 queue_id;
1551 struct fec_enet_private *fep = netdev_priv(ndev);
1552
1553 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1554 clear_bit(queue_id, &fep->work_rx);
1555 pkt_received += fec_enet_rx_queue(ndev,
1556 budget - pkt_received, queue_id);
1557 }
1558 return pkt_received;
1559 }
1560
1561 static bool
1562 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1563 {
1564 if (int_events == 0)
1565 return false;
1566
1567 if (int_events & FEC_ENET_RXF)
1568 fep->work_rx |= (1 << 2);
1569 if (int_events & FEC_ENET_RXF_1)
1570 fep->work_rx |= (1 << 0);
1571 if (int_events & FEC_ENET_RXF_2)
1572 fep->work_rx |= (1 << 1);
1573
1574 if (int_events & FEC_ENET_TXF)
1575 fep->work_tx |= (1 << 2);
1576 if (int_events & FEC_ENET_TXF_1)
1577 fep->work_tx |= (1 << 0);
1578 if (int_events & FEC_ENET_TXF_2)
1579 fep->work_tx |= (1 << 1);
1580
1581 return true;
1582 }
1583
1584 static irqreturn_t
1585 fec_enet_interrupt(int irq, void *dev_id)
1586 {
1587 struct net_device *ndev = dev_id;
1588 struct fec_enet_private *fep = netdev_priv(ndev);
1589 uint int_events;
1590 irqreturn_t ret = IRQ_NONE;
1591
1592 int_events = readl(fep->hwp + FEC_IEVENT);
1593 writel(int_events, fep->hwp + FEC_IEVENT);
1594 fec_enet_collect_events(fep, int_events);
1595
1596 if ((fep->work_tx || fep->work_rx) && fep->link) {
1597 ret = IRQ_HANDLED;
1598
1599 if (napi_schedule_prep(&fep->napi)) {
1600 /* Disable the NAPI interrupts */
1601 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1602 __napi_schedule(&fep->napi);
1603 }
1604 }
1605
1606 if (int_events & FEC_ENET_MII) {
1607 ret = IRQ_HANDLED;
1608 complete(&fep->mdio_done);
1609 }
1610
1611 if (fep->ptp_clock)
1612 fec_ptp_check_pps_event(fep);
1613
1614 return ret;
1615 }
1616
1617 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1618 {
1619 struct net_device *ndev = napi->dev;
1620 struct fec_enet_private *fep = netdev_priv(ndev);
1621 int pkts;
1622
1623 pkts = fec_enet_rx(ndev, budget);
1624
1625 fec_enet_tx(ndev);
1626
1627 if (pkts < budget) {
1628 napi_complete(napi);
1629 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1630 }
1631 return pkts;
1632 }
1633
1634 /* ------------------------------------------------------------------------- */
1635 static void fec_get_mac(struct net_device *ndev)
1636 {
1637 struct fec_enet_private *fep = netdev_priv(ndev);
1638 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1639 unsigned char *iap, tmpaddr[ETH_ALEN];
1640
1641 /*
1642 * try to get mac address in following order:
1643 *
1644 * 1) module parameter via kernel command line in form
1645 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1646 */
1647 iap = macaddr;
1648
1649 /*
1650 * 2) from device tree data
1651 */
1652 if (!is_valid_ether_addr(iap)) {
1653 struct device_node *np = fep->pdev->dev.of_node;
1654 if (np) {
1655 const char *mac = of_get_mac_address(np);
1656 if (mac)
1657 iap = (unsigned char *) mac;
1658 }
1659 }
1660
1661 /*
1662 * 3) from flash or fuse (via platform data)
1663 */
1664 if (!is_valid_ether_addr(iap)) {
1665 #ifdef CONFIG_M5272
1666 if (FEC_FLASHMAC)
1667 iap = (unsigned char *)FEC_FLASHMAC;
1668 #else
1669 if (pdata)
1670 iap = (unsigned char *)&pdata->mac;
1671 #endif
1672 }
1673
1674 /*
1675 * 4) FEC mac registers set by bootloader
1676 */
1677 if (!is_valid_ether_addr(iap)) {
1678 *((__be32 *) &tmpaddr[0]) =
1679 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1680 *((__be16 *) &tmpaddr[4]) =
1681 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1682 iap = &tmpaddr[0];
1683 }
1684
1685 /*
1686 * 5) random mac address
1687 */
1688 if (!is_valid_ether_addr(iap)) {
1689 /* Report it and use a random ethernet address instead */
1690 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1691 eth_hw_addr_random(ndev);
1692 netdev_info(ndev, "Using random MAC address: %pM\n",
1693 ndev->dev_addr);
1694 return;
1695 }
1696
1697 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1698
1699 /* Adjust MAC if using macaddr */
1700 if (iap == macaddr)
1701 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1702 }
1703
1704 /* ------------------------------------------------------------------------- */
1705
1706 /*
1707 * Phy section
1708 */
1709 static void fec_enet_adjust_link(struct net_device *ndev)
1710 {
1711 struct fec_enet_private *fep = netdev_priv(ndev);
1712 struct phy_device *phy_dev = fep->phy_dev;
1713 int status_change = 0;
1714
1715 /* Prevent a state halted on mii error */
1716 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1717 phy_dev->state = PHY_RESUMING;
1718 return;
1719 }
1720
1721 /*
1722 * If the netdev is down, or is going down, we're not interested
1723 * in link state events, so just mark our idea of the link as down
1724 * and ignore the event.
1725 */
1726 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1727 fep->link = 0;
1728 } else if (phy_dev->link) {
1729 if (!fep->link) {
1730 fep->link = phy_dev->link;
1731 status_change = 1;
1732 }
1733
1734 if (fep->full_duplex != phy_dev->duplex) {
1735 fep->full_duplex = phy_dev->duplex;
1736 status_change = 1;
1737 }
1738
1739 if (phy_dev->speed != fep->speed) {
1740 fep->speed = phy_dev->speed;
1741 status_change = 1;
1742 }
1743
1744 /* if any of the above changed restart the FEC */
1745 if (status_change) {
1746 napi_disable(&fep->napi);
1747 netif_tx_lock_bh(ndev);
1748 fec_restart(ndev);
1749 netif_wake_queue(ndev);
1750 netif_tx_unlock_bh(ndev);
1751 napi_enable(&fep->napi);
1752 }
1753 } else {
1754 if (fep->link) {
1755 napi_disable(&fep->napi);
1756 netif_tx_lock_bh(ndev);
1757 fec_stop(ndev);
1758 netif_tx_unlock_bh(ndev);
1759 napi_enable(&fep->napi);
1760 fep->link = phy_dev->link;
1761 status_change = 1;
1762 }
1763 }
1764
1765 if (status_change)
1766 phy_print_status(phy_dev);
1767 }
1768
1769 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1770 {
1771 struct fec_enet_private *fep = bus->priv;
1772 struct device *dev = &fep->pdev->dev;
1773 unsigned long time_left;
1774 int ret = 0;
1775
1776 ret = pm_runtime_get_sync(dev);
1777 if (IS_ERR_VALUE(ret))
1778 return ret;
1779
1780 fep->mii_timeout = 0;
1781 init_completion(&fep->mdio_done);
1782
1783 /* start a read op */
1784 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1785 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1786 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1787
1788 /* wait for end of transfer */
1789 time_left = wait_for_completion_timeout(&fep->mdio_done,
1790 usecs_to_jiffies(FEC_MII_TIMEOUT));
1791 if (time_left == 0) {
1792 fep->mii_timeout = 1;
1793 netdev_err(fep->netdev, "MDIO read timeout\n");
1794 ret = -ETIMEDOUT;
1795 goto out;
1796 }
1797
1798 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1799
1800 out:
1801 pm_runtime_mark_last_busy(dev);
1802 pm_runtime_put_autosuspend(dev);
1803
1804 return ret;
1805 }
1806
1807 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1808 u16 value)
1809 {
1810 struct fec_enet_private *fep = bus->priv;
1811 struct device *dev = &fep->pdev->dev;
1812 unsigned long time_left;
1813 int ret = 0;
1814
1815 ret = pm_runtime_get_sync(dev);
1816 if (IS_ERR_VALUE(ret))
1817 return ret;
1818
1819 fep->mii_timeout = 0;
1820 init_completion(&fep->mdio_done);
1821
1822 /* start a write op */
1823 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1824 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1825 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1826 fep->hwp + FEC_MII_DATA);
1827
1828 /* wait for end of transfer */
1829 time_left = wait_for_completion_timeout(&fep->mdio_done,
1830 usecs_to_jiffies(FEC_MII_TIMEOUT));
1831 if (time_left == 0) {
1832 fep->mii_timeout = 1;
1833 netdev_err(fep->netdev, "MDIO write timeout\n");
1834 ret = -ETIMEDOUT;
1835 }
1836
1837 pm_runtime_mark_last_busy(dev);
1838 pm_runtime_put_autosuspend(dev);
1839
1840 return ret;
1841 }
1842
1843 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1844 {
1845 struct fec_enet_private *fep = netdev_priv(ndev);
1846 int ret;
1847
1848 if (enable) {
1849 ret = clk_prepare_enable(fep->clk_ahb);
1850 if (ret)
1851 return ret;
1852 if (fep->clk_enet_out) {
1853 ret = clk_prepare_enable(fep->clk_enet_out);
1854 if (ret)
1855 goto failed_clk_enet_out;
1856 }
1857 if (fep->clk_ptp) {
1858 mutex_lock(&fep->ptp_clk_mutex);
1859 ret = clk_prepare_enable(fep->clk_ptp);
1860 if (ret) {
1861 mutex_unlock(&fep->ptp_clk_mutex);
1862 goto failed_clk_ptp;
1863 } else {
1864 fep->ptp_clk_on = true;
1865 }
1866 mutex_unlock(&fep->ptp_clk_mutex);
1867 }
1868 if (fep->clk_ref) {
1869 ret = clk_prepare_enable(fep->clk_ref);
1870 if (ret)
1871 goto failed_clk_ref;
1872 }
1873 } else {
1874 clk_disable_unprepare(fep->clk_ahb);
1875 if (fep->clk_enet_out)
1876 clk_disable_unprepare(fep->clk_enet_out);
1877 if (fep->clk_ptp) {
1878 mutex_lock(&fep->ptp_clk_mutex);
1879 clk_disable_unprepare(fep->clk_ptp);
1880 fep->ptp_clk_on = false;
1881 mutex_unlock(&fep->ptp_clk_mutex);
1882 }
1883 if (fep->clk_ref)
1884 clk_disable_unprepare(fep->clk_ref);
1885 }
1886
1887 return 0;
1888
1889 failed_clk_ref:
1890 if (fep->clk_ref)
1891 clk_disable_unprepare(fep->clk_ref);
1892 failed_clk_ptp:
1893 if (fep->clk_enet_out)
1894 clk_disable_unprepare(fep->clk_enet_out);
1895 failed_clk_enet_out:
1896 clk_disable_unprepare(fep->clk_ahb);
1897
1898 return ret;
1899 }
1900
1901 static int fec_enet_mii_probe(struct net_device *ndev)
1902 {
1903 struct fec_enet_private *fep = netdev_priv(ndev);
1904 struct phy_device *phy_dev = NULL;
1905 char mdio_bus_id[MII_BUS_ID_SIZE];
1906 char phy_name[MII_BUS_ID_SIZE + 3];
1907 int phy_id;
1908 int dev_id = fep->dev_id;
1909
1910 fep->phy_dev = NULL;
1911
1912 if (fep->phy_node) {
1913 phy_dev = of_phy_connect(ndev, fep->phy_node,
1914 &fec_enet_adjust_link, 0,
1915 fep->phy_interface);
1916 if (!phy_dev)
1917 return -ENODEV;
1918 } else {
1919 /* check for attached phy */
1920 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1921 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1922 continue;
1923 if (fep->mii_bus->phy_map[phy_id] == NULL)
1924 continue;
1925 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1926 continue;
1927 if (dev_id--)
1928 continue;
1929 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1930 break;
1931 }
1932
1933 if (phy_id >= PHY_MAX_ADDR) {
1934 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1935 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1936 phy_id = 0;
1937 }
1938
1939 snprintf(phy_name, sizeof(phy_name),
1940 PHY_ID_FMT, mdio_bus_id, phy_id);
1941 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1942 fep->phy_interface);
1943 }
1944
1945 if (IS_ERR(phy_dev)) {
1946 netdev_err(ndev, "could not attach to PHY\n");
1947 return PTR_ERR(phy_dev);
1948 }
1949
1950 /* mask with MAC supported features */
1951 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
1952 phy_dev->supported &= PHY_GBIT_FEATURES;
1953 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1954 #if !defined(CONFIG_M5272)
1955 phy_dev->supported |= SUPPORTED_Pause;
1956 #endif
1957 }
1958 else
1959 phy_dev->supported &= PHY_BASIC_FEATURES;
1960
1961 phy_dev->advertising = phy_dev->supported;
1962
1963 fep->phy_dev = phy_dev;
1964 fep->link = 0;
1965 fep->full_duplex = 0;
1966
1967 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1968 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1969 fep->phy_dev->irq);
1970
1971 return 0;
1972 }
1973
1974 static int fec_enet_mii_init(struct platform_device *pdev)
1975 {
1976 static struct mii_bus *fec0_mii_bus;
1977 struct net_device *ndev = platform_get_drvdata(pdev);
1978 struct fec_enet_private *fep = netdev_priv(ndev);
1979 struct device_node *node;
1980 int err = -ENXIO, i;
1981 u32 mii_speed, holdtime;
1982
1983 /*
1984 * The i.MX28 dual fec interfaces are not equal.
1985 * Here are the differences:
1986 *
1987 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1988 * - fec0 acts as the 1588 time master while fec1 is slave
1989 * - external phys can only be configured by fec0
1990 *
1991 * That is to say fec1 can not work independently. It only works
1992 * when fec0 is working. The reason behind this design is that the
1993 * second interface is added primarily for Switch mode.
1994 *
1995 * Because of the last point above, both phys are attached on fec0
1996 * mdio interface in board design, and need to be configured by
1997 * fec0 mii_bus.
1998 */
1999 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
2000 /* fec1 uses fec0 mii_bus */
2001 if (mii_cnt && fec0_mii_bus) {
2002 fep->mii_bus = fec0_mii_bus;
2003 mii_cnt++;
2004 return 0;
2005 }
2006 return -ENOENT;
2007 }
2008
2009 fep->mii_timeout = 0;
2010
2011 /*
2012 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
2013 *
2014 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2015 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
2016 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2017 * document.
2018 */
2019 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
2020 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2021 mii_speed--;
2022 if (mii_speed > 63) {
2023 dev_err(&pdev->dev,
2024 "fec clock (%lu) to fast to get right mii speed\n",
2025 clk_get_rate(fep->clk_ipg));
2026 err = -EINVAL;
2027 goto err_out;
2028 }
2029
2030 /*
2031 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2032 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2033 * versions are RAZ there, so just ignore the difference and write the
2034 * register always.
2035 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2036 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2037 * output.
2038 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2039 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2040 * holdtime cannot result in a value greater than 3.
2041 */
2042 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2043
2044 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2045
2046 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2047
2048 fep->mii_bus = mdiobus_alloc();
2049 if (fep->mii_bus == NULL) {
2050 err = -ENOMEM;
2051 goto err_out;
2052 }
2053
2054 fep->mii_bus->name = "fec_enet_mii_bus";
2055 fep->mii_bus->read = fec_enet_mdio_read;
2056 fep->mii_bus->write = fec_enet_mdio_write;
2057 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2058 pdev->name, fep->dev_id + 1);
2059 fep->mii_bus->priv = fep;
2060 fep->mii_bus->parent = &pdev->dev;
2061
2062 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
2063 if (!fep->mii_bus->irq) {
2064 err = -ENOMEM;
2065 goto err_out_free_mdiobus;
2066 }
2067
2068 for (i = 0; i < PHY_MAX_ADDR; i++)
2069 fep->mii_bus->irq[i] = PHY_POLL;
2070
2071 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2072 if (node) {
2073 err = of_mdiobus_register(fep->mii_bus, node);
2074 of_node_put(node);
2075 } else {
2076 err = mdiobus_register(fep->mii_bus);
2077 }
2078
2079 if (err)
2080 goto err_out_free_mdio_irq;
2081
2082 mii_cnt++;
2083
2084 /* save fec0 mii_bus */
2085 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2086 fec0_mii_bus = fep->mii_bus;
2087
2088 return 0;
2089
2090 err_out_free_mdio_irq:
2091 kfree(fep->mii_bus->irq);
2092 err_out_free_mdiobus:
2093 mdiobus_free(fep->mii_bus);
2094 err_out:
2095 return err;
2096 }
2097
2098 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2099 {
2100 if (--mii_cnt == 0) {
2101 mdiobus_unregister(fep->mii_bus);
2102 kfree(fep->mii_bus->irq);
2103 mdiobus_free(fep->mii_bus);
2104 }
2105 }
2106
2107 static int fec_enet_get_settings(struct net_device *ndev,
2108 struct ethtool_cmd *cmd)
2109 {
2110 struct fec_enet_private *fep = netdev_priv(ndev);
2111 struct phy_device *phydev = fep->phy_dev;
2112
2113 if (!phydev)
2114 return -ENODEV;
2115
2116 return phy_ethtool_gset(phydev, cmd);
2117 }
2118
2119 static int fec_enet_set_settings(struct net_device *ndev,
2120 struct ethtool_cmd *cmd)
2121 {
2122 struct fec_enet_private *fep = netdev_priv(ndev);
2123 struct phy_device *phydev = fep->phy_dev;
2124
2125 if (!phydev)
2126 return -ENODEV;
2127
2128 return phy_ethtool_sset(phydev, cmd);
2129 }
2130
2131 static void fec_enet_get_drvinfo(struct net_device *ndev,
2132 struct ethtool_drvinfo *info)
2133 {
2134 struct fec_enet_private *fep = netdev_priv(ndev);
2135
2136 strlcpy(info->driver, fep->pdev->dev.driver->name,
2137 sizeof(info->driver));
2138 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2139 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2140 }
2141
2142 static int fec_enet_get_regs_len(struct net_device *ndev)
2143 {
2144 struct fec_enet_private *fep = netdev_priv(ndev);
2145 struct resource *r;
2146 int s = 0;
2147
2148 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2149 if (r)
2150 s = resource_size(r);
2151
2152 return s;
2153 }
2154
2155 /* List of registers that can be safety be read to dump them with ethtool */
2156 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2157 defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
2158 defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
2159 static u32 fec_enet_register_offset[] = {
2160 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2161 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2162 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2163 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2164 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2165 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2166 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2167 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2168 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2169 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2170 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2171 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2172 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2173 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2174 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2175 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2176 RMON_T_P_GTE2048, RMON_T_OCTETS,
2177 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2178 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2179 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2180 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2181 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2182 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2183 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2184 RMON_R_P_GTE2048, RMON_R_OCTETS,
2185 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2186 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2187 };
2188 #else
2189 static u32 fec_enet_register_offset[] = {
2190 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2191 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2192 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2193 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2194 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2195 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2196 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2197 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2198 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2199 };
2200 #endif
2201
2202 static void fec_enet_get_regs(struct net_device *ndev,
2203 struct ethtool_regs *regs, void *regbuf)
2204 {
2205 struct fec_enet_private *fep = netdev_priv(ndev);
2206 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2207 u32 *buf = (u32 *)regbuf;
2208 u32 i, off;
2209
2210 memset(buf, 0, regs->len);
2211
2212 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
2213 off = fec_enet_register_offset[i] / 4;
2214 buf[off] = readl(&theregs[off]);
2215 }
2216 }
2217
2218 static int fec_enet_get_ts_info(struct net_device *ndev,
2219 struct ethtool_ts_info *info)
2220 {
2221 struct fec_enet_private *fep = netdev_priv(ndev);
2222
2223 if (fep->bufdesc_ex) {
2224
2225 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2226 SOF_TIMESTAMPING_RX_SOFTWARE |
2227 SOF_TIMESTAMPING_SOFTWARE |
2228 SOF_TIMESTAMPING_TX_HARDWARE |
2229 SOF_TIMESTAMPING_RX_HARDWARE |
2230 SOF_TIMESTAMPING_RAW_HARDWARE;
2231 if (fep->ptp_clock)
2232 info->phc_index = ptp_clock_index(fep->ptp_clock);
2233 else
2234 info->phc_index = -1;
2235
2236 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2237 (1 << HWTSTAMP_TX_ON);
2238
2239 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2240 (1 << HWTSTAMP_FILTER_ALL);
2241 return 0;
2242 } else {
2243 return ethtool_op_get_ts_info(ndev, info);
2244 }
2245 }
2246
2247 #if !defined(CONFIG_M5272)
2248
2249 static void fec_enet_get_pauseparam(struct net_device *ndev,
2250 struct ethtool_pauseparam *pause)
2251 {
2252 struct fec_enet_private *fep = netdev_priv(ndev);
2253
2254 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2255 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2256 pause->rx_pause = pause->tx_pause;
2257 }
2258
2259 static int fec_enet_set_pauseparam(struct net_device *ndev,
2260 struct ethtool_pauseparam *pause)
2261 {
2262 struct fec_enet_private *fep = netdev_priv(ndev);
2263
2264 if (!fep->phy_dev)
2265 return -ENODEV;
2266
2267 if (pause->tx_pause != pause->rx_pause) {
2268 netdev_info(ndev,
2269 "hardware only support enable/disable both tx and rx");
2270 return -EINVAL;
2271 }
2272
2273 fep->pause_flag = 0;
2274
2275 /* tx pause must be same as rx pause */
2276 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2277 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2278
2279 if (pause->rx_pause || pause->autoneg) {
2280 fep->phy_dev->supported |= ADVERTISED_Pause;
2281 fep->phy_dev->advertising |= ADVERTISED_Pause;
2282 } else {
2283 fep->phy_dev->supported &= ~ADVERTISED_Pause;
2284 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
2285 }
2286
2287 if (pause->autoneg) {
2288 if (netif_running(ndev))
2289 fec_stop(ndev);
2290 phy_start_aneg(fep->phy_dev);
2291 }
2292 if (netif_running(ndev)) {
2293 napi_disable(&fep->napi);
2294 netif_tx_lock_bh(ndev);
2295 fec_restart(ndev);
2296 netif_wake_queue(ndev);
2297 netif_tx_unlock_bh(ndev);
2298 napi_enable(&fep->napi);
2299 }
2300
2301 return 0;
2302 }
2303
2304 static const struct fec_stat {
2305 char name[ETH_GSTRING_LEN];
2306 u16 offset;
2307 } fec_stats[] = {
2308 /* RMON TX */
2309 { "tx_dropped", RMON_T_DROP },
2310 { "tx_packets", RMON_T_PACKETS },
2311 { "tx_broadcast", RMON_T_BC_PKT },
2312 { "tx_multicast", RMON_T_MC_PKT },
2313 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2314 { "tx_undersize", RMON_T_UNDERSIZE },
2315 { "tx_oversize", RMON_T_OVERSIZE },
2316 { "tx_fragment", RMON_T_FRAG },
2317 { "tx_jabber", RMON_T_JAB },
2318 { "tx_collision", RMON_T_COL },
2319 { "tx_64byte", RMON_T_P64 },
2320 { "tx_65to127byte", RMON_T_P65TO127 },
2321 { "tx_128to255byte", RMON_T_P128TO255 },
2322 { "tx_256to511byte", RMON_T_P256TO511 },
2323 { "tx_512to1023byte", RMON_T_P512TO1023 },
2324 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2325 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2326 { "tx_octets", RMON_T_OCTETS },
2327
2328 /* IEEE TX */
2329 { "IEEE_tx_drop", IEEE_T_DROP },
2330 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2331 { "IEEE_tx_1col", IEEE_T_1COL },
2332 { "IEEE_tx_mcol", IEEE_T_MCOL },
2333 { "IEEE_tx_def", IEEE_T_DEF },
2334 { "IEEE_tx_lcol", IEEE_T_LCOL },
2335 { "IEEE_tx_excol", IEEE_T_EXCOL },
2336 { "IEEE_tx_macerr", IEEE_T_MACERR },
2337 { "IEEE_tx_cserr", IEEE_T_CSERR },
2338 { "IEEE_tx_sqe", IEEE_T_SQE },
2339 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2340 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2341
2342 /* RMON RX */
2343 { "rx_packets", RMON_R_PACKETS },
2344 { "rx_broadcast", RMON_R_BC_PKT },
2345 { "rx_multicast", RMON_R_MC_PKT },
2346 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2347 { "rx_undersize", RMON_R_UNDERSIZE },
2348 { "rx_oversize", RMON_R_OVERSIZE },
2349 { "rx_fragment", RMON_R_FRAG },
2350 { "rx_jabber", RMON_R_JAB },
2351 { "rx_64byte", RMON_R_P64 },
2352 { "rx_65to127byte", RMON_R_P65TO127 },
2353 { "rx_128to255byte", RMON_R_P128TO255 },
2354 { "rx_256to511byte", RMON_R_P256TO511 },
2355 { "rx_512to1023byte", RMON_R_P512TO1023 },
2356 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2357 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2358 { "rx_octets", RMON_R_OCTETS },
2359
2360 /* IEEE RX */
2361 { "IEEE_rx_drop", IEEE_R_DROP },
2362 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2363 { "IEEE_rx_crc", IEEE_R_CRC },
2364 { "IEEE_rx_align", IEEE_R_ALIGN },
2365 { "IEEE_rx_macerr", IEEE_R_MACERR },
2366 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2367 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2368 };
2369
2370 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2371 struct ethtool_stats *stats, u64 *data)
2372 {
2373 struct fec_enet_private *fep = netdev_priv(dev);
2374 int i;
2375
2376 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2377 data[i] = readl(fep->hwp + fec_stats[i].offset);
2378 }
2379
2380 static void fec_enet_get_strings(struct net_device *netdev,
2381 u32 stringset, u8 *data)
2382 {
2383 int i;
2384 switch (stringset) {
2385 case ETH_SS_STATS:
2386 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2387 memcpy(data + i * ETH_GSTRING_LEN,
2388 fec_stats[i].name, ETH_GSTRING_LEN);
2389 break;
2390 }
2391 }
2392
2393 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2394 {
2395 switch (sset) {
2396 case ETH_SS_STATS:
2397 return ARRAY_SIZE(fec_stats);
2398 default:
2399 return -EOPNOTSUPP;
2400 }
2401 }
2402 #endif /* !defined(CONFIG_M5272) */
2403
2404 static int fec_enet_nway_reset(struct net_device *dev)
2405 {
2406 struct fec_enet_private *fep = netdev_priv(dev);
2407 struct phy_device *phydev = fep->phy_dev;
2408
2409 if (!phydev)
2410 return -ENODEV;
2411
2412 return genphy_restart_aneg(phydev);
2413 }
2414
2415 /* ITR clock source is enet system clock (clk_ahb).
2416 * TCTT unit is cycle_ns * 64 cycle
2417 * So, the ICTT value = X us / (cycle_ns * 64)
2418 */
2419 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2420 {
2421 struct fec_enet_private *fep = netdev_priv(ndev);
2422
2423 return us * (fep->itr_clk_rate / 64000) / 1000;
2424 }
2425
2426 /* Set threshold for interrupt coalescing */
2427 static void fec_enet_itr_coal_set(struct net_device *ndev)
2428 {
2429 struct fec_enet_private *fep = netdev_priv(ndev);
2430 int rx_itr, tx_itr;
2431
2432 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2433 return;
2434
2435 /* Must be greater than zero to avoid unpredictable behavior */
2436 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2437 !fep->tx_time_itr || !fep->tx_pkts_itr)
2438 return;
2439
2440 /* Select enet system clock as Interrupt Coalescing
2441 * timer Clock Source
2442 */
2443 rx_itr = FEC_ITR_CLK_SEL;
2444 tx_itr = FEC_ITR_CLK_SEL;
2445
2446 /* set ICFT and ICTT */
2447 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2448 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2449 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2450 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2451
2452 rx_itr |= FEC_ITR_EN;
2453 tx_itr |= FEC_ITR_EN;
2454
2455 writel(tx_itr, fep->hwp + FEC_TXIC0);
2456 writel(rx_itr, fep->hwp + FEC_RXIC0);
2457 writel(tx_itr, fep->hwp + FEC_TXIC1);
2458 writel(rx_itr, fep->hwp + FEC_RXIC1);
2459 writel(tx_itr, fep->hwp + FEC_TXIC2);
2460 writel(rx_itr, fep->hwp + FEC_RXIC2);
2461 }
2462
2463 static int
2464 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2465 {
2466 struct fec_enet_private *fep = netdev_priv(ndev);
2467
2468 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2469 return -EOPNOTSUPP;
2470
2471 ec->rx_coalesce_usecs = fep->rx_time_itr;
2472 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2473
2474 ec->tx_coalesce_usecs = fep->tx_time_itr;
2475 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2476
2477 return 0;
2478 }
2479
2480 static int
2481 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2482 {
2483 struct fec_enet_private *fep = netdev_priv(ndev);
2484 unsigned int cycle;
2485
2486 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2487 return -EOPNOTSUPP;
2488
2489 if (ec->rx_max_coalesced_frames > 255) {
2490 pr_err("Rx coalesced frames exceed hardware limiation");
2491 return -EINVAL;
2492 }
2493
2494 if (ec->tx_max_coalesced_frames > 255) {
2495 pr_err("Tx coalesced frame exceed hardware limiation");
2496 return -EINVAL;
2497 }
2498
2499 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2500 if (cycle > 0xFFFF) {
2501 pr_err("Rx coalesed usec exceeed hardware limiation");
2502 return -EINVAL;
2503 }
2504
2505 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2506 if (cycle > 0xFFFF) {
2507 pr_err("Rx coalesed usec exceeed hardware limiation");
2508 return -EINVAL;
2509 }
2510
2511 fep->rx_time_itr = ec->rx_coalesce_usecs;
2512 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2513
2514 fep->tx_time_itr = ec->tx_coalesce_usecs;
2515 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2516
2517 fec_enet_itr_coal_set(ndev);
2518
2519 return 0;
2520 }
2521
2522 static void fec_enet_itr_coal_init(struct net_device *ndev)
2523 {
2524 struct ethtool_coalesce ec;
2525
2526 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2527 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2528
2529 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2530 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2531
2532 fec_enet_set_coalesce(ndev, &ec);
2533 }
2534
2535 static int fec_enet_get_tunable(struct net_device *netdev,
2536 const struct ethtool_tunable *tuna,
2537 void *data)
2538 {
2539 struct fec_enet_private *fep = netdev_priv(netdev);
2540 int ret = 0;
2541
2542 switch (tuna->id) {
2543 case ETHTOOL_RX_COPYBREAK:
2544 *(u32 *)data = fep->rx_copybreak;
2545 break;
2546 default:
2547 ret = -EINVAL;
2548 break;
2549 }
2550
2551 return ret;
2552 }
2553
2554 static int fec_enet_set_tunable(struct net_device *netdev,
2555 const struct ethtool_tunable *tuna,
2556 const void *data)
2557 {
2558 struct fec_enet_private *fep = netdev_priv(netdev);
2559 int ret = 0;
2560
2561 switch (tuna->id) {
2562 case ETHTOOL_RX_COPYBREAK:
2563 fep->rx_copybreak = *(u32 *)data;
2564 break;
2565 default:
2566 ret = -EINVAL;
2567 break;
2568 }
2569
2570 return ret;
2571 }
2572
2573 static void
2574 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2575 {
2576 struct fec_enet_private *fep = netdev_priv(ndev);
2577
2578 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2579 wol->supported = WAKE_MAGIC;
2580 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2581 } else {
2582 wol->supported = wol->wolopts = 0;
2583 }
2584 }
2585
2586 static int
2587 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2588 {
2589 struct fec_enet_private *fep = netdev_priv(ndev);
2590
2591 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2592 return -EINVAL;
2593
2594 if (wol->wolopts & ~WAKE_MAGIC)
2595 return -EINVAL;
2596
2597 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2598 if (device_may_wakeup(&ndev->dev)) {
2599 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2600 if (fep->irq[0] > 0)
2601 enable_irq_wake(fep->irq[0]);
2602 } else {
2603 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2604 if (fep->irq[0] > 0)
2605 disable_irq_wake(fep->irq[0]);
2606 }
2607
2608 return 0;
2609 }
2610
2611 static const struct ethtool_ops fec_enet_ethtool_ops = {
2612 .get_settings = fec_enet_get_settings,
2613 .set_settings = fec_enet_set_settings,
2614 .get_drvinfo = fec_enet_get_drvinfo,
2615 .get_regs_len = fec_enet_get_regs_len,
2616 .get_regs = fec_enet_get_regs,
2617 .nway_reset = fec_enet_nway_reset,
2618 .get_link = ethtool_op_get_link,
2619 .get_coalesce = fec_enet_get_coalesce,
2620 .set_coalesce = fec_enet_set_coalesce,
2621 #ifndef CONFIG_M5272
2622 .get_pauseparam = fec_enet_get_pauseparam,
2623 .set_pauseparam = fec_enet_set_pauseparam,
2624 .get_strings = fec_enet_get_strings,
2625 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2626 .get_sset_count = fec_enet_get_sset_count,
2627 #endif
2628 .get_ts_info = fec_enet_get_ts_info,
2629 .get_tunable = fec_enet_get_tunable,
2630 .set_tunable = fec_enet_set_tunable,
2631 .get_wol = fec_enet_get_wol,
2632 .set_wol = fec_enet_set_wol,
2633 };
2634
2635 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2636 {
2637 struct fec_enet_private *fep = netdev_priv(ndev);
2638 struct phy_device *phydev = fep->phy_dev;
2639
2640 if (!netif_running(ndev))
2641 return -EINVAL;
2642
2643 if (!phydev)
2644 return -ENODEV;
2645
2646 if (fep->bufdesc_ex) {
2647 if (cmd == SIOCSHWTSTAMP)
2648 return fec_ptp_set(ndev, rq);
2649 if (cmd == SIOCGHWTSTAMP)
2650 return fec_ptp_get(ndev, rq);
2651 }
2652
2653 return phy_mii_ioctl(phydev, rq, cmd);
2654 }
2655
2656 static void fec_enet_free_buffers(struct net_device *ndev)
2657 {
2658 struct fec_enet_private *fep = netdev_priv(ndev);
2659 unsigned int i;
2660 struct sk_buff *skb;
2661 struct bufdesc *bdp;
2662 struct fec_enet_priv_tx_q *txq;
2663 struct fec_enet_priv_rx_q *rxq;
2664 unsigned int q;
2665
2666 for (q = 0; q < fep->num_rx_queues; q++) {
2667 rxq = fep->rx_queue[q];
2668 bdp = rxq->rx_bd_base;
2669 for (i = 0; i < rxq->rx_ring_size; i++) {
2670 skb = rxq->rx_skbuff[i];
2671 rxq->rx_skbuff[i] = NULL;
2672 if (skb) {
2673 dma_unmap_single(&fep->pdev->dev,
2674 bdp->cbd_bufaddr,
2675 FEC_ENET_RX_FRSIZE - fep->rx_align,
2676 DMA_FROM_DEVICE);
2677 dev_kfree_skb(skb);
2678 }
2679 bdp = fec_enet_get_nextdesc(bdp, fep, q);
2680 }
2681 }
2682
2683 for (q = 0; q < fep->num_tx_queues; q++) {
2684 txq = fep->tx_queue[q];
2685 bdp = txq->tx_bd_base;
2686 for (i = 0; i < txq->tx_ring_size; i++) {
2687 kfree(txq->tx_bounce[i]);
2688 txq->tx_bounce[i] = NULL;
2689 skb = txq->tx_skbuff[i];
2690 txq->tx_skbuff[i] = NULL;
2691 dev_kfree_skb(skb);
2692 }
2693 }
2694 }
2695
2696 static void fec_enet_free_queue(struct net_device *ndev)
2697 {
2698 struct fec_enet_private *fep = netdev_priv(ndev);
2699 int i;
2700 struct fec_enet_priv_tx_q *txq;
2701
2702 for (i = 0; i < fep->num_tx_queues; i++)
2703 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2704 txq = fep->tx_queue[i];
2705 dma_free_coherent(NULL,
2706 txq->tx_ring_size * TSO_HEADER_SIZE,
2707 txq->tso_hdrs,
2708 txq->tso_hdrs_dma);
2709 }
2710
2711 for (i = 0; i < fep->num_rx_queues; i++)
2712 kfree(fep->rx_queue[i]);
2713 for (i = 0; i < fep->num_tx_queues; i++)
2714 kfree(fep->tx_queue[i]);
2715 }
2716
2717 static int fec_enet_alloc_queue(struct net_device *ndev)
2718 {
2719 struct fec_enet_private *fep = netdev_priv(ndev);
2720 int i;
2721 int ret = 0;
2722 struct fec_enet_priv_tx_q *txq;
2723
2724 for (i = 0; i < fep->num_tx_queues; i++) {
2725 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2726 if (!txq) {
2727 ret = -ENOMEM;
2728 goto alloc_failed;
2729 }
2730
2731 fep->tx_queue[i] = txq;
2732 txq->tx_ring_size = TX_RING_SIZE;
2733 fep->total_tx_ring_size += fep->tx_queue[i]->tx_ring_size;
2734
2735 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2736 txq->tx_wake_threshold =
2737 (txq->tx_ring_size - txq->tx_stop_threshold) / 2;
2738
2739 txq->tso_hdrs = dma_alloc_coherent(NULL,
2740 txq->tx_ring_size * TSO_HEADER_SIZE,
2741 &txq->tso_hdrs_dma,
2742 GFP_KERNEL);
2743 if (!txq->tso_hdrs) {
2744 ret = -ENOMEM;
2745 goto alloc_failed;
2746 }
2747 }
2748
2749 for (i = 0; i < fep->num_rx_queues; i++) {
2750 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2751 GFP_KERNEL);
2752 if (!fep->rx_queue[i]) {
2753 ret = -ENOMEM;
2754 goto alloc_failed;
2755 }
2756
2757 fep->rx_queue[i]->rx_ring_size = RX_RING_SIZE;
2758 fep->total_rx_ring_size += fep->rx_queue[i]->rx_ring_size;
2759 }
2760 return ret;
2761
2762 alloc_failed:
2763 fec_enet_free_queue(ndev);
2764 return ret;
2765 }
2766
2767 static int
2768 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2769 {
2770 struct fec_enet_private *fep = netdev_priv(ndev);
2771 unsigned int i;
2772 struct sk_buff *skb;
2773 struct bufdesc *bdp;
2774 struct fec_enet_priv_rx_q *rxq;
2775
2776 rxq = fep->rx_queue[queue];
2777 bdp = rxq->rx_bd_base;
2778 for (i = 0; i < rxq->rx_ring_size; i++) {
2779 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2780 if (!skb)
2781 goto err_alloc;
2782
2783 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2784 dev_kfree_skb(skb);
2785 goto err_alloc;
2786 }
2787
2788 rxq->rx_skbuff[i] = skb;
2789 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2790
2791 if (fep->bufdesc_ex) {
2792 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2793 ebdp->cbd_esc = BD_ENET_RX_INT;
2794 }
2795
2796 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2797 }
2798
2799 /* Set the last buffer to wrap. */
2800 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2801 bdp->cbd_sc |= BD_SC_WRAP;
2802 return 0;
2803
2804 err_alloc:
2805 fec_enet_free_buffers(ndev);
2806 return -ENOMEM;
2807 }
2808
2809 static int
2810 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2811 {
2812 struct fec_enet_private *fep = netdev_priv(ndev);
2813 unsigned int i;
2814 struct bufdesc *bdp;
2815 struct fec_enet_priv_tx_q *txq;
2816
2817 txq = fep->tx_queue[queue];
2818 bdp = txq->tx_bd_base;
2819 for (i = 0; i < txq->tx_ring_size; i++) {
2820 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2821 if (!txq->tx_bounce[i])
2822 goto err_alloc;
2823
2824 bdp->cbd_sc = 0;
2825 bdp->cbd_bufaddr = 0;
2826
2827 if (fep->bufdesc_ex) {
2828 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2829 ebdp->cbd_esc = BD_ENET_TX_INT;
2830 }
2831
2832 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2833 }
2834
2835 /* Set the last buffer to wrap. */
2836 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2837 bdp->cbd_sc |= BD_SC_WRAP;
2838
2839 return 0;
2840
2841 err_alloc:
2842 fec_enet_free_buffers(ndev);
2843 return -ENOMEM;
2844 }
2845
2846 static int fec_enet_alloc_buffers(struct net_device *ndev)
2847 {
2848 struct fec_enet_private *fep = netdev_priv(ndev);
2849 unsigned int i;
2850
2851 for (i = 0; i < fep->num_rx_queues; i++)
2852 if (fec_enet_alloc_rxq_buffers(ndev, i))
2853 return -ENOMEM;
2854
2855 for (i = 0; i < fep->num_tx_queues; i++)
2856 if (fec_enet_alloc_txq_buffers(ndev, i))
2857 return -ENOMEM;
2858 return 0;
2859 }
2860
2861 static int
2862 fec_enet_open(struct net_device *ndev)
2863 {
2864 struct fec_enet_private *fep = netdev_priv(ndev);
2865 int ret;
2866
2867 ret = pm_runtime_get_sync(&fep->pdev->dev);
2868 if (IS_ERR_VALUE(ret))
2869 return ret;
2870
2871 pinctrl_pm_select_default_state(&fep->pdev->dev);
2872 ret = fec_enet_clk_enable(ndev, true);
2873 if (ret)
2874 goto clk_enable;
2875
2876 /* I should reset the ring buffers here, but I don't yet know
2877 * a simple way to do that.
2878 */
2879
2880 ret = fec_enet_alloc_buffers(ndev);
2881 if (ret)
2882 goto err_enet_alloc;
2883
2884 /* Init MAC prior to mii bus probe */
2885 fec_restart(ndev);
2886
2887 /* Probe and connect to PHY when open the interface */
2888 ret = fec_enet_mii_probe(ndev);
2889 if (ret)
2890 goto err_enet_mii_probe;
2891
2892 napi_enable(&fep->napi);
2893 phy_start(fep->phy_dev);
2894 netif_tx_start_all_queues(ndev);
2895
2896 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2897 FEC_WOL_FLAG_ENABLE);
2898
2899 return 0;
2900
2901 err_enet_mii_probe:
2902 fec_enet_free_buffers(ndev);
2903 err_enet_alloc:
2904 fec_enet_clk_enable(ndev, false);
2905 clk_enable:
2906 pm_runtime_mark_last_busy(&fep->pdev->dev);
2907 pm_runtime_put_autosuspend(&fep->pdev->dev);
2908 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2909 return ret;
2910 }
2911
2912 static int
2913 fec_enet_close(struct net_device *ndev)
2914 {
2915 struct fec_enet_private *fep = netdev_priv(ndev);
2916
2917 phy_stop(fep->phy_dev);
2918
2919 if (netif_device_present(ndev)) {
2920 napi_disable(&fep->napi);
2921 netif_tx_disable(ndev);
2922 fec_stop(ndev);
2923 }
2924
2925 phy_disconnect(fep->phy_dev);
2926 fep->phy_dev = NULL;
2927
2928 fec_enet_clk_enable(ndev, false);
2929 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2930 pm_runtime_mark_last_busy(&fep->pdev->dev);
2931 pm_runtime_put_autosuspend(&fep->pdev->dev);
2932
2933 fec_enet_free_buffers(ndev);
2934
2935 return 0;
2936 }
2937
2938 /* Set or clear the multicast filter for this adaptor.
2939 * Skeleton taken from sunlance driver.
2940 * The CPM Ethernet implementation allows Multicast as well as individual
2941 * MAC address filtering. Some of the drivers check to make sure it is
2942 * a group multicast address, and discard those that are not. I guess I
2943 * will do the same for now, but just remove the test if you want
2944 * individual filtering as well (do the upper net layers want or support
2945 * this kind of feature?).
2946 */
2947
2948 #define HASH_BITS 6 /* #bits in hash */
2949 #define CRC32_POLY 0xEDB88320
2950
2951 static void set_multicast_list(struct net_device *ndev)
2952 {
2953 struct fec_enet_private *fep = netdev_priv(ndev);
2954 struct netdev_hw_addr *ha;
2955 unsigned int i, bit, data, crc, tmp;
2956 unsigned char hash;
2957
2958 if (ndev->flags & IFF_PROMISC) {
2959 tmp = readl(fep->hwp + FEC_R_CNTRL);
2960 tmp |= 0x8;
2961 writel(tmp, fep->hwp + FEC_R_CNTRL);
2962 return;
2963 }
2964
2965 tmp = readl(fep->hwp + FEC_R_CNTRL);
2966 tmp &= ~0x8;
2967 writel(tmp, fep->hwp + FEC_R_CNTRL);
2968
2969 if (ndev->flags & IFF_ALLMULTI) {
2970 /* Catch all multicast addresses, so set the
2971 * filter to all 1's
2972 */
2973 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2974 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2975
2976 return;
2977 }
2978
2979 /* Clear filter and add the addresses in hash register
2980 */
2981 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2982 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2983
2984 netdev_for_each_mc_addr(ha, ndev) {
2985 /* calculate crc32 value of mac address */
2986 crc = 0xffffffff;
2987
2988 for (i = 0; i < ndev->addr_len; i++) {
2989 data = ha->addr[i];
2990 for (bit = 0; bit < 8; bit++, data >>= 1) {
2991 crc = (crc >> 1) ^
2992 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2993 }
2994 }
2995
2996 /* only upper 6 bits (HASH_BITS) are used
2997 * which point to specific bit in he hash registers
2998 */
2999 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
3000
3001 if (hash > 31) {
3002 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3003 tmp |= 1 << (hash - 32);
3004 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3005 } else {
3006 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3007 tmp |= 1 << hash;
3008 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3009 }
3010 }
3011 }
3012
3013 /* Set a MAC change in hardware. */
3014 static int
3015 fec_set_mac_address(struct net_device *ndev, void *p)
3016 {
3017 struct fec_enet_private *fep = netdev_priv(ndev);
3018 struct sockaddr *addr = p;
3019
3020 if (addr) {
3021 if (!is_valid_ether_addr(addr->sa_data))
3022 return -EADDRNOTAVAIL;
3023 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3024 }
3025
3026 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3027 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
3028 fep->hwp + FEC_ADDR_LOW);
3029 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
3030 fep->hwp + FEC_ADDR_HIGH);
3031 return 0;
3032 }
3033
3034 #ifdef CONFIG_NET_POLL_CONTROLLER
3035 /**
3036 * fec_poll_controller - FEC Poll controller function
3037 * @dev: The FEC network adapter
3038 *
3039 * Polled functionality used by netconsole and others in non interrupt mode
3040 *
3041 */
3042 static void fec_poll_controller(struct net_device *dev)
3043 {
3044 int i;
3045 struct fec_enet_private *fep = netdev_priv(dev);
3046
3047 for (i = 0; i < FEC_IRQ_NUM; i++) {
3048 if (fep->irq[i] > 0) {
3049 disable_irq(fep->irq[i]);
3050 fec_enet_interrupt(fep->irq[i], dev);
3051 enable_irq(fep->irq[i]);
3052 }
3053 }
3054 }
3055 #endif
3056
3057 #define FEATURES_NEED_QUIESCE NETIF_F_RXCSUM
3058 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3059 netdev_features_t features)
3060 {
3061 struct fec_enet_private *fep = netdev_priv(netdev);
3062 netdev_features_t changed = features ^ netdev->features;
3063
3064 netdev->features = features;
3065
3066 /* Receive checksum has been changed */
3067 if (changed & NETIF_F_RXCSUM) {
3068 if (features & NETIF_F_RXCSUM)
3069 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3070 else
3071 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3072 }
3073 }
3074
3075 static int fec_set_features(struct net_device *netdev,
3076 netdev_features_t features)
3077 {
3078 struct fec_enet_private *fep = netdev_priv(netdev);
3079 netdev_features_t changed = features ^ netdev->features;
3080
3081 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) {
3082 napi_disable(&fep->napi);
3083 netif_tx_lock_bh(netdev);
3084 fec_stop(netdev);
3085 fec_enet_set_netdev_features(netdev, features);
3086 fec_restart(netdev);
3087 netif_tx_wake_all_queues(netdev);
3088 netif_tx_unlock_bh(netdev);
3089 napi_enable(&fep->napi);
3090 } else {
3091 fec_enet_set_netdev_features(netdev, features);
3092 }
3093
3094 return 0;
3095 }
3096
3097 static const struct net_device_ops fec_netdev_ops = {
3098 .ndo_open = fec_enet_open,
3099 .ndo_stop = fec_enet_close,
3100 .ndo_start_xmit = fec_enet_start_xmit,
3101 .ndo_set_rx_mode = set_multicast_list,
3102 .ndo_change_mtu = eth_change_mtu,
3103 .ndo_validate_addr = eth_validate_addr,
3104 .ndo_tx_timeout = fec_timeout,
3105 .ndo_set_mac_address = fec_set_mac_address,
3106 .ndo_do_ioctl = fec_enet_ioctl,
3107 #ifdef CONFIG_NET_POLL_CONTROLLER
3108 .ndo_poll_controller = fec_poll_controller,
3109 #endif
3110 .ndo_set_features = fec_set_features,
3111 };
3112
3113 /*
3114 * XXX: We need to clean up on failure exits here.
3115 *
3116 */
3117 static int fec_enet_init(struct net_device *ndev)
3118 {
3119 struct fec_enet_private *fep = netdev_priv(ndev);
3120 struct fec_enet_priv_tx_q *txq;
3121 struct fec_enet_priv_rx_q *rxq;
3122 struct bufdesc *cbd_base;
3123 dma_addr_t bd_dma;
3124 int bd_size;
3125 unsigned int i;
3126
3127 #if defined(CONFIG_ARM)
3128 fep->rx_align = 0xf;
3129 fep->tx_align = 0xf;
3130 #else
3131 fep->rx_align = 0x3;
3132 fep->tx_align = 0x3;
3133 #endif
3134
3135 fec_enet_alloc_queue(ndev);
3136
3137 if (fep->bufdesc_ex)
3138 fep->bufdesc_size = sizeof(struct bufdesc_ex);
3139 else
3140 fep->bufdesc_size = sizeof(struct bufdesc);
3141 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) *
3142 fep->bufdesc_size;
3143
3144 /* Allocate memory for buffer descriptors. */
3145 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3146 GFP_KERNEL);
3147 if (!cbd_base) {
3148 return -ENOMEM;
3149 }
3150
3151 memset(cbd_base, 0, bd_size);
3152
3153 /* Get the Ethernet address */
3154 fec_get_mac(ndev);
3155 /* make sure MAC we just acquired is programmed into the hw */
3156 fec_set_mac_address(ndev, NULL);
3157
3158 /* Set receive and transmit descriptor base. */
3159 for (i = 0; i < fep->num_rx_queues; i++) {
3160 rxq = fep->rx_queue[i];
3161 rxq->index = i;
3162 rxq->rx_bd_base = (struct bufdesc *)cbd_base;
3163 rxq->bd_dma = bd_dma;
3164 if (fep->bufdesc_ex) {
3165 bd_dma += sizeof(struct bufdesc_ex) * rxq->rx_ring_size;
3166 cbd_base = (struct bufdesc *)
3167 (((struct bufdesc_ex *)cbd_base) + rxq->rx_ring_size);
3168 } else {
3169 bd_dma += sizeof(struct bufdesc) * rxq->rx_ring_size;
3170 cbd_base += rxq->rx_ring_size;
3171 }
3172 }
3173
3174 for (i = 0; i < fep->num_tx_queues; i++) {
3175 txq = fep->tx_queue[i];
3176 txq->index = i;
3177 txq->tx_bd_base = (struct bufdesc *)cbd_base;
3178 txq->bd_dma = bd_dma;
3179 if (fep->bufdesc_ex) {
3180 bd_dma += sizeof(struct bufdesc_ex) * txq->tx_ring_size;
3181 cbd_base = (struct bufdesc *)
3182 (((struct bufdesc_ex *)cbd_base) + txq->tx_ring_size);
3183 } else {
3184 bd_dma += sizeof(struct bufdesc) * txq->tx_ring_size;
3185 cbd_base += txq->tx_ring_size;
3186 }
3187 }
3188
3189
3190 /* The FEC Ethernet specific entries in the device structure */
3191 ndev->watchdog_timeo = TX_TIMEOUT;
3192 ndev->netdev_ops = &fec_netdev_ops;
3193 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3194
3195 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3196 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3197
3198 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3199 /* enable hw VLAN support */
3200 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3201
3202 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3203 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3204
3205 /* enable hw accelerator */
3206 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3207 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3208 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3209 }
3210
3211 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3212 fep->tx_align = 0;
3213 fep->rx_align = 0x3f;
3214 }
3215
3216 ndev->hw_features = ndev->features;
3217
3218 fec_restart(ndev);
3219
3220 return 0;
3221 }
3222
3223 #ifdef CONFIG_OF
3224 static void fec_reset_phy(struct platform_device *pdev)
3225 {
3226 int err, phy_reset;
3227 int msec = 1;
3228 struct device_node *np = pdev->dev.of_node;
3229
3230 if (!np)
3231 return;
3232
3233 of_property_read_u32(np, "phy-reset-duration", &msec);
3234 /* A sane reset duration should not be longer than 1s */
3235 if (msec > 1000)
3236 msec = 1;
3237
3238 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3239 if (!gpio_is_valid(phy_reset))
3240 return;
3241
3242 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3243 GPIOF_OUT_INIT_LOW, "phy-reset");
3244 if (err) {
3245 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3246 return;
3247 }
3248 msleep(msec);
3249 gpio_set_value(phy_reset, 1);
3250 }
3251 #else /* CONFIG_OF */
3252 static void fec_reset_phy(struct platform_device *pdev)
3253 {
3254 /*
3255 * In case of platform probe, the reset has been done
3256 * by machine code.
3257 */
3258 }
3259 #endif /* CONFIG_OF */
3260
3261 static void
3262 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3263 {
3264 struct device_node *np = pdev->dev.of_node;
3265 int err;
3266
3267 *num_tx = *num_rx = 1;
3268
3269 if (!np || !of_device_is_available(np))
3270 return;
3271
3272 /* parse the num of tx and rx queues */
3273 err = of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3274 if (err)
3275 *num_tx = 1;
3276
3277 err = of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3278 if (err)
3279 *num_rx = 1;
3280
3281 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3282 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3283 *num_tx);
3284 *num_tx = 1;
3285 return;
3286 }
3287
3288 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3289 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3290 *num_rx);
3291 *num_rx = 1;
3292 return;
3293 }
3294
3295 }
3296
3297 static int
3298 fec_probe(struct platform_device *pdev)
3299 {
3300 struct fec_enet_private *fep;
3301 struct fec_platform_data *pdata;
3302 struct net_device *ndev;
3303 int i, irq, ret = 0;
3304 struct resource *r;
3305 const struct of_device_id *of_id;
3306 static int dev_id;
3307 struct device_node *np = pdev->dev.of_node, *phy_node;
3308 int num_tx_qs;
3309 int num_rx_qs;
3310
3311 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3312
3313 /* Init network device */
3314 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
3315 num_tx_qs, num_rx_qs);
3316 if (!ndev)
3317 return -ENOMEM;
3318
3319 SET_NETDEV_DEV(ndev, &pdev->dev);
3320
3321 /* setup board info structure */
3322 fep = netdev_priv(ndev);
3323
3324 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3325 if (of_id)
3326 pdev->id_entry = of_id->data;
3327 fep->quirks = pdev->id_entry->driver_data;
3328
3329 fep->netdev = ndev;
3330 fep->num_rx_queues = num_rx_qs;
3331 fep->num_tx_queues = num_tx_qs;
3332
3333 #if !defined(CONFIG_M5272)
3334 /* default enable pause frame auto negotiation */
3335 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3336 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3337 #endif
3338
3339 /* Select default pin state */
3340 pinctrl_pm_select_default_state(&pdev->dev);
3341
3342 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3343 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3344 if (IS_ERR(fep->hwp)) {
3345 ret = PTR_ERR(fep->hwp);
3346 goto failed_ioremap;
3347 }
3348
3349 fep->pdev = pdev;
3350 fep->dev_id = dev_id++;
3351
3352 platform_set_drvdata(pdev, ndev);
3353
3354 if (of_get_property(np, "fsl,magic-packet", NULL))
3355 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3356
3357 phy_node = of_parse_phandle(np, "phy-handle", 0);
3358 if (!phy_node && of_phy_is_fixed_link(np)) {
3359 ret = of_phy_register_fixed_link(np);
3360 if (ret < 0) {
3361 dev_err(&pdev->dev,
3362 "broken fixed-link specification\n");
3363 goto failed_phy;
3364 }
3365 phy_node = of_node_get(np);
3366 }
3367 fep->phy_node = phy_node;
3368
3369 ret = of_get_phy_mode(pdev->dev.of_node);
3370 if (ret < 0) {
3371 pdata = dev_get_platdata(&pdev->dev);
3372 if (pdata)
3373 fep->phy_interface = pdata->phy;
3374 else
3375 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3376 } else {
3377 fep->phy_interface = ret;
3378 }
3379
3380 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3381 if (IS_ERR(fep->clk_ipg)) {
3382 ret = PTR_ERR(fep->clk_ipg);
3383 goto failed_clk;
3384 }
3385
3386 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3387 if (IS_ERR(fep->clk_ahb)) {
3388 ret = PTR_ERR(fep->clk_ahb);
3389 goto failed_clk;
3390 }
3391
3392 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3393
3394 /* enet_out is optional, depends on board */
3395 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3396 if (IS_ERR(fep->clk_enet_out))
3397 fep->clk_enet_out = NULL;
3398
3399 fep->ptp_clk_on = false;
3400 mutex_init(&fep->ptp_clk_mutex);
3401
3402 /* clk_ref is optional, depends on board */
3403 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3404 if (IS_ERR(fep->clk_ref))
3405 fep->clk_ref = NULL;
3406
3407 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3408 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3409 if (IS_ERR(fep->clk_ptp)) {
3410 fep->clk_ptp = NULL;
3411 fep->bufdesc_ex = false;
3412 }
3413
3414 ret = fec_enet_clk_enable(ndev, true);
3415 if (ret)
3416 goto failed_clk;
3417
3418 ret = clk_prepare_enable(fep->clk_ipg);
3419 if (ret)
3420 goto failed_clk_ipg;
3421
3422 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3423 if (!IS_ERR(fep->reg_phy)) {
3424 ret = regulator_enable(fep->reg_phy);
3425 if (ret) {
3426 dev_err(&pdev->dev,
3427 "Failed to enable phy regulator: %d\n", ret);
3428 goto failed_regulator;
3429 }
3430 } else {
3431 fep->reg_phy = NULL;
3432 }
3433
3434 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3435 pm_runtime_use_autosuspend(&pdev->dev);
3436 pm_runtime_set_active(&pdev->dev);
3437 pm_runtime_enable(&pdev->dev);
3438
3439 fec_reset_phy(pdev);
3440
3441 if (fep->bufdesc_ex)
3442 fec_ptp_init(pdev);
3443
3444 ret = fec_enet_init(ndev);
3445 if (ret)
3446 goto failed_init;
3447
3448 for (i = 0; i < FEC_IRQ_NUM; i++) {
3449 irq = platform_get_irq(pdev, i);
3450 if (irq < 0) {
3451 if (i)
3452 break;
3453 ret = irq;
3454 goto failed_irq;
3455 }
3456 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3457 0, pdev->name, ndev);
3458 if (ret)
3459 goto failed_irq;
3460
3461 fep->irq[i] = irq;
3462 }
3463
3464 init_completion(&fep->mdio_done);
3465 ret = fec_enet_mii_init(pdev);
3466 if (ret)
3467 goto failed_mii_init;
3468
3469 /* Carrier starts down, phylib will bring it up */
3470 netif_carrier_off(ndev);
3471 fec_enet_clk_enable(ndev, false);
3472 pinctrl_pm_select_sleep_state(&pdev->dev);
3473
3474 ret = register_netdev(ndev);
3475 if (ret)
3476 goto failed_register;
3477
3478 device_init_wakeup(&ndev->dev, fep->wol_flag &
3479 FEC_WOL_HAS_MAGIC_PACKET);
3480
3481 if (fep->bufdesc_ex && fep->ptp_clock)
3482 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3483
3484 fep->rx_copybreak = COPYBREAK_DEFAULT;
3485 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3486
3487 pm_runtime_mark_last_busy(&pdev->dev);
3488 pm_runtime_put_autosuspend(&pdev->dev);
3489
3490 return 0;
3491
3492 failed_register:
3493 fec_enet_mii_remove(fep);
3494 failed_mii_init:
3495 failed_irq:
3496 failed_init:
3497 fec_ptp_stop(pdev);
3498 if (fep->reg_phy)
3499 regulator_disable(fep->reg_phy);
3500 failed_regulator:
3501 clk_disable_unprepare(fep->clk_ipg);
3502 failed_clk_ipg:
3503 fec_enet_clk_enable(ndev, false);
3504 failed_clk:
3505 failed_phy:
3506 of_node_put(phy_node);
3507 failed_ioremap:
3508 free_netdev(ndev);
3509
3510 return ret;
3511 }
3512
3513 static int
3514 fec_drv_remove(struct platform_device *pdev)
3515 {
3516 struct net_device *ndev = platform_get_drvdata(pdev);
3517 struct fec_enet_private *fep = netdev_priv(ndev);
3518
3519 cancel_work_sync(&fep->tx_timeout_work);
3520 fec_ptp_stop(pdev);
3521 unregister_netdev(ndev);
3522 fec_enet_mii_remove(fep);
3523 if (fep->reg_phy)
3524 regulator_disable(fep->reg_phy);
3525 of_node_put(fep->phy_node);
3526 free_netdev(ndev);
3527
3528 return 0;
3529 }
3530
3531 static int __maybe_unused fec_suspend(struct device *dev)
3532 {
3533 struct net_device *ndev = dev_get_drvdata(dev);
3534 struct fec_enet_private *fep = netdev_priv(ndev);
3535
3536 rtnl_lock();
3537 if (netif_running(ndev)) {
3538 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3539 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
3540 phy_stop(fep->phy_dev);
3541 napi_disable(&fep->napi);
3542 netif_tx_lock_bh(ndev);
3543 netif_device_detach(ndev);
3544 netif_tx_unlock_bh(ndev);
3545 fec_stop(ndev);
3546 fec_enet_clk_enable(ndev, false);
3547 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3548 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3549 }
3550 rtnl_unlock();
3551
3552 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3553 regulator_disable(fep->reg_phy);
3554
3555 /* SOC supply clock to phy, when clock is disabled, phy link down
3556 * SOC control phy regulator, when regulator is disabled, phy link down
3557 */
3558 if (fep->clk_enet_out || fep->reg_phy)
3559 fep->link = 0;
3560
3561 return 0;
3562 }
3563
3564 static int __maybe_unused fec_resume(struct device *dev)
3565 {
3566 struct net_device *ndev = dev_get_drvdata(dev);
3567 struct fec_enet_private *fep = netdev_priv(ndev);
3568 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
3569 int ret;
3570 int val;
3571
3572 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
3573 ret = regulator_enable(fep->reg_phy);
3574 if (ret)
3575 return ret;
3576 }
3577
3578 rtnl_lock();
3579 if (netif_running(ndev)) {
3580 ret = fec_enet_clk_enable(ndev, true);
3581 if (ret) {
3582 rtnl_unlock();
3583 goto failed_clk;
3584 }
3585 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3586 if (pdata && pdata->sleep_mode_enable)
3587 pdata->sleep_mode_enable(false);
3588 val = readl(fep->hwp + FEC_ECNTRL);
3589 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3590 writel(val, fep->hwp + FEC_ECNTRL);
3591 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3592 } else {
3593 pinctrl_pm_select_default_state(&fep->pdev->dev);
3594 }
3595 fec_restart(ndev);
3596 netif_tx_lock_bh(ndev);
3597 netif_device_attach(ndev);
3598 netif_tx_unlock_bh(ndev);
3599 napi_enable(&fep->napi);
3600 phy_start(fep->phy_dev);
3601 }
3602 rtnl_unlock();
3603
3604 return 0;
3605
3606 failed_clk:
3607 if (fep->reg_phy)
3608 regulator_disable(fep->reg_phy);
3609 return ret;
3610 }
3611
3612 static int __maybe_unused fec_runtime_suspend(struct device *dev)
3613 {
3614 struct net_device *ndev = dev_get_drvdata(dev);
3615 struct fec_enet_private *fep = netdev_priv(ndev);
3616
3617 clk_disable_unprepare(fep->clk_ipg);
3618
3619 return 0;
3620 }
3621
3622 static int __maybe_unused fec_runtime_resume(struct device *dev)
3623 {
3624 struct net_device *ndev = dev_get_drvdata(dev);
3625 struct fec_enet_private *fep = netdev_priv(ndev);
3626
3627 return clk_prepare_enable(fep->clk_ipg);
3628 }
3629
3630 static const struct dev_pm_ops fec_pm_ops = {
3631 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3632 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3633 };
3634
3635 static struct platform_driver fec_driver = {
3636 .driver = {
3637 .name = DRIVER_NAME,
3638 .pm = &fec_pm_ops,
3639 .of_match_table = fec_dt_ids,
3640 },
3641 .id_table = fec_devtype,
3642 .probe = fec_probe,
3643 .remove = fec_drv_remove,
3644 };
3645
3646 module_platform_driver(fec_driver);
3647
3648 MODULE_ALIAS("platform:"DRIVER_NAME);
3649 MODULE_LICENSE("GPL");
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