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Merge remote-tracking branches 'asoc/topic/davinci', 'asoc/topic/fsl-card' and 'asoc...
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / freescale / fec_main.c
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 *
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/ptrace.h>
29 #include <linux/errno.h>
30 #include <linux/ioport.h>
31 #include <linux/slab.h>
32 #include <linux/interrupt.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/in.h>
38 #include <linux/ip.h>
39 #include <net/ip.h>
40 #include <net/tso.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/icmp.h>
44 #include <linux/spinlock.h>
45 #include <linux/workqueue.h>
46 #include <linux/bitops.h>
47 #include <linux/io.h>
48 #include <linux/irq.h>
49 #include <linux/clk.h>
50 #include <linux/platform_device.h>
51 #include <linux/mdio.h>
52 #include <linux/phy.h>
53 #include <linux/fec.h>
54 #include <linux/of.h>
55 #include <linux/of_device.h>
56 #include <linux/of_gpio.h>
57 #include <linux/of_mdio.h>
58 #include <linux/of_net.h>
59 #include <linux/regulator/consumer.h>
60 #include <linux/if_vlan.h>
61 #include <linux/pinctrl/consumer.h>
62 #include <linux/prefetch.h>
63
64 #include <asm/cacheflush.h>
65
66 #include "fec.h"
67
68 static void set_multicast_list(struct net_device *ndev);
69 static void fec_enet_itr_coal_init(struct net_device *ndev);
70
71 #define DRIVER_NAME "fec"
72
73 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
74
75 /* Pause frame feild and FIFO threshold */
76 #define FEC_ENET_FCE (1 << 5)
77 #define FEC_ENET_RSEM_V 0x84
78 #define FEC_ENET_RSFL_V 16
79 #define FEC_ENET_RAEM_V 0x8
80 #define FEC_ENET_RAFL_V 0x8
81 #define FEC_ENET_OPD_V 0xFFF0
82 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */
83
84 static struct platform_device_id fec_devtype[] = {
85 {
86 /* keep it for coldfire */
87 .name = DRIVER_NAME,
88 .driver_data = 0,
89 }, {
90 .name = "imx25-fec",
91 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_HAS_RACC,
92 }, {
93 .name = "imx27-fec",
94 .driver_data = FEC_QUIRK_HAS_RACC,
95 }, {
96 .name = "imx28-fec",
97 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
98 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC,
99 }, {
100 .name = "imx6q-fec",
101 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
102 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
103 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
104 FEC_QUIRK_HAS_RACC,
105 }, {
106 .name = "mvf600-fec",
107 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
108 }, {
109 .name = "imx6sx-fec",
110 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
111 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
112 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
113 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
114 FEC_QUIRK_HAS_RACC,
115 }, {
116 /* sentinel */
117 }
118 };
119 MODULE_DEVICE_TABLE(platform, fec_devtype);
120
121 enum imx_fec_type {
122 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
123 IMX27_FEC, /* runs on i.mx27/35/51 */
124 IMX28_FEC,
125 IMX6Q_FEC,
126 MVF600_FEC,
127 IMX6SX_FEC,
128 };
129
130 static const struct of_device_id fec_dt_ids[] = {
131 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
132 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
133 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
134 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
135 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
136 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
137 { /* sentinel */ }
138 };
139 MODULE_DEVICE_TABLE(of, fec_dt_ids);
140
141 static unsigned char macaddr[ETH_ALEN];
142 module_param_array(macaddr, byte, NULL, 0);
143 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
144
145 #if defined(CONFIG_M5272)
146 /*
147 * Some hardware gets it MAC address out of local flash memory.
148 * if this is non-zero then assume it is the address to get MAC from.
149 */
150 #if defined(CONFIG_NETtel)
151 #define FEC_FLASHMAC 0xf0006006
152 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
153 #define FEC_FLASHMAC 0xf0006000
154 #elif defined(CONFIG_CANCam)
155 #define FEC_FLASHMAC 0xf0020000
156 #elif defined (CONFIG_M5272C3)
157 #define FEC_FLASHMAC (0xffe04000 + 4)
158 #elif defined(CONFIG_MOD5272)
159 #define FEC_FLASHMAC 0xffc0406b
160 #else
161 #define FEC_FLASHMAC 0
162 #endif
163 #endif /* CONFIG_M5272 */
164
165 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
166 */
167 #define PKT_MAXBUF_SIZE 1522
168 #define PKT_MINBUF_SIZE 64
169 #define PKT_MAXBLR_SIZE 1536
170
171 /* FEC receive acceleration */
172 #define FEC_RACC_IPDIS (1 << 1)
173 #define FEC_RACC_PRODIS (1 << 2)
174 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
175
176 /*
177 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
178 * size bits. Other FEC hardware does not, so we need to take that into
179 * account when setting it.
180 */
181 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
182 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
183 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
184 #else
185 #define OPT_FRAME_SIZE 0
186 #endif
187
188 /* FEC MII MMFR bits definition */
189 #define FEC_MMFR_ST (1 << 30)
190 #define FEC_MMFR_OP_READ (2 << 28)
191 #define FEC_MMFR_OP_WRITE (1 << 28)
192 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
193 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
194 #define FEC_MMFR_TA (2 << 16)
195 #define FEC_MMFR_DATA(v) (v & 0xffff)
196 /* FEC ECR bits definition */
197 #define FEC_ECR_MAGICEN (1 << 2)
198 #define FEC_ECR_SLEEP (1 << 3)
199
200 #define FEC_MII_TIMEOUT 30000 /* us */
201
202 /* Transmitter timeout */
203 #define TX_TIMEOUT (2 * HZ)
204
205 #define FEC_PAUSE_FLAG_AUTONEG 0x1
206 #define FEC_PAUSE_FLAG_ENABLE 0x2
207 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
208 #define FEC_WOL_FLAG_ENABLE (0x1 << 1)
209 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
210
211 #define COPYBREAK_DEFAULT 256
212
213 #define TSO_HEADER_SIZE 128
214 /* Max number of allowed TCP segments for software TSO */
215 #define FEC_MAX_TSO_SEGS 100
216 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
217
218 #define IS_TSO_HEADER(txq, addr) \
219 ((addr >= txq->tso_hdrs_dma) && \
220 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
221
222 static int mii_cnt;
223
224 static inline
225 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
226 struct fec_enet_private *fep,
227 int queue_id)
228 {
229 struct bufdesc *new_bd = bdp + 1;
230 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
231 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
232 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
233 struct bufdesc_ex *ex_base;
234 struct bufdesc *base;
235 int ring_size;
236
237 if (bdp >= txq->tx_bd_base) {
238 base = txq->tx_bd_base;
239 ring_size = txq->tx_ring_size;
240 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
241 } else {
242 base = rxq->rx_bd_base;
243 ring_size = rxq->rx_ring_size;
244 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
245 }
246
247 if (fep->bufdesc_ex)
248 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
249 ex_base : ex_new_bd);
250 else
251 return (new_bd >= (base + ring_size)) ?
252 base : new_bd;
253 }
254
255 static inline
256 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
257 struct fec_enet_private *fep,
258 int queue_id)
259 {
260 struct bufdesc *new_bd = bdp - 1;
261 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
262 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
263 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
264 struct bufdesc_ex *ex_base;
265 struct bufdesc *base;
266 int ring_size;
267
268 if (bdp >= txq->tx_bd_base) {
269 base = txq->tx_bd_base;
270 ring_size = txq->tx_ring_size;
271 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
272 } else {
273 base = rxq->rx_bd_base;
274 ring_size = rxq->rx_ring_size;
275 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
276 }
277
278 if (fep->bufdesc_ex)
279 return (struct bufdesc *)((ex_new_bd < ex_base) ?
280 (ex_new_bd + ring_size) : ex_new_bd);
281 else
282 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
283 }
284
285 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
286 struct fec_enet_private *fep)
287 {
288 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
289 }
290
291 static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep,
292 struct fec_enet_priv_tx_q *txq)
293 {
294 int entries;
295
296 entries = ((const char *)txq->dirty_tx -
297 (const char *)txq->cur_tx) / fep->bufdesc_size - 1;
298
299 return entries > 0 ? entries : entries + txq->tx_ring_size;
300 }
301
302 static void swap_buffer(void *bufaddr, int len)
303 {
304 int i;
305 unsigned int *buf = bufaddr;
306
307 for (i = 0; i < len; i += 4, buf++)
308 swab32s(buf);
309 }
310
311 static void swap_buffer2(void *dst_buf, void *src_buf, int len)
312 {
313 int i;
314 unsigned int *src = src_buf;
315 unsigned int *dst = dst_buf;
316
317 for (i = 0; i < len; i += 4, src++, dst++)
318 *dst = swab32p(src);
319 }
320
321 static void fec_dump(struct net_device *ndev)
322 {
323 struct fec_enet_private *fep = netdev_priv(ndev);
324 struct bufdesc *bdp;
325 struct fec_enet_priv_tx_q *txq;
326 int index = 0;
327
328 netdev_info(ndev, "TX ring dump\n");
329 pr_info("Nr SC addr len SKB\n");
330
331 txq = fep->tx_queue[0];
332 bdp = txq->tx_bd_base;
333
334 do {
335 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
336 index,
337 bdp == txq->cur_tx ? 'S' : ' ',
338 bdp == txq->dirty_tx ? 'H' : ' ',
339 fec16_to_cpu(bdp->cbd_sc),
340 fec32_to_cpu(bdp->cbd_bufaddr),
341 fec16_to_cpu(bdp->cbd_datlen),
342 txq->tx_skbuff[index]);
343 bdp = fec_enet_get_nextdesc(bdp, fep, 0);
344 index++;
345 } while (bdp != txq->tx_bd_base);
346 }
347
348 static inline bool is_ipv4_pkt(struct sk_buff *skb)
349 {
350 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
351 }
352
353 static int
354 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
355 {
356 /* Only run for packets requiring a checksum. */
357 if (skb->ip_summed != CHECKSUM_PARTIAL)
358 return 0;
359
360 if (unlikely(skb_cow_head(skb, 0)))
361 return -1;
362
363 if (is_ipv4_pkt(skb))
364 ip_hdr(skb)->check = 0;
365 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
366
367 return 0;
368 }
369
370 static struct bufdesc *
371 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
372 struct sk_buff *skb,
373 struct net_device *ndev)
374 {
375 struct fec_enet_private *fep = netdev_priv(ndev);
376 struct bufdesc *bdp = txq->cur_tx;
377 struct bufdesc_ex *ebdp;
378 int nr_frags = skb_shinfo(skb)->nr_frags;
379 unsigned short queue = skb_get_queue_mapping(skb);
380 int frag, frag_len;
381 unsigned short status;
382 unsigned int estatus = 0;
383 skb_frag_t *this_frag;
384 unsigned int index;
385 void *bufaddr;
386 dma_addr_t addr;
387 int i;
388
389 for (frag = 0; frag < nr_frags; frag++) {
390 this_frag = &skb_shinfo(skb)->frags[frag];
391 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
392 ebdp = (struct bufdesc_ex *)bdp;
393
394 status = fec16_to_cpu(bdp->cbd_sc);
395 status &= ~BD_ENET_TX_STATS;
396 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
397 frag_len = skb_shinfo(skb)->frags[frag].size;
398
399 /* Handle the last BD specially */
400 if (frag == nr_frags - 1) {
401 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
402 if (fep->bufdesc_ex) {
403 estatus |= BD_ENET_TX_INT;
404 if (unlikely(skb_shinfo(skb)->tx_flags &
405 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
406 estatus |= BD_ENET_TX_TS;
407 }
408 }
409
410 if (fep->bufdesc_ex) {
411 if (fep->quirks & FEC_QUIRK_HAS_AVB)
412 estatus |= FEC_TX_BD_FTYPE(queue);
413 if (skb->ip_summed == CHECKSUM_PARTIAL)
414 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
415 ebdp->cbd_bdu = 0;
416 ebdp->cbd_esc = cpu_to_fec32(estatus);
417 }
418
419 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
420
421 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
422 if (((unsigned long) bufaddr) & fep->tx_align ||
423 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
424 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
425 bufaddr = txq->tx_bounce[index];
426
427 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
428 swap_buffer(bufaddr, frag_len);
429 }
430
431 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
432 DMA_TO_DEVICE);
433 if (dma_mapping_error(&fep->pdev->dev, addr)) {
434 dev_kfree_skb_any(skb);
435 if (net_ratelimit())
436 netdev_err(ndev, "Tx DMA memory map failed\n");
437 goto dma_mapping_error;
438 }
439
440 bdp->cbd_bufaddr = cpu_to_fec32(addr);
441 bdp->cbd_datlen = cpu_to_fec16(frag_len);
442 bdp->cbd_sc = cpu_to_fec16(status);
443 }
444
445 return bdp;
446 dma_mapping_error:
447 bdp = txq->cur_tx;
448 for (i = 0; i < frag; i++) {
449 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
450 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
451 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
452 }
453 return ERR_PTR(-ENOMEM);
454 }
455
456 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
457 struct sk_buff *skb, struct net_device *ndev)
458 {
459 struct fec_enet_private *fep = netdev_priv(ndev);
460 int nr_frags = skb_shinfo(skb)->nr_frags;
461 struct bufdesc *bdp, *last_bdp;
462 void *bufaddr;
463 dma_addr_t addr;
464 unsigned short status;
465 unsigned short buflen;
466 unsigned short queue;
467 unsigned int estatus = 0;
468 unsigned int index;
469 int entries_free;
470
471 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
472 if (entries_free < MAX_SKB_FRAGS + 1) {
473 dev_kfree_skb_any(skb);
474 if (net_ratelimit())
475 netdev_err(ndev, "NOT enough BD for SG!\n");
476 return NETDEV_TX_OK;
477 }
478
479 /* Protocol checksum off-load for TCP and UDP. */
480 if (fec_enet_clear_csum(skb, ndev)) {
481 dev_kfree_skb_any(skb);
482 return NETDEV_TX_OK;
483 }
484
485 /* Fill in a Tx ring entry */
486 bdp = txq->cur_tx;
487 last_bdp = bdp;
488 status = fec16_to_cpu(bdp->cbd_sc);
489 status &= ~BD_ENET_TX_STATS;
490
491 /* Set buffer length and buffer pointer */
492 bufaddr = skb->data;
493 buflen = skb_headlen(skb);
494
495 queue = skb_get_queue_mapping(skb);
496 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
497 if (((unsigned long) bufaddr) & fep->tx_align ||
498 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
499 memcpy(txq->tx_bounce[index], skb->data, buflen);
500 bufaddr = txq->tx_bounce[index];
501
502 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
503 swap_buffer(bufaddr, buflen);
504 }
505
506 /* Push the data cache so the CPM does not get stale memory data. */
507 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
508 if (dma_mapping_error(&fep->pdev->dev, addr)) {
509 dev_kfree_skb_any(skb);
510 if (net_ratelimit())
511 netdev_err(ndev, "Tx DMA memory map failed\n");
512 return NETDEV_TX_OK;
513 }
514
515 if (nr_frags) {
516 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
517 if (IS_ERR(last_bdp))
518 return NETDEV_TX_OK;
519 } else {
520 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
521 if (fep->bufdesc_ex) {
522 estatus = BD_ENET_TX_INT;
523 if (unlikely(skb_shinfo(skb)->tx_flags &
524 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
525 estatus |= BD_ENET_TX_TS;
526 }
527 }
528
529 if (fep->bufdesc_ex) {
530
531 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
532
533 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
534 fep->hwts_tx_en))
535 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
536
537 if (fep->quirks & FEC_QUIRK_HAS_AVB)
538 estatus |= FEC_TX_BD_FTYPE(queue);
539
540 if (skb->ip_summed == CHECKSUM_PARTIAL)
541 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
542
543 ebdp->cbd_bdu = 0;
544 ebdp->cbd_esc = cpu_to_fec32(estatus);
545 }
546
547 index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep);
548 /* Save skb pointer */
549 txq->tx_skbuff[index] = skb;
550
551 bdp->cbd_datlen = cpu_to_fec16(buflen);
552 bdp->cbd_bufaddr = cpu_to_fec32(addr);
553
554 /* Send it on its way. Tell FEC it's ready, interrupt when done,
555 * it's the last BD of the frame, and to put the CRC on the end.
556 */
557 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
558 bdp->cbd_sc = cpu_to_fec16(status);
559
560 /* If this was the last BD in the ring, start at the beginning again. */
561 bdp = fec_enet_get_nextdesc(last_bdp, fep, queue);
562
563 skb_tx_timestamp(skb);
564
565 /* Make sure the update to bdp and tx_skbuff are performed before
566 * cur_tx.
567 */
568 wmb();
569 txq->cur_tx = bdp;
570
571 /* Trigger transmission start */
572 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
573
574 return 0;
575 }
576
577 static int
578 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
579 struct net_device *ndev,
580 struct bufdesc *bdp, int index, char *data,
581 int size, bool last_tcp, bool is_last)
582 {
583 struct fec_enet_private *fep = netdev_priv(ndev);
584 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
585 unsigned short queue = skb_get_queue_mapping(skb);
586 unsigned short status;
587 unsigned int estatus = 0;
588 dma_addr_t addr;
589
590 status = fec16_to_cpu(bdp->cbd_sc);
591 status &= ~BD_ENET_TX_STATS;
592
593 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
594
595 if (((unsigned long) data) & fep->tx_align ||
596 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
597 memcpy(txq->tx_bounce[index], data, size);
598 data = txq->tx_bounce[index];
599
600 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
601 swap_buffer(data, size);
602 }
603
604 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
605 if (dma_mapping_error(&fep->pdev->dev, addr)) {
606 dev_kfree_skb_any(skb);
607 if (net_ratelimit())
608 netdev_err(ndev, "Tx DMA memory map failed\n");
609 return NETDEV_TX_BUSY;
610 }
611
612 bdp->cbd_datlen = cpu_to_fec16(size);
613 bdp->cbd_bufaddr = cpu_to_fec32(addr);
614
615 if (fep->bufdesc_ex) {
616 if (fep->quirks & FEC_QUIRK_HAS_AVB)
617 estatus |= FEC_TX_BD_FTYPE(queue);
618 if (skb->ip_summed == CHECKSUM_PARTIAL)
619 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
620 ebdp->cbd_bdu = 0;
621 ebdp->cbd_esc = cpu_to_fec32(estatus);
622 }
623
624 /* Handle the last BD specially */
625 if (last_tcp)
626 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
627 if (is_last) {
628 status |= BD_ENET_TX_INTR;
629 if (fep->bufdesc_ex)
630 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
631 }
632
633 bdp->cbd_sc = cpu_to_fec16(status);
634
635 return 0;
636 }
637
638 static int
639 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
640 struct sk_buff *skb, struct net_device *ndev,
641 struct bufdesc *bdp, int index)
642 {
643 struct fec_enet_private *fep = netdev_priv(ndev);
644 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
645 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
646 unsigned short queue = skb_get_queue_mapping(skb);
647 void *bufaddr;
648 unsigned long dmabuf;
649 unsigned short status;
650 unsigned int estatus = 0;
651
652 status = fec16_to_cpu(bdp->cbd_sc);
653 status &= ~BD_ENET_TX_STATS;
654 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
655
656 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
657 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
658 if (((unsigned long)bufaddr) & fep->tx_align ||
659 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
660 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
661 bufaddr = txq->tx_bounce[index];
662
663 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
664 swap_buffer(bufaddr, hdr_len);
665
666 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
667 hdr_len, DMA_TO_DEVICE);
668 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
669 dev_kfree_skb_any(skb);
670 if (net_ratelimit())
671 netdev_err(ndev, "Tx DMA memory map failed\n");
672 return NETDEV_TX_BUSY;
673 }
674 }
675
676 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
677 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
678
679 if (fep->bufdesc_ex) {
680 if (fep->quirks & FEC_QUIRK_HAS_AVB)
681 estatus |= FEC_TX_BD_FTYPE(queue);
682 if (skb->ip_summed == CHECKSUM_PARTIAL)
683 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
684 ebdp->cbd_bdu = 0;
685 ebdp->cbd_esc = cpu_to_fec32(estatus);
686 }
687
688 bdp->cbd_sc = cpu_to_fec16(status);
689
690 return 0;
691 }
692
693 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
694 struct sk_buff *skb,
695 struct net_device *ndev)
696 {
697 struct fec_enet_private *fep = netdev_priv(ndev);
698 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
699 int total_len, data_left;
700 struct bufdesc *bdp = txq->cur_tx;
701 unsigned short queue = skb_get_queue_mapping(skb);
702 struct tso_t tso;
703 unsigned int index = 0;
704 int ret;
705
706 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) {
707 dev_kfree_skb_any(skb);
708 if (net_ratelimit())
709 netdev_err(ndev, "NOT enough BD for TSO!\n");
710 return NETDEV_TX_OK;
711 }
712
713 /* Protocol checksum off-load for TCP and UDP. */
714 if (fec_enet_clear_csum(skb, ndev)) {
715 dev_kfree_skb_any(skb);
716 return NETDEV_TX_OK;
717 }
718
719 /* Initialize the TSO handler, and prepare the first payload */
720 tso_start(skb, &tso);
721
722 total_len = skb->len - hdr_len;
723 while (total_len > 0) {
724 char *hdr;
725
726 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
727 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
728 total_len -= data_left;
729
730 /* prepare packet headers: MAC + IP + TCP */
731 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
732 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
733 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
734 if (ret)
735 goto err_release;
736
737 while (data_left > 0) {
738 int size;
739
740 size = min_t(int, tso.size, data_left);
741 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
742 index = fec_enet_get_bd_index(txq->tx_bd_base,
743 bdp, fep);
744 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
745 bdp, index,
746 tso.data, size,
747 size == data_left,
748 total_len == 0);
749 if (ret)
750 goto err_release;
751
752 data_left -= size;
753 tso_build_data(skb, &tso, size);
754 }
755
756 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
757 }
758
759 /* Save skb pointer */
760 txq->tx_skbuff[index] = skb;
761
762 skb_tx_timestamp(skb);
763 txq->cur_tx = bdp;
764
765 /* Trigger transmission start */
766 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
767 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
768 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
769 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
770 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)))
771 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
772
773 return 0;
774
775 err_release:
776 /* TODO: Release all used data descriptors for TSO */
777 return ret;
778 }
779
780 static netdev_tx_t
781 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
782 {
783 struct fec_enet_private *fep = netdev_priv(ndev);
784 int entries_free;
785 unsigned short queue;
786 struct fec_enet_priv_tx_q *txq;
787 struct netdev_queue *nq;
788 int ret;
789
790 queue = skb_get_queue_mapping(skb);
791 txq = fep->tx_queue[queue];
792 nq = netdev_get_tx_queue(ndev, queue);
793
794 if (skb_is_gso(skb))
795 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
796 else
797 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
798 if (ret)
799 return ret;
800
801 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
802 if (entries_free <= txq->tx_stop_threshold)
803 netif_tx_stop_queue(nq);
804
805 return NETDEV_TX_OK;
806 }
807
808 /* Init RX & TX buffer descriptors
809 */
810 static void fec_enet_bd_init(struct net_device *dev)
811 {
812 struct fec_enet_private *fep = netdev_priv(dev);
813 struct fec_enet_priv_tx_q *txq;
814 struct fec_enet_priv_rx_q *rxq;
815 struct bufdesc *bdp;
816 unsigned int i;
817 unsigned int q;
818
819 for (q = 0; q < fep->num_rx_queues; q++) {
820 /* Initialize the receive buffer descriptors. */
821 rxq = fep->rx_queue[q];
822 bdp = rxq->rx_bd_base;
823
824 for (i = 0; i < rxq->rx_ring_size; i++) {
825
826 /* Initialize the BD for every fragment in the page. */
827 if (bdp->cbd_bufaddr)
828 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
829 else
830 bdp->cbd_sc = cpu_to_fec16(0);
831 bdp = fec_enet_get_nextdesc(bdp, fep, q);
832 }
833
834 /* Set the last buffer to wrap */
835 bdp = fec_enet_get_prevdesc(bdp, fep, q);
836 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
837
838 rxq->cur_rx = rxq->rx_bd_base;
839 }
840
841 for (q = 0; q < fep->num_tx_queues; q++) {
842 /* ...and the same for transmit */
843 txq = fep->tx_queue[q];
844 bdp = txq->tx_bd_base;
845 txq->cur_tx = bdp;
846
847 for (i = 0; i < txq->tx_ring_size; i++) {
848 /* Initialize the BD for every fragment in the page. */
849 bdp->cbd_sc = cpu_to_fec16(0);
850 if (txq->tx_skbuff[i]) {
851 dev_kfree_skb_any(txq->tx_skbuff[i]);
852 txq->tx_skbuff[i] = NULL;
853 }
854 bdp->cbd_bufaddr = cpu_to_fec32(0);
855 bdp = fec_enet_get_nextdesc(bdp, fep, q);
856 }
857
858 /* Set the last buffer to wrap */
859 bdp = fec_enet_get_prevdesc(bdp, fep, q);
860 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
861 txq->dirty_tx = bdp;
862 }
863 }
864
865 static void fec_enet_active_rxring(struct net_device *ndev)
866 {
867 struct fec_enet_private *fep = netdev_priv(ndev);
868 int i;
869
870 for (i = 0; i < fep->num_rx_queues; i++)
871 writel(0, fep->hwp + FEC_R_DES_ACTIVE(i));
872 }
873
874 static void fec_enet_enable_ring(struct net_device *ndev)
875 {
876 struct fec_enet_private *fep = netdev_priv(ndev);
877 struct fec_enet_priv_tx_q *txq;
878 struct fec_enet_priv_rx_q *rxq;
879 int i;
880
881 for (i = 0; i < fep->num_rx_queues; i++) {
882 rxq = fep->rx_queue[i];
883 writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i));
884 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
885
886 /* enable DMA1/2 */
887 if (i)
888 writel(RCMR_MATCHEN | RCMR_CMP(i),
889 fep->hwp + FEC_RCMR(i));
890 }
891
892 for (i = 0; i < fep->num_tx_queues; i++) {
893 txq = fep->tx_queue[i];
894 writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i));
895
896 /* enable DMA1/2 */
897 if (i)
898 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
899 fep->hwp + FEC_DMA_CFG(i));
900 }
901 }
902
903 static void fec_enet_reset_skb(struct net_device *ndev)
904 {
905 struct fec_enet_private *fep = netdev_priv(ndev);
906 struct fec_enet_priv_tx_q *txq;
907 int i, j;
908
909 for (i = 0; i < fep->num_tx_queues; i++) {
910 txq = fep->tx_queue[i];
911
912 for (j = 0; j < txq->tx_ring_size; j++) {
913 if (txq->tx_skbuff[j]) {
914 dev_kfree_skb_any(txq->tx_skbuff[j]);
915 txq->tx_skbuff[j] = NULL;
916 }
917 }
918 }
919 }
920
921 /*
922 * This function is called to start or restart the FEC during a link
923 * change, transmit timeout, or to reconfigure the FEC. The network
924 * packet processing for this device must be stopped before this call.
925 */
926 static void
927 fec_restart(struct net_device *ndev)
928 {
929 struct fec_enet_private *fep = netdev_priv(ndev);
930 u32 val;
931 u32 temp_mac[2];
932 u32 rcntl = OPT_FRAME_SIZE | 0x04;
933 u32 ecntl = 0x2; /* ETHEREN */
934
935 /* Whack a reset. We should wait for this.
936 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
937 * instead of reset MAC itself.
938 */
939 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
940 writel(0, fep->hwp + FEC_ECNTRL);
941 } else {
942 writel(1, fep->hwp + FEC_ECNTRL);
943 udelay(10);
944 }
945
946 /*
947 * enet-mac reset will reset mac address registers too,
948 * so need to reconfigure it.
949 */
950 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
951 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
952 writel((__force u32)cpu_to_be32(temp_mac[0]),
953 fep->hwp + FEC_ADDR_LOW);
954 writel((__force u32)cpu_to_be32(temp_mac[1]),
955 fep->hwp + FEC_ADDR_HIGH);
956 }
957
958 /* Clear any outstanding interrupt. */
959 writel(0xffffffff, fep->hwp + FEC_IEVENT);
960
961 fec_enet_bd_init(ndev);
962
963 fec_enet_enable_ring(ndev);
964
965 /* Reset tx SKB buffers. */
966 fec_enet_reset_skb(ndev);
967
968 /* Enable MII mode */
969 if (fep->full_duplex == DUPLEX_FULL) {
970 /* FD enable */
971 writel(0x04, fep->hwp + FEC_X_CNTRL);
972 } else {
973 /* No Rcv on Xmit */
974 rcntl |= 0x02;
975 writel(0x0, fep->hwp + FEC_X_CNTRL);
976 }
977
978 /* Set MII speed */
979 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
980
981 #if !defined(CONFIG_M5272)
982 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
983 /* set RX checksum */
984 val = readl(fep->hwp + FEC_RACC);
985 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
986 val |= FEC_RACC_OPTIONS;
987 else
988 val &= ~FEC_RACC_OPTIONS;
989 writel(val, fep->hwp + FEC_RACC);
990 }
991 #endif
992
993 /*
994 * The phy interface and speed need to get configured
995 * differently on enet-mac.
996 */
997 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
998 /* Enable flow control and length check */
999 rcntl |= 0x40000000 | 0x00000020;
1000
1001 /* RGMII, RMII or MII */
1002 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
1003 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1004 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
1005 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
1006 rcntl |= (1 << 6);
1007 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1008 rcntl |= (1 << 8);
1009 else
1010 rcntl &= ~(1 << 8);
1011
1012 /* 1G, 100M or 10M */
1013 if (fep->phy_dev) {
1014 if (fep->phy_dev->speed == SPEED_1000)
1015 ecntl |= (1 << 5);
1016 else if (fep->phy_dev->speed == SPEED_100)
1017 rcntl &= ~(1 << 9);
1018 else
1019 rcntl |= (1 << 9);
1020 }
1021 } else {
1022 #ifdef FEC_MIIGSK_ENR
1023 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1024 u32 cfgr;
1025 /* disable the gasket and wait */
1026 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1027 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1028 udelay(1);
1029
1030 /*
1031 * configure the gasket:
1032 * RMII, 50 MHz, no loopback, no echo
1033 * MII, 25 MHz, no loopback, no echo
1034 */
1035 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1036 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1037 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
1038 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1039 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1040
1041 /* re-enable the gasket */
1042 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1043 }
1044 #endif
1045 }
1046
1047 #if !defined(CONFIG_M5272)
1048 /* enable pause frame*/
1049 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1050 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1051 fep->phy_dev && fep->phy_dev->pause)) {
1052 rcntl |= FEC_ENET_FCE;
1053
1054 /* set FIFO threshold parameter to reduce overrun */
1055 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1056 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1057 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1058 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1059
1060 /* OPD */
1061 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1062 } else {
1063 rcntl &= ~FEC_ENET_FCE;
1064 }
1065 #endif /* !defined(CONFIG_M5272) */
1066
1067 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1068
1069 /* Setup multicast filter. */
1070 set_multicast_list(ndev);
1071 #ifndef CONFIG_M5272
1072 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1073 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1074 #endif
1075
1076 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1077 /* enable ENET endian swap */
1078 ecntl |= (1 << 8);
1079 /* enable ENET store and forward mode */
1080 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1081 }
1082
1083 if (fep->bufdesc_ex)
1084 ecntl |= (1 << 4);
1085
1086 #ifndef CONFIG_M5272
1087 /* Enable the MIB statistic event counters */
1088 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1089 #endif
1090
1091 /* And last, enable the transmit and receive processing */
1092 writel(ecntl, fep->hwp + FEC_ECNTRL);
1093 fec_enet_active_rxring(ndev);
1094
1095 if (fep->bufdesc_ex)
1096 fec_ptp_start_cyclecounter(ndev);
1097
1098 /* Enable interrupts we wish to service */
1099 if (fep->link)
1100 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1101 else
1102 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1103
1104 /* Init the interrupt coalescing */
1105 fec_enet_itr_coal_init(ndev);
1106
1107 }
1108
1109 static void
1110 fec_stop(struct net_device *ndev)
1111 {
1112 struct fec_enet_private *fep = netdev_priv(ndev);
1113 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1114 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1115 u32 val;
1116
1117 /* We cannot expect a graceful transmit stop without link !!! */
1118 if (fep->link) {
1119 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1120 udelay(10);
1121 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1122 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1123 }
1124
1125 /* Whack a reset. We should wait for this.
1126 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1127 * instead of reset MAC itself.
1128 */
1129 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1130 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1131 writel(0, fep->hwp + FEC_ECNTRL);
1132 } else {
1133 writel(1, fep->hwp + FEC_ECNTRL);
1134 udelay(10);
1135 }
1136 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1137 } else {
1138 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1139 val = readl(fep->hwp + FEC_ECNTRL);
1140 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1141 writel(val, fep->hwp + FEC_ECNTRL);
1142
1143 if (pdata && pdata->sleep_mode_enable)
1144 pdata->sleep_mode_enable(true);
1145 }
1146 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1147
1148 /* We have to keep ENET enabled to have MII interrupt stay working */
1149 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1150 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1151 writel(2, fep->hwp + FEC_ECNTRL);
1152 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1153 }
1154 }
1155
1156
1157 static void
1158 fec_timeout(struct net_device *ndev)
1159 {
1160 struct fec_enet_private *fep = netdev_priv(ndev);
1161
1162 fec_dump(ndev);
1163
1164 ndev->stats.tx_errors++;
1165
1166 schedule_work(&fep->tx_timeout_work);
1167 }
1168
1169 static void fec_enet_timeout_work(struct work_struct *work)
1170 {
1171 struct fec_enet_private *fep =
1172 container_of(work, struct fec_enet_private, tx_timeout_work);
1173 struct net_device *ndev = fep->netdev;
1174
1175 rtnl_lock();
1176 if (netif_device_present(ndev) || netif_running(ndev)) {
1177 napi_disable(&fep->napi);
1178 netif_tx_lock_bh(ndev);
1179 fec_restart(ndev);
1180 netif_wake_queue(ndev);
1181 netif_tx_unlock_bh(ndev);
1182 napi_enable(&fep->napi);
1183 }
1184 rtnl_unlock();
1185 }
1186
1187 static void
1188 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1189 struct skb_shared_hwtstamps *hwtstamps)
1190 {
1191 unsigned long flags;
1192 u64 ns;
1193
1194 spin_lock_irqsave(&fep->tmreg_lock, flags);
1195 ns = timecounter_cyc2time(&fep->tc, ts);
1196 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1197
1198 memset(hwtstamps, 0, sizeof(*hwtstamps));
1199 hwtstamps->hwtstamp = ns_to_ktime(ns);
1200 }
1201
1202 static void
1203 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1204 {
1205 struct fec_enet_private *fep;
1206 struct bufdesc *bdp;
1207 unsigned short status;
1208 struct sk_buff *skb;
1209 struct fec_enet_priv_tx_q *txq;
1210 struct netdev_queue *nq;
1211 int index = 0;
1212 int entries_free;
1213
1214 fep = netdev_priv(ndev);
1215
1216 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1217
1218 txq = fep->tx_queue[queue_id];
1219 /* get next bdp of dirty_tx */
1220 nq = netdev_get_tx_queue(ndev, queue_id);
1221 bdp = txq->dirty_tx;
1222
1223 /* get next bdp of dirty_tx */
1224 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1225
1226 while (bdp != READ_ONCE(txq->cur_tx)) {
1227 /* Order the load of cur_tx and cbd_sc */
1228 rmb();
1229 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1230 if (status & BD_ENET_TX_READY)
1231 break;
1232
1233 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
1234
1235 skb = txq->tx_skbuff[index];
1236 txq->tx_skbuff[index] = NULL;
1237 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1238 dma_unmap_single(&fep->pdev->dev,
1239 fec32_to_cpu(bdp->cbd_bufaddr),
1240 fec16_to_cpu(bdp->cbd_datlen),
1241 DMA_TO_DEVICE);
1242 bdp->cbd_bufaddr = cpu_to_fec32(0);
1243 if (!skb) {
1244 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1245 continue;
1246 }
1247
1248 /* Check for errors. */
1249 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1250 BD_ENET_TX_RL | BD_ENET_TX_UN |
1251 BD_ENET_TX_CSL)) {
1252 ndev->stats.tx_errors++;
1253 if (status & BD_ENET_TX_HB) /* No heartbeat */
1254 ndev->stats.tx_heartbeat_errors++;
1255 if (status & BD_ENET_TX_LC) /* Late collision */
1256 ndev->stats.tx_window_errors++;
1257 if (status & BD_ENET_TX_RL) /* Retrans limit */
1258 ndev->stats.tx_aborted_errors++;
1259 if (status & BD_ENET_TX_UN) /* Underrun */
1260 ndev->stats.tx_fifo_errors++;
1261 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1262 ndev->stats.tx_carrier_errors++;
1263 } else {
1264 ndev->stats.tx_packets++;
1265 ndev->stats.tx_bytes += skb->len;
1266 }
1267
1268 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1269 fep->bufdesc_ex) {
1270 struct skb_shared_hwtstamps shhwtstamps;
1271 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1272
1273 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1274 skb_tstamp_tx(skb, &shhwtstamps);
1275 }
1276
1277 /* Deferred means some collisions occurred during transmit,
1278 * but we eventually sent the packet OK.
1279 */
1280 if (status & BD_ENET_TX_DEF)
1281 ndev->stats.collisions++;
1282
1283 /* Free the sk buffer associated with this last transmit */
1284 dev_kfree_skb_any(skb);
1285
1286 /* Make sure the update to bdp and tx_skbuff are performed
1287 * before dirty_tx
1288 */
1289 wmb();
1290 txq->dirty_tx = bdp;
1291
1292 /* Update pointer to next buffer descriptor to be transmitted */
1293 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1294
1295 /* Since we have freed up a buffer, the ring is no longer full
1296 */
1297 if (netif_queue_stopped(ndev)) {
1298 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
1299 if (entries_free >= txq->tx_wake_threshold)
1300 netif_tx_wake_queue(nq);
1301 }
1302 }
1303
1304 /* ERR006538: Keep the transmitter going */
1305 if (bdp != txq->cur_tx &&
1306 readl(fep->hwp + FEC_X_DES_ACTIVE(queue_id)) == 0)
1307 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue_id));
1308 }
1309
1310 static void
1311 fec_enet_tx(struct net_device *ndev)
1312 {
1313 struct fec_enet_private *fep = netdev_priv(ndev);
1314 u16 queue_id;
1315 /* First process class A queue, then Class B and Best Effort queue */
1316 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1317 clear_bit(queue_id, &fep->work_tx);
1318 fec_enet_tx_queue(ndev, queue_id);
1319 }
1320 return;
1321 }
1322
1323 static int
1324 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1325 {
1326 struct fec_enet_private *fep = netdev_priv(ndev);
1327 int off;
1328
1329 off = ((unsigned long)skb->data) & fep->rx_align;
1330 if (off)
1331 skb_reserve(skb, fep->rx_align + 1 - off);
1332
1333 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE));
1334 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) {
1335 if (net_ratelimit())
1336 netdev_err(ndev, "Rx DMA memory map failed\n");
1337 return -ENOMEM;
1338 }
1339
1340 return 0;
1341 }
1342
1343 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1344 struct bufdesc *bdp, u32 length, bool swap)
1345 {
1346 struct fec_enet_private *fep = netdev_priv(ndev);
1347 struct sk_buff *new_skb;
1348
1349 if (length > fep->rx_copybreak)
1350 return false;
1351
1352 new_skb = netdev_alloc_skb(ndev, length);
1353 if (!new_skb)
1354 return false;
1355
1356 dma_sync_single_for_cpu(&fep->pdev->dev,
1357 fec32_to_cpu(bdp->cbd_bufaddr),
1358 FEC_ENET_RX_FRSIZE - fep->rx_align,
1359 DMA_FROM_DEVICE);
1360 if (!swap)
1361 memcpy(new_skb->data, (*skb)->data, length);
1362 else
1363 swap_buffer2(new_skb->data, (*skb)->data, length);
1364 *skb = new_skb;
1365
1366 return true;
1367 }
1368
1369 /* During a receive, the cur_rx points to the current incoming buffer.
1370 * When we update through the ring, if the next incoming buffer has
1371 * not been given to the system, we just set the empty indicator,
1372 * effectively tossing the packet.
1373 */
1374 static int
1375 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1376 {
1377 struct fec_enet_private *fep = netdev_priv(ndev);
1378 struct fec_enet_priv_rx_q *rxq;
1379 struct bufdesc *bdp;
1380 unsigned short status;
1381 struct sk_buff *skb_new = NULL;
1382 struct sk_buff *skb;
1383 ushort pkt_len;
1384 __u8 *data;
1385 int pkt_received = 0;
1386 struct bufdesc_ex *ebdp = NULL;
1387 bool vlan_packet_rcvd = false;
1388 u16 vlan_tag;
1389 int index = 0;
1390 bool is_copybreak;
1391 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1392
1393 #ifdef CONFIG_M532x
1394 flush_cache_all();
1395 #endif
1396 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1397 rxq = fep->rx_queue[queue_id];
1398
1399 /* First, grab all of the stats for the incoming packet.
1400 * These get messed up if we get called due to a busy condition.
1401 */
1402 bdp = rxq->cur_rx;
1403
1404 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1405
1406 if (pkt_received >= budget)
1407 break;
1408 pkt_received++;
1409
1410 /* Since we have allocated space to hold a complete frame,
1411 * the last indicator should be set.
1412 */
1413 if ((status & BD_ENET_RX_LAST) == 0)
1414 netdev_err(ndev, "rcv is not +last\n");
1415
1416 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
1417
1418 /* Check for errors. */
1419 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1420 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
1421 ndev->stats.rx_errors++;
1422 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1423 /* Frame too long or too short. */
1424 ndev->stats.rx_length_errors++;
1425 }
1426 if (status & BD_ENET_RX_NO) /* Frame alignment */
1427 ndev->stats.rx_frame_errors++;
1428 if (status & BD_ENET_RX_CR) /* CRC Error */
1429 ndev->stats.rx_crc_errors++;
1430 if (status & BD_ENET_RX_OV) /* FIFO overrun */
1431 ndev->stats.rx_fifo_errors++;
1432 }
1433
1434 /* Report late collisions as a frame error.
1435 * On this error, the BD is closed, but we don't know what we
1436 * have in the buffer. So, just drop this frame on the floor.
1437 */
1438 if (status & BD_ENET_RX_CL) {
1439 ndev->stats.rx_errors++;
1440 ndev->stats.rx_frame_errors++;
1441 goto rx_processing_done;
1442 }
1443
1444 /* Process the incoming frame. */
1445 ndev->stats.rx_packets++;
1446 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1447 ndev->stats.rx_bytes += pkt_len;
1448
1449 index = fec_enet_get_bd_index(rxq->rx_bd_base, bdp, fep);
1450 skb = rxq->rx_skbuff[index];
1451
1452 /* The packet length includes FCS, but we don't want to
1453 * include that when passing upstream as it messes up
1454 * bridging applications.
1455 */
1456 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1457 need_swap);
1458 if (!is_copybreak) {
1459 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1460 if (unlikely(!skb_new)) {
1461 ndev->stats.rx_dropped++;
1462 goto rx_processing_done;
1463 }
1464 dma_unmap_single(&fep->pdev->dev,
1465 fec32_to_cpu(bdp->cbd_bufaddr),
1466 FEC_ENET_RX_FRSIZE - fep->rx_align,
1467 DMA_FROM_DEVICE);
1468 }
1469
1470 prefetch(skb->data - NET_IP_ALIGN);
1471 skb_put(skb, pkt_len - 4);
1472 data = skb->data;
1473 if (!is_copybreak && need_swap)
1474 swap_buffer(data, pkt_len);
1475
1476 /* Extract the enhanced buffer descriptor */
1477 ebdp = NULL;
1478 if (fep->bufdesc_ex)
1479 ebdp = (struct bufdesc_ex *)bdp;
1480
1481 /* If this is a VLAN packet remove the VLAN Tag */
1482 vlan_packet_rcvd = false;
1483 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1484 fep->bufdesc_ex &&
1485 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1486 /* Push and remove the vlan tag */
1487 struct vlan_hdr *vlan_header =
1488 (struct vlan_hdr *) (data + ETH_HLEN);
1489 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1490
1491 vlan_packet_rcvd = true;
1492
1493 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1494 skb_pull(skb, VLAN_HLEN);
1495 }
1496
1497 skb->protocol = eth_type_trans(skb, ndev);
1498
1499 /* Get receive timestamp from the skb */
1500 if (fep->hwts_rx_en && fep->bufdesc_ex)
1501 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1502 skb_hwtstamps(skb));
1503
1504 if (fep->bufdesc_ex &&
1505 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1506 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1507 /* don't check it */
1508 skb->ip_summed = CHECKSUM_UNNECESSARY;
1509 } else {
1510 skb_checksum_none_assert(skb);
1511 }
1512 }
1513
1514 /* Handle received VLAN packets */
1515 if (vlan_packet_rcvd)
1516 __vlan_hwaccel_put_tag(skb,
1517 htons(ETH_P_8021Q),
1518 vlan_tag);
1519
1520 napi_gro_receive(&fep->napi, skb);
1521
1522 if (is_copybreak) {
1523 dma_sync_single_for_device(&fep->pdev->dev,
1524 fec32_to_cpu(bdp->cbd_bufaddr),
1525 FEC_ENET_RX_FRSIZE - fep->rx_align,
1526 DMA_FROM_DEVICE);
1527 } else {
1528 rxq->rx_skbuff[index] = skb_new;
1529 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1530 }
1531
1532 rx_processing_done:
1533 /* Clear the status flags for this buffer */
1534 status &= ~BD_ENET_RX_STATS;
1535
1536 /* Mark the buffer empty */
1537 status |= BD_ENET_RX_EMPTY;
1538 bdp->cbd_sc = cpu_to_fec16(status);
1539
1540 if (fep->bufdesc_ex) {
1541 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1542
1543 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1544 ebdp->cbd_prot = 0;
1545 ebdp->cbd_bdu = 0;
1546 }
1547
1548 /* Update BD pointer to next entry */
1549 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1550
1551 /* Doing this here will keep the FEC running while we process
1552 * incoming frames. On a heavily loaded network, we should be
1553 * able to keep up at the expense of system resources.
1554 */
1555 writel(0, fep->hwp + FEC_R_DES_ACTIVE(queue_id));
1556 }
1557 rxq->cur_rx = bdp;
1558 return pkt_received;
1559 }
1560
1561 static int
1562 fec_enet_rx(struct net_device *ndev, int budget)
1563 {
1564 int pkt_received = 0;
1565 u16 queue_id;
1566 struct fec_enet_private *fep = netdev_priv(ndev);
1567
1568 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1569 clear_bit(queue_id, &fep->work_rx);
1570 pkt_received += fec_enet_rx_queue(ndev,
1571 budget - pkt_received, queue_id);
1572 }
1573 return pkt_received;
1574 }
1575
1576 static bool
1577 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1578 {
1579 if (int_events == 0)
1580 return false;
1581
1582 if (int_events & FEC_ENET_RXF)
1583 fep->work_rx |= (1 << 2);
1584 if (int_events & FEC_ENET_RXF_1)
1585 fep->work_rx |= (1 << 0);
1586 if (int_events & FEC_ENET_RXF_2)
1587 fep->work_rx |= (1 << 1);
1588
1589 if (int_events & FEC_ENET_TXF)
1590 fep->work_tx |= (1 << 2);
1591 if (int_events & FEC_ENET_TXF_1)
1592 fep->work_tx |= (1 << 0);
1593 if (int_events & FEC_ENET_TXF_2)
1594 fep->work_tx |= (1 << 1);
1595
1596 return true;
1597 }
1598
1599 static irqreturn_t
1600 fec_enet_interrupt(int irq, void *dev_id)
1601 {
1602 struct net_device *ndev = dev_id;
1603 struct fec_enet_private *fep = netdev_priv(ndev);
1604 uint int_events;
1605 irqreturn_t ret = IRQ_NONE;
1606
1607 int_events = readl(fep->hwp + FEC_IEVENT);
1608 writel(int_events, fep->hwp + FEC_IEVENT);
1609 fec_enet_collect_events(fep, int_events);
1610
1611 if ((fep->work_tx || fep->work_rx) && fep->link) {
1612 ret = IRQ_HANDLED;
1613
1614 if (napi_schedule_prep(&fep->napi)) {
1615 /* Disable the NAPI interrupts */
1616 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1617 __napi_schedule(&fep->napi);
1618 }
1619 }
1620
1621 if (int_events & FEC_ENET_MII) {
1622 ret = IRQ_HANDLED;
1623 complete(&fep->mdio_done);
1624 }
1625
1626 if (fep->ptp_clock)
1627 fec_ptp_check_pps_event(fep);
1628
1629 return ret;
1630 }
1631
1632 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1633 {
1634 struct net_device *ndev = napi->dev;
1635 struct fec_enet_private *fep = netdev_priv(ndev);
1636 int pkts;
1637
1638 pkts = fec_enet_rx(ndev, budget);
1639
1640 fec_enet_tx(ndev);
1641
1642 if (pkts < budget) {
1643 napi_complete(napi);
1644 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1645 }
1646 return pkts;
1647 }
1648
1649 /* ------------------------------------------------------------------------- */
1650 static void fec_get_mac(struct net_device *ndev)
1651 {
1652 struct fec_enet_private *fep = netdev_priv(ndev);
1653 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1654 unsigned char *iap, tmpaddr[ETH_ALEN];
1655
1656 /*
1657 * try to get mac address in following order:
1658 *
1659 * 1) module parameter via kernel command line in form
1660 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1661 */
1662 iap = macaddr;
1663
1664 /*
1665 * 2) from device tree data
1666 */
1667 if (!is_valid_ether_addr(iap)) {
1668 struct device_node *np = fep->pdev->dev.of_node;
1669 if (np) {
1670 const char *mac = of_get_mac_address(np);
1671 if (mac)
1672 iap = (unsigned char *) mac;
1673 }
1674 }
1675
1676 /*
1677 * 3) from flash or fuse (via platform data)
1678 */
1679 if (!is_valid_ether_addr(iap)) {
1680 #ifdef CONFIG_M5272
1681 if (FEC_FLASHMAC)
1682 iap = (unsigned char *)FEC_FLASHMAC;
1683 #else
1684 if (pdata)
1685 iap = (unsigned char *)&pdata->mac;
1686 #endif
1687 }
1688
1689 /*
1690 * 4) FEC mac registers set by bootloader
1691 */
1692 if (!is_valid_ether_addr(iap)) {
1693 *((__be32 *) &tmpaddr[0]) =
1694 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1695 *((__be16 *) &tmpaddr[4]) =
1696 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1697 iap = &tmpaddr[0];
1698 }
1699
1700 /*
1701 * 5) random mac address
1702 */
1703 if (!is_valid_ether_addr(iap)) {
1704 /* Report it and use a random ethernet address instead */
1705 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1706 eth_hw_addr_random(ndev);
1707 netdev_info(ndev, "Using random MAC address: %pM\n",
1708 ndev->dev_addr);
1709 return;
1710 }
1711
1712 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1713
1714 /* Adjust MAC if using macaddr */
1715 if (iap == macaddr)
1716 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1717 }
1718
1719 /* ------------------------------------------------------------------------- */
1720
1721 /*
1722 * Phy section
1723 */
1724 static void fec_enet_adjust_link(struct net_device *ndev)
1725 {
1726 struct fec_enet_private *fep = netdev_priv(ndev);
1727 struct phy_device *phy_dev = fep->phy_dev;
1728 int status_change = 0;
1729
1730 /* Prevent a state halted on mii error */
1731 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1732 phy_dev->state = PHY_RESUMING;
1733 return;
1734 }
1735
1736 /*
1737 * If the netdev is down, or is going down, we're not interested
1738 * in link state events, so just mark our idea of the link as down
1739 * and ignore the event.
1740 */
1741 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1742 fep->link = 0;
1743 } else if (phy_dev->link) {
1744 if (!fep->link) {
1745 fep->link = phy_dev->link;
1746 status_change = 1;
1747 }
1748
1749 if (fep->full_duplex != phy_dev->duplex) {
1750 fep->full_duplex = phy_dev->duplex;
1751 status_change = 1;
1752 }
1753
1754 if (phy_dev->speed != fep->speed) {
1755 fep->speed = phy_dev->speed;
1756 status_change = 1;
1757 }
1758
1759 /* if any of the above changed restart the FEC */
1760 if (status_change) {
1761 napi_disable(&fep->napi);
1762 netif_tx_lock_bh(ndev);
1763 fec_restart(ndev);
1764 netif_wake_queue(ndev);
1765 netif_tx_unlock_bh(ndev);
1766 napi_enable(&fep->napi);
1767 }
1768 } else {
1769 if (fep->link) {
1770 napi_disable(&fep->napi);
1771 netif_tx_lock_bh(ndev);
1772 fec_stop(ndev);
1773 netif_tx_unlock_bh(ndev);
1774 napi_enable(&fep->napi);
1775 fep->link = phy_dev->link;
1776 status_change = 1;
1777 }
1778 }
1779
1780 if (status_change)
1781 phy_print_status(phy_dev);
1782 }
1783
1784 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1785 {
1786 struct fec_enet_private *fep = bus->priv;
1787 struct device *dev = &fep->pdev->dev;
1788 unsigned long time_left;
1789 int ret = 0;
1790
1791 ret = pm_runtime_get_sync(dev);
1792 if (ret < 0)
1793 return ret;
1794
1795 fep->mii_timeout = 0;
1796 reinit_completion(&fep->mdio_done);
1797
1798 /* start a read op */
1799 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1800 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1801 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1802
1803 /* wait for end of transfer */
1804 time_left = wait_for_completion_timeout(&fep->mdio_done,
1805 usecs_to_jiffies(FEC_MII_TIMEOUT));
1806 if (time_left == 0) {
1807 fep->mii_timeout = 1;
1808 netdev_err(fep->netdev, "MDIO read timeout\n");
1809 ret = -ETIMEDOUT;
1810 goto out;
1811 }
1812
1813 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1814
1815 out:
1816 pm_runtime_mark_last_busy(dev);
1817 pm_runtime_put_autosuspend(dev);
1818
1819 return ret;
1820 }
1821
1822 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1823 u16 value)
1824 {
1825 struct fec_enet_private *fep = bus->priv;
1826 struct device *dev = &fep->pdev->dev;
1827 unsigned long time_left;
1828 int ret;
1829
1830 ret = pm_runtime_get_sync(dev);
1831 if (ret < 0)
1832 return ret;
1833 else
1834 ret = 0;
1835
1836 fep->mii_timeout = 0;
1837 reinit_completion(&fep->mdio_done);
1838
1839 /* start a write op */
1840 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1841 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1842 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1843 fep->hwp + FEC_MII_DATA);
1844
1845 /* wait for end of transfer */
1846 time_left = wait_for_completion_timeout(&fep->mdio_done,
1847 usecs_to_jiffies(FEC_MII_TIMEOUT));
1848 if (time_left == 0) {
1849 fep->mii_timeout = 1;
1850 netdev_err(fep->netdev, "MDIO write timeout\n");
1851 ret = -ETIMEDOUT;
1852 }
1853
1854 pm_runtime_mark_last_busy(dev);
1855 pm_runtime_put_autosuspend(dev);
1856
1857 return ret;
1858 }
1859
1860 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1861 {
1862 struct fec_enet_private *fep = netdev_priv(ndev);
1863 int ret;
1864
1865 if (enable) {
1866 ret = clk_prepare_enable(fep->clk_ahb);
1867 if (ret)
1868 return ret;
1869 if (fep->clk_enet_out) {
1870 ret = clk_prepare_enable(fep->clk_enet_out);
1871 if (ret)
1872 goto failed_clk_enet_out;
1873 }
1874 if (fep->clk_ptp) {
1875 mutex_lock(&fep->ptp_clk_mutex);
1876 ret = clk_prepare_enable(fep->clk_ptp);
1877 if (ret) {
1878 mutex_unlock(&fep->ptp_clk_mutex);
1879 goto failed_clk_ptp;
1880 } else {
1881 fep->ptp_clk_on = true;
1882 }
1883 mutex_unlock(&fep->ptp_clk_mutex);
1884 }
1885 if (fep->clk_ref) {
1886 ret = clk_prepare_enable(fep->clk_ref);
1887 if (ret)
1888 goto failed_clk_ref;
1889 }
1890 } else {
1891 clk_disable_unprepare(fep->clk_ahb);
1892 if (fep->clk_enet_out)
1893 clk_disable_unprepare(fep->clk_enet_out);
1894 if (fep->clk_ptp) {
1895 mutex_lock(&fep->ptp_clk_mutex);
1896 clk_disable_unprepare(fep->clk_ptp);
1897 fep->ptp_clk_on = false;
1898 mutex_unlock(&fep->ptp_clk_mutex);
1899 }
1900 if (fep->clk_ref)
1901 clk_disable_unprepare(fep->clk_ref);
1902 }
1903
1904 return 0;
1905
1906 failed_clk_ref:
1907 if (fep->clk_ref)
1908 clk_disable_unprepare(fep->clk_ref);
1909 failed_clk_ptp:
1910 if (fep->clk_enet_out)
1911 clk_disable_unprepare(fep->clk_enet_out);
1912 failed_clk_enet_out:
1913 clk_disable_unprepare(fep->clk_ahb);
1914
1915 return ret;
1916 }
1917
1918 static int fec_enet_mii_probe(struct net_device *ndev)
1919 {
1920 struct fec_enet_private *fep = netdev_priv(ndev);
1921 struct phy_device *phy_dev = NULL;
1922 char mdio_bus_id[MII_BUS_ID_SIZE];
1923 char phy_name[MII_BUS_ID_SIZE + 3];
1924 int phy_id;
1925 int dev_id = fep->dev_id;
1926
1927 fep->phy_dev = NULL;
1928
1929 if (fep->phy_node) {
1930 phy_dev = of_phy_connect(ndev, fep->phy_node,
1931 &fec_enet_adjust_link, 0,
1932 fep->phy_interface);
1933 if (!phy_dev)
1934 return -ENODEV;
1935 } else {
1936 /* check for attached phy */
1937 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1938 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
1939 continue;
1940 if (dev_id--)
1941 continue;
1942 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1943 break;
1944 }
1945
1946 if (phy_id >= PHY_MAX_ADDR) {
1947 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1948 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1949 phy_id = 0;
1950 }
1951
1952 snprintf(phy_name, sizeof(phy_name),
1953 PHY_ID_FMT, mdio_bus_id, phy_id);
1954 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1955 fep->phy_interface);
1956 }
1957
1958 if (IS_ERR(phy_dev)) {
1959 netdev_err(ndev, "could not attach to PHY\n");
1960 return PTR_ERR(phy_dev);
1961 }
1962
1963 /* mask with MAC supported features */
1964 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
1965 phy_dev->supported &= PHY_GBIT_FEATURES;
1966 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1967 #if !defined(CONFIG_M5272)
1968 phy_dev->supported |= SUPPORTED_Pause;
1969 #endif
1970 }
1971 else
1972 phy_dev->supported &= PHY_BASIC_FEATURES;
1973
1974 phy_dev->advertising = phy_dev->supported;
1975
1976 fep->phy_dev = phy_dev;
1977 fep->link = 0;
1978 fep->full_duplex = 0;
1979
1980 phy_attached_info(phy_dev);
1981
1982 return 0;
1983 }
1984
1985 static int fec_enet_mii_init(struct platform_device *pdev)
1986 {
1987 static struct mii_bus *fec0_mii_bus;
1988 struct net_device *ndev = platform_get_drvdata(pdev);
1989 struct fec_enet_private *fep = netdev_priv(ndev);
1990 struct device_node *node;
1991 int err = -ENXIO;
1992 u32 mii_speed, holdtime;
1993
1994 /*
1995 * The i.MX28 dual fec interfaces are not equal.
1996 * Here are the differences:
1997 *
1998 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1999 * - fec0 acts as the 1588 time master while fec1 is slave
2000 * - external phys can only be configured by fec0
2001 *
2002 * That is to say fec1 can not work independently. It only works
2003 * when fec0 is working. The reason behind this design is that the
2004 * second interface is added primarily for Switch mode.
2005 *
2006 * Because of the last point above, both phys are attached on fec0
2007 * mdio interface in board design, and need to be configured by
2008 * fec0 mii_bus.
2009 */
2010 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
2011 /* fec1 uses fec0 mii_bus */
2012 if (mii_cnt && fec0_mii_bus) {
2013 fep->mii_bus = fec0_mii_bus;
2014 mii_cnt++;
2015 return 0;
2016 }
2017 return -ENOENT;
2018 }
2019
2020 fep->mii_timeout = 0;
2021
2022 /*
2023 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
2024 *
2025 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2026 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
2027 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2028 * document.
2029 */
2030 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
2031 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2032 mii_speed--;
2033 if (mii_speed > 63) {
2034 dev_err(&pdev->dev,
2035 "fec clock (%lu) to fast to get right mii speed\n",
2036 clk_get_rate(fep->clk_ipg));
2037 err = -EINVAL;
2038 goto err_out;
2039 }
2040
2041 /*
2042 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2043 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2044 * versions are RAZ there, so just ignore the difference and write the
2045 * register always.
2046 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2047 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2048 * output.
2049 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2050 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2051 * holdtime cannot result in a value greater than 3.
2052 */
2053 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2054
2055 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2056
2057 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2058
2059 fep->mii_bus = mdiobus_alloc();
2060 if (fep->mii_bus == NULL) {
2061 err = -ENOMEM;
2062 goto err_out;
2063 }
2064
2065 fep->mii_bus->name = "fec_enet_mii_bus";
2066 fep->mii_bus->read = fec_enet_mdio_read;
2067 fep->mii_bus->write = fec_enet_mdio_write;
2068 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2069 pdev->name, fep->dev_id + 1);
2070 fep->mii_bus->priv = fep;
2071 fep->mii_bus->parent = &pdev->dev;
2072
2073 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2074 if (node) {
2075 err = of_mdiobus_register(fep->mii_bus, node);
2076 of_node_put(node);
2077 } else {
2078 err = mdiobus_register(fep->mii_bus);
2079 }
2080
2081 if (err)
2082 goto err_out_free_mdiobus;
2083
2084 mii_cnt++;
2085
2086 /* save fec0 mii_bus */
2087 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2088 fec0_mii_bus = fep->mii_bus;
2089
2090 return 0;
2091
2092 err_out_free_mdiobus:
2093 mdiobus_free(fep->mii_bus);
2094 err_out:
2095 return err;
2096 }
2097
2098 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2099 {
2100 if (--mii_cnt == 0) {
2101 mdiobus_unregister(fep->mii_bus);
2102 mdiobus_free(fep->mii_bus);
2103 }
2104 }
2105
2106 static int fec_enet_get_settings(struct net_device *ndev,
2107 struct ethtool_cmd *cmd)
2108 {
2109 struct fec_enet_private *fep = netdev_priv(ndev);
2110 struct phy_device *phydev = fep->phy_dev;
2111
2112 if (!phydev)
2113 return -ENODEV;
2114
2115 return phy_ethtool_gset(phydev, cmd);
2116 }
2117
2118 static int fec_enet_set_settings(struct net_device *ndev,
2119 struct ethtool_cmd *cmd)
2120 {
2121 struct fec_enet_private *fep = netdev_priv(ndev);
2122 struct phy_device *phydev = fep->phy_dev;
2123
2124 if (!phydev)
2125 return -ENODEV;
2126
2127 return phy_ethtool_sset(phydev, cmd);
2128 }
2129
2130 static void fec_enet_get_drvinfo(struct net_device *ndev,
2131 struct ethtool_drvinfo *info)
2132 {
2133 struct fec_enet_private *fep = netdev_priv(ndev);
2134
2135 strlcpy(info->driver, fep->pdev->dev.driver->name,
2136 sizeof(info->driver));
2137 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2138 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2139 }
2140
2141 static int fec_enet_get_regs_len(struct net_device *ndev)
2142 {
2143 struct fec_enet_private *fep = netdev_priv(ndev);
2144 struct resource *r;
2145 int s = 0;
2146
2147 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2148 if (r)
2149 s = resource_size(r);
2150
2151 return s;
2152 }
2153
2154 /* List of registers that can be safety be read to dump them with ethtool */
2155 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2156 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
2157 static u32 fec_enet_register_offset[] = {
2158 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2159 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2160 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2161 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2162 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2163 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2164 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2165 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2166 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2167 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2168 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2169 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2170 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2171 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2172 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2173 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2174 RMON_T_P_GTE2048, RMON_T_OCTETS,
2175 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2176 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2177 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2178 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2179 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2180 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2181 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2182 RMON_R_P_GTE2048, RMON_R_OCTETS,
2183 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2184 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2185 };
2186 #else
2187 static u32 fec_enet_register_offset[] = {
2188 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2189 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2190 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2191 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2192 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2193 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2194 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2195 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2196 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2197 };
2198 #endif
2199
2200 static void fec_enet_get_regs(struct net_device *ndev,
2201 struct ethtool_regs *regs, void *regbuf)
2202 {
2203 struct fec_enet_private *fep = netdev_priv(ndev);
2204 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2205 u32 *buf = (u32 *)regbuf;
2206 u32 i, off;
2207
2208 memset(buf, 0, regs->len);
2209
2210 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
2211 off = fec_enet_register_offset[i] / 4;
2212 buf[off] = readl(&theregs[off]);
2213 }
2214 }
2215
2216 static int fec_enet_get_ts_info(struct net_device *ndev,
2217 struct ethtool_ts_info *info)
2218 {
2219 struct fec_enet_private *fep = netdev_priv(ndev);
2220
2221 if (fep->bufdesc_ex) {
2222
2223 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2224 SOF_TIMESTAMPING_RX_SOFTWARE |
2225 SOF_TIMESTAMPING_SOFTWARE |
2226 SOF_TIMESTAMPING_TX_HARDWARE |
2227 SOF_TIMESTAMPING_RX_HARDWARE |
2228 SOF_TIMESTAMPING_RAW_HARDWARE;
2229 if (fep->ptp_clock)
2230 info->phc_index = ptp_clock_index(fep->ptp_clock);
2231 else
2232 info->phc_index = -1;
2233
2234 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2235 (1 << HWTSTAMP_TX_ON);
2236
2237 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2238 (1 << HWTSTAMP_FILTER_ALL);
2239 return 0;
2240 } else {
2241 return ethtool_op_get_ts_info(ndev, info);
2242 }
2243 }
2244
2245 #if !defined(CONFIG_M5272)
2246
2247 static void fec_enet_get_pauseparam(struct net_device *ndev,
2248 struct ethtool_pauseparam *pause)
2249 {
2250 struct fec_enet_private *fep = netdev_priv(ndev);
2251
2252 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2253 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2254 pause->rx_pause = pause->tx_pause;
2255 }
2256
2257 static int fec_enet_set_pauseparam(struct net_device *ndev,
2258 struct ethtool_pauseparam *pause)
2259 {
2260 struct fec_enet_private *fep = netdev_priv(ndev);
2261
2262 if (!fep->phy_dev)
2263 return -ENODEV;
2264
2265 if (pause->tx_pause != pause->rx_pause) {
2266 netdev_info(ndev,
2267 "hardware only support enable/disable both tx and rx");
2268 return -EINVAL;
2269 }
2270
2271 fep->pause_flag = 0;
2272
2273 /* tx pause must be same as rx pause */
2274 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2275 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2276
2277 if (pause->rx_pause || pause->autoneg) {
2278 fep->phy_dev->supported |= ADVERTISED_Pause;
2279 fep->phy_dev->advertising |= ADVERTISED_Pause;
2280 } else {
2281 fep->phy_dev->supported &= ~ADVERTISED_Pause;
2282 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
2283 }
2284
2285 if (pause->autoneg) {
2286 if (netif_running(ndev))
2287 fec_stop(ndev);
2288 phy_start_aneg(fep->phy_dev);
2289 }
2290 if (netif_running(ndev)) {
2291 napi_disable(&fep->napi);
2292 netif_tx_lock_bh(ndev);
2293 fec_restart(ndev);
2294 netif_wake_queue(ndev);
2295 netif_tx_unlock_bh(ndev);
2296 napi_enable(&fep->napi);
2297 }
2298
2299 return 0;
2300 }
2301
2302 static const struct fec_stat {
2303 char name[ETH_GSTRING_LEN];
2304 u16 offset;
2305 } fec_stats[] = {
2306 /* RMON TX */
2307 { "tx_dropped", RMON_T_DROP },
2308 { "tx_packets", RMON_T_PACKETS },
2309 { "tx_broadcast", RMON_T_BC_PKT },
2310 { "tx_multicast", RMON_T_MC_PKT },
2311 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2312 { "tx_undersize", RMON_T_UNDERSIZE },
2313 { "tx_oversize", RMON_T_OVERSIZE },
2314 { "tx_fragment", RMON_T_FRAG },
2315 { "tx_jabber", RMON_T_JAB },
2316 { "tx_collision", RMON_T_COL },
2317 { "tx_64byte", RMON_T_P64 },
2318 { "tx_65to127byte", RMON_T_P65TO127 },
2319 { "tx_128to255byte", RMON_T_P128TO255 },
2320 { "tx_256to511byte", RMON_T_P256TO511 },
2321 { "tx_512to1023byte", RMON_T_P512TO1023 },
2322 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2323 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2324 { "tx_octets", RMON_T_OCTETS },
2325
2326 /* IEEE TX */
2327 { "IEEE_tx_drop", IEEE_T_DROP },
2328 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2329 { "IEEE_tx_1col", IEEE_T_1COL },
2330 { "IEEE_tx_mcol", IEEE_T_MCOL },
2331 { "IEEE_tx_def", IEEE_T_DEF },
2332 { "IEEE_tx_lcol", IEEE_T_LCOL },
2333 { "IEEE_tx_excol", IEEE_T_EXCOL },
2334 { "IEEE_tx_macerr", IEEE_T_MACERR },
2335 { "IEEE_tx_cserr", IEEE_T_CSERR },
2336 { "IEEE_tx_sqe", IEEE_T_SQE },
2337 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2338 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2339
2340 /* RMON RX */
2341 { "rx_packets", RMON_R_PACKETS },
2342 { "rx_broadcast", RMON_R_BC_PKT },
2343 { "rx_multicast", RMON_R_MC_PKT },
2344 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2345 { "rx_undersize", RMON_R_UNDERSIZE },
2346 { "rx_oversize", RMON_R_OVERSIZE },
2347 { "rx_fragment", RMON_R_FRAG },
2348 { "rx_jabber", RMON_R_JAB },
2349 { "rx_64byte", RMON_R_P64 },
2350 { "rx_65to127byte", RMON_R_P65TO127 },
2351 { "rx_128to255byte", RMON_R_P128TO255 },
2352 { "rx_256to511byte", RMON_R_P256TO511 },
2353 { "rx_512to1023byte", RMON_R_P512TO1023 },
2354 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2355 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2356 { "rx_octets", RMON_R_OCTETS },
2357
2358 /* IEEE RX */
2359 { "IEEE_rx_drop", IEEE_R_DROP },
2360 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2361 { "IEEE_rx_crc", IEEE_R_CRC },
2362 { "IEEE_rx_align", IEEE_R_ALIGN },
2363 { "IEEE_rx_macerr", IEEE_R_MACERR },
2364 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2365 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2366 };
2367
2368 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2369 struct ethtool_stats *stats, u64 *data)
2370 {
2371 struct fec_enet_private *fep = netdev_priv(dev);
2372 int i;
2373
2374 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2375 data[i] = readl(fep->hwp + fec_stats[i].offset);
2376 }
2377
2378 static void fec_enet_get_strings(struct net_device *netdev,
2379 u32 stringset, u8 *data)
2380 {
2381 int i;
2382 switch (stringset) {
2383 case ETH_SS_STATS:
2384 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2385 memcpy(data + i * ETH_GSTRING_LEN,
2386 fec_stats[i].name, ETH_GSTRING_LEN);
2387 break;
2388 }
2389 }
2390
2391 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2392 {
2393 switch (sset) {
2394 case ETH_SS_STATS:
2395 return ARRAY_SIZE(fec_stats);
2396 default:
2397 return -EOPNOTSUPP;
2398 }
2399 }
2400 #endif /* !defined(CONFIG_M5272) */
2401
2402 static int fec_enet_nway_reset(struct net_device *dev)
2403 {
2404 struct fec_enet_private *fep = netdev_priv(dev);
2405 struct phy_device *phydev = fep->phy_dev;
2406
2407 if (!phydev)
2408 return -ENODEV;
2409
2410 return genphy_restart_aneg(phydev);
2411 }
2412
2413 /* ITR clock source is enet system clock (clk_ahb).
2414 * TCTT unit is cycle_ns * 64 cycle
2415 * So, the ICTT value = X us / (cycle_ns * 64)
2416 */
2417 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2418 {
2419 struct fec_enet_private *fep = netdev_priv(ndev);
2420
2421 return us * (fep->itr_clk_rate / 64000) / 1000;
2422 }
2423
2424 /* Set threshold for interrupt coalescing */
2425 static void fec_enet_itr_coal_set(struct net_device *ndev)
2426 {
2427 struct fec_enet_private *fep = netdev_priv(ndev);
2428 int rx_itr, tx_itr;
2429
2430 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2431 return;
2432
2433 /* Must be greater than zero to avoid unpredictable behavior */
2434 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2435 !fep->tx_time_itr || !fep->tx_pkts_itr)
2436 return;
2437
2438 /* Select enet system clock as Interrupt Coalescing
2439 * timer Clock Source
2440 */
2441 rx_itr = FEC_ITR_CLK_SEL;
2442 tx_itr = FEC_ITR_CLK_SEL;
2443
2444 /* set ICFT and ICTT */
2445 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2446 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2447 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2448 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2449
2450 rx_itr |= FEC_ITR_EN;
2451 tx_itr |= FEC_ITR_EN;
2452
2453 writel(tx_itr, fep->hwp + FEC_TXIC0);
2454 writel(rx_itr, fep->hwp + FEC_RXIC0);
2455 writel(tx_itr, fep->hwp + FEC_TXIC1);
2456 writel(rx_itr, fep->hwp + FEC_RXIC1);
2457 writel(tx_itr, fep->hwp + FEC_TXIC2);
2458 writel(rx_itr, fep->hwp + FEC_RXIC2);
2459 }
2460
2461 static int
2462 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2463 {
2464 struct fec_enet_private *fep = netdev_priv(ndev);
2465
2466 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2467 return -EOPNOTSUPP;
2468
2469 ec->rx_coalesce_usecs = fep->rx_time_itr;
2470 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2471
2472 ec->tx_coalesce_usecs = fep->tx_time_itr;
2473 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2474
2475 return 0;
2476 }
2477
2478 static int
2479 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2480 {
2481 struct fec_enet_private *fep = netdev_priv(ndev);
2482 unsigned int cycle;
2483
2484 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2485 return -EOPNOTSUPP;
2486
2487 if (ec->rx_max_coalesced_frames > 255) {
2488 pr_err("Rx coalesced frames exceed hardware limiation");
2489 return -EINVAL;
2490 }
2491
2492 if (ec->tx_max_coalesced_frames > 255) {
2493 pr_err("Tx coalesced frame exceed hardware limiation");
2494 return -EINVAL;
2495 }
2496
2497 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2498 if (cycle > 0xFFFF) {
2499 pr_err("Rx coalesed usec exceeed hardware limiation");
2500 return -EINVAL;
2501 }
2502
2503 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2504 if (cycle > 0xFFFF) {
2505 pr_err("Rx coalesed usec exceeed hardware limiation");
2506 return -EINVAL;
2507 }
2508
2509 fep->rx_time_itr = ec->rx_coalesce_usecs;
2510 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2511
2512 fep->tx_time_itr = ec->tx_coalesce_usecs;
2513 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2514
2515 fec_enet_itr_coal_set(ndev);
2516
2517 return 0;
2518 }
2519
2520 static void fec_enet_itr_coal_init(struct net_device *ndev)
2521 {
2522 struct ethtool_coalesce ec;
2523
2524 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2525 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2526
2527 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2528 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2529
2530 fec_enet_set_coalesce(ndev, &ec);
2531 }
2532
2533 static int fec_enet_get_tunable(struct net_device *netdev,
2534 const struct ethtool_tunable *tuna,
2535 void *data)
2536 {
2537 struct fec_enet_private *fep = netdev_priv(netdev);
2538 int ret = 0;
2539
2540 switch (tuna->id) {
2541 case ETHTOOL_RX_COPYBREAK:
2542 *(u32 *)data = fep->rx_copybreak;
2543 break;
2544 default:
2545 ret = -EINVAL;
2546 break;
2547 }
2548
2549 return ret;
2550 }
2551
2552 static int fec_enet_set_tunable(struct net_device *netdev,
2553 const struct ethtool_tunable *tuna,
2554 const void *data)
2555 {
2556 struct fec_enet_private *fep = netdev_priv(netdev);
2557 int ret = 0;
2558
2559 switch (tuna->id) {
2560 case ETHTOOL_RX_COPYBREAK:
2561 fep->rx_copybreak = *(u32 *)data;
2562 break;
2563 default:
2564 ret = -EINVAL;
2565 break;
2566 }
2567
2568 return ret;
2569 }
2570
2571 static void
2572 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2573 {
2574 struct fec_enet_private *fep = netdev_priv(ndev);
2575
2576 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2577 wol->supported = WAKE_MAGIC;
2578 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2579 } else {
2580 wol->supported = wol->wolopts = 0;
2581 }
2582 }
2583
2584 static int
2585 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2586 {
2587 struct fec_enet_private *fep = netdev_priv(ndev);
2588
2589 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2590 return -EINVAL;
2591
2592 if (wol->wolopts & ~WAKE_MAGIC)
2593 return -EINVAL;
2594
2595 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2596 if (device_may_wakeup(&ndev->dev)) {
2597 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2598 if (fep->irq[0] > 0)
2599 enable_irq_wake(fep->irq[0]);
2600 } else {
2601 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2602 if (fep->irq[0] > 0)
2603 disable_irq_wake(fep->irq[0]);
2604 }
2605
2606 return 0;
2607 }
2608
2609 static const struct ethtool_ops fec_enet_ethtool_ops = {
2610 .get_settings = fec_enet_get_settings,
2611 .set_settings = fec_enet_set_settings,
2612 .get_drvinfo = fec_enet_get_drvinfo,
2613 .get_regs_len = fec_enet_get_regs_len,
2614 .get_regs = fec_enet_get_regs,
2615 .nway_reset = fec_enet_nway_reset,
2616 .get_link = ethtool_op_get_link,
2617 .get_coalesce = fec_enet_get_coalesce,
2618 .set_coalesce = fec_enet_set_coalesce,
2619 #ifndef CONFIG_M5272
2620 .get_pauseparam = fec_enet_get_pauseparam,
2621 .set_pauseparam = fec_enet_set_pauseparam,
2622 .get_strings = fec_enet_get_strings,
2623 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2624 .get_sset_count = fec_enet_get_sset_count,
2625 #endif
2626 .get_ts_info = fec_enet_get_ts_info,
2627 .get_tunable = fec_enet_get_tunable,
2628 .set_tunable = fec_enet_set_tunable,
2629 .get_wol = fec_enet_get_wol,
2630 .set_wol = fec_enet_set_wol,
2631 };
2632
2633 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2634 {
2635 struct fec_enet_private *fep = netdev_priv(ndev);
2636 struct phy_device *phydev = fep->phy_dev;
2637
2638 if (!netif_running(ndev))
2639 return -EINVAL;
2640
2641 if (!phydev)
2642 return -ENODEV;
2643
2644 if (fep->bufdesc_ex) {
2645 if (cmd == SIOCSHWTSTAMP)
2646 return fec_ptp_set(ndev, rq);
2647 if (cmd == SIOCGHWTSTAMP)
2648 return fec_ptp_get(ndev, rq);
2649 }
2650
2651 return phy_mii_ioctl(phydev, rq, cmd);
2652 }
2653
2654 static void fec_enet_free_buffers(struct net_device *ndev)
2655 {
2656 struct fec_enet_private *fep = netdev_priv(ndev);
2657 unsigned int i;
2658 struct sk_buff *skb;
2659 struct bufdesc *bdp;
2660 struct fec_enet_priv_tx_q *txq;
2661 struct fec_enet_priv_rx_q *rxq;
2662 unsigned int q;
2663
2664 for (q = 0; q < fep->num_rx_queues; q++) {
2665 rxq = fep->rx_queue[q];
2666 bdp = rxq->rx_bd_base;
2667 for (i = 0; i < rxq->rx_ring_size; i++) {
2668 skb = rxq->rx_skbuff[i];
2669 rxq->rx_skbuff[i] = NULL;
2670 if (skb) {
2671 dma_unmap_single(&fep->pdev->dev,
2672 fec32_to_cpu(bdp->cbd_bufaddr),
2673 FEC_ENET_RX_FRSIZE - fep->rx_align,
2674 DMA_FROM_DEVICE);
2675 dev_kfree_skb(skb);
2676 }
2677 bdp = fec_enet_get_nextdesc(bdp, fep, q);
2678 }
2679 }
2680
2681 for (q = 0; q < fep->num_tx_queues; q++) {
2682 txq = fep->tx_queue[q];
2683 bdp = txq->tx_bd_base;
2684 for (i = 0; i < txq->tx_ring_size; i++) {
2685 kfree(txq->tx_bounce[i]);
2686 txq->tx_bounce[i] = NULL;
2687 skb = txq->tx_skbuff[i];
2688 txq->tx_skbuff[i] = NULL;
2689 dev_kfree_skb(skb);
2690 }
2691 }
2692 }
2693
2694 static void fec_enet_free_queue(struct net_device *ndev)
2695 {
2696 struct fec_enet_private *fep = netdev_priv(ndev);
2697 int i;
2698 struct fec_enet_priv_tx_q *txq;
2699
2700 for (i = 0; i < fep->num_tx_queues; i++)
2701 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2702 txq = fep->tx_queue[i];
2703 dma_free_coherent(NULL,
2704 txq->tx_ring_size * TSO_HEADER_SIZE,
2705 txq->tso_hdrs,
2706 txq->tso_hdrs_dma);
2707 }
2708
2709 for (i = 0; i < fep->num_rx_queues; i++)
2710 kfree(fep->rx_queue[i]);
2711 for (i = 0; i < fep->num_tx_queues; i++)
2712 kfree(fep->tx_queue[i]);
2713 }
2714
2715 static int fec_enet_alloc_queue(struct net_device *ndev)
2716 {
2717 struct fec_enet_private *fep = netdev_priv(ndev);
2718 int i;
2719 int ret = 0;
2720 struct fec_enet_priv_tx_q *txq;
2721
2722 for (i = 0; i < fep->num_tx_queues; i++) {
2723 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2724 if (!txq) {
2725 ret = -ENOMEM;
2726 goto alloc_failed;
2727 }
2728
2729 fep->tx_queue[i] = txq;
2730 txq->tx_ring_size = TX_RING_SIZE;
2731 fep->total_tx_ring_size += fep->tx_queue[i]->tx_ring_size;
2732
2733 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2734 txq->tx_wake_threshold =
2735 (txq->tx_ring_size - txq->tx_stop_threshold) / 2;
2736
2737 txq->tso_hdrs = dma_alloc_coherent(NULL,
2738 txq->tx_ring_size * TSO_HEADER_SIZE,
2739 &txq->tso_hdrs_dma,
2740 GFP_KERNEL);
2741 if (!txq->tso_hdrs) {
2742 ret = -ENOMEM;
2743 goto alloc_failed;
2744 }
2745 }
2746
2747 for (i = 0; i < fep->num_rx_queues; i++) {
2748 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2749 GFP_KERNEL);
2750 if (!fep->rx_queue[i]) {
2751 ret = -ENOMEM;
2752 goto alloc_failed;
2753 }
2754
2755 fep->rx_queue[i]->rx_ring_size = RX_RING_SIZE;
2756 fep->total_rx_ring_size += fep->rx_queue[i]->rx_ring_size;
2757 }
2758 return ret;
2759
2760 alloc_failed:
2761 fec_enet_free_queue(ndev);
2762 return ret;
2763 }
2764
2765 static int
2766 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2767 {
2768 struct fec_enet_private *fep = netdev_priv(ndev);
2769 unsigned int i;
2770 struct sk_buff *skb;
2771 struct bufdesc *bdp;
2772 struct fec_enet_priv_rx_q *rxq;
2773
2774 rxq = fep->rx_queue[queue];
2775 bdp = rxq->rx_bd_base;
2776 for (i = 0; i < rxq->rx_ring_size; i++) {
2777 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2778 if (!skb)
2779 goto err_alloc;
2780
2781 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2782 dev_kfree_skb(skb);
2783 goto err_alloc;
2784 }
2785
2786 rxq->rx_skbuff[i] = skb;
2787 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
2788
2789 if (fep->bufdesc_ex) {
2790 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2791 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
2792 }
2793
2794 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2795 }
2796
2797 /* Set the last buffer to wrap. */
2798 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2799 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2800 return 0;
2801
2802 err_alloc:
2803 fec_enet_free_buffers(ndev);
2804 return -ENOMEM;
2805 }
2806
2807 static int
2808 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2809 {
2810 struct fec_enet_private *fep = netdev_priv(ndev);
2811 unsigned int i;
2812 struct bufdesc *bdp;
2813 struct fec_enet_priv_tx_q *txq;
2814
2815 txq = fep->tx_queue[queue];
2816 bdp = txq->tx_bd_base;
2817 for (i = 0; i < txq->tx_ring_size; i++) {
2818 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2819 if (!txq->tx_bounce[i])
2820 goto err_alloc;
2821
2822 bdp->cbd_sc = cpu_to_fec16(0);
2823 bdp->cbd_bufaddr = cpu_to_fec32(0);
2824
2825 if (fep->bufdesc_ex) {
2826 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2827 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
2828 }
2829
2830 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2831 }
2832
2833 /* Set the last buffer to wrap. */
2834 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2835 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2836
2837 return 0;
2838
2839 err_alloc:
2840 fec_enet_free_buffers(ndev);
2841 return -ENOMEM;
2842 }
2843
2844 static int fec_enet_alloc_buffers(struct net_device *ndev)
2845 {
2846 struct fec_enet_private *fep = netdev_priv(ndev);
2847 unsigned int i;
2848
2849 for (i = 0; i < fep->num_rx_queues; i++)
2850 if (fec_enet_alloc_rxq_buffers(ndev, i))
2851 return -ENOMEM;
2852
2853 for (i = 0; i < fep->num_tx_queues; i++)
2854 if (fec_enet_alloc_txq_buffers(ndev, i))
2855 return -ENOMEM;
2856 return 0;
2857 }
2858
2859 static int
2860 fec_enet_open(struct net_device *ndev)
2861 {
2862 struct fec_enet_private *fep = netdev_priv(ndev);
2863 int ret;
2864
2865 ret = pm_runtime_get_sync(&fep->pdev->dev);
2866 if (ret < 0)
2867 return ret;
2868
2869 pinctrl_pm_select_default_state(&fep->pdev->dev);
2870 ret = fec_enet_clk_enable(ndev, true);
2871 if (ret)
2872 goto clk_enable;
2873
2874 /* I should reset the ring buffers here, but I don't yet know
2875 * a simple way to do that.
2876 */
2877
2878 ret = fec_enet_alloc_buffers(ndev);
2879 if (ret)
2880 goto err_enet_alloc;
2881
2882 /* Init MAC prior to mii bus probe */
2883 fec_restart(ndev);
2884
2885 /* Probe and connect to PHY when open the interface */
2886 ret = fec_enet_mii_probe(ndev);
2887 if (ret)
2888 goto err_enet_mii_probe;
2889
2890 napi_enable(&fep->napi);
2891 phy_start(fep->phy_dev);
2892 netif_tx_start_all_queues(ndev);
2893
2894 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2895 FEC_WOL_FLAG_ENABLE);
2896
2897 return 0;
2898
2899 err_enet_mii_probe:
2900 fec_enet_free_buffers(ndev);
2901 err_enet_alloc:
2902 fec_enet_clk_enable(ndev, false);
2903 clk_enable:
2904 pm_runtime_mark_last_busy(&fep->pdev->dev);
2905 pm_runtime_put_autosuspend(&fep->pdev->dev);
2906 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2907 return ret;
2908 }
2909
2910 static int
2911 fec_enet_close(struct net_device *ndev)
2912 {
2913 struct fec_enet_private *fep = netdev_priv(ndev);
2914
2915 phy_stop(fep->phy_dev);
2916
2917 if (netif_device_present(ndev)) {
2918 napi_disable(&fep->napi);
2919 netif_tx_disable(ndev);
2920 fec_stop(ndev);
2921 }
2922
2923 phy_disconnect(fep->phy_dev);
2924 fep->phy_dev = NULL;
2925
2926 fec_enet_clk_enable(ndev, false);
2927 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2928 pm_runtime_mark_last_busy(&fep->pdev->dev);
2929 pm_runtime_put_autosuspend(&fep->pdev->dev);
2930
2931 fec_enet_free_buffers(ndev);
2932
2933 return 0;
2934 }
2935
2936 /* Set or clear the multicast filter for this adaptor.
2937 * Skeleton taken from sunlance driver.
2938 * The CPM Ethernet implementation allows Multicast as well as individual
2939 * MAC address filtering. Some of the drivers check to make sure it is
2940 * a group multicast address, and discard those that are not. I guess I
2941 * will do the same for now, but just remove the test if you want
2942 * individual filtering as well (do the upper net layers want or support
2943 * this kind of feature?).
2944 */
2945
2946 #define HASH_BITS 6 /* #bits in hash */
2947 #define CRC32_POLY 0xEDB88320
2948
2949 static void set_multicast_list(struct net_device *ndev)
2950 {
2951 struct fec_enet_private *fep = netdev_priv(ndev);
2952 struct netdev_hw_addr *ha;
2953 unsigned int i, bit, data, crc, tmp;
2954 unsigned char hash;
2955
2956 if (ndev->flags & IFF_PROMISC) {
2957 tmp = readl(fep->hwp + FEC_R_CNTRL);
2958 tmp |= 0x8;
2959 writel(tmp, fep->hwp + FEC_R_CNTRL);
2960 return;
2961 }
2962
2963 tmp = readl(fep->hwp + FEC_R_CNTRL);
2964 tmp &= ~0x8;
2965 writel(tmp, fep->hwp + FEC_R_CNTRL);
2966
2967 if (ndev->flags & IFF_ALLMULTI) {
2968 /* Catch all multicast addresses, so set the
2969 * filter to all 1's
2970 */
2971 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2972 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2973
2974 return;
2975 }
2976
2977 /* Clear filter and add the addresses in hash register
2978 */
2979 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2980 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2981
2982 netdev_for_each_mc_addr(ha, ndev) {
2983 /* calculate crc32 value of mac address */
2984 crc = 0xffffffff;
2985
2986 for (i = 0; i < ndev->addr_len; i++) {
2987 data = ha->addr[i];
2988 for (bit = 0; bit < 8; bit++, data >>= 1) {
2989 crc = (crc >> 1) ^
2990 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2991 }
2992 }
2993
2994 /* only upper 6 bits (HASH_BITS) are used
2995 * which point to specific bit in he hash registers
2996 */
2997 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2998
2999 if (hash > 31) {
3000 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3001 tmp |= 1 << (hash - 32);
3002 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3003 } else {
3004 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3005 tmp |= 1 << hash;
3006 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3007 }
3008 }
3009 }
3010
3011 /* Set a MAC change in hardware. */
3012 static int
3013 fec_set_mac_address(struct net_device *ndev, void *p)
3014 {
3015 struct fec_enet_private *fep = netdev_priv(ndev);
3016 struct sockaddr *addr = p;
3017
3018 if (addr) {
3019 if (!is_valid_ether_addr(addr->sa_data))
3020 return -EADDRNOTAVAIL;
3021 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3022 }
3023
3024 /* Add netif status check here to avoid system hang in below case:
3025 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3026 * After ethx down, fec all clocks are gated off and then register
3027 * access causes system hang.
3028 */
3029 if (!netif_running(ndev))
3030 return 0;
3031
3032 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3033 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
3034 fep->hwp + FEC_ADDR_LOW);
3035 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
3036 fep->hwp + FEC_ADDR_HIGH);
3037 return 0;
3038 }
3039
3040 #ifdef CONFIG_NET_POLL_CONTROLLER
3041 /**
3042 * fec_poll_controller - FEC Poll controller function
3043 * @dev: The FEC network adapter
3044 *
3045 * Polled functionality used by netconsole and others in non interrupt mode
3046 *
3047 */
3048 static void fec_poll_controller(struct net_device *dev)
3049 {
3050 int i;
3051 struct fec_enet_private *fep = netdev_priv(dev);
3052
3053 for (i = 0; i < FEC_IRQ_NUM; i++) {
3054 if (fep->irq[i] > 0) {
3055 disable_irq(fep->irq[i]);
3056 fec_enet_interrupt(fep->irq[i], dev);
3057 enable_irq(fep->irq[i]);
3058 }
3059 }
3060 }
3061 #endif
3062
3063 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3064 netdev_features_t features)
3065 {
3066 struct fec_enet_private *fep = netdev_priv(netdev);
3067 netdev_features_t changed = features ^ netdev->features;
3068
3069 netdev->features = features;
3070
3071 /* Receive checksum has been changed */
3072 if (changed & NETIF_F_RXCSUM) {
3073 if (features & NETIF_F_RXCSUM)
3074 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3075 else
3076 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3077 }
3078 }
3079
3080 static int fec_set_features(struct net_device *netdev,
3081 netdev_features_t features)
3082 {
3083 struct fec_enet_private *fep = netdev_priv(netdev);
3084 netdev_features_t changed = features ^ netdev->features;
3085
3086 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3087 napi_disable(&fep->napi);
3088 netif_tx_lock_bh(netdev);
3089 fec_stop(netdev);
3090 fec_enet_set_netdev_features(netdev, features);
3091 fec_restart(netdev);
3092 netif_tx_wake_all_queues(netdev);
3093 netif_tx_unlock_bh(netdev);
3094 napi_enable(&fep->napi);
3095 } else {
3096 fec_enet_set_netdev_features(netdev, features);
3097 }
3098
3099 return 0;
3100 }
3101
3102 static const struct net_device_ops fec_netdev_ops = {
3103 .ndo_open = fec_enet_open,
3104 .ndo_stop = fec_enet_close,
3105 .ndo_start_xmit = fec_enet_start_xmit,
3106 .ndo_set_rx_mode = set_multicast_list,
3107 .ndo_change_mtu = eth_change_mtu,
3108 .ndo_validate_addr = eth_validate_addr,
3109 .ndo_tx_timeout = fec_timeout,
3110 .ndo_set_mac_address = fec_set_mac_address,
3111 .ndo_do_ioctl = fec_enet_ioctl,
3112 #ifdef CONFIG_NET_POLL_CONTROLLER
3113 .ndo_poll_controller = fec_poll_controller,
3114 #endif
3115 .ndo_set_features = fec_set_features,
3116 };
3117
3118 /*
3119 * XXX: We need to clean up on failure exits here.
3120 *
3121 */
3122 static int fec_enet_init(struct net_device *ndev)
3123 {
3124 struct fec_enet_private *fep = netdev_priv(ndev);
3125 struct fec_enet_priv_tx_q *txq;
3126 struct fec_enet_priv_rx_q *rxq;
3127 struct bufdesc *cbd_base;
3128 dma_addr_t bd_dma;
3129 int bd_size;
3130 unsigned int i;
3131
3132 #if defined(CONFIG_ARM)
3133 fep->rx_align = 0xf;
3134 fep->tx_align = 0xf;
3135 #else
3136 fep->rx_align = 0x3;
3137 fep->tx_align = 0x3;
3138 #endif
3139
3140 fec_enet_alloc_queue(ndev);
3141
3142 if (fep->bufdesc_ex)
3143 fep->bufdesc_size = sizeof(struct bufdesc_ex);
3144 else
3145 fep->bufdesc_size = sizeof(struct bufdesc);
3146 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) *
3147 fep->bufdesc_size;
3148
3149 /* Allocate memory for buffer descriptors. */
3150 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3151 GFP_KERNEL);
3152 if (!cbd_base) {
3153 return -ENOMEM;
3154 }
3155
3156 memset(cbd_base, 0, bd_size);
3157
3158 /* Get the Ethernet address */
3159 fec_get_mac(ndev);
3160 /* make sure MAC we just acquired is programmed into the hw */
3161 fec_set_mac_address(ndev, NULL);
3162
3163 /* Set receive and transmit descriptor base. */
3164 for (i = 0; i < fep->num_rx_queues; i++) {
3165 rxq = fep->rx_queue[i];
3166 rxq->index = i;
3167 rxq->rx_bd_base = (struct bufdesc *)cbd_base;
3168 rxq->bd_dma = bd_dma;
3169 if (fep->bufdesc_ex) {
3170 bd_dma += sizeof(struct bufdesc_ex) * rxq->rx_ring_size;
3171 cbd_base = (struct bufdesc *)
3172 (((struct bufdesc_ex *)cbd_base) + rxq->rx_ring_size);
3173 } else {
3174 bd_dma += sizeof(struct bufdesc) * rxq->rx_ring_size;
3175 cbd_base += rxq->rx_ring_size;
3176 }
3177 }
3178
3179 for (i = 0; i < fep->num_tx_queues; i++) {
3180 txq = fep->tx_queue[i];
3181 txq->index = i;
3182 txq->tx_bd_base = (struct bufdesc *)cbd_base;
3183 txq->bd_dma = bd_dma;
3184 if (fep->bufdesc_ex) {
3185 bd_dma += sizeof(struct bufdesc_ex) * txq->tx_ring_size;
3186 cbd_base = (struct bufdesc *)
3187 (((struct bufdesc_ex *)cbd_base) + txq->tx_ring_size);
3188 } else {
3189 bd_dma += sizeof(struct bufdesc) * txq->tx_ring_size;
3190 cbd_base += txq->tx_ring_size;
3191 }
3192 }
3193
3194
3195 /* The FEC Ethernet specific entries in the device structure */
3196 ndev->watchdog_timeo = TX_TIMEOUT;
3197 ndev->netdev_ops = &fec_netdev_ops;
3198 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3199
3200 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3201 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3202
3203 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3204 /* enable hw VLAN support */
3205 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3206
3207 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3208 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3209
3210 /* enable hw accelerator */
3211 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3212 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3213 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3214 }
3215
3216 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3217 fep->tx_align = 0;
3218 fep->rx_align = 0x3f;
3219 }
3220
3221 ndev->hw_features = ndev->features;
3222
3223 fec_restart(ndev);
3224
3225 return 0;
3226 }
3227
3228 #ifdef CONFIG_OF
3229 static void fec_reset_phy(struct platform_device *pdev)
3230 {
3231 int err, phy_reset;
3232 int msec = 1;
3233 struct device_node *np = pdev->dev.of_node;
3234
3235 if (!np)
3236 return;
3237
3238 of_property_read_u32(np, "phy-reset-duration", &msec);
3239 /* A sane reset duration should not be longer than 1s */
3240 if (msec > 1000)
3241 msec = 1;
3242
3243 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3244 if (!gpio_is_valid(phy_reset))
3245 return;
3246
3247 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3248 GPIOF_OUT_INIT_LOW, "phy-reset");
3249 if (err) {
3250 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3251 return;
3252 }
3253 msleep(msec);
3254 gpio_set_value_cansleep(phy_reset, 1);
3255 }
3256 #else /* CONFIG_OF */
3257 static void fec_reset_phy(struct platform_device *pdev)
3258 {
3259 /*
3260 * In case of platform probe, the reset has been done
3261 * by machine code.
3262 */
3263 }
3264 #endif /* CONFIG_OF */
3265
3266 static void
3267 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3268 {
3269 struct device_node *np = pdev->dev.of_node;
3270
3271 *num_tx = *num_rx = 1;
3272
3273 if (!np || !of_device_is_available(np))
3274 return;
3275
3276 /* parse the num of tx and rx queues */
3277 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3278
3279 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3280
3281 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3282 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3283 *num_tx);
3284 *num_tx = 1;
3285 return;
3286 }
3287
3288 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3289 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3290 *num_rx);
3291 *num_rx = 1;
3292 return;
3293 }
3294
3295 }
3296
3297 static int
3298 fec_probe(struct platform_device *pdev)
3299 {
3300 struct fec_enet_private *fep;
3301 struct fec_platform_data *pdata;
3302 struct net_device *ndev;
3303 int i, irq, ret = 0;
3304 struct resource *r;
3305 const struct of_device_id *of_id;
3306 static int dev_id;
3307 struct device_node *np = pdev->dev.of_node, *phy_node;
3308 int num_tx_qs;
3309 int num_rx_qs;
3310
3311 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3312
3313 /* Init network device */
3314 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
3315 num_tx_qs, num_rx_qs);
3316 if (!ndev)
3317 return -ENOMEM;
3318
3319 SET_NETDEV_DEV(ndev, &pdev->dev);
3320
3321 /* setup board info structure */
3322 fep = netdev_priv(ndev);
3323
3324 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3325 if (of_id)
3326 pdev->id_entry = of_id->data;
3327 fep->quirks = pdev->id_entry->driver_data;
3328
3329 fep->netdev = ndev;
3330 fep->num_rx_queues = num_rx_qs;
3331 fep->num_tx_queues = num_tx_qs;
3332
3333 #if !defined(CONFIG_M5272)
3334 /* default enable pause frame auto negotiation */
3335 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3336 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3337 #endif
3338
3339 /* Select default pin state */
3340 pinctrl_pm_select_default_state(&pdev->dev);
3341
3342 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3343 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3344 if (IS_ERR(fep->hwp)) {
3345 ret = PTR_ERR(fep->hwp);
3346 goto failed_ioremap;
3347 }
3348
3349 fep->pdev = pdev;
3350 fep->dev_id = dev_id++;
3351
3352 platform_set_drvdata(pdev, ndev);
3353
3354 if (of_get_property(np, "fsl,magic-packet", NULL))
3355 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3356
3357 phy_node = of_parse_phandle(np, "phy-handle", 0);
3358 if (!phy_node && of_phy_is_fixed_link(np)) {
3359 ret = of_phy_register_fixed_link(np);
3360 if (ret < 0) {
3361 dev_err(&pdev->dev,
3362 "broken fixed-link specification\n");
3363 goto failed_phy;
3364 }
3365 phy_node = of_node_get(np);
3366 }
3367 fep->phy_node = phy_node;
3368
3369 ret = of_get_phy_mode(pdev->dev.of_node);
3370 if (ret < 0) {
3371 pdata = dev_get_platdata(&pdev->dev);
3372 if (pdata)
3373 fep->phy_interface = pdata->phy;
3374 else
3375 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3376 } else {
3377 fep->phy_interface = ret;
3378 }
3379
3380 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3381 if (IS_ERR(fep->clk_ipg)) {
3382 ret = PTR_ERR(fep->clk_ipg);
3383 goto failed_clk;
3384 }
3385
3386 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3387 if (IS_ERR(fep->clk_ahb)) {
3388 ret = PTR_ERR(fep->clk_ahb);
3389 goto failed_clk;
3390 }
3391
3392 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3393
3394 /* enet_out is optional, depends on board */
3395 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3396 if (IS_ERR(fep->clk_enet_out))
3397 fep->clk_enet_out = NULL;
3398
3399 fep->ptp_clk_on = false;
3400 mutex_init(&fep->ptp_clk_mutex);
3401
3402 /* clk_ref is optional, depends on board */
3403 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3404 if (IS_ERR(fep->clk_ref))
3405 fep->clk_ref = NULL;
3406
3407 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3408 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3409 if (IS_ERR(fep->clk_ptp)) {
3410 fep->clk_ptp = NULL;
3411 fep->bufdesc_ex = false;
3412 }
3413
3414 ret = fec_enet_clk_enable(ndev, true);
3415 if (ret)
3416 goto failed_clk;
3417
3418 ret = clk_prepare_enable(fep->clk_ipg);
3419 if (ret)
3420 goto failed_clk_ipg;
3421
3422 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3423 if (!IS_ERR(fep->reg_phy)) {
3424 ret = regulator_enable(fep->reg_phy);
3425 if (ret) {
3426 dev_err(&pdev->dev,
3427 "Failed to enable phy regulator: %d\n", ret);
3428 goto failed_regulator;
3429 }
3430 } else {
3431 fep->reg_phy = NULL;
3432 }
3433
3434 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3435 pm_runtime_use_autosuspend(&pdev->dev);
3436 pm_runtime_get_noresume(&pdev->dev);
3437 pm_runtime_set_active(&pdev->dev);
3438 pm_runtime_enable(&pdev->dev);
3439
3440 fec_reset_phy(pdev);
3441
3442 if (fep->bufdesc_ex)
3443 fec_ptp_init(pdev);
3444
3445 ret = fec_enet_init(ndev);
3446 if (ret)
3447 goto failed_init;
3448
3449 for (i = 0; i < FEC_IRQ_NUM; i++) {
3450 irq = platform_get_irq(pdev, i);
3451 if (irq < 0) {
3452 if (i)
3453 break;
3454 ret = irq;
3455 goto failed_irq;
3456 }
3457 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3458 0, pdev->name, ndev);
3459 if (ret)
3460 goto failed_irq;
3461
3462 fep->irq[i] = irq;
3463 }
3464
3465 init_completion(&fep->mdio_done);
3466 ret = fec_enet_mii_init(pdev);
3467 if (ret)
3468 goto failed_mii_init;
3469
3470 /* Carrier starts down, phylib will bring it up */
3471 netif_carrier_off(ndev);
3472 fec_enet_clk_enable(ndev, false);
3473 pinctrl_pm_select_sleep_state(&pdev->dev);
3474
3475 ret = register_netdev(ndev);
3476 if (ret)
3477 goto failed_register;
3478
3479 device_init_wakeup(&ndev->dev, fep->wol_flag &
3480 FEC_WOL_HAS_MAGIC_PACKET);
3481
3482 if (fep->bufdesc_ex && fep->ptp_clock)
3483 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3484
3485 fep->rx_copybreak = COPYBREAK_DEFAULT;
3486 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3487
3488 pm_runtime_mark_last_busy(&pdev->dev);
3489 pm_runtime_put_autosuspend(&pdev->dev);
3490
3491 return 0;
3492
3493 failed_register:
3494 fec_enet_mii_remove(fep);
3495 failed_mii_init:
3496 failed_irq:
3497 failed_init:
3498 fec_ptp_stop(pdev);
3499 if (fep->reg_phy)
3500 regulator_disable(fep->reg_phy);
3501 failed_regulator:
3502 clk_disable_unprepare(fep->clk_ipg);
3503 failed_clk_ipg:
3504 fec_enet_clk_enable(ndev, false);
3505 failed_clk:
3506 failed_phy:
3507 of_node_put(phy_node);
3508 failed_ioremap:
3509 free_netdev(ndev);
3510
3511 return ret;
3512 }
3513
3514 static int
3515 fec_drv_remove(struct platform_device *pdev)
3516 {
3517 struct net_device *ndev = platform_get_drvdata(pdev);
3518 struct fec_enet_private *fep = netdev_priv(ndev);
3519
3520 cancel_work_sync(&fep->tx_timeout_work);
3521 fec_ptp_stop(pdev);
3522 unregister_netdev(ndev);
3523 fec_enet_mii_remove(fep);
3524 if (fep->reg_phy)
3525 regulator_disable(fep->reg_phy);
3526 of_node_put(fep->phy_node);
3527 free_netdev(ndev);
3528
3529 return 0;
3530 }
3531
3532 static int __maybe_unused fec_suspend(struct device *dev)
3533 {
3534 struct net_device *ndev = dev_get_drvdata(dev);
3535 struct fec_enet_private *fep = netdev_priv(ndev);
3536
3537 rtnl_lock();
3538 if (netif_running(ndev)) {
3539 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3540 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
3541 phy_stop(fep->phy_dev);
3542 napi_disable(&fep->napi);
3543 netif_tx_lock_bh(ndev);
3544 netif_device_detach(ndev);
3545 netif_tx_unlock_bh(ndev);
3546 fec_stop(ndev);
3547 fec_enet_clk_enable(ndev, false);
3548 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3549 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3550 }
3551 rtnl_unlock();
3552
3553 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3554 regulator_disable(fep->reg_phy);
3555
3556 /* SOC supply clock to phy, when clock is disabled, phy link down
3557 * SOC control phy regulator, when regulator is disabled, phy link down
3558 */
3559 if (fep->clk_enet_out || fep->reg_phy)
3560 fep->link = 0;
3561
3562 return 0;
3563 }
3564
3565 static int __maybe_unused fec_resume(struct device *dev)
3566 {
3567 struct net_device *ndev = dev_get_drvdata(dev);
3568 struct fec_enet_private *fep = netdev_priv(ndev);
3569 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
3570 int ret;
3571 int val;
3572
3573 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
3574 ret = regulator_enable(fep->reg_phy);
3575 if (ret)
3576 return ret;
3577 }
3578
3579 rtnl_lock();
3580 if (netif_running(ndev)) {
3581 ret = fec_enet_clk_enable(ndev, true);
3582 if (ret) {
3583 rtnl_unlock();
3584 goto failed_clk;
3585 }
3586 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3587 if (pdata && pdata->sleep_mode_enable)
3588 pdata->sleep_mode_enable(false);
3589 val = readl(fep->hwp + FEC_ECNTRL);
3590 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3591 writel(val, fep->hwp + FEC_ECNTRL);
3592 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3593 } else {
3594 pinctrl_pm_select_default_state(&fep->pdev->dev);
3595 }
3596 fec_restart(ndev);
3597 netif_tx_lock_bh(ndev);
3598 netif_device_attach(ndev);
3599 netif_tx_unlock_bh(ndev);
3600 napi_enable(&fep->napi);
3601 phy_start(fep->phy_dev);
3602 }
3603 rtnl_unlock();
3604
3605 return 0;
3606
3607 failed_clk:
3608 if (fep->reg_phy)
3609 regulator_disable(fep->reg_phy);
3610 return ret;
3611 }
3612
3613 static int __maybe_unused fec_runtime_suspend(struct device *dev)
3614 {
3615 struct net_device *ndev = dev_get_drvdata(dev);
3616 struct fec_enet_private *fep = netdev_priv(ndev);
3617
3618 clk_disable_unprepare(fep->clk_ipg);
3619
3620 return 0;
3621 }
3622
3623 static int __maybe_unused fec_runtime_resume(struct device *dev)
3624 {
3625 struct net_device *ndev = dev_get_drvdata(dev);
3626 struct fec_enet_private *fep = netdev_priv(ndev);
3627
3628 return clk_prepare_enable(fep->clk_ipg);
3629 }
3630
3631 static const struct dev_pm_ops fec_pm_ops = {
3632 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3633 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3634 };
3635
3636 static struct platform_driver fec_driver = {
3637 .driver = {
3638 .name = DRIVER_NAME,
3639 .pm = &fec_pm_ops,
3640 .of_match_table = fec_dt_ids,
3641 },
3642 .id_table = fec_devtype,
3643 .probe = fec_probe,
3644 .remove = fec_drv_remove,
3645 };
3646
3647 module_platform_driver(fec_driver);
3648
3649 MODULE_ALIAS("platform:"DRIVER_NAME);
3650 MODULE_LICENSE("GPL");
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