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[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / freescale / fec_main.c
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 *
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/ptrace.h>
29 #include <linux/errno.h>
30 #include <linux/ioport.h>
31 #include <linux/slab.h>
32 #include <linux/interrupt.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/in.h>
38 #include <linux/ip.h>
39 #include <net/ip.h>
40 #include <net/tso.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/icmp.h>
44 #include <linux/spinlock.h>
45 #include <linux/workqueue.h>
46 #include <linux/bitops.h>
47 #include <linux/io.h>
48 #include <linux/irq.h>
49 #include <linux/clk.h>
50 #include <linux/platform_device.h>
51 #include <linux/mdio.h>
52 #include <linux/phy.h>
53 #include <linux/fec.h>
54 #include <linux/of.h>
55 #include <linux/of_device.h>
56 #include <linux/of_gpio.h>
57 #include <linux/of_mdio.h>
58 #include <linux/of_net.h>
59 #include <linux/regulator/consumer.h>
60 #include <linux/if_vlan.h>
61 #include <linux/pinctrl/consumer.h>
62 #include <linux/prefetch.h>
63 #include <soc/imx/cpuidle.h>
64
65 #include <asm/cacheflush.h>
66
67 #include "fec.h"
68
69 static void set_multicast_list(struct net_device *ndev);
70 static void fec_enet_itr_coal_init(struct net_device *ndev);
71
72 #define DRIVER_NAME "fec"
73
74 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
75
76 /* Pause frame feild and FIFO threshold */
77 #define FEC_ENET_FCE (1 << 5)
78 #define FEC_ENET_RSEM_V 0x84
79 #define FEC_ENET_RSFL_V 16
80 #define FEC_ENET_RAEM_V 0x8
81 #define FEC_ENET_RAFL_V 0x8
82 #define FEC_ENET_OPD_V 0xFFF0
83 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */
84
85 static struct platform_device_id fec_devtype[] = {
86 {
87 /* keep it for coldfire */
88 .name = DRIVER_NAME,
89 .driver_data = 0,
90 }, {
91 .name = "imx25-fec",
92 .driver_data = FEC_QUIRK_USE_GASKET,
93 }, {
94 .name = "imx27-fec",
95 .driver_data = 0,
96 }, {
97 .name = "imx28-fec",
98 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
99 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC,
100 }, {
101 .name = "imx6q-fec",
102 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
103 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
104 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
105 FEC_QUIRK_HAS_RACC,
106 }, {
107 .name = "mvf600-fec",
108 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
109 }, {
110 .name = "imx6sx-fec",
111 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
112 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
113 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
114 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
115 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE,
116 }, {
117 .name = "imx6ul-fec",
118 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
119 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
120 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 |
121 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC |
122 FEC_QUIRK_HAS_COALESCE,
123 }, {
124 /* sentinel */
125 }
126 };
127 MODULE_DEVICE_TABLE(platform, fec_devtype);
128
129 enum imx_fec_type {
130 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
131 IMX27_FEC, /* runs on i.mx27/35/51 */
132 IMX28_FEC,
133 IMX6Q_FEC,
134 MVF600_FEC,
135 IMX6SX_FEC,
136 IMX6UL_FEC,
137 };
138
139 static const struct of_device_id fec_dt_ids[] = {
140 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
141 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
142 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
143 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
144 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
145 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
146 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
147 { /* sentinel */ }
148 };
149 MODULE_DEVICE_TABLE(of, fec_dt_ids);
150
151 static unsigned char macaddr[ETH_ALEN];
152 module_param_array(macaddr, byte, NULL, 0);
153 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
154
155 #if defined(CONFIG_M5272)
156 /*
157 * Some hardware gets it MAC address out of local flash memory.
158 * if this is non-zero then assume it is the address to get MAC from.
159 */
160 #if defined(CONFIG_NETtel)
161 #define FEC_FLASHMAC 0xf0006006
162 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
163 #define FEC_FLASHMAC 0xf0006000
164 #elif defined(CONFIG_CANCam)
165 #define FEC_FLASHMAC 0xf0020000
166 #elif defined (CONFIG_M5272C3)
167 #define FEC_FLASHMAC (0xffe04000 + 4)
168 #elif defined(CONFIG_MOD5272)
169 #define FEC_FLASHMAC 0xffc0406b
170 #else
171 #define FEC_FLASHMAC 0
172 #endif
173 #endif /* CONFIG_M5272 */
174
175 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
176 */
177 #define PKT_MAXBUF_SIZE 1522
178 #define PKT_MINBUF_SIZE 64
179 #define PKT_MAXBLR_SIZE 1536
180
181 /* FEC receive acceleration */
182 #define FEC_RACC_IPDIS (1 << 1)
183 #define FEC_RACC_PRODIS (1 << 2)
184 #define FEC_RACC_SHIFT16 BIT(7)
185 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
186
187 /*
188 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
189 * size bits. Other FEC hardware does not, so we need to take that into
190 * account when setting it.
191 */
192 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
193 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
194 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
195 #else
196 #define OPT_FRAME_SIZE 0
197 #endif
198
199 /* FEC MII MMFR bits definition */
200 #define FEC_MMFR_ST (1 << 30)
201 #define FEC_MMFR_OP_READ (2 << 28)
202 #define FEC_MMFR_OP_WRITE (1 << 28)
203 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
204 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
205 #define FEC_MMFR_TA (2 << 16)
206 #define FEC_MMFR_DATA(v) (v & 0xffff)
207 /* FEC ECR bits definition */
208 #define FEC_ECR_MAGICEN (1 << 2)
209 #define FEC_ECR_SLEEP (1 << 3)
210
211 #define FEC_MII_TIMEOUT 30000 /* us */
212
213 /* Transmitter timeout */
214 #define TX_TIMEOUT (2 * HZ)
215
216 #define FEC_PAUSE_FLAG_AUTONEG 0x1
217 #define FEC_PAUSE_FLAG_ENABLE 0x2
218 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
219 #define FEC_WOL_FLAG_ENABLE (0x1 << 1)
220 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
221
222 #define COPYBREAK_DEFAULT 256
223
224 #define TSO_HEADER_SIZE 128
225 /* Max number of allowed TCP segments for software TSO */
226 #define FEC_MAX_TSO_SEGS 100
227 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
228
229 #define IS_TSO_HEADER(txq, addr) \
230 ((addr >= txq->tso_hdrs_dma) && \
231 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
232
233 static int mii_cnt;
234
235 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
236 struct bufdesc_prop *bd)
237 {
238 return (bdp >= bd->last) ? bd->base
239 : (struct bufdesc *)(((void *)bdp) + bd->dsize);
240 }
241
242 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
243 struct bufdesc_prop *bd)
244 {
245 return (bdp <= bd->base) ? bd->last
246 : (struct bufdesc *)(((void *)bdp) - bd->dsize);
247 }
248
249 static int fec_enet_get_bd_index(struct bufdesc *bdp,
250 struct bufdesc_prop *bd)
251 {
252 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
253 }
254
255 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
256 {
257 int entries;
258
259 entries = (((const char *)txq->dirty_tx -
260 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
261
262 return entries >= 0 ? entries : entries + txq->bd.ring_size;
263 }
264
265 static void swap_buffer(void *bufaddr, int len)
266 {
267 int i;
268 unsigned int *buf = bufaddr;
269
270 for (i = 0; i < len; i += 4, buf++)
271 swab32s(buf);
272 }
273
274 static void swap_buffer2(void *dst_buf, void *src_buf, int len)
275 {
276 int i;
277 unsigned int *src = src_buf;
278 unsigned int *dst = dst_buf;
279
280 for (i = 0; i < len; i += 4, src++, dst++)
281 *dst = swab32p(src);
282 }
283
284 static void fec_dump(struct net_device *ndev)
285 {
286 struct fec_enet_private *fep = netdev_priv(ndev);
287 struct bufdesc *bdp;
288 struct fec_enet_priv_tx_q *txq;
289 int index = 0;
290
291 netdev_info(ndev, "TX ring dump\n");
292 pr_info("Nr SC addr len SKB\n");
293
294 txq = fep->tx_queue[0];
295 bdp = txq->bd.base;
296
297 do {
298 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
299 index,
300 bdp == txq->bd.cur ? 'S' : ' ',
301 bdp == txq->dirty_tx ? 'H' : ' ',
302 fec16_to_cpu(bdp->cbd_sc),
303 fec32_to_cpu(bdp->cbd_bufaddr),
304 fec16_to_cpu(bdp->cbd_datlen),
305 txq->tx_skbuff[index]);
306 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
307 index++;
308 } while (bdp != txq->bd.base);
309 }
310
311 static inline bool is_ipv4_pkt(struct sk_buff *skb)
312 {
313 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
314 }
315
316 static int
317 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
318 {
319 /* Only run for packets requiring a checksum. */
320 if (skb->ip_summed != CHECKSUM_PARTIAL)
321 return 0;
322
323 if (unlikely(skb_cow_head(skb, 0)))
324 return -1;
325
326 if (is_ipv4_pkt(skb))
327 ip_hdr(skb)->check = 0;
328 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
329
330 return 0;
331 }
332
333 static struct bufdesc *
334 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
335 struct sk_buff *skb,
336 struct net_device *ndev)
337 {
338 struct fec_enet_private *fep = netdev_priv(ndev);
339 struct bufdesc *bdp = txq->bd.cur;
340 struct bufdesc_ex *ebdp;
341 int nr_frags = skb_shinfo(skb)->nr_frags;
342 int frag, frag_len;
343 unsigned short status;
344 unsigned int estatus = 0;
345 skb_frag_t *this_frag;
346 unsigned int index;
347 void *bufaddr;
348 dma_addr_t addr;
349 int i;
350
351 for (frag = 0; frag < nr_frags; frag++) {
352 this_frag = &skb_shinfo(skb)->frags[frag];
353 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
354 ebdp = (struct bufdesc_ex *)bdp;
355
356 status = fec16_to_cpu(bdp->cbd_sc);
357 status &= ~BD_ENET_TX_STATS;
358 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
359 frag_len = skb_shinfo(skb)->frags[frag].size;
360
361 /* Handle the last BD specially */
362 if (frag == nr_frags - 1) {
363 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
364 if (fep->bufdesc_ex) {
365 estatus |= BD_ENET_TX_INT;
366 if (unlikely(skb_shinfo(skb)->tx_flags &
367 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
368 estatus |= BD_ENET_TX_TS;
369 }
370 }
371
372 if (fep->bufdesc_ex) {
373 if (fep->quirks & FEC_QUIRK_HAS_AVB)
374 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
375 if (skb->ip_summed == CHECKSUM_PARTIAL)
376 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
377 ebdp->cbd_bdu = 0;
378 ebdp->cbd_esc = cpu_to_fec32(estatus);
379 }
380
381 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
382
383 index = fec_enet_get_bd_index(bdp, &txq->bd);
384 if (((unsigned long) bufaddr) & fep->tx_align ||
385 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
386 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
387 bufaddr = txq->tx_bounce[index];
388
389 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
390 swap_buffer(bufaddr, frag_len);
391 }
392
393 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
394 DMA_TO_DEVICE);
395 if (dma_mapping_error(&fep->pdev->dev, addr)) {
396 if (net_ratelimit())
397 netdev_err(ndev, "Tx DMA memory map failed\n");
398 goto dma_mapping_error;
399 }
400
401 bdp->cbd_bufaddr = cpu_to_fec32(addr);
402 bdp->cbd_datlen = cpu_to_fec16(frag_len);
403 /* Make sure the updates to rest of the descriptor are
404 * performed before transferring ownership.
405 */
406 wmb();
407 bdp->cbd_sc = cpu_to_fec16(status);
408 }
409
410 return bdp;
411 dma_mapping_error:
412 bdp = txq->bd.cur;
413 for (i = 0; i < frag; i++) {
414 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
415 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
416 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
417 }
418 return ERR_PTR(-ENOMEM);
419 }
420
421 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
422 struct sk_buff *skb, struct net_device *ndev)
423 {
424 struct fec_enet_private *fep = netdev_priv(ndev);
425 int nr_frags = skb_shinfo(skb)->nr_frags;
426 struct bufdesc *bdp, *last_bdp;
427 void *bufaddr;
428 dma_addr_t addr;
429 unsigned short status;
430 unsigned short buflen;
431 unsigned int estatus = 0;
432 unsigned int index;
433 int entries_free;
434
435 entries_free = fec_enet_get_free_txdesc_num(txq);
436 if (entries_free < MAX_SKB_FRAGS + 1) {
437 dev_kfree_skb_any(skb);
438 if (net_ratelimit())
439 netdev_err(ndev, "NOT enough BD for SG!\n");
440 return NETDEV_TX_OK;
441 }
442
443 /* Protocol checksum off-load for TCP and UDP. */
444 if (fec_enet_clear_csum(skb, ndev)) {
445 dev_kfree_skb_any(skb);
446 return NETDEV_TX_OK;
447 }
448
449 /* Fill in a Tx ring entry */
450 bdp = txq->bd.cur;
451 last_bdp = bdp;
452 status = fec16_to_cpu(bdp->cbd_sc);
453 status &= ~BD_ENET_TX_STATS;
454
455 /* Set buffer length and buffer pointer */
456 bufaddr = skb->data;
457 buflen = skb_headlen(skb);
458
459 index = fec_enet_get_bd_index(bdp, &txq->bd);
460 if (((unsigned long) bufaddr) & fep->tx_align ||
461 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
462 memcpy(txq->tx_bounce[index], skb->data, buflen);
463 bufaddr = txq->tx_bounce[index];
464
465 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
466 swap_buffer(bufaddr, buflen);
467 }
468
469 /* Push the data cache so the CPM does not get stale memory data. */
470 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
471 if (dma_mapping_error(&fep->pdev->dev, addr)) {
472 dev_kfree_skb_any(skb);
473 if (net_ratelimit())
474 netdev_err(ndev, "Tx DMA memory map failed\n");
475 return NETDEV_TX_OK;
476 }
477
478 if (nr_frags) {
479 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
480 if (IS_ERR(last_bdp)) {
481 dma_unmap_single(&fep->pdev->dev, addr,
482 buflen, DMA_TO_DEVICE);
483 dev_kfree_skb_any(skb);
484 return NETDEV_TX_OK;
485 }
486 } else {
487 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
488 if (fep->bufdesc_ex) {
489 estatus = BD_ENET_TX_INT;
490 if (unlikely(skb_shinfo(skb)->tx_flags &
491 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
492 estatus |= BD_ENET_TX_TS;
493 }
494 }
495 bdp->cbd_bufaddr = cpu_to_fec32(addr);
496 bdp->cbd_datlen = cpu_to_fec16(buflen);
497
498 if (fep->bufdesc_ex) {
499
500 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
501
502 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
503 fep->hwts_tx_en))
504 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
505
506 if (fep->quirks & FEC_QUIRK_HAS_AVB)
507 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
508
509 if (skb->ip_summed == CHECKSUM_PARTIAL)
510 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
511
512 ebdp->cbd_bdu = 0;
513 ebdp->cbd_esc = cpu_to_fec32(estatus);
514 }
515
516 index = fec_enet_get_bd_index(last_bdp, &txq->bd);
517 /* Save skb pointer */
518 txq->tx_skbuff[index] = skb;
519
520 /* Make sure the updates to rest of the descriptor are performed before
521 * transferring ownership.
522 */
523 wmb();
524
525 /* Send it on its way. Tell FEC it's ready, interrupt when done,
526 * it's the last BD of the frame, and to put the CRC on the end.
527 */
528 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
529 bdp->cbd_sc = cpu_to_fec16(status);
530
531 /* If this was the last BD in the ring, start at the beginning again. */
532 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
533
534 skb_tx_timestamp(skb);
535
536 /* Make sure the update to bdp and tx_skbuff are performed before
537 * txq->bd.cur.
538 */
539 wmb();
540 txq->bd.cur = bdp;
541
542 /* Trigger transmission start */
543 writel(0, txq->bd.reg_desc_active);
544
545 return 0;
546 }
547
548 static int
549 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
550 struct net_device *ndev,
551 struct bufdesc *bdp, int index, char *data,
552 int size, bool last_tcp, bool is_last)
553 {
554 struct fec_enet_private *fep = netdev_priv(ndev);
555 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
556 unsigned short status;
557 unsigned int estatus = 0;
558 dma_addr_t addr;
559
560 status = fec16_to_cpu(bdp->cbd_sc);
561 status &= ~BD_ENET_TX_STATS;
562
563 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
564
565 if (((unsigned long) data) & fep->tx_align ||
566 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
567 memcpy(txq->tx_bounce[index], data, size);
568 data = txq->tx_bounce[index];
569
570 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
571 swap_buffer(data, size);
572 }
573
574 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
575 if (dma_mapping_error(&fep->pdev->dev, addr)) {
576 dev_kfree_skb_any(skb);
577 if (net_ratelimit())
578 netdev_err(ndev, "Tx DMA memory map failed\n");
579 return NETDEV_TX_BUSY;
580 }
581
582 bdp->cbd_datlen = cpu_to_fec16(size);
583 bdp->cbd_bufaddr = cpu_to_fec32(addr);
584
585 if (fep->bufdesc_ex) {
586 if (fep->quirks & FEC_QUIRK_HAS_AVB)
587 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
588 if (skb->ip_summed == CHECKSUM_PARTIAL)
589 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
590 ebdp->cbd_bdu = 0;
591 ebdp->cbd_esc = cpu_to_fec32(estatus);
592 }
593
594 /* Handle the last BD specially */
595 if (last_tcp)
596 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
597 if (is_last) {
598 status |= BD_ENET_TX_INTR;
599 if (fep->bufdesc_ex)
600 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
601 }
602
603 bdp->cbd_sc = cpu_to_fec16(status);
604
605 return 0;
606 }
607
608 static int
609 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
610 struct sk_buff *skb, struct net_device *ndev,
611 struct bufdesc *bdp, int index)
612 {
613 struct fec_enet_private *fep = netdev_priv(ndev);
614 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
615 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
616 void *bufaddr;
617 unsigned long dmabuf;
618 unsigned short status;
619 unsigned int estatus = 0;
620
621 status = fec16_to_cpu(bdp->cbd_sc);
622 status &= ~BD_ENET_TX_STATS;
623 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
624
625 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
626 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
627 if (((unsigned long)bufaddr) & fep->tx_align ||
628 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
629 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
630 bufaddr = txq->tx_bounce[index];
631
632 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
633 swap_buffer(bufaddr, hdr_len);
634
635 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
636 hdr_len, DMA_TO_DEVICE);
637 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
638 dev_kfree_skb_any(skb);
639 if (net_ratelimit())
640 netdev_err(ndev, "Tx DMA memory map failed\n");
641 return NETDEV_TX_BUSY;
642 }
643 }
644
645 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
646 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
647
648 if (fep->bufdesc_ex) {
649 if (fep->quirks & FEC_QUIRK_HAS_AVB)
650 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
651 if (skb->ip_summed == CHECKSUM_PARTIAL)
652 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
653 ebdp->cbd_bdu = 0;
654 ebdp->cbd_esc = cpu_to_fec32(estatus);
655 }
656
657 bdp->cbd_sc = cpu_to_fec16(status);
658
659 return 0;
660 }
661
662 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
663 struct sk_buff *skb,
664 struct net_device *ndev)
665 {
666 struct fec_enet_private *fep = netdev_priv(ndev);
667 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
668 int total_len, data_left;
669 struct bufdesc *bdp = txq->bd.cur;
670 struct tso_t tso;
671 unsigned int index = 0;
672 int ret;
673
674 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
675 dev_kfree_skb_any(skb);
676 if (net_ratelimit())
677 netdev_err(ndev, "NOT enough BD for TSO!\n");
678 return NETDEV_TX_OK;
679 }
680
681 /* Protocol checksum off-load for TCP and UDP. */
682 if (fec_enet_clear_csum(skb, ndev)) {
683 dev_kfree_skb_any(skb);
684 return NETDEV_TX_OK;
685 }
686
687 /* Initialize the TSO handler, and prepare the first payload */
688 tso_start(skb, &tso);
689
690 total_len = skb->len - hdr_len;
691 while (total_len > 0) {
692 char *hdr;
693
694 index = fec_enet_get_bd_index(bdp, &txq->bd);
695 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
696 total_len -= data_left;
697
698 /* prepare packet headers: MAC + IP + TCP */
699 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
700 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
701 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
702 if (ret)
703 goto err_release;
704
705 while (data_left > 0) {
706 int size;
707
708 size = min_t(int, tso.size, data_left);
709 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
710 index = fec_enet_get_bd_index(bdp, &txq->bd);
711 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
712 bdp, index,
713 tso.data, size,
714 size == data_left,
715 total_len == 0);
716 if (ret)
717 goto err_release;
718
719 data_left -= size;
720 tso_build_data(skb, &tso, size);
721 }
722
723 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
724 }
725
726 /* Save skb pointer */
727 txq->tx_skbuff[index] = skb;
728
729 skb_tx_timestamp(skb);
730 txq->bd.cur = bdp;
731
732 /* Trigger transmission start */
733 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
734 !readl(txq->bd.reg_desc_active) ||
735 !readl(txq->bd.reg_desc_active) ||
736 !readl(txq->bd.reg_desc_active) ||
737 !readl(txq->bd.reg_desc_active))
738 writel(0, txq->bd.reg_desc_active);
739
740 return 0;
741
742 err_release:
743 /* TODO: Release all used data descriptors for TSO */
744 return ret;
745 }
746
747 static netdev_tx_t
748 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
749 {
750 struct fec_enet_private *fep = netdev_priv(ndev);
751 int entries_free;
752 unsigned short queue;
753 struct fec_enet_priv_tx_q *txq;
754 struct netdev_queue *nq;
755 int ret;
756
757 queue = skb_get_queue_mapping(skb);
758 txq = fep->tx_queue[queue];
759 nq = netdev_get_tx_queue(ndev, queue);
760
761 if (skb_is_gso(skb))
762 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
763 else
764 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
765 if (ret)
766 return ret;
767
768 entries_free = fec_enet_get_free_txdesc_num(txq);
769 if (entries_free <= txq->tx_stop_threshold)
770 netif_tx_stop_queue(nq);
771
772 return NETDEV_TX_OK;
773 }
774
775 /* Init RX & TX buffer descriptors
776 */
777 static void fec_enet_bd_init(struct net_device *dev)
778 {
779 struct fec_enet_private *fep = netdev_priv(dev);
780 struct fec_enet_priv_tx_q *txq;
781 struct fec_enet_priv_rx_q *rxq;
782 struct bufdesc *bdp;
783 unsigned int i;
784 unsigned int q;
785
786 for (q = 0; q < fep->num_rx_queues; q++) {
787 /* Initialize the receive buffer descriptors. */
788 rxq = fep->rx_queue[q];
789 bdp = rxq->bd.base;
790
791 for (i = 0; i < rxq->bd.ring_size; i++) {
792
793 /* Initialize the BD for every fragment in the page. */
794 if (bdp->cbd_bufaddr)
795 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
796 else
797 bdp->cbd_sc = cpu_to_fec16(0);
798 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
799 }
800
801 /* Set the last buffer to wrap */
802 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
803 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
804
805 rxq->bd.cur = rxq->bd.base;
806 }
807
808 for (q = 0; q < fep->num_tx_queues; q++) {
809 /* ...and the same for transmit */
810 txq = fep->tx_queue[q];
811 bdp = txq->bd.base;
812 txq->bd.cur = bdp;
813
814 for (i = 0; i < txq->bd.ring_size; i++) {
815 /* Initialize the BD for every fragment in the page. */
816 bdp->cbd_sc = cpu_to_fec16(0);
817 if (txq->tx_skbuff[i]) {
818 dev_kfree_skb_any(txq->tx_skbuff[i]);
819 txq->tx_skbuff[i] = NULL;
820 }
821 bdp->cbd_bufaddr = cpu_to_fec32(0);
822 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
823 }
824
825 /* Set the last buffer to wrap */
826 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
827 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
828 txq->dirty_tx = bdp;
829 }
830 }
831
832 static void fec_enet_active_rxring(struct net_device *ndev)
833 {
834 struct fec_enet_private *fep = netdev_priv(ndev);
835 int i;
836
837 for (i = 0; i < fep->num_rx_queues; i++)
838 writel(0, fep->rx_queue[i]->bd.reg_desc_active);
839 }
840
841 static void fec_enet_enable_ring(struct net_device *ndev)
842 {
843 struct fec_enet_private *fep = netdev_priv(ndev);
844 struct fec_enet_priv_tx_q *txq;
845 struct fec_enet_priv_rx_q *rxq;
846 int i;
847
848 for (i = 0; i < fep->num_rx_queues; i++) {
849 rxq = fep->rx_queue[i];
850 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
851 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
852
853 /* enable DMA1/2 */
854 if (i)
855 writel(RCMR_MATCHEN | RCMR_CMP(i),
856 fep->hwp + FEC_RCMR(i));
857 }
858
859 for (i = 0; i < fep->num_tx_queues; i++) {
860 txq = fep->tx_queue[i];
861 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
862
863 /* enable DMA1/2 */
864 if (i)
865 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
866 fep->hwp + FEC_DMA_CFG(i));
867 }
868 }
869
870 static void fec_enet_reset_skb(struct net_device *ndev)
871 {
872 struct fec_enet_private *fep = netdev_priv(ndev);
873 struct fec_enet_priv_tx_q *txq;
874 int i, j;
875
876 for (i = 0; i < fep->num_tx_queues; i++) {
877 txq = fep->tx_queue[i];
878
879 for (j = 0; j < txq->bd.ring_size; j++) {
880 if (txq->tx_skbuff[j]) {
881 dev_kfree_skb_any(txq->tx_skbuff[j]);
882 txq->tx_skbuff[j] = NULL;
883 }
884 }
885 }
886 }
887
888 /*
889 * This function is called to start or restart the FEC during a link
890 * change, transmit timeout, or to reconfigure the FEC. The network
891 * packet processing for this device must be stopped before this call.
892 */
893 static void
894 fec_restart(struct net_device *ndev)
895 {
896 struct fec_enet_private *fep = netdev_priv(ndev);
897 u32 val;
898 u32 temp_mac[2];
899 u32 rcntl = OPT_FRAME_SIZE | 0x04;
900 u32 ecntl = 0x2; /* ETHEREN */
901
902 /* Whack a reset. We should wait for this.
903 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
904 * instead of reset MAC itself.
905 */
906 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
907 writel(0, fep->hwp + FEC_ECNTRL);
908 } else {
909 writel(1, fep->hwp + FEC_ECNTRL);
910 udelay(10);
911 }
912
913 /*
914 * enet-mac reset will reset mac address registers too,
915 * so need to reconfigure it.
916 */
917 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
918 writel((__force u32)cpu_to_be32(temp_mac[0]),
919 fep->hwp + FEC_ADDR_LOW);
920 writel((__force u32)cpu_to_be32(temp_mac[1]),
921 fep->hwp + FEC_ADDR_HIGH);
922
923 /* Clear any outstanding interrupt. */
924 writel(0xffffffff, fep->hwp + FEC_IEVENT);
925
926 fec_enet_bd_init(ndev);
927
928 fec_enet_enable_ring(ndev);
929
930 /* Reset tx SKB buffers. */
931 fec_enet_reset_skb(ndev);
932
933 /* Enable MII mode */
934 if (fep->full_duplex == DUPLEX_FULL) {
935 /* FD enable */
936 writel(0x04, fep->hwp + FEC_X_CNTRL);
937 } else {
938 /* No Rcv on Xmit */
939 rcntl |= 0x02;
940 writel(0x0, fep->hwp + FEC_X_CNTRL);
941 }
942
943 /* Set MII speed */
944 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
945
946 #if !defined(CONFIG_M5272)
947 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
948 val = readl(fep->hwp + FEC_RACC);
949 /* align IP header */
950 val |= FEC_RACC_SHIFT16;
951 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
952 /* set RX checksum */
953 val |= FEC_RACC_OPTIONS;
954 else
955 val &= ~FEC_RACC_OPTIONS;
956 writel(val, fep->hwp + FEC_RACC);
957 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
958 }
959 #endif
960
961 /*
962 * The phy interface and speed need to get configured
963 * differently on enet-mac.
964 */
965 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
966 /* Enable flow control and length check */
967 rcntl |= 0x40000000 | 0x00000020;
968
969 /* RGMII, RMII or MII */
970 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
971 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
972 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
973 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
974 rcntl |= (1 << 6);
975 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
976 rcntl |= (1 << 8);
977 else
978 rcntl &= ~(1 << 8);
979
980 /* 1G, 100M or 10M */
981 if (ndev->phydev) {
982 if (ndev->phydev->speed == SPEED_1000)
983 ecntl |= (1 << 5);
984 else if (ndev->phydev->speed == SPEED_100)
985 rcntl &= ~(1 << 9);
986 else
987 rcntl |= (1 << 9);
988 }
989 } else {
990 #ifdef FEC_MIIGSK_ENR
991 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
992 u32 cfgr;
993 /* disable the gasket and wait */
994 writel(0, fep->hwp + FEC_MIIGSK_ENR);
995 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
996 udelay(1);
997
998 /*
999 * configure the gasket:
1000 * RMII, 50 MHz, no loopback, no echo
1001 * MII, 25 MHz, no loopback, no echo
1002 */
1003 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1004 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1005 if (ndev->phydev && ndev->phydev->speed == SPEED_10)
1006 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1007 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1008
1009 /* re-enable the gasket */
1010 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1011 }
1012 #endif
1013 }
1014
1015 #if !defined(CONFIG_M5272)
1016 /* enable pause frame*/
1017 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1018 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1019 ndev->phydev && ndev->phydev->pause)) {
1020 rcntl |= FEC_ENET_FCE;
1021
1022 /* set FIFO threshold parameter to reduce overrun */
1023 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1024 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1025 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1026 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1027
1028 /* OPD */
1029 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1030 } else {
1031 rcntl &= ~FEC_ENET_FCE;
1032 }
1033 #endif /* !defined(CONFIG_M5272) */
1034
1035 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1036
1037 /* Setup multicast filter. */
1038 set_multicast_list(ndev);
1039 #ifndef CONFIG_M5272
1040 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1041 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1042 #endif
1043
1044 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1045 /* enable ENET endian swap */
1046 ecntl |= (1 << 8);
1047 /* enable ENET store and forward mode */
1048 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1049 }
1050
1051 if (fep->bufdesc_ex)
1052 ecntl |= (1 << 4);
1053
1054 #ifndef CONFIG_M5272
1055 /* Enable the MIB statistic event counters */
1056 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1057 #endif
1058
1059 /* And last, enable the transmit and receive processing */
1060 writel(ecntl, fep->hwp + FEC_ECNTRL);
1061 fec_enet_active_rxring(ndev);
1062
1063 if (fep->bufdesc_ex)
1064 fec_ptp_start_cyclecounter(ndev);
1065
1066 /* Enable interrupts we wish to service */
1067 if (fep->link)
1068 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1069 else
1070 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1071
1072 /* Init the interrupt coalescing */
1073 fec_enet_itr_coal_init(ndev);
1074
1075 }
1076
1077 static void
1078 fec_stop(struct net_device *ndev)
1079 {
1080 struct fec_enet_private *fep = netdev_priv(ndev);
1081 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1082 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1083 u32 val;
1084
1085 /* We cannot expect a graceful transmit stop without link !!! */
1086 if (fep->link) {
1087 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1088 udelay(10);
1089 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1090 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1091 }
1092
1093 /* Whack a reset. We should wait for this.
1094 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1095 * instead of reset MAC itself.
1096 */
1097 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1098 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1099 writel(0, fep->hwp + FEC_ECNTRL);
1100 } else {
1101 writel(1, fep->hwp + FEC_ECNTRL);
1102 udelay(10);
1103 }
1104 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1105 } else {
1106 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1107 val = readl(fep->hwp + FEC_ECNTRL);
1108 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1109 writel(val, fep->hwp + FEC_ECNTRL);
1110
1111 if (pdata && pdata->sleep_mode_enable)
1112 pdata->sleep_mode_enable(true);
1113 }
1114 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1115
1116 /* We have to keep ENET enabled to have MII interrupt stay working */
1117 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1118 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1119 writel(2, fep->hwp + FEC_ECNTRL);
1120 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1121 }
1122 }
1123
1124
1125 static void
1126 fec_timeout(struct net_device *ndev)
1127 {
1128 struct fec_enet_private *fep = netdev_priv(ndev);
1129
1130 fec_dump(ndev);
1131
1132 ndev->stats.tx_errors++;
1133
1134 schedule_work(&fep->tx_timeout_work);
1135 }
1136
1137 static void fec_enet_timeout_work(struct work_struct *work)
1138 {
1139 struct fec_enet_private *fep =
1140 container_of(work, struct fec_enet_private, tx_timeout_work);
1141 struct net_device *ndev = fep->netdev;
1142
1143 rtnl_lock();
1144 if (netif_device_present(ndev) || netif_running(ndev)) {
1145 napi_disable(&fep->napi);
1146 netif_tx_lock_bh(ndev);
1147 fec_restart(ndev);
1148 netif_wake_queue(ndev);
1149 netif_tx_unlock_bh(ndev);
1150 napi_enable(&fep->napi);
1151 }
1152 rtnl_unlock();
1153 }
1154
1155 static void
1156 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1157 struct skb_shared_hwtstamps *hwtstamps)
1158 {
1159 unsigned long flags;
1160 u64 ns;
1161
1162 spin_lock_irqsave(&fep->tmreg_lock, flags);
1163 ns = timecounter_cyc2time(&fep->tc, ts);
1164 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1165
1166 memset(hwtstamps, 0, sizeof(*hwtstamps));
1167 hwtstamps->hwtstamp = ns_to_ktime(ns);
1168 }
1169
1170 static void
1171 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1172 {
1173 struct fec_enet_private *fep;
1174 struct bufdesc *bdp;
1175 unsigned short status;
1176 struct sk_buff *skb;
1177 struct fec_enet_priv_tx_q *txq;
1178 struct netdev_queue *nq;
1179 int index = 0;
1180 int entries_free;
1181
1182 fep = netdev_priv(ndev);
1183
1184 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1185
1186 txq = fep->tx_queue[queue_id];
1187 /* get next bdp of dirty_tx */
1188 nq = netdev_get_tx_queue(ndev, queue_id);
1189 bdp = txq->dirty_tx;
1190
1191 /* get next bdp of dirty_tx */
1192 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1193
1194 while (bdp != READ_ONCE(txq->bd.cur)) {
1195 /* Order the load of bd.cur and cbd_sc */
1196 rmb();
1197 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1198 if (status & BD_ENET_TX_READY)
1199 break;
1200
1201 index = fec_enet_get_bd_index(bdp, &txq->bd);
1202
1203 skb = txq->tx_skbuff[index];
1204 txq->tx_skbuff[index] = NULL;
1205 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1206 dma_unmap_single(&fep->pdev->dev,
1207 fec32_to_cpu(bdp->cbd_bufaddr),
1208 fec16_to_cpu(bdp->cbd_datlen),
1209 DMA_TO_DEVICE);
1210 bdp->cbd_bufaddr = cpu_to_fec32(0);
1211 if (!skb)
1212 goto skb_done;
1213
1214 /* Check for errors. */
1215 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1216 BD_ENET_TX_RL | BD_ENET_TX_UN |
1217 BD_ENET_TX_CSL)) {
1218 ndev->stats.tx_errors++;
1219 if (status & BD_ENET_TX_HB) /* No heartbeat */
1220 ndev->stats.tx_heartbeat_errors++;
1221 if (status & BD_ENET_TX_LC) /* Late collision */
1222 ndev->stats.tx_window_errors++;
1223 if (status & BD_ENET_TX_RL) /* Retrans limit */
1224 ndev->stats.tx_aborted_errors++;
1225 if (status & BD_ENET_TX_UN) /* Underrun */
1226 ndev->stats.tx_fifo_errors++;
1227 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1228 ndev->stats.tx_carrier_errors++;
1229 } else {
1230 ndev->stats.tx_packets++;
1231 ndev->stats.tx_bytes += skb->len;
1232 }
1233
1234 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1235 fep->bufdesc_ex) {
1236 struct skb_shared_hwtstamps shhwtstamps;
1237 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1238
1239 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1240 skb_tstamp_tx(skb, &shhwtstamps);
1241 }
1242
1243 /* Deferred means some collisions occurred during transmit,
1244 * but we eventually sent the packet OK.
1245 */
1246 if (status & BD_ENET_TX_DEF)
1247 ndev->stats.collisions++;
1248
1249 /* Free the sk buffer associated with this last transmit */
1250 dev_kfree_skb_any(skb);
1251 skb_done:
1252 /* Make sure the update to bdp and tx_skbuff are performed
1253 * before dirty_tx
1254 */
1255 wmb();
1256 txq->dirty_tx = bdp;
1257
1258 /* Update pointer to next buffer descriptor to be transmitted */
1259 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1260
1261 /* Since we have freed up a buffer, the ring is no longer full
1262 */
1263 if (netif_queue_stopped(ndev)) {
1264 entries_free = fec_enet_get_free_txdesc_num(txq);
1265 if (entries_free >= txq->tx_wake_threshold)
1266 netif_tx_wake_queue(nq);
1267 }
1268 }
1269
1270 /* ERR006358: Keep the transmitter going */
1271 if (bdp != txq->bd.cur &&
1272 readl(txq->bd.reg_desc_active) == 0)
1273 writel(0, txq->bd.reg_desc_active);
1274 }
1275
1276 static void
1277 fec_enet_tx(struct net_device *ndev)
1278 {
1279 struct fec_enet_private *fep = netdev_priv(ndev);
1280 u16 queue_id;
1281 /* First process class A queue, then Class B and Best Effort queue */
1282 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1283 clear_bit(queue_id, &fep->work_tx);
1284 fec_enet_tx_queue(ndev, queue_id);
1285 }
1286 return;
1287 }
1288
1289 static int
1290 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1291 {
1292 struct fec_enet_private *fep = netdev_priv(ndev);
1293 int off;
1294
1295 off = ((unsigned long)skb->data) & fep->rx_align;
1296 if (off)
1297 skb_reserve(skb, fep->rx_align + 1 - off);
1298
1299 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE));
1300 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) {
1301 if (net_ratelimit())
1302 netdev_err(ndev, "Rx DMA memory map failed\n");
1303 return -ENOMEM;
1304 }
1305
1306 return 0;
1307 }
1308
1309 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1310 struct bufdesc *bdp, u32 length, bool swap)
1311 {
1312 struct fec_enet_private *fep = netdev_priv(ndev);
1313 struct sk_buff *new_skb;
1314
1315 if (length > fep->rx_copybreak)
1316 return false;
1317
1318 new_skb = netdev_alloc_skb(ndev, length);
1319 if (!new_skb)
1320 return false;
1321
1322 dma_sync_single_for_cpu(&fep->pdev->dev,
1323 fec32_to_cpu(bdp->cbd_bufaddr),
1324 FEC_ENET_RX_FRSIZE - fep->rx_align,
1325 DMA_FROM_DEVICE);
1326 if (!swap)
1327 memcpy(new_skb->data, (*skb)->data, length);
1328 else
1329 swap_buffer2(new_skb->data, (*skb)->data, length);
1330 *skb = new_skb;
1331
1332 return true;
1333 }
1334
1335 /* During a receive, the bd_rx.cur points to the current incoming buffer.
1336 * When we update through the ring, if the next incoming buffer has
1337 * not been given to the system, we just set the empty indicator,
1338 * effectively tossing the packet.
1339 */
1340 static int
1341 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1342 {
1343 struct fec_enet_private *fep = netdev_priv(ndev);
1344 struct fec_enet_priv_rx_q *rxq;
1345 struct bufdesc *bdp;
1346 unsigned short status;
1347 struct sk_buff *skb_new = NULL;
1348 struct sk_buff *skb;
1349 ushort pkt_len;
1350 __u8 *data;
1351 int pkt_received = 0;
1352 struct bufdesc_ex *ebdp = NULL;
1353 bool vlan_packet_rcvd = false;
1354 u16 vlan_tag;
1355 int index = 0;
1356 bool is_copybreak;
1357 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1358
1359 #ifdef CONFIG_M532x
1360 flush_cache_all();
1361 #endif
1362 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1363 rxq = fep->rx_queue[queue_id];
1364
1365 /* First, grab all of the stats for the incoming packet.
1366 * These get messed up if we get called due to a busy condition.
1367 */
1368 bdp = rxq->bd.cur;
1369
1370 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1371
1372 if (pkt_received >= budget)
1373 break;
1374 pkt_received++;
1375
1376 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
1377
1378 /* Check for errors. */
1379 status ^= BD_ENET_RX_LAST;
1380 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1381 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1382 BD_ENET_RX_CL)) {
1383 ndev->stats.rx_errors++;
1384 if (status & BD_ENET_RX_OV) {
1385 /* FIFO overrun */
1386 ndev->stats.rx_fifo_errors++;
1387 goto rx_processing_done;
1388 }
1389 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1390 | BD_ENET_RX_LAST)) {
1391 /* Frame too long or too short. */
1392 ndev->stats.rx_length_errors++;
1393 if (status & BD_ENET_RX_LAST)
1394 netdev_err(ndev, "rcv is not +last\n");
1395 }
1396 if (status & BD_ENET_RX_CR) /* CRC Error */
1397 ndev->stats.rx_crc_errors++;
1398 /* Report late collisions as a frame error. */
1399 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1400 ndev->stats.rx_frame_errors++;
1401 goto rx_processing_done;
1402 }
1403
1404 /* Process the incoming frame. */
1405 ndev->stats.rx_packets++;
1406 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1407 ndev->stats.rx_bytes += pkt_len;
1408
1409 index = fec_enet_get_bd_index(bdp, &rxq->bd);
1410 skb = rxq->rx_skbuff[index];
1411
1412 /* The packet length includes FCS, but we don't want to
1413 * include that when passing upstream as it messes up
1414 * bridging applications.
1415 */
1416 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1417 need_swap);
1418 if (!is_copybreak) {
1419 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1420 if (unlikely(!skb_new)) {
1421 ndev->stats.rx_dropped++;
1422 goto rx_processing_done;
1423 }
1424 dma_unmap_single(&fep->pdev->dev,
1425 fec32_to_cpu(bdp->cbd_bufaddr),
1426 FEC_ENET_RX_FRSIZE - fep->rx_align,
1427 DMA_FROM_DEVICE);
1428 }
1429
1430 prefetch(skb->data - NET_IP_ALIGN);
1431 skb_put(skb, pkt_len - 4);
1432 data = skb->data;
1433
1434 if (!is_copybreak && need_swap)
1435 swap_buffer(data, pkt_len);
1436
1437 #if !defined(CONFIG_M5272)
1438 if (fep->quirks & FEC_QUIRK_HAS_RACC)
1439 data = skb_pull_inline(skb, 2);
1440 #endif
1441
1442 /* Extract the enhanced buffer descriptor */
1443 ebdp = NULL;
1444 if (fep->bufdesc_ex)
1445 ebdp = (struct bufdesc_ex *)bdp;
1446
1447 /* If this is a VLAN packet remove the VLAN Tag */
1448 vlan_packet_rcvd = false;
1449 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1450 fep->bufdesc_ex &&
1451 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1452 /* Push and remove the vlan tag */
1453 struct vlan_hdr *vlan_header =
1454 (struct vlan_hdr *) (data + ETH_HLEN);
1455 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1456
1457 vlan_packet_rcvd = true;
1458
1459 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1460 skb_pull(skb, VLAN_HLEN);
1461 }
1462
1463 skb->protocol = eth_type_trans(skb, ndev);
1464
1465 /* Get receive timestamp from the skb */
1466 if (fep->hwts_rx_en && fep->bufdesc_ex)
1467 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1468 skb_hwtstamps(skb));
1469
1470 if (fep->bufdesc_ex &&
1471 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1472 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1473 /* don't check it */
1474 skb->ip_summed = CHECKSUM_UNNECESSARY;
1475 } else {
1476 skb_checksum_none_assert(skb);
1477 }
1478 }
1479
1480 /* Handle received VLAN packets */
1481 if (vlan_packet_rcvd)
1482 __vlan_hwaccel_put_tag(skb,
1483 htons(ETH_P_8021Q),
1484 vlan_tag);
1485
1486 napi_gro_receive(&fep->napi, skb);
1487
1488 if (is_copybreak) {
1489 dma_sync_single_for_device(&fep->pdev->dev,
1490 fec32_to_cpu(bdp->cbd_bufaddr),
1491 FEC_ENET_RX_FRSIZE - fep->rx_align,
1492 DMA_FROM_DEVICE);
1493 } else {
1494 rxq->rx_skbuff[index] = skb_new;
1495 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1496 }
1497
1498 rx_processing_done:
1499 /* Clear the status flags for this buffer */
1500 status &= ~BD_ENET_RX_STATS;
1501
1502 /* Mark the buffer empty */
1503 status |= BD_ENET_RX_EMPTY;
1504
1505 if (fep->bufdesc_ex) {
1506 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1507
1508 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1509 ebdp->cbd_prot = 0;
1510 ebdp->cbd_bdu = 0;
1511 }
1512 /* Make sure the updates to rest of the descriptor are
1513 * performed before transferring ownership.
1514 */
1515 wmb();
1516 bdp->cbd_sc = cpu_to_fec16(status);
1517
1518 /* Update BD pointer to next entry */
1519 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1520
1521 /* Doing this here will keep the FEC running while we process
1522 * incoming frames. On a heavily loaded network, we should be
1523 * able to keep up at the expense of system resources.
1524 */
1525 writel(0, rxq->bd.reg_desc_active);
1526 }
1527 rxq->bd.cur = bdp;
1528 return pkt_received;
1529 }
1530
1531 static int
1532 fec_enet_rx(struct net_device *ndev, int budget)
1533 {
1534 int pkt_received = 0;
1535 u16 queue_id;
1536 struct fec_enet_private *fep = netdev_priv(ndev);
1537
1538 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1539 int ret;
1540
1541 ret = fec_enet_rx_queue(ndev,
1542 budget - pkt_received, queue_id);
1543
1544 if (ret < budget - pkt_received)
1545 clear_bit(queue_id, &fep->work_rx);
1546
1547 pkt_received += ret;
1548 }
1549 return pkt_received;
1550 }
1551
1552 static bool
1553 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1554 {
1555 if (int_events == 0)
1556 return false;
1557
1558 if (int_events & FEC_ENET_RXF)
1559 fep->work_rx |= (1 << 2);
1560 if (int_events & FEC_ENET_RXF_1)
1561 fep->work_rx |= (1 << 0);
1562 if (int_events & FEC_ENET_RXF_2)
1563 fep->work_rx |= (1 << 1);
1564
1565 if (int_events & FEC_ENET_TXF)
1566 fep->work_tx |= (1 << 2);
1567 if (int_events & FEC_ENET_TXF_1)
1568 fep->work_tx |= (1 << 0);
1569 if (int_events & FEC_ENET_TXF_2)
1570 fep->work_tx |= (1 << 1);
1571
1572 return true;
1573 }
1574
1575 static irqreturn_t
1576 fec_enet_interrupt(int irq, void *dev_id)
1577 {
1578 struct net_device *ndev = dev_id;
1579 struct fec_enet_private *fep = netdev_priv(ndev);
1580 uint int_events;
1581 irqreturn_t ret = IRQ_NONE;
1582
1583 int_events = readl(fep->hwp + FEC_IEVENT);
1584 writel(int_events, fep->hwp + FEC_IEVENT);
1585 fec_enet_collect_events(fep, int_events);
1586
1587 if ((fep->work_tx || fep->work_rx) && fep->link) {
1588 ret = IRQ_HANDLED;
1589
1590 if (napi_schedule_prep(&fep->napi)) {
1591 /* Disable the NAPI interrupts */
1592 writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK);
1593 __napi_schedule(&fep->napi);
1594 }
1595 }
1596
1597 if (int_events & FEC_ENET_MII) {
1598 ret = IRQ_HANDLED;
1599 complete(&fep->mdio_done);
1600 }
1601
1602 if (fep->ptp_clock)
1603 fec_ptp_check_pps_event(fep);
1604
1605 return ret;
1606 }
1607
1608 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1609 {
1610 struct net_device *ndev = napi->dev;
1611 struct fec_enet_private *fep = netdev_priv(ndev);
1612 int pkts;
1613
1614 pkts = fec_enet_rx(ndev, budget);
1615
1616 fec_enet_tx(ndev);
1617
1618 if (pkts < budget) {
1619 napi_complete_done(napi, pkts);
1620 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1621 }
1622 return pkts;
1623 }
1624
1625 /* ------------------------------------------------------------------------- */
1626 static void fec_get_mac(struct net_device *ndev)
1627 {
1628 struct fec_enet_private *fep = netdev_priv(ndev);
1629 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1630 unsigned char *iap, tmpaddr[ETH_ALEN];
1631
1632 /*
1633 * try to get mac address in following order:
1634 *
1635 * 1) module parameter via kernel command line in form
1636 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1637 */
1638 iap = macaddr;
1639
1640 /*
1641 * 2) from device tree data
1642 */
1643 if (!is_valid_ether_addr(iap)) {
1644 struct device_node *np = fep->pdev->dev.of_node;
1645 if (np) {
1646 const char *mac = of_get_mac_address(np);
1647 if (mac)
1648 iap = (unsigned char *) mac;
1649 }
1650 }
1651
1652 /*
1653 * 3) from flash or fuse (via platform data)
1654 */
1655 if (!is_valid_ether_addr(iap)) {
1656 #ifdef CONFIG_M5272
1657 if (FEC_FLASHMAC)
1658 iap = (unsigned char *)FEC_FLASHMAC;
1659 #else
1660 if (pdata)
1661 iap = (unsigned char *)&pdata->mac;
1662 #endif
1663 }
1664
1665 /*
1666 * 4) FEC mac registers set by bootloader
1667 */
1668 if (!is_valid_ether_addr(iap)) {
1669 *((__be32 *) &tmpaddr[0]) =
1670 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1671 *((__be16 *) &tmpaddr[4]) =
1672 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1673 iap = &tmpaddr[0];
1674 }
1675
1676 /*
1677 * 5) random mac address
1678 */
1679 if (!is_valid_ether_addr(iap)) {
1680 /* Report it and use a random ethernet address instead */
1681 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1682 eth_hw_addr_random(ndev);
1683 netdev_info(ndev, "Using random MAC address: %pM\n",
1684 ndev->dev_addr);
1685 return;
1686 }
1687
1688 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1689
1690 /* Adjust MAC if using macaddr */
1691 if (iap == macaddr)
1692 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1693 }
1694
1695 /* ------------------------------------------------------------------------- */
1696
1697 /*
1698 * Phy section
1699 */
1700 static void fec_enet_adjust_link(struct net_device *ndev)
1701 {
1702 struct fec_enet_private *fep = netdev_priv(ndev);
1703 struct phy_device *phy_dev = ndev->phydev;
1704 int status_change = 0;
1705
1706 /* Prevent a state halted on mii error */
1707 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1708 phy_dev->state = PHY_RESUMING;
1709 return;
1710 }
1711
1712 /*
1713 * If the netdev is down, or is going down, we're not interested
1714 * in link state events, so just mark our idea of the link as down
1715 * and ignore the event.
1716 */
1717 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1718 fep->link = 0;
1719 } else if (phy_dev->link) {
1720 if (!fep->link) {
1721 fep->link = phy_dev->link;
1722 status_change = 1;
1723 }
1724
1725 if (fep->full_duplex != phy_dev->duplex) {
1726 fep->full_duplex = phy_dev->duplex;
1727 status_change = 1;
1728 }
1729
1730 if (phy_dev->speed != fep->speed) {
1731 fep->speed = phy_dev->speed;
1732 status_change = 1;
1733 }
1734
1735 /* if any of the above changed restart the FEC */
1736 if (status_change) {
1737 napi_disable(&fep->napi);
1738 netif_tx_lock_bh(ndev);
1739 fec_restart(ndev);
1740 netif_wake_queue(ndev);
1741 netif_tx_unlock_bh(ndev);
1742 napi_enable(&fep->napi);
1743 }
1744 } else {
1745 if (fep->link) {
1746 napi_disable(&fep->napi);
1747 netif_tx_lock_bh(ndev);
1748 fec_stop(ndev);
1749 netif_tx_unlock_bh(ndev);
1750 napi_enable(&fep->napi);
1751 fep->link = phy_dev->link;
1752 status_change = 1;
1753 }
1754 }
1755
1756 if (status_change)
1757 phy_print_status(phy_dev);
1758 }
1759
1760 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1761 {
1762 struct fec_enet_private *fep = bus->priv;
1763 struct device *dev = &fep->pdev->dev;
1764 unsigned long time_left;
1765 int ret = 0;
1766
1767 ret = pm_runtime_get_sync(dev);
1768 if (ret < 0)
1769 return ret;
1770
1771 fep->mii_timeout = 0;
1772 reinit_completion(&fep->mdio_done);
1773
1774 /* start a read op */
1775 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1776 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1777 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1778
1779 /* wait for end of transfer */
1780 time_left = wait_for_completion_timeout(&fep->mdio_done,
1781 usecs_to_jiffies(FEC_MII_TIMEOUT));
1782 if (time_left == 0) {
1783 fep->mii_timeout = 1;
1784 netdev_err(fep->netdev, "MDIO read timeout\n");
1785 ret = -ETIMEDOUT;
1786 goto out;
1787 }
1788
1789 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1790
1791 out:
1792 pm_runtime_mark_last_busy(dev);
1793 pm_runtime_put_autosuspend(dev);
1794
1795 return ret;
1796 }
1797
1798 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1799 u16 value)
1800 {
1801 struct fec_enet_private *fep = bus->priv;
1802 struct device *dev = &fep->pdev->dev;
1803 unsigned long time_left;
1804 int ret;
1805
1806 ret = pm_runtime_get_sync(dev);
1807 if (ret < 0)
1808 return ret;
1809 else
1810 ret = 0;
1811
1812 fep->mii_timeout = 0;
1813 reinit_completion(&fep->mdio_done);
1814
1815 /* start a write op */
1816 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1817 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1818 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1819 fep->hwp + FEC_MII_DATA);
1820
1821 /* wait for end of transfer */
1822 time_left = wait_for_completion_timeout(&fep->mdio_done,
1823 usecs_to_jiffies(FEC_MII_TIMEOUT));
1824 if (time_left == 0) {
1825 fep->mii_timeout = 1;
1826 netdev_err(fep->netdev, "MDIO write timeout\n");
1827 ret = -ETIMEDOUT;
1828 }
1829
1830 pm_runtime_mark_last_busy(dev);
1831 pm_runtime_put_autosuspend(dev);
1832
1833 return ret;
1834 }
1835
1836 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1837 {
1838 struct fec_enet_private *fep = netdev_priv(ndev);
1839 int ret;
1840
1841 if (enable) {
1842 ret = clk_prepare_enable(fep->clk_ahb);
1843 if (ret)
1844 return ret;
1845
1846 ret = clk_prepare_enable(fep->clk_enet_out);
1847 if (ret)
1848 goto failed_clk_enet_out;
1849
1850 if (fep->clk_ptp) {
1851 mutex_lock(&fep->ptp_clk_mutex);
1852 ret = clk_prepare_enable(fep->clk_ptp);
1853 if (ret) {
1854 mutex_unlock(&fep->ptp_clk_mutex);
1855 goto failed_clk_ptp;
1856 } else {
1857 fep->ptp_clk_on = true;
1858 }
1859 mutex_unlock(&fep->ptp_clk_mutex);
1860 }
1861
1862 ret = clk_prepare_enable(fep->clk_ref);
1863 if (ret)
1864 goto failed_clk_ref;
1865 } else {
1866 clk_disable_unprepare(fep->clk_ahb);
1867 clk_disable_unprepare(fep->clk_enet_out);
1868 if (fep->clk_ptp) {
1869 mutex_lock(&fep->ptp_clk_mutex);
1870 clk_disable_unprepare(fep->clk_ptp);
1871 fep->ptp_clk_on = false;
1872 mutex_unlock(&fep->ptp_clk_mutex);
1873 }
1874 clk_disable_unprepare(fep->clk_ref);
1875 }
1876
1877 return 0;
1878
1879 failed_clk_ref:
1880 if (fep->clk_ref)
1881 clk_disable_unprepare(fep->clk_ref);
1882 failed_clk_ptp:
1883 if (fep->clk_enet_out)
1884 clk_disable_unprepare(fep->clk_enet_out);
1885 failed_clk_enet_out:
1886 clk_disable_unprepare(fep->clk_ahb);
1887
1888 return ret;
1889 }
1890
1891 static int fec_enet_mii_probe(struct net_device *ndev)
1892 {
1893 struct fec_enet_private *fep = netdev_priv(ndev);
1894 struct phy_device *phy_dev = NULL;
1895 char mdio_bus_id[MII_BUS_ID_SIZE];
1896 char phy_name[MII_BUS_ID_SIZE + 3];
1897 int phy_id;
1898 int dev_id = fep->dev_id;
1899
1900 if (fep->phy_node) {
1901 phy_dev = of_phy_connect(ndev, fep->phy_node,
1902 &fec_enet_adjust_link, 0,
1903 fep->phy_interface);
1904 if (!phy_dev)
1905 return -ENODEV;
1906 } else {
1907 /* check for attached phy */
1908 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1909 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
1910 continue;
1911 if (dev_id--)
1912 continue;
1913 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1914 break;
1915 }
1916
1917 if (phy_id >= PHY_MAX_ADDR) {
1918 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1919 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1920 phy_id = 0;
1921 }
1922
1923 snprintf(phy_name, sizeof(phy_name),
1924 PHY_ID_FMT, mdio_bus_id, phy_id);
1925 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1926 fep->phy_interface);
1927 }
1928
1929 if (IS_ERR(phy_dev)) {
1930 netdev_err(ndev, "could not attach to PHY\n");
1931 return PTR_ERR(phy_dev);
1932 }
1933
1934 /* mask with MAC supported features */
1935 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
1936 phy_dev->supported &= PHY_GBIT_FEATURES;
1937 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1938 #if !defined(CONFIG_M5272)
1939 phy_dev->supported |= SUPPORTED_Pause;
1940 #endif
1941 }
1942 else
1943 phy_dev->supported &= PHY_BASIC_FEATURES;
1944
1945 phy_dev->advertising = phy_dev->supported;
1946
1947 fep->link = 0;
1948 fep->full_duplex = 0;
1949
1950 phy_attached_info(phy_dev);
1951
1952 return 0;
1953 }
1954
1955 static int fec_enet_mii_init(struct platform_device *pdev)
1956 {
1957 static struct mii_bus *fec0_mii_bus;
1958 struct net_device *ndev = platform_get_drvdata(pdev);
1959 struct fec_enet_private *fep = netdev_priv(ndev);
1960 struct device_node *node;
1961 int err = -ENXIO;
1962 u32 mii_speed, holdtime;
1963
1964 /*
1965 * The i.MX28 dual fec interfaces are not equal.
1966 * Here are the differences:
1967 *
1968 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1969 * - fec0 acts as the 1588 time master while fec1 is slave
1970 * - external phys can only be configured by fec0
1971 *
1972 * That is to say fec1 can not work independently. It only works
1973 * when fec0 is working. The reason behind this design is that the
1974 * second interface is added primarily for Switch mode.
1975 *
1976 * Because of the last point above, both phys are attached on fec0
1977 * mdio interface in board design, and need to be configured by
1978 * fec0 mii_bus.
1979 */
1980 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
1981 /* fec1 uses fec0 mii_bus */
1982 if (mii_cnt && fec0_mii_bus) {
1983 fep->mii_bus = fec0_mii_bus;
1984 mii_cnt++;
1985 return 0;
1986 }
1987 return -ENOENT;
1988 }
1989
1990 fep->mii_timeout = 0;
1991
1992 /*
1993 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1994 *
1995 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1996 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1997 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1998 * document.
1999 */
2000 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
2001 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2002 mii_speed--;
2003 if (mii_speed > 63) {
2004 dev_err(&pdev->dev,
2005 "fec clock (%lu) too fast to get right mii speed\n",
2006 clk_get_rate(fep->clk_ipg));
2007 err = -EINVAL;
2008 goto err_out;
2009 }
2010
2011 /*
2012 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2013 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2014 * versions are RAZ there, so just ignore the difference and write the
2015 * register always.
2016 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2017 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2018 * output.
2019 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2020 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2021 * holdtime cannot result in a value greater than 3.
2022 */
2023 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2024
2025 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2026
2027 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2028
2029 fep->mii_bus = mdiobus_alloc();
2030 if (fep->mii_bus == NULL) {
2031 err = -ENOMEM;
2032 goto err_out;
2033 }
2034
2035 fep->mii_bus->name = "fec_enet_mii_bus";
2036 fep->mii_bus->read = fec_enet_mdio_read;
2037 fep->mii_bus->write = fec_enet_mdio_write;
2038 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2039 pdev->name, fep->dev_id + 1);
2040 fep->mii_bus->priv = fep;
2041 fep->mii_bus->parent = &pdev->dev;
2042
2043 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2044 if (node) {
2045 err = of_mdiobus_register(fep->mii_bus, node);
2046 of_node_put(node);
2047 } else {
2048 err = mdiobus_register(fep->mii_bus);
2049 }
2050
2051 if (err)
2052 goto err_out_free_mdiobus;
2053
2054 mii_cnt++;
2055
2056 /* save fec0 mii_bus */
2057 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2058 fec0_mii_bus = fep->mii_bus;
2059
2060 return 0;
2061
2062 err_out_free_mdiobus:
2063 mdiobus_free(fep->mii_bus);
2064 err_out:
2065 return err;
2066 }
2067
2068 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2069 {
2070 if (--mii_cnt == 0) {
2071 mdiobus_unregister(fep->mii_bus);
2072 mdiobus_free(fep->mii_bus);
2073 }
2074 }
2075
2076 static void fec_enet_get_drvinfo(struct net_device *ndev,
2077 struct ethtool_drvinfo *info)
2078 {
2079 struct fec_enet_private *fep = netdev_priv(ndev);
2080
2081 strlcpy(info->driver, fep->pdev->dev.driver->name,
2082 sizeof(info->driver));
2083 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2084 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2085 }
2086
2087 static int fec_enet_get_regs_len(struct net_device *ndev)
2088 {
2089 struct fec_enet_private *fep = netdev_priv(ndev);
2090 struct resource *r;
2091 int s = 0;
2092
2093 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2094 if (r)
2095 s = resource_size(r);
2096
2097 return s;
2098 }
2099
2100 /* List of registers that can be safety be read to dump them with ethtool */
2101 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2102 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
2103 static u32 fec_enet_register_offset[] = {
2104 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2105 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2106 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2107 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2108 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2109 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2110 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2111 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2112 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2113 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2114 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2115 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2116 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2117 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2118 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2119 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2120 RMON_T_P_GTE2048, RMON_T_OCTETS,
2121 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2122 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2123 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2124 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2125 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2126 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2127 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2128 RMON_R_P_GTE2048, RMON_R_OCTETS,
2129 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2130 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2131 };
2132 #else
2133 static u32 fec_enet_register_offset[] = {
2134 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2135 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2136 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2137 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2138 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2139 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2140 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2141 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2142 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2143 };
2144 #endif
2145
2146 static void fec_enet_get_regs(struct net_device *ndev,
2147 struct ethtool_regs *regs, void *regbuf)
2148 {
2149 struct fec_enet_private *fep = netdev_priv(ndev);
2150 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2151 u32 *buf = (u32 *)regbuf;
2152 u32 i, off;
2153
2154 memset(buf, 0, regs->len);
2155
2156 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
2157 off = fec_enet_register_offset[i] / 4;
2158 buf[off] = readl(&theregs[off]);
2159 }
2160 }
2161
2162 static int fec_enet_get_ts_info(struct net_device *ndev,
2163 struct ethtool_ts_info *info)
2164 {
2165 struct fec_enet_private *fep = netdev_priv(ndev);
2166
2167 if (fep->bufdesc_ex) {
2168
2169 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2170 SOF_TIMESTAMPING_RX_SOFTWARE |
2171 SOF_TIMESTAMPING_SOFTWARE |
2172 SOF_TIMESTAMPING_TX_HARDWARE |
2173 SOF_TIMESTAMPING_RX_HARDWARE |
2174 SOF_TIMESTAMPING_RAW_HARDWARE;
2175 if (fep->ptp_clock)
2176 info->phc_index = ptp_clock_index(fep->ptp_clock);
2177 else
2178 info->phc_index = -1;
2179
2180 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2181 (1 << HWTSTAMP_TX_ON);
2182
2183 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2184 (1 << HWTSTAMP_FILTER_ALL);
2185 return 0;
2186 } else {
2187 return ethtool_op_get_ts_info(ndev, info);
2188 }
2189 }
2190
2191 #if !defined(CONFIG_M5272)
2192
2193 static void fec_enet_get_pauseparam(struct net_device *ndev,
2194 struct ethtool_pauseparam *pause)
2195 {
2196 struct fec_enet_private *fep = netdev_priv(ndev);
2197
2198 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2199 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2200 pause->rx_pause = pause->tx_pause;
2201 }
2202
2203 static int fec_enet_set_pauseparam(struct net_device *ndev,
2204 struct ethtool_pauseparam *pause)
2205 {
2206 struct fec_enet_private *fep = netdev_priv(ndev);
2207
2208 if (!ndev->phydev)
2209 return -ENODEV;
2210
2211 if (pause->tx_pause != pause->rx_pause) {
2212 netdev_info(ndev,
2213 "hardware only support enable/disable both tx and rx");
2214 return -EINVAL;
2215 }
2216
2217 fep->pause_flag = 0;
2218
2219 /* tx pause must be same as rx pause */
2220 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2221 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2222
2223 if (pause->rx_pause || pause->autoneg) {
2224 ndev->phydev->supported |= ADVERTISED_Pause;
2225 ndev->phydev->advertising |= ADVERTISED_Pause;
2226 } else {
2227 ndev->phydev->supported &= ~ADVERTISED_Pause;
2228 ndev->phydev->advertising &= ~ADVERTISED_Pause;
2229 }
2230
2231 if (pause->autoneg) {
2232 if (netif_running(ndev))
2233 fec_stop(ndev);
2234 phy_start_aneg(ndev->phydev);
2235 }
2236 if (netif_running(ndev)) {
2237 napi_disable(&fep->napi);
2238 netif_tx_lock_bh(ndev);
2239 fec_restart(ndev);
2240 netif_wake_queue(ndev);
2241 netif_tx_unlock_bh(ndev);
2242 napi_enable(&fep->napi);
2243 }
2244
2245 return 0;
2246 }
2247
2248 static const struct fec_stat {
2249 char name[ETH_GSTRING_LEN];
2250 u16 offset;
2251 } fec_stats[] = {
2252 /* RMON TX */
2253 { "tx_dropped", RMON_T_DROP },
2254 { "tx_packets", RMON_T_PACKETS },
2255 { "tx_broadcast", RMON_T_BC_PKT },
2256 { "tx_multicast", RMON_T_MC_PKT },
2257 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2258 { "tx_undersize", RMON_T_UNDERSIZE },
2259 { "tx_oversize", RMON_T_OVERSIZE },
2260 { "tx_fragment", RMON_T_FRAG },
2261 { "tx_jabber", RMON_T_JAB },
2262 { "tx_collision", RMON_T_COL },
2263 { "tx_64byte", RMON_T_P64 },
2264 { "tx_65to127byte", RMON_T_P65TO127 },
2265 { "tx_128to255byte", RMON_T_P128TO255 },
2266 { "tx_256to511byte", RMON_T_P256TO511 },
2267 { "tx_512to1023byte", RMON_T_P512TO1023 },
2268 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2269 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2270 { "tx_octets", RMON_T_OCTETS },
2271
2272 /* IEEE TX */
2273 { "IEEE_tx_drop", IEEE_T_DROP },
2274 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2275 { "IEEE_tx_1col", IEEE_T_1COL },
2276 { "IEEE_tx_mcol", IEEE_T_MCOL },
2277 { "IEEE_tx_def", IEEE_T_DEF },
2278 { "IEEE_tx_lcol", IEEE_T_LCOL },
2279 { "IEEE_tx_excol", IEEE_T_EXCOL },
2280 { "IEEE_tx_macerr", IEEE_T_MACERR },
2281 { "IEEE_tx_cserr", IEEE_T_CSERR },
2282 { "IEEE_tx_sqe", IEEE_T_SQE },
2283 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2284 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2285
2286 /* RMON RX */
2287 { "rx_packets", RMON_R_PACKETS },
2288 { "rx_broadcast", RMON_R_BC_PKT },
2289 { "rx_multicast", RMON_R_MC_PKT },
2290 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2291 { "rx_undersize", RMON_R_UNDERSIZE },
2292 { "rx_oversize", RMON_R_OVERSIZE },
2293 { "rx_fragment", RMON_R_FRAG },
2294 { "rx_jabber", RMON_R_JAB },
2295 { "rx_64byte", RMON_R_P64 },
2296 { "rx_65to127byte", RMON_R_P65TO127 },
2297 { "rx_128to255byte", RMON_R_P128TO255 },
2298 { "rx_256to511byte", RMON_R_P256TO511 },
2299 { "rx_512to1023byte", RMON_R_P512TO1023 },
2300 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2301 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2302 { "rx_octets", RMON_R_OCTETS },
2303
2304 /* IEEE RX */
2305 { "IEEE_rx_drop", IEEE_R_DROP },
2306 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2307 { "IEEE_rx_crc", IEEE_R_CRC },
2308 { "IEEE_rx_align", IEEE_R_ALIGN },
2309 { "IEEE_rx_macerr", IEEE_R_MACERR },
2310 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2311 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2312 };
2313
2314 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64))
2315
2316 static void fec_enet_update_ethtool_stats(struct net_device *dev)
2317 {
2318 struct fec_enet_private *fep = netdev_priv(dev);
2319 int i;
2320
2321 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2322 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset);
2323 }
2324
2325 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2326 struct ethtool_stats *stats, u64 *data)
2327 {
2328 struct fec_enet_private *fep = netdev_priv(dev);
2329
2330 if (netif_running(dev))
2331 fec_enet_update_ethtool_stats(dev);
2332
2333 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE);
2334 }
2335
2336 static void fec_enet_get_strings(struct net_device *netdev,
2337 u32 stringset, u8 *data)
2338 {
2339 int i;
2340 switch (stringset) {
2341 case ETH_SS_STATS:
2342 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2343 memcpy(data + i * ETH_GSTRING_LEN,
2344 fec_stats[i].name, ETH_GSTRING_LEN);
2345 break;
2346 }
2347 }
2348
2349 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2350 {
2351 switch (sset) {
2352 case ETH_SS_STATS:
2353 return ARRAY_SIZE(fec_stats);
2354 default:
2355 return -EOPNOTSUPP;
2356 }
2357 }
2358
2359 #else /* !defined(CONFIG_M5272) */
2360 #define FEC_STATS_SIZE 0
2361 static inline void fec_enet_update_ethtool_stats(struct net_device *dev)
2362 {
2363 }
2364 #endif /* !defined(CONFIG_M5272) */
2365
2366 /* ITR clock source is enet system clock (clk_ahb).
2367 * TCTT unit is cycle_ns * 64 cycle
2368 * So, the ICTT value = X us / (cycle_ns * 64)
2369 */
2370 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2371 {
2372 struct fec_enet_private *fep = netdev_priv(ndev);
2373
2374 return us * (fep->itr_clk_rate / 64000) / 1000;
2375 }
2376
2377 /* Set threshold for interrupt coalescing */
2378 static void fec_enet_itr_coal_set(struct net_device *ndev)
2379 {
2380 struct fec_enet_private *fep = netdev_priv(ndev);
2381 int rx_itr, tx_itr;
2382
2383 /* Must be greater than zero to avoid unpredictable behavior */
2384 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2385 !fep->tx_time_itr || !fep->tx_pkts_itr)
2386 return;
2387
2388 /* Select enet system clock as Interrupt Coalescing
2389 * timer Clock Source
2390 */
2391 rx_itr = FEC_ITR_CLK_SEL;
2392 tx_itr = FEC_ITR_CLK_SEL;
2393
2394 /* set ICFT and ICTT */
2395 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2396 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2397 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2398 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2399
2400 rx_itr |= FEC_ITR_EN;
2401 tx_itr |= FEC_ITR_EN;
2402
2403 writel(tx_itr, fep->hwp + FEC_TXIC0);
2404 writel(rx_itr, fep->hwp + FEC_RXIC0);
2405 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
2406 writel(tx_itr, fep->hwp + FEC_TXIC1);
2407 writel(rx_itr, fep->hwp + FEC_RXIC1);
2408 writel(tx_itr, fep->hwp + FEC_TXIC2);
2409 writel(rx_itr, fep->hwp + FEC_RXIC2);
2410 }
2411 }
2412
2413 static int
2414 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2415 {
2416 struct fec_enet_private *fep = netdev_priv(ndev);
2417
2418 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2419 return -EOPNOTSUPP;
2420
2421 ec->rx_coalesce_usecs = fep->rx_time_itr;
2422 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2423
2424 ec->tx_coalesce_usecs = fep->tx_time_itr;
2425 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2426
2427 return 0;
2428 }
2429
2430 static int
2431 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2432 {
2433 struct fec_enet_private *fep = netdev_priv(ndev);
2434 unsigned int cycle;
2435
2436 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2437 return -EOPNOTSUPP;
2438
2439 if (ec->rx_max_coalesced_frames > 255) {
2440 pr_err("Rx coalesced frames exceed hardware limitation\n");
2441 return -EINVAL;
2442 }
2443
2444 if (ec->tx_max_coalesced_frames > 255) {
2445 pr_err("Tx coalesced frame exceed hardware limitation\n");
2446 return -EINVAL;
2447 }
2448
2449 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2450 if (cycle > 0xFFFF) {
2451 pr_err("Rx coalesced usec exceed hardware limitation\n");
2452 return -EINVAL;
2453 }
2454
2455 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2456 if (cycle > 0xFFFF) {
2457 pr_err("Rx coalesced usec exceed hardware limitation\n");
2458 return -EINVAL;
2459 }
2460
2461 fep->rx_time_itr = ec->rx_coalesce_usecs;
2462 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2463
2464 fep->tx_time_itr = ec->tx_coalesce_usecs;
2465 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2466
2467 fec_enet_itr_coal_set(ndev);
2468
2469 return 0;
2470 }
2471
2472 static void fec_enet_itr_coal_init(struct net_device *ndev)
2473 {
2474 struct ethtool_coalesce ec;
2475
2476 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2477 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2478
2479 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2480 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2481
2482 fec_enet_set_coalesce(ndev, &ec);
2483 }
2484
2485 static int fec_enet_get_tunable(struct net_device *netdev,
2486 const struct ethtool_tunable *tuna,
2487 void *data)
2488 {
2489 struct fec_enet_private *fep = netdev_priv(netdev);
2490 int ret = 0;
2491
2492 switch (tuna->id) {
2493 case ETHTOOL_RX_COPYBREAK:
2494 *(u32 *)data = fep->rx_copybreak;
2495 break;
2496 default:
2497 ret = -EINVAL;
2498 break;
2499 }
2500
2501 return ret;
2502 }
2503
2504 static int fec_enet_set_tunable(struct net_device *netdev,
2505 const struct ethtool_tunable *tuna,
2506 const void *data)
2507 {
2508 struct fec_enet_private *fep = netdev_priv(netdev);
2509 int ret = 0;
2510
2511 switch (tuna->id) {
2512 case ETHTOOL_RX_COPYBREAK:
2513 fep->rx_copybreak = *(u32 *)data;
2514 break;
2515 default:
2516 ret = -EINVAL;
2517 break;
2518 }
2519
2520 return ret;
2521 }
2522
2523 static void
2524 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2525 {
2526 struct fec_enet_private *fep = netdev_priv(ndev);
2527
2528 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2529 wol->supported = WAKE_MAGIC;
2530 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2531 } else {
2532 wol->supported = wol->wolopts = 0;
2533 }
2534 }
2535
2536 static int
2537 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2538 {
2539 struct fec_enet_private *fep = netdev_priv(ndev);
2540
2541 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2542 return -EINVAL;
2543
2544 if (wol->wolopts & ~WAKE_MAGIC)
2545 return -EINVAL;
2546
2547 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2548 if (device_may_wakeup(&ndev->dev)) {
2549 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2550 if (fep->irq[0] > 0)
2551 enable_irq_wake(fep->irq[0]);
2552 } else {
2553 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2554 if (fep->irq[0] > 0)
2555 disable_irq_wake(fep->irq[0]);
2556 }
2557
2558 return 0;
2559 }
2560
2561 static const struct ethtool_ops fec_enet_ethtool_ops = {
2562 .get_drvinfo = fec_enet_get_drvinfo,
2563 .get_regs_len = fec_enet_get_regs_len,
2564 .get_regs = fec_enet_get_regs,
2565 .nway_reset = phy_ethtool_nway_reset,
2566 .get_link = ethtool_op_get_link,
2567 .get_coalesce = fec_enet_get_coalesce,
2568 .set_coalesce = fec_enet_set_coalesce,
2569 #ifndef CONFIG_M5272
2570 .get_pauseparam = fec_enet_get_pauseparam,
2571 .set_pauseparam = fec_enet_set_pauseparam,
2572 .get_strings = fec_enet_get_strings,
2573 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2574 .get_sset_count = fec_enet_get_sset_count,
2575 #endif
2576 .get_ts_info = fec_enet_get_ts_info,
2577 .get_tunable = fec_enet_get_tunable,
2578 .set_tunable = fec_enet_set_tunable,
2579 .get_wol = fec_enet_get_wol,
2580 .set_wol = fec_enet_set_wol,
2581 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2582 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2583 };
2584
2585 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2586 {
2587 struct fec_enet_private *fep = netdev_priv(ndev);
2588 struct phy_device *phydev = ndev->phydev;
2589
2590 if (!netif_running(ndev))
2591 return -EINVAL;
2592
2593 if (!phydev)
2594 return -ENODEV;
2595
2596 if (fep->bufdesc_ex) {
2597 if (cmd == SIOCSHWTSTAMP)
2598 return fec_ptp_set(ndev, rq);
2599 if (cmd == SIOCGHWTSTAMP)
2600 return fec_ptp_get(ndev, rq);
2601 }
2602
2603 return phy_mii_ioctl(phydev, rq, cmd);
2604 }
2605
2606 static void fec_enet_free_buffers(struct net_device *ndev)
2607 {
2608 struct fec_enet_private *fep = netdev_priv(ndev);
2609 unsigned int i;
2610 struct sk_buff *skb;
2611 struct bufdesc *bdp;
2612 struct fec_enet_priv_tx_q *txq;
2613 struct fec_enet_priv_rx_q *rxq;
2614 unsigned int q;
2615
2616 for (q = 0; q < fep->num_rx_queues; q++) {
2617 rxq = fep->rx_queue[q];
2618 bdp = rxq->bd.base;
2619 for (i = 0; i < rxq->bd.ring_size; i++) {
2620 skb = rxq->rx_skbuff[i];
2621 rxq->rx_skbuff[i] = NULL;
2622 if (skb) {
2623 dma_unmap_single(&fep->pdev->dev,
2624 fec32_to_cpu(bdp->cbd_bufaddr),
2625 FEC_ENET_RX_FRSIZE - fep->rx_align,
2626 DMA_FROM_DEVICE);
2627 dev_kfree_skb(skb);
2628 }
2629 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2630 }
2631 }
2632
2633 for (q = 0; q < fep->num_tx_queues; q++) {
2634 txq = fep->tx_queue[q];
2635 bdp = txq->bd.base;
2636 for (i = 0; i < txq->bd.ring_size; i++) {
2637 kfree(txq->tx_bounce[i]);
2638 txq->tx_bounce[i] = NULL;
2639 skb = txq->tx_skbuff[i];
2640 txq->tx_skbuff[i] = NULL;
2641 dev_kfree_skb(skb);
2642 }
2643 }
2644 }
2645
2646 static void fec_enet_free_queue(struct net_device *ndev)
2647 {
2648 struct fec_enet_private *fep = netdev_priv(ndev);
2649 int i;
2650 struct fec_enet_priv_tx_q *txq;
2651
2652 for (i = 0; i < fep->num_tx_queues; i++)
2653 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2654 txq = fep->tx_queue[i];
2655 dma_free_coherent(&fep->pdev->dev,
2656 txq->bd.ring_size * TSO_HEADER_SIZE,
2657 txq->tso_hdrs,
2658 txq->tso_hdrs_dma);
2659 }
2660
2661 for (i = 0; i < fep->num_rx_queues; i++)
2662 kfree(fep->rx_queue[i]);
2663 for (i = 0; i < fep->num_tx_queues; i++)
2664 kfree(fep->tx_queue[i]);
2665 }
2666
2667 static int fec_enet_alloc_queue(struct net_device *ndev)
2668 {
2669 struct fec_enet_private *fep = netdev_priv(ndev);
2670 int i;
2671 int ret = 0;
2672 struct fec_enet_priv_tx_q *txq;
2673
2674 for (i = 0; i < fep->num_tx_queues; i++) {
2675 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2676 if (!txq) {
2677 ret = -ENOMEM;
2678 goto alloc_failed;
2679 }
2680
2681 fep->tx_queue[i] = txq;
2682 txq->bd.ring_size = TX_RING_SIZE;
2683 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
2684
2685 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2686 txq->tx_wake_threshold =
2687 (txq->bd.ring_size - txq->tx_stop_threshold) / 2;
2688
2689 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev,
2690 txq->bd.ring_size * TSO_HEADER_SIZE,
2691 &txq->tso_hdrs_dma,
2692 GFP_KERNEL);
2693 if (!txq->tso_hdrs) {
2694 ret = -ENOMEM;
2695 goto alloc_failed;
2696 }
2697 }
2698
2699 for (i = 0; i < fep->num_rx_queues; i++) {
2700 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2701 GFP_KERNEL);
2702 if (!fep->rx_queue[i]) {
2703 ret = -ENOMEM;
2704 goto alloc_failed;
2705 }
2706
2707 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
2708 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
2709 }
2710 return ret;
2711
2712 alloc_failed:
2713 fec_enet_free_queue(ndev);
2714 return ret;
2715 }
2716
2717 static int
2718 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2719 {
2720 struct fec_enet_private *fep = netdev_priv(ndev);
2721 unsigned int i;
2722 struct sk_buff *skb;
2723 struct bufdesc *bdp;
2724 struct fec_enet_priv_rx_q *rxq;
2725
2726 rxq = fep->rx_queue[queue];
2727 bdp = rxq->bd.base;
2728 for (i = 0; i < rxq->bd.ring_size; i++) {
2729 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2730 if (!skb)
2731 goto err_alloc;
2732
2733 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2734 dev_kfree_skb(skb);
2735 goto err_alloc;
2736 }
2737
2738 rxq->rx_skbuff[i] = skb;
2739 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
2740
2741 if (fep->bufdesc_ex) {
2742 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2743 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
2744 }
2745
2746 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2747 }
2748
2749 /* Set the last buffer to wrap. */
2750 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
2751 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2752 return 0;
2753
2754 err_alloc:
2755 fec_enet_free_buffers(ndev);
2756 return -ENOMEM;
2757 }
2758
2759 static int
2760 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2761 {
2762 struct fec_enet_private *fep = netdev_priv(ndev);
2763 unsigned int i;
2764 struct bufdesc *bdp;
2765 struct fec_enet_priv_tx_q *txq;
2766
2767 txq = fep->tx_queue[queue];
2768 bdp = txq->bd.base;
2769 for (i = 0; i < txq->bd.ring_size; i++) {
2770 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2771 if (!txq->tx_bounce[i])
2772 goto err_alloc;
2773
2774 bdp->cbd_sc = cpu_to_fec16(0);
2775 bdp->cbd_bufaddr = cpu_to_fec32(0);
2776
2777 if (fep->bufdesc_ex) {
2778 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2779 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
2780 }
2781
2782 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
2783 }
2784
2785 /* Set the last buffer to wrap. */
2786 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
2787 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2788
2789 return 0;
2790
2791 err_alloc:
2792 fec_enet_free_buffers(ndev);
2793 return -ENOMEM;
2794 }
2795
2796 static int fec_enet_alloc_buffers(struct net_device *ndev)
2797 {
2798 struct fec_enet_private *fep = netdev_priv(ndev);
2799 unsigned int i;
2800
2801 for (i = 0; i < fep->num_rx_queues; i++)
2802 if (fec_enet_alloc_rxq_buffers(ndev, i))
2803 return -ENOMEM;
2804
2805 for (i = 0; i < fep->num_tx_queues; i++)
2806 if (fec_enet_alloc_txq_buffers(ndev, i))
2807 return -ENOMEM;
2808 return 0;
2809 }
2810
2811 static int
2812 fec_enet_open(struct net_device *ndev)
2813 {
2814 struct fec_enet_private *fep = netdev_priv(ndev);
2815 int ret;
2816
2817 ret = pm_runtime_get_sync(&fep->pdev->dev);
2818 if (ret < 0)
2819 return ret;
2820
2821 pinctrl_pm_select_default_state(&fep->pdev->dev);
2822 ret = fec_enet_clk_enable(ndev, true);
2823 if (ret)
2824 goto clk_enable;
2825
2826 /* I should reset the ring buffers here, but I don't yet know
2827 * a simple way to do that.
2828 */
2829
2830 ret = fec_enet_alloc_buffers(ndev);
2831 if (ret)
2832 goto err_enet_alloc;
2833
2834 /* Init MAC prior to mii bus probe */
2835 fec_restart(ndev);
2836
2837 /* Probe and connect to PHY when open the interface */
2838 ret = fec_enet_mii_probe(ndev);
2839 if (ret)
2840 goto err_enet_mii_probe;
2841
2842 if (fep->quirks & FEC_QUIRK_ERR006687)
2843 imx6q_cpuidle_fec_irqs_used();
2844
2845 napi_enable(&fep->napi);
2846 phy_start(ndev->phydev);
2847 netif_tx_start_all_queues(ndev);
2848
2849 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2850 FEC_WOL_FLAG_ENABLE);
2851
2852 return 0;
2853
2854 err_enet_mii_probe:
2855 fec_enet_free_buffers(ndev);
2856 err_enet_alloc:
2857 fec_enet_clk_enable(ndev, false);
2858 clk_enable:
2859 pm_runtime_mark_last_busy(&fep->pdev->dev);
2860 pm_runtime_put_autosuspend(&fep->pdev->dev);
2861 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2862 return ret;
2863 }
2864
2865 static int
2866 fec_enet_close(struct net_device *ndev)
2867 {
2868 struct fec_enet_private *fep = netdev_priv(ndev);
2869
2870 phy_stop(ndev->phydev);
2871
2872 if (netif_device_present(ndev)) {
2873 napi_disable(&fep->napi);
2874 netif_tx_disable(ndev);
2875 fec_stop(ndev);
2876 }
2877
2878 phy_disconnect(ndev->phydev);
2879
2880 if (fep->quirks & FEC_QUIRK_ERR006687)
2881 imx6q_cpuidle_fec_irqs_unused();
2882
2883 fec_enet_update_ethtool_stats(ndev);
2884
2885 fec_enet_clk_enable(ndev, false);
2886 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2887 pm_runtime_mark_last_busy(&fep->pdev->dev);
2888 pm_runtime_put_autosuspend(&fep->pdev->dev);
2889
2890 fec_enet_free_buffers(ndev);
2891
2892 return 0;
2893 }
2894
2895 /* Set or clear the multicast filter for this adaptor.
2896 * Skeleton taken from sunlance driver.
2897 * The CPM Ethernet implementation allows Multicast as well as individual
2898 * MAC address filtering. Some of the drivers check to make sure it is
2899 * a group multicast address, and discard those that are not. I guess I
2900 * will do the same for now, but just remove the test if you want
2901 * individual filtering as well (do the upper net layers want or support
2902 * this kind of feature?).
2903 */
2904
2905 #define FEC_HASH_BITS 6 /* #bits in hash */
2906 #define CRC32_POLY 0xEDB88320
2907
2908 static void set_multicast_list(struct net_device *ndev)
2909 {
2910 struct fec_enet_private *fep = netdev_priv(ndev);
2911 struct netdev_hw_addr *ha;
2912 unsigned int i, bit, data, crc, tmp;
2913 unsigned char hash;
2914 unsigned int hash_high = 0, hash_low = 0;
2915
2916 if (ndev->flags & IFF_PROMISC) {
2917 tmp = readl(fep->hwp + FEC_R_CNTRL);
2918 tmp |= 0x8;
2919 writel(tmp, fep->hwp + FEC_R_CNTRL);
2920 return;
2921 }
2922
2923 tmp = readl(fep->hwp + FEC_R_CNTRL);
2924 tmp &= ~0x8;
2925 writel(tmp, fep->hwp + FEC_R_CNTRL);
2926
2927 if (ndev->flags & IFF_ALLMULTI) {
2928 /* Catch all multicast addresses, so set the
2929 * filter to all 1's
2930 */
2931 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2932 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2933
2934 return;
2935 }
2936
2937 /* Add the addresses in hash register */
2938 netdev_for_each_mc_addr(ha, ndev) {
2939 /* calculate crc32 value of mac address */
2940 crc = 0xffffffff;
2941
2942 for (i = 0; i < ndev->addr_len; i++) {
2943 data = ha->addr[i];
2944 for (bit = 0; bit < 8; bit++, data >>= 1) {
2945 crc = (crc >> 1) ^
2946 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2947 }
2948 }
2949
2950 /* only upper 6 bits (FEC_HASH_BITS) are used
2951 * which point to specific bit in the hash registers
2952 */
2953 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f;
2954
2955 if (hash > 31)
2956 hash_high |= 1 << (hash - 32);
2957 else
2958 hash_low |= 1 << hash;
2959 }
2960
2961 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2962 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2963 }
2964
2965 /* Set a MAC change in hardware. */
2966 static int
2967 fec_set_mac_address(struct net_device *ndev, void *p)
2968 {
2969 struct fec_enet_private *fep = netdev_priv(ndev);
2970 struct sockaddr *addr = p;
2971
2972 if (addr) {
2973 if (!is_valid_ether_addr(addr->sa_data))
2974 return -EADDRNOTAVAIL;
2975 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2976 }
2977
2978 /* Add netif status check here to avoid system hang in below case:
2979 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
2980 * After ethx down, fec all clocks are gated off and then register
2981 * access causes system hang.
2982 */
2983 if (!netif_running(ndev))
2984 return 0;
2985
2986 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2987 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
2988 fep->hwp + FEC_ADDR_LOW);
2989 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
2990 fep->hwp + FEC_ADDR_HIGH);
2991 return 0;
2992 }
2993
2994 #ifdef CONFIG_NET_POLL_CONTROLLER
2995 /**
2996 * fec_poll_controller - FEC Poll controller function
2997 * @dev: The FEC network adapter
2998 *
2999 * Polled functionality used by netconsole and others in non interrupt mode
3000 *
3001 */
3002 static void fec_poll_controller(struct net_device *dev)
3003 {
3004 int i;
3005 struct fec_enet_private *fep = netdev_priv(dev);
3006
3007 for (i = 0; i < FEC_IRQ_NUM; i++) {
3008 if (fep->irq[i] > 0) {
3009 disable_irq(fep->irq[i]);
3010 fec_enet_interrupt(fep->irq[i], dev);
3011 enable_irq(fep->irq[i]);
3012 }
3013 }
3014 }
3015 #endif
3016
3017 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3018 netdev_features_t features)
3019 {
3020 struct fec_enet_private *fep = netdev_priv(netdev);
3021 netdev_features_t changed = features ^ netdev->features;
3022
3023 netdev->features = features;
3024
3025 /* Receive checksum has been changed */
3026 if (changed & NETIF_F_RXCSUM) {
3027 if (features & NETIF_F_RXCSUM)
3028 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3029 else
3030 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3031 }
3032 }
3033
3034 static int fec_set_features(struct net_device *netdev,
3035 netdev_features_t features)
3036 {
3037 struct fec_enet_private *fep = netdev_priv(netdev);
3038 netdev_features_t changed = features ^ netdev->features;
3039
3040 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3041 napi_disable(&fep->napi);
3042 netif_tx_lock_bh(netdev);
3043 fec_stop(netdev);
3044 fec_enet_set_netdev_features(netdev, features);
3045 fec_restart(netdev);
3046 netif_tx_wake_all_queues(netdev);
3047 netif_tx_unlock_bh(netdev);
3048 napi_enable(&fep->napi);
3049 } else {
3050 fec_enet_set_netdev_features(netdev, features);
3051 }
3052
3053 return 0;
3054 }
3055
3056 static const struct net_device_ops fec_netdev_ops = {
3057 .ndo_open = fec_enet_open,
3058 .ndo_stop = fec_enet_close,
3059 .ndo_start_xmit = fec_enet_start_xmit,
3060 .ndo_set_rx_mode = set_multicast_list,
3061 .ndo_validate_addr = eth_validate_addr,
3062 .ndo_tx_timeout = fec_timeout,
3063 .ndo_set_mac_address = fec_set_mac_address,
3064 .ndo_do_ioctl = fec_enet_ioctl,
3065 #ifdef CONFIG_NET_POLL_CONTROLLER
3066 .ndo_poll_controller = fec_poll_controller,
3067 #endif
3068 .ndo_set_features = fec_set_features,
3069 };
3070
3071 static const unsigned short offset_des_active_rxq[] = {
3072 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3073 };
3074
3075 static const unsigned short offset_des_active_txq[] = {
3076 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3077 };
3078
3079 /*
3080 * XXX: We need to clean up on failure exits here.
3081 *
3082 */
3083 static int fec_enet_init(struct net_device *ndev)
3084 {
3085 struct fec_enet_private *fep = netdev_priv(ndev);
3086 struct bufdesc *cbd_base;
3087 dma_addr_t bd_dma;
3088 int bd_size;
3089 unsigned int i;
3090 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
3091 sizeof(struct bufdesc);
3092 unsigned dsize_log2 = __fls(dsize);
3093
3094 WARN_ON(dsize != (1 << dsize_log2));
3095 #if defined(CONFIG_ARM)
3096 fep->rx_align = 0xf;
3097 fep->tx_align = 0xf;
3098 #else
3099 fep->rx_align = 0x3;
3100 fep->tx_align = 0x3;
3101 #endif
3102
3103 fec_enet_alloc_queue(ndev);
3104
3105 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
3106
3107 /* Allocate memory for buffer descriptors. */
3108 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3109 GFP_KERNEL);
3110 if (!cbd_base) {
3111 return -ENOMEM;
3112 }
3113
3114 memset(cbd_base, 0, bd_size);
3115
3116 /* Get the Ethernet address */
3117 fec_get_mac(ndev);
3118 /* make sure MAC we just acquired is programmed into the hw */
3119 fec_set_mac_address(ndev, NULL);
3120
3121 /* Set receive and transmit descriptor base. */
3122 for (i = 0; i < fep->num_rx_queues; i++) {
3123 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
3124 unsigned size = dsize * rxq->bd.ring_size;
3125
3126 rxq->bd.qid = i;
3127 rxq->bd.base = cbd_base;
3128 rxq->bd.cur = cbd_base;
3129 rxq->bd.dma = bd_dma;
3130 rxq->bd.dsize = dsize;
3131 rxq->bd.dsize_log2 = dsize_log2;
3132 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
3133 bd_dma += size;
3134 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3135 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3136 }
3137
3138 for (i = 0; i < fep->num_tx_queues; i++) {
3139 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
3140 unsigned size = dsize * txq->bd.ring_size;
3141
3142 txq->bd.qid = i;
3143 txq->bd.base = cbd_base;
3144 txq->bd.cur = cbd_base;
3145 txq->bd.dma = bd_dma;
3146 txq->bd.dsize = dsize;
3147 txq->bd.dsize_log2 = dsize_log2;
3148 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
3149 bd_dma += size;
3150 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3151 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3152 }
3153
3154
3155 /* The FEC Ethernet specific entries in the device structure */
3156 ndev->watchdog_timeo = TX_TIMEOUT;
3157 ndev->netdev_ops = &fec_netdev_ops;
3158 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3159
3160 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3161 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3162
3163 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3164 /* enable hw VLAN support */
3165 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3166
3167 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3168 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3169
3170 /* enable hw accelerator */
3171 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3172 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3173 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3174 }
3175
3176 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3177 fep->tx_align = 0;
3178 fep->rx_align = 0x3f;
3179 }
3180
3181 ndev->hw_features = ndev->features;
3182
3183 fec_restart(ndev);
3184
3185 fec_enet_update_ethtool_stats(ndev);
3186
3187 return 0;
3188 }
3189
3190 #ifdef CONFIG_OF
3191 static int fec_reset_phy(struct platform_device *pdev)
3192 {
3193 int err, phy_reset;
3194 bool active_high = false;
3195 int msec = 1;
3196 struct device_node *np = pdev->dev.of_node;
3197
3198 if (!np)
3199 return 0;
3200
3201 err = of_property_read_u32(np, "phy-reset-duration", &msec);
3202 /* A sane reset duration should not be longer than 1s */
3203 if (!err && msec > 1000)
3204 msec = 1;
3205
3206 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3207 if (phy_reset == -EPROBE_DEFER)
3208 return phy_reset;
3209 else if (!gpio_is_valid(phy_reset))
3210 return 0;
3211
3212 active_high = of_property_read_bool(np, "phy-reset-active-high");
3213
3214 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3215 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
3216 "phy-reset");
3217 if (err) {
3218 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3219 return err;
3220 }
3221
3222 if (msec > 20)
3223 msleep(msec);
3224 else
3225 usleep_range(msec * 1000, msec * 1000 + 1000);
3226
3227 gpio_set_value_cansleep(phy_reset, !active_high);
3228
3229 return 0;
3230 }
3231 #else /* CONFIG_OF */
3232 static int fec_reset_phy(struct platform_device *pdev)
3233 {
3234 /*
3235 * In case of platform probe, the reset has been done
3236 * by machine code.
3237 */
3238 return 0;
3239 }
3240 #endif /* CONFIG_OF */
3241
3242 static void
3243 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3244 {
3245 struct device_node *np = pdev->dev.of_node;
3246
3247 *num_tx = *num_rx = 1;
3248
3249 if (!np || !of_device_is_available(np))
3250 return;
3251
3252 /* parse the num of tx and rx queues */
3253 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3254
3255 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3256
3257 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3258 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3259 *num_tx);
3260 *num_tx = 1;
3261 return;
3262 }
3263
3264 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3265 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3266 *num_rx);
3267 *num_rx = 1;
3268 return;
3269 }
3270
3271 }
3272
3273 static int
3274 fec_probe(struct platform_device *pdev)
3275 {
3276 struct fec_enet_private *fep;
3277 struct fec_platform_data *pdata;
3278 struct net_device *ndev;
3279 int i, irq, ret = 0;
3280 struct resource *r;
3281 const struct of_device_id *of_id;
3282 static int dev_id;
3283 struct device_node *np = pdev->dev.of_node, *phy_node;
3284 int num_tx_qs;
3285 int num_rx_qs;
3286
3287 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3288
3289 /* Init network device */
3290 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) +
3291 FEC_STATS_SIZE, num_tx_qs, num_rx_qs);
3292 if (!ndev)
3293 return -ENOMEM;
3294
3295 SET_NETDEV_DEV(ndev, &pdev->dev);
3296
3297 /* setup board info structure */
3298 fep = netdev_priv(ndev);
3299
3300 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3301 if (of_id)
3302 pdev->id_entry = of_id->data;
3303 fep->quirks = pdev->id_entry->driver_data;
3304
3305 fep->netdev = ndev;
3306 fep->num_rx_queues = num_rx_qs;
3307 fep->num_tx_queues = num_tx_qs;
3308
3309 #if !defined(CONFIG_M5272)
3310 /* default enable pause frame auto negotiation */
3311 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3312 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3313 #endif
3314
3315 /* Select default pin state */
3316 pinctrl_pm_select_default_state(&pdev->dev);
3317
3318 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3319 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3320 if (IS_ERR(fep->hwp)) {
3321 ret = PTR_ERR(fep->hwp);
3322 goto failed_ioremap;
3323 }
3324
3325 fep->pdev = pdev;
3326 fep->dev_id = dev_id++;
3327
3328 platform_set_drvdata(pdev, ndev);
3329
3330 if ((of_machine_is_compatible("fsl,imx6q") ||
3331 of_machine_is_compatible("fsl,imx6dl")) &&
3332 !of_property_read_bool(np, "fsl,err006687-workaround-present"))
3333 fep->quirks |= FEC_QUIRK_ERR006687;
3334
3335 if (of_get_property(np, "fsl,magic-packet", NULL))
3336 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3337
3338 phy_node = of_parse_phandle(np, "phy-handle", 0);
3339 if (!phy_node && of_phy_is_fixed_link(np)) {
3340 ret = of_phy_register_fixed_link(np);
3341 if (ret < 0) {
3342 dev_err(&pdev->dev,
3343 "broken fixed-link specification\n");
3344 goto failed_phy;
3345 }
3346 phy_node = of_node_get(np);
3347 }
3348 fep->phy_node = phy_node;
3349
3350 ret = of_get_phy_mode(pdev->dev.of_node);
3351 if (ret < 0) {
3352 pdata = dev_get_platdata(&pdev->dev);
3353 if (pdata)
3354 fep->phy_interface = pdata->phy;
3355 else
3356 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3357 } else {
3358 fep->phy_interface = ret;
3359 }
3360
3361 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3362 if (IS_ERR(fep->clk_ipg)) {
3363 ret = PTR_ERR(fep->clk_ipg);
3364 goto failed_clk;
3365 }
3366
3367 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3368 if (IS_ERR(fep->clk_ahb)) {
3369 ret = PTR_ERR(fep->clk_ahb);
3370 goto failed_clk;
3371 }
3372
3373 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3374
3375 /* enet_out is optional, depends on board */
3376 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3377 if (IS_ERR(fep->clk_enet_out))
3378 fep->clk_enet_out = NULL;
3379
3380 fep->ptp_clk_on = false;
3381 mutex_init(&fep->ptp_clk_mutex);
3382
3383 /* clk_ref is optional, depends on board */
3384 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3385 if (IS_ERR(fep->clk_ref))
3386 fep->clk_ref = NULL;
3387
3388 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3389 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3390 if (IS_ERR(fep->clk_ptp)) {
3391 fep->clk_ptp = NULL;
3392 fep->bufdesc_ex = false;
3393 }
3394
3395 ret = fec_enet_clk_enable(ndev, true);
3396 if (ret)
3397 goto failed_clk;
3398
3399 ret = clk_prepare_enable(fep->clk_ipg);
3400 if (ret)
3401 goto failed_clk_ipg;
3402
3403 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3404 if (!IS_ERR(fep->reg_phy)) {
3405 ret = regulator_enable(fep->reg_phy);
3406 if (ret) {
3407 dev_err(&pdev->dev,
3408 "Failed to enable phy regulator: %d\n", ret);
3409 clk_disable_unprepare(fep->clk_ipg);
3410 goto failed_regulator;
3411 }
3412 } else {
3413 fep->reg_phy = NULL;
3414 }
3415
3416 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3417 pm_runtime_use_autosuspend(&pdev->dev);
3418 pm_runtime_get_noresume(&pdev->dev);
3419 pm_runtime_set_active(&pdev->dev);
3420 pm_runtime_enable(&pdev->dev);
3421
3422 ret = fec_reset_phy(pdev);
3423 if (ret)
3424 goto failed_reset;
3425
3426 if (fep->bufdesc_ex)
3427 fec_ptp_init(pdev);
3428
3429 ret = fec_enet_init(ndev);
3430 if (ret)
3431 goto failed_init;
3432
3433 for (i = 0; i < FEC_IRQ_NUM; i++) {
3434 irq = platform_get_irq(pdev, i);
3435 if (irq < 0) {
3436 if (i)
3437 break;
3438 ret = irq;
3439 goto failed_irq;
3440 }
3441 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3442 0, pdev->name, ndev);
3443 if (ret)
3444 goto failed_irq;
3445
3446 fep->irq[i] = irq;
3447 }
3448
3449 init_completion(&fep->mdio_done);
3450 ret = fec_enet_mii_init(pdev);
3451 if (ret)
3452 goto failed_mii_init;
3453
3454 /* Carrier starts down, phylib will bring it up */
3455 netif_carrier_off(ndev);
3456 fec_enet_clk_enable(ndev, false);
3457 pinctrl_pm_select_sleep_state(&pdev->dev);
3458
3459 ret = register_netdev(ndev);
3460 if (ret)
3461 goto failed_register;
3462
3463 device_init_wakeup(&ndev->dev, fep->wol_flag &
3464 FEC_WOL_HAS_MAGIC_PACKET);
3465
3466 if (fep->bufdesc_ex && fep->ptp_clock)
3467 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3468
3469 fep->rx_copybreak = COPYBREAK_DEFAULT;
3470 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3471
3472 pm_runtime_mark_last_busy(&pdev->dev);
3473 pm_runtime_put_autosuspend(&pdev->dev);
3474
3475 return 0;
3476
3477 failed_register:
3478 fec_enet_mii_remove(fep);
3479 failed_mii_init:
3480 failed_irq:
3481 failed_init:
3482 fec_ptp_stop(pdev);
3483 if (fep->reg_phy)
3484 regulator_disable(fep->reg_phy);
3485 failed_reset:
3486 pm_runtime_put(&pdev->dev);
3487 pm_runtime_disable(&pdev->dev);
3488 failed_regulator:
3489 failed_clk_ipg:
3490 fec_enet_clk_enable(ndev, false);
3491 failed_clk:
3492 if (of_phy_is_fixed_link(np))
3493 of_phy_deregister_fixed_link(np);
3494 failed_phy:
3495 of_node_put(phy_node);
3496 failed_ioremap:
3497 free_netdev(ndev);
3498
3499 return ret;
3500 }
3501
3502 static int
3503 fec_drv_remove(struct platform_device *pdev)
3504 {
3505 struct net_device *ndev = platform_get_drvdata(pdev);
3506 struct fec_enet_private *fep = netdev_priv(ndev);
3507 struct device_node *np = pdev->dev.of_node;
3508
3509 cancel_work_sync(&fep->tx_timeout_work);
3510 fec_ptp_stop(pdev);
3511 unregister_netdev(ndev);
3512 fec_enet_mii_remove(fep);
3513 if (fep->reg_phy)
3514 regulator_disable(fep->reg_phy);
3515 if (of_phy_is_fixed_link(np))
3516 of_phy_deregister_fixed_link(np);
3517 of_node_put(fep->phy_node);
3518 free_netdev(ndev);
3519
3520 return 0;
3521 }
3522
3523 static int __maybe_unused fec_suspend(struct device *dev)
3524 {
3525 struct net_device *ndev = dev_get_drvdata(dev);
3526 struct fec_enet_private *fep = netdev_priv(ndev);
3527
3528 rtnl_lock();
3529 if (netif_running(ndev)) {
3530 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3531 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
3532 phy_stop(ndev->phydev);
3533 napi_disable(&fep->napi);
3534 netif_tx_lock_bh(ndev);
3535 netif_device_detach(ndev);
3536 netif_tx_unlock_bh(ndev);
3537 fec_stop(ndev);
3538 fec_enet_clk_enable(ndev, false);
3539 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3540 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3541 }
3542 rtnl_unlock();
3543
3544 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3545 regulator_disable(fep->reg_phy);
3546
3547 /* SOC supply clock to phy, when clock is disabled, phy link down
3548 * SOC control phy regulator, when regulator is disabled, phy link down
3549 */
3550 if (fep->clk_enet_out || fep->reg_phy)
3551 fep->link = 0;
3552
3553 return 0;
3554 }
3555
3556 static int __maybe_unused fec_resume(struct device *dev)
3557 {
3558 struct net_device *ndev = dev_get_drvdata(dev);
3559 struct fec_enet_private *fep = netdev_priv(ndev);
3560 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
3561 int ret;
3562 int val;
3563
3564 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
3565 ret = regulator_enable(fep->reg_phy);
3566 if (ret)
3567 return ret;
3568 }
3569
3570 rtnl_lock();
3571 if (netif_running(ndev)) {
3572 ret = fec_enet_clk_enable(ndev, true);
3573 if (ret) {
3574 rtnl_unlock();
3575 goto failed_clk;
3576 }
3577 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3578 if (pdata && pdata->sleep_mode_enable)
3579 pdata->sleep_mode_enable(false);
3580 val = readl(fep->hwp + FEC_ECNTRL);
3581 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3582 writel(val, fep->hwp + FEC_ECNTRL);
3583 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3584 } else {
3585 pinctrl_pm_select_default_state(&fep->pdev->dev);
3586 }
3587 fec_restart(ndev);
3588 netif_tx_lock_bh(ndev);
3589 netif_device_attach(ndev);
3590 netif_tx_unlock_bh(ndev);
3591 napi_enable(&fep->napi);
3592 phy_start(ndev->phydev);
3593 }
3594 rtnl_unlock();
3595
3596 return 0;
3597
3598 failed_clk:
3599 if (fep->reg_phy)
3600 regulator_disable(fep->reg_phy);
3601 return ret;
3602 }
3603
3604 static int __maybe_unused fec_runtime_suspend(struct device *dev)
3605 {
3606 struct net_device *ndev = dev_get_drvdata(dev);
3607 struct fec_enet_private *fep = netdev_priv(ndev);
3608
3609 clk_disable_unprepare(fep->clk_ipg);
3610
3611 return 0;
3612 }
3613
3614 static int __maybe_unused fec_runtime_resume(struct device *dev)
3615 {
3616 struct net_device *ndev = dev_get_drvdata(dev);
3617 struct fec_enet_private *fep = netdev_priv(ndev);
3618
3619 return clk_prepare_enable(fep->clk_ipg);
3620 }
3621
3622 static const struct dev_pm_ops fec_pm_ops = {
3623 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3624 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3625 };
3626
3627 static struct platform_driver fec_driver = {
3628 .driver = {
3629 .name = DRIVER_NAME,
3630 .pm = &fec_pm_ops,
3631 .of_match_table = fec_dt_ids,
3632 },
3633 .id_table = fec_devtype,
3634 .probe = fec_probe,
3635 .remove = fec_drv_remove,
3636 };
3637
3638 module_platform_driver(fec_driver);
3639
3640 MODULE_ALIAS("platform:"DRIVER_NAME);
3641 MODULE_LICENSE("GPL");
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