1 /* drivers/net/ethernet/freescale/gianfar.c
3 * Gianfar Ethernet Driver
4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
6 * Based on 8260_io/fcc_enet.c
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12 * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
13 * Copyright 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/init.h>
74 #include <linux/delay.h>
75 #include <linux/netdevice.h>
76 #include <linux/etherdevice.h>
77 #include <linux/skbuff.h>
78 #include <linux/if_vlan.h>
79 #include <linux/spinlock.h>
81 #include <linux/of_mdio.h>
82 #include <linux/of_platform.h>
84 #include <linux/tcp.h>
85 #include <linux/udp.h>
87 #include <linux/net_tstamp.h>
92 #include <asm/uaccess.h>
93 #include <linux/module.h>
94 #include <linux/dma-mapping.h>
95 #include <linux/crc32.h>
96 #include <linux/mii.h>
97 #include <linux/phy.h>
98 #include <linux/phy_fixed.h>
100 #include <linux/of_net.h>
104 #define TX_TIMEOUT (1*HZ)
106 const char gfar_driver_version
[] = "1.3";
108 static int gfar_enet_open(struct net_device
*dev
);
109 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
110 static void gfar_reset_task(struct work_struct
*work
);
111 static void gfar_timeout(struct net_device
*dev
);
112 static int gfar_close(struct net_device
*dev
);
113 struct sk_buff
*gfar_new_skb(struct net_device
*dev
);
114 static void gfar_new_rxbdp(struct gfar_priv_rx_q
*rx_queue
, struct rxbd8
*bdp
,
115 struct sk_buff
*skb
);
116 static int gfar_set_mac_address(struct net_device
*dev
);
117 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
);
118 static irqreturn_t
gfar_error(int irq
, void *dev_id
);
119 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
);
120 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
);
121 static void adjust_link(struct net_device
*dev
);
122 static void init_registers(struct net_device
*dev
);
123 static int init_phy(struct net_device
*dev
);
124 static int gfar_probe(struct platform_device
*ofdev
);
125 static int gfar_remove(struct platform_device
*ofdev
);
126 static void free_skb_resources(struct gfar_private
*priv
);
127 static void gfar_set_multi(struct net_device
*dev
);
128 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
);
129 static void gfar_configure_serdes(struct net_device
*dev
);
130 static int gfar_poll(struct napi_struct
*napi
, int budget
);
131 #ifdef CONFIG_NET_POLL_CONTROLLER
132 static void gfar_netpoll(struct net_device
*dev
);
134 int gfar_clean_rx_ring(struct gfar_priv_rx_q
*rx_queue
, int rx_work_limit
);
135 static void gfar_clean_tx_ring(struct gfar_priv_tx_q
*tx_queue
);
136 static void gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
137 int amount_pull
, struct napi_struct
*napi
);
138 void gfar_halt(struct net_device
*dev
);
139 static void gfar_halt_nodisable(struct net_device
*dev
);
140 void gfar_start(struct net_device
*dev
);
141 static void gfar_clear_exact_match(struct net_device
*dev
);
142 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
,
144 static int gfar_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
);
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
150 static void gfar_init_rxbdp(struct gfar_priv_rx_q
*rx_queue
, struct rxbd8
*bdp
,
157 lstatus
= BD_LFLAG(RXBD_EMPTY
| RXBD_INTERRUPT
);
158 if (bdp
== rx_queue
->rx_bd_base
+ rx_queue
->rx_ring_size
- 1)
159 lstatus
|= BD_LFLAG(RXBD_WRAP
);
163 bdp
->lstatus
= lstatus
;
166 static int gfar_init_bds(struct net_device
*ndev
)
168 struct gfar_private
*priv
= netdev_priv(ndev
);
169 struct gfar_priv_tx_q
*tx_queue
= NULL
;
170 struct gfar_priv_rx_q
*rx_queue
= NULL
;
175 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
176 tx_queue
= priv
->tx_queue
[i
];
177 /* Initialize some variables in our dev structure */
178 tx_queue
->num_txbdfree
= tx_queue
->tx_ring_size
;
179 tx_queue
->dirty_tx
= tx_queue
->tx_bd_base
;
180 tx_queue
->cur_tx
= tx_queue
->tx_bd_base
;
181 tx_queue
->skb_curtx
= 0;
182 tx_queue
->skb_dirtytx
= 0;
184 /* Initialize Transmit Descriptor Ring */
185 txbdp
= tx_queue
->tx_bd_base
;
186 for (j
= 0; j
< tx_queue
->tx_ring_size
; j
++) {
192 /* Set the last descriptor in the ring to indicate wrap */
194 txbdp
->status
|= TXBD_WRAP
;
197 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
198 rx_queue
= priv
->rx_queue
[i
];
199 rx_queue
->cur_rx
= rx_queue
->rx_bd_base
;
200 rx_queue
->skb_currx
= 0;
201 rxbdp
= rx_queue
->rx_bd_base
;
203 for (j
= 0; j
< rx_queue
->rx_ring_size
; j
++) {
204 struct sk_buff
*skb
= rx_queue
->rx_skbuff
[j
];
207 gfar_init_rxbdp(rx_queue
, rxbdp
,
210 skb
= gfar_new_skb(ndev
);
212 netdev_err(ndev
, "Can't allocate RX buffers\n");
215 rx_queue
->rx_skbuff
[j
] = skb
;
217 gfar_new_rxbdp(rx_queue
, rxbdp
, skb
);
228 static int gfar_alloc_skb_resources(struct net_device
*ndev
)
233 struct gfar_private
*priv
= netdev_priv(ndev
);
234 struct device
*dev
= priv
->dev
;
235 struct gfar_priv_tx_q
*tx_queue
= NULL
;
236 struct gfar_priv_rx_q
*rx_queue
= NULL
;
238 priv
->total_tx_ring_size
= 0;
239 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
240 priv
->total_tx_ring_size
+= priv
->tx_queue
[i
]->tx_ring_size
;
242 priv
->total_rx_ring_size
= 0;
243 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
244 priv
->total_rx_ring_size
+= priv
->rx_queue
[i
]->rx_ring_size
;
246 /* Allocate memory for the buffer descriptors */
247 vaddr
= dma_alloc_coherent(dev
,
248 (priv
->total_tx_ring_size
*
249 sizeof(struct txbd8
)) +
250 (priv
->total_rx_ring_size
*
251 sizeof(struct rxbd8
)),
256 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
257 tx_queue
= priv
->tx_queue
[i
];
258 tx_queue
->tx_bd_base
= vaddr
;
259 tx_queue
->tx_bd_dma_base
= addr
;
260 tx_queue
->dev
= ndev
;
261 /* enet DMA only understands physical addresses */
262 addr
+= sizeof(struct txbd8
) * tx_queue
->tx_ring_size
;
263 vaddr
+= sizeof(struct txbd8
) * tx_queue
->tx_ring_size
;
266 /* Start the rx descriptor ring where the tx ring leaves off */
267 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
268 rx_queue
= priv
->rx_queue
[i
];
269 rx_queue
->rx_bd_base
= vaddr
;
270 rx_queue
->rx_bd_dma_base
= addr
;
271 rx_queue
->dev
= ndev
;
272 addr
+= sizeof(struct rxbd8
) * rx_queue
->rx_ring_size
;
273 vaddr
+= sizeof(struct rxbd8
) * rx_queue
->rx_ring_size
;
276 /* Setup the skbuff rings */
277 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
278 tx_queue
= priv
->tx_queue
[i
];
279 tx_queue
->tx_skbuff
=
280 kmalloc_array(tx_queue
->tx_ring_size
,
281 sizeof(*tx_queue
->tx_skbuff
),
283 if (!tx_queue
->tx_skbuff
)
286 for (k
= 0; k
< tx_queue
->tx_ring_size
; k
++)
287 tx_queue
->tx_skbuff
[k
] = NULL
;
290 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
291 rx_queue
= priv
->rx_queue
[i
];
292 rx_queue
->rx_skbuff
=
293 kmalloc_array(rx_queue
->rx_ring_size
,
294 sizeof(*rx_queue
->rx_skbuff
),
296 if (!rx_queue
->rx_skbuff
)
299 for (j
= 0; j
< rx_queue
->rx_ring_size
; j
++)
300 rx_queue
->rx_skbuff
[j
] = NULL
;
303 if (gfar_init_bds(ndev
))
309 free_skb_resources(priv
);
313 static void gfar_init_tx_rx_base(struct gfar_private
*priv
)
315 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
319 baddr
= ®s
->tbase0
;
320 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
321 gfar_write(baddr
, priv
->tx_queue
[i
]->tx_bd_dma_base
);
325 baddr
= ®s
->rbase0
;
326 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
327 gfar_write(baddr
, priv
->rx_queue
[i
]->rx_bd_dma_base
);
332 static void gfar_init_mac(struct net_device
*ndev
)
334 struct gfar_private
*priv
= netdev_priv(ndev
);
335 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
340 /* write the tx/rx base registers */
341 gfar_init_tx_rx_base(priv
);
343 /* Configure the coalescing support */
344 gfar_configure_coalescing_all(priv
);
346 /* set this when rx hw offload (TOE) functions are being used */
347 priv
->uses_rxfcb
= 0;
349 if (priv
->rx_filer_enable
) {
350 rctrl
|= RCTRL_FILREN
;
351 /* Program the RIR0 reg with the required distribution */
352 gfar_write(®s
->rir0
, DEFAULT_RIR0
);
355 /* Restore PROMISC mode */
356 if (ndev
->flags
& IFF_PROMISC
)
359 if (ndev
->features
& NETIF_F_RXCSUM
) {
360 rctrl
|= RCTRL_CHECKSUMMING
;
361 priv
->uses_rxfcb
= 1;
364 if (priv
->extended_hash
) {
365 rctrl
|= RCTRL_EXTHASH
;
367 gfar_clear_exact_match(ndev
);
372 rctrl
&= ~RCTRL_PAL_MASK
;
373 rctrl
|= RCTRL_PADDING(priv
->padding
);
376 /* Insert receive time stamps into padding alignment bytes */
377 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_TIMER
) {
378 rctrl
&= ~RCTRL_PAL_MASK
;
379 rctrl
|= RCTRL_PADDING(8);
383 /* Enable HW time stamping if requested from user space */
384 if (priv
->hwts_rx_en
) {
385 rctrl
|= RCTRL_PRSDEP_INIT
| RCTRL_TS_ENABLE
;
386 priv
->uses_rxfcb
= 1;
389 if (ndev
->features
& NETIF_F_HW_VLAN_CTAG_RX
) {
390 rctrl
|= RCTRL_VLEX
| RCTRL_PRSDEP_INIT
;
391 priv
->uses_rxfcb
= 1;
394 /* Init rctrl based on our settings */
395 gfar_write(®s
->rctrl
, rctrl
);
397 if (ndev
->features
& NETIF_F_IP_CSUM
)
398 tctrl
|= TCTRL_INIT_CSUM
;
400 if (priv
->prio_sched_en
)
401 tctrl
|= TCTRL_TXSCHED_PRIO
;
403 tctrl
|= TCTRL_TXSCHED_WRRS
;
404 gfar_write(®s
->tr03wt
, DEFAULT_WRRS_WEIGHT
);
405 gfar_write(®s
->tr47wt
, DEFAULT_WRRS_WEIGHT
);
408 gfar_write(®s
->tctrl
, tctrl
);
410 /* Set the extraction length and index */
411 attrs
= ATTRELI_EL(priv
->rx_stash_size
) |
412 ATTRELI_EI(priv
->rx_stash_index
);
414 gfar_write(®s
->attreli
, attrs
);
416 /* Start with defaults, and add stashing or locking
417 * depending on the approprate variables
419 attrs
= ATTR_INIT_SETTINGS
;
421 if (priv
->bd_stash_en
)
422 attrs
|= ATTR_BDSTASH
;
424 if (priv
->rx_stash_size
!= 0)
425 attrs
|= ATTR_BUFSTASH
;
427 gfar_write(®s
->attr
, attrs
);
429 gfar_write(®s
->fifo_tx_thr
, priv
->fifo_threshold
);
430 gfar_write(®s
->fifo_tx_starve
, priv
->fifo_starve
);
431 gfar_write(®s
->fifo_tx_starve_shutoff
, priv
->fifo_starve_off
);
434 static struct net_device_stats
*gfar_get_stats(struct net_device
*dev
)
436 struct gfar_private
*priv
= netdev_priv(dev
);
437 unsigned long rx_packets
= 0, rx_bytes
= 0, rx_dropped
= 0;
438 unsigned long tx_packets
= 0, tx_bytes
= 0;
441 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
442 rx_packets
+= priv
->rx_queue
[i
]->stats
.rx_packets
;
443 rx_bytes
+= priv
->rx_queue
[i
]->stats
.rx_bytes
;
444 rx_dropped
+= priv
->rx_queue
[i
]->stats
.rx_dropped
;
447 dev
->stats
.rx_packets
= rx_packets
;
448 dev
->stats
.rx_bytes
= rx_bytes
;
449 dev
->stats
.rx_dropped
= rx_dropped
;
451 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
452 tx_bytes
+= priv
->tx_queue
[i
]->stats
.tx_bytes
;
453 tx_packets
+= priv
->tx_queue
[i
]->stats
.tx_packets
;
456 dev
->stats
.tx_bytes
= tx_bytes
;
457 dev
->stats
.tx_packets
= tx_packets
;
462 static const struct net_device_ops gfar_netdev_ops
= {
463 .ndo_open
= gfar_enet_open
,
464 .ndo_start_xmit
= gfar_start_xmit
,
465 .ndo_stop
= gfar_close
,
466 .ndo_change_mtu
= gfar_change_mtu
,
467 .ndo_set_features
= gfar_set_features
,
468 .ndo_set_rx_mode
= gfar_set_multi
,
469 .ndo_tx_timeout
= gfar_timeout
,
470 .ndo_do_ioctl
= gfar_ioctl
,
471 .ndo_get_stats
= gfar_get_stats
,
472 .ndo_set_mac_address
= eth_mac_addr
,
473 .ndo_validate_addr
= eth_validate_addr
,
474 #ifdef CONFIG_NET_POLL_CONTROLLER
475 .ndo_poll_controller
= gfar_netpoll
,
479 void lock_rx_qs(struct gfar_private
*priv
)
483 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
484 spin_lock(&priv
->rx_queue
[i
]->rxlock
);
487 void lock_tx_qs(struct gfar_private
*priv
)
491 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
492 spin_lock(&priv
->tx_queue
[i
]->txlock
);
495 void unlock_rx_qs(struct gfar_private
*priv
)
499 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
500 spin_unlock(&priv
->rx_queue
[i
]->rxlock
);
503 void unlock_tx_qs(struct gfar_private
*priv
)
507 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
508 spin_unlock(&priv
->tx_queue
[i
]->txlock
);
511 static void free_tx_pointers(struct gfar_private
*priv
)
515 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
516 kfree(priv
->tx_queue
[i
]);
519 static void free_rx_pointers(struct gfar_private
*priv
)
523 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
524 kfree(priv
->rx_queue
[i
]);
527 static void unmap_group_regs(struct gfar_private
*priv
)
531 for (i
= 0; i
< MAXGROUPS
; i
++)
532 if (priv
->gfargrp
[i
].regs
)
533 iounmap(priv
->gfargrp
[i
].regs
);
536 static void free_gfar_dev(struct gfar_private
*priv
)
540 for (i
= 0; i
< priv
->num_grps
; i
++)
541 for (j
= 0; j
< GFAR_NUM_IRQS
; j
++) {
542 kfree(priv
->gfargrp
[i
].irqinfo
[j
]);
543 priv
->gfargrp
[i
].irqinfo
[j
] = NULL
;
546 free_netdev(priv
->ndev
);
549 static void disable_napi(struct gfar_private
*priv
)
553 for (i
= 0; i
< priv
->num_grps
; i
++)
554 napi_disable(&priv
->gfargrp
[i
].napi
);
557 static void enable_napi(struct gfar_private
*priv
)
561 for (i
= 0; i
< priv
->num_grps
; i
++)
562 napi_enable(&priv
->gfargrp
[i
].napi
);
565 static int gfar_parse_group(struct device_node
*np
,
566 struct gfar_private
*priv
, const char *model
)
568 struct gfar_priv_grp
*grp
= &priv
->gfargrp
[priv
->num_grps
];
572 for (i
= 0; i
< GFAR_NUM_IRQS
; i
++) {
573 grp
->irqinfo
[i
] = kzalloc(sizeof(struct gfar_irqinfo
),
575 if (!grp
->irqinfo
[i
])
579 grp
->regs
= of_iomap(np
, 0);
583 gfar_irq(grp
, TX
)->irq
= irq_of_parse_and_map(np
, 0);
585 /* If we aren't the FEC we have multiple interrupts */
586 if (model
&& strcasecmp(model
, "FEC")) {
587 gfar_irq(grp
, RX
)->irq
= irq_of_parse_and_map(np
, 1);
588 gfar_irq(grp
, ER
)->irq
= irq_of_parse_and_map(np
, 2);
589 if (gfar_irq(grp
, TX
)->irq
== NO_IRQ
||
590 gfar_irq(grp
, RX
)->irq
== NO_IRQ
||
591 gfar_irq(grp
, ER
)->irq
== NO_IRQ
)
595 grp
->grp_id
= priv
->num_grps
;
597 spin_lock_init(&grp
->grplock
);
598 if (priv
->mode
== MQ_MG_MODE
) {
599 queue_mask
= (u32
*)of_get_property(np
, "fsl,rx-bit-map", NULL
);
600 grp
->rx_bit_map
= queue_mask
?
601 *queue_mask
: (DEFAULT_MAPPING
>> priv
->num_grps
);
602 queue_mask
= (u32
*)of_get_property(np
, "fsl,tx-bit-map", NULL
);
603 grp
->tx_bit_map
= queue_mask
?
604 *queue_mask
: (DEFAULT_MAPPING
>> priv
->num_grps
);
606 grp
->rx_bit_map
= 0xFF;
607 grp
->tx_bit_map
= 0xFF;
614 static int gfar_of_init(struct platform_device
*ofdev
, struct net_device
**pdev
)
618 const void *mac_addr
;
620 struct net_device
*dev
= NULL
;
621 struct gfar_private
*priv
= NULL
;
622 struct device_node
*np
= ofdev
->dev
.of_node
;
623 struct device_node
*child
= NULL
;
625 const u32
*stash_len
;
626 const u32
*stash_idx
;
627 unsigned int num_tx_qs
, num_rx_qs
;
628 u32
*tx_queues
, *rx_queues
;
630 if (!np
|| !of_device_is_available(np
))
633 /* parse the num of tx and rx queues */
634 tx_queues
= (u32
*)of_get_property(np
, "fsl,num_tx_queues", NULL
);
635 num_tx_qs
= tx_queues
? *tx_queues
: 1;
637 if (num_tx_qs
> MAX_TX_QS
) {
638 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
639 num_tx_qs
, MAX_TX_QS
);
640 pr_err("Cannot do alloc_etherdev, aborting\n");
644 rx_queues
= (u32
*)of_get_property(np
, "fsl,num_rx_queues", NULL
);
645 num_rx_qs
= rx_queues
? *rx_queues
: 1;
647 if (num_rx_qs
> MAX_RX_QS
) {
648 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
649 num_rx_qs
, MAX_RX_QS
);
650 pr_err("Cannot do alloc_etherdev, aborting\n");
654 *pdev
= alloc_etherdev_mq(sizeof(*priv
), num_tx_qs
);
659 priv
= netdev_priv(dev
);
662 priv
->num_tx_queues
= num_tx_qs
;
663 netif_set_real_num_rx_queues(dev
, num_rx_qs
);
664 priv
->num_rx_queues
= num_rx_qs
;
665 priv
->num_grps
= 0x0;
667 /* Init Rx queue filer rule set linked list */
668 INIT_LIST_HEAD(&priv
->rx_list
.list
);
669 priv
->rx_list
.count
= 0;
670 mutex_init(&priv
->rx_queue_access
);
672 model
= of_get_property(np
, "model", NULL
);
674 for (i
= 0; i
< MAXGROUPS
; i
++)
675 priv
->gfargrp
[i
].regs
= NULL
;
677 /* Parse and initialize group specific information */
678 if (of_device_is_compatible(np
, "fsl,etsec2")) {
679 priv
->mode
= MQ_MG_MODE
;
680 for_each_child_of_node(np
, child
) {
681 err
= gfar_parse_group(child
, priv
, model
);
686 priv
->mode
= SQ_SG_MODE
;
687 err
= gfar_parse_group(np
, priv
, model
);
692 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
693 priv
->tx_queue
[i
] = NULL
;
694 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
695 priv
->rx_queue
[i
] = NULL
;
697 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
698 priv
->tx_queue
[i
] = kzalloc(sizeof(struct gfar_priv_tx_q
),
700 if (!priv
->tx_queue
[i
]) {
702 goto tx_alloc_failed
;
704 priv
->tx_queue
[i
]->tx_skbuff
= NULL
;
705 priv
->tx_queue
[i
]->qindex
= i
;
706 priv
->tx_queue
[i
]->dev
= dev
;
707 spin_lock_init(&(priv
->tx_queue
[i
]->txlock
));
710 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
711 priv
->rx_queue
[i
] = kzalloc(sizeof(struct gfar_priv_rx_q
),
713 if (!priv
->rx_queue
[i
]) {
715 goto rx_alloc_failed
;
717 priv
->rx_queue
[i
]->rx_skbuff
= NULL
;
718 priv
->rx_queue
[i
]->qindex
= i
;
719 priv
->rx_queue
[i
]->dev
= dev
;
720 spin_lock_init(&(priv
->rx_queue
[i
]->rxlock
));
724 stash
= of_get_property(np
, "bd-stash", NULL
);
727 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_BD_STASHING
;
728 priv
->bd_stash_en
= 1;
731 stash_len
= of_get_property(np
, "rx-stash-len", NULL
);
734 priv
->rx_stash_size
= *stash_len
;
736 stash_idx
= of_get_property(np
, "rx-stash-idx", NULL
);
739 priv
->rx_stash_index
= *stash_idx
;
741 if (stash_len
|| stash_idx
)
742 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_BUF_STASHING
;
744 mac_addr
= of_get_mac_address(np
);
747 memcpy(dev
->dev_addr
, mac_addr
, ETH_ALEN
);
749 if (model
&& !strcasecmp(model
, "TSEC"))
750 priv
->device_flags
= FSL_GIANFAR_DEV_HAS_GIGABIT
|
751 FSL_GIANFAR_DEV_HAS_COALESCE
|
752 FSL_GIANFAR_DEV_HAS_RMON
|
753 FSL_GIANFAR_DEV_HAS_MULTI_INTR
;
755 if (model
&& !strcasecmp(model
, "eTSEC"))
756 priv
->device_flags
= FSL_GIANFAR_DEV_HAS_GIGABIT
|
757 FSL_GIANFAR_DEV_HAS_COALESCE
|
758 FSL_GIANFAR_DEV_HAS_RMON
|
759 FSL_GIANFAR_DEV_HAS_MULTI_INTR
|
760 FSL_GIANFAR_DEV_HAS_PADDING
|
761 FSL_GIANFAR_DEV_HAS_CSUM
|
762 FSL_GIANFAR_DEV_HAS_VLAN
|
763 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
|
764 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
|
765 FSL_GIANFAR_DEV_HAS_TIMER
;
767 ctype
= of_get_property(np
, "phy-connection-type", NULL
);
769 /* We only care about rgmii-id. The rest are autodetected */
770 if (ctype
&& !strcmp(ctype
, "rgmii-id"))
771 priv
->interface
= PHY_INTERFACE_MODE_RGMII_ID
;
773 priv
->interface
= PHY_INTERFACE_MODE_MII
;
775 if (of_get_property(np
, "fsl,magic-packet", NULL
))
776 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
;
778 priv
->phy_node
= of_parse_phandle(np
, "phy-handle", 0);
780 /* Find the TBI PHY. If it's not there, we don't support SGMII */
781 priv
->tbi_node
= of_parse_phandle(np
, "tbi-handle", 0);
786 free_rx_pointers(priv
);
788 free_tx_pointers(priv
);
790 unmap_group_regs(priv
);
795 static int gfar_hwtstamp_ioctl(struct net_device
*netdev
,
796 struct ifreq
*ifr
, int cmd
)
798 struct hwtstamp_config config
;
799 struct gfar_private
*priv
= netdev_priv(netdev
);
801 if (copy_from_user(&config
, ifr
->ifr_data
, sizeof(config
)))
804 /* reserved for future extensions */
808 switch (config
.tx_type
) {
809 case HWTSTAMP_TX_OFF
:
810 priv
->hwts_tx_en
= 0;
813 if (!(priv
->device_flags
& FSL_GIANFAR_DEV_HAS_TIMER
))
815 priv
->hwts_tx_en
= 1;
821 switch (config
.rx_filter
) {
822 case HWTSTAMP_FILTER_NONE
:
823 if (priv
->hwts_rx_en
) {
825 priv
->hwts_rx_en
= 0;
826 startup_gfar(netdev
);
830 if (!(priv
->device_flags
& FSL_GIANFAR_DEV_HAS_TIMER
))
832 if (!priv
->hwts_rx_en
) {
834 priv
->hwts_rx_en
= 1;
835 startup_gfar(netdev
);
837 config
.rx_filter
= HWTSTAMP_FILTER_ALL
;
841 return copy_to_user(ifr
->ifr_data
, &config
, sizeof(config
)) ?
845 /* Ioctl MII Interface */
846 static int gfar_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
848 struct gfar_private
*priv
= netdev_priv(dev
);
850 if (!netif_running(dev
))
853 if (cmd
== SIOCSHWTSTAMP
)
854 return gfar_hwtstamp_ioctl(dev
, rq
, cmd
);
859 return phy_mii_ioctl(priv
->phydev
, rq
, cmd
);
862 static unsigned int reverse_bitmap(unsigned int bit_map
, unsigned int max_qs
)
864 unsigned int new_bit_map
= 0x0;
865 int mask
= 0x1 << (max_qs
- 1), i
;
867 for (i
= 0; i
< max_qs
; i
++) {
869 new_bit_map
= new_bit_map
+ (1 << i
);
875 static u32
cluster_entry_per_class(struct gfar_private
*priv
, u32 rqfar
,
878 u32 rqfpr
= FPR_FILER_MASK
;
882 rqfcr
= RQFCR_CLE
| RQFCR_PID_MASK
| RQFCR_CMP_EXACT
;
883 priv
->ftp_rqfpr
[rqfar
] = rqfpr
;
884 priv
->ftp_rqfcr
[rqfar
] = rqfcr
;
885 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
888 rqfcr
= RQFCR_CMP_NOMATCH
;
889 priv
->ftp_rqfpr
[rqfar
] = rqfpr
;
890 priv
->ftp_rqfcr
[rqfar
] = rqfcr
;
891 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
894 rqfcr
= RQFCR_CMP_EXACT
| RQFCR_PID_PARSE
| RQFCR_CLE
| RQFCR_AND
;
896 priv
->ftp_rqfcr
[rqfar
] = rqfcr
;
897 priv
->ftp_rqfpr
[rqfar
] = rqfpr
;
898 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
901 rqfcr
= RQFCR_CMP_EXACT
| RQFCR_PID_MASK
| RQFCR_AND
;
903 priv
->ftp_rqfcr
[rqfar
] = rqfcr
;
904 priv
->ftp_rqfpr
[rqfar
] = rqfpr
;
905 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
910 static void gfar_init_filer_table(struct gfar_private
*priv
)
913 u32 rqfar
= MAX_FILER_IDX
;
915 u32 rqfpr
= FPR_FILER_MASK
;
918 rqfcr
= RQFCR_CMP_MATCH
;
919 priv
->ftp_rqfcr
[rqfar
] = rqfcr
;
920 priv
->ftp_rqfpr
[rqfar
] = rqfpr
;
921 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
923 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV6
);
924 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV6
| RQFPR_UDP
);
925 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV6
| RQFPR_TCP
);
926 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV4
);
927 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV4
| RQFPR_UDP
);
928 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV4
| RQFPR_TCP
);
930 /* cur_filer_idx indicated the first non-masked rule */
931 priv
->cur_filer_idx
= rqfar
;
933 /* Rest are masked rules */
934 rqfcr
= RQFCR_CMP_NOMATCH
;
935 for (i
= 0; i
< rqfar
; i
++) {
936 priv
->ftp_rqfcr
[i
] = rqfcr
;
937 priv
->ftp_rqfpr
[i
] = rqfpr
;
938 gfar_write_filer(priv
, i
, rqfcr
, rqfpr
);
942 static void gfar_detect_errata(struct gfar_private
*priv
)
944 struct device
*dev
= &priv
->ofdev
->dev
;
945 unsigned int pvr
= mfspr(SPRN_PVR
);
946 unsigned int svr
= mfspr(SPRN_SVR
);
947 unsigned int mod
= (svr
>> 16) & 0xfff6; /* w/o E suffix */
948 unsigned int rev
= svr
& 0xffff;
950 /* MPC8313 Rev 2.0 and higher; All MPC837x */
951 if ((pvr
== 0x80850010 && mod
== 0x80b0 && rev
>= 0x0020) ||
952 (pvr
== 0x80861010 && (mod
& 0xfff9) == 0x80c0))
953 priv
->errata
|= GFAR_ERRATA_74
;
955 /* MPC8313 and MPC837x all rev */
956 if ((pvr
== 0x80850010 && mod
== 0x80b0) ||
957 (pvr
== 0x80861010 && (mod
& 0xfff9) == 0x80c0))
958 priv
->errata
|= GFAR_ERRATA_76
;
960 /* MPC8313 and MPC837x all rev */
961 if ((pvr
== 0x80850010 && mod
== 0x80b0) ||
962 (pvr
== 0x80861010 && (mod
& 0xfff9) == 0x80c0))
963 priv
->errata
|= GFAR_ERRATA_A002
;
965 /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
966 if ((pvr
== 0x80850010 && mod
== 0x80b0 && rev
< 0x0020) ||
967 (pvr
== 0x80210020 && mod
== 0x8030 && rev
== 0x0020))
968 priv
->errata
|= GFAR_ERRATA_12
;
971 dev_info(dev
, "enabled errata workarounds, flags: 0x%x\n",
975 /* Set up the ethernet device structure, private data,
976 * and anything else we need before we start
978 static int gfar_probe(struct platform_device
*ofdev
)
981 struct net_device
*dev
= NULL
;
982 struct gfar_private
*priv
= NULL
;
983 struct gfar __iomem
*regs
= NULL
;
984 int err
= 0, i
, grp_idx
= 0;
985 u32 rstat
= 0, tstat
= 0, rqueue
= 0, tqueue
= 0;
989 err
= gfar_of_init(ofdev
, &dev
);
994 priv
= netdev_priv(dev
);
997 priv
->dev
= &ofdev
->dev
;
998 SET_NETDEV_DEV(dev
, &ofdev
->dev
);
1000 spin_lock_init(&priv
->bflock
);
1001 INIT_WORK(&priv
->reset_task
, gfar_reset_task
);
1003 dev_set_drvdata(&ofdev
->dev
, priv
);
1004 regs
= priv
->gfargrp
[0].regs
;
1006 gfar_detect_errata(priv
);
1008 /* Stop the DMA engine now, in case it was running before
1009 * (The firmware could have used it, and left it running).
1013 /* Reset MAC layer */
1014 gfar_write(®s
->maccfg1
, MACCFG1_SOFT_RESET
);
1016 /* We need to delay at least 3 TX clocks */
1019 tempval
= (MACCFG1_TX_FLOW
| MACCFG1_RX_FLOW
);
1020 gfar_write(®s
->maccfg1
, tempval
);
1022 /* Initialize MACCFG2. */
1023 tempval
= MACCFG2_INIT_SETTINGS
;
1024 if (gfar_has_errata(priv
, GFAR_ERRATA_74
))
1025 tempval
|= MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
;
1026 gfar_write(®s
->maccfg2
, tempval
);
1028 /* Initialize ECNTRL */
1029 gfar_write(®s
->ecntrl
, ECNTRL_INIT_SETTINGS
);
1031 /* Set the dev->base_addr to the gfar reg region */
1032 dev
->base_addr
= (unsigned long) regs
;
1034 /* Fill in the dev structure */
1035 dev
->watchdog_timeo
= TX_TIMEOUT
;
1037 dev
->netdev_ops
= &gfar_netdev_ops
;
1038 dev
->ethtool_ops
= &gfar_ethtool_ops
;
1040 /* Register for napi ...We are registering NAPI for each grp */
1041 for (i
= 0; i
< priv
->num_grps
; i
++)
1042 netif_napi_add(dev
, &priv
->gfargrp
[i
].napi
, gfar_poll
,
1045 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_CSUM
) {
1046 dev
->hw_features
= NETIF_F_IP_CSUM
| NETIF_F_SG
|
1048 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
|
1049 NETIF_F_RXCSUM
| NETIF_F_HIGHDMA
;
1052 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_VLAN
) {
1053 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_TX
|
1054 NETIF_F_HW_VLAN_CTAG_RX
;
1055 dev
->features
|= NETIF_F_HW_VLAN_CTAG_RX
;
1058 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
) {
1059 priv
->extended_hash
= 1;
1060 priv
->hash_width
= 9;
1062 priv
->hash_regs
[0] = ®s
->igaddr0
;
1063 priv
->hash_regs
[1] = ®s
->igaddr1
;
1064 priv
->hash_regs
[2] = ®s
->igaddr2
;
1065 priv
->hash_regs
[3] = ®s
->igaddr3
;
1066 priv
->hash_regs
[4] = ®s
->igaddr4
;
1067 priv
->hash_regs
[5] = ®s
->igaddr5
;
1068 priv
->hash_regs
[6] = ®s
->igaddr6
;
1069 priv
->hash_regs
[7] = ®s
->igaddr7
;
1070 priv
->hash_regs
[8] = ®s
->gaddr0
;
1071 priv
->hash_regs
[9] = ®s
->gaddr1
;
1072 priv
->hash_regs
[10] = ®s
->gaddr2
;
1073 priv
->hash_regs
[11] = ®s
->gaddr3
;
1074 priv
->hash_regs
[12] = ®s
->gaddr4
;
1075 priv
->hash_regs
[13] = ®s
->gaddr5
;
1076 priv
->hash_regs
[14] = ®s
->gaddr6
;
1077 priv
->hash_regs
[15] = ®s
->gaddr7
;
1080 priv
->extended_hash
= 0;
1081 priv
->hash_width
= 8;
1083 priv
->hash_regs
[0] = ®s
->gaddr0
;
1084 priv
->hash_regs
[1] = ®s
->gaddr1
;
1085 priv
->hash_regs
[2] = ®s
->gaddr2
;
1086 priv
->hash_regs
[3] = ®s
->gaddr3
;
1087 priv
->hash_regs
[4] = ®s
->gaddr4
;
1088 priv
->hash_regs
[5] = ®s
->gaddr5
;
1089 priv
->hash_regs
[6] = ®s
->gaddr6
;
1090 priv
->hash_regs
[7] = ®s
->gaddr7
;
1093 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_PADDING
)
1094 priv
->padding
= DEFAULT_PADDING
;
1098 if (dev
->features
& NETIF_F_IP_CSUM
||
1099 priv
->device_flags
& FSL_GIANFAR_DEV_HAS_TIMER
)
1100 dev
->needed_headroom
= GMAC_FCB_LEN
;
1102 /* Program the isrg regs only if number of grps > 1 */
1103 if (priv
->num_grps
> 1) {
1104 baddr
= ®s
->isrg0
;
1105 for (i
= 0; i
< priv
->num_grps
; i
++) {
1106 isrg
|= (priv
->gfargrp
[i
].rx_bit_map
<< ISRG_SHIFT_RX
);
1107 isrg
|= (priv
->gfargrp
[i
].tx_bit_map
<< ISRG_SHIFT_TX
);
1108 gfar_write(baddr
, isrg
);
1114 /* Need to reverse the bit maps as bit_map's MSB is q0
1115 * but, for_each_set_bit parses from right to left, which
1116 * basically reverses the queue numbers
1118 for (i
= 0; i
< priv
->num_grps
; i
++) {
1119 priv
->gfargrp
[i
].tx_bit_map
=
1120 reverse_bitmap(priv
->gfargrp
[i
].tx_bit_map
, MAX_TX_QS
);
1121 priv
->gfargrp
[i
].rx_bit_map
=
1122 reverse_bitmap(priv
->gfargrp
[i
].rx_bit_map
, MAX_RX_QS
);
1125 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1126 * also assign queues to groups
1128 for (grp_idx
= 0; grp_idx
< priv
->num_grps
; grp_idx
++) {
1129 priv
->gfargrp
[grp_idx
].num_rx_queues
= 0x0;
1131 for_each_set_bit(i
, &priv
->gfargrp
[grp_idx
].rx_bit_map
,
1132 priv
->num_rx_queues
) {
1133 priv
->gfargrp
[grp_idx
].num_rx_queues
++;
1134 priv
->rx_queue
[i
]->grp
= &priv
->gfargrp
[grp_idx
];
1135 rstat
= rstat
| (RSTAT_CLEAR_RHALT
>> i
);
1136 rqueue
= rqueue
| ((RQUEUE_EN0
| RQUEUE_EX0
) >> i
);
1138 priv
->gfargrp
[grp_idx
].num_tx_queues
= 0x0;
1140 for_each_set_bit(i
, &priv
->gfargrp
[grp_idx
].tx_bit_map
,
1141 priv
->num_tx_queues
) {
1142 priv
->gfargrp
[grp_idx
].num_tx_queues
++;
1143 priv
->tx_queue
[i
]->grp
= &priv
->gfargrp
[grp_idx
];
1144 tstat
= tstat
| (TSTAT_CLEAR_THALT
>> i
);
1145 tqueue
= tqueue
| (TQUEUE_EN0
>> i
);
1147 priv
->gfargrp
[grp_idx
].rstat
= rstat
;
1148 priv
->gfargrp
[grp_idx
].tstat
= tstat
;
1152 gfar_write(®s
->rqueue
, rqueue
);
1153 gfar_write(®s
->tqueue
, tqueue
);
1155 priv
->rx_buffer_size
= DEFAULT_RX_BUFFER_SIZE
;
1157 /* Initializing some of the rx/tx queue level parameters */
1158 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
1159 priv
->tx_queue
[i
]->tx_ring_size
= DEFAULT_TX_RING_SIZE
;
1160 priv
->tx_queue
[i
]->num_txbdfree
= DEFAULT_TX_RING_SIZE
;
1161 priv
->tx_queue
[i
]->txcoalescing
= DEFAULT_TX_COALESCE
;
1162 priv
->tx_queue
[i
]->txic
= DEFAULT_TXIC
;
1165 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
1166 priv
->rx_queue
[i
]->rx_ring_size
= DEFAULT_RX_RING_SIZE
;
1167 priv
->rx_queue
[i
]->rxcoalescing
= DEFAULT_RX_COALESCE
;
1168 priv
->rx_queue
[i
]->rxic
= DEFAULT_RXIC
;
1171 /* always enable rx filer */
1172 priv
->rx_filer_enable
= 1;
1173 /* Enable most messages by default */
1174 priv
->msg_enable
= (NETIF_MSG_IFUP
<< 1 ) - 1;
1175 /* use pritority h/w tx queue scheduling for single queue devices */
1176 if (priv
->num_tx_queues
== 1)
1177 priv
->prio_sched_en
= 1;
1179 /* Carrier starts down, phylib will bring it up */
1180 netif_carrier_off(dev
);
1182 err
= register_netdev(dev
);
1185 pr_err("%s: Cannot register net device, aborting\n", dev
->name
);
1189 device_init_wakeup(&dev
->dev
,
1190 priv
->device_flags
&
1191 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
1193 /* fill out IRQ number and name fields */
1194 for (i
= 0; i
< priv
->num_grps
; i
++) {
1195 struct gfar_priv_grp
*grp
= &priv
->gfargrp
[i
];
1196 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1197 sprintf(gfar_irq(grp
, TX
)->name
, "%s%s%c%s",
1198 dev
->name
, "_g", '0' + i
, "_tx");
1199 sprintf(gfar_irq(grp
, RX
)->name
, "%s%s%c%s",
1200 dev
->name
, "_g", '0' + i
, "_rx");
1201 sprintf(gfar_irq(grp
, ER
)->name
, "%s%s%c%s",
1202 dev
->name
, "_g", '0' + i
, "_er");
1204 strcpy(gfar_irq(grp
, TX
)->name
, dev
->name
);
1207 /* Initialize the filer table */
1208 gfar_init_filer_table(priv
);
1210 /* Create all the sysfs files */
1211 gfar_init_sysfs(dev
);
1213 /* Print out the device info */
1214 netdev_info(dev
, "mac: %pM\n", dev
->dev_addr
);
1216 /* Even more device info helps when determining which kernel
1217 * provided which set of benchmarks.
1219 netdev_info(dev
, "Running with NAPI enabled\n");
1220 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
1221 netdev_info(dev
, "RX BD ring size for Q[%d]: %d\n",
1222 i
, priv
->rx_queue
[i
]->rx_ring_size
);
1223 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
1224 netdev_info(dev
, "TX BD ring size for Q[%d]: %d\n",
1225 i
, priv
->tx_queue
[i
]->tx_ring_size
);
1230 unmap_group_regs(priv
);
1231 free_tx_pointers(priv
);
1232 free_rx_pointers(priv
);
1234 of_node_put(priv
->phy_node
);
1236 of_node_put(priv
->tbi_node
);
1237 free_gfar_dev(priv
);
1241 static int gfar_remove(struct platform_device
*ofdev
)
1243 struct gfar_private
*priv
= dev_get_drvdata(&ofdev
->dev
);
1246 of_node_put(priv
->phy_node
);
1248 of_node_put(priv
->tbi_node
);
1250 dev_set_drvdata(&ofdev
->dev
, NULL
);
1252 unregister_netdev(priv
->ndev
);
1253 unmap_group_regs(priv
);
1254 free_gfar_dev(priv
);
1261 static int gfar_suspend(struct device
*dev
)
1263 struct gfar_private
*priv
= dev_get_drvdata(dev
);
1264 struct net_device
*ndev
= priv
->ndev
;
1265 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1266 unsigned long flags
;
1269 int magic_packet
= priv
->wol_en
&&
1270 (priv
->device_flags
&
1271 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
1273 netif_device_detach(ndev
);
1275 if (netif_running(ndev
)) {
1277 local_irq_save(flags
);
1281 gfar_halt_nodisable(ndev
);
1283 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1284 tempval
= gfar_read(®s
->maccfg1
);
1286 tempval
&= ~MACCFG1_TX_EN
;
1289 tempval
&= ~MACCFG1_RX_EN
;
1291 gfar_write(®s
->maccfg1
, tempval
);
1295 local_irq_restore(flags
);
1300 /* Enable interrupt on Magic Packet */
1301 gfar_write(®s
->imask
, IMASK_MAG
);
1303 /* Enable Magic Packet mode */
1304 tempval
= gfar_read(®s
->maccfg2
);
1305 tempval
|= MACCFG2_MPEN
;
1306 gfar_write(®s
->maccfg2
, tempval
);
1308 phy_stop(priv
->phydev
);
1315 static int gfar_resume(struct device
*dev
)
1317 struct gfar_private
*priv
= dev_get_drvdata(dev
);
1318 struct net_device
*ndev
= priv
->ndev
;
1319 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1320 unsigned long flags
;
1322 int magic_packet
= priv
->wol_en
&&
1323 (priv
->device_flags
&
1324 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
1326 if (!netif_running(ndev
)) {
1327 netif_device_attach(ndev
);
1331 if (!magic_packet
&& priv
->phydev
)
1332 phy_start(priv
->phydev
);
1334 /* Disable Magic Packet mode, in case something
1337 local_irq_save(flags
);
1341 tempval
= gfar_read(®s
->maccfg2
);
1342 tempval
&= ~MACCFG2_MPEN
;
1343 gfar_write(®s
->maccfg2
, tempval
);
1349 local_irq_restore(flags
);
1351 netif_device_attach(ndev
);
1358 static int gfar_restore(struct device
*dev
)
1360 struct gfar_private
*priv
= dev_get_drvdata(dev
);
1361 struct net_device
*ndev
= priv
->ndev
;
1363 if (!netif_running(ndev
)) {
1364 netif_device_attach(ndev
);
1369 if (gfar_init_bds(ndev
)) {
1370 free_skb_resources(priv
);
1374 init_registers(ndev
);
1375 gfar_set_mac_address(ndev
);
1376 gfar_init_mac(ndev
);
1381 priv
->oldduplex
= -1;
1384 phy_start(priv
->phydev
);
1386 netif_device_attach(ndev
);
1392 static struct dev_pm_ops gfar_pm_ops
= {
1393 .suspend
= gfar_suspend
,
1394 .resume
= gfar_resume
,
1395 .freeze
= gfar_suspend
,
1396 .thaw
= gfar_resume
,
1397 .restore
= gfar_restore
,
1400 #define GFAR_PM_OPS (&gfar_pm_ops)
1404 #define GFAR_PM_OPS NULL
1408 /* Reads the controller's registers to determine what interface
1409 * connects it to the PHY.
1411 static phy_interface_t
gfar_get_interface(struct net_device
*dev
)
1413 struct gfar_private
*priv
= netdev_priv(dev
);
1414 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1417 ecntrl
= gfar_read(®s
->ecntrl
);
1419 if (ecntrl
& ECNTRL_SGMII_MODE
)
1420 return PHY_INTERFACE_MODE_SGMII
;
1422 if (ecntrl
& ECNTRL_TBI_MODE
) {
1423 if (ecntrl
& ECNTRL_REDUCED_MODE
)
1424 return PHY_INTERFACE_MODE_RTBI
;
1426 return PHY_INTERFACE_MODE_TBI
;
1429 if (ecntrl
& ECNTRL_REDUCED_MODE
) {
1430 if (ecntrl
& ECNTRL_REDUCED_MII_MODE
) {
1431 return PHY_INTERFACE_MODE_RMII
;
1434 phy_interface_t interface
= priv
->interface
;
1436 /* This isn't autodetected right now, so it must
1437 * be set by the device tree or platform code.
1439 if (interface
== PHY_INTERFACE_MODE_RGMII_ID
)
1440 return PHY_INTERFACE_MODE_RGMII_ID
;
1442 return PHY_INTERFACE_MODE_RGMII
;
1446 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
)
1447 return PHY_INTERFACE_MODE_GMII
;
1449 return PHY_INTERFACE_MODE_MII
;
1453 /* Initializes driver's PHY state, and attaches to the PHY.
1454 * Returns 0 on success.
1456 static int init_phy(struct net_device
*dev
)
1458 struct gfar_private
*priv
= netdev_priv(dev
);
1459 uint gigabit_support
=
1460 priv
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
?
1461 SUPPORTED_1000baseT_Full
: 0;
1462 phy_interface_t interface
;
1466 priv
->oldduplex
= -1;
1468 interface
= gfar_get_interface(dev
);
1470 priv
->phydev
= of_phy_connect(dev
, priv
->phy_node
, &adjust_link
, 0,
1473 priv
->phydev
= of_phy_connect_fixed_link(dev
, &adjust_link
,
1475 if (!priv
->phydev
) {
1476 dev_err(&dev
->dev
, "could not attach to PHY\n");
1480 if (interface
== PHY_INTERFACE_MODE_SGMII
)
1481 gfar_configure_serdes(dev
);
1483 /* Remove any features not supported by the controller */
1484 priv
->phydev
->supported
&= (GFAR_SUPPORTED
| gigabit_support
);
1485 priv
->phydev
->advertising
= priv
->phydev
->supported
;
1490 /* Initialize TBI PHY interface for communicating with the
1491 * SERDES lynx PHY on the chip. We communicate with this PHY
1492 * through the MDIO bus on each controller, treating it as a
1493 * "normal" PHY at the address found in the TBIPA register. We assume
1494 * that the TBIPA register is valid. Either the MDIO bus code will set
1495 * it to a value that doesn't conflict with other PHYs on the bus, or the
1496 * value doesn't matter, as there are no other PHYs on the bus.
1498 static void gfar_configure_serdes(struct net_device
*dev
)
1500 struct gfar_private
*priv
= netdev_priv(dev
);
1501 struct phy_device
*tbiphy
;
1503 if (!priv
->tbi_node
) {
1504 dev_warn(&dev
->dev
, "error: SGMII mode requires that the "
1505 "device tree specify a tbi-handle\n");
1509 tbiphy
= of_phy_find_device(priv
->tbi_node
);
1511 dev_err(&dev
->dev
, "error: Could not get TBI device\n");
1515 /* If the link is already up, we must already be ok, and don't need to
1516 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1517 * everything for us? Resetting it takes the link down and requires
1518 * several seconds for it to come back.
1520 if (phy_read(tbiphy
, MII_BMSR
) & BMSR_LSTATUS
)
1523 /* Single clk mode, mii mode off(for serdes communication) */
1524 phy_write(tbiphy
, MII_TBICON
, TBICON_CLK_SELECT
);
1526 phy_write(tbiphy
, MII_ADVERTISE
,
1527 ADVERTISE_1000XFULL
| ADVERTISE_1000XPAUSE
|
1528 ADVERTISE_1000XPSE_ASYM
);
1530 phy_write(tbiphy
, MII_BMCR
,
1531 BMCR_ANENABLE
| BMCR_ANRESTART
| BMCR_FULLDPLX
|
1535 static void init_registers(struct net_device
*dev
)
1537 struct gfar_private
*priv
= netdev_priv(dev
);
1538 struct gfar __iomem
*regs
= NULL
;
1541 for (i
= 0; i
< priv
->num_grps
; i
++) {
1542 regs
= priv
->gfargrp
[i
].regs
;
1544 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
1546 /* Initialize IMASK */
1547 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
1550 regs
= priv
->gfargrp
[0].regs
;
1551 /* Init hash registers to zero */
1552 gfar_write(®s
->igaddr0
, 0);
1553 gfar_write(®s
->igaddr1
, 0);
1554 gfar_write(®s
->igaddr2
, 0);
1555 gfar_write(®s
->igaddr3
, 0);
1556 gfar_write(®s
->igaddr4
, 0);
1557 gfar_write(®s
->igaddr5
, 0);
1558 gfar_write(®s
->igaddr6
, 0);
1559 gfar_write(®s
->igaddr7
, 0);
1561 gfar_write(®s
->gaddr0
, 0);
1562 gfar_write(®s
->gaddr1
, 0);
1563 gfar_write(®s
->gaddr2
, 0);
1564 gfar_write(®s
->gaddr3
, 0);
1565 gfar_write(®s
->gaddr4
, 0);
1566 gfar_write(®s
->gaddr5
, 0);
1567 gfar_write(®s
->gaddr6
, 0);
1568 gfar_write(®s
->gaddr7
, 0);
1570 /* Zero out the rmon mib registers if it has them */
1571 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_RMON
) {
1572 memset_io(&(regs
->rmon
), 0, sizeof (struct rmon_mib
));
1574 /* Mask off the CAM interrupts */
1575 gfar_write(®s
->rmon
.cam1
, 0xffffffff);
1576 gfar_write(®s
->rmon
.cam2
, 0xffffffff);
1579 /* Initialize the max receive buffer length */
1580 gfar_write(®s
->mrblr
, priv
->rx_buffer_size
);
1582 /* Initialize the Minimum Frame Length Register */
1583 gfar_write(®s
->minflr
, MINFLR_INIT_SETTINGS
);
1586 static int __gfar_is_rx_idle(struct gfar_private
*priv
)
1590 /* Normaly TSEC should not hang on GRS commands, so we should
1591 * actually wait for IEVENT_GRSC flag.
1593 if (likely(!gfar_has_errata(priv
, GFAR_ERRATA_A002
)))
1596 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1597 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1598 * and the Rx can be safely reset.
1600 res
= gfar_read((void __iomem
*)priv
->gfargrp
[0].regs
+ 0xd1c);
1602 if ((res
& 0xffff) == (res
>> 16))
1608 /* Halt the receive and transmit queues */
1609 static void gfar_halt_nodisable(struct net_device
*dev
)
1611 struct gfar_private
*priv
= netdev_priv(dev
);
1612 struct gfar __iomem
*regs
= NULL
;
1616 for (i
= 0; i
< priv
->num_grps
; i
++) {
1617 regs
= priv
->gfargrp
[i
].regs
;
1618 /* Mask all interrupts */
1619 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
1621 /* Clear all interrupts */
1622 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
1625 regs
= priv
->gfargrp
[0].regs
;
1626 /* Stop the DMA, and wait for it to stop */
1627 tempval
= gfar_read(®s
->dmactrl
);
1628 if ((tempval
& (DMACTRL_GRS
| DMACTRL_GTS
)) !=
1629 (DMACTRL_GRS
| DMACTRL_GTS
)) {
1632 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
1633 gfar_write(®s
->dmactrl
, tempval
);
1636 ret
= spin_event_timeout(((gfar_read(®s
->ievent
) &
1637 (IEVENT_GRSC
| IEVENT_GTSC
)) ==
1638 (IEVENT_GRSC
| IEVENT_GTSC
)), 1000000, 0);
1639 if (!ret
&& !(gfar_read(®s
->ievent
) & IEVENT_GRSC
))
1640 ret
= __gfar_is_rx_idle(priv
);
1645 /* Halt the receive and transmit queues */
1646 void gfar_halt(struct net_device
*dev
)
1648 struct gfar_private
*priv
= netdev_priv(dev
);
1649 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1652 gfar_halt_nodisable(dev
);
1654 /* Disable Rx and Tx */
1655 tempval
= gfar_read(®s
->maccfg1
);
1656 tempval
&= ~(MACCFG1_RX_EN
| MACCFG1_TX_EN
);
1657 gfar_write(®s
->maccfg1
, tempval
);
1660 static void free_grp_irqs(struct gfar_priv_grp
*grp
)
1662 free_irq(gfar_irq(grp
, TX
)->irq
, grp
);
1663 free_irq(gfar_irq(grp
, RX
)->irq
, grp
);
1664 free_irq(gfar_irq(grp
, ER
)->irq
, grp
);
1667 void stop_gfar(struct net_device
*dev
)
1669 struct gfar_private
*priv
= netdev_priv(dev
);
1670 unsigned long flags
;
1673 phy_stop(priv
->phydev
);
1677 local_irq_save(flags
);
1685 local_irq_restore(flags
);
1688 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1689 for (i
= 0; i
< priv
->num_grps
; i
++)
1690 free_grp_irqs(&priv
->gfargrp
[i
]);
1692 for (i
= 0; i
< priv
->num_grps
; i
++)
1693 free_irq(gfar_irq(&priv
->gfargrp
[i
], TX
)->irq
,
1697 free_skb_resources(priv
);
1700 static void free_skb_tx_queue(struct gfar_priv_tx_q
*tx_queue
)
1702 struct txbd8
*txbdp
;
1703 struct gfar_private
*priv
= netdev_priv(tx_queue
->dev
);
1706 txbdp
= tx_queue
->tx_bd_base
;
1708 for (i
= 0; i
< tx_queue
->tx_ring_size
; i
++) {
1709 if (!tx_queue
->tx_skbuff
[i
])
1712 dma_unmap_single(priv
->dev
, txbdp
->bufPtr
,
1713 txbdp
->length
, DMA_TO_DEVICE
);
1715 for (j
= 0; j
< skb_shinfo(tx_queue
->tx_skbuff
[i
])->nr_frags
;
1718 dma_unmap_page(priv
->dev
, txbdp
->bufPtr
,
1719 txbdp
->length
, DMA_TO_DEVICE
);
1722 dev_kfree_skb_any(tx_queue
->tx_skbuff
[i
]);
1723 tx_queue
->tx_skbuff
[i
] = NULL
;
1725 kfree(tx_queue
->tx_skbuff
);
1726 tx_queue
->tx_skbuff
= NULL
;
1729 static void free_skb_rx_queue(struct gfar_priv_rx_q
*rx_queue
)
1731 struct rxbd8
*rxbdp
;
1732 struct gfar_private
*priv
= netdev_priv(rx_queue
->dev
);
1735 rxbdp
= rx_queue
->rx_bd_base
;
1737 for (i
= 0; i
< rx_queue
->rx_ring_size
; i
++) {
1738 if (rx_queue
->rx_skbuff
[i
]) {
1739 dma_unmap_single(priv
->dev
, rxbdp
->bufPtr
,
1740 priv
->rx_buffer_size
,
1742 dev_kfree_skb_any(rx_queue
->rx_skbuff
[i
]);
1743 rx_queue
->rx_skbuff
[i
] = NULL
;
1749 kfree(rx_queue
->rx_skbuff
);
1750 rx_queue
->rx_skbuff
= NULL
;
1753 /* If there are any tx skbs or rx skbs still around, free them.
1754 * Then free tx_skbuff and rx_skbuff
1756 static void free_skb_resources(struct gfar_private
*priv
)
1758 struct gfar_priv_tx_q
*tx_queue
= NULL
;
1759 struct gfar_priv_rx_q
*rx_queue
= NULL
;
1762 /* Go through all the buffer descriptors and free their data buffers */
1763 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
1764 struct netdev_queue
*txq
;
1766 tx_queue
= priv
->tx_queue
[i
];
1767 txq
= netdev_get_tx_queue(tx_queue
->dev
, tx_queue
->qindex
);
1768 if (tx_queue
->tx_skbuff
)
1769 free_skb_tx_queue(tx_queue
);
1770 netdev_tx_reset_queue(txq
);
1773 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
1774 rx_queue
= priv
->rx_queue
[i
];
1775 if (rx_queue
->rx_skbuff
)
1776 free_skb_rx_queue(rx_queue
);
1779 dma_free_coherent(priv
->dev
,
1780 sizeof(struct txbd8
) * priv
->total_tx_ring_size
+
1781 sizeof(struct rxbd8
) * priv
->total_rx_ring_size
,
1782 priv
->tx_queue
[0]->tx_bd_base
,
1783 priv
->tx_queue
[0]->tx_bd_dma_base
);
1786 void gfar_start(struct net_device
*dev
)
1788 struct gfar_private
*priv
= netdev_priv(dev
);
1789 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1793 /* Enable Rx and Tx in MACCFG1 */
1794 tempval
= gfar_read(®s
->maccfg1
);
1795 tempval
|= (MACCFG1_RX_EN
| MACCFG1_TX_EN
);
1796 gfar_write(®s
->maccfg1
, tempval
);
1798 /* Initialize DMACTRL to have WWR and WOP */
1799 tempval
= gfar_read(®s
->dmactrl
);
1800 tempval
|= DMACTRL_INIT_SETTINGS
;
1801 gfar_write(®s
->dmactrl
, tempval
);
1803 /* Make sure we aren't stopped */
1804 tempval
= gfar_read(®s
->dmactrl
);
1805 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
1806 gfar_write(®s
->dmactrl
, tempval
);
1808 for (i
= 0; i
< priv
->num_grps
; i
++) {
1809 regs
= priv
->gfargrp
[i
].regs
;
1810 /* Clear THLT/RHLT, so that the DMA starts polling now */
1811 gfar_write(®s
->tstat
, priv
->gfargrp
[i
].tstat
);
1812 gfar_write(®s
->rstat
, priv
->gfargrp
[i
].rstat
);
1813 /* Unmask the interrupts we look for */
1814 gfar_write(®s
->imask
, IMASK_DEFAULT
);
1817 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1820 static void gfar_configure_coalescing(struct gfar_private
*priv
,
1821 unsigned long tx_mask
, unsigned long rx_mask
)
1823 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1826 if (priv
->mode
== MQ_MG_MODE
) {
1829 baddr
= ®s
->txic0
;
1830 for_each_set_bit(i
, &tx_mask
, priv
->num_tx_queues
) {
1831 gfar_write(baddr
+ i
, 0);
1832 if (likely(priv
->tx_queue
[i
]->txcoalescing
))
1833 gfar_write(baddr
+ i
, priv
->tx_queue
[i
]->txic
);
1836 baddr
= ®s
->rxic0
;
1837 for_each_set_bit(i
, &rx_mask
, priv
->num_rx_queues
) {
1838 gfar_write(baddr
+ i
, 0);
1839 if (likely(priv
->rx_queue
[i
]->rxcoalescing
))
1840 gfar_write(baddr
+ i
, priv
->rx_queue
[i
]->rxic
);
1843 /* Backward compatible case -- even if we enable
1844 * multiple queues, there's only single reg to program
1846 gfar_write(®s
->txic
, 0);
1847 if (likely(priv
->tx_queue
[0]->txcoalescing
))
1848 gfar_write(®s
->txic
, priv
->tx_queue
[0]->txic
);
1850 gfar_write(®s
->rxic
, 0);
1851 if (unlikely(priv
->rx_queue
[0]->rxcoalescing
))
1852 gfar_write(®s
->rxic
, priv
->rx_queue
[0]->rxic
);
1856 void gfar_configure_coalescing_all(struct gfar_private
*priv
)
1858 gfar_configure_coalescing(priv
, 0xFF, 0xFF);
1861 static int register_grp_irqs(struct gfar_priv_grp
*grp
)
1863 struct gfar_private
*priv
= grp
->priv
;
1864 struct net_device
*dev
= priv
->ndev
;
1867 /* If the device has multiple interrupts, register for
1868 * them. Otherwise, only register for the one
1870 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1871 /* Install our interrupt handlers for Error,
1872 * Transmit, and Receive
1874 err
= request_irq(gfar_irq(grp
, ER
)->irq
, gfar_error
, 0,
1875 gfar_irq(grp
, ER
)->name
, grp
);
1877 netif_err(priv
, intr
, dev
, "Can't get IRQ %d\n",
1878 gfar_irq(grp
, ER
)->irq
);
1882 err
= request_irq(gfar_irq(grp
, TX
)->irq
, gfar_transmit
, 0,
1883 gfar_irq(grp
, TX
)->name
, grp
);
1885 netif_err(priv
, intr
, dev
, "Can't get IRQ %d\n",
1886 gfar_irq(grp
, TX
)->irq
);
1889 err
= request_irq(gfar_irq(grp
, RX
)->irq
, gfar_receive
, 0,
1890 gfar_irq(grp
, RX
)->name
, grp
);
1892 netif_err(priv
, intr
, dev
, "Can't get IRQ %d\n",
1893 gfar_irq(grp
, RX
)->irq
);
1897 err
= request_irq(gfar_irq(grp
, TX
)->irq
, gfar_interrupt
, 0,
1898 gfar_irq(grp
, TX
)->name
, grp
);
1900 netif_err(priv
, intr
, dev
, "Can't get IRQ %d\n",
1901 gfar_irq(grp
, TX
)->irq
);
1909 free_irq(gfar_irq(grp
, TX
)->irq
, grp
);
1911 free_irq(gfar_irq(grp
, ER
)->irq
, grp
);
1917 /* Bring the controller up and running */
1918 int startup_gfar(struct net_device
*ndev
)
1920 struct gfar_private
*priv
= netdev_priv(ndev
);
1921 struct gfar __iomem
*regs
= NULL
;
1924 for (i
= 0; i
< priv
->num_grps
; i
++) {
1925 regs
= priv
->gfargrp
[i
].regs
;
1926 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
1929 regs
= priv
->gfargrp
[0].regs
;
1930 err
= gfar_alloc_skb_resources(ndev
);
1934 gfar_init_mac(ndev
);
1936 for (i
= 0; i
< priv
->num_grps
; i
++) {
1937 err
= register_grp_irqs(&priv
->gfargrp
[i
]);
1939 for (j
= 0; j
< i
; j
++)
1940 free_grp_irqs(&priv
->gfargrp
[j
]);
1945 /* Start the controller */
1948 phy_start(priv
->phydev
);
1950 gfar_configure_coalescing_all(priv
);
1955 free_skb_resources(priv
);
1959 /* Called when something needs to use the ethernet device
1960 * Returns 0 for success.
1962 static int gfar_enet_open(struct net_device
*dev
)
1964 struct gfar_private
*priv
= netdev_priv(dev
);
1969 /* Initialize a bunch of registers */
1970 init_registers(dev
);
1972 gfar_set_mac_address(dev
);
1974 err
= init_phy(dev
);
1981 err
= startup_gfar(dev
);
1987 netif_tx_start_all_queues(dev
);
1989 device_set_wakeup_enable(&dev
->dev
, priv
->wol_en
);
1994 static inline struct txfcb
*gfar_add_fcb(struct sk_buff
*skb
)
1996 struct txfcb
*fcb
= (struct txfcb
*)skb_push(skb
, GMAC_FCB_LEN
);
1998 memset(fcb
, 0, GMAC_FCB_LEN
);
2003 static inline void gfar_tx_checksum(struct sk_buff
*skb
, struct txfcb
*fcb
,
2006 /* If we're here, it's a IP packet with a TCP or UDP
2007 * payload. We set it to checksum, using a pseudo-header
2010 u8 flags
= TXFCB_DEFAULT
;
2012 /* Tell the controller what the protocol is
2013 * And provide the already calculated phcs
2015 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
) {
2017 fcb
->phcs
= udp_hdr(skb
)->check
;
2019 fcb
->phcs
= tcp_hdr(skb
)->check
;
2021 /* l3os is the distance between the start of the
2022 * frame (skb->data) and the start of the IP hdr.
2023 * l4os is the distance between the start of the
2024 * l3 hdr and the l4 hdr
2026 fcb
->l3os
= (u16
)(skb_network_offset(skb
) - fcb_length
);
2027 fcb
->l4os
= skb_network_header_len(skb
);
2032 void inline gfar_tx_vlan(struct sk_buff
*skb
, struct txfcb
*fcb
)
2034 fcb
->flags
|= TXFCB_VLN
;
2035 fcb
->vlctl
= vlan_tx_tag_get(skb
);
2038 static inline struct txbd8
*skip_txbd(struct txbd8
*bdp
, int stride
,
2039 struct txbd8
*base
, int ring_size
)
2041 struct txbd8
*new_bd
= bdp
+ stride
;
2043 return (new_bd
>= (base
+ ring_size
)) ? (new_bd
- ring_size
) : new_bd
;
2046 static inline struct txbd8
*next_txbd(struct txbd8
*bdp
, struct txbd8
*base
,
2049 return skip_txbd(bdp
, 1, base
, ring_size
);
2052 /* This is called by the kernel when a frame is ready for transmission.
2053 * It is pointed to by the dev->hard_start_xmit function pointer
2055 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2057 struct gfar_private
*priv
= netdev_priv(dev
);
2058 struct gfar_priv_tx_q
*tx_queue
= NULL
;
2059 struct netdev_queue
*txq
;
2060 struct gfar __iomem
*regs
= NULL
;
2061 struct txfcb
*fcb
= NULL
;
2062 struct txbd8
*txbdp
, *txbdp_start
, *base
, *txbdp_tstamp
= NULL
;
2064 int i
, rq
= 0, do_tstamp
= 0;
2066 unsigned long flags
;
2067 unsigned int nr_frags
, nr_txbds
, length
, fcb_length
= GMAC_FCB_LEN
;
2069 /* TOE=1 frames larger than 2500 bytes may see excess delays
2070 * before start of transmission.
2072 if (unlikely(gfar_has_errata(priv
, GFAR_ERRATA_76
) &&
2073 skb
->ip_summed
== CHECKSUM_PARTIAL
&&
2077 ret
= skb_checksum_help(skb
);
2082 rq
= skb
->queue_mapping
;
2083 tx_queue
= priv
->tx_queue
[rq
];
2084 txq
= netdev_get_tx_queue(dev
, rq
);
2085 base
= tx_queue
->tx_bd_base
;
2086 regs
= tx_queue
->grp
->regs
;
2088 /* check if time stamp should be generated */
2089 if (unlikely(skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
&&
2090 priv
->hwts_tx_en
)) {
2092 fcb_length
= GMAC_FCB_LEN
+ GMAC_TXPAL_LEN
;
2095 /* make space for additional header when fcb is needed */
2096 if (((skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
2097 vlan_tx_tag_present(skb
) ||
2098 unlikely(do_tstamp
)) &&
2099 (skb_headroom(skb
) < fcb_length
)) {
2100 struct sk_buff
*skb_new
;
2102 skb_new
= skb_realloc_headroom(skb
, fcb_length
);
2104 dev
->stats
.tx_errors
++;
2106 return NETDEV_TX_OK
;
2110 skb_set_owner_w(skb_new
, skb
->sk
);
2115 /* total number of fragments in the SKB */
2116 nr_frags
= skb_shinfo(skb
)->nr_frags
;
2118 /* calculate the required number of TxBDs for this skb */
2119 if (unlikely(do_tstamp
))
2120 nr_txbds
= nr_frags
+ 2;
2122 nr_txbds
= nr_frags
+ 1;
2124 /* check if there is space to queue this packet */
2125 if (nr_txbds
> tx_queue
->num_txbdfree
) {
2126 /* no space, stop the queue */
2127 netif_tx_stop_queue(txq
);
2128 dev
->stats
.tx_fifo_errors
++;
2129 return NETDEV_TX_BUSY
;
2132 /* Update transmit stats */
2133 tx_queue
->stats
.tx_bytes
+= skb
->len
;
2134 tx_queue
->stats
.tx_packets
++;
2136 txbdp
= txbdp_start
= tx_queue
->cur_tx
;
2137 lstatus
= txbdp
->lstatus
;
2139 /* Time stamp insertion requires one additional TxBD */
2140 if (unlikely(do_tstamp
))
2141 txbdp_tstamp
= txbdp
= next_txbd(txbdp
, base
,
2142 tx_queue
->tx_ring_size
);
2144 if (nr_frags
== 0) {
2145 if (unlikely(do_tstamp
))
2146 txbdp_tstamp
->lstatus
|= BD_LFLAG(TXBD_LAST
|
2149 lstatus
|= BD_LFLAG(TXBD_LAST
| TXBD_INTERRUPT
);
2151 /* Place the fragment addresses and lengths into the TxBDs */
2152 for (i
= 0; i
< nr_frags
; i
++) {
2153 /* Point at the next BD, wrapping as needed */
2154 txbdp
= next_txbd(txbdp
, base
, tx_queue
->tx_ring_size
);
2156 length
= skb_shinfo(skb
)->frags
[i
].size
;
2158 lstatus
= txbdp
->lstatus
| length
|
2159 BD_LFLAG(TXBD_READY
);
2161 /* Handle the last BD specially */
2162 if (i
== nr_frags
- 1)
2163 lstatus
|= BD_LFLAG(TXBD_LAST
| TXBD_INTERRUPT
);
2165 bufaddr
= skb_frag_dma_map(priv
->dev
,
2166 &skb_shinfo(skb
)->frags
[i
],
2171 /* set the TxBD length and buffer pointer */
2172 txbdp
->bufPtr
= bufaddr
;
2173 txbdp
->lstatus
= lstatus
;
2176 lstatus
= txbdp_start
->lstatus
;
2179 /* Add TxPAL between FCB and frame if required */
2180 if (unlikely(do_tstamp
)) {
2181 skb_push(skb
, GMAC_TXPAL_LEN
);
2182 memset(skb
->data
, 0, GMAC_TXPAL_LEN
);
2185 /* Set up checksumming */
2186 if (CHECKSUM_PARTIAL
== skb
->ip_summed
) {
2187 fcb
= gfar_add_fcb(skb
);
2188 /* as specified by errata */
2189 if (unlikely(gfar_has_errata(priv
, GFAR_ERRATA_12
) &&
2190 ((unsigned long)fcb
% 0x20) > 0x18)) {
2191 __skb_pull(skb
, GMAC_FCB_LEN
);
2192 skb_checksum_help(skb
);
2194 lstatus
|= BD_LFLAG(TXBD_TOE
);
2195 gfar_tx_checksum(skb
, fcb
, fcb_length
);
2199 if (vlan_tx_tag_present(skb
)) {
2200 if (unlikely(NULL
== fcb
)) {
2201 fcb
= gfar_add_fcb(skb
);
2202 lstatus
|= BD_LFLAG(TXBD_TOE
);
2205 gfar_tx_vlan(skb
, fcb
);
2208 /* Setup tx hardware time stamping if requested */
2209 if (unlikely(do_tstamp
)) {
2210 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
2212 fcb
= gfar_add_fcb(skb
);
2214 lstatus
|= BD_LFLAG(TXBD_TOE
);
2217 txbdp_start
->bufPtr
= dma_map_single(priv
->dev
, skb
->data
,
2218 skb_headlen(skb
), DMA_TO_DEVICE
);
2220 /* If time stamping is requested one additional TxBD must be set up. The
2221 * first TxBD points to the FCB and must have a data length of
2222 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2223 * the full frame length.
2225 if (unlikely(do_tstamp
)) {
2226 txbdp_tstamp
->bufPtr
= txbdp_start
->bufPtr
+ fcb_length
;
2227 txbdp_tstamp
->lstatus
|= BD_LFLAG(TXBD_READY
) |
2228 (skb_headlen(skb
) - fcb_length
);
2229 lstatus
|= BD_LFLAG(TXBD_CRC
| TXBD_READY
) | GMAC_FCB_LEN
;
2231 lstatus
|= BD_LFLAG(TXBD_CRC
| TXBD_READY
) | skb_headlen(skb
);
2234 netdev_tx_sent_queue(txq
, skb
->len
);
2236 /* We can work in parallel with gfar_clean_tx_ring(), except
2237 * when modifying num_txbdfree. Note that we didn't grab the lock
2238 * when we were reading the num_txbdfree and checking for available
2239 * space, that's because outside of this function it can only grow,
2240 * and once we've got needed space, it cannot suddenly disappear.
2242 * The lock also protects us from gfar_error(), which can modify
2243 * regs->tstat and thus retrigger the transfers, which is why we
2244 * also must grab the lock before setting ready bit for the first
2245 * to be transmitted BD.
2247 spin_lock_irqsave(&tx_queue
->txlock
, flags
);
2249 /* The powerpc-specific eieio() is used, as wmb() has too strong
2250 * semantics (it requires synchronization between cacheable and
2251 * uncacheable mappings, which eieio doesn't provide and which we
2252 * don't need), thus requiring a more expensive sync instruction. At
2253 * some point, the set of architecture-independent barrier functions
2254 * should be expanded to include weaker barriers.
2258 txbdp_start
->lstatus
= lstatus
;
2260 eieio(); /* force lstatus write before tx_skbuff */
2262 tx_queue
->tx_skbuff
[tx_queue
->skb_curtx
] = skb
;
2264 /* Update the current skb pointer to the next entry we will use
2265 * (wrapping if necessary)
2267 tx_queue
->skb_curtx
= (tx_queue
->skb_curtx
+ 1) &
2268 TX_RING_MOD_MASK(tx_queue
->tx_ring_size
);
2270 tx_queue
->cur_tx
= next_txbd(txbdp
, base
, tx_queue
->tx_ring_size
);
2272 /* reduce TxBD free count */
2273 tx_queue
->num_txbdfree
-= (nr_txbds
);
2275 /* If the next BD still needs to be cleaned up, then the bds
2276 * are full. We need to tell the kernel to stop sending us stuff.
2278 if (!tx_queue
->num_txbdfree
) {
2279 netif_tx_stop_queue(txq
);
2281 dev
->stats
.tx_fifo_errors
++;
2284 /* Tell the DMA to go go go */
2285 gfar_write(®s
->tstat
, TSTAT_CLEAR_THALT
>> tx_queue
->qindex
);
2288 spin_unlock_irqrestore(&tx_queue
->txlock
, flags
);
2290 return NETDEV_TX_OK
;
2293 /* Stops the kernel queue, and halts the controller */
2294 static int gfar_close(struct net_device
*dev
)
2296 struct gfar_private
*priv
= netdev_priv(dev
);
2300 cancel_work_sync(&priv
->reset_task
);
2303 /* Disconnect from the PHY */
2304 phy_disconnect(priv
->phydev
);
2305 priv
->phydev
= NULL
;
2307 netif_tx_stop_all_queues(dev
);
2312 /* Changes the mac address if the controller is not running. */
2313 static int gfar_set_mac_address(struct net_device
*dev
)
2315 gfar_set_mac_for_addr(dev
, 0, dev
->dev_addr
);
2320 /* Check if rx parser should be activated */
2321 void gfar_check_rx_parser_mode(struct gfar_private
*priv
)
2323 struct gfar __iomem
*regs
;
2326 regs
= priv
->gfargrp
[0].regs
;
2328 tempval
= gfar_read(®s
->rctrl
);
2329 /* If parse is no longer required, then disable parser */
2330 if (tempval
& RCTRL_REQ_PARSER
) {
2331 tempval
|= RCTRL_PRSDEP_INIT
;
2332 priv
->uses_rxfcb
= 1;
2334 tempval
&= ~RCTRL_PRSDEP_INIT
;
2335 priv
->uses_rxfcb
= 0;
2337 gfar_write(®s
->rctrl
, tempval
);
2340 /* Enables and disables VLAN insertion/extraction */
2341 void gfar_vlan_mode(struct net_device
*dev
, netdev_features_t features
)
2343 struct gfar_private
*priv
= netdev_priv(dev
);
2344 struct gfar __iomem
*regs
= NULL
;
2345 unsigned long flags
;
2348 regs
= priv
->gfargrp
[0].regs
;
2349 local_irq_save(flags
);
2352 if (features
& NETIF_F_HW_VLAN_CTAG_TX
) {
2353 /* Enable VLAN tag insertion */
2354 tempval
= gfar_read(®s
->tctrl
);
2355 tempval
|= TCTRL_VLINS
;
2356 gfar_write(®s
->tctrl
, tempval
);
2358 /* Disable VLAN tag insertion */
2359 tempval
= gfar_read(®s
->tctrl
);
2360 tempval
&= ~TCTRL_VLINS
;
2361 gfar_write(®s
->tctrl
, tempval
);
2364 if (features
& NETIF_F_HW_VLAN_CTAG_RX
) {
2365 /* Enable VLAN tag extraction */
2366 tempval
= gfar_read(®s
->rctrl
);
2367 tempval
|= (RCTRL_VLEX
| RCTRL_PRSDEP_INIT
);
2368 gfar_write(®s
->rctrl
, tempval
);
2369 priv
->uses_rxfcb
= 1;
2371 /* Disable VLAN tag extraction */
2372 tempval
= gfar_read(®s
->rctrl
);
2373 tempval
&= ~RCTRL_VLEX
;
2374 gfar_write(®s
->rctrl
, tempval
);
2376 gfar_check_rx_parser_mode(priv
);
2379 gfar_change_mtu(dev
, dev
->mtu
);
2382 local_irq_restore(flags
);
2385 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
)
2387 int tempsize
, tempval
;
2388 struct gfar_private
*priv
= netdev_priv(dev
);
2389 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
2390 int oldsize
= priv
->rx_buffer_size
;
2391 int frame_size
= new_mtu
+ ETH_HLEN
;
2393 if ((frame_size
< 64) || (frame_size
> JUMBO_FRAME_SIZE
)) {
2394 netif_err(priv
, drv
, dev
, "Invalid MTU setting\n");
2398 if (priv
->uses_rxfcb
)
2399 frame_size
+= GMAC_FCB_LEN
;
2401 frame_size
+= priv
->padding
;
2403 tempsize
= (frame_size
& ~(INCREMENTAL_BUFFER_SIZE
- 1)) +
2404 INCREMENTAL_BUFFER_SIZE
;
2406 /* Only stop and start the controller if it isn't already
2407 * stopped, and we changed something
2409 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
2412 priv
->rx_buffer_size
= tempsize
;
2416 gfar_write(®s
->mrblr
, priv
->rx_buffer_size
);
2417 gfar_write(®s
->maxfrm
, priv
->rx_buffer_size
);
2419 /* If the mtu is larger than the max size for standard
2420 * ethernet frames (ie, a jumbo frame), then set maccfg2
2421 * to allow huge frames, and to check the length
2423 tempval
= gfar_read(®s
->maccfg2
);
2425 if (priv
->rx_buffer_size
> DEFAULT_RX_BUFFER_SIZE
||
2426 gfar_has_errata(priv
, GFAR_ERRATA_74
))
2427 tempval
|= (MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
2429 tempval
&= ~(MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
2431 gfar_write(®s
->maccfg2
, tempval
);
2433 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
2439 /* gfar_reset_task gets scheduled when a packet has not been
2440 * transmitted after a set amount of time.
2441 * For now, assume that clearing out all the structures, and
2442 * starting over will fix the problem.
2444 static void gfar_reset_task(struct work_struct
*work
)
2446 struct gfar_private
*priv
= container_of(work
, struct gfar_private
,
2448 struct net_device
*dev
= priv
->ndev
;
2450 if (dev
->flags
& IFF_UP
) {
2451 netif_tx_stop_all_queues(dev
);
2454 netif_tx_start_all_queues(dev
);
2457 netif_tx_schedule_all(dev
);
2460 static void gfar_timeout(struct net_device
*dev
)
2462 struct gfar_private
*priv
= netdev_priv(dev
);
2464 dev
->stats
.tx_errors
++;
2465 schedule_work(&priv
->reset_task
);
2468 static void gfar_align_skb(struct sk_buff
*skb
)
2470 /* We need the data buffer to be aligned properly. We will reserve
2471 * as many bytes as needed to align the data properly
2473 skb_reserve(skb
, RXBUF_ALIGNMENT
-
2474 (((unsigned long) skb
->data
) & (RXBUF_ALIGNMENT
- 1)));
2477 /* Interrupt Handler for Transmit complete */
2478 static void gfar_clean_tx_ring(struct gfar_priv_tx_q
*tx_queue
)
2480 struct net_device
*dev
= tx_queue
->dev
;
2481 struct netdev_queue
*txq
;
2482 struct gfar_private
*priv
= netdev_priv(dev
);
2483 struct txbd8
*bdp
, *next
= NULL
;
2484 struct txbd8
*lbdp
= NULL
;
2485 struct txbd8
*base
= tx_queue
->tx_bd_base
;
2486 struct sk_buff
*skb
;
2488 int tx_ring_size
= tx_queue
->tx_ring_size
;
2489 int frags
= 0, nr_txbds
= 0;
2492 int tqi
= tx_queue
->qindex
;
2493 unsigned int bytes_sent
= 0;
2497 txq
= netdev_get_tx_queue(dev
, tqi
);
2498 bdp
= tx_queue
->dirty_tx
;
2499 skb_dirtytx
= tx_queue
->skb_dirtytx
;
2501 while ((skb
= tx_queue
->tx_skbuff
[skb_dirtytx
])) {
2502 unsigned long flags
;
2504 frags
= skb_shinfo(skb
)->nr_frags
;
2506 /* When time stamping, one additional TxBD must be freed.
2507 * Also, we need to dma_unmap_single() the TxPAL.
2509 if (unlikely(skb_shinfo(skb
)->tx_flags
& SKBTX_IN_PROGRESS
))
2510 nr_txbds
= frags
+ 2;
2512 nr_txbds
= frags
+ 1;
2514 lbdp
= skip_txbd(bdp
, nr_txbds
- 1, base
, tx_ring_size
);
2516 lstatus
= lbdp
->lstatus
;
2518 /* Only clean completed frames */
2519 if ((lstatus
& BD_LFLAG(TXBD_READY
)) &&
2520 (lstatus
& BD_LENGTH_MASK
))
2523 if (unlikely(skb_shinfo(skb
)->tx_flags
& SKBTX_IN_PROGRESS
)) {
2524 next
= next_txbd(bdp
, base
, tx_ring_size
);
2525 buflen
= next
->length
+ GMAC_FCB_LEN
+ GMAC_TXPAL_LEN
;
2527 buflen
= bdp
->length
;
2529 dma_unmap_single(priv
->dev
, bdp
->bufPtr
,
2530 buflen
, DMA_TO_DEVICE
);
2532 if (unlikely(skb_shinfo(skb
)->tx_flags
& SKBTX_IN_PROGRESS
)) {
2533 struct skb_shared_hwtstamps shhwtstamps
;
2534 u64
*ns
= (u64
*) (((u32
)skb
->data
+ 0x10) & ~0x7);
2536 memset(&shhwtstamps
, 0, sizeof(shhwtstamps
));
2537 shhwtstamps
.hwtstamp
= ns_to_ktime(*ns
);
2538 skb_pull(skb
, GMAC_FCB_LEN
+ GMAC_TXPAL_LEN
);
2539 skb_tstamp_tx(skb
, &shhwtstamps
);
2540 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
2544 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
2545 bdp
= next_txbd(bdp
, base
, tx_ring_size
);
2547 for (i
= 0; i
< frags
; i
++) {
2548 dma_unmap_page(priv
->dev
, bdp
->bufPtr
,
2549 bdp
->length
, DMA_TO_DEVICE
);
2550 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
2551 bdp
= next_txbd(bdp
, base
, tx_ring_size
);
2554 bytes_sent
+= skb
->len
;
2556 dev_kfree_skb_any(skb
);
2558 tx_queue
->tx_skbuff
[skb_dirtytx
] = NULL
;
2560 skb_dirtytx
= (skb_dirtytx
+ 1) &
2561 TX_RING_MOD_MASK(tx_ring_size
);
2564 spin_lock_irqsave(&tx_queue
->txlock
, flags
);
2565 tx_queue
->num_txbdfree
+= nr_txbds
;
2566 spin_unlock_irqrestore(&tx_queue
->txlock
, flags
);
2569 /* If we freed a buffer, we can restart transmission, if necessary */
2570 if (netif_tx_queue_stopped(txq
) && tx_queue
->num_txbdfree
)
2571 netif_wake_subqueue(dev
, tqi
);
2573 /* Update dirty indicators */
2574 tx_queue
->skb_dirtytx
= skb_dirtytx
;
2575 tx_queue
->dirty_tx
= bdp
;
2577 netdev_tx_completed_queue(txq
, howmany
, bytes_sent
);
2580 static void gfar_schedule_cleanup(struct gfar_priv_grp
*gfargrp
)
2582 unsigned long flags
;
2584 spin_lock_irqsave(&gfargrp
->grplock
, flags
);
2585 if (napi_schedule_prep(&gfargrp
->napi
)) {
2586 gfar_write(&gfargrp
->regs
->imask
, IMASK_RTX_DISABLED
);
2587 __napi_schedule(&gfargrp
->napi
);
2589 /* Clear IEVENT, so interrupts aren't called again
2590 * because of the packets that have already arrived.
2592 gfar_write(&gfargrp
->regs
->ievent
, IEVENT_RTX_MASK
);
2594 spin_unlock_irqrestore(&gfargrp
->grplock
, flags
);
2598 /* Interrupt Handler for Transmit complete */
2599 static irqreturn_t
gfar_transmit(int irq
, void *grp_id
)
2601 gfar_schedule_cleanup((struct gfar_priv_grp
*)grp_id
);
2605 static void gfar_new_rxbdp(struct gfar_priv_rx_q
*rx_queue
, struct rxbd8
*bdp
,
2606 struct sk_buff
*skb
)
2608 struct net_device
*dev
= rx_queue
->dev
;
2609 struct gfar_private
*priv
= netdev_priv(dev
);
2612 buf
= dma_map_single(priv
->dev
, skb
->data
,
2613 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
2614 gfar_init_rxbdp(rx_queue
, bdp
, buf
);
2617 static struct sk_buff
*gfar_alloc_skb(struct net_device
*dev
)
2619 struct gfar_private
*priv
= netdev_priv(dev
);
2620 struct sk_buff
*skb
;
2622 skb
= netdev_alloc_skb(dev
, priv
->rx_buffer_size
+ RXBUF_ALIGNMENT
);
2626 gfar_align_skb(skb
);
2631 struct sk_buff
*gfar_new_skb(struct net_device
*dev
)
2633 return gfar_alloc_skb(dev
);
2636 static inline void count_errors(unsigned short status
, struct net_device
*dev
)
2638 struct gfar_private
*priv
= netdev_priv(dev
);
2639 struct net_device_stats
*stats
= &dev
->stats
;
2640 struct gfar_extra_stats
*estats
= &priv
->extra_stats
;
2642 /* If the packet was truncated, none of the other errors matter */
2643 if (status
& RXBD_TRUNCATED
) {
2644 stats
->rx_length_errors
++;
2646 atomic64_inc(&estats
->rx_trunc
);
2650 /* Count the errors, if there were any */
2651 if (status
& (RXBD_LARGE
| RXBD_SHORT
)) {
2652 stats
->rx_length_errors
++;
2654 if (status
& RXBD_LARGE
)
2655 atomic64_inc(&estats
->rx_large
);
2657 atomic64_inc(&estats
->rx_short
);
2659 if (status
& RXBD_NONOCTET
) {
2660 stats
->rx_frame_errors
++;
2661 atomic64_inc(&estats
->rx_nonoctet
);
2663 if (status
& RXBD_CRCERR
) {
2664 atomic64_inc(&estats
->rx_crcerr
);
2665 stats
->rx_crc_errors
++;
2667 if (status
& RXBD_OVERRUN
) {
2668 atomic64_inc(&estats
->rx_overrun
);
2669 stats
->rx_crc_errors
++;
2673 irqreturn_t
gfar_receive(int irq
, void *grp_id
)
2675 gfar_schedule_cleanup((struct gfar_priv_grp
*)grp_id
);
2679 static inline void gfar_rx_checksum(struct sk_buff
*skb
, struct rxfcb
*fcb
)
2681 /* If valid headers were found, and valid sums
2682 * were verified, then we tell the kernel that no
2683 * checksumming is necessary. Otherwise, it is [FIXME]
2685 if ((fcb
->flags
& RXFCB_CSUM_MASK
) == (RXFCB_CIP
| RXFCB_CTU
))
2686 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2688 skb_checksum_none_assert(skb
);
2692 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2693 static void gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
2694 int amount_pull
, struct napi_struct
*napi
)
2696 struct gfar_private
*priv
= netdev_priv(dev
);
2697 struct rxfcb
*fcb
= NULL
;
2699 /* fcb is at the beginning if exists */
2700 fcb
= (struct rxfcb
*)skb
->data
;
2702 /* Remove the FCB from the skb
2703 * Remove the padded bytes, if there are any
2706 skb_record_rx_queue(skb
, fcb
->rq
);
2707 skb_pull(skb
, amount_pull
);
2710 /* Get receive timestamp from the skb */
2711 if (priv
->hwts_rx_en
) {
2712 struct skb_shared_hwtstamps
*shhwtstamps
= skb_hwtstamps(skb
);
2713 u64
*ns
= (u64
*) skb
->data
;
2715 memset(shhwtstamps
, 0, sizeof(*shhwtstamps
));
2716 shhwtstamps
->hwtstamp
= ns_to_ktime(*ns
);
2720 skb_pull(skb
, priv
->padding
);
2722 if (dev
->features
& NETIF_F_RXCSUM
)
2723 gfar_rx_checksum(skb
, fcb
);
2725 /* Tell the skb what kind of packet this is */
2726 skb
->protocol
= eth_type_trans(skb
, dev
);
2728 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2729 * Even if vlan rx accel is disabled, on some chips
2730 * RXFCB_VLN is pseudo randomly set.
2732 if (dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
&&
2733 fcb
->flags
& RXFCB_VLN
)
2734 __vlan_hwaccel_put_tag(skb
, fcb
->vlctl
);
2736 /* Send the packet up the stack */
2737 napi_gro_receive(napi
, skb
);
2741 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2742 * until the budget/quota has been reached. Returns the number
2745 int gfar_clean_rx_ring(struct gfar_priv_rx_q
*rx_queue
, int rx_work_limit
)
2747 struct net_device
*dev
= rx_queue
->dev
;
2748 struct rxbd8
*bdp
, *base
;
2749 struct sk_buff
*skb
;
2753 struct gfar_private
*priv
= netdev_priv(dev
);
2755 /* Get the first full descriptor */
2756 bdp
= rx_queue
->cur_rx
;
2757 base
= rx_queue
->rx_bd_base
;
2759 amount_pull
= priv
->uses_rxfcb
? GMAC_FCB_LEN
: 0;
2761 while (!((bdp
->status
& RXBD_EMPTY
) || (--rx_work_limit
< 0))) {
2762 struct sk_buff
*newskb
;
2766 /* Add another skb for the future */
2767 newskb
= gfar_new_skb(dev
);
2769 skb
= rx_queue
->rx_skbuff
[rx_queue
->skb_currx
];
2771 dma_unmap_single(priv
->dev
, bdp
->bufPtr
,
2772 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
2774 if (unlikely(!(bdp
->status
& RXBD_ERR
) &&
2775 bdp
->length
> priv
->rx_buffer_size
))
2776 bdp
->status
= RXBD_LARGE
;
2778 /* We drop the frame if we failed to allocate a new buffer */
2779 if (unlikely(!newskb
|| !(bdp
->status
& RXBD_LAST
) ||
2780 bdp
->status
& RXBD_ERR
)) {
2781 count_errors(bdp
->status
, dev
);
2783 if (unlikely(!newskb
))
2788 /* Increment the number of packets */
2789 rx_queue
->stats
.rx_packets
++;
2793 pkt_len
= bdp
->length
- ETH_FCS_LEN
;
2794 /* Remove the FCS from the packet length */
2795 skb_put(skb
, pkt_len
);
2796 rx_queue
->stats
.rx_bytes
+= pkt_len
;
2797 skb_record_rx_queue(skb
, rx_queue
->qindex
);
2798 gfar_process_frame(dev
, skb
, amount_pull
,
2799 &rx_queue
->grp
->napi
);
2802 netif_warn(priv
, rx_err
, dev
, "Missing skb!\n");
2803 rx_queue
->stats
.rx_dropped
++;
2804 atomic64_inc(&priv
->extra_stats
.rx_skbmissing
);
2809 rx_queue
->rx_skbuff
[rx_queue
->skb_currx
] = newskb
;
2811 /* Setup the new bdp */
2812 gfar_new_rxbdp(rx_queue
, bdp
, newskb
);
2814 /* Update to the next pointer */
2815 bdp
= next_bd(bdp
, base
, rx_queue
->rx_ring_size
);
2817 /* update to point at the next skb */
2818 rx_queue
->skb_currx
= (rx_queue
->skb_currx
+ 1) &
2819 RX_RING_MOD_MASK(rx_queue
->rx_ring_size
);
2822 /* Update the current rxbd pointer to be the next one */
2823 rx_queue
->cur_rx
= bdp
;
2828 static int gfar_poll(struct napi_struct
*napi
, int budget
)
2830 struct gfar_priv_grp
*gfargrp
=
2831 container_of(napi
, struct gfar_priv_grp
, napi
);
2832 struct gfar_private
*priv
= gfargrp
->priv
;
2833 struct gfar __iomem
*regs
= gfargrp
->regs
;
2834 struct gfar_priv_tx_q
*tx_queue
= NULL
;
2835 struct gfar_priv_rx_q
*rx_queue
= NULL
;
2836 int work_done
= 0, work_done_per_q
= 0;
2837 int i
, budget_per_q
= 0;
2839 unsigned long rstat_rxf
;
2842 /* Clear IEVENT, so interrupts aren't called again
2843 * because of the packets that have already arrived
2845 gfar_write(®s
->ievent
, IEVENT_RTX_MASK
);
2847 rstat_rxf
= gfar_read(®s
->rstat
) & RSTAT_RXF_MASK
;
2849 num_act_queues
= bitmap_weight(&rstat_rxf
, MAX_RX_QS
);
2851 budget_per_q
= budget
/num_act_queues
;
2855 for_each_set_bit(i
, &gfargrp
->tx_bit_map
, priv
->num_tx_queues
) {
2856 tx_queue
= priv
->tx_queue
[i
];
2857 /* run Tx cleanup to completion */
2858 if (tx_queue
->tx_skbuff
[tx_queue
->skb_dirtytx
]) {
2859 gfar_clean_tx_ring(tx_queue
);
2864 for_each_set_bit(i
, &gfargrp
->rx_bit_map
, priv
->num_rx_queues
) {
2865 /* skip queue if not active */
2866 if (!(rstat_rxf
& (RSTAT_CLEAR_RXF0
>> i
)))
2869 rx_queue
= priv
->rx_queue
[i
];
2871 gfar_clean_rx_ring(rx_queue
, budget_per_q
);
2872 work_done
+= work_done_per_q
;
2874 /* finished processing this queue */
2875 if (work_done_per_q
< budget_per_q
) {
2876 /* clear active queue hw indication */
2877 gfar_write(®s
->rstat
,
2878 RSTAT_CLEAR_RXF0
>> i
);
2879 rstat_rxf
&= ~(RSTAT_CLEAR_RXF0
>> i
);
2882 if (!num_act_queues
)
2884 /* recompute budget per Rx queue */
2886 (budget
- work_done
) / num_act_queues
;
2890 if (work_done
>= budget
)
2893 if (!num_act_queues
&& !has_tx_work
) {
2895 napi_complete(napi
);
2897 /* Clear the halt bit in RSTAT */
2898 gfar_write(®s
->rstat
, gfargrp
->rstat
);
2900 gfar_write(®s
->imask
, IMASK_DEFAULT
);
2902 /* If we are coalescing interrupts, update the timer
2903 * Otherwise, clear it
2905 gfar_configure_coalescing(priv
, gfargrp
->rx_bit_map
,
2906 gfargrp
->tx_bit_map
);
2914 #ifdef CONFIG_NET_POLL_CONTROLLER
2915 /* Polling 'interrupt' - used by things like netconsole to send skbs
2916 * without having to re-enable interrupts. It's not called while
2917 * the interrupt routine is executing.
2919 static void gfar_netpoll(struct net_device
*dev
)
2921 struct gfar_private
*priv
= netdev_priv(dev
);
2924 /* If the device has multiple interrupts, run tx/rx */
2925 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
2926 for (i
= 0; i
< priv
->num_grps
; i
++) {
2927 struct gfar_priv_grp
*grp
= &priv
->gfargrp
[i
];
2929 disable_irq(gfar_irq(grp
, TX
)->irq
);
2930 disable_irq(gfar_irq(grp
, RX
)->irq
);
2931 disable_irq(gfar_irq(grp
, ER
)->irq
);
2932 gfar_interrupt(gfar_irq(grp
, TX
)->irq
, grp
);
2933 enable_irq(gfar_irq(grp
, ER
)->irq
);
2934 enable_irq(gfar_irq(grp
, RX
)->irq
);
2935 enable_irq(gfar_irq(grp
, TX
)->irq
);
2938 for (i
= 0; i
< priv
->num_grps
; i
++) {
2939 struct gfar_priv_grp
*grp
= &priv
->gfargrp
[i
];
2941 disable_irq(gfar_irq(grp
, TX
)->irq
);
2942 gfar_interrupt(gfar_irq(grp
, TX
)->irq
, grp
);
2943 enable_irq(gfar_irq(grp
, TX
)->irq
);
2949 /* The interrupt handler for devices with one interrupt */
2950 static irqreturn_t
gfar_interrupt(int irq
, void *grp_id
)
2952 struct gfar_priv_grp
*gfargrp
= grp_id
;
2954 /* Save ievent for future reference */
2955 u32 events
= gfar_read(&gfargrp
->regs
->ievent
);
2957 /* Check for reception */
2958 if (events
& IEVENT_RX_MASK
)
2959 gfar_receive(irq
, grp_id
);
2961 /* Check for transmit completion */
2962 if (events
& IEVENT_TX_MASK
)
2963 gfar_transmit(irq
, grp_id
);
2965 /* Check for errors */
2966 if (events
& IEVENT_ERR_MASK
)
2967 gfar_error(irq
, grp_id
);
2972 /* Called every time the controller might need to be made
2973 * aware of new link state. The PHY code conveys this
2974 * information through variables in the phydev structure, and this
2975 * function converts those variables into the appropriate
2976 * register values, and can bring down the device if needed.
2978 static void adjust_link(struct net_device
*dev
)
2980 struct gfar_private
*priv
= netdev_priv(dev
);
2981 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
2982 unsigned long flags
;
2983 struct phy_device
*phydev
= priv
->phydev
;
2986 local_irq_save(flags
);
2990 u32 tempval
= gfar_read(®s
->maccfg2
);
2991 u32 ecntrl
= gfar_read(®s
->ecntrl
);
2993 /* Now we make sure that we can be in full duplex mode.
2994 * If not, we operate in half-duplex mode.
2996 if (phydev
->duplex
!= priv
->oldduplex
) {
2998 if (!(phydev
->duplex
))
2999 tempval
&= ~(MACCFG2_FULL_DUPLEX
);
3001 tempval
|= MACCFG2_FULL_DUPLEX
;
3003 priv
->oldduplex
= phydev
->duplex
;
3006 if (phydev
->speed
!= priv
->oldspeed
) {
3008 switch (phydev
->speed
) {
3011 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_GMII
);
3013 ecntrl
&= ~(ECNTRL_R100
);
3018 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_MII
);
3020 /* Reduced mode distinguishes
3021 * between 10 and 100
3023 if (phydev
->speed
== SPEED_100
)
3024 ecntrl
|= ECNTRL_R100
;
3026 ecntrl
&= ~(ECNTRL_R100
);
3029 netif_warn(priv
, link
, dev
,
3030 "Ack! Speed (%d) is not 10/100/1000!\n",
3035 priv
->oldspeed
= phydev
->speed
;
3038 gfar_write(®s
->maccfg2
, tempval
);
3039 gfar_write(®s
->ecntrl
, ecntrl
);
3041 if (!priv
->oldlink
) {
3045 } else if (priv
->oldlink
) {
3049 priv
->oldduplex
= -1;
3052 if (new_state
&& netif_msg_link(priv
))
3053 phy_print_status(phydev
);
3055 local_irq_restore(flags
);
3058 /* Update the hash table based on the current list of multicast
3059 * addresses we subscribe to. Also, change the promiscuity of
3060 * the device based on the flags (this function is called
3061 * whenever dev->flags is changed
3063 static void gfar_set_multi(struct net_device
*dev
)
3065 struct netdev_hw_addr
*ha
;
3066 struct gfar_private
*priv
= netdev_priv(dev
);
3067 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
3070 if (dev
->flags
& IFF_PROMISC
) {
3071 /* Set RCTRL to PROM */
3072 tempval
= gfar_read(®s
->rctrl
);
3073 tempval
|= RCTRL_PROM
;
3074 gfar_write(®s
->rctrl
, tempval
);
3076 /* Set RCTRL to not PROM */
3077 tempval
= gfar_read(®s
->rctrl
);
3078 tempval
&= ~(RCTRL_PROM
);
3079 gfar_write(®s
->rctrl
, tempval
);
3082 if (dev
->flags
& IFF_ALLMULTI
) {
3083 /* Set the hash to rx all multicast frames */
3084 gfar_write(®s
->igaddr0
, 0xffffffff);
3085 gfar_write(®s
->igaddr1
, 0xffffffff);
3086 gfar_write(®s
->igaddr2
, 0xffffffff);
3087 gfar_write(®s
->igaddr3
, 0xffffffff);
3088 gfar_write(®s
->igaddr4
, 0xffffffff);
3089 gfar_write(®s
->igaddr5
, 0xffffffff);
3090 gfar_write(®s
->igaddr6
, 0xffffffff);
3091 gfar_write(®s
->igaddr7
, 0xffffffff);
3092 gfar_write(®s
->gaddr0
, 0xffffffff);
3093 gfar_write(®s
->gaddr1
, 0xffffffff);
3094 gfar_write(®s
->gaddr2
, 0xffffffff);
3095 gfar_write(®s
->gaddr3
, 0xffffffff);
3096 gfar_write(®s
->gaddr4
, 0xffffffff);
3097 gfar_write(®s
->gaddr5
, 0xffffffff);
3098 gfar_write(®s
->gaddr6
, 0xffffffff);
3099 gfar_write(®s
->gaddr7
, 0xffffffff);
3104 /* zero out the hash */
3105 gfar_write(®s
->igaddr0
, 0x0);
3106 gfar_write(®s
->igaddr1
, 0x0);
3107 gfar_write(®s
->igaddr2
, 0x0);
3108 gfar_write(®s
->igaddr3
, 0x0);
3109 gfar_write(®s
->igaddr4
, 0x0);
3110 gfar_write(®s
->igaddr5
, 0x0);
3111 gfar_write(®s
->igaddr6
, 0x0);
3112 gfar_write(®s
->igaddr7
, 0x0);
3113 gfar_write(®s
->gaddr0
, 0x0);
3114 gfar_write(®s
->gaddr1
, 0x0);
3115 gfar_write(®s
->gaddr2
, 0x0);
3116 gfar_write(®s
->gaddr3
, 0x0);
3117 gfar_write(®s
->gaddr4
, 0x0);
3118 gfar_write(®s
->gaddr5
, 0x0);
3119 gfar_write(®s
->gaddr6
, 0x0);
3120 gfar_write(®s
->gaddr7
, 0x0);
3122 /* If we have extended hash tables, we need to
3123 * clear the exact match registers to prepare for
3126 if (priv
->extended_hash
) {
3127 em_num
= GFAR_EM_NUM
+ 1;
3128 gfar_clear_exact_match(dev
);
3135 if (netdev_mc_empty(dev
))
3138 /* Parse the list, and set the appropriate bits */
3139 netdev_for_each_mc_addr(ha
, dev
) {
3141 gfar_set_mac_for_addr(dev
, idx
, ha
->addr
);
3144 gfar_set_hash_for_addr(dev
, ha
->addr
);
3150 /* Clears each of the exact match registers to zero, so they
3151 * don't interfere with normal reception
3153 static void gfar_clear_exact_match(struct net_device
*dev
)
3156 static const u8 zero_arr
[ETH_ALEN
] = {0, 0, 0, 0, 0, 0};
3158 for (idx
= 1; idx
< GFAR_EM_NUM
+ 1; idx
++)
3159 gfar_set_mac_for_addr(dev
, idx
, zero_arr
);
3162 /* Set the appropriate hash bit for the given addr */
3163 /* The algorithm works like so:
3164 * 1) Take the Destination Address (ie the multicast address), and
3165 * do a CRC on it (little endian), and reverse the bits of the
3167 * 2) Use the 8 most significant bits as a hash into a 256-entry
3168 * table. The table is controlled through 8 32-bit registers:
3169 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3170 * gaddr7. This means that the 3 most significant bits in the
3171 * hash index which gaddr register to use, and the 5 other bits
3172 * indicate which bit (assuming an IBM numbering scheme, which
3173 * for PowerPC (tm) is usually the case) in the register holds
3176 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
)
3179 struct gfar_private
*priv
= netdev_priv(dev
);
3180 u32 result
= ether_crc(ETH_ALEN
, addr
);
3181 int width
= priv
->hash_width
;
3182 u8 whichbit
= (result
>> (32 - width
)) & 0x1f;
3183 u8 whichreg
= result
>> (32 - width
+ 5);
3184 u32 value
= (1 << (31-whichbit
));
3186 tempval
= gfar_read(priv
->hash_regs
[whichreg
]);
3188 gfar_write(priv
->hash_regs
[whichreg
], tempval
);
3192 /* There are multiple MAC Address register pairs on some controllers
3193 * This function sets the numth pair to a given address
3195 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
,
3198 struct gfar_private
*priv
= netdev_priv(dev
);
3199 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
3201 char tmpbuf
[ETH_ALEN
];
3203 u32 __iomem
*macptr
= ®s
->macstnaddr1
;
3207 /* Now copy it into the mac registers backwards, cuz
3208 * little endian is silly
3210 for (idx
= 0; idx
< ETH_ALEN
; idx
++)
3211 tmpbuf
[ETH_ALEN
- 1 - idx
] = addr
[idx
];
3213 gfar_write(macptr
, *((u32
*) (tmpbuf
)));
3215 tempval
= *((u32
*) (tmpbuf
+ 4));
3217 gfar_write(macptr
+1, tempval
);
3220 /* GFAR error interrupt handler */
3221 static irqreturn_t
gfar_error(int irq
, void *grp_id
)
3223 struct gfar_priv_grp
*gfargrp
= grp_id
;
3224 struct gfar __iomem
*regs
= gfargrp
->regs
;
3225 struct gfar_private
*priv
= gfargrp
->priv
;
3226 struct net_device
*dev
= priv
->ndev
;
3228 /* Save ievent for future reference */
3229 u32 events
= gfar_read(®s
->ievent
);
3232 gfar_write(®s
->ievent
, events
& IEVENT_ERR_MASK
);
3234 /* Magic Packet is not an error. */
3235 if ((priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
) &&
3236 (events
& IEVENT_MAG
))
3237 events
&= ~IEVENT_MAG
;
3240 if (netif_msg_rx_err(priv
) || netif_msg_tx_err(priv
))
3242 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3243 events
, gfar_read(®s
->imask
));
3245 /* Update the error counters */
3246 if (events
& IEVENT_TXE
) {
3247 dev
->stats
.tx_errors
++;
3249 if (events
& IEVENT_LC
)
3250 dev
->stats
.tx_window_errors
++;
3251 if (events
& IEVENT_CRL
)
3252 dev
->stats
.tx_aborted_errors
++;
3253 if (events
& IEVENT_XFUN
) {
3254 unsigned long flags
;
3256 netif_dbg(priv
, tx_err
, dev
,
3257 "TX FIFO underrun, packet dropped\n");
3258 dev
->stats
.tx_dropped
++;
3259 atomic64_inc(&priv
->extra_stats
.tx_underrun
);
3261 local_irq_save(flags
);
3264 /* Reactivate the Tx Queues */
3265 gfar_write(®s
->tstat
, gfargrp
->tstat
);
3268 local_irq_restore(flags
);
3270 netif_dbg(priv
, tx_err
, dev
, "Transmit Error\n");
3272 if (events
& IEVENT_BSY
) {
3273 dev
->stats
.rx_errors
++;
3274 atomic64_inc(&priv
->extra_stats
.rx_bsy
);
3276 gfar_receive(irq
, grp_id
);
3278 netif_dbg(priv
, rx_err
, dev
, "busy error (rstat: %x)\n",
3279 gfar_read(®s
->rstat
));
3281 if (events
& IEVENT_BABR
) {
3282 dev
->stats
.rx_errors
++;
3283 atomic64_inc(&priv
->extra_stats
.rx_babr
);
3285 netif_dbg(priv
, rx_err
, dev
, "babbling RX error\n");
3287 if (events
& IEVENT_EBERR
) {
3288 atomic64_inc(&priv
->extra_stats
.eberr
);
3289 netif_dbg(priv
, rx_err
, dev
, "bus error\n");
3291 if (events
& IEVENT_RXC
)
3292 netif_dbg(priv
, rx_status
, dev
, "control frame\n");
3294 if (events
& IEVENT_BABT
) {
3295 atomic64_inc(&priv
->extra_stats
.tx_babt
);
3296 netif_dbg(priv
, tx_err
, dev
, "babbling TX error\n");
3301 static struct of_device_id gfar_match
[] =
3305 .compatible
= "gianfar",
3308 .compatible
= "fsl,etsec2",
3312 MODULE_DEVICE_TABLE(of
, gfar_match
);
3314 /* Structure for a device driver */
3315 static struct platform_driver gfar_driver
= {
3317 .name
= "fsl-gianfar",
3318 .owner
= THIS_MODULE
,
3320 .of_match_table
= gfar_match
,
3322 .probe
= gfar_probe
,
3323 .remove
= gfar_remove
,
3326 module_platform_driver(gfar_driver
);