1 /* drivers/net/ethernet/freescale/gianfar.c
3 * Gianfar Ethernet Driver
4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
6 * Based on 8260_io/fcc_enet.c
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
13 * Copyright 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/delay.h>
74 #include <linux/netdevice.h>
75 #include <linux/etherdevice.h>
76 #include <linux/skbuff.h>
77 #include <linux/if_vlan.h>
78 #include <linux/spinlock.h>
80 #include <linux/of_address.h>
81 #include <linux/of_irq.h>
82 #include <linux/of_mdio.h>
83 #include <linux/of_platform.h>
85 #include <linux/tcp.h>
86 #include <linux/udp.h>
88 #include <linux/net_tstamp.h>
92 #include <asm/mpc85xx.h>
94 #include <asm/uaccess.h>
95 #include <linux/module.h>
96 #include <linux/dma-mapping.h>
97 #include <linux/crc32.h>
98 #include <linux/mii.h>
99 #include <linux/phy.h>
100 #include <linux/phy_fixed.h>
101 #include <linux/of.h>
102 #include <linux/of_net.h>
106 #define TX_TIMEOUT (1*HZ)
108 const char gfar_driver_version
[] = "1.3";
110 static int gfar_enet_open(struct net_device
*dev
);
111 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
112 static void gfar_reset_task(struct work_struct
*work
);
113 static void gfar_timeout(struct net_device
*dev
);
114 static int gfar_close(struct net_device
*dev
);
115 struct sk_buff
*gfar_new_skb(struct net_device
*dev
);
116 static void gfar_new_rxbdp(struct gfar_priv_rx_q
*rx_queue
, struct rxbd8
*bdp
,
117 struct sk_buff
*skb
);
118 static int gfar_set_mac_address(struct net_device
*dev
);
119 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
);
120 static irqreturn_t
gfar_error(int irq
, void *dev_id
);
121 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
);
122 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
);
123 static void adjust_link(struct net_device
*dev
);
124 static void init_registers(struct net_device
*dev
);
125 static int init_phy(struct net_device
*dev
);
126 static int gfar_probe(struct platform_device
*ofdev
);
127 static int gfar_remove(struct platform_device
*ofdev
);
128 static void free_skb_resources(struct gfar_private
*priv
);
129 static void gfar_set_multi(struct net_device
*dev
);
130 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
);
131 static void gfar_configure_serdes(struct net_device
*dev
);
132 static int gfar_poll(struct napi_struct
*napi
, int budget
);
133 static int gfar_poll_sq(struct napi_struct
*napi
, int budget
);
134 #ifdef CONFIG_NET_POLL_CONTROLLER
135 static void gfar_netpoll(struct net_device
*dev
);
137 int gfar_clean_rx_ring(struct gfar_priv_rx_q
*rx_queue
, int rx_work_limit
);
138 static void gfar_clean_tx_ring(struct gfar_priv_tx_q
*tx_queue
);
139 static void gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
140 int amount_pull
, struct napi_struct
*napi
);
141 void gfar_halt(struct net_device
*dev
);
142 static void gfar_halt_nodisable(struct net_device
*dev
);
143 void gfar_start(struct net_device
*dev
);
144 static void gfar_clear_exact_match(struct net_device
*dev
);
145 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
,
147 static int gfar_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
);
149 MODULE_AUTHOR("Freescale Semiconductor, Inc");
150 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
151 MODULE_LICENSE("GPL");
153 static void gfar_init_rxbdp(struct gfar_priv_rx_q
*rx_queue
, struct rxbd8
*bdp
,
160 lstatus
= BD_LFLAG(RXBD_EMPTY
| RXBD_INTERRUPT
);
161 if (bdp
== rx_queue
->rx_bd_base
+ rx_queue
->rx_ring_size
- 1)
162 lstatus
|= BD_LFLAG(RXBD_WRAP
);
166 bdp
->lstatus
= lstatus
;
169 static int gfar_init_bds(struct net_device
*ndev
)
171 struct gfar_private
*priv
= netdev_priv(ndev
);
172 struct gfar_priv_tx_q
*tx_queue
= NULL
;
173 struct gfar_priv_rx_q
*rx_queue
= NULL
;
178 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
179 tx_queue
= priv
->tx_queue
[i
];
180 /* Initialize some variables in our dev structure */
181 tx_queue
->num_txbdfree
= tx_queue
->tx_ring_size
;
182 tx_queue
->dirty_tx
= tx_queue
->tx_bd_base
;
183 tx_queue
->cur_tx
= tx_queue
->tx_bd_base
;
184 tx_queue
->skb_curtx
= 0;
185 tx_queue
->skb_dirtytx
= 0;
187 /* Initialize Transmit Descriptor Ring */
188 txbdp
= tx_queue
->tx_bd_base
;
189 for (j
= 0; j
< tx_queue
->tx_ring_size
; j
++) {
195 /* Set the last descriptor in the ring to indicate wrap */
197 txbdp
->status
|= TXBD_WRAP
;
200 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
201 rx_queue
= priv
->rx_queue
[i
];
202 rx_queue
->cur_rx
= rx_queue
->rx_bd_base
;
203 rx_queue
->skb_currx
= 0;
204 rxbdp
= rx_queue
->rx_bd_base
;
206 for (j
= 0; j
< rx_queue
->rx_ring_size
; j
++) {
207 struct sk_buff
*skb
= rx_queue
->rx_skbuff
[j
];
210 gfar_init_rxbdp(rx_queue
, rxbdp
,
213 skb
= gfar_new_skb(ndev
);
215 netdev_err(ndev
, "Can't allocate RX buffers\n");
218 rx_queue
->rx_skbuff
[j
] = skb
;
220 gfar_new_rxbdp(rx_queue
, rxbdp
, skb
);
231 static int gfar_alloc_skb_resources(struct net_device
*ndev
)
236 struct gfar_private
*priv
= netdev_priv(ndev
);
237 struct device
*dev
= priv
->dev
;
238 struct gfar_priv_tx_q
*tx_queue
= NULL
;
239 struct gfar_priv_rx_q
*rx_queue
= NULL
;
241 priv
->total_tx_ring_size
= 0;
242 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
243 priv
->total_tx_ring_size
+= priv
->tx_queue
[i
]->tx_ring_size
;
245 priv
->total_rx_ring_size
= 0;
246 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
247 priv
->total_rx_ring_size
+= priv
->rx_queue
[i
]->rx_ring_size
;
249 /* Allocate memory for the buffer descriptors */
250 vaddr
= dma_alloc_coherent(dev
,
251 (priv
->total_tx_ring_size
*
252 sizeof(struct txbd8
)) +
253 (priv
->total_rx_ring_size
*
254 sizeof(struct rxbd8
)),
259 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
260 tx_queue
= priv
->tx_queue
[i
];
261 tx_queue
->tx_bd_base
= vaddr
;
262 tx_queue
->tx_bd_dma_base
= addr
;
263 tx_queue
->dev
= ndev
;
264 /* enet DMA only understands physical addresses */
265 addr
+= sizeof(struct txbd8
) * tx_queue
->tx_ring_size
;
266 vaddr
+= sizeof(struct txbd8
) * tx_queue
->tx_ring_size
;
269 /* Start the rx descriptor ring where the tx ring leaves off */
270 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
271 rx_queue
= priv
->rx_queue
[i
];
272 rx_queue
->rx_bd_base
= vaddr
;
273 rx_queue
->rx_bd_dma_base
= addr
;
274 rx_queue
->dev
= ndev
;
275 addr
+= sizeof(struct rxbd8
) * rx_queue
->rx_ring_size
;
276 vaddr
+= sizeof(struct rxbd8
) * rx_queue
->rx_ring_size
;
279 /* Setup the skbuff rings */
280 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
281 tx_queue
= priv
->tx_queue
[i
];
282 tx_queue
->tx_skbuff
=
283 kmalloc_array(tx_queue
->tx_ring_size
,
284 sizeof(*tx_queue
->tx_skbuff
),
286 if (!tx_queue
->tx_skbuff
)
289 for (k
= 0; k
< tx_queue
->tx_ring_size
; k
++)
290 tx_queue
->tx_skbuff
[k
] = NULL
;
293 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
294 rx_queue
= priv
->rx_queue
[i
];
295 rx_queue
->rx_skbuff
=
296 kmalloc_array(rx_queue
->rx_ring_size
,
297 sizeof(*rx_queue
->rx_skbuff
),
299 if (!rx_queue
->rx_skbuff
)
302 for (j
= 0; j
< rx_queue
->rx_ring_size
; j
++)
303 rx_queue
->rx_skbuff
[j
] = NULL
;
306 if (gfar_init_bds(ndev
))
312 free_skb_resources(priv
);
316 static void gfar_init_tx_rx_base(struct gfar_private
*priv
)
318 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
322 baddr
= ®s
->tbase0
;
323 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
324 gfar_write(baddr
, priv
->tx_queue
[i
]->tx_bd_dma_base
);
328 baddr
= ®s
->rbase0
;
329 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
330 gfar_write(baddr
, priv
->rx_queue
[i
]->rx_bd_dma_base
);
335 static void gfar_init_mac(struct net_device
*ndev
)
337 struct gfar_private
*priv
= netdev_priv(ndev
);
338 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
343 /* write the tx/rx base registers */
344 gfar_init_tx_rx_base(priv
);
346 /* Configure the coalescing support */
347 gfar_configure_coalescing_all(priv
);
349 /* set this when rx hw offload (TOE) functions are being used */
350 priv
->uses_rxfcb
= 0;
352 if (priv
->rx_filer_enable
) {
353 rctrl
|= RCTRL_FILREN
;
354 /* Program the RIR0 reg with the required distribution */
355 gfar_write(®s
->rir0
, DEFAULT_RIR0
);
358 /* Restore PROMISC mode */
359 if (ndev
->flags
& IFF_PROMISC
)
362 if (ndev
->features
& NETIF_F_RXCSUM
) {
363 rctrl
|= RCTRL_CHECKSUMMING
;
364 priv
->uses_rxfcb
= 1;
367 if (priv
->extended_hash
) {
368 rctrl
|= RCTRL_EXTHASH
;
370 gfar_clear_exact_match(ndev
);
375 rctrl
&= ~RCTRL_PAL_MASK
;
376 rctrl
|= RCTRL_PADDING(priv
->padding
);
379 /* Insert receive time stamps into padding alignment bytes */
380 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_TIMER
) {
381 rctrl
&= ~RCTRL_PAL_MASK
;
382 rctrl
|= RCTRL_PADDING(8);
386 /* Enable HW time stamping if requested from user space */
387 if (priv
->hwts_rx_en
) {
388 rctrl
|= RCTRL_PRSDEP_INIT
| RCTRL_TS_ENABLE
;
389 priv
->uses_rxfcb
= 1;
392 if (ndev
->features
& NETIF_F_HW_VLAN_CTAG_RX
) {
393 rctrl
|= RCTRL_VLEX
| RCTRL_PRSDEP_INIT
;
394 priv
->uses_rxfcb
= 1;
397 /* Init rctrl based on our settings */
398 gfar_write(®s
->rctrl
, rctrl
);
400 if (ndev
->features
& NETIF_F_IP_CSUM
)
401 tctrl
|= TCTRL_INIT_CSUM
;
403 if (priv
->prio_sched_en
)
404 tctrl
|= TCTRL_TXSCHED_PRIO
;
406 tctrl
|= TCTRL_TXSCHED_WRRS
;
407 gfar_write(®s
->tr03wt
, DEFAULT_WRRS_WEIGHT
);
408 gfar_write(®s
->tr47wt
, DEFAULT_WRRS_WEIGHT
);
411 gfar_write(®s
->tctrl
, tctrl
);
413 /* Set the extraction length and index */
414 attrs
= ATTRELI_EL(priv
->rx_stash_size
) |
415 ATTRELI_EI(priv
->rx_stash_index
);
417 gfar_write(®s
->attreli
, attrs
);
419 /* Start with defaults, and add stashing or locking
420 * depending on the approprate variables
422 attrs
= ATTR_INIT_SETTINGS
;
424 if (priv
->bd_stash_en
)
425 attrs
|= ATTR_BDSTASH
;
427 if (priv
->rx_stash_size
!= 0)
428 attrs
|= ATTR_BUFSTASH
;
430 gfar_write(®s
->attr
, attrs
);
432 gfar_write(®s
->fifo_tx_thr
, priv
->fifo_threshold
);
433 gfar_write(®s
->fifo_tx_starve
, priv
->fifo_starve
);
434 gfar_write(®s
->fifo_tx_starve_shutoff
, priv
->fifo_starve_off
);
437 static struct net_device_stats
*gfar_get_stats(struct net_device
*dev
)
439 struct gfar_private
*priv
= netdev_priv(dev
);
440 unsigned long rx_packets
= 0, rx_bytes
= 0, rx_dropped
= 0;
441 unsigned long tx_packets
= 0, tx_bytes
= 0;
444 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
445 rx_packets
+= priv
->rx_queue
[i
]->stats
.rx_packets
;
446 rx_bytes
+= priv
->rx_queue
[i
]->stats
.rx_bytes
;
447 rx_dropped
+= priv
->rx_queue
[i
]->stats
.rx_dropped
;
450 dev
->stats
.rx_packets
= rx_packets
;
451 dev
->stats
.rx_bytes
= rx_bytes
;
452 dev
->stats
.rx_dropped
= rx_dropped
;
454 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
455 tx_bytes
+= priv
->tx_queue
[i
]->stats
.tx_bytes
;
456 tx_packets
+= priv
->tx_queue
[i
]->stats
.tx_packets
;
459 dev
->stats
.tx_bytes
= tx_bytes
;
460 dev
->stats
.tx_packets
= tx_packets
;
465 static const struct net_device_ops gfar_netdev_ops
= {
466 .ndo_open
= gfar_enet_open
,
467 .ndo_start_xmit
= gfar_start_xmit
,
468 .ndo_stop
= gfar_close
,
469 .ndo_change_mtu
= gfar_change_mtu
,
470 .ndo_set_features
= gfar_set_features
,
471 .ndo_set_rx_mode
= gfar_set_multi
,
472 .ndo_tx_timeout
= gfar_timeout
,
473 .ndo_do_ioctl
= gfar_ioctl
,
474 .ndo_get_stats
= gfar_get_stats
,
475 .ndo_set_mac_address
= eth_mac_addr
,
476 .ndo_validate_addr
= eth_validate_addr
,
477 #ifdef CONFIG_NET_POLL_CONTROLLER
478 .ndo_poll_controller
= gfar_netpoll
,
482 void lock_rx_qs(struct gfar_private
*priv
)
486 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
487 spin_lock(&priv
->rx_queue
[i
]->rxlock
);
490 void lock_tx_qs(struct gfar_private
*priv
)
494 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
495 spin_lock(&priv
->tx_queue
[i
]->txlock
);
498 void unlock_rx_qs(struct gfar_private
*priv
)
502 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
503 spin_unlock(&priv
->rx_queue
[i
]->rxlock
);
506 void unlock_tx_qs(struct gfar_private
*priv
)
510 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
511 spin_unlock(&priv
->tx_queue
[i
]->txlock
);
514 static int gfar_alloc_tx_queues(struct gfar_private
*priv
)
518 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
519 priv
->tx_queue
[i
] = kzalloc(sizeof(struct gfar_priv_tx_q
),
521 if (!priv
->tx_queue
[i
])
524 priv
->tx_queue
[i
]->tx_skbuff
= NULL
;
525 priv
->tx_queue
[i
]->qindex
= i
;
526 priv
->tx_queue
[i
]->dev
= priv
->ndev
;
527 spin_lock_init(&(priv
->tx_queue
[i
]->txlock
));
532 static int gfar_alloc_rx_queues(struct gfar_private
*priv
)
536 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
537 priv
->rx_queue
[i
] = kzalloc(sizeof(struct gfar_priv_rx_q
),
539 if (!priv
->rx_queue
[i
])
542 priv
->rx_queue
[i
]->rx_skbuff
= NULL
;
543 priv
->rx_queue
[i
]->qindex
= i
;
544 priv
->rx_queue
[i
]->dev
= priv
->ndev
;
545 spin_lock_init(&(priv
->rx_queue
[i
]->rxlock
));
550 static void gfar_free_tx_queues(struct gfar_private
*priv
)
554 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
555 kfree(priv
->tx_queue
[i
]);
558 static void gfar_free_rx_queues(struct gfar_private
*priv
)
562 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
563 kfree(priv
->rx_queue
[i
]);
566 static void unmap_group_regs(struct gfar_private
*priv
)
570 for (i
= 0; i
< MAXGROUPS
; i
++)
571 if (priv
->gfargrp
[i
].regs
)
572 iounmap(priv
->gfargrp
[i
].regs
);
575 static void free_gfar_dev(struct gfar_private
*priv
)
579 for (i
= 0; i
< priv
->num_grps
; i
++)
580 for (j
= 0; j
< GFAR_NUM_IRQS
; j
++) {
581 kfree(priv
->gfargrp
[i
].irqinfo
[j
]);
582 priv
->gfargrp
[i
].irqinfo
[j
] = NULL
;
585 free_netdev(priv
->ndev
);
588 static void disable_napi(struct gfar_private
*priv
)
592 for (i
= 0; i
< priv
->num_grps
; i
++)
593 napi_disable(&priv
->gfargrp
[i
].napi
);
596 static void enable_napi(struct gfar_private
*priv
)
600 for (i
= 0; i
< priv
->num_grps
; i
++)
601 napi_enable(&priv
->gfargrp
[i
].napi
);
604 static int gfar_parse_group(struct device_node
*np
,
605 struct gfar_private
*priv
, const char *model
)
607 struct gfar_priv_grp
*grp
= &priv
->gfargrp
[priv
->num_grps
];
611 for (i
= 0; i
< GFAR_NUM_IRQS
; i
++) {
612 grp
->irqinfo
[i
] = kzalloc(sizeof(struct gfar_irqinfo
),
614 if (!grp
->irqinfo
[i
])
618 grp
->regs
= of_iomap(np
, 0);
622 gfar_irq(grp
, TX
)->irq
= irq_of_parse_and_map(np
, 0);
624 /* If we aren't the FEC we have multiple interrupts */
625 if (model
&& strcasecmp(model
, "FEC")) {
626 gfar_irq(grp
, RX
)->irq
= irq_of_parse_and_map(np
, 1);
627 gfar_irq(grp
, ER
)->irq
= irq_of_parse_and_map(np
, 2);
628 if (gfar_irq(grp
, TX
)->irq
== NO_IRQ
||
629 gfar_irq(grp
, RX
)->irq
== NO_IRQ
||
630 gfar_irq(grp
, ER
)->irq
== NO_IRQ
)
635 spin_lock_init(&grp
->grplock
);
636 if (priv
->mode
== MQ_MG_MODE
) {
637 queue_mask
= (u32
*)of_get_property(np
, "fsl,rx-bit-map", NULL
);
638 grp
->rx_bit_map
= queue_mask
?
639 *queue_mask
: (DEFAULT_MAPPING
>> priv
->num_grps
);
640 queue_mask
= (u32
*)of_get_property(np
, "fsl,tx-bit-map", NULL
);
641 grp
->tx_bit_map
= queue_mask
?
642 *queue_mask
: (DEFAULT_MAPPING
>> priv
->num_grps
);
644 grp
->rx_bit_map
= 0xFF;
645 grp
->tx_bit_map
= 0xFF;
648 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
649 * right to left, so we need to revert the 8 bits to get the q index
651 grp
->rx_bit_map
= bitrev8(grp
->rx_bit_map
);
652 grp
->tx_bit_map
= bitrev8(grp
->tx_bit_map
);
654 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
655 * also assign queues to groups
657 for_each_set_bit(i
, &grp
->rx_bit_map
, priv
->num_rx_queues
) {
658 grp
->num_rx_queues
++;
659 grp
->rstat
|= (RSTAT_CLEAR_RHALT
>> i
);
660 priv
->rqueue
|= ((RQUEUE_EN0
| RQUEUE_EX0
) >> i
);
661 priv
->rx_queue
[i
]->grp
= grp
;
664 for_each_set_bit(i
, &grp
->tx_bit_map
, priv
->num_tx_queues
) {
665 grp
->num_tx_queues
++;
666 grp
->tstat
|= (TSTAT_CLEAR_THALT
>> i
);
667 priv
->tqueue
|= (TQUEUE_EN0
>> i
);
668 priv
->tx_queue
[i
]->grp
= grp
;
676 static int gfar_of_init(struct platform_device
*ofdev
, struct net_device
**pdev
)
680 const void *mac_addr
;
682 struct net_device
*dev
= NULL
;
683 struct gfar_private
*priv
= NULL
;
684 struct device_node
*np
= ofdev
->dev
.of_node
;
685 struct device_node
*child
= NULL
;
687 const u32
*stash_len
;
688 const u32
*stash_idx
;
689 unsigned int num_tx_qs
, num_rx_qs
;
690 u32
*tx_queues
, *rx_queues
;
692 if (!np
|| !of_device_is_available(np
))
695 /* parse the num of tx and rx queues */
696 tx_queues
= (u32
*)of_get_property(np
, "fsl,num_tx_queues", NULL
);
697 num_tx_qs
= tx_queues
? *tx_queues
: 1;
699 if (num_tx_qs
> MAX_TX_QS
) {
700 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
701 num_tx_qs
, MAX_TX_QS
);
702 pr_err("Cannot do alloc_etherdev, aborting\n");
706 rx_queues
= (u32
*)of_get_property(np
, "fsl,num_rx_queues", NULL
);
707 num_rx_qs
= rx_queues
? *rx_queues
: 1;
709 if (num_rx_qs
> MAX_RX_QS
) {
710 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
711 num_rx_qs
, MAX_RX_QS
);
712 pr_err("Cannot do alloc_etherdev, aborting\n");
716 *pdev
= alloc_etherdev_mq(sizeof(*priv
), num_tx_qs
);
721 priv
= netdev_priv(dev
);
724 priv
->num_tx_queues
= num_tx_qs
;
725 netif_set_real_num_rx_queues(dev
, num_rx_qs
);
726 priv
->num_rx_queues
= num_rx_qs
;
728 err
= gfar_alloc_tx_queues(priv
);
730 goto tx_alloc_failed
;
732 err
= gfar_alloc_rx_queues(priv
);
734 goto rx_alloc_failed
;
736 /* Init Rx queue filer rule set linked list */
737 INIT_LIST_HEAD(&priv
->rx_list
.list
);
738 priv
->rx_list
.count
= 0;
739 mutex_init(&priv
->rx_queue_access
);
741 model
= of_get_property(np
, "model", NULL
);
743 for (i
= 0; i
< MAXGROUPS
; i
++)
744 priv
->gfargrp
[i
].regs
= NULL
;
746 /* Parse and initialize group specific information */
747 if (of_device_is_compatible(np
, "fsl,etsec2")) {
748 priv
->mode
= MQ_MG_MODE
;
749 for_each_child_of_node(np
, child
) {
750 err
= gfar_parse_group(child
, priv
, model
);
755 priv
->mode
= SQ_SG_MODE
;
756 err
= gfar_parse_group(np
, priv
, model
);
761 stash
= of_get_property(np
, "bd-stash", NULL
);
764 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_BD_STASHING
;
765 priv
->bd_stash_en
= 1;
768 stash_len
= of_get_property(np
, "rx-stash-len", NULL
);
771 priv
->rx_stash_size
= *stash_len
;
773 stash_idx
= of_get_property(np
, "rx-stash-idx", NULL
);
776 priv
->rx_stash_index
= *stash_idx
;
778 if (stash_len
|| stash_idx
)
779 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_BUF_STASHING
;
781 mac_addr
= of_get_mac_address(np
);
784 memcpy(dev
->dev_addr
, mac_addr
, ETH_ALEN
);
786 if (model
&& !strcasecmp(model
, "TSEC"))
787 priv
->device_flags
= FSL_GIANFAR_DEV_HAS_GIGABIT
|
788 FSL_GIANFAR_DEV_HAS_COALESCE
|
789 FSL_GIANFAR_DEV_HAS_RMON
|
790 FSL_GIANFAR_DEV_HAS_MULTI_INTR
;
792 if (model
&& !strcasecmp(model
, "eTSEC"))
793 priv
->device_flags
= FSL_GIANFAR_DEV_HAS_GIGABIT
|
794 FSL_GIANFAR_DEV_HAS_COALESCE
|
795 FSL_GIANFAR_DEV_HAS_RMON
|
796 FSL_GIANFAR_DEV_HAS_MULTI_INTR
|
797 FSL_GIANFAR_DEV_HAS_PADDING
|
798 FSL_GIANFAR_DEV_HAS_CSUM
|
799 FSL_GIANFAR_DEV_HAS_VLAN
|
800 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
|
801 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
|
802 FSL_GIANFAR_DEV_HAS_TIMER
;
804 ctype
= of_get_property(np
, "phy-connection-type", NULL
);
806 /* We only care about rgmii-id. The rest are autodetected */
807 if (ctype
&& !strcmp(ctype
, "rgmii-id"))
808 priv
->interface
= PHY_INTERFACE_MODE_RGMII_ID
;
810 priv
->interface
= PHY_INTERFACE_MODE_MII
;
812 if (of_get_property(np
, "fsl,magic-packet", NULL
))
813 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
;
815 priv
->phy_node
= of_parse_phandle(np
, "phy-handle", 0);
817 /* Find the TBI PHY. If it's not there, we don't support SGMII */
818 priv
->tbi_node
= of_parse_phandle(np
, "tbi-handle", 0);
823 unmap_group_regs(priv
);
825 gfar_free_rx_queues(priv
);
827 gfar_free_tx_queues(priv
);
832 static int gfar_hwtstamp_set(struct net_device
*netdev
, struct ifreq
*ifr
)
834 struct hwtstamp_config config
;
835 struct gfar_private
*priv
= netdev_priv(netdev
);
837 if (copy_from_user(&config
, ifr
->ifr_data
, sizeof(config
)))
840 /* reserved for future extensions */
844 switch (config
.tx_type
) {
845 case HWTSTAMP_TX_OFF
:
846 priv
->hwts_tx_en
= 0;
849 if (!(priv
->device_flags
& FSL_GIANFAR_DEV_HAS_TIMER
))
851 priv
->hwts_tx_en
= 1;
857 switch (config
.rx_filter
) {
858 case HWTSTAMP_FILTER_NONE
:
859 if (priv
->hwts_rx_en
) {
861 priv
->hwts_rx_en
= 0;
862 startup_gfar(netdev
);
866 if (!(priv
->device_flags
& FSL_GIANFAR_DEV_HAS_TIMER
))
868 if (!priv
->hwts_rx_en
) {
870 priv
->hwts_rx_en
= 1;
871 startup_gfar(netdev
);
873 config
.rx_filter
= HWTSTAMP_FILTER_ALL
;
877 return copy_to_user(ifr
->ifr_data
, &config
, sizeof(config
)) ?
881 static int gfar_hwtstamp_get(struct net_device
*netdev
, struct ifreq
*ifr
)
883 struct hwtstamp_config config
;
884 struct gfar_private
*priv
= netdev_priv(netdev
);
887 config
.tx_type
= priv
->hwts_tx_en
? HWTSTAMP_TX_ON
: HWTSTAMP_TX_OFF
;
888 config
.rx_filter
= (priv
->hwts_rx_en
?
889 HWTSTAMP_FILTER_ALL
: HWTSTAMP_FILTER_NONE
);
891 return copy_to_user(ifr
->ifr_data
, &config
, sizeof(config
)) ?
895 static int gfar_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
897 struct gfar_private
*priv
= netdev_priv(dev
);
899 if (!netif_running(dev
))
902 if (cmd
== SIOCSHWTSTAMP
)
903 return gfar_hwtstamp_set(dev
, rq
);
904 if (cmd
== SIOCGHWTSTAMP
)
905 return gfar_hwtstamp_get(dev
, rq
);
910 return phy_mii_ioctl(priv
->phydev
, rq
, cmd
);
913 static u32
cluster_entry_per_class(struct gfar_private
*priv
, u32 rqfar
,
916 u32 rqfpr
= FPR_FILER_MASK
;
920 rqfcr
= RQFCR_CLE
| RQFCR_PID_MASK
| RQFCR_CMP_EXACT
;
921 priv
->ftp_rqfpr
[rqfar
] = rqfpr
;
922 priv
->ftp_rqfcr
[rqfar
] = rqfcr
;
923 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
926 rqfcr
= RQFCR_CMP_NOMATCH
;
927 priv
->ftp_rqfpr
[rqfar
] = rqfpr
;
928 priv
->ftp_rqfcr
[rqfar
] = rqfcr
;
929 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
932 rqfcr
= RQFCR_CMP_EXACT
| RQFCR_PID_PARSE
| RQFCR_CLE
| RQFCR_AND
;
934 priv
->ftp_rqfcr
[rqfar
] = rqfcr
;
935 priv
->ftp_rqfpr
[rqfar
] = rqfpr
;
936 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
939 rqfcr
= RQFCR_CMP_EXACT
| RQFCR_PID_MASK
| RQFCR_AND
;
941 priv
->ftp_rqfcr
[rqfar
] = rqfcr
;
942 priv
->ftp_rqfpr
[rqfar
] = rqfpr
;
943 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
948 static void gfar_init_filer_table(struct gfar_private
*priv
)
951 u32 rqfar
= MAX_FILER_IDX
;
953 u32 rqfpr
= FPR_FILER_MASK
;
956 rqfcr
= RQFCR_CMP_MATCH
;
957 priv
->ftp_rqfcr
[rqfar
] = rqfcr
;
958 priv
->ftp_rqfpr
[rqfar
] = rqfpr
;
959 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
961 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV6
);
962 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV6
| RQFPR_UDP
);
963 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV6
| RQFPR_TCP
);
964 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV4
);
965 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV4
| RQFPR_UDP
);
966 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV4
| RQFPR_TCP
);
968 /* cur_filer_idx indicated the first non-masked rule */
969 priv
->cur_filer_idx
= rqfar
;
971 /* Rest are masked rules */
972 rqfcr
= RQFCR_CMP_NOMATCH
;
973 for (i
= 0; i
< rqfar
; i
++) {
974 priv
->ftp_rqfcr
[i
] = rqfcr
;
975 priv
->ftp_rqfpr
[i
] = rqfpr
;
976 gfar_write_filer(priv
, i
, rqfcr
, rqfpr
);
980 static void __gfar_detect_errata_83xx(struct gfar_private
*priv
)
982 unsigned int pvr
= mfspr(SPRN_PVR
);
983 unsigned int svr
= mfspr(SPRN_SVR
);
984 unsigned int mod
= (svr
>> 16) & 0xfff6; /* w/o E suffix */
985 unsigned int rev
= svr
& 0xffff;
987 /* MPC8313 Rev 2.0 and higher; All MPC837x */
988 if ((pvr
== 0x80850010 && mod
== 0x80b0 && rev
>= 0x0020) ||
989 (pvr
== 0x80861010 && (mod
& 0xfff9) == 0x80c0))
990 priv
->errata
|= GFAR_ERRATA_74
;
992 /* MPC8313 and MPC837x all rev */
993 if ((pvr
== 0x80850010 && mod
== 0x80b0) ||
994 (pvr
== 0x80861010 && (mod
& 0xfff9) == 0x80c0))
995 priv
->errata
|= GFAR_ERRATA_76
;
997 /* MPC8313 Rev < 2.0 */
998 if (pvr
== 0x80850010 && mod
== 0x80b0 && rev
< 0x0020)
999 priv
->errata
|= GFAR_ERRATA_12
;
1002 static void __gfar_detect_errata_85xx(struct gfar_private
*priv
)
1004 unsigned int svr
= mfspr(SPRN_SVR
);
1006 if ((SVR_SOC_VER(svr
) == SVR_8548
) && (SVR_REV(svr
) == 0x20))
1007 priv
->errata
|= GFAR_ERRATA_12
;
1008 if (((SVR_SOC_VER(svr
) == SVR_P2020
) && (SVR_REV(svr
) < 0x20)) ||
1009 ((SVR_SOC_VER(svr
) == SVR_P2010
) && (SVR_REV(svr
) < 0x20)))
1010 priv
->errata
|= GFAR_ERRATA_76
; /* aka eTSEC 20 */
1013 static void gfar_detect_errata(struct gfar_private
*priv
)
1015 struct device
*dev
= &priv
->ofdev
->dev
;
1017 /* no plans to fix */
1018 priv
->errata
|= GFAR_ERRATA_A002
;
1020 if (pvr_version_is(PVR_VER_E500V1
) || pvr_version_is(PVR_VER_E500V2
))
1021 __gfar_detect_errata_85xx(priv
);
1022 else /* non-mpc85xx parts, i.e. e300 core based */
1023 __gfar_detect_errata_83xx(priv
);
1026 dev_info(dev
, "enabled errata workarounds, flags: 0x%x\n",
1030 static void gfar_hw_init(struct gfar_private
*priv
)
1032 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1035 /* Reset MAC layer */
1036 gfar_write(®s
->maccfg1
, MACCFG1_SOFT_RESET
);
1038 /* We need to delay at least 3 TX clocks */
1041 /* the soft reset bit is not self-resetting, so we need to
1042 * clear it before resuming normal operation
1044 gfar_write(®s
->maccfg1
, 0);
1046 /* Initialize MACCFG2. */
1047 tempval
= MACCFG2_INIT_SETTINGS
;
1048 if (gfar_has_errata(priv
, GFAR_ERRATA_74
))
1049 tempval
|= MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
;
1050 gfar_write(®s
->maccfg2
, tempval
);
1052 /* Initialize ECNTRL */
1053 gfar_write(®s
->ecntrl
, ECNTRL_INIT_SETTINGS
);
1055 /* Program the interrupt steering regs, only for MG devices */
1056 if (priv
->num_grps
> 1)
1057 gfar_write_isrg(priv
);
1059 /* Enable all Rx/Tx queues after MAC reset */
1060 gfar_write(®s
->rqueue
, priv
->rqueue
);
1061 gfar_write(®s
->tqueue
, priv
->tqueue
);
1064 static void __init
gfar_init_addr_hash_table(struct gfar_private
*priv
)
1066 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1068 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
) {
1069 priv
->extended_hash
= 1;
1070 priv
->hash_width
= 9;
1072 priv
->hash_regs
[0] = ®s
->igaddr0
;
1073 priv
->hash_regs
[1] = ®s
->igaddr1
;
1074 priv
->hash_regs
[2] = ®s
->igaddr2
;
1075 priv
->hash_regs
[3] = ®s
->igaddr3
;
1076 priv
->hash_regs
[4] = ®s
->igaddr4
;
1077 priv
->hash_regs
[5] = ®s
->igaddr5
;
1078 priv
->hash_regs
[6] = ®s
->igaddr6
;
1079 priv
->hash_regs
[7] = ®s
->igaddr7
;
1080 priv
->hash_regs
[8] = ®s
->gaddr0
;
1081 priv
->hash_regs
[9] = ®s
->gaddr1
;
1082 priv
->hash_regs
[10] = ®s
->gaddr2
;
1083 priv
->hash_regs
[11] = ®s
->gaddr3
;
1084 priv
->hash_regs
[12] = ®s
->gaddr4
;
1085 priv
->hash_regs
[13] = ®s
->gaddr5
;
1086 priv
->hash_regs
[14] = ®s
->gaddr6
;
1087 priv
->hash_regs
[15] = ®s
->gaddr7
;
1090 priv
->extended_hash
= 0;
1091 priv
->hash_width
= 8;
1093 priv
->hash_regs
[0] = ®s
->gaddr0
;
1094 priv
->hash_regs
[1] = ®s
->gaddr1
;
1095 priv
->hash_regs
[2] = ®s
->gaddr2
;
1096 priv
->hash_regs
[3] = ®s
->gaddr3
;
1097 priv
->hash_regs
[4] = ®s
->gaddr4
;
1098 priv
->hash_regs
[5] = ®s
->gaddr5
;
1099 priv
->hash_regs
[6] = ®s
->gaddr6
;
1100 priv
->hash_regs
[7] = ®s
->gaddr7
;
1104 /* Set up the ethernet device structure, private data,
1105 * and anything else we need before we start
1107 static int gfar_probe(struct platform_device
*ofdev
)
1109 struct net_device
*dev
= NULL
;
1110 struct gfar_private
*priv
= NULL
;
1113 err
= gfar_of_init(ofdev
, &dev
);
1118 priv
= netdev_priv(dev
);
1120 priv
->ofdev
= ofdev
;
1121 priv
->dev
= &ofdev
->dev
;
1122 SET_NETDEV_DEV(dev
, &ofdev
->dev
);
1124 spin_lock_init(&priv
->bflock
);
1125 INIT_WORK(&priv
->reset_task
, gfar_reset_task
);
1127 platform_set_drvdata(ofdev
, priv
);
1129 gfar_detect_errata(priv
);
1131 /* Stop the DMA engine now, in case it was running before
1132 * (The firmware could have used it, and left it running).
1138 /* Set the dev->base_addr to the gfar reg region */
1139 dev
->base_addr
= (unsigned long) priv
->gfargrp
[0].regs
;
1141 /* Fill in the dev structure */
1142 dev
->watchdog_timeo
= TX_TIMEOUT
;
1144 dev
->netdev_ops
= &gfar_netdev_ops
;
1145 dev
->ethtool_ops
= &gfar_ethtool_ops
;
1147 /* Register for napi ...We are registering NAPI for each grp */
1148 if (priv
->mode
== SQ_SG_MODE
)
1149 netif_napi_add(dev
, &priv
->gfargrp
[0].napi
, gfar_poll_sq
,
1152 for (i
= 0; i
< priv
->num_grps
; i
++)
1153 netif_napi_add(dev
, &priv
->gfargrp
[i
].napi
, gfar_poll
,
1156 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_CSUM
) {
1157 dev
->hw_features
= NETIF_F_IP_CSUM
| NETIF_F_SG
|
1159 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
|
1160 NETIF_F_RXCSUM
| NETIF_F_HIGHDMA
;
1163 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_VLAN
) {
1164 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_TX
|
1165 NETIF_F_HW_VLAN_CTAG_RX
;
1166 dev
->features
|= NETIF_F_HW_VLAN_CTAG_RX
;
1169 gfar_init_addr_hash_table(priv
);
1171 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_PADDING
)
1172 priv
->padding
= DEFAULT_PADDING
;
1176 if (dev
->features
& NETIF_F_IP_CSUM
||
1177 priv
->device_flags
& FSL_GIANFAR_DEV_HAS_TIMER
)
1178 dev
->needed_headroom
= GMAC_FCB_LEN
;
1180 priv
->rx_buffer_size
= DEFAULT_RX_BUFFER_SIZE
;
1182 /* Initializing some of the rx/tx queue level parameters */
1183 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
1184 priv
->tx_queue
[i
]->tx_ring_size
= DEFAULT_TX_RING_SIZE
;
1185 priv
->tx_queue
[i
]->num_txbdfree
= DEFAULT_TX_RING_SIZE
;
1186 priv
->tx_queue
[i
]->txcoalescing
= DEFAULT_TX_COALESCE
;
1187 priv
->tx_queue
[i
]->txic
= DEFAULT_TXIC
;
1190 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
1191 priv
->rx_queue
[i
]->rx_ring_size
= DEFAULT_RX_RING_SIZE
;
1192 priv
->rx_queue
[i
]->rxcoalescing
= DEFAULT_RX_COALESCE
;
1193 priv
->rx_queue
[i
]->rxic
= DEFAULT_RXIC
;
1196 /* always enable rx filer */
1197 priv
->rx_filer_enable
= 1;
1198 /* Enable most messages by default */
1199 priv
->msg_enable
= (NETIF_MSG_IFUP
<< 1 ) - 1;
1200 /* use pritority h/w tx queue scheduling for single queue devices */
1201 if (priv
->num_tx_queues
== 1)
1202 priv
->prio_sched_en
= 1;
1204 /* Carrier starts down, phylib will bring it up */
1205 netif_carrier_off(dev
);
1207 err
= register_netdev(dev
);
1210 pr_err("%s: Cannot register net device, aborting\n", dev
->name
);
1214 device_init_wakeup(&dev
->dev
,
1215 priv
->device_flags
&
1216 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
1218 /* fill out IRQ number and name fields */
1219 for (i
= 0; i
< priv
->num_grps
; i
++) {
1220 struct gfar_priv_grp
*grp
= &priv
->gfargrp
[i
];
1221 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1222 sprintf(gfar_irq(grp
, TX
)->name
, "%s%s%c%s",
1223 dev
->name
, "_g", '0' + i
, "_tx");
1224 sprintf(gfar_irq(grp
, RX
)->name
, "%s%s%c%s",
1225 dev
->name
, "_g", '0' + i
, "_rx");
1226 sprintf(gfar_irq(grp
, ER
)->name
, "%s%s%c%s",
1227 dev
->name
, "_g", '0' + i
, "_er");
1229 strcpy(gfar_irq(grp
, TX
)->name
, dev
->name
);
1232 /* Initialize the filer table */
1233 gfar_init_filer_table(priv
);
1235 /* Create all the sysfs files */
1236 gfar_init_sysfs(dev
);
1238 /* Print out the device info */
1239 netdev_info(dev
, "mac: %pM\n", dev
->dev_addr
);
1241 /* Even more device info helps when determining which kernel
1242 * provided which set of benchmarks.
1244 netdev_info(dev
, "Running with NAPI enabled\n");
1245 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
1246 netdev_info(dev
, "RX BD ring size for Q[%d]: %d\n",
1247 i
, priv
->rx_queue
[i
]->rx_ring_size
);
1248 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
1249 netdev_info(dev
, "TX BD ring size for Q[%d]: %d\n",
1250 i
, priv
->tx_queue
[i
]->tx_ring_size
);
1255 unmap_group_regs(priv
);
1256 gfar_free_rx_queues(priv
);
1257 gfar_free_tx_queues(priv
);
1259 of_node_put(priv
->phy_node
);
1261 of_node_put(priv
->tbi_node
);
1262 free_gfar_dev(priv
);
1266 static int gfar_remove(struct platform_device
*ofdev
)
1268 struct gfar_private
*priv
= platform_get_drvdata(ofdev
);
1271 of_node_put(priv
->phy_node
);
1273 of_node_put(priv
->tbi_node
);
1275 unregister_netdev(priv
->ndev
);
1276 unmap_group_regs(priv
);
1277 gfar_free_rx_queues(priv
);
1278 gfar_free_tx_queues(priv
);
1279 free_gfar_dev(priv
);
1286 static int gfar_suspend(struct device
*dev
)
1288 struct gfar_private
*priv
= dev_get_drvdata(dev
);
1289 struct net_device
*ndev
= priv
->ndev
;
1290 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1291 unsigned long flags
;
1294 int magic_packet
= priv
->wol_en
&&
1295 (priv
->device_flags
&
1296 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
1298 netif_device_detach(ndev
);
1300 if (netif_running(ndev
)) {
1302 local_irq_save(flags
);
1306 gfar_halt_nodisable(ndev
);
1308 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1309 tempval
= gfar_read(®s
->maccfg1
);
1311 tempval
&= ~MACCFG1_TX_EN
;
1314 tempval
&= ~MACCFG1_RX_EN
;
1316 gfar_write(®s
->maccfg1
, tempval
);
1320 local_irq_restore(flags
);
1325 /* Enable interrupt on Magic Packet */
1326 gfar_write(®s
->imask
, IMASK_MAG
);
1328 /* Enable Magic Packet mode */
1329 tempval
= gfar_read(®s
->maccfg2
);
1330 tempval
|= MACCFG2_MPEN
;
1331 gfar_write(®s
->maccfg2
, tempval
);
1333 phy_stop(priv
->phydev
);
1340 static int gfar_resume(struct device
*dev
)
1342 struct gfar_private
*priv
= dev_get_drvdata(dev
);
1343 struct net_device
*ndev
= priv
->ndev
;
1344 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1345 unsigned long flags
;
1347 int magic_packet
= priv
->wol_en
&&
1348 (priv
->device_flags
&
1349 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
1351 if (!netif_running(ndev
)) {
1352 netif_device_attach(ndev
);
1356 if (!magic_packet
&& priv
->phydev
)
1357 phy_start(priv
->phydev
);
1359 /* Disable Magic Packet mode, in case something
1362 local_irq_save(flags
);
1366 tempval
= gfar_read(®s
->maccfg2
);
1367 tempval
&= ~MACCFG2_MPEN
;
1368 gfar_write(®s
->maccfg2
, tempval
);
1374 local_irq_restore(flags
);
1376 netif_device_attach(ndev
);
1383 static int gfar_restore(struct device
*dev
)
1385 struct gfar_private
*priv
= dev_get_drvdata(dev
);
1386 struct net_device
*ndev
= priv
->ndev
;
1388 if (!netif_running(ndev
)) {
1389 netif_device_attach(ndev
);
1394 if (gfar_init_bds(ndev
)) {
1395 free_skb_resources(priv
);
1399 init_registers(ndev
);
1400 gfar_set_mac_address(ndev
);
1401 gfar_init_mac(ndev
);
1406 priv
->oldduplex
= -1;
1409 phy_start(priv
->phydev
);
1411 netif_device_attach(ndev
);
1417 static struct dev_pm_ops gfar_pm_ops
= {
1418 .suspend
= gfar_suspend
,
1419 .resume
= gfar_resume
,
1420 .freeze
= gfar_suspend
,
1421 .thaw
= gfar_resume
,
1422 .restore
= gfar_restore
,
1425 #define GFAR_PM_OPS (&gfar_pm_ops)
1429 #define GFAR_PM_OPS NULL
1433 /* Reads the controller's registers to determine what interface
1434 * connects it to the PHY.
1436 static phy_interface_t
gfar_get_interface(struct net_device
*dev
)
1438 struct gfar_private
*priv
= netdev_priv(dev
);
1439 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1442 ecntrl
= gfar_read(®s
->ecntrl
);
1444 if (ecntrl
& ECNTRL_SGMII_MODE
)
1445 return PHY_INTERFACE_MODE_SGMII
;
1447 if (ecntrl
& ECNTRL_TBI_MODE
) {
1448 if (ecntrl
& ECNTRL_REDUCED_MODE
)
1449 return PHY_INTERFACE_MODE_RTBI
;
1451 return PHY_INTERFACE_MODE_TBI
;
1454 if (ecntrl
& ECNTRL_REDUCED_MODE
) {
1455 if (ecntrl
& ECNTRL_REDUCED_MII_MODE
) {
1456 return PHY_INTERFACE_MODE_RMII
;
1459 phy_interface_t interface
= priv
->interface
;
1461 /* This isn't autodetected right now, so it must
1462 * be set by the device tree or platform code.
1464 if (interface
== PHY_INTERFACE_MODE_RGMII_ID
)
1465 return PHY_INTERFACE_MODE_RGMII_ID
;
1467 return PHY_INTERFACE_MODE_RGMII
;
1471 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
)
1472 return PHY_INTERFACE_MODE_GMII
;
1474 return PHY_INTERFACE_MODE_MII
;
1478 /* Initializes driver's PHY state, and attaches to the PHY.
1479 * Returns 0 on success.
1481 static int init_phy(struct net_device
*dev
)
1483 struct gfar_private
*priv
= netdev_priv(dev
);
1484 uint gigabit_support
=
1485 priv
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
?
1486 GFAR_SUPPORTED_GBIT
: 0;
1487 phy_interface_t interface
;
1491 priv
->oldduplex
= -1;
1493 interface
= gfar_get_interface(dev
);
1495 priv
->phydev
= of_phy_connect(dev
, priv
->phy_node
, &adjust_link
, 0,
1498 priv
->phydev
= of_phy_connect_fixed_link(dev
, &adjust_link
,
1500 if (!priv
->phydev
) {
1501 dev_err(&dev
->dev
, "could not attach to PHY\n");
1505 if (interface
== PHY_INTERFACE_MODE_SGMII
)
1506 gfar_configure_serdes(dev
);
1508 /* Remove any features not supported by the controller */
1509 priv
->phydev
->supported
&= (GFAR_SUPPORTED
| gigabit_support
);
1510 priv
->phydev
->advertising
= priv
->phydev
->supported
;
1515 /* Initialize TBI PHY interface for communicating with the
1516 * SERDES lynx PHY on the chip. We communicate with this PHY
1517 * through the MDIO bus on each controller, treating it as a
1518 * "normal" PHY at the address found in the TBIPA register. We assume
1519 * that the TBIPA register is valid. Either the MDIO bus code will set
1520 * it to a value that doesn't conflict with other PHYs on the bus, or the
1521 * value doesn't matter, as there are no other PHYs on the bus.
1523 static void gfar_configure_serdes(struct net_device
*dev
)
1525 struct gfar_private
*priv
= netdev_priv(dev
);
1526 struct phy_device
*tbiphy
;
1528 if (!priv
->tbi_node
) {
1529 dev_warn(&dev
->dev
, "error: SGMII mode requires that the "
1530 "device tree specify a tbi-handle\n");
1534 tbiphy
= of_phy_find_device(priv
->tbi_node
);
1536 dev_err(&dev
->dev
, "error: Could not get TBI device\n");
1540 /* If the link is already up, we must already be ok, and don't need to
1541 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1542 * everything for us? Resetting it takes the link down and requires
1543 * several seconds for it to come back.
1545 if (phy_read(tbiphy
, MII_BMSR
) & BMSR_LSTATUS
)
1548 /* Single clk mode, mii mode off(for serdes communication) */
1549 phy_write(tbiphy
, MII_TBICON
, TBICON_CLK_SELECT
);
1551 phy_write(tbiphy
, MII_ADVERTISE
,
1552 ADVERTISE_1000XFULL
| ADVERTISE_1000XPAUSE
|
1553 ADVERTISE_1000XPSE_ASYM
);
1555 phy_write(tbiphy
, MII_BMCR
,
1556 BMCR_ANENABLE
| BMCR_ANRESTART
| BMCR_FULLDPLX
|
1560 static void init_registers(struct net_device
*dev
)
1562 struct gfar_private
*priv
= netdev_priv(dev
);
1563 struct gfar __iomem
*regs
= NULL
;
1566 for (i
= 0; i
< priv
->num_grps
; i
++) {
1567 regs
= priv
->gfargrp
[i
].regs
;
1569 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
1571 /* Initialize IMASK */
1572 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
1575 regs
= priv
->gfargrp
[0].regs
;
1576 /* Init hash registers to zero */
1577 gfar_write(®s
->igaddr0
, 0);
1578 gfar_write(®s
->igaddr1
, 0);
1579 gfar_write(®s
->igaddr2
, 0);
1580 gfar_write(®s
->igaddr3
, 0);
1581 gfar_write(®s
->igaddr4
, 0);
1582 gfar_write(®s
->igaddr5
, 0);
1583 gfar_write(®s
->igaddr6
, 0);
1584 gfar_write(®s
->igaddr7
, 0);
1586 gfar_write(®s
->gaddr0
, 0);
1587 gfar_write(®s
->gaddr1
, 0);
1588 gfar_write(®s
->gaddr2
, 0);
1589 gfar_write(®s
->gaddr3
, 0);
1590 gfar_write(®s
->gaddr4
, 0);
1591 gfar_write(®s
->gaddr5
, 0);
1592 gfar_write(®s
->gaddr6
, 0);
1593 gfar_write(®s
->gaddr7
, 0);
1595 /* Zero out the rmon mib registers if it has them */
1596 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_RMON
) {
1597 memset_io(&(regs
->rmon
), 0, sizeof (struct rmon_mib
));
1599 /* Mask off the CAM interrupts */
1600 gfar_write(®s
->rmon
.cam1
, 0xffffffff);
1601 gfar_write(®s
->rmon
.cam2
, 0xffffffff);
1604 /* Initialize the max receive buffer length */
1605 gfar_write(®s
->mrblr
, priv
->rx_buffer_size
);
1607 /* Initialize the Minimum Frame Length Register */
1608 gfar_write(®s
->minflr
, MINFLR_INIT_SETTINGS
);
1611 static int __gfar_is_rx_idle(struct gfar_private
*priv
)
1615 /* Normaly TSEC should not hang on GRS commands, so we should
1616 * actually wait for IEVENT_GRSC flag.
1618 if (!gfar_has_errata(priv
, GFAR_ERRATA_A002
))
1621 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1622 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1623 * and the Rx can be safely reset.
1625 res
= gfar_read((void __iomem
*)priv
->gfargrp
[0].regs
+ 0xd1c);
1627 if ((res
& 0xffff) == (res
>> 16))
1633 /* Halt the receive and transmit queues */
1634 static void gfar_halt_nodisable(struct net_device
*dev
)
1636 struct gfar_private
*priv
= netdev_priv(dev
);
1637 struct gfar __iomem
*regs
= NULL
;
1641 for (i
= 0; i
< priv
->num_grps
; i
++) {
1642 regs
= priv
->gfargrp
[i
].regs
;
1643 /* Mask all interrupts */
1644 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
1646 /* Clear all interrupts */
1647 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
1650 regs
= priv
->gfargrp
[0].regs
;
1651 /* Stop the DMA, and wait for it to stop */
1652 tempval
= gfar_read(®s
->dmactrl
);
1653 if ((tempval
& (DMACTRL_GRS
| DMACTRL_GTS
)) !=
1654 (DMACTRL_GRS
| DMACTRL_GTS
)) {
1657 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
1658 gfar_write(®s
->dmactrl
, tempval
);
1661 ret
= spin_event_timeout(((gfar_read(®s
->ievent
) &
1662 (IEVENT_GRSC
| IEVENT_GTSC
)) ==
1663 (IEVENT_GRSC
| IEVENT_GTSC
)), 1000000, 0);
1664 if (!ret
&& !(gfar_read(®s
->ievent
) & IEVENT_GRSC
))
1665 ret
= __gfar_is_rx_idle(priv
);
1670 /* Halt the receive and transmit queues */
1671 void gfar_halt(struct net_device
*dev
)
1673 struct gfar_private
*priv
= netdev_priv(dev
);
1674 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1677 gfar_halt_nodisable(dev
);
1679 /* Disable Rx and Tx */
1680 tempval
= gfar_read(®s
->maccfg1
);
1681 tempval
&= ~(MACCFG1_RX_EN
| MACCFG1_TX_EN
);
1682 gfar_write(®s
->maccfg1
, tempval
);
1685 static void free_grp_irqs(struct gfar_priv_grp
*grp
)
1687 free_irq(gfar_irq(grp
, TX
)->irq
, grp
);
1688 free_irq(gfar_irq(grp
, RX
)->irq
, grp
);
1689 free_irq(gfar_irq(grp
, ER
)->irq
, grp
);
1692 void stop_gfar(struct net_device
*dev
)
1694 struct gfar_private
*priv
= netdev_priv(dev
);
1695 unsigned long flags
;
1698 phy_stop(priv
->phydev
);
1702 local_irq_save(flags
);
1710 local_irq_restore(flags
);
1713 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1714 for (i
= 0; i
< priv
->num_grps
; i
++)
1715 free_grp_irqs(&priv
->gfargrp
[i
]);
1717 for (i
= 0; i
< priv
->num_grps
; i
++)
1718 free_irq(gfar_irq(&priv
->gfargrp
[i
], TX
)->irq
,
1722 free_skb_resources(priv
);
1725 static void free_skb_tx_queue(struct gfar_priv_tx_q
*tx_queue
)
1727 struct txbd8
*txbdp
;
1728 struct gfar_private
*priv
= netdev_priv(tx_queue
->dev
);
1731 txbdp
= tx_queue
->tx_bd_base
;
1733 for (i
= 0; i
< tx_queue
->tx_ring_size
; i
++) {
1734 if (!tx_queue
->tx_skbuff
[i
])
1737 dma_unmap_single(priv
->dev
, txbdp
->bufPtr
,
1738 txbdp
->length
, DMA_TO_DEVICE
);
1740 for (j
= 0; j
< skb_shinfo(tx_queue
->tx_skbuff
[i
])->nr_frags
;
1743 dma_unmap_page(priv
->dev
, txbdp
->bufPtr
,
1744 txbdp
->length
, DMA_TO_DEVICE
);
1747 dev_kfree_skb_any(tx_queue
->tx_skbuff
[i
]);
1748 tx_queue
->tx_skbuff
[i
] = NULL
;
1750 kfree(tx_queue
->tx_skbuff
);
1751 tx_queue
->tx_skbuff
= NULL
;
1754 static void free_skb_rx_queue(struct gfar_priv_rx_q
*rx_queue
)
1756 struct rxbd8
*rxbdp
;
1757 struct gfar_private
*priv
= netdev_priv(rx_queue
->dev
);
1760 rxbdp
= rx_queue
->rx_bd_base
;
1762 for (i
= 0; i
< rx_queue
->rx_ring_size
; i
++) {
1763 if (rx_queue
->rx_skbuff
[i
]) {
1764 dma_unmap_single(priv
->dev
, rxbdp
->bufPtr
,
1765 priv
->rx_buffer_size
,
1767 dev_kfree_skb_any(rx_queue
->rx_skbuff
[i
]);
1768 rx_queue
->rx_skbuff
[i
] = NULL
;
1774 kfree(rx_queue
->rx_skbuff
);
1775 rx_queue
->rx_skbuff
= NULL
;
1778 /* If there are any tx skbs or rx skbs still around, free them.
1779 * Then free tx_skbuff and rx_skbuff
1781 static void free_skb_resources(struct gfar_private
*priv
)
1783 struct gfar_priv_tx_q
*tx_queue
= NULL
;
1784 struct gfar_priv_rx_q
*rx_queue
= NULL
;
1787 /* Go through all the buffer descriptors and free their data buffers */
1788 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
1789 struct netdev_queue
*txq
;
1791 tx_queue
= priv
->tx_queue
[i
];
1792 txq
= netdev_get_tx_queue(tx_queue
->dev
, tx_queue
->qindex
);
1793 if (tx_queue
->tx_skbuff
)
1794 free_skb_tx_queue(tx_queue
);
1795 netdev_tx_reset_queue(txq
);
1798 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
1799 rx_queue
= priv
->rx_queue
[i
];
1800 if (rx_queue
->rx_skbuff
)
1801 free_skb_rx_queue(rx_queue
);
1804 dma_free_coherent(priv
->dev
,
1805 sizeof(struct txbd8
) * priv
->total_tx_ring_size
+
1806 sizeof(struct rxbd8
) * priv
->total_rx_ring_size
,
1807 priv
->tx_queue
[0]->tx_bd_base
,
1808 priv
->tx_queue
[0]->tx_bd_dma_base
);
1811 void gfar_start(struct net_device
*dev
)
1813 struct gfar_private
*priv
= netdev_priv(dev
);
1814 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1818 /* Enable Rx and Tx in MACCFG1 */
1819 tempval
= gfar_read(®s
->maccfg1
);
1820 tempval
|= (MACCFG1_RX_EN
| MACCFG1_TX_EN
);
1821 gfar_write(®s
->maccfg1
, tempval
);
1823 /* Initialize DMACTRL to have WWR and WOP */
1824 tempval
= gfar_read(®s
->dmactrl
);
1825 tempval
|= DMACTRL_INIT_SETTINGS
;
1826 gfar_write(®s
->dmactrl
, tempval
);
1828 /* Make sure we aren't stopped */
1829 tempval
= gfar_read(®s
->dmactrl
);
1830 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
1831 gfar_write(®s
->dmactrl
, tempval
);
1833 for (i
= 0; i
< priv
->num_grps
; i
++) {
1834 regs
= priv
->gfargrp
[i
].regs
;
1835 /* Clear THLT/RHLT, so that the DMA starts polling now */
1836 gfar_write(®s
->tstat
, priv
->gfargrp
[i
].tstat
);
1837 gfar_write(®s
->rstat
, priv
->gfargrp
[i
].rstat
);
1838 /* Unmask the interrupts we look for */
1839 gfar_write(®s
->imask
, IMASK_DEFAULT
);
1842 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1845 static void gfar_configure_coalescing(struct gfar_private
*priv
,
1846 unsigned long tx_mask
, unsigned long rx_mask
)
1848 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1851 if (priv
->mode
== MQ_MG_MODE
) {
1854 baddr
= ®s
->txic0
;
1855 for_each_set_bit(i
, &tx_mask
, priv
->num_tx_queues
) {
1856 gfar_write(baddr
+ i
, 0);
1857 if (likely(priv
->tx_queue
[i
]->txcoalescing
))
1858 gfar_write(baddr
+ i
, priv
->tx_queue
[i
]->txic
);
1861 baddr
= ®s
->rxic0
;
1862 for_each_set_bit(i
, &rx_mask
, priv
->num_rx_queues
) {
1863 gfar_write(baddr
+ i
, 0);
1864 if (likely(priv
->rx_queue
[i
]->rxcoalescing
))
1865 gfar_write(baddr
+ i
, priv
->rx_queue
[i
]->rxic
);
1868 /* Backward compatible case -- even if we enable
1869 * multiple queues, there's only single reg to program
1871 gfar_write(®s
->txic
, 0);
1872 if (likely(priv
->tx_queue
[0]->txcoalescing
))
1873 gfar_write(®s
->txic
, priv
->tx_queue
[0]->txic
);
1875 gfar_write(®s
->rxic
, 0);
1876 if (unlikely(priv
->rx_queue
[0]->rxcoalescing
))
1877 gfar_write(®s
->rxic
, priv
->rx_queue
[0]->rxic
);
1881 void gfar_configure_coalescing_all(struct gfar_private
*priv
)
1883 gfar_configure_coalescing(priv
, 0xFF, 0xFF);
1886 static int register_grp_irqs(struct gfar_priv_grp
*grp
)
1888 struct gfar_private
*priv
= grp
->priv
;
1889 struct net_device
*dev
= priv
->ndev
;
1892 /* If the device has multiple interrupts, register for
1893 * them. Otherwise, only register for the one
1895 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1896 /* Install our interrupt handlers for Error,
1897 * Transmit, and Receive
1899 err
= request_irq(gfar_irq(grp
, ER
)->irq
, gfar_error
, 0,
1900 gfar_irq(grp
, ER
)->name
, grp
);
1902 netif_err(priv
, intr
, dev
, "Can't get IRQ %d\n",
1903 gfar_irq(grp
, ER
)->irq
);
1907 err
= request_irq(gfar_irq(grp
, TX
)->irq
, gfar_transmit
, 0,
1908 gfar_irq(grp
, TX
)->name
, grp
);
1910 netif_err(priv
, intr
, dev
, "Can't get IRQ %d\n",
1911 gfar_irq(grp
, TX
)->irq
);
1914 err
= request_irq(gfar_irq(grp
, RX
)->irq
, gfar_receive
, 0,
1915 gfar_irq(grp
, RX
)->name
, grp
);
1917 netif_err(priv
, intr
, dev
, "Can't get IRQ %d\n",
1918 gfar_irq(grp
, RX
)->irq
);
1922 err
= request_irq(gfar_irq(grp
, TX
)->irq
, gfar_interrupt
, 0,
1923 gfar_irq(grp
, TX
)->name
, grp
);
1925 netif_err(priv
, intr
, dev
, "Can't get IRQ %d\n",
1926 gfar_irq(grp
, TX
)->irq
);
1934 free_irq(gfar_irq(grp
, TX
)->irq
, grp
);
1936 free_irq(gfar_irq(grp
, ER
)->irq
, grp
);
1942 /* Bring the controller up and running */
1943 int startup_gfar(struct net_device
*ndev
)
1945 struct gfar_private
*priv
= netdev_priv(ndev
);
1946 struct gfar __iomem
*regs
= NULL
;
1949 for (i
= 0; i
< priv
->num_grps
; i
++) {
1950 regs
= priv
->gfargrp
[i
].regs
;
1951 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
1954 regs
= priv
->gfargrp
[0].regs
;
1955 err
= gfar_alloc_skb_resources(ndev
);
1959 gfar_init_mac(ndev
);
1961 for (i
= 0; i
< priv
->num_grps
; i
++) {
1962 err
= register_grp_irqs(&priv
->gfargrp
[i
]);
1964 for (j
= 0; j
< i
; j
++)
1965 free_grp_irqs(&priv
->gfargrp
[j
]);
1970 /* Start the controller */
1973 phy_start(priv
->phydev
);
1975 gfar_configure_coalescing_all(priv
);
1980 free_skb_resources(priv
);
1984 /* Called when something needs to use the ethernet device
1985 * Returns 0 for success.
1987 static int gfar_enet_open(struct net_device
*dev
)
1989 struct gfar_private
*priv
= netdev_priv(dev
);
1994 /* Initialize a bunch of registers */
1995 init_registers(dev
);
1997 gfar_set_mac_address(dev
);
1999 err
= init_phy(dev
);
2006 err
= startup_gfar(dev
);
2012 netif_tx_start_all_queues(dev
);
2014 device_set_wakeup_enable(&dev
->dev
, priv
->wol_en
);
2019 static inline struct txfcb
*gfar_add_fcb(struct sk_buff
*skb
)
2021 struct txfcb
*fcb
= (struct txfcb
*)skb_push(skb
, GMAC_FCB_LEN
);
2023 memset(fcb
, 0, GMAC_FCB_LEN
);
2028 static inline void gfar_tx_checksum(struct sk_buff
*skb
, struct txfcb
*fcb
,
2031 /* If we're here, it's a IP packet with a TCP or UDP
2032 * payload. We set it to checksum, using a pseudo-header
2035 u8 flags
= TXFCB_DEFAULT
;
2037 /* Tell the controller what the protocol is
2038 * And provide the already calculated phcs
2040 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
) {
2042 fcb
->phcs
= udp_hdr(skb
)->check
;
2044 fcb
->phcs
= tcp_hdr(skb
)->check
;
2046 /* l3os is the distance between the start of the
2047 * frame (skb->data) and the start of the IP hdr.
2048 * l4os is the distance between the start of the
2049 * l3 hdr and the l4 hdr
2051 fcb
->l3os
= (u16
)(skb_network_offset(skb
) - fcb_length
);
2052 fcb
->l4os
= skb_network_header_len(skb
);
2057 void inline gfar_tx_vlan(struct sk_buff
*skb
, struct txfcb
*fcb
)
2059 fcb
->flags
|= TXFCB_VLN
;
2060 fcb
->vlctl
= vlan_tx_tag_get(skb
);
2063 static inline struct txbd8
*skip_txbd(struct txbd8
*bdp
, int stride
,
2064 struct txbd8
*base
, int ring_size
)
2066 struct txbd8
*new_bd
= bdp
+ stride
;
2068 return (new_bd
>= (base
+ ring_size
)) ? (new_bd
- ring_size
) : new_bd
;
2071 static inline struct txbd8
*next_txbd(struct txbd8
*bdp
, struct txbd8
*base
,
2074 return skip_txbd(bdp
, 1, base
, ring_size
);
2077 /* eTSEC12: csum generation not supported for some fcb offsets */
2078 static inline bool gfar_csum_errata_12(struct gfar_private
*priv
,
2079 unsigned long fcb_addr
)
2081 return (gfar_has_errata(priv
, GFAR_ERRATA_12
) &&
2082 (fcb_addr
% 0x20) > 0x18);
2085 /* eTSEC76: csum generation for frames larger than 2500 may
2086 * cause excess delays before start of transmission
2088 static inline bool gfar_csum_errata_76(struct gfar_private
*priv
,
2091 return (gfar_has_errata(priv
, GFAR_ERRATA_76
) &&
2095 /* This is called by the kernel when a frame is ready for transmission.
2096 * It is pointed to by the dev->hard_start_xmit function pointer
2098 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2100 struct gfar_private
*priv
= netdev_priv(dev
);
2101 struct gfar_priv_tx_q
*tx_queue
= NULL
;
2102 struct netdev_queue
*txq
;
2103 struct gfar __iomem
*regs
= NULL
;
2104 struct txfcb
*fcb
= NULL
;
2105 struct txbd8
*txbdp
, *txbdp_start
, *base
, *txbdp_tstamp
= NULL
;
2108 int do_tstamp
, do_csum
, do_vlan
;
2110 unsigned long flags
;
2111 unsigned int nr_frags
, nr_txbds
, bytes_sent
, fcb_len
= 0;
2113 rq
= skb
->queue_mapping
;
2114 tx_queue
= priv
->tx_queue
[rq
];
2115 txq
= netdev_get_tx_queue(dev
, rq
);
2116 base
= tx_queue
->tx_bd_base
;
2117 regs
= tx_queue
->grp
->regs
;
2119 do_csum
= (CHECKSUM_PARTIAL
== skb
->ip_summed
);
2120 do_vlan
= vlan_tx_tag_present(skb
);
2121 do_tstamp
= (skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
) &&
2124 if (do_csum
|| do_vlan
)
2125 fcb_len
= GMAC_FCB_LEN
;
2127 /* check if time stamp should be generated */
2128 if (unlikely(do_tstamp
))
2129 fcb_len
= GMAC_FCB_LEN
+ GMAC_TXPAL_LEN
;
2131 /* make space for additional header when fcb is needed */
2132 if (fcb_len
&& unlikely(skb_headroom(skb
) < fcb_len
)) {
2133 struct sk_buff
*skb_new
;
2135 skb_new
= skb_realloc_headroom(skb
, fcb_len
);
2137 dev
->stats
.tx_errors
++;
2139 return NETDEV_TX_OK
;
2143 skb_set_owner_w(skb_new
, skb
->sk
);
2148 /* total number of fragments in the SKB */
2149 nr_frags
= skb_shinfo(skb
)->nr_frags
;
2151 /* calculate the required number of TxBDs for this skb */
2152 if (unlikely(do_tstamp
))
2153 nr_txbds
= nr_frags
+ 2;
2155 nr_txbds
= nr_frags
+ 1;
2157 /* check if there is space to queue this packet */
2158 if (nr_txbds
> tx_queue
->num_txbdfree
) {
2159 /* no space, stop the queue */
2160 netif_tx_stop_queue(txq
);
2161 dev
->stats
.tx_fifo_errors
++;
2162 return NETDEV_TX_BUSY
;
2165 /* Update transmit stats */
2166 bytes_sent
= skb
->len
;
2167 tx_queue
->stats
.tx_bytes
+= bytes_sent
;
2168 /* keep Tx bytes on wire for BQL accounting */
2169 GFAR_CB(skb
)->bytes_sent
= bytes_sent
;
2170 tx_queue
->stats
.tx_packets
++;
2172 txbdp
= txbdp_start
= tx_queue
->cur_tx
;
2173 lstatus
= txbdp
->lstatus
;
2175 /* Time stamp insertion requires one additional TxBD */
2176 if (unlikely(do_tstamp
))
2177 txbdp_tstamp
= txbdp
= next_txbd(txbdp
, base
,
2178 tx_queue
->tx_ring_size
);
2180 if (nr_frags
== 0) {
2181 if (unlikely(do_tstamp
))
2182 txbdp_tstamp
->lstatus
|= BD_LFLAG(TXBD_LAST
|
2185 lstatus
|= BD_LFLAG(TXBD_LAST
| TXBD_INTERRUPT
);
2187 /* Place the fragment addresses and lengths into the TxBDs */
2188 for (i
= 0; i
< nr_frags
; i
++) {
2189 unsigned int frag_len
;
2190 /* Point at the next BD, wrapping as needed */
2191 txbdp
= next_txbd(txbdp
, base
, tx_queue
->tx_ring_size
);
2193 frag_len
= skb_shinfo(skb
)->frags
[i
].size
;
2195 lstatus
= txbdp
->lstatus
| frag_len
|
2196 BD_LFLAG(TXBD_READY
);
2198 /* Handle the last BD specially */
2199 if (i
== nr_frags
- 1)
2200 lstatus
|= BD_LFLAG(TXBD_LAST
| TXBD_INTERRUPT
);
2202 bufaddr
= skb_frag_dma_map(priv
->dev
,
2203 &skb_shinfo(skb
)->frags
[i
],
2208 /* set the TxBD length and buffer pointer */
2209 txbdp
->bufPtr
= bufaddr
;
2210 txbdp
->lstatus
= lstatus
;
2213 lstatus
= txbdp_start
->lstatus
;
2216 /* Add TxPAL between FCB and frame if required */
2217 if (unlikely(do_tstamp
)) {
2218 skb_push(skb
, GMAC_TXPAL_LEN
);
2219 memset(skb
->data
, 0, GMAC_TXPAL_LEN
);
2222 /* Add TxFCB if required */
2224 fcb
= gfar_add_fcb(skb
);
2225 lstatus
|= BD_LFLAG(TXBD_TOE
);
2228 /* Set up checksumming */
2230 gfar_tx_checksum(skb
, fcb
, fcb_len
);
2232 if (unlikely(gfar_csum_errata_12(priv
, (unsigned long)fcb
)) ||
2233 unlikely(gfar_csum_errata_76(priv
, skb
->len
))) {
2234 __skb_pull(skb
, GMAC_FCB_LEN
);
2235 skb_checksum_help(skb
);
2236 if (do_vlan
|| do_tstamp
) {
2237 /* put back a new fcb for vlan/tstamp TOE */
2238 fcb
= gfar_add_fcb(skb
);
2240 /* Tx TOE not used */
2241 lstatus
&= ~(BD_LFLAG(TXBD_TOE
));
2248 gfar_tx_vlan(skb
, fcb
);
2250 /* Setup tx hardware time stamping if requested */
2251 if (unlikely(do_tstamp
)) {
2252 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
2256 txbdp_start
->bufPtr
= dma_map_single(priv
->dev
, skb
->data
,
2257 skb_headlen(skb
), DMA_TO_DEVICE
);
2259 /* If time stamping is requested one additional TxBD must be set up. The
2260 * first TxBD points to the FCB and must have a data length of
2261 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2262 * the full frame length.
2264 if (unlikely(do_tstamp
)) {
2265 txbdp_tstamp
->bufPtr
= txbdp_start
->bufPtr
+ fcb_len
;
2266 txbdp_tstamp
->lstatus
|= BD_LFLAG(TXBD_READY
) |
2267 (skb_headlen(skb
) - fcb_len
);
2268 lstatus
|= BD_LFLAG(TXBD_CRC
| TXBD_READY
) | GMAC_FCB_LEN
;
2270 lstatus
|= BD_LFLAG(TXBD_CRC
| TXBD_READY
) | skb_headlen(skb
);
2273 netdev_tx_sent_queue(txq
, bytes_sent
);
2275 /* We can work in parallel with gfar_clean_tx_ring(), except
2276 * when modifying num_txbdfree. Note that we didn't grab the lock
2277 * when we were reading the num_txbdfree and checking for available
2278 * space, that's because outside of this function it can only grow,
2279 * and once we've got needed space, it cannot suddenly disappear.
2281 * The lock also protects us from gfar_error(), which can modify
2282 * regs->tstat and thus retrigger the transfers, which is why we
2283 * also must grab the lock before setting ready bit for the first
2284 * to be transmitted BD.
2286 spin_lock_irqsave(&tx_queue
->txlock
, flags
);
2288 /* The powerpc-specific eieio() is used, as wmb() has too strong
2289 * semantics (it requires synchronization between cacheable and
2290 * uncacheable mappings, which eieio doesn't provide and which we
2291 * don't need), thus requiring a more expensive sync instruction. At
2292 * some point, the set of architecture-independent barrier functions
2293 * should be expanded to include weaker barriers.
2297 txbdp_start
->lstatus
= lstatus
;
2299 eieio(); /* force lstatus write before tx_skbuff */
2301 tx_queue
->tx_skbuff
[tx_queue
->skb_curtx
] = skb
;
2303 /* Update the current skb pointer to the next entry we will use
2304 * (wrapping if necessary)
2306 tx_queue
->skb_curtx
= (tx_queue
->skb_curtx
+ 1) &
2307 TX_RING_MOD_MASK(tx_queue
->tx_ring_size
);
2309 tx_queue
->cur_tx
= next_txbd(txbdp
, base
, tx_queue
->tx_ring_size
);
2311 /* reduce TxBD free count */
2312 tx_queue
->num_txbdfree
-= (nr_txbds
);
2314 /* If the next BD still needs to be cleaned up, then the bds
2315 * are full. We need to tell the kernel to stop sending us stuff.
2317 if (!tx_queue
->num_txbdfree
) {
2318 netif_tx_stop_queue(txq
);
2320 dev
->stats
.tx_fifo_errors
++;
2323 /* Tell the DMA to go go go */
2324 gfar_write(®s
->tstat
, TSTAT_CLEAR_THALT
>> tx_queue
->qindex
);
2327 spin_unlock_irqrestore(&tx_queue
->txlock
, flags
);
2329 return NETDEV_TX_OK
;
2332 /* Stops the kernel queue, and halts the controller */
2333 static int gfar_close(struct net_device
*dev
)
2335 struct gfar_private
*priv
= netdev_priv(dev
);
2339 cancel_work_sync(&priv
->reset_task
);
2342 /* Disconnect from the PHY */
2343 phy_disconnect(priv
->phydev
);
2344 priv
->phydev
= NULL
;
2346 netif_tx_stop_all_queues(dev
);
2351 /* Changes the mac address if the controller is not running. */
2352 static int gfar_set_mac_address(struct net_device
*dev
)
2354 gfar_set_mac_for_addr(dev
, 0, dev
->dev_addr
);
2359 /* Check if rx parser should be activated */
2360 void gfar_check_rx_parser_mode(struct gfar_private
*priv
)
2362 struct gfar __iomem
*regs
;
2365 regs
= priv
->gfargrp
[0].regs
;
2367 tempval
= gfar_read(®s
->rctrl
);
2368 /* If parse is no longer required, then disable parser */
2369 if (tempval
& RCTRL_REQ_PARSER
) {
2370 tempval
|= RCTRL_PRSDEP_INIT
;
2371 priv
->uses_rxfcb
= 1;
2373 tempval
&= ~RCTRL_PRSDEP_INIT
;
2374 priv
->uses_rxfcb
= 0;
2376 gfar_write(®s
->rctrl
, tempval
);
2379 /* Enables and disables VLAN insertion/extraction */
2380 void gfar_vlan_mode(struct net_device
*dev
, netdev_features_t features
)
2382 struct gfar_private
*priv
= netdev_priv(dev
);
2383 struct gfar __iomem
*regs
= NULL
;
2384 unsigned long flags
;
2387 regs
= priv
->gfargrp
[0].regs
;
2388 local_irq_save(flags
);
2391 if (features
& NETIF_F_HW_VLAN_CTAG_TX
) {
2392 /* Enable VLAN tag insertion */
2393 tempval
= gfar_read(®s
->tctrl
);
2394 tempval
|= TCTRL_VLINS
;
2395 gfar_write(®s
->tctrl
, tempval
);
2397 /* Disable VLAN tag insertion */
2398 tempval
= gfar_read(®s
->tctrl
);
2399 tempval
&= ~TCTRL_VLINS
;
2400 gfar_write(®s
->tctrl
, tempval
);
2403 if (features
& NETIF_F_HW_VLAN_CTAG_RX
) {
2404 /* Enable VLAN tag extraction */
2405 tempval
= gfar_read(®s
->rctrl
);
2406 tempval
|= (RCTRL_VLEX
| RCTRL_PRSDEP_INIT
);
2407 gfar_write(®s
->rctrl
, tempval
);
2408 priv
->uses_rxfcb
= 1;
2410 /* Disable VLAN tag extraction */
2411 tempval
= gfar_read(®s
->rctrl
);
2412 tempval
&= ~RCTRL_VLEX
;
2413 gfar_write(®s
->rctrl
, tempval
);
2415 gfar_check_rx_parser_mode(priv
);
2418 gfar_change_mtu(dev
, dev
->mtu
);
2421 local_irq_restore(flags
);
2424 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
)
2426 int tempsize
, tempval
;
2427 struct gfar_private
*priv
= netdev_priv(dev
);
2428 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
2429 int oldsize
= priv
->rx_buffer_size
;
2430 int frame_size
= new_mtu
+ ETH_HLEN
;
2432 if ((frame_size
< 64) || (frame_size
> JUMBO_FRAME_SIZE
)) {
2433 netif_err(priv
, drv
, dev
, "Invalid MTU setting\n");
2437 if (priv
->uses_rxfcb
)
2438 frame_size
+= GMAC_FCB_LEN
;
2440 frame_size
+= priv
->padding
;
2442 tempsize
= (frame_size
& ~(INCREMENTAL_BUFFER_SIZE
- 1)) +
2443 INCREMENTAL_BUFFER_SIZE
;
2445 /* Only stop and start the controller if it isn't already
2446 * stopped, and we changed something
2448 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
2451 priv
->rx_buffer_size
= tempsize
;
2455 gfar_write(®s
->mrblr
, priv
->rx_buffer_size
);
2456 gfar_write(®s
->maxfrm
, priv
->rx_buffer_size
);
2458 /* If the mtu is larger than the max size for standard
2459 * ethernet frames (ie, a jumbo frame), then set maccfg2
2460 * to allow huge frames, and to check the length
2462 tempval
= gfar_read(®s
->maccfg2
);
2464 if (priv
->rx_buffer_size
> DEFAULT_RX_BUFFER_SIZE
||
2465 gfar_has_errata(priv
, GFAR_ERRATA_74
))
2466 tempval
|= (MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
2468 tempval
&= ~(MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
2470 gfar_write(®s
->maccfg2
, tempval
);
2472 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
2478 /* gfar_reset_task gets scheduled when a packet has not been
2479 * transmitted after a set amount of time.
2480 * For now, assume that clearing out all the structures, and
2481 * starting over will fix the problem.
2483 static void gfar_reset_task(struct work_struct
*work
)
2485 struct gfar_private
*priv
= container_of(work
, struct gfar_private
,
2487 struct net_device
*dev
= priv
->ndev
;
2489 if (dev
->flags
& IFF_UP
) {
2490 netif_tx_stop_all_queues(dev
);
2493 netif_tx_start_all_queues(dev
);
2496 netif_tx_schedule_all(dev
);
2499 static void gfar_timeout(struct net_device
*dev
)
2501 struct gfar_private
*priv
= netdev_priv(dev
);
2503 dev
->stats
.tx_errors
++;
2504 schedule_work(&priv
->reset_task
);
2507 static void gfar_align_skb(struct sk_buff
*skb
)
2509 /* We need the data buffer to be aligned properly. We will reserve
2510 * as many bytes as needed to align the data properly
2512 skb_reserve(skb
, RXBUF_ALIGNMENT
-
2513 (((unsigned long) skb
->data
) & (RXBUF_ALIGNMENT
- 1)));
2516 /* Interrupt Handler for Transmit complete */
2517 static void gfar_clean_tx_ring(struct gfar_priv_tx_q
*tx_queue
)
2519 struct net_device
*dev
= tx_queue
->dev
;
2520 struct netdev_queue
*txq
;
2521 struct gfar_private
*priv
= netdev_priv(dev
);
2522 struct txbd8
*bdp
, *next
= NULL
;
2523 struct txbd8
*lbdp
= NULL
;
2524 struct txbd8
*base
= tx_queue
->tx_bd_base
;
2525 struct sk_buff
*skb
;
2527 int tx_ring_size
= tx_queue
->tx_ring_size
;
2528 int frags
= 0, nr_txbds
= 0;
2531 int tqi
= tx_queue
->qindex
;
2532 unsigned int bytes_sent
= 0;
2536 txq
= netdev_get_tx_queue(dev
, tqi
);
2537 bdp
= tx_queue
->dirty_tx
;
2538 skb_dirtytx
= tx_queue
->skb_dirtytx
;
2540 while ((skb
= tx_queue
->tx_skbuff
[skb_dirtytx
])) {
2541 unsigned long flags
;
2543 frags
= skb_shinfo(skb
)->nr_frags
;
2545 /* When time stamping, one additional TxBD must be freed.
2546 * Also, we need to dma_unmap_single() the TxPAL.
2548 if (unlikely(skb_shinfo(skb
)->tx_flags
& SKBTX_IN_PROGRESS
))
2549 nr_txbds
= frags
+ 2;
2551 nr_txbds
= frags
+ 1;
2553 lbdp
= skip_txbd(bdp
, nr_txbds
- 1, base
, tx_ring_size
);
2555 lstatus
= lbdp
->lstatus
;
2557 /* Only clean completed frames */
2558 if ((lstatus
& BD_LFLAG(TXBD_READY
)) &&
2559 (lstatus
& BD_LENGTH_MASK
))
2562 if (unlikely(skb_shinfo(skb
)->tx_flags
& SKBTX_IN_PROGRESS
)) {
2563 next
= next_txbd(bdp
, base
, tx_ring_size
);
2564 buflen
= next
->length
+ GMAC_FCB_LEN
+ GMAC_TXPAL_LEN
;
2566 buflen
= bdp
->length
;
2568 dma_unmap_single(priv
->dev
, bdp
->bufPtr
,
2569 buflen
, DMA_TO_DEVICE
);
2571 if (unlikely(skb_shinfo(skb
)->tx_flags
& SKBTX_IN_PROGRESS
)) {
2572 struct skb_shared_hwtstamps shhwtstamps
;
2573 u64
*ns
= (u64
*) (((u32
)skb
->data
+ 0x10) & ~0x7);
2575 memset(&shhwtstamps
, 0, sizeof(shhwtstamps
));
2576 shhwtstamps
.hwtstamp
= ns_to_ktime(*ns
);
2577 skb_pull(skb
, GMAC_FCB_LEN
+ GMAC_TXPAL_LEN
);
2578 skb_tstamp_tx(skb
, &shhwtstamps
);
2579 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
2583 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
2584 bdp
= next_txbd(bdp
, base
, tx_ring_size
);
2586 for (i
= 0; i
< frags
; i
++) {
2587 dma_unmap_page(priv
->dev
, bdp
->bufPtr
,
2588 bdp
->length
, DMA_TO_DEVICE
);
2589 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
2590 bdp
= next_txbd(bdp
, base
, tx_ring_size
);
2593 bytes_sent
+= GFAR_CB(skb
)->bytes_sent
;
2595 dev_kfree_skb_any(skb
);
2597 tx_queue
->tx_skbuff
[skb_dirtytx
] = NULL
;
2599 skb_dirtytx
= (skb_dirtytx
+ 1) &
2600 TX_RING_MOD_MASK(tx_ring_size
);
2603 spin_lock_irqsave(&tx_queue
->txlock
, flags
);
2604 tx_queue
->num_txbdfree
+= nr_txbds
;
2605 spin_unlock_irqrestore(&tx_queue
->txlock
, flags
);
2608 /* If we freed a buffer, we can restart transmission, if necessary */
2609 if (netif_tx_queue_stopped(txq
) && tx_queue
->num_txbdfree
)
2610 netif_wake_subqueue(dev
, tqi
);
2612 /* Update dirty indicators */
2613 tx_queue
->skb_dirtytx
= skb_dirtytx
;
2614 tx_queue
->dirty_tx
= bdp
;
2616 netdev_tx_completed_queue(txq
, howmany
, bytes_sent
);
2619 static void gfar_schedule_cleanup(struct gfar_priv_grp
*gfargrp
)
2621 unsigned long flags
;
2623 spin_lock_irqsave(&gfargrp
->grplock
, flags
);
2624 if (napi_schedule_prep(&gfargrp
->napi
)) {
2625 gfar_write(&gfargrp
->regs
->imask
, IMASK_RTX_DISABLED
);
2626 __napi_schedule(&gfargrp
->napi
);
2628 /* Clear IEVENT, so interrupts aren't called again
2629 * because of the packets that have already arrived.
2631 gfar_write(&gfargrp
->regs
->ievent
, IEVENT_RTX_MASK
);
2633 spin_unlock_irqrestore(&gfargrp
->grplock
, flags
);
2637 /* Interrupt Handler for Transmit complete */
2638 static irqreturn_t
gfar_transmit(int irq
, void *grp_id
)
2640 gfar_schedule_cleanup((struct gfar_priv_grp
*)grp_id
);
2644 static void gfar_new_rxbdp(struct gfar_priv_rx_q
*rx_queue
, struct rxbd8
*bdp
,
2645 struct sk_buff
*skb
)
2647 struct net_device
*dev
= rx_queue
->dev
;
2648 struct gfar_private
*priv
= netdev_priv(dev
);
2651 buf
= dma_map_single(priv
->dev
, skb
->data
,
2652 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
2653 gfar_init_rxbdp(rx_queue
, bdp
, buf
);
2656 static struct sk_buff
*gfar_alloc_skb(struct net_device
*dev
)
2658 struct gfar_private
*priv
= netdev_priv(dev
);
2659 struct sk_buff
*skb
;
2661 skb
= netdev_alloc_skb(dev
, priv
->rx_buffer_size
+ RXBUF_ALIGNMENT
);
2665 gfar_align_skb(skb
);
2670 struct sk_buff
*gfar_new_skb(struct net_device
*dev
)
2672 return gfar_alloc_skb(dev
);
2675 static inline void count_errors(unsigned short status
, struct net_device
*dev
)
2677 struct gfar_private
*priv
= netdev_priv(dev
);
2678 struct net_device_stats
*stats
= &dev
->stats
;
2679 struct gfar_extra_stats
*estats
= &priv
->extra_stats
;
2681 /* If the packet was truncated, none of the other errors matter */
2682 if (status
& RXBD_TRUNCATED
) {
2683 stats
->rx_length_errors
++;
2685 atomic64_inc(&estats
->rx_trunc
);
2689 /* Count the errors, if there were any */
2690 if (status
& (RXBD_LARGE
| RXBD_SHORT
)) {
2691 stats
->rx_length_errors
++;
2693 if (status
& RXBD_LARGE
)
2694 atomic64_inc(&estats
->rx_large
);
2696 atomic64_inc(&estats
->rx_short
);
2698 if (status
& RXBD_NONOCTET
) {
2699 stats
->rx_frame_errors
++;
2700 atomic64_inc(&estats
->rx_nonoctet
);
2702 if (status
& RXBD_CRCERR
) {
2703 atomic64_inc(&estats
->rx_crcerr
);
2704 stats
->rx_crc_errors
++;
2706 if (status
& RXBD_OVERRUN
) {
2707 atomic64_inc(&estats
->rx_overrun
);
2708 stats
->rx_crc_errors
++;
2712 irqreturn_t
gfar_receive(int irq
, void *grp_id
)
2714 gfar_schedule_cleanup((struct gfar_priv_grp
*)grp_id
);
2718 static inline void gfar_rx_checksum(struct sk_buff
*skb
, struct rxfcb
*fcb
)
2720 /* If valid headers were found, and valid sums
2721 * were verified, then we tell the kernel that no
2722 * checksumming is necessary. Otherwise, it is [FIXME]
2724 if ((fcb
->flags
& RXFCB_CSUM_MASK
) == (RXFCB_CIP
| RXFCB_CTU
))
2725 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2727 skb_checksum_none_assert(skb
);
2731 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2732 static void gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
2733 int amount_pull
, struct napi_struct
*napi
)
2735 struct gfar_private
*priv
= netdev_priv(dev
);
2736 struct rxfcb
*fcb
= NULL
;
2738 /* fcb is at the beginning if exists */
2739 fcb
= (struct rxfcb
*)skb
->data
;
2741 /* Remove the FCB from the skb
2742 * Remove the padded bytes, if there are any
2745 skb_record_rx_queue(skb
, fcb
->rq
);
2746 skb_pull(skb
, amount_pull
);
2749 /* Get receive timestamp from the skb */
2750 if (priv
->hwts_rx_en
) {
2751 struct skb_shared_hwtstamps
*shhwtstamps
= skb_hwtstamps(skb
);
2752 u64
*ns
= (u64
*) skb
->data
;
2754 memset(shhwtstamps
, 0, sizeof(*shhwtstamps
));
2755 shhwtstamps
->hwtstamp
= ns_to_ktime(*ns
);
2759 skb_pull(skb
, priv
->padding
);
2761 if (dev
->features
& NETIF_F_RXCSUM
)
2762 gfar_rx_checksum(skb
, fcb
);
2764 /* Tell the skb what kind of packet this is */
2765 skb
->protocol
= eth_type_trans(skb
, dev
);
2767 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2768 * Even if vlan rx accel is disabled, on some chips
2769 * RXFCB_VLN is pseudo randomly set.
2771 if (dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
&&
2772 fcb
->flags
& RXFCB_VLN
)
2773 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), fcb
->vlctl
);
2775 /* Send the packet up the stack */
2776 napi_gro_receive(napi
, skb
);
2780 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2781 * until the budget/quota has been reached. Returns the number
2784 int gfar_clean_rx_ring(struct gfar_priv_rx_q
*rx_queue
, int rx_work_limit
)
2786 struct net_device
*dev
= rx_queue
->dev
;
2787 struct rxbd8
*bdp
, *base
;
2788 struct sk_buff
*skb
;
2792 struct gfar_private
*priv
= netdev_priv(dev
);
2794 /* Get the first full descriptor */
2795 bdp
= rx_queue
->cur_rx
;
2796 base
= rx_queue
->rx_bd_base
;
2798 amount_pull
= priv
->uses_rxfcb
? GMAC_FCB_LEN
: 0;
2800 while (!((bdp
->status
& RXBD_EMPTY
) || (--rx_work_limit
< 0))) {
2801 struct sk_buff
*newskb
;
2805 /* Add another skb for the future */
2806 newskb
= gfar_new_skb(dev
);
2808 skb
= rx_queue
->rx_skbuff
[rx_queue
->skb_currx
];
2810 dma_unmap_single(priv
->dev
, bdp
->bufPtr
,
2811 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
2813 if (unlikely(!(bdp
->status
& RXBD_ERR
) &&
2814 bdp
->length
> priv
->rx_buffer_size
))
2815 bdp
->status
= RXBD_LARGE
;
2817 /* We drop the frame if we failed to allocate a new buffer */
2818 if (unlikely(!newskb
|| !(bdp
->status
& RXBD_LAST
) ||
2819 bdp
->status
& RXBD_ERR
)) {
2820 count_errors(bdp
->status
, dev
);
2822 if (unlikely(!newskb
))
2827 /* Increment the number of packets */
2828 rx_queue
->stats
.rx_packets
++;
2832 pkt_len
= bdp
->length
- ETH_FCS_LEN
;
2833 /* Remove the FCS from the packet length */
2834 skb_put(skb
, pkt_len
);
2835 rx_queue
->stats
.rx_bytes
+= pkt_len
;
2836 skb_record_rx_queue(skb
, rx_queue
->qindex
);
2837 gfar_process_frame(dev
, skb
, amount_pull
,
2838 &rx_queue
->grp
->napi
);
2841 netif_warn(priv
, rx_err
, dev
, "Missing skb!\n");
2842 rx_queue
->stats
.rx_dropped
++;
2843 atomic64_inc(&priv
->extra_stats
.rx_skbmissing
);
2848 rx_queue
->rx_skbuff
[rx_queue
->skb_currx
] = newskb
;
2850 /* Setup the new bdp */
2851 gfar_new_rxbdp(rx_queue
, bdp
, newskb
);
2853 /* Update to the next pointer */
2854 bdp
= next_bd(bdp
, base
, rx_queue
->rx_ring_size
);
2856 /* update to point at the next skb */
2857 rx_queue
->skb_currx
= (rx_queue
->skb_currx
+ 1) &
2858 RX_RING_MOD_MASK(rx_queue
->rx_ring_size
);
2861 /* Update the current rxbd pointer to be the next one */
2862 rx_queue
->cur_rx
= bdp
;
2867 static int gfar_poll_sq(struct napi_struct
*napi
, int budget
)
2869 struct gfar_priv_grp
*gfargrp
=
2870 container_of(napi
, struct gfar_priv_grp
, napi
);
2871 struct gfar __iomem
*regs
= gfargrp
->regs
;
2872 struct gfar_priv_tx_q
*tx_queue
= gfargrp
->priv
->tx_queue
[0];
2873 struct gfar_priv_rx_q
*rx_queue
= gfargrp
->priv
->rx_queue
[0];
2876 /* Clear IEVENT, so interrupts aren't called again
2877 * because of the packets that have already arrived
2879 gfar_write(®s
->ievent
, IEVENT_RTX_MASK
);
2881 /* run Tx cleanup to completion */
2882 if (tx_queue
->tx_skbuff
[tx_queue
->skb_dirtytx
])
2883 gfar_clean_tx_ring(tx_queue
);
2885 work_done
= gfar_clean_rx_ring(rx_queue
, budget
);
2887 if (work_done
< budget
) {
2888 napi_complete(napi
);
2889 /* Clear the halt bit in RSTAT */
2890 gfar_write(®s
->rstat
, gfargrp
->rstat
);
2892 gfar_write(®s
->imask
, IMASK_DEFAULT
);
2894 /* If we are coalescing interrupts, update the timer
2895 * Otherwise, clear it
2897 gfar_write(®s
->txic
, 0);
2898 if (likely(tx_queue
->txcoalescing
))
2899 gfar_write(®s
->txic
, tx_queue
->txic
);
2901 gfar_write(®s
->rxic
, 0);
2902 if (unlikely(rx_queue
->rxcoalescing
))
2903 gfar_write(®s
->rxic
, rx_queue
->rxic
);
2909 static int gfar_poll(struct napi_struct
*napi
, int budget
)
2911 struct gfar_priv_grp
*gfargrp
=
2912 container_of(napi
, struct gfar_priv_grp
, napi
);
2913 struct gfar_private
*priv
= gfargrp
->priv
;
2914 struct gfar __iomem
*regs
= gfargrp
->regs
;
2915 struct gfar_priv_tx_q
*tx_queue
= NULL
;
2916 struct gfar_priv_rx_q
*rx_queue
= NULL
;
2917 int work_done
= 0, work_done_per_q
= 0;
2918 int i
, budget_per_q
= 0;
2919 int has_tx_work
= 0;
2920 unsigned long rstat_rxf
;
2923 /* Clear IEVENT, so interrupts aren't called again
2924 * because of the packets that have already arrived
2926 gfar_write(®s
->ievent
, IEVENT_RTX_MASK
);
2928 rstat_rxf
= gfar_read(®s
->rstat
) & RSTAT_RXF_MASK
;
2930 num_act_queues
= bitmap_weight(&rstat_rxf
, MAX_RX_QS
);
2932 budget_per_q
= budget
/num_act_queues
;
2934 for_each_set_bit(i
, &gfargrp
->tx_bit_map
, priv
->num_tx_queues
) {
2935 tx_queue
= priv
->tx_queue
[i
];
2936 /* run Tx cleanup to completion */
2937 if (tx_queue
->tx_skbuff
[tx_queue
->skb_dirtytx
]) {
2938 gfar_clean_tx_ring(tx_queue
);
2943 for_each_set_bit(i
, &gfargrp
->rx_bit_map
, priv
->num_rx_queues
) {
2944 /* skip queue if not active */
2945 if (!(rstat_rxf
& (RSTAT_CLEAR_RXF0
>> i
)))
2948 rx_queue
= priv
->rx_queue
[i
];
2950 gfar_clean_rx_ring(rx_queue
, budget_per_q
);
2951 work_done
+= work_done_per_q
;
2953 /* finished processing this queue */
2954 if (work_done_per_q
< budget_per_q
) {
2955 /* clear active queue hw indication */
2956 gfar_write(®s
->rstat
,
2957 RSTAT_CLEAR_RXF0
>> i
);
2960 if (!num_act_queues
)
2965 if (!num_act_queues
&& !has_tx_work
) {
2967 napi_complete(napi
);
2969 /* Clear the halt bit in RSTAT */
2970 gfar_write(®s
->rstat
, gfargrp
->rstat
);
2972 gfar_write(®s
->imask
, IMASK_DEFAULT
);
2974 /* If we are coalescing interrupts, update the timer
2975 * Otherwise, clear it
2977 gfar_configure_coalescing(priv
, gfargrp
->rx_bit_map
,
2978 gfargrp
->tx_bit_map
);
2984 #ifdef CONFIG_NET_POLL_CONTROLLER
2985 /* Polling 'interrupt' - used by things like netconsole to send skbs
2986 * without having to re-enable interrupts. It's not called while
2987 * the interrupt routine is executing.
2989 static void gfar_netpoll(struct net_device
*dev
)
2991 struct gfar_private
*priv
= netdev_priv(dev
);
2994 /* If the device has multiple interrupts, run tx/rx */
2995 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
2996 for (i
= 0; i
< priv
->num_grps
; i
++) {
2997 struct gfar_priv_grp
*grp
= &priv
->gfargrp
[i
];
2999 disable_irq(gfar_irq(grp
, TX
)->irq
);
3000 disable_irq(gfar_irq(grp
, RX
)->irq
);
3001 disable_irq(gfar_irq(grp
, ER
)->irq
);
3002 gfar_interrupt(gfar_irq(grp
, TX
)->irq
, grp
);
3003 enable_irq(gfar_irq(grp
, ER
)->irq
);
3004 enable_irq(gfar_irq(grp
, RX
)->irq
);
3005 enable_irq(gfar_irq(grp
, TX
)->irq
);
3008 for (i
= 0; i
< priv
->num_grps
; i
++) {
3009 struct gfar_priv_grp
*grp
= &priv
->gfargrp
[i
];
3011 disable_irq(gfar_irq(grp
, TX
)->irq
);
3012 gfar_interrupt(gfar_irq(grp
, TX
)->irq
, grp
);
3013 enable_irq(gfar_irq(grp
, TX
)->irq
);
3019 /* The interrupt handler for devices with one interrupt */
3020 static irqreturn_t
gfar_interrupt(int irq
, void *grp_id
)
3022 struct gfar_priv_grp
*gfargrp
= grp_id
;
3024 /* Save ievent for future reference */
3025 u32 events
= gfar_read(&gfargrp
->regs
->ievent
);
3027 /* Check for reception */
3028 if (events
& IEVENT_RX_MASK
)
3029 gfar_receive(irq
, grp_id
);
3031 /* Check for transmit completion */
3032 if (events
& IEVENT_TX_MASK
)
3033 gfar_transmit(irq
, grp_id
);
3035 /* Check for errors */
3036 if (events
& IEVENT_ERR_MASK
)
3037 gfar_error(irq
, grp_id
);
3042 static u32
gfar_get_flowctrl_cfg(struct gfar_private
*priv
)
3044 struct phy_device
*phydev
= priv
->phydev
;
3047 if (!phydev
->duplex
)
3050 if (!priv
->pause_aneg_en
) {
3051 if (priv
->tx_pause_en
)
3052 val
|= MACCFG1_TX_FLOW
;
3053 if (priv
->rx_pause_en
)
3054 val
|= MACCFG1_RX_FLOW
;
3056 u16 lcl_adv
, rmt_adv
;
3058 /* get link partner capabilities */
3061 rmt_adv
= LPA_PAUSE_CAP
;
3062 if (phydev
->asym_pause
)
3063 rmt_adv
|= LPA_PAUSE_ASYM
;
3065 lcl_adv
= mii_advertise_flowctrl(phydev
->advertising
);
3067 flowctrl
= mii_resolve_flowctrl_fdx(lcl_adv
, rmt_adv
);
3068 if (flowctrl
& FLOW_CTRL_TX
)
3069 val
|= MACCFG1_TX_FLOW
;
3070 if (flowctrl
& FLOW_CTRL_RX
)
3071 val
|= MACCFG1_RX_FLOW
;
3077 /* Called every time the controller might need to be made
3078 * aware of new link state. The PHY code conveys this
3079 * information through variables in the phydev structure, and this
3080 * function converts those variables into the appropriate
3081 * register values, and can bring down the device if needed.
3083 static void adjust_link(struct net_device
*dev
)
3085 struct gfar_private
*priv
= netdev_priv(dev
);
3086 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
3087 unsigned long flags
;
3088 struct phy_device
*phydev
= priv
->phydev
;
3091 local_irq_save(flags
);
3095 u32 tempval1
= gfar_read(®s
->maccfg1
);
3096 u32 tempval
= gfar_read(®s
->maccfg2
);
3097 u32 ecntrl
= gfar_read(®s
->ecntrl
);
3099 /* Now we make sure that we can be in full duplex mode.
3100 * If not, we operate in half-duplex mode.
3102 if (phydev
->duplex
!= priv
->oldduplex
) {
3104 if (!(phydev
->duplex
))
3105 tempval
&= ~(MACCFG2_FULL_DUPLEX
);
3107 tempval
|= MACCFG2_FULL_DUPLEX
;
3109 priv
->oldduplex
= phydev
->duplex
;
3112 if (phydev
->speed
!= priv
->oldspeed
) {
3114 switch (phydev
->speed
) {
3117 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_GMII
);
3119 ecntrl
&= ~(ECNTRL_R100
);
3124 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_MII
);
3126 /* Reduced mode distinguishes
3127 * between 10 and 100
3129 if (phydev
->speed
== SPEED_100
)
3130 ecntrl
|= ECNTRL_R100
;
3132 ecntrl
&= ~(ECNTRL_R100
);
3135 netif_warn(priv
, link
, dev
,
3136 "Ack! Speed (%d) is not 10/100/1000!\n",
3141 priv
->oldspeed
= phydev
->speed
;
3144 tempval1
&= ~(MACCFG1_TX_FLOW
| MACCFG1_RX_FLOW
);
3145 tempval1
|= gfar_get_flowctrl_cfg(priv
);
3147 gfar_write(®s
->maccfg1
, tempval1
);
3148 gfar_write(®s
->maccfg2
, tempval
);
3149 gfar_write(®s
->ecntrl
, ecntrl
);
3151 if (!priv
->oldlink
) {
3155 } else if (priv
->oldlink
) {
3159 priv
->oldduplex
= -1;
3162 if (new_state
&& netif_msg_link(priv
))
3163 phy_print_status(phydev
);
3165 local_irq_restore(flags
);
3168 /* Update the hash table based on the current list of multicast
3169 * addresses we subscribe to. Also, change the promiscuity of
3170 * the device based on the flags (this function is called
3171 * whenever dev->flags is changed
3173 static void gfar_set_multi(struct net_device
*dev
)
3175 struct netdev_hw_addr
*ha
;
3176 struct gfar_private
*priv
= netdev_priv(dev
);
3177 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
3180 if (dev
->flags
& IFF_PROMISC
) {
3181 /* Set RCTRL to PROM */
3182 tempval
= gfar_read(®s
->rctrl
);
3183 tempval
|= RCTRL_PROM
;
3184 gfar_write(®s
->rctrl
, tempval
);
3186 /* Set RCTRL to not PROM */
3187 tempval
= gfar_read(®s
->rctrl
);
3188 tempval
&= ~(RCTRL_PROM
);
3189 gfar_write(®s
->rctrl
, tempval
);
3192 if (dev
->flags
& IFF_ALLMULTI
) {
3193 /* Set the hash to rx all multicast frames */
3194 gfar_write(®s
->igaddr0
, 0xffffffff);
3195 gfar_write(®s
->igaddr1
, 0xffffffff);
3196 gfar_write(®s
->igaddr2
, 0xffffffff);
3197 gfar_write(®s
->igaddr3
, 0xffffffff);
3198 gfar_write(®s
->igaddr4
, 0xffffffff);
3199 gfar_write(®s
->igaddr5
, 0xffffffff);
3200 gfar_write(®s
->igaddr6
, 0xffffffff);
3201 gfar_write(®s
->igaddr7
, 0xffffffff);
3202 gfar_write(®s
->gaddr0
, 0xffffffff);
3203 gfar_write(®s
->gaddr1
, 0xffffffff);
3204 gfar_write(®s
->gaddr2
, 0xffffffff);
3205 gfar_write(®s
->gaddr3
, 0xffffffff);
3206 gfar_write(®s
->gaddr4
, 0xffffffff);
3207 gfar_write(®s
->gaddr5
, 0xffffffff);
3208 gfar_write(®s
->gaddr6
, 0xffffffff);
3209 gfar_write(®s
->gaddr7
, 0xffffffff);
3214 /* zero out the hash */
3215 gfar_write(®s
->igaddr0
, 0x0);
3216 gfar_write(®s
->igaddr1
, 0x0);
3217 gfar_write(®s
->igaddr2
, 0x0);
3218 gfar_write(®s
->igaddr3
, 0x0);
3219 gfar_write(®s
->igaddr4
, 0x0);
3220 gfar_write(®s
->igaddr5
, 0x0);
3221 gfar_write(®s
->igaddr6
, 0x0);
3222 gfar_write(®s
->igaddr7
, 0x0);
3223 gfar_write(®s
->gaddr0
, 0x0);
3224 gfar_write(®s
->gaddr1
, 0x0);
3225 gfar_write(®s
->gaddr2
, 0x0);
3226 gfar_write(®s
->gaddr3
, 0x0);
3227 gfar_write(®s
->gaddr4
, 0x0);
3228 gfar_write(®s
->gaddr5
, 0x0);
3229 gfar_write(®s
->gaddr6
, 0x0);
3230 gfar_write(®s
->gaddr7
, 0x0);
3232 /* If we have extended hash tables, we need to
3233 * clear the exact match registers to prepare for
3236 if (priv
->extended_hash
) {
3237 em_num
= GFAR_EM_NUM
+ 1;
3238 gfar_clear_exact_match(dev
);
3245 if (netdev_mc_empty(dev
))
3248 /* Parse the list, and set the appropriate bits */
3249 netdev_for_each_mc_addr(ha
, dev
) {
3251 gfar_set_mac_for_addr(dev
, idx
, ha
->addr
);
3254 gfar_set_hash_for_addr(dev
, ha
->addr
);
3260 /* Clears each of the exact match registers to zero, so they
3261 * don't interfere with normal reception
3263 static void gfar_clear_exact_match(struct net_device
*dev
)
3266 static const u8 zero_arr
[ETH_ALEN
] = {0, 0, 0, 0, 0, 0};
3268 for (idx
= 1; idx
< GFAR_EM_NUM
+ 1; idx
++)
3269 gfar_set_mac_for_addr(dev
, idx
, zero_arr
);
3272 /* Set the appropriate hash bit for the given addr */
3273 /* The algorithm works like so:
3274 * 1) Take the Destination Address (ie the multicast address), and
3275 * do a CRC on it (little endian), and reverse the bits of the
3277 * 2) Use the 8 most significant bits as a hash into a 256-entry
3278 * table. The table is controlled through 8 32-bit registers:
3279 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3280 * gaddr7. This means that the 3 most significant bits in the
3281 * hash index which gaddr register to use, and the 5 other bits
3282 * indicate which bit (assuming an IBM numbering scheme, which
3283 * for PowerPC (tm) is usually the case) in the register holds
3286 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
)
3289 struct gfar_private
*priv
= netdev_priv(dev
);
3290 u32 result
= ether_crc(ETH_ALEN
, addr
);
3291 int width
= priv
->hash_width
;
3292 u8 whichbit
= (result
>> (32 - width
)) & 0x1f;
3293 u8 whichreg
= result
>> (32 - width
+ 5);
3294 u32 value
= (1 << (31-whichbit
));
3296 tempval
= gfar_read(priv
->hash_regs
[whichreg
]);
3298 gfar_write(priv
->hash_regs
[whichreg
], tempval
);
3302 /* There are multiple MAC Address register pairs on some controllers
3303 * This function sets the numth pair to a given address
3305 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
,
3308 struct gfar_private
*priv
= netdev_priv(dev
);
3309 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
3311 char tmpbuf
[ETH_ALEN
];
3313 u32 __iomem
*macptr
= ®s
->macstnaddr1
;
3317 /* Now copy it into the mac registers backwards, cuz
3318 * little endian is silly
3320 for (idx
= 0; idx
< ETH_ALEN
; idx
++)
3321 tmpbuf
[ETH_ALEN
- 1 - idx
] = addr
[idx
];
3323 gfar_write(macptr
, *((u32
*) (tmpbuf
)));
3325 tempval
= *((u32
*) (tmpbuf
+ 4));
3327 gfar_write(macptr
+1, tempval
);
3330 /* GFAR error interrupt handler */
3331 static irqreturn_t
gfar_error(int irq
, void *grp_id
)
3333 struct gfar_priv_grp
*gfargrp
= grp_id
;
3334 struct gfar __iomem
*regs
= gfargrp
->regs
;
3335 struct gfar_private
*priv
= gfargrp
->priv
;
3336 struct net_device
*dev
= priv
->ndev
;
3338 /* Save ievent for future reference */
3339 u32 events
= gfar_read(®s
->ievent
);
3342 gfar_write(®s
->ievent
, events
& IEVENT_ERR_MASK
);
3344 /* Magic Packet is not an error. */
3345 if ((priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
) &&
3346 (events
& IEVENT_MAG
))
3347 events
&= ~IEVENT_MAG
;
3350 if (netif_msg_rx_err(priv
) || netif_msg_tx_err(priv
))
3352 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3353 events
, gfar_read(®s
->imask
));
3355 /* Update the error counters */
3356 if (events
& IEVENT_TXE
) {
3357 dev
->stats
.tx_errors
++;
3359 if (events
& IEVENT_LC
)
3360 dev
->stats
.tx_window_errors
++;
3361 if (events
& IEVENT_CRL
)
3362 dev
->stats
.tx_aborted_errors
++;
3363 if (events
& IEVENT_XFUN
) {
3364 unsigned long flags
;
3366 netif_dbg(priv
, tx_err
, dev
,
3367 "TX FIFO underrun, packet dropped\n");
3368 dev
->stats
.tx_dropped
++;
3369 atomic64_inc(&priv
->extra_stats
.tx_underrun
);
3371 local_irq_save(flags
);
3374 /* Reactivate the Tx Queues */
3375 gfar_write(®s
->tstat
, gfargrp
->tstat
);
3378 local_irq_restore(flags
);
3380 netif_dbg(priv
, tx_err
, dev
, "Transmit Error\n");
3382 if (events
& IEVENT_BSY
) {
3383 dev
->stats
.rx_errors
++;
3384 atomic64_inc(&priv
->extra_stats
.rx_bsy
);
3386 gfar_receive(irq
, grp_id
);
3388 netif_dbg(priv
, rx_err
, dev
, "busy error (rstat: %x)\n",
3389 gfar_read(®s
->rstat
));
3391 if (events
& IEVENT_BABR
) {
3392 dev
->stats
.rx_errors
++;
3393 atomic64_inc(&priv
->extra_stats
.rx_babr
);
3395 netif_dbg(priv
, rx_err
, dev
, "babbling RX error\n");
3397 if (events
& IEVENT_EBERR
) {
3398 atomic64_inc(&priv
->extra_stats
.eberr
);
3399 netif_dbg(priv
, rx_err
, dev
, "bus error\n");
3401 if (events
& IEVENT_RXC
)
3402 netif_dbg(priv
, rx_status
, dev
, "control frame\n");
3404 if (events
& IEVENT_BABT
) {
3405 atomic64_inc(&priv
->extra_stats
.tx_babt
);
3406 netif_dbg(priv
, tx_err
, dev
, "babbling TX error\n");
3411 static struct of_device_id gfar_match
[] =
3415 .compatible
= "gianfar",
3418 .compatible
= "fsl,etsec2",
3422 MODULE_DEVICE_TABLE(of
, gfar_match
);
3424 /* Structure for a device driver */
3425 static struct platform_driver gfar_driver
= {
3427 .name
= "fsl-gianfar",
3428 .owner
= THIS_MODULE
,
3430 .of_match_table
= gfar_match
,
3432 .probe
= gfar_probe
,
3433 .remove
= gfar_remove
,
3436 module_platform_driver(gfar_driver
);