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[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / hisilicon / hix5hd2_gmac.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Copyright (c) 2014 Linaro Ltd.
3 * Copyright (c) 2014 Hisilicon Limited.
4 */
5
6 #include <linux/module.h>
7 #include <linux/interrupt.h>
8 #include <linux/etherdevice.h>
9 #include <linux/platform_device.h>
10 #include <linux/of_device.h>
11 #include <linux/of_net.h>
12 #include <linux/of_mdio.h>
13 #include <linux/reset.h>
14 #include <linux/clk.h>
15 #include <linux/circ_buf.h>
16
17 #define STATION_ADDR_LOW 0x0000
18 #define STATION_ADDR_HIGH 0x0004
19 #define MAC_DUPLEX_HALF_CTRL 0x0008
20 #define MAX_FRM_SIZE 0x003c
21 #define PORT_MODE 0x0040
22 #define PORT_EN 0x0044
23 #define BITS_TX_EN BIT(2)
24 #define BITS_RX_EN BIT(1)
25 #define REC_FILT_CONTROL 0x0064
26 #define BIT_CRC_ERR_PASS BIT(5)
27 #define BIT_PAUSE_FRM_PASS BIT(4)
28 #define BIT_VLAN_DROP_EN BIT(3)
29 #define BIT_BC_DROP_EN BIT(2)
30 #define BIT_MC_MATCH_EN BIT(1)
31 #define BIT_UC_MATCH_EN BIT(0)
32 #define PORT_MC_ADDR_LOW 0x0068
33 #define PORT_MC_ADDR_HIGH 0x006C
34 #define CF_CRC_STRIP 0x01b0
35 #define MODE_CHANGE_EN 0x01b4
36 #define BIT_MODE_CHANGE_EN BIT(0)
37 #define COL_SLOT_TIME 0x01c0
38 #define RECV_CONTROL 0x01e0
39 #define BIT_STRIP_PAD_EN BIT(3)
40 #define BIT_RUNT_PKT_EN BIT(4)
41 #define CONTROL_WORD 0x0214
42 #define MDIO_SINGLE_CMD 0x03c0
43 #define MDIO_SINGLE_DATA 0x03c4
44 #define MDIO_CTRL 0x03cc
45 #define MDIO_RDATA_STATUS 0x03d0
46
47 #define MDIO_START BIT(20)
48 #define MDIO_R_VALID BIT(0)
49 #define MDIO_READ (BIT(17) | MDIO_START)
50 #define MDIO_WRITE (BIT(16) | MDIO_START)
51
52 #define RX_FQ_START_ADDR 0x0500
53 #define RX_FQ_DEPTH 0x0504
54 #define RX_FQ_WR_ADDR 0x0508
55 #define RX_FQ_RD_ADDR 0x050c
56 #define RX_FQ_VLDDESC_CNT 0x0510
57 #define RX_FQ_ALEMPTY_TH 0x0514
58 #define RX_FQ_REG_EN 0x0518
59 #define BITS_RX_FQ_START_ADDR_EN BIT(2)
60 #define BITS_RX_FQ_DEPTH_EN BIT(1)
61 #define BITS_RX_FQ_RD_ADDR_EN BIT(0)
62 #define RX_FQ_ALFULL_TH 0x051c
63 #define RX_BQ_START_ADDR 0x0520
64 #define RX_BQ_DEPTH 0x0524
65 #define RX_BQ_WR_ADDR 0x0528
66 #define RX_BQ_RD_ADDR 0x052c
67 #define RX_BQ_FREE_DESC_CNT 0x0530
68 #define RX_BQ_ALEMPTY_TH 0x0534
69 #define RX_BQ_REG_EN 0x0538
70 #define BITS_RX_BQ_START_ADDR_EN BIT(2)
71 #define BITS_RX_BQ_DEPTH_EN BIT(1)
72 #define BITS_RX_BQ_WR_ADDR_EN BIT(0)
73 #define RX_BQ_ALFULL_TH 0x053c
74 #define TX_BQ_START_ADDR 0x0580
75 #define TX_BQ_DEPTH 0x0584
76 #define TX_BQ_WR_ADDR 0x0588
77 #define TX_BQ_RD_ADDR 0x058c
78 #define TX_BQ_VLDDESC_CNT 0x0590
79 #define TX_BQ_ALEMPTY_TH 0x0594
80 #define TX_BQ_REG_EN 0x0598
81 #define BITS_TX_BQ_START_ADDR_EN BIT(2)
82 #define BITS_TX_BQ_DEPTH_EN BIT(1)
83 #define BITS_TX_BQ_RD_ADDR_EN BIT(0)
84 #define TX_BQ_ALFULL_TH 0x059c
85 #define TX_RQ_START_ADDR 0x05a0
86 #define TX_RQ_DEPTH 0x05a4
87 #define TX_RQ_WR_ADDR 0x05a8
88 #define TX_RQ_RD_ADDR 0x05ac
89 #define TX_RQ_FREE_DESC_CNT 0x05b0
90 #define TX_RQ_ALEMPTY_TH 0x05b4
91 #define TX_RQ_REG_EN 0x05b8
92 #define BITS_TX_RQ_START_ADDR_EN BIT(2)
93 #define BITS_TX_RQ_DEPTH_EN BIT(1)
94 #define BITS_TX_RQ_WR_ADDR_EN BIT(0)
95 #define TX_RQ_ALFULL_TH 0x05bc
96 #define RAW_PMU_INT 0x05c0
97 #define ENA_PMU_INT 0x05c4
98 #define STATUS_PMU_INT 0x05c8
99 #define MAC_FIFO_ERR_IN BIT(30)
100 #define TX_RQ_IN_TIMEOUT_INT BIT(29)
101 #define RX_BQ_IN_TIMEOUT_INT BIT(28)
102 #define TXOUTCFF_FULL_INT BIT(27)
103 #define TXOUTCFF_EMPTY_INT BIT(26)
104 #define TXCFF_FULL_INT BIT(25)
105 #define TXCFF_EMPTY_INT BIT(24)
106 #define RXOUTCFF_FULL_INT BIT(23)
107 #define RXOUTCFF_EMPTY_INT BIT(22)
108 #define RXCFF_FULL_INT BIT(21)
109 #define RXCFF_EMPTY_INT BIT(20)
110 #define TX_RQ_IN_INT BIT(19)
111 #define TX_BQ_OUT_INT BIT(18)
112 #define RX_BQ_IN_INT BIT(17)
113 #define RX_FQ_OUT_INT BIT(16)
114 #define TX_RQ_EMPTY_INT BIT(15)
115 #define TX_RQ_FULL_INT BIT(14)
116 #define TX_RQ_ALEMPTY_INT BIT(13)
117 #define TX_RQ_ALFULL_INT BIT(12)
118 #define TX_BQ_EMPTY_INT BIT(11)
119 #define TX_BQ_FULL_INT BIT(10)
120 #define TX_BQ_ALEMPTY_INT BIT(9)
121 #define TX_BQ_ALFULL_INT BIT(8)
122 #define RX_BQ_EMPTY_INT BIT(7)
123 #define RX_BQ_FULL_INT BIT(6)
124 #define RX_BQ_ALEMPTY_INT BIT(5)
125 #define RX_BQ_ALFULL_INT BIT(4)
126 #define RX_FQ_EMPTY_INT BIT(3)
127 #define RX_FQ_FULL_INT BIT(2)
128 #define RX_FQ_ALEMPTY_INT BIT(1)
129 #define RX_FQ_ALFULL_INT BIT(0)
130
131 #define DEF_INT_MASK (RX_BQ_IN_INT | RX_BQ_IN_TIMEOUT_INT | \
132 TX_RQ_IN_INT | TX_RQ_IN_TIMEOUT_INT)
133
134 #define DESC_WR_RD_ENA 0x05cc
135 #define IN_QUEUE_TH 0x05d8
136 #define OUT_QUEUE_TH 0x05dc
137 #define QUEUE_TX_BQ_SHIFT 16
138 #define RX_BQ_IN_TIMEOUT_TH 0x05e0
139 #define TX_RQ_IN_TIMEOUT_TH 0x05e4
140 #define STOP_CMD 0x05e8
141 #define BITS_TX_STOP BIT(1)
142 #define BITS_RX_STOP BIT(0)
143 #define FLUSH_CMD 0x05eC
144 #define BITS_TX_FLUSH_CMD BIT(5)
145 #define BITS_RX_FLUSH_CMD BIT(4)
146 #define BITS_TX_FLUSH_FLAG_DOWN BIT(3)
147 #define BITS_TX_FLUSH_FLAG_UP BIT(2)
148 #define BITS_RX_FLUSH_FLAG_DOWN BIT(1)
149 #define BITS_RX_FLUSH_FLAG_UP BIT(0)
150 #define RX_CFF_NUM_REG 0x05f0
151 #define PMU_FSM_REG 0x05f8
152 #define RX_FIFO_PKT_IN_NUM 0x05fc
153 #define RX_FIFO_PKT_OUT_NUM 0x0600
154
155 #define RGMII_SPEED_1000 0x2c
156 #define RGMII_SPEED_100 0x2f
157 #define RGMII_SPEED_10 0x2d
158 #define MII_SPEED_100 0x0f
159 #define MII_SPEED_10 0x0d
160 #define GMAC_SPEED_1000 0x05
161 #define GMAC_SPEED_100 0x01
162 #define GMAC_SPEED_10 0x00
163 #define GMAC_FULL_DUPLEX BIT(4)
164
165 #define RX_BQ_INT_THRESHOLD 0x01
166 #define TX_RQ_INT_THRESHOLD 0x01
167 #define RX_BQ_IN_TIMEOUT 0x10000
168 #define TX_RQ_IN_TIMEOUT 0x50000
169
170 #define MAC_MAX_FRAME_SIZE 1600
171 #define DESC_SIZE 32
172 #define RX_DESC_NUM 1024
173 #define TX_DESC_NUM 1024
174
175 #define DESC_VLD_FREE 0
176 #define DESC_VLD_BUSY 0x80000000
177 #define DESC_FL_MID 0
178 #define DESC_FL_LAST 0x20000000
179 #define DESC_FL_FIRST 0x40000000
180 #define DESC_FL_FULL 0x60000000
181 #define DESC_DATA_LEN_OFF 16
182 #define DESC_BUFF_LEN_OFF 0
183 #define DESC_DATA_MASK 0x7ff
184 #define DESC_SG BIT(30)
185 #define DESC_FRAGS_NUM_OFF 11
186
187 /* DMA descriptor ring helpers */
188 #define dma_ring_incr(n, s) (((n) + 1) & ((s) - 1))
189 #define dma_cnt(n) ((n) >> 5)
190 #define dma_byte(n) ((n) << 5)
191
192 #define HW_CAP_TSO BIT(0)
193 #define GEMAC_V1 0
194 #define GEMAC_V2 (GEMAC_V1 | HW_CAP_TSO)
195 #define HAS_CAP_TSO(hw_cap) ((hw_cap) & HW_CAP_TSO)
196
197 #define PHY_RESET_DELAYS_PROPERTY "hisilicon,phy-reset-delays-us"
198
199 enum phy_reset_delays {
200 PRE_DELAY,
201 PULSE,
202 POST_DELAY,
203 DELAYS_NUM,
204 };
205
206 struct hix5hd2_desc {
207 __le32 buff_addr;
208 __le32 cmd;
209 } __aligned(32);
210
211 struct hix5hd2_desc_sw {
212 struct hix5hd2_desc *desc;
213 dma_addr_t phys_addr;
214 unsigned int count;
215 unsigned int size;
216 };
217
218 struct hix5hd2_sg_desc_ring {
219 struct sg_desc *desc;
220 dma_addr_t phys_addr;
221 };
222
223 struct frags_info {
224 __le32 addr;
225 __le32 size;
226 };
227
228 /* hardware supported max skb frags num */
229 #define SG_MAX_SKB_FRAGS 17
230 struct sg_desc {
231 __le32 total_len;
232 __le32 resvd0;
233 __le32 linear_addr;
234 __le32 linear_len;
235 /* reserve one more frags for memory alignment */
236 struct frags_info frags[SG_MAX_SKB_FRAGS + 1];
237 };
238
239 #define QUEUE_NUMS 4
240 struct hix5hd2_priv {
241 struct hix5hd2_desc_sw pool[QUEUE_NUMS];
242 #define rx_fq pool[0]
243 #define rx_bq pool[1]
244 #define tx_bq pool[2]
245 #define tx_rq pool[3]
246 struct hix5hd2_sg_desc_ring tx_ring;
247
248 void __iomem *base;
249 void __iomem *ctrl_base;
250
251 struct sk_buff *tx_skb[TX_DESC_NUM];
252 struct sk_buff *rx_skb[RX_DESC_NUM];
253
254 struct device *dev;
255 struct net_device *netdev;
256
257 struct device_node *phy_node;
258 phy_interface_t phy_mode;
259
260 unsigned long hw_cap;
261 unsigned int speed;
262 unsigned int duplex;
263
264 struct clk *mac_core_clk;
265 struct clk *mac_ifc_clk;
266 struct reset_control *mac_core_rst;
267 struct reset_control *mac_ifc_rst;
268 struct reset_control *phy_rst;
269 u32 phy_reset_delays[DELAYS_NUM];
270 struct mii_bus *bus;
271 struct napi_struct napi;
272 struct work_struct tx_timeout_task;
273 };
274
275 static inline void hix5hd2_mac_interface_reset(struct hix5hd2_priv *priv)
276 {
277 if (!priv->mac_ifc_rst)
278 return;
279
280 reset_control_assert(priv->mac_ifc_rst);
281 reset_control_deassert(priv->mac_ifc_rst);
282 }
283
284 static void hix5hd2_config_port(struct net_device *dev, u32 speed, u32 duplex)
285 {
286 struct hix5hd2_priv *priv = netdev_priv(dev);
287 u32 val;
288
289 priv->speed = speed;
290 priv->duplex = duplex;
291
292 switch (priv->phy_mode) {
293 case PHY_INTERFACE_MODE_RGMII:
294 if (speed == SPEED_1000)
295 val = RGMII_SPEED_1000;
296 else if (speed == SPEED_100)
297 val = RGMII_SPEED_100;
298 else
299 val = RGMII_SPEED_10;
300 break;
301 case PHY_INTERFACE_MODE_MII:
302 if (speed == SPEED_100)
303 val = MII_SPEED_100;
304 else
305 val = MII_SPEED_10;
306 break;
307 default:
308 netdev_warn(dev, "not supported mode\n");
309 val = MII_SPEED_10;
310 break;
311 }
312
313 if (duplex)
314 val |= GMAC_FULL_DUPLEX;
315 writel_relaxed(val, priv->ctrl_base);
316 hix5hd2_mac_interface_reset(priv);
317
318 writel_relaxed(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN);
319 if (speed == SPEED_1000)
320 val = GMAC_SPEED_1000;
321 else if (speed == SPEED_100)
322 val = GMAC_SPEED_100;
323 else
324 val = GMAC_SPEED_10;
325 writel_relaxed(val, priv->base + PORT_MODE);
326 writel_relaxed(0, priv->base + MODE_CHANGE_EN);
327 writel_relaxed(duplex, priv->base + MAC_DUPLEX_HALF_CTRL);
328 }
329
330 static void hix5hd2_set_desc_depth(struct hix5hd2_priv *priv, int rx, int tx)
331 {
332 writel_relaxed(BITS_RX_FQ_DEPTH_EN, priv->base + RX_FQ_REG_EN);
333 writel_relaxed(rx << 3, priv->base + RX_FQ_DEPTH);
334 writel_relaxed(0, priv->base + RX_FQ_REG_EN);
335
336 writel_relaxed(BITS_RX_BQ_DEPTH_EN, priv->base + RX_BQ_REG_EN);
337 writel_relaxed(rx << 3, priv->base + RX_BQ_DEPTH);
338 writel_relaxed(0, priv->base + RX_BQ_REG_EN);
339
340 writel_relaxed(BITS_TX_BQ_DEPTH_EN, priv->base + TX_BQ_REG_EN);
341 writel_relaxed(tx << 3, priv->base + TX_BQ_DEPTH);
342 writel_relaxed(0, priv->base + TX_BQ_REG_EN);
343
344 writel_relaxed(BITS_TX_RQ_DEPTH_EN, priv->base + TX_RQ_REG_EN);
345 writel_relaxed(tx << 3, priv->base + TX_RQ_DEPTH);
346 writel_relaxed(0, priv->base + TX_RQ_REG_EN);
347 }
348
349 static void hix5hd2_set_rx_fq(struct hix5hd2_priv *priv, dma_addr_t phy_addr)
350 {
351 writel_relaxed(BITS_RX_FQ_START_ADDR_EN, priv->base + RX_FQ_REG_EN);
352 writel_relaxed(phy_addr, priv->base + RX_FQ_START_ADDR);
353 writel_relaxed(0, priv->base + RX_FQ_REG_EN);
354 }
355
356 static void hix5hd2_set_rx_bq(struct hix5hd2_priv *priv, dma_addr_t phy_addr)
357 {
358 writel_relaxed(BITS_RX_BQ_START_ADDR_EN, priv->base + RX_BQ_REG_EN);
359 writel_relaxed(phy_addr, priv->base + RX_BQ_START_ADDR);
360 writel_relaxed(0, priv->base + RX_BQ_REG_EN);
361 }
362
363 static void hix5hd2_set_tx_bq(struct hix5hd2_priv *priv, dma_addr_t phy_addr)
364 {
365 writel_relaxed(BITS_TX_BQ_START_ADDR_EN, priv->base + TX_BQ_REG_EN);
366 writel_relaxed(phy_addr, priv->base + TX_BQ_START_ADDR);
367 writel_relaxed(0, priv->base + TX_BQ_REG_EN);
368 }
369
370 static void hix5hd2_set_tx_rq(struct hix5hd2_priv *priv, dma_addr_t phy_addr)
371 {
372 writel_relaxed(BITS_TX_RQ_START_ADDR_EN, priv->base + TX_RQ_REG_EN);
373 writel_relaxed(phy_addr, priv->base + TX_RQ_START_ADDR);
374 writel_relaxed(0, priv->base + TX_RQ_REG_EN);
375 }
376
377 static void hix5hd2_set_desc_addr(struct hix5hd2_priv *priv)
378 {
379 hix5hd2_set_rx_fq(priv, priv->rx_fq.phys_addr);
380 hix5hd2_set_rx_bq(priv, priv->rx_bq.phys_addr);
381 hix5hd2_set_tx_rq(priv, priv->tx_rq.phys_addr);
382 hix5hd2_set_tx_bq(priv, priv->tx_bq.phys_addr);
383 }
384
385 static void hix5hd2_hw_init(struct hix5hd2_priv *priv)
386 {
387 u32 val;
388
389 /* disable and clear all interrupts */
390 writel_relaxed(0, priv->base + ENA_PMU_INT);
391 writel_relaxed(~0, priv->base + RAW_PMU_INT);
392
393 writel_relaxed(BIT_CRC_ERR_PASS, priv->base + REC_FILT_CONTROL);
394 writel_relaxed(MAC_MAX_FRAME_SIZE, priv->base + CONTROL_WORD);
395 writel_relaxed(0, priv->base + COL_SLOT_TIME);
396
397 val = RX_BQ_INT_THRESHOLD | TX_RQ_INT_THRESHOLD << QUEUE_TX_BQ_SHIFT;
398 writel_relaxed(val, priv->base + IN_QUEUE_TH);
399
400 writel_relaxed(RX_BQ_IN_TIMEOUT, priv->base + RX_BQ_IN_TIMEOUT_TH);
401 writel_relaxed(TX_RQ_IN_TIMEOUT, priv->base + TX_RQ_IN_TIMEOUT_TH);
402
403 hix5hd2_set_desc_depth(priv, RX_DESC_NUM, TX_DESC_NUM);
404 hix5hd2_set_desc_addr(priv);
405 }
406
407 static void hix5hd2_irq_enable(struct hix5hd2_priv *priv)
408 {
409 writel_relaxed(DEF_INT_MASK, priv->base + ENA_PMU_INT);
410 }
411
412 static void hix5hd2_irq_disable(struct hix5hd2_priv *priv)
413 {
414 writel_relaxed(0, priv->base + ENA_PMU_INT);
415 }
416
417 static void hix5hd2_port_enable(struct hix5hd2_priv *priv)
418 {
419 writel_relaxed(0xf, priv->base + DESC_WR_RD_ENA);
420 writel_relaxed(BITS_RX_EN | BITS_TX_EN, priv->base + PORT_EN);
421 }
422
423 static void hix5hd2_port_disable(struct hix5hd2_priv *priv)
424 {
425 writel_relaxed(~(u32)(BITS_RX_EN | BITS_TX_EN), priv->base + PORT_EN);
426 writel_relaxed(0, priv->base + DESC_WR_RD_ENA);
427 }
428
429 static void hix5hd2_hw_set_mac_addr(struct net_device *dev)
430 {
431 struct hix5hd2_priv *priv = netdev_priv(dev);
432 unsigned char *mac = dev->dev_addr;
433 u32 val;
434
435 val = mac[1] | (mac[0] << 8);
436 writel_relaxed(val, priv->base + STATION_ADDR_HIGH);
437
438 val = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24);
439 writel_relaxed(val, priv->base + STATION_ADDR_LOW);
440 }
441
442 static int hix5hd2_net_set_mac_address(struct net_device *dev, void *p)
443 {
444 int ret;
445
446 ret = eth_mac_addr(dev, p);
447 if (!ret)
448 hix5hd2_hw_set_mac_addr(dev);
449
450 return ret;
451 }
452
453 static void hix5hd2_adjust_link(struct net_device *dev)
454 {
455 struct hix5hd2_priv *priv = netdev_priv(dev);
456 struct phy_device *phy = dev->phydev;
457
458 if ((priv->speed != phy->speed) || (priv->duplex != phy->duplex)) {
459 hix5hd2_config_port(dev, phy->speed, phy->duplex);
460 phy_print_status(phy);
461 }
462 }
463
464 static void hix5hd2_rx_refill(struct hix5hd2_priv *priv)
465 {
466 struct hix5hd2_desc *desc;
467 struct sk_buff *skb;
468 u32 start, end, num, pos, i;
469 u32 len = MAC_MAX_FRAME_SIZE;
470 dma_addr_t addr;
471
472 /* software write pointer */
473 start = dma_cnt(readl_relaxed(priv->base + RX_FQ_WR_ADDR));
474 /* logic read pointer */
475 end = dma_cnt(readl_relaxed(priv->base + RX_FQ_RD_ADDR));
476 num = CIRC_SPACE(start, end, RX_DESC_NUM);
477
478 for (i = 0, pos = start; i < num; i++) {
479 if (priv->rx_skb[pos]) {
480 break;
481 } else {
482 skb = netdev_alloc_skb_ip_align(priv->netdev, len);
483 if (unlikely(skb == NULL))
484 break;
485 }
486
487 addr = dma_map_single(priv->dev, skb->data, len, DMA_FROM_DEVICE);
488 if (dma_mapping_error(priv->dev, addr)) {
489 dev_kfree_skb_any(skb);
490 break;
491 }
492
493 desc = priv->rx_fq.desc + pos;
494 desc->buff_addr = cpu_to_le32(addr);
495 priv->rx_skb[pos] = skb;
496 desc->cmd = cpu_to_le32(DESC_VLD_FREE |
497 (len - 1) << DESC_BUFF_LEN_OFF);
498 pos = dma_ring_incr(pos, RX_DESC_NUM);
499 }
500
501 /* ensure desc updated */
502 wmb();
503
504 if (pos != start)
505 writel_relaxed(dma_byte(pos), priv->base + RX_FQ_WR_ADDR);
506 }
507
508 static int hix5hd2_rx(struct net_device *dev, int limit)
509 {
510 struct hix5hd2_priv *priv = netdev_priv(dev);
511 struct sk_buff *skb;
512 struct hix5hd2_desc *desc;
513 dma_addr_t addr;
514 u32 start, end, num, pos, i, len;
515
516 /* software read pointer */
517 start = dma_cnt(readl_relaxed(priv->base + RX_BQ_RD_ADDR));
518 /* logic write pointer */
519 end = dma_cnt(readl_relaxed(priv->base + RX_BQ_WR_ADDR));
520 num = CIRC_CNT(end, start, RX_DESC_NUM);
521 if (num > limit)
522 num = limit;
523
524 /* ensure get updated desc */
525 rmb();
526 for (i = 0, pos = start; i < num; i++) {
527 skb = priv->rx_skb[pos];
528 if (unlikely(!skb)) {
529 netdev_err(dev, "inconsistent rx_skb\n");
530 break;
531 }
532 priv->rx_skb[pos] = NULL;
533
534 desc = priv->rx_bq.desc + pos;
535 len = (le32_to_cpu(desc->cmd) >> DESC_DATA_LEN_OFF) &
536 DESC_DATA_MASK;
537 addr = le32_to_cpu(desc->buff_addr);
538 dma_unmap_single(priv->dev, addr, MAC_MAX_FRAME_SIZE,
539 DMA_FROM_DEVICE);
540
541 skb_put(skb, len);
542 if (skb->len > MAC_MAX_FRAME_SIZE) {
543 netdev_err(dev, "rcv len err, len = %d\n", skb->len);
544 dev->stats.rx_errors++;
545 dev->stats.rx_length_errors++;
546 dev_kfree_skb_any(skb);
547 goto next;
548 }
549
550 skb->protocol = eth_type_trans(skb, dev);
551 napi_gro_receive(&priv->napi, skb);
552 dev->stats.rx_packets++;
553 dev->stats.rx_bytes += skb->len;
554 next:
555 pos = dma_ring_incr(pos, RX_DESC_NUM);
556 }
557
558 if (pos != start)
559 writel_relaxed(dma_byte(pos), priv->base + RX_BQ_RD_ADDR);
560
561 hix5hd2_rx_refill(priv);
562
563 return num;
564 }
565
566 static void hix5hd2_clean_sg_desc(struct hix5hd2_priv *priv,
567 struct sk_buff *skb, u32 pos)
568 {
569 struct sg_desc *desc;
570 dma_addr_t addr;
571 u32 len;
572 int i;
573
574 desc = priv->tx_ring.desc + pos;
575
576 addr = le32_to_cpu(desc->linear_addr);
577 len = le32_to_cpu(desc->linear_len);
578 dma_unmap_single(priv->dev, addr, len, DMA_TO_DEVICE);
579
580 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
581 addr = le32_to_cpu(desc->frags[i].addr);
582 len = le32_to_cpu(desc->frags[i].size);
583 dma_unmap_page(priv->dev, addr, len, DMA_TO_DEVICE);
584 }
585 }
586
587 static void hix5hd2_xmit_reclaim(struct net_device *dev)
588 {
589 struct sk_buff *skb;
590 struct hix5hd2_desc *desc;
591 struct hix5hd2_priv *priv = netdev_priv(dev);
592 unsigned int bytes_compl = 0, pkts_compl = 0;
593 u32 start, end, num, pos, i;
594 dma_addr_t addr;
595
596 netif_tx_lock(dev);
597
598 /* software read */
599 start = dma_cnt(readl_relaxed(priv->base + TX_RQ_RD_ADDR));
600 /* logic write */
601 end = dma_cnt(readl_relaxed(priv->base + TX_RQ_WR_ADDR));
602 num = CIRC_CNT(end, start, TX_DESC_NUM);
603
604 for (i = 0, pos = start; i < num; i++) {
605 skb = priv->tx_skb[pos];
606 if (unlikely(!skb)) {
607 netdev_err(dev, "inconsistent tx_skb\n");
608 break;
609 }
610
611 pkts_compl++;
612 bytes_compl += skb->len;
613 desc = priv->tx_rq.desc + pos;
614
615 if (skb_shinfo(skb)->nr_frags) {
616 hix5hd2_clean_sg_desc(priv, skb, pos);
617 } else {
618 addr = le32_to_cpu(desc->buff_addr);
619 dma_unmap_single(priv->dev, addr, skb->len,
620 DMA_TO_DEVICE);
621 }
622
623 priv->tx_skb[pos] = NULL;
624 dev_consume_skb_any(skb);
625 pos = dma_ring_incr(pos, TX_DESC_NUM);
626 }
627
628 if (pos != start)
629 writel_relaxed(dma_byte(pos), priv->base + TX_RQ_RD_ADDR);
630
631 netif_tx_unlock(dev);
632
633 if (pkts_compl || bytes_compl)
634 netdev_completed_queue(dev, pkts_compl, bytes_compl);
635
636 if (unlikely(netif_queue_stopped(priv->netdev)) && pkts_compl)
637 netif_wake_queue(priv->netdev);
638 }
639
640 static int hix5hd2_poll(struct napi_struct *napi, int budget)
641 {
642 struct hix5hd2_priv *priv = container_of(napi,
643 struct hix5hd2_priv, napi);
644 struct net_device *dev = priv->netdev;
645 int work_done = 0, task = budget;
646 int ints, num;
647
648 do {
649 hix5hd2_xmit_reclaim(dev);
650 num = hix5hd2_rx(dev, task);
651 work_done += num;
652 task -= num;
653 if ((work_done >= budget) || (num == 0))
654 break;
655
656 ints = readl_relaxed(priv->base + RAW_PMU_INT);
657 writel_relaxed(ints, priv->base + RAW_PMU_INT);
658 } while (ints & DEF_INT_MASK);
659
660 if (work_done < budget) {
661 napi_complete_done(napi, work_done);
662 hix5hd2_irq_enable(priv);
663 }
664
665 return work_done;
666 }
667
668 static irqreturn_t hix5hd2_interrupt(int irq, void *dev_id)
669 {
670 struct net_device *dev = (struct net_device *)dev_id;
671 struct hix5hd2_priv *priv = netdev_priv(dev);
672 int ints = readl_relaxed(priv->base + RAW_PMU_INT);
673
674 writel_relaxed(ints, priv->base + RAW_PMU_INT);
675 if (likely(ints & DEF_INT_MASK)) {
676 hix5hd2_irq_disable(priv);
677 napi_schedule(&priv->napi);
678 }
679
680 return IRQ_HANDLED;
681 }
682
683 static u32 hix5hd2_get_desc_cmd(struct sk_buff *skb, unsigned long hw_cap)
684 {
685 u32 cmd = 0;
686
687 if (HAS_CAP_TSO(hw_cap)) {
688 if (skb_shinfo(skb)->nr_frags)
689 cmd |= DESC_SG;
690 cmd |= skb_shinfo(skb)->nr_frags << DESC_FRAGS_NUM_OFF;
691 } else {
692 cmd |= DESC_FL_FULL |
693 ((skb->len & DESC_DATA_MASK) << DESC_BUFF_LEN_OFF);
694 }
695
696 cmd |= (skb->len & DESC_DATA_MASK) << DESC_DATA_LEN_OFF;
697 cmd |= DESC_VLD_BUSY;
698
699 return cmd;
700 }
701
702 static int hix5hd2_fill_sg_desc(struct hix5hd2_priv *priv,
703 struct sk_buff *skb, u32 pos)
704 {
705 struct sg_desc *desc;
706 dma_addr_t addr;
707 int ret;
708 int i;
709
710 desc = priv->tx_ring.desc + pos;
711
712 desc->total_len = cpu_to_le32(skb->len);
713 addr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
714 DMA_TO_DEVICE);
715 if (unlikely(dma_mapping_error(priv->dev, addr)))
716 return -EINVAL;
717 desc->linear_addr = cpu_to_le32(addr);
718 desc->linear_len = cpu_to_le32(skb_headlen(skb));
719
720 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
721 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
722 int len = skb_frag_size(frag);
723
724 addr = skb_frag_dma_map(priv->dev, frag, 0, len, DMA_TO_DEVICE);
725 ret = dma_mapping_error(priv->dev, addr);
726 if (unlikely(ret))
727 return -EINVAL;
728 desc->frags[i].addr = cpu_to_le32(addr);
729 desc->frags[i].size = cpu_to_le32(len);
730 }
731
732 return 0;
733 }
734
735 static netdev_tx_t hix5hd2_net_xmit(struct sk_buff *skb, struct net_device *dev)
736 {
737 struct hix5hd2_priv *priv = netdev_priv(dev);
738 struct hix5hd2_desc *desc;
739 dma_addr_t addr;
740 u32 pos;
741 u32 cmd;
742 int ret;
743
744 /* software write pointer */
745 pos = dma_cnt(readl_relaxed(priv->base + TX_BQ_WR_ADDR));
746 if (unlikely(priv->tx_skb[pos])) {
747 dev->stats.tx_dropped++;
748 dev->stats.tx_fifo_errors++;
749 netif_stop_queue(dev);
750 return NETDEV_TX_BUSY;
751 }
752
753 desc = priv->tx_bq.desc + pos;
754
755 cmd = hix5hd2_get_desc_cmd(skb, priv->hw_cap);
756 desc->cmd = cpu_to_le32(cmd);
757
758 if (skb_shinfo(skb)->nr_frags) {
759 ret = hix5hd2_fill_sg_desc(priv, skb, pos);
760 if (unlikely(ret)) {
761 dev_kfree_skb_any(skb);
762 dev->stats.tx_dropped++;
763 return NETDEV_TX_OK;
764 }
765 addr = priv->tx_ring.phys_addr + pos * sizeof(struct sg_desc);
766 } else {
767 addr = dma_map_single(priv->dev, skb->data, skb->len,
768 DMA_TO_DEVICE);
769 if (unlikely(dma_mapping_error(priv->dev, addr))) {
770 dev_kfree_skb_any(skb);
771 dev->stats.tx_dropped++;
772 return NETDEV_TX_OK;
773 }
774 }
775 desc->buff_addr = cpu_to_le32(addr);
776
777 priv->tx_skb[pos] = skb;
778
779 /* ensure desc updated */
780 wmb();
781
782 pos = dma_ring_incr(pos, TX_DESC_NUM);
783 writel_relaxed(dma_byte(pos), priv->base + TX_BQ_WR_ADDR);
784
785 netif_trans_update(dev);
786 dev->stats.tx_packets++;
787 dev->stats.tx_bytes += skb->len;
788 netdev_sent_queue(dev, skb->len);
789
790 return NETDEV_TX_OK;
791 }
792
793 static void hix5hd2_free_dma_desc_rings(struct hix5hd2_priv *priv)
794 {
795 struct hix5hd2_desc *desc;
796 dma_addr_t addr;
797 int i;
798
799 for (i = 0; i < RX_DESC_NUM; i++) {
800 struct sk_buff *skb = priv->rx_skb[i];
801 if (skb == NULL)
802 continue;
803
804 desc = priv->rx_fq.desc + i;
805 addr = le32_to_cpu(desc->buff_addr);
806 dma_unmap_single(priv->dev, addr,
807 MAC_MAX_FRAME_SIZE, DMA_FROM_DEVICE);
808 dev_kfree_skb_any(skb);
809 priv->rx_skb[i] = NULL;
810 }
811
812 for (i = 0; i < TX_DESC_NUM; i++) {
813 struct sk_buff *skb = priv->tx_skb[i];
814 if (skb == NULL)
815 continue;
816
817 desc = priv->tx_rq.desc + i;
818 addr = le32_to_cpu(desc->buff_addr);
819 dma_unmap_single(priv->dev, addr, skb->len, DMA_TO_DEVICE);
820 dev_kfree_skb_any(skb);
821 priv->tx_skb[i] = NULL;
822 }
823 }
824
825 static int hix5hd2_net_open(struct net_device *dev)
826 {
827 struct hix5hd2_priv *priv = netdev_priv(dev);
828 struct phy_device *phy;
829 int ret;
830
831 ret = clk_prepare_enable(priv->mac_core_clk);
832 if (ret < 0) {
833 netdev_err(dev, "failed to enable mac core clk %d\n", ret);
834 return ret;
835 }
836
837 ret = clk_prepare_enable(priv->mac_ifc_clk);
838 if (ret < 0) {
839 clk_disable_unprepare(priv->mac_core_clk);
840 netdev_err(dev, "failed to enable mac ifc clk %d\n", ret);
841 return ret;
842 }
843
844 phy = of_phy_connect(dev, priv->phy_node,
845 &hix5hd2_adjust_link, 0, priv->phy_mode);
846 if (!phy) {
847 clk_disable_unprepare(priv->mac_ifc_clk);
848 clk_disable_unprepare(priv->mac_core_clk);
849 return -ENODEV;
850 }
851
852 phy_start(phy);
853 hix5hd2_hw_init(priv);
854 hix5hd2_rx_refill(priv);
855
856 netdev_reset_queue(dev);
857 netif_start_queue(dev);
858 napi_enable(&priv->napi);
859
860 hix5hd2_port_enable(priv);
861 hix5hd2_irq_enable(priv);
862
863 return 0;
864 }
865
866 static int hix5hd2_net_close(struct net_device *dev)
867 {
868 struct hix5hd2_priv *priv = netdev_priv(dev);
869
870 hix5hd2_port_disable(priv);
871 hix5hd2_irq_disable(priv);
872 napi_disable(&priv->napi);
873 netif_stop_queue(dev);
874 hix5hd2_free_dma_desc_rings(priv);
875
876 if (dev->phydev) {
877 phy_stop(dev->phydev);
878 phy_disconnect(dev->phydev);
879 }
880
881 clk_disable_unprepare(priv->mac_ifc_clk);
882 clk_disable_unprepare(priv->mac_core_clk);
883
884 return 0;
885 }
886
887 static void hix5hd2_tx_timeout_task(struct work_struct *work)
888 {
889 struct hix5hd2_priv *priv;
890
891 priv = container_of(work, struct hix5hd2_priv, tx_timeout_task);
892 hix5hd2_net_close(priv->netdev);
893 hix5hd2_net_open(priv->netdev);
894 }
895
896 static void hix5hd2_net_timeout(struct net_device *dev, unsigned int txqueue)
897 {
898 struct hix5hd2_priv *priv = netdev_priv(dev);
899
900 schedule_work(&priv->tx_timeout_task);
901 }
902
903 static const struct net_device_ops hix5hd2_netdev_ops = {
904 .ndo_open = hix5hd2_net_open,
905 .ndo_stop = hix5hd2_net_close,
906 .ndo_start_xmit = hix5hd2_net_xmit,
907 .ndo_tx_timeout = hix5hd2_net_timeout,
908 .ndo_set_mac_address = hix5hd2_net_set_mac_address,
909 };
910
911 static const struct ethtool_ops hix5hd2_ethtools_ops = {
912 .get_link = ethtool_op_get_link,
913 .get_link_ksettings = phy_ethtool_get_link_ksettings,
914 .set_link_ksettings = phy_ethtool_set_link_ksettings,
915 };
916
917 static int hix5hd2_mdio_wait_ready(struct mii_bus *bus)
918 {
919 struct hix5hd2_priv *priv = bus->priv;
920 void __iomem *base = priv->base;
921 int i, timeout = 10000;
922
923 for (i = 0; readl_relaxed(base + MDIO_SINGLE_CMD) & MDIO_START; i++) {
924 if (i == timeout)
925 return -ETIMEDOUT;
926 usleep_range(10, 20);
927 }
928
929 return 0;
930 }
931
932 static int hix5hd2_mdio_read(struct mii_bus *bus, int phy, int reg)
933 {
934 struct hix5hd2_priv *priv = bus->priv;
935 void __iomem *base = priv->base;
936 int val, ret;
937
938 ret = hix5hd2_mdio_wait_ready(bus);
939 if (ret < 0)
940 goto out;
941
942 writel_relaxed(MDIO_READ | phy << 8 | reg, base + MDIO_SINGLE_CMD);
943 ret = hix5hd2_mdio_wait_ready(bus);
944 if (ret < 0)
945 goto out;
946
947 val = readl_relaxed(base + MDIO_RDATA_STATUS);
948 if (val & MDIO_R_VALID) {
949 dev_err(bus->parent, "SMI bus read not valid\n");
950 ret = -ENODEV;
951 goto out;
952 }
953
954 val = readl_relaxed(priv->base + MDIO_SINGLE_DATA);
955 ret = (val >> 16) & 0xFFFF;
956 out:
957 return ret;
958 }
959
960 static int hix5hd2_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
961 {
962 struct hix5hd2_priv *priv = bus->priv;
963 void __iomem *base = priv->base;
964 int ret;
965
966 ret = hix5hd2_mdio_wait_ready(bus);
967 if (ret < 0)
968 goto out;
969
970 writel_relaxed(val, base + MDIO_SINGLE_DATA);
971 writel_relaxed(MDIO_WRITE | phy << 8 | reg, base + MDIO_SINGLE_CMD);
972 ret = hix5hd2_mdio_wait_ready(bus);
973 out:
974 return ret;
975 }
976
977 static void hix5hd2_destroy_hw_desc_queue(struct hix5hd2_priv *priv)
978 {
979 int i;
980
981 for (i = 0; i < QUEUE_NUMS; i++) {
982 if (priv->pool[i].desc) {
983 dma_free_coherent(priv->dev, priv->pool[i].size,
984 priv->pool[i].desc,
985 priv->pool[i].phys_addr);
986 priv->pool[i].desc = NULL;
987 }
988 }
989 }
990
991 static int hix5hd2_init_hw_desc_queue(struct hix5hd2_priv *priv)
992 {
993 struct device *dev = priv->dev;
994 struct hix5hd2_desc *virt_addr;
995 dma_addr_t phys_addr;
996 int size, i;
997
998 priv->rx_fq.count = RX_DESC_NUM;
999 priv->rx_bq.count = RX_DESC_NUM;
1000 priv->tx_bq.count = TX_DESC_NUM;
1001 priv->tx_rq.count = TX_DESC_NUM;
1002
1003 for (i = 0; i < QUEUE_NUMS; i++) {
1004 size = priv->pool[i].count * sizeof(struct hix5hd2_desc);
1005 virt_addr = dma_alloc_coherent(dev, size, &phys_addr,
1006 GFP_KERNEL);
1007 if (virt_addr == NULL)
1008 goto error_free_pool;
1009
1010 priv->pool[i].size = size;
1011 priv->pool[i].desc = virt_addr;
1012 priv->pool[i].phys_addr = phys_addr;
1013 }
1014 return 0;
1015
1016 error_free_pool:
1017 hix5hd2_destroy_hw_desc_queue(priv);
1018
1019 return -ENOMEM;
1020 }
1021
1022 static int hix5hd2_init_sg_desc_queue(struct hix5hd2_priv *priv)
1023 {
1024 struct sg_desc *desc;
1025 dma_addr_t phys_addr;
1026
1027 desc = dma_alloc_coherent(priv->dev,
1028 TX_DESC_NUM * sizeof(struct sg_desc),
1029 &phys_addr, GFP_KERNEL);
1030 if (!desc)
1031 return -ENOMEM;
1032
1033 priv->tx_ring.desc = desc;
1034 priv->tx_ring.phys_addr = phys_addr;
1035
1036 return 0;
1037 }
1038
1039 static void hix5hd2_destroy_sg_desc_queue(struct hix5hd2_priv *priv)
1040 {
1041 if (priv->tx_ring.desc) {
1042 dma_free_coherent(priv->dev,
1043 TX_DESC_NUM * sizeof(struct sg_desc),
1044 priv->tx_ring.desc, priv->tx_ring.phys_addr);
1045 priv->tx_ring.desc = NULL;
1046 }
1047 }
1048
1049 static inline void hix5hd2_mac_core_reset(struct hix5hd2_priv *priv)
1050 {
1051 if (!priv->mac_core_rst)
1052 return;
1053
1054 reset_control_assert(priv->mac_core_rst);
1055 reset_control_deassert(priv->mac_core_rst);
1056 }
1057
1058 static void hix5hd2_sleep_us(u32 time_us)
1059 {
1060 u32 time_ms;
1061
1062 if (!time_us)
1063 return;
1064
1065 time_ms = DIV_ROUND_UP(time_us, 1000);
1066 if (time_ms < 20)
1067 usleep_range(time_us, time_us + 500);
1068 else
1069 msleep(time_ms);
1070 }
1071
1072 static void hix5hd2_phy_reset(struct hix5hd2_priv *priv)
1073 {
1074 /* To make sure PHY hardware reset success,
1075 * we must keep PHY in deassert state first and
1076 * then complete the hardware reset operation
1077 */
1078 reset_control_deassert(priv->phy_rst);
1079 hix5hd2_sleep_us(priv->phy_reset_delays[PRE_DELAY]);
1080
1081 reset_control_assert(priv->phy_rst);
1082 /* delay some time to ensure reset ok,
1083 * this depends on PHY hardware feature
1084 */
1085 hix5hd2_sleep_us(priv->phy_reset_delays[PULSE]);
1086 reset_control_deassert(priv->phy_rst);
1087 /* delay some time to ensure later MDIO access */
1088 hix5hd2_sleep_us(priv->phy_reset_delays[POST_DELAY]);
1089 }
1090
1091 static const struct of_device_id hix5hd2_of_match[];
1092
1093 static int hix5hd2_dev_probe(struct platform_device *pdev)
1094 {
1095 struct device *dev = &pdev->dev;
1096 struct device_node *node = dev->of_node;
1097 const struct of_device_id *of_id = NULL;
1098 struct net_device *ndev;
1099 struct hix5hd2_priv *priv;
1100 struct mii_bus *bus;
1101 int ret;
1102
1103 ndev = alloc_etherdev(sizeof(struct hix5hd2_priv));
1104 if (!ndev)
1105 return -ENOMEM;
1106
1107 platform_set_drvdata(pdev, ndev);
1108
1109 priv = netdev_priv(ndev);
1110 priv->dev = dev;
1111 priv->netdev = ndev;
1112
1113 of_id = of_match_device(hix5hd2_of_match, dev);
1114 if (!of_id) {
1115 ret = -EINVAL;
1116 goto out_free_netdev;
1117 }
1118 priv->hw_cap = (unsigned long)of_id->data;
1119
1120 priv->base = devm_platform_ioremap_resource(pdev, 0);
1121 if (IS_ERR(priv->base)) {
1122 ret = PTR_ERR(priv->base);
1123 goto out_free_netdev;
1124 }
1125
1126 priv->ctrl_base = devm_platform_ioremap_resource(pdev, 1);
1127 if (IS_ERR(priv->ctrl_base)) {
1128 ret = PTR_ERR(priv->ctrl_base);
1129 goto out_free_netdev;
1130 }
1131
1132 priv->mac_core_clk = devm_clk_get(&pdev->dev, "mac_core");
1133 if (IS_ERR(priv->mac_core_clk)) {
1134 netdev_err(ndev, "failed to get mac core clk\n");
1135 ret = -ENODEV;
1136 goto out_free_netdev;
1137 }
1138
1139 ret = clk_prepare_enable(priv->mac_core_clk);
1140 if (ret < 0) {
1141 netdev_err(ndev, "failed to enable mac core clk %d\n", ret);
1142 goto out_free_netdev;
1143 }
1144
1145 priv->mac_ifc_clk = devm_clk_get(&pdev->dev, "mac_ifc");
1146 if (IS_ERR(priv->mac_ifc_clk))
1147 priv->mac_ifc_clk = NULL;
1148
1149 ret = clk_prepare_enable(priv->mac_ifc_clk);
1150 if (ret < 0) {
1151 netdev_err(ndev, "failed to enable mac ifc clk %d\n", ret);
1152 goto out_disable_mac_core_clk;
1153 }
1154
1155 priv->mac_core_rst = devm_reset_control_get(dev, "mac_core");
1156 if (IS_ERR(priv->mac_core_rst))
1157 priv->mac_core_rst = NULL;
1158 hix5hd2_mac_core_reset(priv);
1159
1160 priv->mac_ifc_rst = devm_reset_control_get(dev, "mac_ifc");
1161 if (IS_ERR(priv->mac_ifc_rst))
1162 priv->mac_ifc_rst = NULL;
1163
1164 priv->phy_rst = devm_reset_control_get(dev, "phy");
1165 if (IS_ERR(priv->phy_rst)) {
1166 priv->phy_rst = NULL;
1167 } else {
1168 ret = of_property_read_u32_array(node,
1169 PHY_RESET_DELAYS_PROPERTY,
1170 priv->phy_reset_delays,
1171 DELAYS_NUM);
1172 if (ret)
1173 goto out_disable_clk;
1174 hix5hd2_phy_reset(priv);
1175 }
1176
1177 bus = mdiobus_alloc();
1178 if (bus == NULL) {
1179 ret = -ENOMEM;
1180 goto out_disable_clk;
1181 }
1182
1183 bus->priv = priv;
1184 bus->name = "hix5hd2_mii_bus";
1185 bus->read = hix5hd2_mdio_read;
1186 bus->write = hix5hd2_mdio_write;
1187 bus->parent = &pdev->dev;
1188 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev));
1189 priv->bus = bus;
1190
1191 ret = of_mdiobus_register(bus, node);
1192 if (ret)
1193 goto err_free_mdio;
1194
1195 ret = of_get_phy_mode(node, &priv->phy_mode);
1196 if (ret) {
1197 netdev_err(ndev, "not find phy-mode\n");
1198 goto err_mdiobus;
1199 }
1200
1201 priv->phy_node = of_parse_phandle(node, "phy-handle", 0);
1202 if (!priv->phy_node) {
1203 netdev_err(ndev, "not find phy-handle\n");
1204 ret = -EINVAL;
1205 goto err_mdiobus;
1206 }
1207
1208 ndev->irq = platform_get_irq(pdev, 0);
1209 if (ndev->irq <= 0) {
1210 netdev_err(ndev, "No irq resource\n");
1211 ret = -EINVAL;
1212 goto out_phy_node;
1213 }
1214
1215 ret = devm_request_irq(dev, ndev->irq, hix5hd2_interrupt,
1216 0, pdev->name, ndev);
1217 if (ret) {
1218 netdev_err(ndev, "devm_request_irq failed\n");
1219 goto out_phy_node;
1220 }
1221
1222 ret = of_get_mac_address(node, ndev->dev_addr);
1223 if (ret) {
1224 eth_hw_addr_random(ndev);
1225 netdev_warn(ndev, "using random MAC address %pM\n",
1226 ndev->dev_addr);
1227 }
1228
1229 INIT_WORK(&priv->tx_timeout_task, hix5hd2_tx_timeout_task);
1230 ndev->watchdog_timeo = 6 * HZ;
1231 ndev->priv_flags |= IFF_UNICAST_FLT;
1232 ndev->netdev_ops = &hix5hd2_netdev_ops;
1233 ndev->ethtool_ops = &hix5hd2_ethtools_ops;
1234 SET_NETDEV_DEV(ndev, dev);
1235
1236 if (HAS_CAP_TSO(priv->hw_cap))
1237 ndev->hw_features |= NETIF_F_SG;
1238
1239 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
1240 ndev->vlan_features |= ndev->features;
1241
1242 ret = hix5hd2_init_hw_desc_queue(priv);
1243 if (ret)
1244 goto out_phy_node;
1245
1246 netif_napi_add(ndev, &priv->napi, hix5hd2_poll, NAPI_POLL_WEIGHT);
1247
1248 if (HAS_CAP_TSO(priv->hw_cap)) {
1249 ret = hix5hd2_init_sg_desc_queue(priv);
1250 if (ret)
1251 goto out_destroy_queue;
1252 }
1253
1254 ret = register_netdev(priv->netdev);
1255 if (ret) {
1256 netdev_err(ndev, "register_netdev failed!");
1257 goto out_destroy_queue;
1258 }
1259
1260 clk_disable_unprepare(priv->mac_ifc_clk);
1261 clk_disable_unprepare(priv->mac_core_clk);
1262
1263 return ret;
1264
1265 out_destroy_queue:
1266 if (HAS_CAP_TSO(priv->hw_cap))
1267 hix5hd2_destroy_sg_desc_queue(priv);
1268 netif_napi_del(&priv->napi);
1269 hix5hd2_destroy_hw_desc_queue(priv);
1270 out_phy_node:
1271 of_node_put(priv->phy_node);
1272 err_mdiobus:
1273 mdiobus_unregister(bus);
1274 err_free_mdio:
1275 mdiobus_free(bus);
1276 out_disable_clk:
1277 clk_disable_unprepare(priv->mac_ifc_clk);
1278 out_disable_mac_core_clk:
1279 clk_disable_unprepare(priv->mac_core_clk);
1280 out_free_netdev:
1281 free_netdev(ndev);
1282
1283 return ret;
1284 }
1285
1286 static int hix5hd2_dev_remove(struct platform_device *pdev)
1287 {
1288 struct net_device *ndev = platform_get_drvdata(pdev);
1289 struct hix5hd2_priv *priv = netdev_priv(ndev);
1290
1291 netif_napi_del(&priv->napi);
1292 unregister_netdev(ndev);
1293 mdiobus_unregister(priv->bus);
1294 mdiobus_free(priv->bus);
1295
1296 if (HAS_CAP_TSO(priv->hw_cap))
1297 hix5hd2_destroy_sg_desc_queue(priv);
1298 hix5hd2_destroy_hw_desc_queue(priv);
1299 of_node_put(priv->phy_node);
1300 cancel_work_sync(&priv->tx_timeout_task);
1301 free_netdev(ndev);
1302
1303 return 0;
1304 }
1305
1306 static const struct of_device_id hix5hd2_of_match[] = {
1307 { .compatible = "hisilicon,hisi-gmac-v1", .data = (void *)GEMAC_V1 },
1308 { .compatible = "hisilicon,hisi-gmac-v2", .data = (void *)GEMAC_V2 },
1309 { .compatible = "hisilicon,hix5hd2-gmac", .data = (void *)GEMAC_V1 },
1310 { .compatible = "hisilicon,hi3798cv200-gmac", .data = (void *)GEMAC_V2 },
1311 { .compatible = "hisilicon,hi3516a-gmac", .data = (void *)GEMAC_V2 },
1312 {},
1313 };
1314
1315 MODULE_DEVICE_TABLE(of, hix5hd2_of_match);
1316
1317 static struct platform_driver hix5hd2_dev_driver = {
1318 .driver = {
1319 .name = "hisi-gmac",
1320 .of_match_table = hix5hd2_of_match,
1321 },
1322 .probe = hix5hd2_dev_probe,
1323 .remove = hix5hd2_dev_remove,
1324 };
1325
1326 module_platform_driver(hix5hd2_dev_driver);
1327
1328 MODULE_DESCRIPTION("HISILICON Gigabit Ethernet MAC driver");
1329 MODULE_LICENSE("GPL v2");
1330 MODULE_ALIAS("platform:hisi-gmac");
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