drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c

   1 /*
   2  * Copyright (c) 2014-2015 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/delay.h>
  11 #include <linux/of_mdio.h>
  12 #include "hns_dsaf_main.h"
  13 #include "hns_dsaf_mac.h"
  14 #include "hns_dsaf_gmac.h"
  15
  16 static const struct mac_stats_string g_gmac_stats_string[] = {
  17         {"gmac_rx_octets_total_ok", MAC_STATS_FIELD_OFF(rx_good_bytes)},
  18         {"gmac_rx_octets_bad", MAC_STATS_FIELD_OFF(rx_bad_bytes)},
  19         {"gmac_rx_uc_pkts", MAC_STATS_FIELD_OFF(rx_uc_pkts)},
  20         {"gmac_rx_mc_pkts", MAC_STATS_FIELD_OFF(rx_mc_pkts)},
  21         {"gmac_rx_bc_pkts", MAC_STATS_FIELD_OFF(rx_bc_pkts)},
  22         {"gmac_rx_pkts_64octets", MAC_STATS_FIELD_OFF(rx_64bytes)},
  23         {"gmac_rx_pkts_65to127", MAC_STATS_FIELD_OFF(rx_65to127)},
  24         {"gmac_rx_pkts_128to255", MAC_STATS_FIELD_OFF(rx_128to255)},
  25         {"gmac_rx_pkts_256to511", MAC_STATS_FIELD_OFF(rx_256to511)},
  26         {"gmac_rx_pkts_512to1023", MAC_STATS_FIELD_OFF(rx_512to1023)},
  27         {"gmac_rx_pkts_1024to1518", MAC_STATS_FIELD_OFF(rx_1024to1518)},
  28         {"gmac_rx_pkts_1519tomax", MAC_STATS_FIELD_OFF(rx_1519tomax)},
  29         {"gmac_rx_fcs_errors", MAC_STATS_FIELD_OFF(rx_fcs_err)},
  30         {"gmac_rx_tagged", MAC_STATS_FIELD_OFF(rx_vlan_pkts)},
  31         {"gmac_rx_data_err", MAC_STATS_FIELD_OFF(rx_data_err)},
  32         {"gmac_rx_align_errors", MAC_STATS_FIELD_OFF(rx_align_err)},
  33         {"gmac_rx_long_errors", MAC_STATS_FIELD_OFF(rx_oversize)},
  34         {"gmac_rx_jabber_errors", MAC_STATS_FIELD_OFF(rx_jabber_err)},
  35         {"gmac_rx_pause_maccontrol", MAC_STATS_FIELD_OFF(rx_pfc_tc0)},
  36         {"gmac_rx_unknown_maccontrol", MAC_STATS_FIELD_OFF(rx_unknown_ctrl)},
  37         {"gmac_rx_very_long_err", MAC_STATS_FIELD_OFF(rx_long_err)},
  38         {"gmac_rx_runt_err", MAC_STATS_FIELD_OFF(rx_minto64)},
  39         {"gmac_rx_short_err", MAC_STATS_FIELD_OFF(rx_under_min)},
  40         {"gmac_rx_filt_pkt", MAC_STATS_FIELD_OFF(rx_filter_pkts)},
  41         {"gmac_rx_octets_total_filt", MAC_STATS_FIELD_OFF(rx_filter_bytes)},
  42         {"gmac_rx_overrun_cnt", MAC_STATS_FIELD_OFF(rx_fifo_overrun_err)},
  43         {"gmac_rx_length_err", MAC_STATS_FIELD_OFF(rx_len_err)},
  44         {"gmac_rx_fail_comma", MAC_STATS_FIELD_OFF(rx_comma_err)},
  45
  46         {"gmac_tx_octets_ok", MAC_STATS_FIELD_OFF(tx_good_bytes)},
  47         {"gmac_tx_octets_bad", MAC_STATS_FIELD_OFF(tx_bad_bytes)},
  48         {"gmac_tx_uc_pkts", MAC_STATS_FIELD_OFF(tx_uc_pkts)},
  49         {"gmac_tx_mc_pkts", MAC_STATS_FIELD_OFF(tx_mc_pkts)},
  50         {"gmac_tx_bc_pkts", MAC_STATS_FIELD_OFF(tx_bc_pkts)},
  51         {"gmac_tx_pkts_64octets", MAC_STATS_FIELD_OFF(tx_64bytes)},
  52         {"gmac_tx_pkts_65to127", MAC_STATS_FIELD_OFF(tx_65to127)},
  53         {"gmac_tx_pkts_128to255", MAC_STATS_FIELD_OFF(tx_128to255)},
  54         {"gmac_tx_pkts_256to511", MAC_STATS_FIELD_OFF(tx_256to511)},
  55         {"gmac_tx_pkts_512to1023", MAC_STATS_FIELD_OFF(tx_512to1023)},
  56         {"gmac_tx_pkts_1024to1518", MAC_STATS_FIELD_OFF(tx_1024to1518)},
  57         {"gmac_tx_pkts_1519tomax", MAC_STATS_FIELD_OFF(tx_1519tomax)},
  58         {"gmac_tx_excessive_length_drop", MAC_STATS_FIELD_OFF(tx_jabber_err)},
  59         {"gmac_tx_underrun", MAC_STATS_FIELD_OFF(tx_underrun_err)},
  60         {"gmac_tx_tagged", MAC_STATS_FIELD_OFF(tx_vlan)},
  61         {"gmac_tx_crc_error", MAC_STATS_FIELD_OFF(tx_crc_err)},
  62         {"gmac_tx_pause_frames", MAC_STATS_FIELD_OFF(tx_pfc_tc0)}
  63 };
  64
  65 static void hns_gmac_enable(void *mac_drv, enum mac_commom_mode mode)
  66 {
  67         struct mac_driver *drv = (struct mac_driver *)mac_drv;
  68
  69         /*enable GE rX/tX */
  70         if ((mode == MAC_COMM_MODE_TX) || (mode == MAC_COMM_MODE_RX_AND_TX))
  71                 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_TX_EN_B, 1);
  72
  73         if ((mode == MAC_COMM_MODE_RX) || (mode == MAC_COMM_MODE_RX_AND_TX))
  74                 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_RX_EN_B, 1);
  75 }
  76
  77 static void hns_gmac_disable(void *mac_drv, enum mac_commom_mode mode)
  78 {
  79         struct mac_driver *drv = (struct mac_driver *)mac_drv;
  80
  81         /*disable GE rX/tX */
  82         if ((mode == MAC_COMM_MODE_TX) || (mode == MAC_COMM_MODE_RX_AND_TX))
  83                 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_TX_EN_B, 0);
  84
  85         if ((mode == MAC_COMM_MODE_RX) || (mode == MAC_COMM_MODE_RX_AND_TX))
  86                 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_RX_EN_B, 0);
  87 }
  88
  89 /**
  90 *hns_gmac_get_en - get port enable
  91 *@mac_drv:mac device
  92 *@rx:rx enable
  93 *@tx:tx enable
  94 */
  95 static void hns_gmac_get_en(void *mac_drv, u32 *rx, u32 *tx)
  96 {
  97         struct mac_driver *drv = (struct mac_driver *)mac_drv;
  98         u32 porten;
  99
 100         porten = dsaf_read_dev(drv, GMAC_PORT_EN_REG);
 101         *tx = dsaf_get_bit(porten, GMAC_PORT_TX_EN_B);
 102         *rx = dsaf_get_bit(porten, GMAC_PORT_RX_EN_B);
 103 }
 104
 105 static void hns_gmac_free(void *mac_drv)
 106 {
 107         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 108         struct dsaf_device *dsaf_dev
 109                 = (struct dsaf_device *)dev_get_drvdata(drv->dev);
 110
 111         u32 mac_id = drv->mac_id;
 112
 113         dsaf_dev->misc_op->ge_srst(dsaf_dev, mac_id, 0);
 114 }
 115
 116 static void hns_gmac_set_tx_auto_pause_frames(void *mac_drv, u16 newval)
 117 {
 118         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 119
 120         dsaf_set_dev_field(drv, GMAC_FC_TX_TIMER_REG, GMAC_FC_TX_TIMER_M,
 121                            GMAC_FC_TX_TIMER_S, newval);
 122 }
 123
 124 static void hns_gmac_get_tx_auto_pause_frames(void *mac_drv, u16 *newval)
 125 {
 126         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 127
 128         *newval = dsaf_get_dev_field(drv, GMAC_FC_TX_TIMER_REG,
 129                                      GMAC_FC_TX_TIMER_M, GMAC_FC_TX_TIMER_S);
 130 }
 131
 132 static void hns_gmac_set_rx_auto_pause_frames(void *mac_drv, u32 newval)
 133 {
 134         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 135
 136         dsaf_set_dev_bit(drv, GMAC_PAUSE_EN_REG,
 137                          GMAC_PAUSE_EN_RX_FDFC_B, !!newval);
 138 }
 139
 140 static void hns_gmac_config_max_frame_length(void *mac_drv, u16 newval)
 141 {
 142         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 143
 144         dsaf_set_dev_field(drv, GMAC_MAX_FRM_SIZE_REG, GMAC_MAX_FRM_SIZE_M,
 145                            GMAC_MAX_FRM_SIZE_S, newval);
 146
 147         dsaf_set_dev_field(drv, GAMC_RX_MAX_FRAME, GMAC_MAX_FRM_SIZE_M,
 148                            GMAC_MAX_FRM_SIZE_S, newval);
 149 }
 150
 151 static void hns_gmac_config_pad_and_crc(void *mac_drv, u8 newval)
 152 {
 153         u32 tx_ctrl;
 154         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 155
 156         tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG);
 157         dsaf_set_bit(tx_ctrl, GMAC_TX_PAD_EN_B, !!newval);
 158         dsaf_set_bit(tx_ctrl, GMAC_TX_CRC_ADD_B, !!newval);
 159         dsaf_write_dev(drv, GMAC_TRANSMIT_CONTROL_REG, tx_ctrl);
 160 }
 161
 162 static void hns_gmac_config_an_mode(void *mac_drv, u8 newval)
 163 {
 164         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 165
 166         dsaf_set_dev_bit(drv, GMAC_TRANSMIT_CONTROL_REG,
 167                          GMAC_TX_AN_EN_B, !!newval);
 168 }
 169
 170 static void hns_gmac_tx_loop_pkt_dis(void *mac_drv)
 171 {
 172         u32 tx_loop_pkt_pri;
 173         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 174
 175         tx_loop_pkt_pri = dsaf_read_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG);
 176         dsaf_set_bit(tx_loop_pkt_pri, GMAC_TX_LOOP_PKT_EN_B, 1);
 177         dsaf_set_bit(tx_loop_pkt_pri, GMAC_TX_LOOP_PKT_HIG_PRI_B, 0);
 178         dsaf_write_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG, tx_loop_pkt_pri);
 179 }
 180
 181 static void hns_gmac_set_duplex_type(void *mac_drv, u8 newval)
 182 {
 183         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 184
 185         dsaf_set_dev_bit(drv, GMAC_DUPLEX_TYPE_REG,
 186                          GMAC_DUPLEX_TYPE_B, !!newval);
 187 }
 188
 189 static void hns_gmac_get_duplex_type(void *mac_drv,
 190                                      enum hns_gmac_duplex_mdoe *duplex_mode)
 191 {
 192         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 193
 194         *duplex_mode = (enum hns_gmac_duplex_mdoe)dsaf_get_dev_bit(
 195                 drv, GMAC_DUPLEX_TYPE_REG, GMAC_DUPLEX_TYPE_B);
 196 }
 197
 198 static void hns_gmac_get_port_mode(void *mac_drv, enum hns_port_mode *port_mode)
 199 {
 200         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 201
 202         *port_mode = (enum hns_port_mode)dsaf_get_dev_field(
 203                 drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S);
 204 }
 205
 206 static void hns_gmac_port_mode_get(void *mac_drv,
 207                                    struct hns_gmac_port_mode_cfg *port_mode)
 208 {
 209         u32 tx_ctrl;
 210         u32 recv_ctrl;
 211         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 212
 213         port_mode->port_mode = (enum hns_port_mode)dsaf_get_dev_field(
 214                 drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S);
 215
 216         tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG);
 217         recv_ctrl = dsaf_read_dev(drv, GMAC_RECV_CONTROL_REG);
 218
 219         port_mode->max_frm_size =
 220                 dsaf_get_dev_field(drv, GMAC_MAX_FRM_SIZE_REG,
 221                                    GMAC_MAX_FRM_SIZE_M, GMAC_MAX_FRM_SIZE_S);
 222         port_mode->short_runts_thr =
 223                 dsaf_get_dev_field(drv, GMAC_SHORT_RUNTS_THR_REG,
 224                                    GMAC_SHORT_RUNTS_THR_M,
 225                                    GMAC_SHORT_RUNTS_THR_S);
 226
 227         port_mode->pad_enable = dsaf_get_bit(tx_ctrl, GMAC_TX_PAD_EN_B);
 228         port_mode->crc_add = dsaf_get_bit(tx_ctrl, GMAC_TX_CRC_ADD_B);
 229         port_mode->an_enable = dsaf_get_bit(tx_ctrl, GMAC_TX_AN_EN_B);
 230
 231         port_mode->runt_pkt_en =
 232                 dsaf_get_bit(recv_ctrl, GMAC_RECV_CTRL_RUNT_PKT_EN_B);
 233         port_mode->strip_pad_en =
 234                 dsaf_get_bit(recv_ctrl, GMAC_RECV_CTRL_STRIP_PAD_EN_B);
 235 }
 236
 237 static void hns_gmac_pause_frm_cfg(void *mac_drv, u32 rx_pause_en,
 238                                    u32 tx_pause_en)
 239 {
 240         u32 pause_en;
 241         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 242
 243         pause_en = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG);
 244         dsaf_set_bit(pause_en, GMAC_PAUSE_EN_RX_FDFC_B, !!rx_pause_en);
 245         dsaf_set_bit(pause_en, GMAC_PAUSE_EN_TX_FDFC_B, !!tx_pause_en);
 246         dsaf_write_dev(drv, GMAC_PAUSE_EN_REG, pause_en);
 247 }
 248
 249 static void hns_gmac_get_pausefrm_cfg(void *mac_drv, u32 *rx_pause_en,
 250                                       u32 *tx_pause_en)
 251 {
 252         u32 pause_en;
 253         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 254
 255         pause_en = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG);
 256
 257         *rx_pause_en = dsaf_get_bit(pause_en, GMAC_PAUSE_EN_RX_FDFC_B);
 258         *tx_pause_en = dsaf_get_bit(pause_en, GMAC_PAUSE_EN_TX_FDFC_B);
 259 }
 260
 261 static int hns_gmac_adjust_link(void *mac_drv, enum mac_speed speed,
 262                                 u32 full_duplex)
 263 {
 264         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 265
 266         dsaf_set_dev_bit(drv, GMAC_DUPLEX_TYPE_REG,
 267                          GMAC_DUPLEX_TYPE_B, !!full_duplex);
 268
 269         switch (speed) {
 270         case MAC_SPEED_10:
 271                 dsaf_set_dev_field(
 272                         drv, GMAC_PORT_MODE_REG,
 273                         GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x6);
 274                 break;
 275         case MAC_SPEED_100:
 276                 dsaf_set_dev_field(
 277                         drv, GMAC_PORT_MODE_REG,
 278                         GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x7);
 279                 break;
 280         case MAC_SPEED_1000:
 281                 dsaf_set_dev_field(
 282                         drv, GMAC_PORT_MODE_REG,
 283                         GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x8);
 284                 break;
 285         default:
 286                 dev_err(drv->dev,
 287                         "hns_gmac_adjust_link fail, speed%d mac%d\n",
 288                         speed, drv->mac_id);
 289                 return -EINVAL;
 290         }
 291
 292         return 0;
 293 }
 294
 295 static void hns_gmac_set_uc_match(void *mac_drv, u16 en)
 296 {
 297         struct mac_driver *drv = mac_drv;
 298
 299         dsaf_set_dev_bit(drv, GMAC_REC_FILT_CONTROL_REG,
 300                          GMAC_UC_MATCH_EN_B, !en);
 301         dsaf_set_dev_bit(drv, GMAC_STATION_ADDR_HIGH_2_REG,
 302                          GMAC_ADDR_EN_B, !en);
 303 }
 304
 305 static void hns_gmac_set_promisc(void *mac_drv, u8 en)
 306 {
 307         struct mac_driver *drv = mac_drv;
 308
 309         if (drv->mac_cb->mac_type == HNAE_PORT_DEBUG)
 310                 hns_gmac_set_uc_match(mac_drv, en);
 311 }
 312
 313 static void hns_gmac_init(void *mac_drv)
 314 {
 315         u32 port;
 316         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 317         struct dsaf_device *dsaf_dev
 318                 = (struct dsaf_device *)dev_get_drvdata(drv->dev);
 319
 320         port = drv->mac_id;
 321
 322         dsaf_dev->misc_op->ge_srst(dsaf_dev, port, 0);
 323         mdelay(10);
 324         dsaf_dev->misc_op->ge_srst(dsaf_dev, port, 1);
 325         mdelay(10);
 326         hns_gmac_disable(mac_drv, MAC_COMM_MODE_RX_AND_TX);
 327         hns_gmac_tx_loop_pkt_dis(mac_drv);
 328         if (drv->mac_cb->mac_type == HNAE_PORT_DEBUG)
 329                 hns_gmac_set_uc_match(mac_drv, 0);
 330
 331         hns_gmac_config_pad_and_crc(mac_drv, 1);
 332
 333         dsaf_set_dev_bit(drv, GMAC_MODE_CHANGE_EN_REG,
 334                          GMAC_MODE_CHANGE_EB_B, 1);
 335
 336         /* reduce gmac tx water line to avoid gmac hang-up
 337          * in speed 100M and duplex half.
 338          */
 339         dsaf_set_dev_field(drv, GMAC_TX_WATER_LINE_REG, GMAC_TX_WATER_LINE_MASK,
 340                            GMAC_TX_WATER_LINE_SHIFT, 8);
 341 }
 342
 343 void hns_gmac_update_stats(void *mac_drv)
 344 {
 345         struct mac_hw_stats *hw_stats = NULL;
 346         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 347
 348         hw_stats = &drv->mac_cb->hw_stats;
 349
 350         /* RX */
 351         hw_stats->rx_good_bytes
 352                 += dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_OK_REG);
 353         hw_stats->rx_bad_bytes
 354                 += dsaf_read_dev(drv, GMAC_RX_OCTETS_BAD_REG);
 355         hw_stats->rx_uc_pkts += dsaf_read_dev(drv, GMAC_RX_UC_PKTS_REG);
 356         hw_stats->rx_mc_pkts += dsaf_read_dev(drv, GMAC_RX_MC_PKTS_REG);
 357         hw_stats->rx_bc_pkts += dsaf_read_dev(drv, GMAC_RX_BC_PKTS_REG);
 358         hw_stats->rx_64bytes
 359                 += dsaf_read_dev(drv, GMAC_RX_PKTS_64OCTETS_REG);
 360         hw_stats->rx_65to127
 361                 += dsaf_read_dev(drv, GMAC_RX_PKTS_65TO127OCTETS_REG);
 362         hw_stats->rx_128to255
 363                 += dsaf_read_dev(drv, GMAC_RX_PKTS_128TO255OCTETS_REG);
 364         hw_stats->rx_256to511
 365                 += dsaf_read_dev(drv, GMAC_RX_PKTS_255TO511OCTETS_REG);
 366         hw_stats->rx_512to1023
 367                 += dsaf_read_dev(drv, GMAC_RX_PKTS_512TO1023OCTETS_REG);
 368         hw_stats->rx_1024to1518
 369                 += dsaf_read_dev(drv, GMAC_RX_PKTS_1024TO1518OCTETS_REG);
 370         hw_stats->rx_1519tomax
 371                 += dsaf_read_dev(drv, GMAC_RX_PKTS_1519TOMAXOCTETS_REG);
 372         hw_stats->rx_fcs_err += dsaf_read_dev(drv, GMAC_RX_FCS_ERRORS_REG);
 373         hw_stats->rx_vlan_pkts += dsaf_read_dev(drv, GMAC_RX_TAGGED_REG);
 374         hw_stats->rx_data_err += dsaf_read_dev(drv, GMAC_RX_DATA_ERR_REG);
 375         hw_stats->rx_align_err
 376                 += dsaf_read_dev(drv, GMAC_RX_ALIGN_ERRORS_REG);
 377         hw_stats->rx_oversize
 378                 += dsaf_read_dev(drv, GMAC_RX_LONG_ERRORS_REG);
 379         hw_stats->rx_jabber_err
 380                 += dsaf_read_dev(drv, GMAC_RX_JABBER_ERRORS_REG);
 381         hw_stats->rx_pfc_tc0
 382                 += dsaf_read_dev(drv, GMAC_RX_PAUSE_MACCTRL_FRAM_REG);
 383         hw_stats->rx_unknown_ctrl
 384                 += dsaf_read_dev(drv, GMAC_RX_UNKNOWN_MACCTRL_FRAM_REG);
 385         hw_stats->rx_long_err
 386                 += dsaf_read_dev(drv, GMAC_RX_VERY_LONG_ERR_CNT_REG);
 387         hw_stats->rx_minto64
 388                 += dsaf_read_dev(drv, GMAC_RX_RUNT_ERR_CNT_REG);
 389         hw_stats->rx_under_min
 390                 += dsaf_read_dev(drv, GMAC_RX_SHORT_ERR_CNT_REG);
 391         hw_stats->rx_filter_pkts
 392                 += dsaf_read_dev(drv, GMAC_RX_FILT_PKT_CNT_REG);
 393         hw_stats->rx_filter_bytes
 394                 += dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_FILT_REG);
 395         hw_stats->rx_fifo_overrun_err
 396                 += dsaf_read_dev(drv, GMAC_RX_OVERRUN_CNT_REG);
 397         hw_stats->rx_len_err
 398                 += dsaf_read_dev(drv, GMAC_RX_LENGTHFIELD_ERR_CNT_REG);
 399         hw_stats->rx_comma_err
 400                 += dsaf_read_dev(drv, GMAC_RX_FAIL_COMMA_CNT_REG);
 401
 402         /* TX */
 403         hw_stats->tx_good_bytes
 404                 += dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_OK_REG);
 405         hw_stats->tx_bad_bytes
 406                 += dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_BAD_REG);
 407         hw_stats->tx_uc_pkts += dsaf_read_dev(drv, GMAC_TX_UC_PKTS_REG);
 408         hw_stats->tx_mc_pkts += dsaf_read_dev(drv, GMAC_TX_MC_PKTS_REG);
 409         hw_stats->tx_bc_pkts += dsaf_read_dev(drv, GMAC_TX_BC_PKTS_REG);
 410         hw_stats->tx_64bytes
 411                 += dsaf_read_dev(drv, GMAC_TX_PKTS_64OCTETS_REG);
 412         hw_stats->tx_65to127
 413                 += dsaf_read_dev(drv, GMAC_TX_PKTS_65TO127OCTETS_REG);
 414         hw_stats->tx_128to255
 415                 += dsaf_read_dev(drv, GMAC_TX_PKTS_128TO255OCTETS_REG);
 416         hw_stats->tx_256to511
 417                 += dsaf_read_dev(drv, GMAC_TX_PKTS_255TO511OCTETS_REG);
 418         hw_stats->tx_512to1023
 419                 += dsaf_read_dev(drv, GMAC_TX_PKTS_512TO1023OCTETS_REG);
 420         hw_stats->tx_1024to1518
 421                 += dsaf_read_dev(drv, GMAC_TX_PKTS_1024TO1518OCTETS_REG);
 422         hw_stats->tx_1519tomax
 423                 += dsaf_read_dev(drv, GMAC_TX_PKTS_1519TOMAXOCTETS_REG);
 424         hw_stats->tx_jabber_err
 425                 += dsaf_read_dev(drv, GMAC_TX_EXCESSIVE_LENGTH_DROP_REG);
 426         hw_stats->tx_underrun_err
 427                 += dsaf_read_dev(drv, GMAC_TX_UNDERRUN_REG);
 428         hw_stats->tx_vlan += dsaf_read_dev(drv, GMAC_TX_TAGGED_REG);
 429         hw_stats->tx_crc_err += dsaf_read_dev(drv, GMAC_TX_CRC_ERROR_REG);
 430         hw_stats->tx_pfc_tc0
 431                 += dsaf_read_dev(drv, GMAC_TX_PAUSE_FRAMES_REG);
 432 }
 433
 434 static void hns_gmac_set_mac_addr(void *mac_drv, char *mac_addr)
 435 {
 436         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 437
 438         u32 high_val = mac_addr[1] | (mac_addr[0] << 8);
 439
 440         u32 low_val = mac_addr[5] | (mac_addr[4] << 8)
 441                 | (mac_addr[3] << 16) | (mac_addr[2] << 24);
 442
 443         u32 val = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG);
 444         u32 sta_addr_en = dsaf_get_bit(val, GMAC_ADDR_EN_B);
 445
 446         dsaf_write_dev(drv, GMAC_STATION_ADDR_LOW_2_REG, low_val);
 447         dsaf_write_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG,
 448                        high_val | (sta_addr_en << GMAC_ADDR_EN_B));
 449 }
 450
 451 static int hns_gmac_config_loopback(void *mac_drv, enum hnae_loop loop_mode,
 452                                     u8 enable)
 453 {
 454         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 455
 456         switch (loop_mode) {
 457         case MAC_INTERNALLOOP_MAC:
 458                 dsaf_set_dev_bit(drv, GMAC_LOOP_REG, GMAC_LP_REG_CF2MI_LP_EN_B,
 459                                  !!enable);
 460                 break;
 461         default:
 462                 dev_err(drv->dev, "loop_mode error\n");
 463                 return -EINVAL;
 464         }
 465
 466         return 0;
 467 }
 468
 469 static void hns_gmac_get_info(void *mac_drv, struct mac_info *mac_info)
 470 {
 471         enum hns_gmac_duplex_mdoe duplex;
 472         enum hns_port_mode speed;
 473         u32 rx_pause;
 474         u32 tx_pause;
 475         u32 rx;
 476         u32 tx;
 477         u16 fc_tx_timer;
 478         struct hns_gmac_port_mode_cfg port_mode = { GMAC_10M_MII, 0 };
 479
 480         hns_gmac_port_mode_get(mac_drv, &port_mode);
 481         mac_info->pad_and_crc_en = port_mode.crc_add && port_mode.pad_enable;
 482         mac_info->auto_neg = port_mode.an_enable;
 483
 484         hns_gmac_get_tx_auto_pause_frames(mac_drv, &fc_tx_timer);
 485         mac_info->tx_pause_time = fc_tx_timer;
 486
 487         hns_gmac_get_en(mac_drv, &rx, &tx);
 488         mac_info->port_en = rx && tx;
 489
 490         hns_gmac_get_duplex_type(mac_drv, &duplex);
 491         mac_info->duplex = duplex;
 492
 493         hns_gmac_get_port_mode(mac_drv, &speed);
 494         switch (speed) {
 495         case GMAC_10M_SGMII:
 496                 mac_info->speed = MAC_SPEED_10;
 497                 break;
 498         case GMAC_100M_SGMII:
 499                 mac_info->speed = MAC_SPEED_100;
 500                 break;
 501         case GMAC_1000M_SGMII:
 502                 mac_info->speed = MAC_SPEED_1000;
 503                 break;
 504         default:
 505                 mac_info->speed = 0;
 506                 break;
 507         }
 508
 509         hns_gmac_get_pausefrm_cfg(mac_drv, &rx_pause, &tx_pause);
 510         mac_info->rx_pause_en = rx_pause;
 511         mac_info->tx_pause_en = tx_pause;
 512 }
 513
 514 static void hns_gmac_autoneg_stat(void *mac_drv, u32 *enable)
 515 {
 516         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 517
 518         *enable = dsaf_get_dev_bit(drv, GMAC_TRANSMIT_CONTROL_REG,
 519                                    GMAC_TX_AN_EN_B);
 520 }
 521
 522 static void hns_gmac_get_link_status(void *mac_drv, u32 *link_stat)
 523 {
 524         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 525
 526         *link_stat = dsaf_get_dev_bit(drv, GMAC_AN_NEG_STATE_REG,
 527                                       GMAC_AN_NEG_STAT_RX_SYNC_OK_B);
 528 }
 529
 530 static void hns_gmac_get_regs(void *mac_drv, void *data)
 531 {
 532         u32 *regs = data;
 533         int i;
 534         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 535
 536         /* base config registers */
 537         regs[0] = dsaf_read_dev(drv, GMAC_DUPLEX_TYPE_REG);
 538         regs[1] = dsaf_read_dev(drv, GMAC_FD_FC_TYPE_REG);
 539         regs[2] = dsaf_read_dev(drv, GMAC_FC_TX_TIMER_REG);
 540         regs[3] = dsaf_read_dev(drv, GMAC_FD_FC_ADDR_LOW_REG);
 541         regs[4] = dsaf_read_dev(drv, GMAC_FD_FC_ADDR_HIGH_REG);
 542         regs[5] = dsaf_read_dev(drv, GMAC_IPG_TX_TIMER_REG);
 543         regs[6] = dsaf_read_dev(drv, GMAC_PAUSE_THR_REG);
 544         regs[7] = dsaf_read_dev(drv, GMAC_MAX_FRM_SIZE_REG);
 545         regs[8] = dsaf_read_dev(drv, GMAC_PORT_MODE_REG);
 546         regs[9] = dsaf_read_dev(drv, GMAC_PORT_EN_REG);
 547         regs[10] = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG);
 548         regs[11] = dsaf_read_dev(drv, GMAC_SHORT_RUNTS_THR_REG);
 549         regs[12] = dsaf_read_dev(drv, GMAC_AN_NEG_STATE_REG);
 550         regs[13] = dsaf_read_dev(drv, GMAC_TX_LOCAL_PAGE_REG);
 551         regs[14] = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG);
 552         regs[15] = dsaf_read_dev(drv, GMAC_REC_FILT_CONTROL_REG);
 553         regs[16] = dsaf_read_dev(drv, GMAC_PTP_CONFIG_REG);
 554
 555         /* rx static registers */
 556         regs[17] = dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_OK_REG);
 557         regs[18] = dsaf_read_dev(drv, GMAC_RX_OCTETS_BAD_REG);
 558         regs[19] = dsaf_read_dev(drv, GMAC_RX_UC_PKTS_REG);
 559         regs[20] = dsaf_read_dev(drv, GMAC_RX_MC_PKTS_REG);
 560         regs[21] = dsaf_read_dev(drv, GMAC_RX_BC_PKTS_REG);
 561         regs[22] = dsaf_read_dev(drv, GMAC_RX_PKTS_64OCTETS_REG);
 562         regs[23] = dsaf_read_dev(drv, GMAC_RX_PKTS_65TO127OCTETS_REG);
 563         regs[24] = dsaf_read_dev(drv, GMAC_RX_PKTS_128TO255OCTETS_REG);
 564         regs[25] = dsaf_read_dev(drv, GMAC_RX_PKTS_255TO511OCTETS_REG);
 565         regs[26] = dsaf_read_dev(drv, GMAC_RX_PKTS_512TO1023OCTETS_REG);
 566         regs[27] = dsaf_read_dev(drv, GMAC_RX_PKTS_1024TO1518OCTETS_REG);
 567         regs[28] = dsaf_read_dev(drv, GMAC_RX_PKTS_1519TOMAXOCTETS_REG);
 568         regs[29] = dsaf_read_dev(drv, GMAC_RX_FCS_ERRORS_REG);
 569         regs[30] = dsaf_read_dev(drv, GMAC_RX_TAGGED_REG);
 570         regs[31] = dsaf_read_dev(drv, GMAC_RX_DATA_ERR_REG);
 571         regs[32] = dsaf_read_dev(drv, GMAC_RX_ALIGN_ERRORS_REG);
 572         regs[33] = dsaf_read_dev(drv, GMAC_RX_LONG_ERRORS_REG);
 573         regs[34] = dsaf_read_dev(drv, GMAC_RX_JABBER_ERRORS_REG);
 574         regs[35] = dsaf_read_dev(drv, GMAC_RX_PAUSE_MACCTRL_FRAM_REG);
 575         regs[36] = dsaf_read_dev(drv, GMAC_RX_UNKNOWN_MACCTRL_FRAM_REG);
 576         regs[37] = dsaf_read_dev(drv, GMAC_RX_VERY_LONG_ERR_CNT_REG);
 577         regs[38] = dsaf_read_dev(drv, GMAC_RX_RUNT_ERR_CNT_REG);
 578         regs[39] = dsaf_read_dev(drv, GMAC_RX_SHORT_ERR_CNT_REG);
 579         regs[40] = dsaf_read_dev(drv, GMAC_RX_FILT_PKT_CNT_REG);
 580         regs[41] = dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_FILT_REG);
 581
 582         /* tx static registers */
 583         regs[42] = dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_OK_REG);
 584         regs[43] = dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_BAD_REG);
 585         regs[44] = dsaf_read_dev(drv, GMAC_TX_UC_PKTS_REG);
 586         regs[45] = dsaf_read_dev(drv, GMAC_TX_MC_PKTS_REG);
 587         regs[46] = dsaf_read_dev(drv, GMAC_TX_BC_PKTS_REG);
 588         regs[47] = dsaf_read_dev(drv, GMAC_TX_PKTS_64OCTETS_REG);
 589         regs[48] = dsaf_read_dev(drv, GMAC_TX_PKTS_65TO127OCTETS_REG);
 590         regs[49] = dsaf_read_dev(drv, GMAC_TX_PKTS_128TO255OCTETS_REG);
 591         regs[50] = dsaf_read_dev(drv, GMAC_TX_PKTS_255TO511OCTETS_REG);
 592         regs[51] = dsaf_read_dev(drv, GMAC_TX_PKTS_512TO1023OCTETS_REG);
 593         regs[52] = dsaf_read_dev(drv, GMAC_TX_PKTS_1024TO1518OCTETS_REG);
 594         regs[53] = dsaf_read_dev(drv, GMAC_TX_PKTS_1519TOMAXOCTETS_REG);
 595         regs[54] = dsaf_read_dev(drv, GMAC_TX_EXCESSIVE_LENGTH_DROP_REG);
 596         regs[55] = dsaf_read_dev(drv, GMAC_TX_UNDERRUN_REG);
 597         regs[56] = dsaf_read_dev(drv, GMAC_TX_TAGGED_REG);
 598         regs[57] = dsaf_read_dev(drv, GMAC_TX_CRC_ERROR_REG);
 599         regs[58] = dsaf_read_dev(drv, GMAC_TX_PAUSE_FRAMES_REG);
 600
 601         regs[59] = dsaf_read_dev(drv, GAMC_RX_MAX_FRAME);
 602         regs[60] = dsaf_read_dev(drv, GMAC_LINE_LOOP_BACK_REG);
 603         regs[61] = dsaf_read_dev(drv, GMAC_CF_CRC_STRIP_REG);
 604         regs[62] = dsaf_read_dev(drv, GMAC_MODE_CHANGE_EN_REG);
 605         regs[63] = dsaf_read_dev(drv, GMAC_SIXTEEN_BIT_CNTR_REG);
 606         regs[64] = dsaf_read_dev(drv, GMAC_LD_LINK_COUNTER_REG);
 607         regs[65] = dsaf_read_dev(drv, GMAC_LOOP_REG);
 608         regs[66] = dsaf_read_dev(drv, GMAC_RECV_CONTROL_REG);
 609         regs[67] = dsaf_read_dev(drv, GMAC_VLAN_CODE_REG);
 610         regs[68] = dsaf_read_dev(drv, GMAC_RX_OVERRUN_CNT_REG);
 611         regs[69] = dsaf_read_dev(drv, GMAC_RX_LENGTHFIELD_ERR_CNT_REG);
 612         regs[70] = dsaf_read_dev(drv, GMAC_RX_FAIL_COMMA_CNT_REG);
 613
 614         regs[71] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_0_REG);
 615         regs[72] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_0_REG);
 616         regs[73] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_1_REG);
 617         regs[74] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_1_REG);
 618         regs[75] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_2_REG);
 619         regs[76] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG);
 620         regs[77] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_3_REG);
 621         regs[78] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_3_REG);
 622         regs[79] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_4_REG);
 623         regs[80] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_4_REG);
 624         regs[81] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_5_REG);
 625         regs[82] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_5_REG);
 626         regs[83] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_MSK_0_REG);
 627         regs[84] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_MSK_0_REG);
 628         regs[85] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_MSK_1_REG);
 629         regs[86] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_MSK_1_REG);
 630         regs[87] = dsaf_read_dev(drv, GMAC_MAC_SKIP_LEN_REG);
 631         regs[88] = dsaf_read_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG);
 632
 633         /* mark end of mac regs */
 634         for (i = 89; i < 96; i++)
 635                 regs[i] = 0xaaaaaaaa;
 636 }
 637
 638 static void hns_gmac_get_stats(void *mac_drv, u64 *data)
 639 {
 640         u32 i;
 641         u64 *buf = data;
 642         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 643         struct mac_hw_stats *hw_stats = NULL;
 644
 645         hw_stats = &drv->mac_cb->hw_stats;
 646
 647         for (i = 0; i < ARRAY_SIZE(g_gmac_stats_string); i++) {
 648                 buf[i] = DSAF_STATS_READ(hw_stats,
 649                         g_gmac_stats_string[i].offset);
 650         }
 651 }
 652
 653 static void hns_gmac_get_strings(u32 stringset, u8 *data)
 654 {
 655         char *buff = (char *)data;
 656         u32 i;
 657
 658         if (stringset != ETH_SS_STATS)
 659                 return;
 660
 661         for (i = 0; i < ARRAY_SIZE(g_gmac_stats_string); i++) {
 662                 snprintf(buff, ETH_GSTRING_LEN, "%s",
 663                          g_gmac_stats_string[i].desc);
 664                 buff = buff + ETH_GSTRING_LEN;
 665         }
 666 }
 667
 668 static int hns_gmac_get_sset_count(int stringset)
 669 {
 670         if (stringset == ETH_SS_STATS)
 671                 return ARRAY_SIZE(g_gmac_stats_string);
 672
 673         return 0;
 674 }
 675
 676 static int hns_gmac_get_regs_count(void)
 677 {
 678         return ETH_GMAC_DUMP_NUM;
 679 }
 680
 681 void *hns_gmac_config(struct hns_mac_cb *mac_cb, struct mac_params *mac_param)
 682 {
 683         struct mac_driver *mac_drv;
 684
 685         mac_drv = devm_kzalloc(mac_cb->dev, sizeof(*mac_drv), GFP_KERNEL);
 686         if (!mac_drv)
 687                 return NULL;
 688
 689         mac_drv->mac_init = hns_gmac_init;
 690         mac_drv->mac_enable = hns_gmac_enable;
 691         mac_drv->mac_disable = hns_gmac_disable;
 692         mac_drv->mac_free = hns_gmac_free;
 693         mac_drv->adjust_link = hns_gmac_adjust_link;
 694         mac_drv->set_tx_auto_pause_frames = hns_gmac_set_tx_auto_pause_frames;
 695         mac_drv->config_max_frame_length = hns_gmac_config_max_frame_length;
 696         mac_drv->mac_pausefrm_cfg = hns_gmac_pause_frm_cfg;
 697
 698         mac_drv->mac_id = mac_param->mac_id;
 699         mac_drv->mac_mode = mac_param->mac_mode;
 700         mac_drv->io_base = mac_param->vaddr;
 701         mac_drv->dev = mac_param->dev;
 702         mac_drv->mac_cb = mac_cb;
 703
 704         mac_drv->set_mac_addr = hns_gmac_set_mac_addr;
 705         mac_drv->set_an_mode = hns_gmac_config_an_mode;
 706         mac_drv->config_loopback = hns_gmac_config_loopback;
 707         mac_drv->config_pad_and_crc = hns_gmac_config_pad_and_crc;
 708         mac_drv->config_half_duplex = hns_gmac_set_duplex_type;
 709         mac_drv->set_rx_ignore_pause_frames = hns_gmac_set_rx_auto_pause_frames;
 710         mac_drv->get_info = hns_gmac_get_info;
 711         mac_drv->autoneg_stat = hns_gmac_autoneg_stat;
 712         mac_drv->get_pause_enable = hns_gmac_get_pausefrm_cfg;
 713         mac_drv->get_link_status = hns_gmac_get_link_status;
 714         mac_drv->get_regs = hns_gmac_get_regs;
 715         mac_drv->get_regs_count = hns_gmac_get_regs_count;
 716         mac_drv->get_ethtool_stats = hns_gmac_get_stats;
 717         mac_drv->get_sset_count = hns_gmac_get_sset_count;
 718         mac_drv->get_strings = hns_gmac_get_strings;
 719         mac_drv->update_stats = hns_gmac_update_stats;
 720         mac_drv->set_promiscuous = hns_gmac_set_promisc;
 721
 722         return (void *)mac_drv;
 723 }