2 * Copyright (c) 2014-2015 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include "hns_dsaf_misc.h"
11 #include "hns_dsaf_mac.h"
12 #include "hns_dsaf_reg.h"
13 #include "hns_dsaf_ppe.h"
15 void hns_cpld_set_led(struct hns_mac_cb
*mac_cb
, int link_status
,
22 pr_err("sfp_led_opt mac_dev is null!\n");
25 if (!mac_cb
->cpld_vaddr
) {
26 dev_err(mac_cb
->dev
, "mac_id=%d, cpld_vaddr is null !\n",
31 if (speed
== MAC_SPEED_10000
)
34 value
= mac_cb
->cpld_led_value
;
37 dsaf_set_bit(value
, DSAF_LED_LINK_B
, link_status
);
38 dsaf_set_field(value
, DSAF_LED_SPEED_M
,
39 DSAF_LED_SPEED_S
, speed_reg
);
40 dsaf_set_bit(value
, DSAF_LED_DATA_B
, data
);
42 if (value
!= mac_cb
->cpld_led_value
) {
43 dsaf_write_b(mac_cb
->cpld_vaddr
, value
);
44 mac_cb
->cpld_led_value
= value
;
47 dsaf_write_b(mac_cb
->cpld_vaddr
, CPLD_LED_DEFAULT_VALUE
);
48 mac_cb
->cpld_led_value
= CPLD_LED_DEFAULT_VALUE
;
52 void cpld_led_reset(struct hns_mac_cb
*mac_cb
)
54 if (!mac_cb
|| !mac_cb
->cpld_vaddr
)
57 dsaf_write_b(mac_cb
->cpld_vaddr
, CPLD_LED_DEFAULT_VALUE
);
58 mac_cb
->cpld_led_value
= CPLD_LED_DEFAULT_VALUE
;
61 int cpld_set_led_id(struct hns_mac_cb
*mac_cb
,
62 enum hnae_led_state status
)
66 mac_cb
->cpld_led_value
= dsaf_read_b(mac_cb
->cpld_vaddr
);
67 dsaf_set_bit(mac_cb
->cpld_led_value
, DSAF_LED_ANCHOR_B
,
69 dsaf_write_b(mac_cb
->cpld_vaddr
, mac_cb
->cpld_led_value
);
71 case HNAE_LED_INACTIVE
:
72 dsaf_set_bit(mac_cb
->cpld_led_value
, DSAF_LED_ANCHOR_B
,
73 CPLD_LED_DEFAULT_VALUE
);
74 dsaf_write_b(mac_cb
->cpld_vaddr
, mac_cb
->cpld_led_value
);
83 #define RESET_REQ_OR_DREQ 1
85 void hns_dsaf_rst(struct dsaf_device
*dsaf_dev
, u32 val
)
91 xbar_reg_addr
= DSAF_SUB_SC_XBAR_RESET_REQ_REG
;
92 nt_reg_addr
= DSAF_SUB_SC_NT_RESET_REQ_REG
;
94 xbar_reg_addr
= DSAF_SUB_SC_XBAR_RESET_DREQ_REG
;
95 nt_reg_addr
= DSAF_SUB_SC_NT_RESET_DREQ_REG
;
98 dsaf_write_reg(dsaf_dev
->sc_base
, xbar_reg_addr
,
100 dsaf_write_reg(dsaf_dev
->sc_base
, nt_reg_addr
,
104 void hns_dsaf_xge_srst_by_port(struct dsaf_device
*dsaf_dev
, u32 port
, u32 val
)
109 if (port
>= DSAF_XGE_NUM
)
112 reg_val
|= RESET_REQ_OR_DREQ
;
114 if (!HNS_DSAF_IS_DEBUG(dsaf_dev
))
115 reg_val
|= 0x2082082 << port
;
117 reg_val
|= 0x2082082 << (dsaf_dev
->reset_offset
+ 6);
120 reg_addr
= DSAF_SUB_SC_XGE_RESET_REQ_REG
;
122 reg_addr
= DSAF_SUB_SC_XGE_RESET_DREQ_REG
;
124 dsaf_write_reg(dsaf_dev
->sc_base
, reg_addr
, reg_val
);
127 void hns_dsaf_xge_core_srst_by_port(struct dsaf_device
*dsaf_dev
,
133 if (port
>= DSAF_XGE_NUM
)
136 if (!HNS_DSAF_IS_DEBUG(dsaf_dev
))
137 reg_val
|= XGMAC_TRX_CORE_SRST_M
<< port
;
139 reg_val
|= XGMAC_TRX_CORE_SRST_M
<<
140 (dsaf_dev
->reset_offset
+ 6);
143 reg_addr
= DSAF_SUB_SC_XGE_RESET_REQ_REG
;
145 reg_addr
= DSAF_SUB_SC_XGE_RESET_DREQ_REG
;
147 dsaf_write_reg(dsaf_dev
->sc_base
, reg_addr
, reg_val
);
150 void hns_dsaf_ge_srst_by_port(struct dsaf_device
*dsaf_dev
, u32 port
, u32 val
)
155 if (port
>= DSAF_GE_NUM
)
158 if (!HNS_DSAF_IS_DEBUG(dsaf_dev
)) {
159 reg_val_1
= 0x1 << port
;
160 /* there is difference between V1 and V2 in register.*/
161 if (AE_IS_VER1(dsaf_dev
->dsaf_ver
))
162 reg_val_2
= 0x1041041 << port
;
164 reg_val_2
= 0x2082082 << port
;
167 dsaf_write_reg(dsaf_dev
->sc_base
,
168 DSAF_SUB_SC_GE_RESET_REQ1_REG
,
171 dsaf_write_reg(dsaf_dev
->sc_base
,
172 DSAF_SUB_SC_GE_RESET_REQ0_REG
,
175 dsaf_write_reg(dsaf_dev
->sc_base
,
176 DSAF_SUB_SC_GE_RESET_DREQ0_REG
,
179 dsaf_write_reg(dsaf_dev
->sc_base
,
180 DSAF_SUB_SC_GE_RESET_DREQ1_REG
,
184 reg_val_1
= 0x15540 << dsaf_dev
->reset_offset
;
185 reg_val_2
= 0x100 << dsaf_dev
->reset_offset
;
188 dsaf_write_reg(dsaf_dev
->sc_base
,
189 DSAF_SUB_SC_GE_RESET_REQ1_REG
,
192 dsaf_write_reg(dsaf_dev
->sc_base
,
193 DSAF_SUB_SC_PPE_RESET_REQ_REG
,
196 dsaf_write_reg(dsaf_dev
->sc_base
,
197 DSAF_SUB_SC_GE_RESET_DREQ1_REG
,
200 dsaf_write_reg(dsaf_dev
->sc_base
,
201 DSAF_SUB_SC_PPE_RESET_DREQ_REG
,
207 void hns_ppe_srst_by_port(struct dsaf_device
*dsaf_dev
, u32 port
, u32 val
)
212 if (!HNS_DSAF_IS_DEBUG(dsaf_dev
))
213 reg_val
|= RESET_REQ_OR_DREQ
<< port
;
215 reg_val
|= RESET_REQ_OR_DREQ
<<
216 (dsaf_dev
->reset_offset
+ 6);
219 reg_addr
= DSAF_SUB_SC_PPE_RESET_REQ_REG
;
221 reg_addr
= DSAF_SUB_SC_PPE_RESET_DREQ_REG
;
223 dsaf_write_reg(dsaf_dev
->sc_base
, reg_addr
, reg_val
);
226 void hns_ppe_com_srst(struct ppe_common_cb
*ppe_common
, u32 val
)
228 struct dsaf_device
*dsaf_dev
= ppe_common
->dsaf_dev
;
232 if (!HNS_DSAF_IS_DEBUG(dsaf_dev
)) {
233 reg_val
= RESET_REQ_OR_DREQ
;
235 reg_addr
= DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG
;
237 reg_addr
= DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG
;
240 reg_val
= 0x100 << dsaf_dev
->reset_offset
;
243 reg_addr
= DSAF_SUB_SC_PPE_RESET_REQ_REG
;
245 reg_addr
= DSAF_SUB_SC_PPE_RESET_DREQ_REG
;
248 dsaf_write_reg(dsaf_dev
->sc_base
, reg_addr
, reg_val
);
252 * hns_mac_get_sds_mode - get phy ifterface form serdes mode
253 * @mac_cb: mac control block
254 * retuen phy interface
256 phy_interface_t
hns_mac_get_phy_if(struct hns_mac_cb
*mac_cb
)
262 bool is_ver1
= AE_IS_VER1(mac_cb
->dsaf_dev
->dsaf_ver
);
263 void __iomem
*sys_ctl_vaddr
= mac_cb
->sys_ctl_vaddr
;
264 int mac_id
= mac_cb
->mac_id
;
265 phy_interface_t phy_if
= PHY_INTERFACE_MODE_NA
;
267 if (is_ver1
&& HNS_DSAF_IS_DEBUG(mac_cb
->dsaf_dev
)) {
268 phy_if
= PHY_INTERFACE_MODE_SGMII
;
269 } else if (mac_id
>= 0 && mac_id
<= 3 &&
270 !HNS_DSAF_IS_DEBUG(mac_cb
->dsaf_dev
)) {
271 reg
= is_ver1
? HNS_MAC_HILINK4_REG
: HNS_MAC_HILINK4V2_REG
;
272 mode
= dsaf_read_reg(sys_ctl_vaddr
, reg
);
273 /* mac_id 0, 1, 2, 3 ---> hilink4 lane 0, 1, 2, 3 */
274 shift
= is_ver1
? 0 : mac_id
;
275 if (dsaf_get_bit(mode
, shift
))
276 phy_if
= PHY_INTERFACE_MODE_XGMII
;
278 phy_if
= PHY_INTERFACE_MODE_SGMII
;
280 reg
= is_ver1
? HNS_MAC_HILINK3_REG
: HNS_MAC_HILINK3V2_REG
;
281 mode
= dsaf_read_reg(sys_ctl_vaddr
, reg
);
282 /* mac_id 4, 5,---> hilink3 lane 2, 3
283 * debug port 0(6), 1(7) ---> hilink3 lane 0, 1
285 phy_offset
= mac_cb
->dsaf_dev
->reset_offset
- 1;
286 shift
= is_ver1
? 0 : mac_id
>= 4 ? mac_id
- 2 : phy_offset
;
287 if (dsaf_get_bit(mode
, shift
))
288 phy_if
= PHY_INTERFACE_MODE_XGMII
;
290 phy_if
= PHY_INTERFACE_MODE_SGMII
;
296 * hns_mac_config_sds_loopback - set loop back for serdes
297 * @mac_cb: mac control block
298 * retuen 0 == success
300 int hns_mac_config_sds_loopback(struct hns_mac_cb
*mac_cb
, u8 en
)
302 /* port 0-3 hilink4 base is serdes_vaddr + 0x00280000
303 * port 4-7 hilink3 base is serdes_vaddr + 0x00200000
305 u8
*base_addr
= (u8
*)mac_cb
->serdes_vaddr
+
306 (mac_cb
->mac_id
<= 3 ? 0x00280000 : 0x00200000);
307 const u8 lane_id
[] = {
308 0, /* mac 0 -> lane 0 */
309 1, /* mac 1 -> lane 1 */
310 2, /* mac 2 -> lane 2 */
311 3, /* mac 3 -> lane 3 */
312 2, /* mac 4 -> lane 2 */
313 3, /* mac 5 -> lane 3 */
314 0, /* mac 6 -> lane 0 */
315 1 /* mac 7 -> lane 1 */
317 #define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
318 u64 reg_offset
= RX_CSR(lane_id
[mac_cb
->mac_id
], 0);
321 int ret
= hns_mac_get_sfp_prsnt(mac_cb
, &sfp_prsnt
);
323 if (!mac_cb
->phy_node
) {
325 pr_info("please confirm sfp is present or not\n");
328 pr_info("no sfp in this eth\n");
331 dsaf_set_reg_field(base_addr
, reg_offset
, 1ull << 10, 10, !!en
);