drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c

   1 /*
   2  * Copyright (c) 2014-2015 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/netdevice.h>
  14 #include <linux/etherdevice.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_platform.h>
  19
  20 #include "hns_dsaf_ppe.h"
  21
  22 void hns_ppe_set_tso_enable(struct hns_ppe_cb *ppe_cb, u32 value)
  23 {
  24         dsaf_set_dev_bit(ppe_cb, PPEV2_CFG_TSO_EN_REG, 0, !!value);
  25 }
  26
  27 void hns_ppe_set_rss_key(struct hns_ppe_cb *ppe_cb,
  28                          const u32 rss_key[HNS_PPEV2_RSS_KEY_NUM])
  29 {
  30         u32 key_item;
  31
  32         for (key_item = 0; key_item < HNS_PPEV2_RSS_KEY_NUM; key_item++)
  33                 dsaf_write_dev(ppe_cb, PPEV2_RSS_KEY_REG + key_item * 0x4,
  34                                rss_key[key_item]);
  35 }
  36
  37 void hns_ppe_set_indir_table(struct hns_ppe_cb *ppe_cb,
  38                              const u32 rss_tab[HNS_PPEV2_RSS_IND_TBL_SIZE])
  39 {
  40         int i;
  41         int reg_value;
  42
  43         for (i = 0; i < (HNS_PPEV2_RSS_IND_TBL_SIZE / 4); i++) {
  44                 reg_value = dsaf_read_dev(ppe_cb,
  45                                           PPEV2_INDRECTION_TBL_REG + i * 0x4);
  46
  47                 dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N0_M,
  48                                PPEV2_CFG_RSS_TBL_4N0_S,
  49                                rss_tab[i * 4 + 0] & 0x1F);
  50                 dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N1_M,
  51                                PPEV2_CFG_RSS_TBL_4N1_S,
  52                                 rss_tab[i * 4 + 1] & 0x1F);
  53                 dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N2_M,
  54                                PPEV2_CFG_RSS_TBL_4N2_S,
  55                                 rss_tab[i * 4 + 2] & 0x1F);
  56                 dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N3_M,
  57                                PPEV2_CFG_RSS_TBL_4N3_S,
  58                                 rss_tab[i * 4 + 3] & 0x1F);
  59                 dsaf_write_dev(
  60                         ppe_cb, PPEV2_INDRECTION_TBL_REG + i * 0x4, reg_value);
  61         }
  62 }
  63
  64 static void __iomem *
  65 hns_ppe_common_get_ioaddr(struct ppe_common_cb *ppe_common)
  66 {
  67         return ppe_common->dsaf_dev->ppe_base + PPE_COMMON_REG_OFFSET;
  68 }
  69
  70 /**
  71  * hns_ppe_common_get_cfg - get ppe common config
  72  * @dsaf_dev: dasf device
  73  * comm_index: common index
  74  * retuen 0 - success , negative --fail
  75  */
  76 int hns_ppe_common_get_cfg(struct dsaf_device *dsaf_dev, int comm_index)
  77 {
  78         struct ppe_common_cb *ppe_common;
  79         int ppe_num;
  80
  81         if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
  82                 ppe_num = HNS_PPE_SERVICE_NW_ENGINE_NUM;
  83         else
  84                 ppe_num = HNS_PPE_DEBUG_NW_ENGINE_NUM;
  85
  86         ppe_common = devm_kzalloc(dsaf_dev->dev, sizeof(*ppe_common) +
  87                 ppe_num * sizeof(struct hns_ppe_cb), GFP_KERNEL);
  88         if (!ppe_common)
  89                 return -ENOMEM;
  90
  91         ppe_common->ppe_num = ppe_num;
  92         ppe_common->dsaf_dev = dsaf_dev;
  93         ppe_common->comm_index = comm_index;
  94         if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
  95                 ppe_common->ppe_mode = PPE_COMMON_MODE_SERVICE;
  96         else
  97                 ppe_common->ppe_mode = PPE_COMMON_MODE_DEBUG;
  98         ppe_common->dev = dsaf_dev->dev;
  99
 100         ppe_common->io_base = hns_ppe_common_get_ioaddr(ppe_common);
 101
 102         dsaf_dev->ppe_common[comm_index] = ppe_common;
 103
 104         return 0;
 105 }
 106
 107 void hns_ppe_common_free_cfg(struct dsaf_device *dsaf_dev, u32 comm_index)
 108 {
 109         dsaf_dev->ppe_common[comm_index] = NULL;
 110 }
 111
 112 static void __iomem *hns_ppe_get_iobase(struct ppe_common_cb *ppe_common,
 113                                         int ppe_idx)
 114 {
 115         return ppe_common->dsaf_dev->ppe_base + ppe_idx * PPE_REG_OFFSET;
 116 }
 117
 118 static void hns_ppe_get_cfg(struct ppe_common_cb *ppe_common)
 119 {
 120         u32 i;
 121         struct hns_ppe_cb *ppe_cb;
 122         u32 ppe_num = ppe_common->ppe_num;
 123
 124         for (i = 0; i < ppe_num; i++) {
 125                 ppe_cb = &ppe_common->ppe_cb[i];
 126                 ppe_cb->dev = ppe_common->dev;
 127                 ppe_cb->next = NULL;
 128                 ppe_cb->ppe_common_cb = ppe_common;
 129                 ppe_cb->index = i;
 130                 ppe_cb->io_base = hns_ppe_get_iobase(ppe_common, i);
 131                 ppe_cb->virq = 0;
 132         }
 133 }
 134
 135 static void hns_ppe_cnt_clr_ce(struct hns_ppe_cb *ppe_cb)
 136 {
 137         dsaf_set_dev_bit(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG,
 138                          PPE_CNT_CLR_CE_B, 1);
 139 }
 140
 141 static void hns_ppe_set_vlan_strip(struct hns_ppe_cb *ppe_cb, int en)
 142 {
 143         dsaf_write_dev(ppe_cb, PPEV2_VLAN_STRIP_EN_REG, en);
 144 }
 145
 146 /**
 147  * hns_ppe_checksum_hw - set ppe checksum caculate
 148  * @ppe_device: ppe device
 149  * @value: value
 150  */
 151 static void hns_ppe_checksum_hw(struct hns_ppe_cb *ppe_cb, u32 value)
 152 {
 153         dsaf_set_dev_field(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG,
 154                            0xfffffff, 0, value);
 155 }
 156
 157 static void hns_ppe_set_qid_mode(struct ppe_common_cb *ppe_common,
 158                                  enum ppe_qid_mode qid_mdoe)
 159 {
 160         dsaf_set_dev_field(ppe_common, PPE_COM_CFG_QID_MODE_REG,
 161                            PPE_CFG_QID_MODE_CF_QID_MODE_M,
 162                            PPE_CFG_QID_MODE_CF_QID_MODE_S, qid_mdoe);
 163 }
 164
 165 /**
 166  * hns_ppe_set_qid - set ppe qid
 167  * @ppe_common: ppe common device
 168  * @qid: queue id
 169  */
 170 static void hns_ppe_set_qid(struct ppe_common_cb *ppe_common, u32 qid)
 171 {
 172         u32 qid_mod = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG);
 173
 174         if (!dsaf_get_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M,
 175                             PPE_CFG_QID_MODE_DEF_QID_S)) {
 176                 dsaf_set_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M,
 177                                PPE_CFG_QID_MODE_DEF_QID_S, qid);
 178                 dsaf_write_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG, qid_mod);
 179         }
 180 }
 181
 182 /**
 183  * hns_ppe_set_port_mode - set port mode
 184  * @ppe_device: ppe device
 185  * @mode: port mode
 186  */
 187 static void hns_ppe_set_port_mode(struct hns_ppe_cb *ppe_cb,
 188                                   enum ppe_port_mode mode)
 189 {
 190         dsaf_write_dev(ppe_cb, PPE_CFG_XGE_MODE_REG, mode);
 191 }
 192
 193 /**
 194  * hns_ppe_common_init_hw - init ppe common device
 195  * @ppe_common: ppe common device
 196  *
 197  * Return 0 on success, negative on failure
 198  */
 199 static int hns_ppe_common_init_hw(struct ppe_common_cb *ppe_common)
 200 {
 201         enum ppe_qid_mode qid_mode;
 202         struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev;
 203         enum dsaf_mode dsaf_mode = dsaf_dev->dsaf_mode;
 204
 205         dsaf_dev->misc_op->ppe_comm_srst(dsaf_dev, 0);
 206         mdelay(100);
 207         dsaf_dev->misc_op->ppe_comm_srst(dsaf_dev, 1);
 208         mdelay(100);
 209
 210         if (ppe_common->ppe_mode == PPE_COMMON_MODE_SERVICE) {
 211                 switch (dsaf_mode) {
 212                 case DSAF_MODE_ENABLE_FIX:
 213                 case DSAF_MODE_DISABLE_FIX:
 214                         qid_mode = PPE_QID_MODE0;
 215                         hns_ppe_set_qid(ppe_common, 0);
 216                         break;
 217                 case DSAF_MODE_ENABLE_0VM:
 218                 case DSAF_MODE_DISABLE_2PORT_64VM:
 219                         qid_mode = PPE_QID_MODE3;
 220                         break;
 221                 case DSAF_MODE_ENABLE_8VM:
 222                 case DSAF_MODE_DISABLE_2PORT_16VM:
 223                         qid_mode = PPE_QID_MODE4;
 224                         break;
 225                 case DSAF_MODE_ENABLE_16VM:
 226                 case DSAF_MODE_DISABLE_6PORT_0VM:
 227                         qid_mode = PPE_QID_MODE5;
 228                         break;
 229                 case DSAF_MODE_ENABLE_32VM:
 230                 case DSAF_MODE_DISABLE_6PORT_16VM:
 231                         qid_mode = PPE_QID_MODE2;
 232                         break;
 233                 case DSAF_MODE_ENABLE_128VM:
 234                 case DSAF_MODE_DISABLE_6PORT_4VM:
 235                         qid_mode = PPE_QID_MODE1;
 236                         break;
 237                 case DSAF_MODE_DISABLE_2PORT_8VM:
 238                         qid_mode = PPE_QID_MODE7;
 239                         break;
 240                 case DSAF_MODE_DISABLE_6PORT_2VM:
 241                         qid_mode = PPE_QID_MODE6;
 242                         break;
 243                 default:
 244                         dev_err(ppe_common->dev,
 245                                 "get ppe queue mode failed! dsaf_mode=%d\n",
 246                                 dsaf_mode);
 247                         return -EINVAL;
 248                 }
 249                 hns_ppe_set_qid_mode(ppe_common, qid_mode);
 250         }
 251
 252         dsaf_set_dev_bit(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG,
 253                          PPE_COMMON_CNT_CLR_CE_B, 1);
 254
 255         return 0;
 256 }
 257
 258 /*clr ppe exception irq*/
 259 static void hns_ppe_exc_irq_en(struct hns_ppe_cb *ppe_cb, int en)
 260 {
 261         u32 clr_vlue = 0xfffffffful;
 262         u32 msk_vlue = en ? 0xfffffffful : 0; /*1 is en, 0 is dis*/
 263         u32 vld_msk = 0;
 264
 265         /*only care bit 0,1,7*/
 266         dsaf_set_bit(vld_msk, 0, 1);
 267         dsaf_set_bit(vld_msk, 1, 1);
 268         dsaf_set_bit(vld_msk, 7, 1);
 269
 270         /*clr sts**/
 271         dsaf_write_dev(ppe_cb, PPE_RINT_REG, clr_vlue);
 272
 273         /*for some reserved bits, so set 0**/
 274         dsaf_write_dev(ppe_cb, PPE_INTEN_REG, msk_vlue & vld_msk);
 275 }
 276
 277 /**
 278  * ppe_init_hw - init ppe
 279  * @ppe_cb: ppe device
 280  */
 281 static void hns_ppe_init_hw(struct hns_ppe_cb *ppe_cb)
 282 {
 283         struct ppe_common_cb *ppe_common_cb = ppe_cb->ppe_common_cb;
 284         u32 port = ppe_cb->index;
 285         struct dsaf_device *dsaf_dev = ppe_common_cb->dsaf_dev;
 286         int i;
 287
 288         /* get default RSS key */
 289         netdev_rss_key_fill(ppe_cb->rss_key, HNS_PPEV2_RSS_KEY_SIZE);
 290
 291         dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 0);
 292         mdelay(10);
 293         dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 1);
 294
 295         /* clr and msk except irq*/
 296         hns_ppe_exc_irq_en(ppe_cb, 0);
 297
 298         if (ppe_common_cb->ppe_mode == PPE_COMMON_MODE_DEBUG) {
 299                 hns_ppe_set_port_mode(ppe_cb, PPE_MODE_GE);
 300                 dsaf_write_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG, 0);
 301         } else {
 302                 hns_ppe_set_port_mode(ppe_cb, PPE_MODE_XGE);
 303         }
 304
 305         hns_ppe_checksum_hw(ppe_cb, 0xffffffff);
 306         hns_ppe_cnt_clr_ce(ppe_cb);
 307
 308         if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
 309                 hns_ppe_set_vlan_strip(ppe_cb, 0);
 310
 311                 dsaf_write_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG,
 312                                HNS_PPEV2_MAX_FRAME_LEN);
 313
 314                 /* set default RSS key in h/w */
 315                 hns_ppe_set_rss_key(ppe_cb, ppe_cb->rss_key);
 316
 317                 /* Set default indrection table in h/w */
 318                 for (i = 0; i < HNS_PPEV2_RSS_IND_TBL_SIZE; i++)
 319                         ppe_cb->rss_indir_table[i] = i;
 320                 hns_ppe_set_indir_table(ppe_cb, ppe_cb->rss_indir_table);
 321         }
 322 }
 323
 324 /**
 325  * ppe_uninit_hw - uninit ppe
 326  * @ppe_device: ppe device
 327  */
 328 static void hns_ppe_uninit_hw(struct hns_ppe_cb *ppe_cb)
 329 {
 330         u32 port;
 331
 332         if (ppe_cb->ppe_common_cb) {
 333                 struct dsaf_device *dsaf_dev = ppe_cb->ppe_common_cb->dsaf_dev;
 334
 335                 port = ppe_cb->index;
 336                 dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 0);
 337         }
 338 }
 339
 340 void hns_ppe_uninit_ex(struct ppe_common_cb *ppe_common)
 341 {
 342         u32 i;
 343
 344         for (i = 0; i < ppe_common->ppe_num; i++) {
 345                 if (ppe_common->dsaf_dev->mac_cb[i])
 346                         hns_ppe_uninit_hw(&ppe_common->ppe_cb[i]);
 347                 memset(&ppe_common->ppe_cb[i], 0, sizeof(struct hns_ppe_cb));
 348         }
 349 }
 350
 351 void hns_ppe_uninit(struct dsaf_device *dsaf_dev)
 352 {
 353         u32 i;
 354
 355         for (i = 0; i < HNS_PPE_COM_NUM; i++) {
 356                 if (dsaf_dev->ppe_common[i])
 357                         hns_ppe_uninit_ex(dsaf_dev->ppe_common[i]);
 358                 hns_rcb_common_free_cfg(dsaf_dev, i);
 359                 hns_ppe_common_free_cfg(dsaf_dev, i);
 360         }
 361 }
 362
 363 /**
 364  * hns_ppe_reset - reinit ppe/rcb hw
 365  * @dsaf_dev: dasf device
 366  * retuen void
 367  */
 368 void hns_ppe_reset_common(struct dsaf_device *dsaf_dev, u8 ppe_common_index)
 369 {
 370         u32 i;
 371         int ret;
 372         struct ppe_common_cb *ppe_common;
 373
 374         ppe_common = dsaf_dev->ppe_common[ppe_common_index];
 375         ret = hns_ppe_common_init_hw(ppe_common);
 376         if (ret)
 377                 return;
 378
 379         for (i = 0; i < ppe_common->ppe_num; i++) {
 380                 /* We only need to initiate ppe when the port exists */
 381                 if (dsaf_dev->mac_cb[i])
 382                         hns_ppe_init_hw(&ppe_common->ppe_cb[i]);
 383         }
 384
 385         ret = hns_rcb_common_init_hw(dsaf_dev->rcb_common[ppe_common_index]);
 386         if (ret)
 387                 return;
 388
 389         hns_rcb_common_init_commit_hw(dsaf_dev->rcb_common[ppe_common_index]);
 390 }
 391
 392 void hns_ppe_update_stats(struct hns_ppe_cb *ppe_cb)
 393 {
 394         struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats;
 395
 396         hw_stats->rx_pkts_from_sw
 397                 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG);
 398         hw_stats->rx_pkts
 399                 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG);
 400         hw_stats->rx_drop_no_bd
 401                 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG);
 402         hw_stats->rx_alloc_buf_fail
 403                 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG);
 404         hw_stats->rx_alloc_buf_wait
 405                 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG);
 406         hw_stats->rx_drop_no_buf
 407                 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG);
 408         hw_stats->rx_err_fifo_full
 409                 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG);
 410
 411         hw_stats->tx_bd_form_rcb
 412                 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG);
 413         hw_stats->tx_pkts_from_rcb
 414                 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG);
 415         hw_stats->tx_pkts
 416                 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG);
 417         hw_stats->tx_err_fifo_empty
 418                 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG);
 419         hw_stats->tx_err_checksum
 420                 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG);
 421 }
 422
 423 int hns_ppe_get_sset_count(int stringset)
 424 {
 425         if (stringset == ETH_SS_STATS)
 426                 return ETH_PPE_STATIC_NUM;
 427         return 0;
 428 }
 429
 430 int hns_ppe_get_regs_count(void)
 431 {
 432         return ETH_PPE_DUMP_NUM;
 433 }
 434
 435 /**
 436  * ppe_get_strings - get ppe srting
 437  * @ppe_device: ppe device
 438  * @stringset: string set type
 439  * @data: output string
 440  */
 441 void hns_ppe_get_strings(struct hns_ppe_cb *ppe_cb, int stringset, u8 *data)
 442 {
 443         char *buff = (char *)data;
 444         int index = ppe_cb->index;
 445
 446         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_sw_pkt", index);
 447         buff = buff + ETH_GSTRING_LEN;
 448         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_ok", index);
 449         buff = buff + ETH_GSTRING_LEN;
 450         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_drop_pkt_no_bd", index);
 451         buff = buff + ETH_GSTRING_LEN;
 452         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_alloc_buf_fail", index);
 453         buff = buff + ETH_GSTRING_LEN;
 454         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_alloc_buf_wait", index);
 455         buff = buff + ETH_GSTRING_LEN;
 456         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_drop_no_buf", index);
 457         buff = buff + ETH_GSTRING_LEN;
 458         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_err_fifo_full", index);
 459         buff = buff + ETH_GSTRING_LEN;
 460
 461         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_bd", index);
 462         buff = buff + ETH_GSTRING_LEN;
 463         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt", index);
 464         buff = buff + ETH_GSTRING_LEN;
 465         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_ok", index);
 466         buff = buff + ETH_GSTRING_LEN;
 467         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_err_fifo_empty", index);
 468         buff = buff + ETH_GSTRING_LEN;
 469         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_err_csum_fail", index);
 470 }
 471
 472 void hns_ppe_get_stats(struct hns_ppe_cb *ppe_cb, u64 *data)
 473 {
 474         u64 *regs_buff = data;
 475         struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats;
 476
 477         regs_buff[0] = hw_stats->rx_pkts_from_sw;
 478         regs_buff[1] = hw_stats->rx_pkts;
 479         regs_buff[2] = hw_stats->rx_drop_no_bd;
 480         regs_buff[3] = hw_stats->rx_alloc_buf_fail;
 481         regs_buff[4] = hw_stats->rx_alloc_buf_wait;
 482         regs_buff[5] = hw_stats->rx_drop_no_buf;
 483         regs_buff[6] = hw_stats->rx_err_fifo_full;
 484
 485         regs_buff[7] = hw_stats->tx_bd_form_rcb;
 486         regs_buff[8] = hw_stats->tx_pkts_from_rcb;
 487         regs_buff[9] = hw_stats->tx_pkts;
 488         regs_buff[10] = hw_stats->tx_err_fifo_empty;
 489         regs_buff[11] = hw_stats->tx_err_checksum;
 490 }
 491
 492 /**
 493  * hns_ppe_init - init ppe device
 494  * @dsaf_dev: dasf device
 495  * retuen 0 - success , negative --fail
 496  */
 497 int hns_ppe_init(struct dsaf_device *dsaf_dev)
 498 {
 499         int ret;
 500         int i;
 501
 502         for (i = 0; i < HNS_PPE_COM_NUM; i++) {
 503                 ret = hns_ppe_common_get_cfg(dsaf_dev, i);
 504                 if (ret)
 505                         goto get_cfg_fail;
 506
 507                 ret = hns_rcb_common_get_cfg(dsaf_dev, i);
 508                 if (ret)
 509                         goto get_cfg_fail;
 510
 511                 hns_ppe_get_cfg(dsaf_dev->ppe_common[i]);
 512
 513                 ret = hns_rcb_get_cfg(dsaf_dev->rcb_common[i]);
 514                 if (ret)
 515                         goto get_cfg_fail;
 516         }
 517
 518         for (i = 0; i < HNS_PPE_COM_NUM; i++)
 519                 hns_ppe_reset_common(dsaf_dev, i);
 520
 521         return 0;
 522
 523 get_cfg_fail:
 524         for (i = 0; i < HNS_PPE_COM_NUM; i++) {
 525                 hns_rcb_common_free_cfg(dsaf_dev, i);
 526                 hns_ppe_common_free_cfg(dsaf_dev, i);
 527         }
 528
 529         return ret;
 530 }
 531
 532 void hns_ppe_get_regs(struct hns_ppe_cb *ppe_cb, void *data)
 533 {
 534         struct ppe_common_cb *ppe_common = ppe_cb->ppe_common_cb;
 535         u32 *regs = data;
 536         u32 i;
 537         u32 offset;
 538
 539         /* ppe common registers */
 540         regs[0] = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG);
 541         regs[1] = dsaf_read_dev(ppe_common, PPE_COM_INTEN_REG);
 542         regs[2] = dsaf_read_dev(ppe_common, PPE_COM_RINT_REG);
 543         regs[3] = dsaf_read_dev(ppe_common, PPE_COM_INTSTS_REG);
 544         regs[4] = dsaf_read_dev(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG);
 545
 546         for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++) {
 547                 offset = PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG + 0x4 * i;
 548                 regs[5 + i] = dsaf_read_dev(ppe_common, offset);
 549                 offset = PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG + 0x4 * i;
 550                 regs[5 + i + DSAF_TOTAL_QUEUE_NUM]
 551                                 = dsaf_read_dev(ppe_common, offset);
 552                 offset = PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG + 0x4 * i;
 553                 regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 2]
 554                                 = dsaf_read_dev(ppe_common, offset);
 555                 offset = PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG + 0x4 * i;
 556                 regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 3]
 557                                 = dsaf_read_dev(ppe_common, offset);
 558         }
 559
 560         /* mark end of ppe regs */
 561         for (i = 521; i < 524; i++)
 562                 regs[i] = 0xeeeeeeee;
 563
 564         /* ppe channel registers */
 565         regs[525] = dsaf_read_dev(ppe_cb, PPE_CFG_TX_FIFO_THRSLD_REG);
 566         regs[526] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_THRSLD_REG);
 567         regs[527] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG);
 568         regs[528] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_SW_BP_THRSLD_REG);
 569         regs[529] = dsaf_read_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG);
 570         regs[530] = dsaf_read_dev(ppe_cb, PPE_CFG_BUS_CTRL_REG);
 571         regs[531] = dsaf_read_dev(ppe_cb, PPE_CFG_TNL_TO_BE_RST_REG);
 572         regs[532] = dsaf_read_dev(ppe_cb, PPE_CURR_TNL_CAN_RST_REG);
 573
 574         regs[533] = dsaf_read_dev(ppe_cb, PPE_CFG_XGE_MODE_REG);
 575         regs[534] = dsaf_read_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG);
 576         regs[535] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_MODE_REG);
 577         regs[536] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_VLAN_TAG_REG);
 578         regs[537] = dsaf_read_dev(ppe_cb, PPE_CFG_TAG_GEN_REG);
 579         regs[538] = dsaf_read_dev(ppe_cb, PPE_CFG_PARSE_TAG_REG);
 580         regs[539] = dsaf_read_dev(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG);
 581
 582         regs[540] = dsaf_read_dev(ppe_cb, PPE_INTEN_REG);
 583         regs[541] = dsaf_read_dev(ppe_cb, PPE_RINT_REG);
 584         regs[542] = dsaf_read_dev(ppe_cb, PPE_INTSTS_REG);
 585         regs[543] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_INT_REG);
 586
 587         regs[544] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME0_REG);
 588         regs[545] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME1_REG);
 589
 590         /* ppe static */
 591         regs[546] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG);
 592         regs[547] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG);
 593         regs[548] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG);
 594         regs[549] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG);
 595         regs[550] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG);
 596         regs[551] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG);
 597         regs[552] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG);
 598         regs[553] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG);
 599         regs[554] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG);
 600         regs[555] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG);
 601         regs[556] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG);
 602         regs[557] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG);
 603
 604         regs[558] = dsaf_read_dev(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG);
 605         regs[559] = dsaf_read_dev(ppe_cb, PPE_CFG_AXI_DBG_REG);
 606         regs[560] = dsaf_read_dev(ppe_cb, PPE_HIS_PRO_ERR_REG);
 607         regs[561] = dsaf_read_dev(ppe_cb, PPE_HIS_TNL_FIFO_ERR_REG);
 608         regs[562] = dsaf_read_dev(ppe_cb, PPE_CURR_CFF_DATA_NUM_REG);
 609         regs[563] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_ST_REG);
 610         regs[564] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_ST_REG);
 611         regs[565] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO0_REG);
 612         regs[566] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO1_REG);
 613         regs[567] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO0_REG);
 614         regs[568] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO1_REG);
 615         regs[569] = dsaf_read_dev(ppe_cb, PPE_ECO0_REG);
 616         regs[570] = dsaf_read_dev(ppe_cb, PPE_ECO1_REG);
 617         regs[571] = dsaf_read_dev(ppe_cb, PPE_ECO2_REG);
 618
 619         /* mark end of ppe regs */
 620         for (i = 572; i < 576; i++)
 621                 regs[i] = 0xeeeeeeee;
 622 }