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net: hns3: Mark expected switch fall-through
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.c
1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #include <linux/dma-mapping.h>
5 #include <linux/etherdevice.h>
6 #include <linux/interrupt.h>
7 #include <linux/if_vlan.h>
8 #include <linux/ip.h>
9 #include <linux/ipv6.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/skbuff.h>
13 #include <linux/sctp.h>
14 #include <linux/vermagic.h>
15 #include <net/gre.h>
16 #include <net/pkt_cls.h>
17 #include <net/vxlan.h>
18
19 #include "hnae3.h"
20 #include "hns3_enet.h"
21
22 static void hns3_clear_all_ring(struct hnae3_handle *h);
23 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h);
24
25 static const char hns3_driver_name[] = "hns3";
26 const char hns3_driver_version[] = VERMAGIC_STRING;
27 static const char hns3_driver_string[] =
28 "Hisilicon Ethernet Network Driver for Hip08 Family";
29 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
30 static struct hnae3_client client;
31
32 /* hns3_pci_tbl - PCI Device ID Table
33 *
34 * Last entry must be all 0s
35 *
36 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
37 * Class, Class Mask, private data (not used) }
38 */
39 static const struct pci_device_id hns3_pci_tbl[] = {
40 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
41 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
43 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
45 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
47 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
49 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
50 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
51 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
52 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
54 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
55 /* required last entry */
56 {0, }
57 };
58 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
59
60 static irqreturn_t hns3_irq_handle(int irq, void *vector)
61 {
62 struct hns3_enet_tqp_vector *tqp_vector = vector;
63
64 napi_schedule(&tqp_vector->napi);
65
66 return IRQ_HANDLED;
67 }
68
69 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
70 {
71 struct hns3_enet_tqp_vector *tqp_vectors;
72 unsigned int i;
73
74 for (i = 0; i < priv->vector_num; i++) {
75 tqp_vectors = &priv->tqp_vector[i];
76
77 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
78 continue;
79
80 /* release the irq resource */
81 free_irq(tqp_vectors->vector_irq, tqp_vectors);
82 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
83 }
84 }
85
86 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
87 {
88 struct hns3_enet_tqp_vector *tqp_vectors;
89 int txrx_int_idx = 0;
90 int rx_int_idx = 0;
91 int tx_int_idx = 0;
92 unsigned int i;
93 int ret;
94
95 for (i = 0; i < priv->vector_num; i++) {
96 tqp_vectors = &priv->tqp_vector[i];
97
98 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
99 continue;
100
101 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
102 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
103 "%s-%s-%d", priv->netdev->name, "TxRx",
104 txrx_int_idx++);
105 txrx_int_idx++;
106 } else if (tqp_vectors->rx_group.ring) {
107 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
108 "%s-%s-%d", priv->netdev->name, "Rx",
109 rx_int_idx++);
110 } else if (tqp_vectors->tx_group.ring) {
111 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
112 "%s-%s-%d", priv->netdev->name, "Tx",
113 tx_int_idx++);
114 } else {
115 /* Skip this unused q_vector */
116 continue;
117 }
118
119 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
120
121 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
122 tqp_vectors->name,
123 tqp_vectors);
124 if (ret) {
125 netdev_err(priv->netdev, "request irq(%d) fail\n",
126 tqp_vectors->vector_irq);
127 return ret;
128 }
129
130 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
131 }
132
133 return 0;
134 }
135
136 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
137 u32 mask_en)
138 {
139 writel(mask_en, tqp_vector->mask_addr);
140 }
141
142 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
143 {
144 napi_enable(&tqp_vector->napi);
145
146 /* enable vector */
147 hns3_mask_vector_irq(tqp_vector, 1);
148 }
149
150 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
151 {
152 /* disable vector */
153 hns3_mask_vector_irq(tqp_vector, 0);
154
155 disable_irq(tqp_vector->vector_irq);
156 napi_disable(&tqp_vector->napi);
157 }
158
159 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
160 u32 rl_value)
161 {
162 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
163
164 /* this defines the configuration for RL (Interrupt Rate Limiter).
165 * Rl defines rate of interrupts i.e. number of interrupts-per-second
166 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
167 */
168
169 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
170 !tqp_vector->rx_group.coal.gl_adapt_enable)
171 /* According to the hardware, the range of rl_reg is
172 * 0-59 and the unit is 4.
173 */
174 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
175
176 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
177 }
178
179 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
180 u32 gl_value)
181 {
182 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
183
184 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
185 }
186
187 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
188 u32 gl_value)
189 {
190 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
191
192 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
193 }
194
195 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
196 struct hns3_nic_priv *priv)
197 {
198 struct hnae3_handle *h = priv->ae_handle;
199
200 /* initialize the configuration for interrupt coalescing.
201 * 1. GL (Interrupt Gap Limiter)
202 * 2. RL (Interrupt Rate Limiter)
203 */
204
205 /* Default: enable interrupt coalescing self-adaptive and GL */
206 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
207 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
208
209 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
210 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
211
212 /* Default: disable RL */
213 h->kinfo.int_rl_setting = 0;
214
215 tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START;
216 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
217 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
218 }
219
220 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
221 struct hns3_nic_priv *priv)
222 {
223 struct hnae3_handle *h = priv->ae_handle;
224
225 hns3_set_vector_coalesce_tx_gl(tqp_vector,
226 tqp_vector->tx_group.coal.int_gl);
227 hns3_set_vector_coalesce_rx_gl(tqp_vector,
228 tqp_vector->rx_group.coal.int_gl);
229 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
230 }
231
232 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
233 {
234 struct hnae3_handle *h = hns3_get_handle(netdev);
235 struct hnae3_knic_private_info *kinfo = &h->kinfo;
236 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
237 int i, ret;
238
239 if (kinfo->num_tc <= 1) {
240 netdev_reset_tc(netdev);
241 } else {
242 ret = netdev_set_num_tc(netdev, kinfo->num_tc);
243 if (ret) {
244 netdev_err(netdev,
245 "netdev_set_num_tc fail, ret=%d!\n", ret);
246 return ret;
247 }
248
249 for (i = 0; i < HNAE3_MAX_TC; i++) {
250 if (!kinfo->tc_info[i].enable)
251 continue;
252
253 netdev_set_tc_queue(netdev,
254 kinfo->tc_info[i].tc,
255 kinfo->tc_info[i].tqp_count,
256 kinfo->tc_info[i].tqp_offset);
257 }
258 }
259
260 ret = netif_set_real_num_tx_queues(netdev, queue_size);
261 if (ret) {
262 netdev_err(netdev,
263 "netif_set_real_num_tx_queues fail, ret=%d!\n",
264 ret);
265 return ret;
266 }
267
268 ret = netif_set_real_num_rx_queues(netdev, queue_size);
269 if (ret) {
270 netdev_err(netdev,
271 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
272 return ret;
273 }
274
275 return 0;
276 }
277
278 static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
279 {
280 u16 free_tqps, max_rss_size, max_tqps;
281
282 h->ae_algo->ops->get_tqps_and_rss_info(h, &free_tqps, &max_rss_size);
283 max_tqps = h->kinfo.num_tc * max_rss_size;
284
285 return min_t(u16, max_tqps, (free_tqps + h->kinfo.num_tqps));
286 }
287
288 static int hns3_nic_net_up(struct net_device *netdev)
289 {
290 struct hns3_nic_priv *priv = netdev_priv(netdev);
291 struct hnae3_handle *h = priv->ae_handle;
292 int i, j;
293 int ret;
294
295 ret = hns3_nic_reset_all_ring(h);
296 if (ret)
297 return ret;
298
299 /* get irq resource for all vectors */
300 ret = hns3_nic_init_irq(priv);
301 if (ret) {
302 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret);
303 return ret;
304 }
305
306 /* enable the vectors */
307 for (i = 0; i < priv->vector_num; i++)
308 hns3_vector_enable(&priv->tqp_vector[i]);
309
310 /* start the ae_dev */
311 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
312 if (ret)
313 goto out_start_err;
314
315 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
316
317 return 0;
318
319 out_start_err:
320 for (j = i - 1; j >= 0; j--)
321 hns3_vector_disable(&priv->tqp_vector[j]);
322
323 hns3_nic_uninit_irq(priv);
324
325 return ret;
326 }
327
328 static int hns3_nic_net_open(struct net_device *netdev)
329 {
330 struct hns3_nic_priv *priv = netdev_priv(netdev);
331 struct hnae3_handle *h = hns3_get_handle(netdev);
332 struct hnae3_knic_private_info *kinfo;
333 int i, ret;
334
335 netif_carrier_off(netdev);
336
337 ret = hns3_nic_set_real_num_queue(netdev);
338 if (ret)
339 return ret;
340
341 ret = hns3_nic_net_up(netdev);
342 if (ret) {
343 netdev_err(netdev,
344 "hns net up fail, ret=%d!\n", ret);
345 return ret;
346 }
347
348 kinfo = &h->kinfo;
349 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
350 netdev_set_prio_tc_map(netdev, i,
351 kinfo->prio_tc[i]);
352 }
353
354 priv->ae_handle->last_reset_time = jiffies;
355 return 0;
356 }
357
358 static void hns3_nic_net_down(struct net_device *netdev)
359 {
360 struct hns3_nic_priv *priv = netdev_priv(netdev);
361 const struct hnae3_ae_ops *ops;
362 int i;
363
364 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
365 return;
366
367 /* disable vectors */
368 for (i = 0; i < priv->vector_num; i++)
369 hns3_vector_disable(&priv->tqp_vector[i]);
370
371 /* stop ae_dev */
372 ops = priv->ae_handle->ae_algo->ops;
373 if (ops->stop)
374 ops->stop(priv->ae_handle);
375
376 /* free irq resources */
377 hns3_nic_uninit_irq(priv);
378
379 hns3_clear_all_ring(priv->ae_handle);
380 }
381
382 static int hns3_nic_net_stop(struct net_device *netdev)
383 {
384 netif_tx_stop_all_queues(netdev);
385 netif_carrier_off(netdev);
386
387 hns3_nic_net_down(netdev);
388
389 return 0;
390 }
391
392 static int hns3_nic_uc_sync(struct net_device *netdev,
393 const unsigned char *addr)
394 {
395 struct hnae3_handle *h = hns3_get_handle(netdev);
396
397 if (h->ae_algo->ops->add_uc_addr)
398 return h->ae_algo->ops->add_uc_addr(h, addr);
399
400 return 0;
401 }
402
403 static int hns3_nic_uc_unsync(struct net_device *netdev,
404 const unsigned char *addr)
405 {
406 struct hnae3_handle *h = hns3_get_handle(netdev);
407
408 if (h->ae_algo->ops->rm_uc_addr)
409 return h->ae_algo->ops->rm_uc_addr(h, addr);
410
411 return 0;
412 }
413
414 static int hns3_nic_mc_sync(struct net_device *netdev,
415 const unsigned char *addr)
416 {
417 struct hnae3_handle *h = hns3_get_handle(netdev);
418
419 if (h->ae_algo->ops->add_mc_addr)
420 return h->ae_algo->ops->add_mc_addr(h, addr);
421
422 return 0;
423 }
424
425 static int hns3_nic_mc_unsync(struct net_device *netdev,
426 const unsigned char *addr)
427 {
428 struct hnae3_handle *h = hns3_get_handle(netdev);
429
430 if (h->ae_algo->ops->rm_mc_addr)
431 return h->ae_algo->ops->rm_mc_addr(h, addr);
432
433 return 0;
434 }
435
436 static void hns3_nic_set_rx_mode(struct net_device *netdev)
437 {
438 struct hnae3_handle *h = hns3_get_handle(netdev);
439
440 if (h->ae_algo->ops->set_promisc_mode) {
441 if (netdev->flags & IFF_PROMISC)
442 h->ae_algo->ops->set_promisc_mode(h, true, true);
443 else if (netdev->flags & IFF_ALLMULTI)
444 h->ae_algo->ops->set_promisc_mode(h, false, true);
445 else
446 h->ae_algo->ops->set_promisc_mode(h, false, false);
447 }
448 if (__dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync))
449 netdev_err(netdev, "sync uc address fail\n");
450 if (netdev->flags & IFF_MULTICAST) {
451 if (__dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync))
452 netdev_err(netdev, "sync mc address fail\n");
453
454 if (h->ae_algo->ops->update_mta_status)
455 h->ae_algo->ops->update_mta_status(h);
456 }
457 }
458
459 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
460 u16 *mss, u32 *type_cs_vlan_tso)
461 {
462 u32 l4_offset, hdr_len;
463 union l3_hdr_info l3;
464 union l4_hdr_info l4;
465 u32 l4_paylen;
466 int ret;
467
468 if (!skb_is_gso(skb))
469 return 0;
470
471 ret = skb_cow_head(skb, 0);
472 if (ret)
473 return ret;
474
475 l3.hdr = skb_network_header(skb);
476 l4.hdr = skb_transport_header(skb);
477
478 /* Software should clear the IPv4's checksum field when tso is
479 * needed.
480 */
481 if (l3.v4->version == 4)
482 l3.v4->check = 0;
483
484 /* tunnel packet.*/
485 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
486 SKB_GSO_GRE_CSUM |
487 SKB_GSO_UDP_TUNNEL |
488 SKB_GSO_UDP_TUNNEL_CSUM)) {
489 if ((!(skb_shinfo(skb)->gso_type &
490 SKB_GSO_PARTIAL)) &&
491 (skb_shinfo(skb)->gso_type &
492 SKB_GSO_UDP_TUNNEL_CSUM)) {
493 /* Software should clear the udp's checksum
494 * field when tso is needed.
495 */
496 l4.udp->check = 0;
497 }
498 /* reset l3&l4 pointers from outer to inner headers */
499 l3.hdr = skb_inner_network_header(skb);
500 l4.hdr = skb_inner_transport_header(skb);
501
502 /* Software should clear the IPv4's checksum field when
503 * tso is needed.
504 */
505 if (l3.v4->version == 4)
506 l3.v4->check = 0;
507 }
508
509 /* normal or tunnel packet*/
510 l4_offset = l4.hdr - skb->data;
511 hdr_len = (l4.tcp->doff * 4) + l4_offset;
512
513 /* remove payload length from inner pseudo checksum when tso*/
514 l4_paylen = skb->len - l4_offset;
515 csum_replace_by_diff(&l4.tcp->check,
516 (__force __wsum)htonl(l4_paylen));
517
518 /* find the txbd field values */
519 *paylen = skb->len - hdr_len;
520 hnae3_set_bit(*type_cs_vlan_tso,
521 HNS3_TXD_TSO_B, 1);
522
523 /* get MSS for TSO */
524 *mss = skb_shinfo(skb)->gso_size;
525
526 return 0;
527 }
528
529 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
530 u8 *il4_proto)
531 {
532 union {
533 struct iphdr *v4;
534 struct ipv6hdr *v6;
535 unsigned char *hdr;
536 } l3;
537 unsigned char *l4_hdr;
538 unsigned char *exthdr;
539 u8 l4_proto_tmp;
540 __be16 frag_off;
541
542 /* find outer header point */
543 l3.hdr = skb_network_header(skb);
544 l4_hdr = skb_transport_header(skb);
545
546 if (skb->protocol == htons(ETH_P_IPV6)) {
547 exthdr = l3.hdr + sizeof(*l3.v6);
548 l4_proto_tmp = l3.v6->nexthdr;
549 if (l4_hdr != exthdr)
550 ipv6_skip_exthdr(skb, exthdr - skb->data,
551 &l4_proto_tmp, &frag_off);
552 } else if (skb->protocol == htons(ETH_P_IP)) {
553 l4_proto_tmp = l3.v4->protocol;
554 } else {
555 return -EINVAL;
556 }
557
558 *ol4_proto = l4_proto_tmp;
559
560 /* tunnel packet */
561 if (!skb->encapsulation) {
562 *il4_proto = 0;
563 return 0;
564 }
565
566 /* find inner header point */
567 l3.hdr = skb_inner_network_header(skb);
568 l4_hdr = skb_inner_transport_header(skb);
569
570 if (l3.v6->version == 6) {
571 exthdr = l3.hdr + sizeof(*l3.v6);
572 l4_proto_tmp = l3.v6->nexthdr;
573 if (l4_hdr != exthdr)
574 ipv6_skip_exthdr(skb, exthdr - skb->data,
575 &l4_proto_tmp, &frag_off);
576 } else if (l3.v4->version == 4) {
577 l4_proto_tmp = l3.v4->protocol;
578 }
579
580 *il4_proto = l4_proto_tmp;
581
582 return 0;
583 }
584
585 static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto,
586 u8 il4_proto, u32 *type_cs_vlan_tso,
587 u32 *ol_type_vlan_len_msec)
588 {
589 union {
590 struct iphdr *v4;
591 struct ipv6hdr *v6;
592 unsigned char *hdr;
593 } l3;
594 union {
595 struct tcphdr *tcp;
596 struct udphdr *udp;
597 struct gre_base_hdr *gre;
598 unsigned char *hdr;
599 } l4;
600 unsigned char *l2_hdr;
601 u8 l4_proto = ol4_proto;
602 u32 ol2_len;
603 u32 ol3_len;
604 u32 ol4_len;
605 u32 l2_len;
606 u32 l3_len;
607
608 l3.hdr = skb_network_header(skb);
609 l4.hdr = skb_transport_header(skb);
610
611 /* compute L2 header size for normal packet, defined in 2 Bytes */
612 l2_len = l3.hdr - skb->data;
613 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
614 HNS3_TXD_L2LEN_S, l2_len >> 1);
615
616 /* tunnel packet*/
617 if (skb->encapsulation) {
618 /* compute OL2 header size, defined in 2 Bytes */
619 ol2_len = l2_len;
620 hnae3_set_field(*ol_type_vlan_len_msec,
621 HNS3_TXD_L2LEN_M,
622 HNS3_TXD_L2LEN_S, ol2_len >> 1);
623
624 /* compute OL3 header size, defined in 4 Bytes */
625 ol3_len = l4.hdr - l3.hdr;
626 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_M,
627 HNS3_TXD_L3LEN_S, ol3_len >> 2);
628
629 /* MAC in UDP, MAC in GRE (0x6558)*/
630 if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) {
631 /* switch MAC header ptr from outer to inner header.*/
632 l2_hdr = skb_inner_mac_header(skb);
633
634 /* compute OL4 header size, defined in 4 Bytes. */
635 ol4_len = l2_hdr - l4.hdr;
636 hnae3_set_field(*ol_type_vlan_len_msec,
637 HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
638 ol4_len >> 2);
639
640 /* switch IP header ptr from outer to inner header */
641 l3.hdr = skb_inner_network_header(skb);
642
643 /* compute inner l2 header size, defined in 2 Bytes. */
644 l2_len = l3.hdr - l2_hdr;
645 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
646 HNS3_TXD_L2LEN_S, l2_len >> 1);
647 } else {
648 /* skb packet types not supported by hardware,
649 * txbd len fild doesn't be filled.
650 */
651 return;
652 }
653
654 /* switch L4 header pointer from outer to inner */
655 l4.hdr = skb_inner_transport_header(skb);
656
657 l4_proto = il4_proto;
658 }
659
660 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
661 l3_len = l4.hdr - l3.hdr;
662 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_M,
663 HNS3_TXD_L3LEN_S, l3_len >> 2);
664
665 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
666 switch (l4_proto) {
667 case IPPROTO_TCP:
668 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
669 HNS3_TXD_L4LEN_S, l4.tcp->doff);
670 break;
671 case IPPROTO_SCTP:
672 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
673 HNS3_TXD_L4LEN_S,
674 (sizeof(struct sctphdr) >> 2));
675 break;
676 case IPPROTO_UDP:
677 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
678 HNS3_TXD_L4LEN_S,
679 (sizeof(struct udphdr) >> 2));
680 break;
681 default:
682 /* skb packet types not supported by hardware,
683 * txbd len fild doesn't be filled.
684 */
685 return;
686 }
687 }
688
689 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
690 * and it is udp packet, which has a dest port as the IANA assigned.
691 * the hardware is expected to do the checksum offload, but the
692 * hardware will not do the checksum offload when udp dest port is
693 * 4789.
694 */
695 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
696 {
697 #define IANA_VXLAN_PORT 4789
698 union {
699 struct tcphdr *tcp;
700 struct udphdr *udp;
701 struct gre_base_hdr *gre;
702 unsigned char *hdr;
703 } l4;
704
705 l4.hdr = skb_transport_header(skb);
706
707 if (!(!skb->encapsulation && l4.udp->dest == htons(IANA_VXLAN_PORT)))
708 return false;
709
710 skb_checksum_help(skb);
711
712 return true;
713 }
714
715 static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto,
716 u8 il4_proto, u32 *type_cs_vlan_tso,
717 u32 *ol_type_vlan_len_msec)
718 {
719 union {
720 struct iphdr *v4;
721 struct ipv6hdr *v6;
722 unsigned char *hdr;
723 } l3;
724 u32 l4_proto = ol4_proto;
725
726 l3.hdr = skb_network_header(skb);
727
728 /* define OL3 type and tunnel type(OL4).*/
729 if (skb->encapsulation) {
730 /* define outer network header type.*/
731 if (skb->protocol == htons(ETH_P_IP)) {
732 if (skb_is_gso(skb))
733 hnae3_set_field(*ol_type_vlan_len_msec,
734 HNS3_TXD_OL3T_M,
735 HNS3_TXD_OL3T_S,
736 HNS3_OL3T_IPV4_CSUM);
737 else
738 hnae3_set_field(*ol_type_vlan_len_msec,
739 HNS3_TXD_OL3T_M,
740 HNS3_TXD_OL3T_S,
741 HNS3_OL3T_IPV4_NO_CSUM);
742
743 } else if (skb->protocol == htons(ETH_P_IPV6)) {
744 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_M,
745 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV6);
746 }
747
748 /* define tunnel type(OL4).*/
749 switch (l4_proto) {
750 case IPPROTO_UDP:
751 hnae3_set_field(*ol_type_vlan_len_msec,
752 HNS3_TXD_TUNTYPE_M,
753 HNS3_TXD_TUNTYPE_S,
754 HNS3_TUN_MAC_IN_UDP);
755 break;
756 case IPPROTO_GRE:
757 hnae3_set_field(*ol_type_vlan_len_msec,
758 HNS3_TXD_TUNTYPE_M,
759 HNS3_TXD_TUNTYPE_S,
760 HNS3_TUN_NVGRE);
761 break;
762 default:
763 /* drop the skb tunnel packet if hardware don't support,
764 * because hardware can't calculate csum when TSO.
765 */
766 if (skb_is_gso(skb))
767 return -EDOM;
768
769 /* the stack computes the IP header already,
770 * driver calculate l4 checksum when not TSO.
771 */
772 skb_checksum_help(skb);
773 return 0;
774 }
775
776 l3.hdr = skb_inner_network_header(skb);
777 l4_proto = il4_proto;
778 }
779
780 if (l3.v4->version == 4) {
781 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
782 HNS3_TXD_L3T_S, HNS3_L3T_IPV4);
783
784 /* the stack computes the IP header already, the only time we
785 * need the hardware to recompute it is in the case of TSO.
786 */
787 if (skb_is_gso(skb))
788 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
789 } else if (l3.v6->version == 6) {
790 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
791 HNS3_TXD_L3T_S, HNS3_L3T_IPV6);
792 }
793
794 switch (l4_proto) {
795 case IPPROTO_TCP:
796 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
797 hnae3_set_field(*type_cs_vlan_tso,
798 HNS3_TXD_L4T_M,
799 HNS3_TXD_L4T_S,
800 HNS3_L4T_TCP);
801 break;
802 case IPPROTO_UDP:
803 if (hns3_tunnel_csum_bug(skb))
804 break;
805
806 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
807 hnae3_set_field(*type_cs_vlan_tso,
808 HNS3_TXD_L4T_M,
809 HNS3_TXD_L4T_S,
810 HNS3_L4T_UDP);
811 break;
812 case IPPROTO_SCTP:
813 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
814 hnae3_set_field(*type_cs_vlan_tso,
815 HNS3_TXD_L4T_M,
816 HNS3_TXD_L4T_S,
817 HNS3_L4T_SCTP);
818 break;
819 default:
820 /* drop the skb tunnel packet if hardware don't support,
821 * because hardware can't calculate csum when TSO.
822 */
823 if (skb_is_gso(skb))
824 return -EDOM;
825
826 /* the stack computes the IP header already,
827 * driver calculate l4 checksum when not TSO.
828 */
829 skb_checksum_help(skb);
830 return 0;
831 }
832
833 return 0;
834 }
835
836 static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end)
837 {
838 /* Config bd buffer end */
839 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_BDTYPE_M,
840 HNS3_TXD_BDTYPE_S, 0);
841 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end);
842 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1);
843 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_SC_M, HNS3_TXD_SC_S, 0);
844 }
845
846 static int hns3_fill_desc_vtags(struct sk_buff *skb,
847 struct hns3_enet_ring *tx_ring,
848 u32 *inner_vlan_flag,
849 u32 *out_vlan_flag,
850 u16 *inner_vtag,
851 u16 *out_vtag)
852 {
853 #define HNS3_TX_VLAN_PRIO_SHIFT 13
854
855 if (skb->protocol == htons(ETH_P_8021Q) &&
856 !(tx_ring->tqp->handle->kinfo.netdev->features &
857 NETIF_F_HW_VLAN_CTAG_TX)) {
858 /* When HW VLAN acceleration is turned off, and the stack
859 * sets the protocol to 802.1q, the driver just need to
860 * set the protocol to the encapsulated ethertype.
861 */
862 skb->protocol = vlan_get_protocol(skb);
863 return 0;
864 }
865
866 if (skb_vlan_tag_present(skb)) {
867 u16 vlan_tag;
868
869 vlan_tag = skb_vlan_tag_get(skb);
870 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT;
871
872 /* Based on hw strategy, use out_vtag in two layer tag case,
873 * and use inner_vtag in one tag case.
874 */
875 if (skb->protocol == htons(ETH_P_8021Q)) {
876 hnae3_set_bit(*out_vlan_flag, HNS3_TXD_OVLAN_B, 1);
877 *out_vtag = vlan_tag;
878 } else {
879 hnae3_set_bit(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1);
880 *inner_vtag = vlan_tag;
881 }
882 } else if (skb->protocol == htons(ETH_P_8021Q)) {
883 struct vlan_ethhdr *vhdr;
884 int rc;
885
886 rc = skb_cow_head(skb, 0);
887 if (rc < 0)
888 return rc;
889 vhdr = (struct vlan_ethhdr *)skb->data;
890 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7)
891 << HNS3_TX_VLAN_PRIO_SHIFT);
892 }
893
894 skb->protocol = vlan_get_protocol(skb);
895 return 0;
896 }
897
898 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
899 int size, dma_addr_t dma, int frag_end,
900 enum hns_desc_type type)
901 {
902 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
903 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
904 u32 ol_type_vlan_len_msec = 0;
905 u16 bdtp_fe_sc_vld_ra_ri = 0;
906 u32 type_cs_vlan_tso = 0;
907 struct sk_buff *skb;
908 u16 inner_vtag = 0;
909 u16 out_vtag = 0;
910 u32 paylen = 0;
911 u16 mss = 0;
912 u8 ol4_proto;
913 u8 il4_proto;
914 int ret;
915
916 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
917 desc_cb->priv = priv;
918 desc_cb->length = size;
919 desc_cb->dma = dma;
920 desc_cb->type = type;
921
922 /* now, fill the descriptor */
923 desc->addr = cpu_to_le64(dma);
924 desc->tx.send_size = cpu_to_le16((u16)size);
925 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, frag_end);
926 desc->tx.bdtp_fe_sc_vld_ra_ri = cpu_to_le16(bdtp_fe_sc_vld_ra_ri);
927
928 if (type == DESC_TYPE_SKB) {
929 skb = (struct sk_buff *)priv;
930 paylen = skb->len;
931
932 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso,
933 &ol_type_vlan_len_msec,
934 &inner_vtag, &out_vtag);
935 if (unlikely(ret))
936 return ret;
937
938 if (skb->ip_summed == CHECKSUM_PARTIAL) {
939 skb_reset_mac_len(skb);
940
941 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
942 if (ret)
943 return ret;
944 hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto,
945 &type_cs_vlan_tso,
946 &ol_type_vlan_len_msec);
947 ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto,
948 &type_cs_vlan_tso,
949 &ol_type_vlan_len_msec);
950 if (ret)
951 return ret;
952
953 ret = hns3_set_tso(skb, &paylen, &mss,
954 &type_cs_vlan_tso);
955 if (ret)
956 return ret;
957 }
958
959 /* Set txbd */
960 desc->tx.ol_type_vlan_len_msec =
961 cpu_to_le32(ol_type_vlan_len_msec);
962 desc->tx.type_cs_vlan_tso_len =
963 cpu_to_le32(type_cs_vlan_tso);
964 desc->tx.paylen = cpu_to_le32(paylen);
965 desc->tx.mss = cpu_to_le16(mss);
966 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
967 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
968 }
969
970 /* move ring pointer to next.*/
971 ring_ptr_move_fw(ring, next_to_use);
972
973 return 0;
974 }
975
976 static int hns3_fill_desc_tso(struct hns3_enet_ring *ring, void *priv,
977 int size, dma_addr_t dma, int frag_end,
978 enum hns_desc_type type)
979 {
980 unsigned int frag_buf_num;
981 unsigned int k;
982 int sizeoflast;
983 int ret;
984
985 frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
986 sizeoflast = size % HNS3_MAX_BD_SIZE;
987 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
988
989 /* When the frag size is bigger than hardware, split this frag */
990 for (k = 0; k < frag_buf_num; k++) {
991 ret = hns3_fill_desc(ring, priv,
992 (k == frag_buf_num - 1) ?
993 sizeoflast : HNS3_MAX_BD_SIZE,
994 dma + HNS3_MAX_BD_SIZE * k,
995 frag_end && (k == frag_buf_num - 1) ? 1 : 0,
996 (type == DESC_TYPE_SKB && !k) ?
997 DESC_TYPE_SKB : DESC_TYPE_PAGE);
998 if (ret)
999 return ret;
1000 }
1001
1002 return 0;
1003 }
1004
1005 static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum,
1006 struct hns3_enet_ring *ring)
1007 {
1008 struct sk_buff *skb = *out_skb;
1009 struct skb_frag_struct *frag;
1010 int bdnum_for_frag;
1011 int frag_num;
1012 int buf_num;
1013 int size;
1014 int i;
1015
1016 size = skb_headlen(skb);
1017 buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1018
1019 frag_num = skb_shinfo(skb)->nr_frags;
1020 for (i = 0; i < frag_num; i++) {
1021 frag = &skb_shinfo(skb)->frags[i];
1022 size = skb_frag_size(frag);
1023 bdnum_for_frag =
1024 (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1025 if (bdnum_for_frag > HNS3_MAX_BD_PER_FRAG)
1026 return -ENOMEM;
1027
1028 buf_num += bdnum_for_frag;
1029 }
1030
1031 if (buf_num > ring_space(ring))
1032 return -EBUSY;
1033
1034 *bnum = buf_num;
1035 return 0;
1036 }
1037
1038 static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum,
1039 struct hns3_enet_ring *ring)
1040 {
1041 struct sk_buff *skb = *out_skb;
1042 int buf_num;
1043
1044 /* No. of segments (plus a header) */
1045 buf_num = skb_shinfo(skb)->nr_frags + 1;
1046
1047 if (buf_num > ring_space(ring))
1048 return -EBUSY;
1049
1050 *bnum = buf_num;
1051
1052 return 0;
1053 }
1054
1055 static void hns_nic_dma_unmap(struct hns3_enet_ring *ring, int next_to_use_orig)
1056 {
1057 struct device *dev = ring_to_dev(ring);
1058 unsigned int i;
1059
1060 for (i = 0; i < ring->desc_num; i++) {
1061 /* check if this is where we started */
1062 if (ring->next_to_use == next_to_use_orig)
1063 break;
1064
1065 /* unmap the descriptor dma address */
1066 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB)
1067 dma_unmap_single(dev,
1068 ring->desc_cb[ring->next_to_use].dma,
1069 ring->desc_cb[ring->next_to_use].length,
1070 DMA_TO_DEVICE);
1071 else
1072 dma_unmap_page(dev,
1073 ring->desc_cb[ring->next_to_use].dma,
1074 ring->desc_cb[ring->next_to_use].length,
1075 DMA_TO_DEVICE);
1076
1077 /* rollback one */
1078 ring_ptr_move_bw(ring, next_to_use);
1079 }
1080 }
1081
1082 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
1083 {
1084 struct hns3_nic_priv *priv = netdev_priv(netdev);
1085 struct hns3_nic_ring_data *ring_data =
1086 &tx_ring_data(priv, skb->queue_mapping);
1087 struct hns3_enet_ring *ring = ring_data->ring;
1088 struct device *dev = priv->dev;
1089 struct netdev_queue *dev_queue;
1090 struct skb_frag_struct *frag;
1091 int next_to_use_head;
1092 int next_to_use_frag;
1093 dma_addr_t dma;
1094 int buf_num;
1095 int seg_num;
1096 int size;
1097 int ret;
1098 int i;
1099
1100 /* Prefetch the data used later */
1101 prefetch(skb->data);
1102
1103 switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) {
1104 case -EBUSY:
1105 u64_stats_update_begin(&ring->syncp);
1106 ring->stats.tx_busy++;
1107 u64_stats_update_end(&ring->syncp);
1108
1109 goto out_net_tx_busy;
1110 case -ENOMEM:
1111 u64_stats_update_begin(&ring->syncp);
1112 ring->stats.sw_err_cnt++;
1113 u64_stats_update_end(&ring->syncp);
1114 netdev_err(netdev, "no memory to xmit!\n");
1115
1116 goto out_err_tx_ok;
1117 default:
1118 break;
1119 }
1120
1121 /* No. of segments (plus a header) */
1122 seg_num = skb_shinfo(skb)->nr_frags + 1;
1123 /* Fill the first part */
1124 size = skb_headlen(skb);
1125
1126 next_to_use_head = ring->next_to_use;
1127
1128 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1129 if (dma_mapping_error(dev, dma)) {
1130 netdev_err(netdev, "TX head DMA map failed\n");
1131 ring->stats.sw_err_cnt++;
1132 goto out_err_tx_ok;
1133 }
1134
1135 ret = priv->ops.fill_desc(ring, skb, size, dma, seg_num == 1 ? 1 : 0,
1136 DESC_TYPE_SKB);
1137 if (ret)
1138 goto head_dma_map_err;
1139
1140 next_to_use_frag = ring->next_to_use;
1141 /* Fill the fragments */
1142 for (i = 1; i < seg_num; i++) {
1143 frag = &skb_shinfo(skb)->frags[i - 1];
1144 size = skb_frag_size(frag);
1145 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1146 if (dma_mapping_error(dev, dma)) {
1147 netdev_err(netdev, "TX frag(%d) DMA map failed\n", i);
1148 ring->stats.sw_err_cnt++;
1149 goto frag_dma_map_err;
1150 }
1151 ret = priv->ops.fill_desc(ring, skb_frag_page(frag), size, dma,
1152 seg_num - 1 == i ? 1 : 0,
1153 DESC_TYPE_PAGE);
1154
1155 if (ret)
1156 goto frag_dma_map_err;
1157 }
1158
1159 /* Complete translate all packets */
1160 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index);
1161 netdev_tx_sent_queue(dev_queue, skb->len);
1162
1163 wmb(); /* Commit all data before submit */
1164
1165 hnae3_queue_xmit(ring->tqp, buf_num);
1166
1167 return NETDEV_TX_OK;
1168
1169 frag_dma_map_err:
1170 hns_nic_dma_unmap(ring, next_to_use_frag);
1171
1172 head_dma_map_err:
1173 hns_nic_dma_unmap(ring, next_to_use_head);
1174
1175 out_err_tx_ok:
1176 dev_kfree_skb_any(skb);
1177 return NETDEV_TX_OK;
1178
1179 out_net_tx_busy:
1180 netif_stop_subqueue(netdev, ring_data->queue_index);
1181 smp_mb(); /* Commit all data before submit */
1182
1183 return NETDEV_TX_BUSY;
1184 }
1185
1186 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1187 {
1188 struct hnae3_handle *h = hns3_get_handle(netdev);
1189 struct sockaddr *mac_addr = p;
1190 int ret;
1191
1192 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1193 return -EADDRNOTAVAIL;
1194
1195 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1196 netdev_info(netdev, "already using mac address %pM\n",
1197 mac_addr->sa_data);
1198 return 0;
1199 }
1200
1201 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
1202 if (ret) {
1203 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1204 return ret;
1205 }
1206
1207 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1208
1209 return 0;
1210 }
1211
1212 static int hns3_nic_set_features(struct net_device *netdev,
1213 netdev_features_t features)
1214 {
1215 netdev_features_t changed = netdev->features ^ features;
1216 struct hns3_nic_priv *priv = netdev_priv(netdev);
1217 struct hnae3_handle *h = priv->ae_handle;
1218 int ret;
1219
1220 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) {
1221 if (features & (NETIF_F_TSO | NETIF_F_TSO6)) {
1222 priv->ops.fill_desc = hns3_fill_desc_tso;
1223 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
1224 } else {
1225 priv->ops.fill_desc = hns3_fill_desc;
1226 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
1227 }
1228 }
1229
1230 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
1231 h->ae_algo->ops->enable_vlan_filter) {
1232 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1233 h->ae_algo->ops->enable_vlan_filter(h, true);
1234 else
1235 h->ae_algo->ops->enable_vlan_filter(h, false);
1236 }
1237
1238 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1239 h->ae_algo->ops->enable_hw_strip_rxvtag) {
1240 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1241 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, true);
1242 else
1243 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, false);
1244
1245 if (ret)
1246 return ret;
1247 }
1248
1249 netdev->features = features;
1250 return 0;
1251 }
1252
1253 static void hns3_nic_get_stats64(struct net_device *netdev,
1254 struct rtnl_link_stats64 *stats)
1255 {
1256 struct hns3_nic_priv *priv = netdev_priv(netdev);
1257 int queue_num = priv->ae_handle->kinfo.num_tqps;
1258 struct hnae3_handle *handle = priv->ae_handle;
1259 struct hns3_enet_ring *ring;
1260 unsigned int start;
1261 unsigned int idx;
1262 u64 tx_bytes = 0;
1263 u64 rx_bytes = 0;
1264 u64 tx_pkts = 0;
1265 u64 rx_pkts = 0;
1266 u64 tx_drop = 0;
1267 u64 rx_drop = 0;
1268
1269 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1270 return;
1271
1272 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1273
1274 for (idx = 0; idx < queue_num; idx++) {
1275 /* fetch the tx stats */
1276 ring = priv->ring_data[idx].ring;
1277 do {
1278 start = u64_stats_fetch_begin_irq(&ring->syncp);
1279 tx_bytes += ring->stats.tx_bytes;
1280 tx_pkts += ring->stats.tx_pkts;
1281 tx_drop += ring->stats.tx_busy;
1282 tx_drop += ring->stats.sw_err_cnt;
1283 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1284
1285 /* fetch the rx stats */
1286 ring = priv->ring_data[idx + queue_num].ring;
1287 do {
1288 start = u64_stats_fetch_begin_irq(&ring->syncp);
1289 rx_bytes += ring->stats.rx_bytes;
1290 rx_pkts += ring->stats.rx_pkts;
1291 rx_drop += ring->stats.non_vld_descs;
1292 rx_drop += ring->stats.err_pkt_len;
1293 rx_drop += ring->stats.l2_err;
1294 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1295 }
1296
1297 stats->tx_bytes = tx_bytes;
1298 stats->tx_packets = tx_pkts;
1299 stats->rx_bytes = rx_bytes;
1300 stats->rx_packets = rx_pkts;
1301
1302 stats->rx_errors = netdev->stats.rx_errors;
1303 stats->multicast = netdev->stats.multicast;
1304 stats->rx_length_errors = netdev->stats.rx_length_errors;
1305 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
1306 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1307
1308 stats->tx_errors = netdev->stats.tx_errors;
1309 stats->rx_dropped = rx_drop + netdev->stats.rx_dropped;
1310 stats->tx_dropped = tx_drop + netdev->stats.tx_dropped;
1311 stats->collisions = netdev->stats.collisions;
1312 stats->rx_over_errors = netdev->stats.rx_over_errors;
1313 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1314 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1315 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1316 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1317 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1318 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1319 stats->tx_window_errors = netdev->stats.tx_window_errors;
1320 stats->rx_compressed = netdev->stats.rx_compressed;
1321 stats->tx_compressed = netdev->stats.tx_compressed;
1322 }
1323
1324 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
1325 {
1326 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
1327 struct hnae3_handle *h = hns3_get_handle(netdev);
1328 struct hnae3_knic_private_info *kinfo = &h->kinfo;
1329 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
1330 u8 tc = mqprio_qopt->qopt.num_tc;
1331 u16 mode = mqprio_qopt->mode;
1332 u8 hw = mqprio_qopt->qopt.hw;
1333 bool if_running;
1334 int ret;
1335
1336 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1337 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1338 return -EOPNOTSUPP;
1339
1340 if (tc > HNAE3_MAX_TC)
1341 return -EINVAL;
1342
1343 if (!netdev)
1344 return -EINVAL;
1345
1346 if_running = netif_running(netdev);
1347 if (if_running) {
1348 hns3_nic_net_stop(netdev);
1349 msleep(100);
1350 }
1351
1352 ret = (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
1353 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP;
1354 if (ret)
1355 goto out;
1356
1357 ret = hns3_nic_set_real_num_queue(netdev);
1358
1359 out:
1360 if (if_running)
1361 hns3_nic_net_open(netdev);
1362
1363 return ret;
1364 }
1365
1366 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
1367 void *type_data)
1368 {
1369 if (type != TC_SETUP_QDISC_MQPRIO)
1370 return -EOPNOTSUPP;
1371
1372 return hns3_setup_tc(dev, type_data);
1373 }
1374
1375 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1376 __be16 proto, u16 vid)
1377 {
1378 struct hnae3_handle *h = hns3_get_handle(netdev);
1379 struct hns3_nic_priv *priv = netdev_priv(netdev);
1380 int ret = -EIO;
1381
1382 if (h->ae_algo->ops->set_vlan_filter)
1383 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1384
1385 if (!ret)
1386 set_bit(vid, priv->active_vlans);
1387
1388 return ret;
1389 }
1390
1391 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1392 __be16 proto, u16 vid)
1393 {
1394 struct hnae3_handle *h = hns3_get_handle(netdev);
1395 struct hns3_nic_priv *priv = netdev_priv(netdev);
1396 int ret = -EIO;
1397
1398 if (h->ae_algo->ops->set_vlan_filter)
1399 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1400
1401 if (!ret)
1402 clear_bit(vid, priv->active_vlans);
1403
1404 return ret;
1405 }
1406
1407 static void hns3_restore_vlan(struct net_device *netdev)
1408 {
1409 struct hns3_nic_priv *priv = netdev_priv(netdev);
1410 u16 vid;
1411 int ret;
1412
1413 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
1414 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
1415 if (ret)
1416 netdev_warn(netdev, "Restore vlan: %d filter, ret:%d\n",
1417 vid, ret);
1418 }
1419 }
1420
1421 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1422 u8 qos, __be16 vlan_proto)
1423 {
1424 struct hnae3_handle *h = hns3_get_handle(netdev);
1425 int ret = -EIO;
1426
1427 if (h->ae_algo->ops->set_vf_vlan_filter)
1428 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
1429 qos, vlan_proto);
1430
1431 return ret;
1432 }
1433
1434 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1435 {
1436 struct hnae3_handle *h = hns3_get_handle(netdev);
1437 bool if_running = netif_running(netdev);
1438 int ret;
1439
1440 if (!h->ae_algo->ops->set_mtu)
1441 return -EOPNOTSUPP;
1442
1443 /* if this was called with netdev up then bring netdevice down */
1444 if (if_running) {
1445 (void)hns3_nic_net_stop(netdev);
1446 msleep(100);
1447 }
1448
1449 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
1450 if (ret) {
1451 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1452 ret);
1453 return ret;
1454 }
1455
1456 netdev->mtu = new_mtu;
1457
1458 /* if the netdev was running earlier, bring it up again */
1459 if (if_running && hns3_nic_net_open(netdev))
1460 ret = -EINVAL;
1461
1462 return ret;
1463 }
1464
1465 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1466 {
1467 struct hns3_nic_priv *priv = netdev_priv(ndev);
1468 struct hns3_enet_ring *tx_ring = NULL;
1469 int timeout_queue = 0;
1470 int hw_head, hw_tail;
1471 int i;
1472
1473 /* Find the stopped queue the same way the stack does */
1474 for (i = 0; i < ndev->real_num_tx_queues; i++) {
1475 struct netdev_queue *q;
1476 unsigned long trans_start;
1477
1478 q = netdev_get_tx_queue(ndev, i);
1479 trans_start = q->trans_start;
1480 if (netif_xmit_stopped(q) &&
1481 time_after(jiffies,
1482 (trans_start + ndev->watchdog_timeo))) {
1483 timeout_queue = i;
1484 break;
1485 }
1486 }
1487
1488 if (i == ndev->num_tx_queues) {
1489 netdev_info(ndev,
1490 "no netdev TX timeout queue found, timeout count: %llu\n",
1491 priv->tx_timeout_count);
1492 return false;
1493 }
1494
1495 tx_ring = priv->ring_data[timeout_queue].ring;
1496
1497 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1498 HNS3_RING_TX_RING_HEAD_REG);
1499 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1500 HNS3_RING_TX_RING_TAIL_REG);
1501 netdev_info(ndev,
1502 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n",
1503 priv->tx_timeout_count,
1504 timeout_queue,
1505 tx_ring->next_to_use,
1506 tx_ring->next_to_clean,
1507 hw_head,
1508 hw_tail,
1509 readl(tx_ring->tqp_vector->mask_addr));
1510
1511 return true;
1512 }
1513
1514 static void hns3_nic_net_timeout(struct net_device *ndev)
1515 {
1516 struct hns3_nic_priv *priv = netdev_priv(ndev);
1517 struct hnae3_handle *h = priv->ae_handle;
1518
1519 if (!hns3_get_tx_timeo_queue_info(ndev))
1520 return;
1521
1522 priv->tx_timeout_count++;
1523
1524 if (time_before(jiffies, (h->last_reset_time + ndev->watchdog_timeo)))
1525 return;
1526
1527 /* request the reset */
1528 if (h->ae_algo->ops->reset_event)
1529 h->ae_algo->ops->reset_event(h);
1530 }
1531
1532 static const struct net_device_ops hns3_nic_netdev_ops = {
1533 .ndo_open = hns3_nic_net_open,
1534 .ndo_stop = hns3_nic_net_stop,
1535 .ndo_start_xmit = hns3_nic_net_xmit,
1536 .ndo_tx_timeout = hns3_nic_net_timeout,
1537 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
1538 .ndo_change_mtu = hns3_nic_change_mtu,
1539 .ndo_set_features = hns3_nic_set_features,
1540 .ndo_get_stats64 = hns3_nic_get_stats64,
1541 .ndo_setup_tc = hns3_nic_setup_tc,
1542 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
1543 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
1544 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
1545 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
1546 };
1547
1548 static bool hns3_is_phys_func(struct pci_dev *pdev)
1549 {
1550 u32 dev_id = pdev->device;
1551
1552 switch (dev_id) {
1553 case HNAE3_DEV_ID_GE:
1554 case HNAE3_DEV_ID_25GE:
1555 case HNAE3_DEV_ID_25GE_RDMA:
1556 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
1557 case HNAE3_DEV_ID_50GE_RDMA:
1558 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
1559 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
1560 return true;
1561 case HNAE3_DEV_ID_100G_VF:
1562 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
1563 return false;
1564 default:
1565 dev_warn(&pdev->dev, "un-recognized pci device-id %d",
1566 dev_id);
1567 }
1568
1569 return false;
1570 }
1571
1572 static void hns3_disable_sriov(struct pci_dev *pdev)
1573 {
1574 /* If our VFs are assigned we cannot shut down SR-IOV
1575 * without causing issues, so just leave the hardware
1576 * available but disabled
1577 */
1578 if (pci_vfs_assigned(pdev)) {
1579 dev_warn(&pdev->dev,
1580 "disabling driver while VFs are assigned\n");
1581 return;
1582 }
1583
1584 pci_disable_sriov(pdev);
1585 }
1586
1587 /* hns3_probe - Device initialization routine
1588 * @pdev: PCI device information struct
1589 * @ent: entry in hns3_pci_tbl
1590 *
1591 * hns3_probe initializes a PF identified by a pci_dev structure.
1592 * The OS initialization, configuring of the PF private structure,
1593 * and a hardware reset occur.
1594 *
1595 * Returns 0 on success, negative on failure
1596 */
1597 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1598 {
1599 struct hnae3_ae_dev *ae_dev;
1600 int ret;
1601
1602 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev),
1603 GFP_KERNEL);
1604 if (!ae_dev) {
1605 ret = -ENOMEM;
1606 return ret;
1607 }
1608
1609 ae_dev->pdev = pdev;
1610 ae_dev->flag = ent->driver_data;
1611 ae_dev->dev_type = HNAE3_DEV_KNIC;
1612 pci_set_drvdata(pdev, ae_dev);
1613
1614 hnae3_register_ae_dev(ae_dev);
1615
1616 return 0;
1617 }
1618
1619 /* hns3_remove - Device removal routine
1620 * @pdev: PCI device information struct
1621 */
1622 static void hns3_remove(struct pci_dev *pdev)
1623 {
1624 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1625
1626 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
1627 hns3_disable_sriov(pdev);
1628
1629 hnae3_unregister_ae_dev(ae_dev);
1630 }
1631
1632 /**
1633 * hns3_pci_sriov_configure
1634 * @pdev: pointer to a pci_dev structure
1635 * @num_vfs: number of VFs to allocate
1636 *
1637 * Enable or change the number of VFs. Called when the user updates the number
1638 * of VFs in sysfs.
1639 **/
1640 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
1641 {
1642 int ret;
1643
1644 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
1645 dev_warn(&pdev->dev, "Can not config SRIOV\n");
1646 return -EINVAL;
1647 }
1648
1649 if (num_vfs) {
1650 ret = pci_enable_sriov(pdev, num_vfs);
1651 if (ret)
1652 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
1653 else
1654 return num_vfs;
1655 } else if (!pci_vfs_assigned(pdev)) {
1656 pci_disable_sriov(pdev);
1657 } else {
1658 dev_warn(&pdev->dev,
1659 "Unable to free VFs because some are assigned to VMs.\n");
1660 }
1661
1662 return 0;
1663 }
1664
1665 static struct pci_driver hns3_driver = {
1666 .name = hns3_driver_name,
1667 .id_table = hns3_pci_tbl,
1668 .probe = hns3_probe,
1669 .remove = hns3_remove,
1670 .sriov_configure = hns3_pci_sriov_configure,
1671 };
1672
1673 /* set default feature to hns3 */
1674 static void hns3_set_default_feature(struct net_device *netdev)
1675 {
1676 struct hnae3_handle *h = hns3_get_handle(netdev);
1677 struct pci_dev *pdev = h->pdev;
1678
1679 netdev->priv_flags |= IFF_UNICAST_FLT;
1680
1681 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1682 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1683 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1684 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1685 NETIF_F_GSO_UDP_TUNNEL_CSUM;
1686
1687 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
1688
1689 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
1690
1691 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1692 NETIF_F_HW_VLAN_CTAG_FILTER |
1693 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
1694 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1695 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1696 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1697 NETIF_F_GSO_UDP_TUNNEL_CSUM;
1698
1699 netdev->vlan_features |=
1700 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
1701 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
1702 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1703 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1704 NETIF_F_GSO_UDP_TUNNEL_CSUM;
1705
1706 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1707 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
1708 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1709 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1710 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1711 NETIF_F_GSO_UDP_TUNNEL_CSUM;
1712
1713 if (pdev->revision != 0x20)
1714 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1715 }
1716
1717 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
1718 struct hns3_desc_cb *cb)
1719 {
1720 unsigned int order = hnae3_page_order(ring);
1721 struct page *p;
1722
1723 p = dev_alloc_pages(order);
1724 if (!p)
1725 return -ENOMEM;
1726
1727 cb->priv = p;
1728 cb->page_offset = 0;
1729 cb->reuse_flag = 0;
1730 cb->buf = page_address(p);
1731 cb->length = hnae3_page_size(ring);
1732 cb->type = DESC_TYPE_PAGE;
1733
1734 return 0;
1735 }
1736
1737 static void hns3_free_buffer(struct hns3_enet_ring *ring,
1738 struct hns3_desc_cb *cb)
1739 {
1740 if (cb->type == DESC_TYPE_SKB)
1741 dev_kfree_skb_any((struct sk_buff *)cb->priv);
1742 else if (!HNAE3_IS_TX_RING(ring))
1743 put_page((struct page *)cb->priv);
1744 memset(cb, 0, sizeof(*cb));
1745 }
1746
1747 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
1748 {
1749 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
1750 cb->length, ring_to_dma_dir(ring));
1751
1752 if (dma_mapping_error(ring_to_dev(ring), cb->dma))
1753 return -EIO;
1754
1755 return 0;
1756 }
1757
1758 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
1759 struct hns3_desc_cb *cb)
1760 {
1761 if (cb->type == DESC_TYPE_SKB)
1762 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
1763 ring_to_dma_dir(ring));
1764 else
1765 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
1766 ring_to_dma_dir(ring));
1767 }
1768
1769 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
1770 {
1771 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
1772 ring->desc[i].addr = 0;
1773 }
1774
1775 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
1776 {
1777 struct hns3_desc_cb *cb = &ring->desc_cb[i];
1778
1779 if (!ring->desc_cb[i].dma)
1780 return;
1781
1782 hns3_buffer_detach(ring, i);
1783 hns3_free_buffer(ring, cb);
1784 }
1785
1786 static void hns3_free_buffers(struct hns3_enet_ring *ring)
1787 {
1788 int i;
1789
1790 for (i = 0; i < ring->desc_num; i++)
1791 hns3_free_buffer_detach(ring, i);
1792 }
1793
1794 /* free desc along with its attached buffer */
1795 static void hns3_free_desc(struct hns3_enet_ring *ring)
1796 {
1797 int size = ring->desc_num * sizeof(ring->desc[0]);
1798
1799 hns3_free_buffers(ring);
1800
1801 if (ring->desc) {
1802 dma_free_coherent(ring_to_dev(ring), size,
1803 ring->desc, ring->desc_dma_addr);
1804 ring->desc = NULL;
1805 }
1806 }
1807
1808 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
1809 {
1810 int size = ring->desc_num * sizeof(ring->desc[0]);
1811
1812 ring->desc = dma_zalloc_coherent(ring_to_dev(ring), size,
1813 &ring->desc_dma_addr,
1814 GFP_KERNEL);
1815 if (!ring->desc)
1816 return -ENOMEM;
1817
1818 return 0;
1819 }
1820
1821 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
1822 struct hns3_desc_cb *cb)
1823 {
1824 int ret;
1825
1826 ret = hns3_alloc_buffer(ring, cb);
1827 if (ret)
1828 goto out;
1829
1830 ret = hns3_map_buffer(ring, cb);
1831 if (ret)
1832 goto out_with_buf;
1833
1834 return 0;
1835
1836 out_with_buf:
1837 hns3_free_buffer(ring, cb);
1838 out:
1839 return ret;
1840 }
1841
1842 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
1843 {
1844 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
1845
1846 if (ret)
1847 return ret;
1848
1849 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
1850
1851 return 0;
1852 }
1853
1854 /* Allocate memory for raw pkg, and map with dma */
1855 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
1856 {
1857 int i, j, ret;
1858
1859 for (i = 0; i < ring->desc_num; i++) {
1860 ret = hns3_alloc_buffer_attach(ring, i);
1861 if (ret)
1862 goto out_buffer_fail;
1863 }
1864
1865 return 0;
1866
1867 out_buffer_fail:
1868 for (j = i - 1; j >= 0; j--)
1869 hns3_free_buffer_detach(ring, j);
1870 return ret;
1871 }
1872
1873 /* detach a in-used buffer and replace with a reserved one */
1874 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
1875 struct hns3_desc_cb *res_cb)
1876 {
1877 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
1878 ring->desc_cb[i] = *res_cb;
1879 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
1880 ring->desc[i].rx.bd_base_info = 0;
1881 }
1882
1883 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
1884 {
1885 ring->desc_cb[i].reuse_flag = 0;
1886 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma
1887 + ring->desc_cb[i].page_offset);
1888 ring->desc[i].rx.bd_base_info = 0;
1889 }
1890
1891 static void hns3_nic_reclaim_one_desc(struct hns3_enet_ring *ring, int *bytes,
1892 int *pkts)
1893 {
1894 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
1895
1896 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
1897 (*bytes) += desc_cb->length;
1898 /* desc_cb will be cleaned, after hnae3_free_buffer_detach*/
1899 hns3_free_buffer_detach(ring, ring->next_to_clean);
1900
1901 ring_ptr_move_fw(ring, next_to_clean);
1902 }
1903
1904 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
1905 {
1906 int u = ring->next_to_use;
1907 int c = ring->next_to_clean;
1908
1909 if (unlikely(h > ring->desc_num))
1910 return 0;
1911
1912 return u > c ? (h > c && h <= u) : (h > c || h <= u);
1913 }
1914
1915 bool hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget)
1916 {
1917 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
1918 struct netdev_queue *dev_queue;
1919 int bytes, pkts;
1920 int head;
1921
1922 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
1923 rmb(); /* Make sure head is ready before touch any data */
1924
1925 if (is_ring_empty(ring) || head == ring->next_to_clean)
1926 return true; /* no data to poll */
1927
1928 if (unlikely(!is_valid_clean_head(ring, head))) {
1929 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head,
1930 ring->next_to_use, ring->next_to_clean);
1931
1932 u64_stats_update_begin(&ring->syncp);
1933 ring->stats.io_err_cnt++;
1934 u64_stats_update_end(&ring->syncp);
1935 return true;
1936 }
1937
1938 bytes = 0;
1939 pkts = 0;
1940 while (head != ring->next_to_clean && budget) {
1941 hns3_nic_reclaim_one_desc(ring, &bytes, &pkts);
1942 /* Issue prefetch for next Tx descriptor */
1943 prefetch(&ring->desc_cb[ring->next_to_clean]);
1944 budget--;
1945 }
1946
1947 ring->tqp_vector->tx_group.total_bytes += bytes;
1948 ring->tqp_vector->tx_group.total_packets += pkts;
1949
1950 u64_stats_update_begin(&ring->syncp);
1951 ring->stats.tx_bytes += bytes;
1952 ring->stats.tx_pkts += pkts;
1953 u64_stats_update_end(&ring->syncp);
1954
1955 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
1956 netdev_tx_completed_queue(dev_queue, pkts, bytes);
1957
1958 if (unlikely(pkts && netif_carrier_ok(netdev) &&
1959 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) {
1960 /* Make sure that anybody stopping the queue after this
1961 * sees the new next_to_clean.
1962 */
1963 smp_mb();
1964 if (netif_tx_queue_stopped(dev_queue)) {
1965 netif_tx_wake_queue(dev_queue);
1966 ring->stats.restart_queue++;
1967 }
1968 }
1969
1970 return !!budget;
1971 }
1972
1973 static int hns3_desc_unused(struct hns3_enet_ring *ring)
1974 {
1975 int ntc = ring->next_to_clean;
1976 int ntu = ring->next_to_use;
1977
1978 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
1979 }
1980
1981 static void
1982 hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count)
1983 {
1984 struct hns3_desc_cb *desc_cb;
1985 struct hns3_desc_cb res_cbs;
1986 int i, ret;
1987
1988 for (i = 0; i < cleand_count; i++) {
1989 desc_cb = &ring->desc_cb[ring->next_to_use];
1990 if (desc_cb->reuse_flag) {
1991 u64_stats_update_begin(&ring->syncp);
1992 ring->stats.reuse_pg_cnt++;
1993 u64_stats_update_end(&ring->syncp);
1994
1995 hns3_reuse_buffer(ring, ring->next_to_use);
1996 } else {
1997 ret = hns3_reserve_buffer_map(ring, &res_cbs);
1998 if (ret) {
1999 u64_stats_update_begin(&ring->syncp);
2000 ring->stats.sw_err_cnt++;
2001 u64_stats_update_end(&ring->syncp);
2002
2003 netdev_err(ring->tqp->handle->kinfo.netdev,
2004 "hnae reserve buffer map failed.\n");
2005 break;
2006 }
2007 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
2008 }
2009
2010 ring_ptr_move_fw(ring, next_to_use);
2011 }
2012
2013 wmb(); /* Make all data has been write before submit */
2014 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2015 }
2016
2017 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2018 struct hns3_enet_ring *ring, int pull_len,
2019 struct hns3_desc_cb *desc_cb)
2020 {
2021 struct hns3_desc *desc;
2022 int truesize, size;
2023 int last_offset;
2024 bool twobufs;
2025
2026 twobufs = ((PAGE_SIZE < 8192) &&
2027 hnae3_buf_size(ring) == HNS3_BUFFER_SIZE_2048);
2028
2029 desc = &ring->desc[ring->next_to_clean];
2030 size = le16_to_cpu(desc->rx.size);
2031
2032 truesize = hnae3_buf_size(ring);
2033
2034 if (!twobufs)
2035 last_offset = hnae3_page_size(ring) - hnae3_buf_size(ring);
2036
2037 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
2038 size - pull_len, truesize);
2039
2040 /* Avoid re-using remote pages,flag default unreuse */
2041 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id()))
2042 return;
2043
2044 if (twobufs) {
2045 /* If we are only owner of page we can reuse it */
2046 if (likely(page_count(desc_cb->priv) == 1)) {
2047 /* Flip page offset to other buffer */
2048 desc_cb->page_offset ^= truesize;
2049
2050 desc_cb->reuse_flag = 1;
2051 /* bump ref count on page before it is given*/
2052 get_page(desc_cb->priv);
2053 }
2054 return;
2055 }
2056
2057 /* Move offset up to the next cache line */
2058 desc_cb->page_offset += truesize;
2059
2060 if (desc_cb->page_offset <= last_offset) {
2061 desc_cb->reuse_flag = 1;
2062 /* Bump ref count on page before it is given*/
2063 get_page(desc_cb->priv);
2064 }
2065 }
2066
2067 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
2068 struct hns3_desc *desc)
2069 {
2070 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2071 int l3_type, l4_type;
2072 u32 bd_base_info;
2073 int ol4_type;
2074 u32 l234info;
2075
2076 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2077 l234info = le32_to_cpu(desc->rx.l234_info);
2078
2079 skb->ip_summed = CHECKSUM_NONE;
2080
2081 skb_checksum_none_assert(skb);
2082
2083 if (!(netdev->features & NETIF_F_RXCSUM))
2084 return;
2085
2086 /* check if hardware has done checksum */
2087 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_L3L4P_B))
2088 return;
2089
2090 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L3E_B) ||
2091 hnae3_get_bit(l234info, HNS3_RXD_L4E_B) ||
2092 hnae3_get_bit(l234info, HNS3_RXD_OL3E_B) ||
2093 hnae3_get_bit(l234info, HNS3_RXD_OL4E_B))) {
2094 netdev_err(netdev, "L3/L4 error pkt\n");
2095 u64_stats_update_begin(&ring->syncp);
2096 ring->stats.l3l4_csum_err++;
2097 u64_stats_update_end(&ring->syncp);
2098
2099 return;
2100 }
2101
2102 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2103 HNS3_RXD_L3ID_S);
2104 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2105 HNS3_RXD_L4ID_S);
2106
2107 ol4_type = hnae3_get_field(l234info, HNS3_RXD_OL4ID_M,
2108 HNS3_RXD_OL4ID_S);
2109 switch (ol4_type) {
2110 case HNS3_OL4_TYPE_MAC_IN_UDP:
2111 case HNS3_OL4_TYPE_NVGRE:
2112 skb->csum_level = 1;
2113 /* fall through */
2114 case HNS3_OL4_TYPE_NO_TUN:
2115 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
2116 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2117 l3_type == HNS3_L3_TYPE_IPV6) &&
2118 (l4_type == HNS3_L4_TYPE_UDP ||
2119 l4_type == HNS3_L4_TYPE_TCP ||
2120 l4_type == HNS3_L4_TYPE_SCTP))
2121 skb->ip_summed = CHECKSUM_UNNECESSARY;
2122 break;
2123 }
2124 }
2125
2126 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2127 {
2128 napi_gro_receive(&ring->tqp_vector->napi, skb);
2129 }
2130
2131 static u16 hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2132 struct hns3_desc *desc, u32 l234info)
2133 {
2134 struct pci_dev *pdev = ring->tqp->handle->pdev;
2135 u16 vlan_tag;
2136
2137 if (pdev->revision == 0x20) {
2138 vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2139 if (!(vlan_tag & VLAN_VID_MASK))
2140 vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2141
2142 return vlan_tag;
2143 }
2144
2145 #define HNS3_STRP_OUTER_VLAN 0x1
2146 #define HNS3_STRP_INNER_VLAN 0x2
2147
2148 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2149 HNS3_RXD_STRP_TAGP_S)) {
2150 case HNS3_STRP_OUTER_VLAN:
2151 vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2152 break;
2153 case HNS3_STRP_INNER_VLAN:
2154 vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2155 break;
2156 default:
2157 vlan_tag = 0;
2158 break;
2159 }
2160
2161 return vlan_tag;
2162 }
2163
2164 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
2165 struct sk_buff **out_skb, int *out_bnum)
2166 {
2167 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2168 struct hns3_desc_cb *desc_cb;
2169 struct hns3_desc *desc;
2170 struct sk_buff *skb;
2171 unsigned char *va;
2172 u32 bd_base_info;
2173 int pull_len;
2174 u32 l234info;
2175 int length;
2176 int bnum;
2177
2178 desc = &ring->desc[ring->next_to_clean];
2179 desc_cb = &ring->desc_cb[ring->next_to_clean];
2180
2181 prefetch(desc);
2182
2183 length = le16_to_cpu(desc->rx.size);
2184 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2185
2186 /* Check valid BD */
2187 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B)))
2188 return -EFAULT;
2189
2190 va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
2191
2192 /* Prefetch first cache line of first page
2193 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
2194 * line size is 64B so need to prefetch twice to make it 128B. But in
2195 * actual we can have greater size of caches with 128B Level 1 cache
2196 * lines. In such a case, single fetch would suffice to cache in the
2197 * relevant part of the header.
2198 */
2199 prefetch(va);
2200 #if L1_CACHE_BYTES < 128
2201 prefetch(va + L1_CACHE_BYTES);
2202 #endif
2203
2204 skb = *out_skb = napi_alloc_skb(&ring->tqp_vector->napi,
2205 HNS3_RX_HEAD_SIZE);
2206 if (unlikely(!skb)) {
2207 netdev_err(netdev, "alloc rx skb fail\n");
2208
2209 u64_stats_update_begin(&ring->syncp);
2210 ring->stats.sw_err_cnt++;
2211 u64_stats_update_end(&ring->syncp);
2212
2213 return -ENOMEM;
2214 }
2215
2216 prefetchw(skb->data);
2217
2218 bnum = 1;
2219 if (length <= HNS3_RX_HEAD_SIZE) {
2220 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2221
2222 /* We can reuse buffer as-is, just make sure it is local */
2223 if (likely(page_to_nid(desc_cb->priv) == numa_node_id()))
2224 desc_cb->reuse_flag = 1;
2225 else /* This page cannot be reused so discard it */
2226 put_page(desc_cb->priv);
2227
2228 ring_ptr_move_fw(ring, next_to_clean);
2229 } else {
2230 u64_stats_update_begin(&ring->syncp);
2231 ring->stats.seg_pkt_cnt++;
2232 u64_stats_update_end(&ring->syncp);
2233
2234 pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE);
2235
2236 memcpy(__skb_put(skb, pull_len), va,
2237 ALIGN(pull_len, sizeof(long)));
2238
2239 hns3_nic_reuse_page(skb, 0, ring, pull_len, desc_cb);
2240 ring_ptr_move_fw(ring, next_to_clean);
2241
2242 while (!hnae3_get_bit(bd_base_info, HNS3_RXD_FE_B)) {
2243 desc = &ring->desc[ring->next_to_clean];
2244 desc_cb = &ring->desc_cb[ring->next_to_clean];
2245 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2246 hns3_nic_reuse_page(skb, bnum, ring, 0, desc_cb);
2247 ring_ptr_move_fw(ring, next_to_clean);
2248 bnum++;
2249 }
2250 }
2251
2252 *out_bnum = bnum;
2253
2254 l234info = le32_to_cpu(desc->rx.l234_info);
2255
2256 /* Based on hw strategy, the tag offloaded will be stored at
2257 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2258 * in one layer tag case.
2259 */
2260 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
2261 u16 vlan_tag;
2262
2263 vlan_tag = hns3_parse_vlan_tag(ring, desc, l234info);
2264 if (vlan_tag & VLAN_VID_MASK)
2265 __vlan_hwaccel_put_tag(skb,
2266 htons(ETH_P_8021Q),
2267 vlan_tag);
2268 }
2269
2270 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) {
2271 netdev_err(netdev, "no valid bd,%016llx,%016llx\n",
2272 ((u64 *)desc)[0], ((u64 *)desc)[1]);
2273 u64_stats_update_begin(&ring->syncp);
2274 ring->stats.non_vld_descs++;
2275 u64_stats_update_end(&ring->syncp);
2276
2277 dev_kfree_skb_any(skb);
2278 return -EINVAL;
2279 }
2280
2281 if (unlikely((!desc->rx.pkt_len) ||
2282 hnae3_get_bit(l234info, HNS3_RXD_TRUNCAT_B))) {
2283 netdev_err(netdev, "truncated pkt\n");
2284 u64_stats_update_begin(&ring->syncp);
2285 ring->stats.err_pkt_len++;
2286 u64_stats_update_end(&ring->syncp);
2287
2288 dev_kfree_skb_any(skb);
2289 return -EFAULT;
2290 }
2291
2292 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L2E_B))) {
2293 netdev_err(netdev, "L2 error pkt\n");
2294 u64_stats_update_begin(&ring->syncp);
2295 ring->stats.l2_err++;
2296 u64_stats_update_end(&ring->syncp);
2297
2298 dev_kfree_skb_any(skb);
2299 return -EFAULT;
2300 }
2301
2302 u64_stats_update_begin(&ring->syncp);
2303 ring->stats.rx_pkts++;
2304 ring->stats.rx_bytes += skb->len;
2305 u64_stats_update_end(&ring->syncp);
2306
2307 ring->tqp_vector->rx_group.total_bytes += skb->len;
2308
2309 hns3_rx_checksum(ring, skb, desc);
2310 return 0;
2311 }
2312
2313 int hns3_clean_rx_ring(
2314 struct hns3_enet_ring *ring, int budget,
2315 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
2316 {
2317 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
2318 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2319 int recv_pkts, recv_bds, clean_count, err;
2320 int unused_count = hns3_desc_unused(ring);
2321 struct sk_buff *skb = NULL;
2322 int num, bnum = 0;
2323
2324 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
2325 rmb(); /* Make sure num taken effect before the other data is touched */
2326
2327 recv_pkts = 0, recv_bds = 0, clean_count = 0;
2328 num -= unused_count;
2329
2330 while (recv_pkts < budget && recv_bds < num) {
2331 /* Reuse or realloc buffers */
2332 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
2333 hns3_nic_alloc_rx_buffers(ring,
2334 clean_count + unused_count);
2335 clean_count = 0;
2336 unused_count = hns3_desc_unused(ring);
2337 }
2338
2339 /* Poll one pkt */
2340 err = hns3_handle_rx_bd(ring, &skb, &bnum);
2341 if (unlikely(!skb)) /* This fault cannot be repaired */
2342 goto out;
2343
2344 recv_bds += bnum;
2345 clean_count += bnum;
2346 if (unlikely(err)) { /* Do jump the err */
2347 recv_pkts++;
2348 continue;
2349 }
2350
2351 /* Do update ip stack process */
2352 skb->protocol = eth_type_trans(skb, netdev);
2353 rx_fn(ring, skb);
2354
2355 recv_pkts++;
2356 }
2357
2358 out:
2359 /* Make all data has been write before submit */
2360 if (clean_count + unused_count > 0)
2361 hns3_nic_alloc_rx_buffers(ring,
2362 clean_count + unused_count);
2363
2364 return recv_pkts;
2365 }
2366
2367 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
2368 {
2369 struct hns3_enet_tqp_vector *tqp_vector =
2370 ring_group->ring->tqp_vector;
2371 enum hns3_flow_level_range new_flow_level;
2372 int packets_per_msecs;
2373 int bytes_per_msecs;
2374 u32 time_passed_ms;
2375 u16 new_int_gl;
2376
2377 if (!ring_group->coal.int_gl || !tqp_vector->last_jiffies)
2378 return false;
2379
2380 if (ring_group->total_packets == 0) {
2381 ring_group->coal.int_gl = HNS3_INT_GL_50K;
2382 ring_group->coal.flow_level = HNS3_FLOW_LOW;
2383 return true;
2384 }
2385
2386 /* Simple throttlerate management
2387 * 0-10MB/s lower (50000 ints/s)
2388 * 10-20MB/s middle (20000 ints/s)
2389 * 20-1249MB/s high (18000 ints/s)
2390 * > 40000pps ultra (8000 ints/s)
2391 */
2392 new_flow_level = ring_group->coal.flow_level;
2393 new_int_gl = ring_group->coal.int_gl;
2394 time_passed_ms =
2395 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
2396
2397 if (!time_passed_ms)
2398 return false;
2399
2400 do_div(ring_group->total_packets, time_passed_ms);
2401 packets_per_msecs = ring_group->total_packets;
2402
2403 do_div(ring_group->total_bytes, time_passed_ms);
2404 bytes_per_msecs = ring_group->total_bytes;
2405
2406 #define HNS3_RX_LOW_BYTE_RATE 10000
2407 #define HNS3_RX_MID_BYTE_RATE 20000
2408
2409 switch (new_flow_level) {
2410 case HNS3_FLOW_LOW:
2411 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
2412 new_flow_level = HNS3_FLOW_MID;
2413 break;
2414 case HNS3_FLOW_MID:
2415 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
2416 new_flow_level = HNS3_FLOW_HIGH;
2417 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
2418 new_flow_level = HNS3_FLOW_LOW;
2419 break;
2420 case HNS3_FLOW_HIGH:
2421 case HNS3_FLOW_ULTRA:
2422 default:
2423 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
2424 new_flow_level = HNS3_FLOW_MID;
2425 break;
2426 }
2427
2428 #define HNS3_RX_ULTRA_PACKET_RATE 40
2429
2430 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
2431 &tqp_vector->rx_group == ring_group)
2432 new_flow_level = HNS3_FLOW_ULTRA;
2433
2434 switch (new_flow_level) {
2435 case HNS3_FLOW_LOW:
2436 new_int_gl = HNS3_INT_GL_50K;
2437 break;
2438 case HNS3_FLOW_MID:
2439 new_int_gl = HNS3_INT_GL_20K;
2440 break;
2441 case HNS3_FLOW_HIGH:
2442 new_int_gl = HNS3_INT_GL_18K;
2443 break;
2444 case HNS3_FLOW_ULTRA:
2445 new_int_gl = HNS3_INT_GL_8K;
2446 break;
2447 default:
2448 break;
2449 }
2450
2451 ring_group->total_bytes = 0;
2452 ring_group->total_packets = 0;
2453 ring_group->coal.flow_level = new_flow_level;
2454 if (new_int_gl != ring_group->coal.int_gl) {
2455 ring_group->coal.int_gl = new_int_gl;
2456 return true;
2457 }
2458 return false;
2459 }
2460
2461 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
2462 {
2463 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
2464 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
2465 bool rx_update, tx_update;
2466
2467 if (tqp_vector->int_adapt_down > 0) {
2468 tqp_vector->int_adapt_down--;
2469 return;
2470 }
2471
2472 if (rx_group->coal.gl_adapt_enable) {
2473 rx_update = hns3_get_new_int_gl(rx_group);
2474 if (rx_update)
2475 hns3_set_vector_coalesce_rx_gl(tqp_vector,
2476 rx_group->coal.int_gl);
2477 }
2478
2479 if (tx_group->coal.gl_adapt_enable) {
2480 tx_update = hns3_get_new_int_gl(&tqp_vector->tx_group);
2481 if (tx_update)
2482 hns3_set_vector_coalesce_tx_gl(tqp_vector,
2483 tx_group->coal.int_gl);
2484 }
2485
2486 tqp_vector->last_jiffies = jiffies;
2487 tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START;
2488 }
2489
2490 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
2491 {
2492 struct hns3_enet_ring *ring;
2493 int rx_pkt_total = 0;
2494
2495 struct hns3_enet_tqp_vector *tqp_vector =
2496 container_of(napi, struct hns3_enet_tqp_vector, napi);
2497 bool clean_complete = true;
2498 int rx_budget;
2499
2500 /* Since the actual Tx work is minimal, we can give the Tx a larger
2501 * budget and be more aggressive about cleaning up the Tx descriptors.
2502 */
2503 hns3_for_each_ring(ring, tqp_vector->tx_group) {
2504 if (!hns3_clean_tx_ring(ring, budget))
2505 clean_complete = false;
2506 }
2507
2508 /* make sure rx ring budget not smaller than 1 */
2509 rx_budget = max(budget / tqp_vector->num_tqps, 1);
2510
2511 hns3_for_each_ring(ring, tqp_vector->rx_group) {
2512 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
2513 hns3_rx_skb);
2514
2515 if (rx_cleaned >= rx_budget)
2516 clean_complete = false;
2517
2518 rx_pkt_total += rx_cleaned;
2519 }
2520
2521 tqp_vector->rx_group.total_packets += rx_pkt_total;
2522
2523 if (!clean_complete)
2524 return budget;
2525
2526 napi_complete(napi);
2527 hns3_update_new_int_gl(tqp_vector);
2528 hns3_mask_vector_irq(tqp_vector, 1);
2529
2530 return rx_pkt_total;
2531 }
2532
2533 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
2534 struct hnae3_ring_chain_node *head)
2535 {
2536 struct pci_dev *pdev = tqp_vector->handle->pdev;
2537 struct hnae3_ring_chain_node *cur_chain = head;
2538 struct hnae3_ring_chain_node *chain;
2539 struct hns3_enet_ring *tx_ring;
2540 struct hns3_enet_ring *rx_ring;
2541
2542 tx_ring = tqp_vector->tx_group.ring;
2543 if (tx_ring) {
2544 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
2545 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2546 HNAE3_RING_TYPE_TX);
2547 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2548 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
2549
2550 cur_chain->next = NULL;
2551
2552 while (tx_ring->next) {
2553 tx_ring = tx_ring->next;
2554
2555 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
2556 GFP_KERNEL);
2557 if (!chain)
2558 return -ENOMEM;
2559
2560 cur_chain->next = chain;
2561 chain->tqp_index = tx_ring->tqp->tqp_index;
2562 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2563 HNAE3_RING_TYPE_TX);
2564 hnae3_set_field(chain->int_gl_idx,
2565 HNAE3_RING_GL_IDX_M,
2566 HNAE3_RING_GL_IDX_S,
2567 HNAE3_RING_GL_TX);
2568
2569 cur_chain = chain;
2570 }
2571 }
2572
2573 rx_ring = tqp_vector->rx_group.ring;
2574 if (!tx_ring && rx_ring) {
2575 cur_chain->next = NULL;
2576 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
2577 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2578 HNAE3_RING_TYPE_RX);
2579 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2580 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
2581
2582 rx_ring = rx_ring->next;
2583 }
2584
2585 while (rx_ring) {
2586 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
2587 if (!chain)
2588 return -ENOMEM;
2589
2590 cur_chain->next = chain;
2591 chain->tqp_index = rx_ring->tqp->tqp_index;
2592 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2593 HNAE3_RING_TYPE_RX);
2594 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2595 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
2596
2597 cur_chain = chain;
2598
2599 rx_ring = rx_ring->next;
2600 }
2601
2602 return 0;
2603 }
2604
2605 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
2606 struct hnae3_ring_chain_node *head)
2607 {
2608 struct pci_dev *pdev = tqp_vector->handle->pdev;
2609 struct hnae3_ring_chain_node *chain_tmp, *chain;
2610
2611 chain = head->next;
2612
2613 while (chain) {
2614 chain_tmp = chain->next;
2615 devm_kfree(&pdev->dev, chain);
2616 chain = chain_tmp;
2617 }
2618 }
2619
2620 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
2621 struct hns3_enet_ring *ring)
2622 {
2623 ring->next = group->ring;
2624 group->ring = ring;
2625
2626 group->count++;
2627 }
2628
2629 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
2630 {
2631 struct hnae3_ring_chain_node vector_ring_chain;
2632 struct hnae3_handle *h = priv->ae_handle;
2633 struct hns3_enet_tqp_vector *tqp_vector;
2634 int ret = 0;
2635 u16 i;
2636
2637 for (i = 0; i < priv->vector_num; i++) {
2638 tqp_vector = &priv->tqp_vector[i];
2639 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
2640 tqp_vector->num_tqps = 0;
2641 }
2642
2643 for (i = 0; i < h->kinfo.num_tqps; i++) {
2644 u16 vector_i = i % priv->vector_num;
2645 u16 tqp_num = h->kinfo.num_tqps;
2646
2647 tqp_vector = &priv->tqp_vector[vector_i];
2648
2649 hns3_add_ring_to_group(&tqp_vector->tx_group,
2650 priv->ring_data[i].ring);
2651
2652 hns3_add_ring_to_group(&tqp_vector->rx_group,
2653 priv->ring_data[i + tqp_num].ring);
2654
2655 priv->ring_data[i].ring->tqp_vector = tqp_vector;
2656 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector;
2657 tqp_vector->num_tqps++;
2658 }
2659
2660 for (i = 0; i < priv->vector_num; i++) {
2661 tqp_vector = &priv->tqp_vector[i];
2662
2663 tqp_vector->rx_group.total_bytes = 0;
2664 tqp_vector->rx_group.total_packets = 0;
2665 tqp_vector->tx_group.total_bytes = 0;
2666 tqp_vector->tx_group.total_packets = 0;
2667 tqp_vector->handle = h;
2668
2669 ret = hns3_get_vector_ring_chain(tqp_vector,
2670 &vector_ring_chain);
2671 if (ret)
2672 return ret;
2673
2674 ret = h->ae_algo->ops->map_ring_to_vector(h,
2675 tqp_vector->vector_irq, &vector_ring_chain);
2676
2677 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
2678
2679 if (ret)
2680 return ret;
2681
2682 netif_napi_add(priv->netdev, &tqp_vector->napi,
2683 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
2684 }
2685
2686 return 0;
2687 }
2688
2689 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
2690 {
2691 struct hnae3_handle *h = priv->ae_handle;
2692 struct hns3_enet_tqp_vector *tqp_vector;
2693 struct hnae3_vector_info *vector;
2694 struct pci_dev *pdev = h->pdev;
2695 u16 tqp_num = h->kinfo.num_tqps;
2696 u16 vector_num;
2697 int ret = 0;
2698 u16 i;
2699
2700 /* RSS size, cpu online and vector_num should be the same */
2701 /* Should consider 2p/4p later */
2702 vector_num = min_t(u16, num_online_cpus(), tqp_num);
2703 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
2704 GFP_KERNEL);
2705 if (!vector)
2706 return -ENOMEM;
2707
2708 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
2709
2710 priv->vector_num = vector_num;
2711 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
2712 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
2713 GFP_KERNEL);
2714 if (!priv->tqp_vector) {
2715 ret = -ENOMEM;
2716 goto out;
2717 }
2718
2719 for (i = 0; i < priv->vector_num; i++) {
2720 tqp_vector = &priv->tqp_vector[i];
2721 tqp_vector->idx = i;
2722 tqp_vector->mask_addr = vector[i].io_addr;
2723 tqp_vector->vector_irq = vector[i].vector;
2724 hns3_vector_gl_rl_init(tqp_vector, priv);
2725 }
2726
2727 out:
2728 devm_kfree(&pdev->dev, vector);
2729 return ret;
2730 }
2731
2732 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
2733 {
2734 group->ring = NULL;
2735 group->count = 0;
2736 }
2737
2738 static int hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
2739 {
2740 struct hnae3_ring_chain_node vector_ring_chain;
2741 struct hnae3_handle *h = priv->ae_handle;
2742 struct hns3_enet_tqp_vector *tqp_vector;
2743 int i, ret;
2744
2745 for (i = 0; i < priv->vector_num; i++) {
2746 tqp_vector = &priv->tqp_vector[i];
2747
2748 ret = hns3_get_vector_ring_chain(tqp_vector,
2749 &vector_ring_chain);
2750 if (ret)
2751 return ret;
2752
2753 ret = h->ae_algo->ops->unmap_ring_from_vector(h,
2754 tqp_vector->vector_irq, &vector_ring_chain);
2755 if (ret)
2756 return ret;
2757
2758 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
2759
2760 if (priv->tqp_vector[i].irq_init_flag == HNS3_VECTOR_INITED) {
2761 (void)irq_set_affinity_hint(
2762 priv->tqp_vector[i].vector_irq,
2763 NULL);
2764 free_irq(priv->tqp_vector[i].vector_irq,
2765 &priv->tqp_vector[i]);
2766 }
2767
2768 priv->ring_data[i].ring->irq_init_flag = HNS3_VECTOR_NOT_INITED;
2769 hns3_clear_ring_group(&tqp_vector->rx_group);
2770 hns3_clear_ring_group(&tqp_vector->tx_group);
2771 netif_napi_del(&priv->tqp_vector[i].napi);
2772 }
2773
2774 return 0;
2775 }
2776
2777 static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
2778 {
2779 struct hnae3_handle *h = priv->ae_handle;
2780 struct pci_dev *pdev = h->pdev;
2781 int i, ret;
2782
2783 for (i = 0; i < priv->vector_num; i++) {
2784 struct hns3_enet_tqp_vector *tqp_vector;
2785
2786 tqp_vector = &priv->tqp_vector[i];
2787 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
2788 if (ret)
2789 return ret;
2790 }
2791
2792 devm_kfree(&pdev->dev, priv->tqp_vector);
2793 return 0;
2794 }
2795
2796 static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
2797 int ring_type)
2798 {
2799 struct hns3_nic_ring_data *ring_data = priv->ring_data;
2800 int queue_num = priv->ae_handle->kinfo.num_tqps;
2801 struct pci_dev *pdev = priv->ae_handle->pdev;
2802 struct hns3_enet_ring *ring;
2803
2804 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL);
2805 if (!ring)
2806 return -ENOMEM;
2807
2808 if (ring_type == HNAE3_RING_TYPE_TX) {
2809 ring_data[q->tqp_index].ring = ring;
2810 ring_data[q->tqp_index].queue_index = q->tqp_index;
2811 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
2812 } else {
2813 ring_data[q->tqp_index + queue_num].ring = ring;
2814 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index;
2815 ring->io_base = q->io_base;
2816 }
2817
2818 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
2819
2820 ring->tqp = q;
2821 ring->desc = NULL;
2822 ring->desc_cb = NULL;
2823 ring->dev = priv->dev;
2824 ring->desc_dma_addr = 0;
2825 ring->buf_size = q->buf_size;
2826 ring->desc_num = q->desc_num;
2827 ring->next_to_use = 0;
2828 ring->next_to_clean = 0;
2829
2830 return 0;
2831 }
2832
2833 static int hns3_queue_to_ring(struct hnae3_queue *tqp,
2834 struct hns3_nic_priv *priv)
2835 {
2836 int ret;
2837
2838 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
2839 if (ret)
2840 return ret;
2841
2842 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
2843 if (ret)
2844 return ret;
2845
2846 return 0;
2847 }
2848
2849 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
2850 {
2851 struct hnae3_handle *h = priv->ae_handle;
2852 struct pci_dev *pdev = h->pdev;
2853 int i, ret;
2854
2855 priv->ring_data = devm_kzalloc(&pdev->dev, h->kinfo.num_tqps *
2856 sizeof(*priv->ring_data) * 2,
2857 GFP_KERNEL);
2858 if (!priv->ring_data)
2859 return -ENOMEM;
2860
2861 for (i = 0; i < h->kinfo.num_tqps; i++) {
2862 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv);
2863 if (ret)
2864 goto err;
2865 }
2866
2867 return 0;
2868 err:
2869 devm_kfree(&pdev->dev, priv->ring_data);
2870 return ret;
2871 }
2872
2873 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
2874 {
2875 struct hnae3_handle *h = priv->ae_handle;
2876 int i;
2877
2878 for (i = 0; i < h->kinfo.num_tqps; i++) {
2879 devm_kfree(priv->dev, priv->ring_data[i].ring);
2880 devm_kfree(priv->dev,
2881 priv->ring_data[i + h->kinfo.num_tqps].ring);
2882 }
2883 devm_kfree(priv->dev, priv->ring_data);
2884 }
2885
2886 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
2887 {
2888 int ret;
2889
2890 if (ring->desc_num <= 0 || ring->buf_size <= 0)
2891 return -EINVAL;
2892
2893 ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]),
2894 GFP_KERNEL);
2895 if (!ring->desc_cb) {
2896 ret = -ENOMEM;
2897 goto out;
2898 }
2899
2900 ret = hns3_alloc_desc(ring);
2901 if (ret)
2902 goto out_with_desc_cb;
2903
2904 if (!HNAE3_IS_TX_RING(ring)) {
2905 ret = hns3_alloc_ring_buffers(ring);
2906 if (ret)
2907 goto out_with_desc;
2908 }
2909
2910 return 0;
2911
2912 out_with_desc:
2913 hns3_free_desc(ring);
2914 out_with_desc_cb:
2915 kfree(ring->desc_cb);
2916 ring->desc_cb = NULL;
2917 out:
2918 return ret;
2919 }
2920
2921 static void hns3_fini_ring(struct hns3_enet_ring *ring)
2922 {
2923 hns3_free_desc(ring);
2924 kfree(ring->desc_cb);
2925 ring->desc_cb = NULL;
2926 ring->next_to_clean = 0;
2927 ring->next_to_use = 0;
2928 }
2929
2930 static int hns3_buf_size2type(u32 buf_size)
2931 {
2932 int bd_size_type;
2933
2934 switch (buf_size) {
2935 case 512:
2936 bd_size_type = HNS3_BD_SIZE_512_TYPE;
2937 break;
2938 case 1024:
2939 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
2940 break;
2941 case 2048:
2942 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
2943 break;
2944 case 4096:
2945 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
2946 break;
2947 default:
2948 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
2949 }
2950
2951 return bd_size_type;
2952 }
2953
2954 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
2955 {
2956 dma_addr_t dma = ring->desc_dma_addr;
2957 struct hnae3_queue *q = ring->tqp;
2958
2959 if (!HNAE3_IS_TX_RING(ring)) {
2960 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG,
2961 (u32)dma);
2962 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
2963 (u32)((dma >> 31) >> 1));
2964
2965 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
2966 hns3_buf_size2type(ring->buf_size));
2967 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
2968 ring->desc_num / 8 - 1);
2969
2970 } else {
2971 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
2972 (u32)dma);
2973 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
2974 (u32)((dma >> 31) >> 1));
2975
2976 hns3_write_dev(q, HNS3_RING_TX_RING_BD_LEN_REG,
2977 hns3_buf_size2type(ring->buf_size));
2978 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
2979 ring->desc_num / 8 - 1);
2980 }
2981 }
2982
2983 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
2984 {
2985 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
2986 int i;
2987
2988 for (i = 0; i < HNAE3_MAX_TC; i++) {
2989 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
2990 int j;
2991
2992 if (!tc_info->enable)
2993 continue;
2994
2995 for (j = 0; j < tc_info->tqp_count; j++) {
2996 struct hnae3_queue *q;
2997
2998 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp;
2999 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3000 tc_info->tc);
3001 }
3002 }
3003 }
3004
3005 int hns3_init_all_ring(struct hns3_nic_priv *priv)
3006 {
3007 struct hnae3_handle *h = priv->ae_handle;
3008 int ring_num = h->kinfo.num_tqps * 2;
3009 int i, j;
3010 int ret;
3011
3012 for (i = 0; i < ring_num; i++) {
3013 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring);
3014 if (ret) {
3015 dev_err(priv->dev,
3016 "Alloc ring memory fail! ret=%d\n", ret);
3017 goto out_when_alloc_ring_memory;
3018 }
3019
3020 u64_stats_init(&priv->ring_data[i].ring->syncp);
3021 }
3022
3023 return 0;
3024
3025 out_when_alloc_ring_memory:
3026 for (j = i - 1; j >= 0; j--)
3027 hns3_fini_ring(priv->ring_data[j].ring);
3028
3029 return -ENOMEM;
3030 }
3031
3032 int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
3033 {
3034 struct hnae3_handle *h = priv->ae_handle;
3035 int i;
3036
3037 for (i = 0; i < h->kinfo.num_tqps; i++) {
3038 if (h->ae_algo->ops->reset_queue)
3039 h->ae_algo->ops->reset_queue(h, i);
3040
3041 hns3_fini_ring(priv->ring_data[i].ring);
3042 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring);
3043 }
3044 return 0;
3045 }
3046
3047 /* Set mac addr if it is configured. or leave it to the AE driver */
3048 static void hns3_init_mac_addr(struct net_device *netdev, bool init)
3049 {
3050 struct hns3_nic_priv *priv = netdev_priv(netdev);
3051 struct hnae3_handle *h = priv->ae_handle;
3052 u8 mac_addr_temp[ETH_ALEN];
3053
3054 if (h->ae_algo->ops->get_mac_addr && init) {
3055 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
3056 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3057 }
3058
3059 /* Check if the MAC address is valid, if not get a random one */
3060 if (!is_valid_ether_addr(netdev->dev_addr)) {
3061 eth_hw_addr_random(netdev);
3062 dev_warn(priv->dev, "using random MAC address %pM\n",
3063 netdev->dev_addr);
3064 }
3065
3066 if (h->ae_algo->ops->set_mac_addr)
3067 h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
3068
3069 }
3070
3071 static void hns3_uninit_mac_addr(struct net_device *netdev)
3072 {
3073 struct hns3_nic_priv *priv = netdev_priv(netdev);
3074 struct hnae3_handle *h = priv->ae_handle;
3075
3076 if (h->ae_algo->ops->rm_uc_addr)
3077 h->ae_algo->ops->rm_uc_addr(h, netdev->dev_addr);
3078 }
3079
3080 static void hns3_nic_set_priv_ops(struct net_device *netdev)
3081 {
3082 struct hns3_nic_priv *priv = netdev_priv(netdev);
3083
3084 if ((netdev->features & NETIF_F_TSO) ||
3085 (netdev->features & NETIF_F_TSO6)) {
3086 priv->ops.fill_desc = hns3_fill_desc_tso;
3087 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
3088 } else {
3089 priv->ops.fill_desc = hns3_fill_desc;
3090 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
3091 }
3092 }
3093
3094 static int hns3_client_init(struct hnae3_handle *handle)
3095 {
3096 struct pci_dev *pdev = handle->pdev;
3097 struct hns3_nic_priv *priv;
3098 struct net_device *netdev;
3099 int ret;
3100
3101 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv),
3102 hns3_get_max_available_channels(handle));
3103 if (!netdev)
3104 return -ENOMEM;
3105
3106 priv = netdev_priv(netdev);
3107 priv->dev = &pdev->dev;
3108 priv->netdev = netdev;
3109 priv->ae_handle = handle;
3110 priv->ae_handle->last_reset_time = jiffies;
3111 priv->tx_timeout_count = 0;
3112
3113 handle->kinfo.netdev = netdev;
3114 handle->priv = (void *)priv;
3115
3116 hns3_init_mac_addr(netdev, true);
3117
3118 hns3_set_default_feature(netdev);
3119
3120 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
3121 netdev->priv_flags |= IFF_UNICAST_FLT;
3122 netdev->netdev_ops = &hns3_nic_netdev_ops;
3123 SET_NETDEV_DEV(netdev, &pdev->dev);
3124 hns3_ethtool_set_ops(netdev);
3125 hns3_nic_set_priv_ops(netdev);
3126
3127 /* Carrier off reporting is important to ethtool even BEFORE open */
3128 netif_carrier_off(netdev);
3129
3130 if (handle->flags & HNAE3_SUPPORT_VF)
3131 handle->reset_level = HNAE3_VF_RESET;
3132 else
3133 handle->reset_level = HNAE3_FUNC_RESET;
3134
3135 ret = hns3_get_ring_config(priv);
3136 if (ret) {
3137 ret = -ENOMEM;
3138 goto out_get_ring_cfg;
3139 }
3140
3141 ret = hns3_nic_alloc_vector_data(priv);
3142 if (ret) {
3143 ret = -ENOMEM;
3144 goto out_alloc_vector_data;
3145 }
3146
3147 ret = hns3_nic_init_vector_data(priv);
3148 if (ret) {
3149 ret = -ENOMEM;
3150 goto out_init_vector_data;
3151 }
3152
3153 ret = hns3_init_all_ring(priv);
3154 if (ret) {
3155 ret = -ENOMEM;
3156 goto out_init_ring_data;
3157 }
3158
3159 ret = register_netdev(netdev);
3160 if (ret) {
3161 dev_err(priv->dev, "probe register netdev fail!\n");
3162 goto out_reg_netdev_fail;
3163 }
3164
3165 hns3_dcbnl_setup(handle);
3166
3167 /* MTU range: (ETH_MIN_MTU(kernel default) - 9706) */
3168 netdev->max_mtu = HNS3_MAX_MTU - (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
3169
3170 return ret;
3171
3172 out_reg_netdev_fail:
3173 out_init_ring_data:
3174 (void)hns3_nic_uninit_vector_data(priv);
3175 out_init_vector_data:
3176 hns3_nic_dealloc_vector_data(priv);
3177 out_alloc_vector_data:
3178 priv->ring_data = NULL;
3179 out_get_ring_cfg:
3180 priv->ae_handle = NULL;
3181 free_netdev(netdev);
3182 return ret;
3183 }
3184
3185 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
3186 {
3187 struct net_device *netdev = handle->kinfo.netdev;
3188 struct hns3_nic_priv *priv = netdev_priv(netdev);
3189 int ret;
3190
3191 if (netdev->reg_state != NETREG_UNINITIALIZED)
3192 unregister_netdev(netdev);
3193
3194 hns3_force_clear_all_rx_ring(handle);
3195
3196 ret = hns3_nic_uninit_vector_data(priv);
3197 if (ret)
3198 netdev_err(netdev, "uninit vector error\n");
3199
3200 ret = hns3_nic_dealloc_vector_data(priv);
3201 if (ret)
3202 netdev_err(netdev, "dealloc vector error\n");
3203
3204 ret = hns3_uninit_all_ring(priv);
3205 if (ret)
3206 netdev_err(netdev, "uninit ring error\n");
3207
3208 hns3_put_ring_config(priv);
3209
3210 priv->ring_data = NULL;
3211
3212 hns3_uninit_mac_addr(netdev);
3213
3214 free_netdev(netdev);
3215 }
3216
3217 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
3218 {
3219 struct net_device *netdev = handle->kinfo.netdev;
3220
3221 if (!netdev)
3222 return;
3223
3224 if (linkup) {
3225 netif_carrier_on(netdev);
3226 netif_tx_wake_all_queues(netdev);
3227 netdev_info(netdev, "link up\n");
3228 } else {
3229 netif_carrier_off(netdev);
3230 netif_tx_stop_all_queues(netdev);
3231 netdev_info(netdev, "link down\n");
3232 }
3233 }
3234
3235 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
3236 {
3237 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3238 struct net_device *ndev = kinfo->netdev;
3239 bool if_running;
3240 int ret;
3241
3242 if (tc > HNAE3_MAX_TC)
3243 return -EINVAL;
3244
3245 if (!ndev)
3246 return -ENODEV;
3247
3248 if_running = netif_running(ndev);
3249
3250 if (if_running) {
3251 (void)hns3_nic_net_stop(ndev);
3252 msleep(100);
3253 }
3254
3255 ret = (kinfo->dcb_ops && kinfo->dcb_ops->map_update) ?
3256 kinfo->dcb_ops->map_update(handle) : -EOPNOTSUPP;
3257 if (ret)
3258 goto err_out;
3259
3260 ret = hns3_nic_set_real_num_queue(ndev);
3261
3262 err_out:
3263 if (if_running)
3264 (void)hns3_nic_net_open(ndev);
3265
3266 return ret;
3267 }
3268
3269 static void hns3_recover_hw_addr(struct net_device *ndev)
3270 {
3271 struct netdev_hw_addr_list *list;
3272 struct netdev_hw_addr *ha, *tmp;
3273
3274 /* go through and sync uc_addr entries to the device */
3275 list = &ndev->uc;
3276 list_for_each_entry_safe(ha, tmp, &list->list, list)
3277 hns3_nic_uc_sync(ndev, ha->addr);
3278
3279 /* go through and sync mc_addr entries to the device */
3280 list = &ndev->mc;
3281 list_for_each_entry_safe(ha, tmp, &list->list, list)
3282 hns3_nic_mc_sync(ndev, ha->addr);
3283 }
3284
3285 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
3286 {
3287 while (ring->next_to_clean != ring->next_to_use) {
3288 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
3289 hns3_free_buffer_detach(ring, ring->next_to_clean);
3290 ring_ptr_move_fw(ring, next_to_clean);
3291 }
3292 }
3293
3294 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
3295 {
3296 struct hns3_desc_cb res_cbs;
3297 int ret;
3298
3299 while (ring->next_to_use != ring->next_to_clean) {
3300 /* When a buffer is not reused, it's memory has been
3301 * freed in hns3_handle_rx_bd or will be freed by
3302 * stack, so we need to replace the buffer here.
3303 */
3304 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3305 ret = hns3_reserve_buffer_map(ring, &res_cbs);
3306 if (ret) {
3307 u64_stats_update_begin(&ring->syncp);
3308 ring->stats.sw_err_cnt++;
3309 u64_stats_update_end(&ring->syncp);
3310 /* if alloc new buffer fail, exit directly
3311 * and reclear in up flow.
3312 */
3313 netdev_warn(ring->tqp->handle->kinfo.netdev,
3314 "reserve buffer map failed, ret = %d\n",
3315 ret);
3316 return ret;
3317 }
3318 hns3_replace_buffer(ring, ring->next_to_use,
3319 &res_cbs);
3320 }
3321 ring_ptr_move_fw(ring, next_to_use);
3322 }
3323
3324 return 0;
3325 }
3326
3327 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
3328 {
3329 while (ring->next_to_use != ring->next_to_clean) {
3330 /* When a buffer is not reused, it's memory has been
3331 * freed in hns3_handle_rx_bd or will be freed by
3332 * stack, so only need to unmap the buffer here.
3333 */
3334 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3335 hns3_unmap_buffer(ring,
3336 &ring->desc_cb[ring->next_to_use]);
3337 ring->desc_cb[ring->next_to_use].dma = 0;
3338 }
3339
3340 ring_ptr_move_fw(ring, next_to_use);
3341 }
3342 }
3343
3344 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h)
3345 {
3346 struct net_device *ndev = h->kinfo.netdev;
3347 struct hns3_nic_priv *priv = netdev_priv(ndev);
3348 struct hns3_enet_ring *ring;
3349 u32 i;
3350
3351 for (i = 0; i < h->kinfo.num_tqps; i++) {
3352 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3353 hns3_force_clear_rx_ring(ring);
3354 }
3355 }
3356
3357 static void hns3_clear_all_ring(struct hnae3_handle *h)
3358 {
3359 struct net_device *ndev = h->kinfo.netdev;
3360 struct hns3_nic_priv *priv = netdev_priv(ndev);
3361 u32 i;
3362
3363 for (i = 0; i < h->kinfo.num_tqps; i++) {
3364 struct netdev_queue *dev_queue;
3365 struct hns3_enet_ring *ring;
3366
3367 ring = priv->ring_data[i].ring;
3368 hns3_clear_tx_ring(ring);
3369 dev_queue = netdev_get_tx_queue(ndev,
3370 priv->ring_data[i].queue_index);
3371 netdev_tx_reset_queue(dev_queue);
3372
3373 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3374 /* Continue to clear other rings even if clearing some
3375 * rings failed.
3376 */
3377 hns3_clear_rx_ring(ring);
3378 }
3379 }
3380
3381 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
3382 {
3383 struct net_device *ndev = h->kinfo.netdev;
3384 struct hns3_nic_priv *priv = netdev_priv(ndev);
3385 struct hns3_enet_ring *rx_ring;
3386 int i, j;
3387 int ret;
3388
3389 for (i = 0; i < h->kinfo.num_tqps; i++) {
3390 h->ae_algo->ops->reset_queue(h, i);
3391 hns3_init_ring_hw(priv->ring_data[i].ring);
3392
3393 /* We need to clear tx ring here because self test will
3394 * use the ring and will not run down before up
3395 */
3396 hns3_clear_tx_ring(priv->ring_data[i].ring);
3397 priv->ring_data[i].ring->next_to_clean = 0;
3398 priv->ring_data[i].ring->next_to_use = 0;
3399
3400 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3401 hns3_init_ring_hw(rx_ring);
3402 ret = hns3_clear_rx_ring(rx_ring);
3403 if (ret)
3404 return ret;
3405
3406 /* We can not know the hardware head and tail when this
3407 * function is called in reset flow, so we reuse all desc.
3408 */
3409 for (j = 0; j < rx_ring->desc_num; j++)
3410 hns3_reuse_buffer(rx_ring, j);
3411
3412 rx_ring->next_to_clean = 0;
3413 rx_ring->next_to_use = 0;
3414 }
3415
3416 hns3_init_tx_ring_tc(priv);
3417
3418 return 0;
3419 }
3420
3421 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
3422 {
3423 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3424 struct net_device *ndev = kinfo->netdev;
3425
3426 if (!netif_running(ndev))
3427 return 0;
3428
3429 return hns3_nic_net_stop(ndev);
3430 }
3431
3432 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
3433 {
3434 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3435 int ret = 0;
3436
3437 if (netif_running(kinfo->netdev)) {
3438 ret = hns3_nic_net_up(kinfo->netdev);
3439 if (ret) {
3440 netdev_err(kinfo->netdev,
3441 "hns net up fail, ret=%d!\n", ret);
3442 return ret;
3443 }
3444 handle->last_reset_time = jiffies;
3445 }
3446
3447 return ret;
3448 }
3449
3450 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
3451 {
3452 struct net_device *netdev = handle->kinfo.netdev;
3453 struct hns3_nic_priv *priv = netdev_priv(netdev);
3454 int ret;
3455
3456 hns3_init_mac_addr(netdev, false);
3457 hns3_nic_set_rx_mode(netdev);
3458 hns3_recover_hw_addr(netdev);
3459
3460 /* Hardware table is only clear when pf resets */
3461 if (!(handle->flags & HNAE3_SUPPORT_VF))
3462 hns3_restore_vlan(netdev);
3463
3464 /* Carrier off reporting is important to ethtool even BEFORE open */
3465 netif_carrier_off(netdev);
3466
3467 ret = hns3_nic_init_vector_data(priv);
3468 if (ret)
3469 return ret;
3470
3471 ret = hns3_init_all_ring(priv);
3472 if (ret) {
3473 hns3_nic_uninit_vector_data(priv);
3474 priv->ring_data = NULL;
3475 }
3476
3477 return ret;
3478 }
3479
3480 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
3481 {
3482 struct net_device *netdev = handle->kinfo.netdev;
3483 struct hns3_nic_priv *priv = netdev_priv(netdev);
3484 int ret;
3485
3486 hns3_force_clear_all_rx_ring(handle);
3487
3488 ret = hns3_nic_uninit_vector_data(priv);
3489 if (ret) {
3490 netdev_err(netdev, "uninit vector error\n");
3491 return ret;
3492 }
3493
3494 ret = hns3_uninit_all_ring(priv);
3495 if (ret)
3496 netdev_err(netdev, "uninit ring error\n");
3497
3498 hns3_uninit_mac_addr(netdev);
3499
3500 return ret;
3501 }
3502
3503 static int hns3_reset_notify(struct hnae3_handle *handle,
3504 enum hnae3_reset_notify_type type)
3505 {
3506 int ret = 0;
3507
3508 switch (type) {
3509 case HNAE3_UP_CLIENT:
3510 ret = hns3_reset_notify_up_enet(handle);
3511 break;
3512 case HNAE3_DOWN_CLIENT:
3513 ret = hns3_reset_notify_down_enet(handle);
3514 break;
3515 case HNAE3_INIT_CLIENT:
3516 ret = hns3_reset_notify_init_enet(handle);
3517 break;
3518 case HNAE3_UNINIT_CLIENT:
3519 ret = hns3_reset_notify_uninit_enet(handle);
3520 break;
3521 default:
3522 break;
3523 }
3524
3525 return ret;
3526 }
3527
3528 static void hns3_restore_coal(struct hns3_nic_priv *priv,
3529 struct hns3_enet_coalesce *tx,
3530 struct hns3_enet_coalesce *rx)
3531 {
3532 u16 vector_num = priv->vector_num;
3533 int i;
3534
3535 for (i = 0; i < vector_num; i++) {
3536 memcpy(&priv->tqp_vector[i].tx_group.coal, tx,
3537 sizeof(struct hns3_enet_coalesce));
3538 memcpy(&priv->tqp_vector[i].rx_group.coal, rx,
3539 sizeof(struct hns3_enet_coalesce));
3540 }
3541 }
3542
3543 static int hns3_modify_tqp_num(struct net_device *netdev, u16 new_tqp_num,
3544 struct hns3_enet_coalesce *tx,
3545 struct hns3_enet_coalesce *rx)
3546 {
3547 struct hns3_nic_priv *priv = netdev_priv(netdev);
3548 struct hnae3_handle *h = hns3_get_handle(netdev);
3549 int ret;
3550
3551 ret = h->ae_algo->ops->set_channels(h, new_tqp_num);
3552 if (ret)
3553 return ret;
3554
3555 ret = hns3_get_ring_config(priv);
3556 if (ret)
3557 return ret;
3558
3559 ret = hns3_nic_alloc_vector_data(priv);
3560 if (ret)
3561 goto err_alloc_vector;
3562
3563 hns3_restore_coal(priv, tx, rx);
3564
3565 ret = hns3_nic_init_vector_data(priv);
3566 if (ret)
3567 goto err_uninit_vector;
3568
3569 ret = hns3_init_all_ring(priv);
3570 if (ret)
3571 goto err_put_ring;
3572
3573 return 0;
3574
3575 err_put_ring:
3576 hns3_put_ring_config(priv);
3577 err_uninit_vector:
3578 hns3_nic_uninit_vector_data(priv);
3579 err_alloc_vector:
3580 hns3_nic_dealloc_vector_data(priv);
3581 return ret;
3582 }
3583
3584 static int hns3_adjust_tqps_num(u8 num_tc, u32 new_tqp_num)
3585 {
3586 return (new_tqp_num / num_tc) * num_tc;
3587 }
3588
3589 int hns3_set_channels(struct net_device *netdev,
3590 struct ethtool_channels *ch)
3591 {
3592 struct hns3_nic_priv *priv = netdev_priv(netdev);
3593 struct hnae3_handle *h = hns3_get_handle(netdev);
3594 struct hnae3_knic_private_info *kinfo = &h->kinfo;
3595 struct hns3_enet_coalesce tx_coal, rx_coal;
3596 bool if_running = netif_running(netdev);
3597 u32 new_tqp_num = ch->combined_count;
3598 u16 org_tqp_num;
3599 int ret;
3600
3601 if (ch->rx_count || ch->tx_count)
3602 return -EINVAL;
3603
3604 if (new_tqp_num > hns3_get_max_available_channels(h) ||
3605 new_tqp_num < kinfo->num_tc) {
3606 dev_err(&netdev->dev,
3607 "Change tqps fail, the tqp range is from %d to %d",
3608 kinfo->num_tc,
3609 hns3_get_max_available_channels(h));
3610 return -EINVAL;
3611 }
3612
3613 new_tqp_num = hns3_adjust_tqps_num(kinfo->num_tc, new_tqp_num);
3614 if (kinfo->num_tqps == new_tqp_num)
3615 return 0;
3616
3617 if (if_running)
3618 hns3_nic_net_stop(netdev);
3619
3620 ret = hns3_nic_uninit_vector_data(priv);
3621 if (ret) {
3622 dev_err(&netdev->dev,
3623 "Unbind vector with tqp fail, nothing is changed");
3624 goto open_netdev;
3625 }
3626
3627 /* Changing the tqp num may also change the vector num,
3628 * ethtool only support setting and querying one coal
3629 * configuation for now, so save the vector 0' coal
3630 * configuation here in order to restore it.
3631 */
3632 memcpy(&tx_coal, &priv->tqp_vector[0].tx_group.coal,
3633 sizeof(struct hns3_enet_coalesce));
3634 memcpy(&rx_coal, &priv->tqp_vector[0].rx_group.coal,
3635 sizeof(struct hns3_enet_coalesce));
3636
3637 hns3_nic_dealloc_vector_data(priv);
3638
3639 hns3_uninit_all_ring(priv);
3640 hns3_put_ring_config(priv);
3641
3642 org_tqp_num = h->kinfo.num_tqps;
3643 ret = hns3_modify_tqp_num(netdev, new_tqp_num, &tx_coal, &rx_coal);
3644 if (ret) {
3645 ret = hns3_modify_tqp_num(netdev, org_tqp_num,
3646 &tx_coal, &rx_coal);
3647 if (ret) {
3648 /* If revert to old tqp failed, fatal error occurred */
3649 dev_err(&netdev->dev,
3650 "Revert to old tqp num fail, ret=%d", ret);
3651 return ret;
3652 }
3653 dev_info(&netdev->dev,
3654 "Change tqp num fail, Revert to old tqp num");
3655 }
3656
3657 open_netdev:
3658 if (if_running)
3659 hns3_nic_net_open(netdev);
3660
3661 return ret;
3662 }
3663
3664 static const struct hnae3_client_ops client_ops = {
3665 .init_instance = hns3_client_init,
3666 .uninit_instance = hns3_client_uninit,
3667 .link_status_change = hns3_link_status_change,
3668 .setup_tc = hns3_client_setup_tc,
3669 .reset_notify = hns3_reset_notify,
3670 };
3671
3672 /* hns3_init_module - Driver registration routine
3673 * hns3_init_module is the first routine called when the driver is
3674 * loaded. All it does is register with the PCI subsystem.
3675 */
3676 static int __init hns3_init_module(void)
3677 {
3678 int ret;
3679
3680 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
3681 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
3682
3683 client.type = HNAE3_CLIENT_KNIC;
3684 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s",
3685 hns3_driver_name);
3686
3687 client.ops = &client_ops;
3688
3689 INIT_LIST_HEAD(&client.node);
3690
3691 ret = hnae3_register_client(&client);
3692 if (ret)
3693 return ret;
3694
3695 ret = pci_register_driver(&hns3_driver);
3696 if (ret)
3697 hnae3_unregister_client(&client);
3698
3699 return ret;
3700 }
3701 module_init(hns3_init_module);
3702
3703 /* hns3_exit_module - Driver exit cleanup routine
3704 * hns3_exit_module is called just before the driver is removed
3705 * from memory.
3706 */
3707 static void __exit hns3_exit_module(void)
3708 {
3709 pci_unregister_driver(&hns3_driver);
3710 hnae3_unregister_client(&client);
3711 }
3712 module_exit(hns3_exit_module);
3713
3714 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
3715 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
3716 MODULE_LICENSE("GPL");
3717 MODULE_ALIAS("pci:hns-nic");
3718 MODULE_VERSION(HNS3_MOD_VERSION);
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