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1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #include <linux/dma-mapping.h>
5 #include <linux/etherdevice.h>
6 #include <linux/interrupt.h>
7 #ifdef CONFIG_RFS_ACCEL
8 #include <linux/cpu_rmap.h>
9 #endif
10 #include <linux/if_vlan.h>
11 #include <linux/irq.h>
12 #include <linux/ip.h>
13 #include <linux/ipv6.h>
14 #include <linux/module.h>
15 #include <linux/pci.h>
16 #include <linux/aer.h>
17 #include <linux/skbuff.h>
18 #include <linux/sctp.h>
19 #include <net/gre.h>
20 #include <net/ip6_checksum.h>
21 #include <net/pkt_cls.h>
22 #include <net/tcp.h>
23 #include <net/vxlan.h>
24
25 #include "hnae3.h"
26 #include "hns3_enet.h"
27 /* All hns3 tracepoints are defined by the include below, which
28 * must be included exactly once across the whole kernel with
29 * CREATE_TRACE_POINTS defined
30 */
31 #define CREATE_TRACE_POINTS
32 #include "hns3_trace.h"
33
34 #define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift)))
35 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
36
37 #define hns3_rl_err(fmt, ...) \
38 do { \
39 if (net_ratelimit()) \
40 netdev_err(fmt, ##__VA_ARGS__); \
41 } while (0)
42
43 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
44
45 static const char hns3_driver_name[] = "hns3";
46 static const char hns3_driver_string[] =
47 "Hisilicon Ethernet Network Driver for Hip08 Family";
48 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
49 static struct hnae3_client client;
50
51 static int debug = -1;
52 module_param(debug, int, 0);
53 MODULE_PARM_DESC(debug, " Network interface message level setting");
54
55 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
56 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
57
58 #define HNS3_INNER_VLAN_TAG 1
59 #define HNS3_OUTER_VLAN_TAG 2
60
61 #define HNS3_MIN_TX_LEN 33U
62
63 /* hns3_pci_tbl - PCI Device ID Table
64 *
65 * Last entry must be all 0s
66 *
67 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
68 * Class, Class Mask, private data (not used) }
69 */
70 static const struct pci_device_id hns3_pci_tbl[] = {
71 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
72 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
74 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
75 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
76 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
77 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
78 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
79 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
80 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
81 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
82 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
83 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
84 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
85 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
86 /* required last entry */
87 {0, }
88 };
89 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
90
91 static irqreturn_t hns3_irq_handle(int irq, void *vector)
92 {
93 struct hns3_enet_tqp_vector *tqp_vector = vector;
94
95 napi_schedule_irqoff(&tqp_vector->napi);
96
97 return IRQ_HANDLED;
98 }
99
100 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
101 {
102 struct hns3_enet_tqp_vector *tqp_vectors;
103 unsigned int i;
104
105 for (i = 0; i < priv->vector_num; i++) {
106 tqp_vectors = &priv->tqp_vector[i];
107
108 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
109 continue;
110
111 /* clear the affinity mask */
112 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
113
114 /* release the irq resource */
115 free_irq(tqp_vectors->vector_irq, tqp_vectors);
116 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
117 }
118 }
119
120 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
121 {
122 struct hns3_enet_tqp_vector *tqp_vectors;
123 int txrx_int_idx = 0;
124 int rx_int_idx = 0;
125 int tx_int_idx = 0;
126 unsigned int i;
127 int ret;
128
129 for (i = 0; i < priv->vector_num; i++) {
130 tqp_vectors = &priv->tqp_vector[i];
131
132 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
133 continue;
134
135 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
136 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
137 "%s-%s-%s-%d", hns3_driver_name,
138 pci_name(priv->ae_handle->pdev),
139 "TxRx", txrx_int_idx++);
140 txrx_int_idx++;
141 } else if (tqp_vectors->rx_group.ring) {
142 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
143 "%s-%s-%s-%d", hns3_driver_name,
144 pci_name(priv->ae_handle->pdev),
145 "Rx", rx_int_idx++);
146 } else if (tqp_vectors->tx_group.ring) {
147 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
148 "%s-%s-%s-%d", hns3_driver_name,
149 pci_name(priv->ae_handle->pdev),
150 "Tx", tx_int_idx++);
151 } else {
152 /* Skip this unused q_vector */
153 continue;
154 }
155
156 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
157
158 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN);
159 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
160 tqp_vectors->name, tqp_vectors);
161 if (ret) {
162 netdev_err(priv->netdev, "request irq(%d) fail\n",
163 tqp_vectors->vector_irq);
164 hns3_nic_uninit_irq(priv);
165 return ret;
166 }
167
168 irq_set_affinity_hint(tqp_vectors->vector_irq,
169 &tqp_vectors->affinity_mask);
170
171 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
172 }
173
174 return 0;
175 }
176
177 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
178 u32 mask_en)
179 {
180 writel(mask_en, tqp_vector->mask_addr);
181 }
182
183 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
184 {
185 napi_enable(&tqp_vector->napi);
186 enable_irq(tqp_vector->vector_irq);
187
188 /* enable vector */
189 hns3_mask_vector_irq(tqp_vector, 1);
190 }
191
192 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
193 {
194 /* disable vector */
195 hns3_mask_vector_irq(tqp_vector, 0);
196
197 disable_irq(tqp_vector->vector_irq);
198 napi_disable(&tqp_vector->napi);
199 }
200
201 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
202 u32 rl_value)
203 {
204 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
205
206 /* this defines the configuration for RL (Interrupt Rate Limiter).
207 * Rl defines rate of interrupts i.e. number of interrupts-per-second
208 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
209 */
210
211 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
212 !tqp_vector->rx_group.coal.gl_adapt_enable)
213 /* According to the hardware, the range of rl_reg is
214 * 0-59 and the unit is 4.
215 */
216 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
217
218 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
219 }
220
221 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
222 u32 gl_value)
223 {
224 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
225
226 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
227 }
228
229 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
230 u32 gl_value)
231 {
232 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
233
234 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
235 }
236
237 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
238 struct hns3_nic_priv *priv)
239 {
240 /* initialize the configuration for interrupt coalescing.
241 * 1. GL (Interrupt Gap Limiter)
242 * 2. RL (Interrupt Rate Limiter)
243 *
244 * Default: enable interrupt coalescing self-adaptive and GL
245 */
246 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
247 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
248
249 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
250 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
251
252 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
253 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
254 }
255
256 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
257 struct hns3_nic_priv *priv)
258 {
259 struct hnae3_handle *h = priv->ae_handle;
260
261 hns3_set_vector_coalesce_tx_gl(tqp_vector,
262 tqp_vector->tx_group.coal.int_gl);
263 hns3_set_vector_coalesce_rx_gl(tqp_vector,
264 tqp_vector->rx_group.coal.int_gl);
265 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
266 }
267
268 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
269 {
270 struct hnae3_handle *h = hns3_get_handle(netdev);
271 struct hnae3_knic_private_info *kinfo = &h->kinfo;
272 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
273 int i, ret;
274
275 if (kinfo->num_tc <= 1) {
276 netdev_reset_tc(netdev);
277 } else {
278 ret = netdev_set_num_tc(netdev, kinfo->num_tc);
279 if (ret) {
280 netdev_err(netdev,
281 "netdev_set_num_tc fail, ret=%d!\n", ret);
282 return ret;
283 }
284
285 for (i = 0; i < HNAE3_MAX_TC; i++) {
286 if (!kinfo->tc_info[i].enable)
287 continue;
288
289 netdev_set_tc_queue(netdev,
290 kinfo->tc_info[i].tc,
291 kinfo->tc_info[i].tqp_count,
292 kinfo->tc_info[i].tqp_offset);
293 }
294 }
295
296 ret = netif_set_real_num_tx_queues(netdev, queue_size);
297 if (ret) {
298 netdev_err(netdev,
299 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
300 return ret;
301 }
302
303 ret = netif_set_real_num_rx_queues(netdev, queue_size);
304 if (ret) {
305 netdev_err(netdev,
306 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
307 return ret;
308 }
309
310 return 0;
311 }
312
313 static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
314 {
315 u16 alloc_tqps, max_rss_size, rss_size;
316
317 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
318 rss_size = alloc_tqps / h->kinfo.num_tc;
319
320 return min_t(u16, rss_size, max_rss_size);
321 }
322
323 static void hns3_tqp_enable(struct hnae3_queue *tqp)
324 {
325 u32 rcb_reg;
326
327 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
328 rcb_reg |= BIT(HNS3_RING_EN_B);
329 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
330 }
331
332 static void hns3_tqp_disable(struct hnae3_queue *tqp)
333 {
334 u32 rcb_reg;
335
336 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
337 rcb_reg &= ~BIT(HNS3_RING_EN_B);
338 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
339 }
340
341 static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
342 {
343 #ifdef CONFIG_RFS_ACCEL
344 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
345 netdev->rx_cpu_rmap = NULL;
346 #endif
347 }
348
349 static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
350 {
351 #ifdef CONFIG_RFS_ACCEL
352 struct hns3_nic_priv *priv = netdev_priv(netdev);
353 struct hns3_enet_tqp_vector *tqp_vector;
354 int i, ret;
355
356 if (!netdev->rx_cpu_rmap) {
357 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
358 if (!netdev->rx_cpu_rmap)
359 return -ENOMEM;
360 }
361
362 for (i = 0; i < priv->vector_num; i++) {
363 tqp_vector = &priv->tqp_vector[i];
364 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
365 tqp_vector->vector_irq);
366 if (ret) {
367 hns3_free_rx_cpu_rmap(netdev);
368 return ret;
369 }
370 }
371 #endif
372 return 0;
373 }
374
375 static int hns3_nic_net_up(struct net_device *netdev)
376 {
377 struct hns3_nic_priv *priv = netdev_priv(netdev);
378 struct hnae3_handle *h = priv->ae_handle;
379 int i, j;
380 int ret;
381
382 ret = hns3_nic_reset_all_ring(h);
383 if (ret)
384 return ret;
385
386 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
387
388 /* enable the vectors */
389 for (i = 0; i < priv->vector_num; i++)
390 hns3_vector_enable(&priv->tqp_vector[i]);
391
392 /* enable rcb */
393 for (j = 0; j < h->kinfo.num_tqps; j++)
394 hns3_tqp_enable(h->kinfo.tqp[j]);
395
396 /* start the ae_dev */
397 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
398 if (ret) {
399 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
400 while (j--)
401 hns3_tqp_disable(h->kinfo.tqp[j]);
402
403 for (j = i - 1; j >= 0; j--)
404 hns3_vector_disable(&priv->tqp_vector[j]);
405 }
406
407 return ret;
408 }
409
410 static void hns3_config_xps(struct hns3_nic_priv *priv)
411 {
412 int i;
413
414 for (i = 0; i < priv->vector_num; i++) {
415 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
416 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
417
418 while (ring) {
419 int ret;
420
421 ret = netif_set_xps_queue(priv->netdev,
422 &tqp_vector->affinity_mask,
423 ring->tqp->tqp_index);
424 if (ret)
425 netdev_warn(priv->netdev,
426 "set xps queue failed: %d", ret);
427
428 ring = ring->next;
429 }
430 }
431 }
432
433 static int hns3_nic_net_open(struct net_device *netdev)
434 {
435 struct hns3_nic_priv *priv = netdev_priv(netdev);
436 struct hnae3_handle *h = hns3_get_handle(netdev);
437 struct hnae3_knic_private_info *kinfo;
438 int i, ret;
439
440 if (hns3_nic_resetting(netdev))
441 return -EBUSY;
442
443 netif_carrier_off(netdev);
444
445 ret = hns3_nic_set_real_num_queue(netdev);
446 if (ret)
447 return ret;
448
449 ret = hns3_nic_net_up(netdev);
450 if (ret) {
451 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
452 return ret;
453 }
454
455 kinfo = &h->kinfo;
456 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
457 netdev_set_prio_tc_map(netdev, i, kinfo->prio_tc[i]);
458
459 if (h->ae_algo->ops->set_timer_task)
460 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
461
462 hns3_config_xps(priv);
463
464 netif_dbg(h, drv, netdev, "net open\n");
465
466 return 0;
467 }
468
469 static void hns3_reset_tx_queue(struct hnae3_handle *h)
470 {
471 struct net_device *ndev = h->kinfo.netdev;
472 struct hns3_nic_priv *priv = netdev_priv(ndev);
473 struct netdev_queue *dev_queue;
474 u32 i;
475
476 for (i = 0; i < h->kinfo.num_tqps; i++) {
477 dev_queue = netdev_get_tx_queue(ndev,
478 priv->ring[i].queue_index);
479 netdev_tx_reset_queue(dev_queue);
480 }
481 }
482
483 static void hns3_nic_net_down(struct net_device *netdev)
484 {
485 struct hns3_nic_priv *priv = netdev_priv(netdev);
486 struct hnae3_handle *h = hns3_get_handle(netdev);
487 const struct hnae3_ae_ops *ops;
488 int i;
489
490 /* disable vectors */
491 for (i = 0; i < priv->vector_num; i++)
492 hns3_vector_disable(&priv->tqp_vector[i]);
493
494 /* disable rcb */
495 for (i = 0; i < h->kinfo.num_tqps; i++)
496 hns3_tqp_disable(h->kinfo.tqp[i]);
497
498 /* stop ae_dev */
499 ops = priv->ae_handle->ae_algo->ops;
500 if (ops->stop)
501 ops->stop(priv->ae_handle);
502
503 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
504 * during reset process, because driver may not be able
505 * to disable the ring through firmware when downing the netdev.
506 */
507 if (!hns3_nic_resetting(netdev))
508 hns3_clear_all_ring(priv->ae_handle, false);
509
510 hns3_reset_tx_queue(priv->ae_handle);
511 }
512
513 static int hns3_nic_net_stop(struct net_device *netdev)
514 {
515 struct hns3_nic_priv *priv = netdev_priv(netdev);
516 struct hnae3_handle *h = hns3_get_handle(netdev);
517
518 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
519 return 0;
520
521 netif_dbg(h, drv, netdev, "net stop\n");
522
523 if (h->ae_algo->ops->set_timer_task)
524 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
525
526 netif_tx_stop_all_queues(netdev);
527 netif_carrier_off(netdev);
528
529 hns3_nic_net_down(netdev);
530
531 return 0;
532 }
533
534 static int hns3_nic_uc_sync(struct net_device *netdev,
535 const unsigned char *addr)
536 {
537 struct hnae3_handle *h = hns3_get_handle(netdev);
538
539 if (h->ae_algo->ops->add_uc_addr)
540 return h->ae_algo->ops->add_uc_addr(h, addr);
541
542 return 0;
543 }
544
545 static int hns3_nic_uc_unsync(struct net_device *netdev,
546 const unsigned char *addr)
547 {
548 struct hnae3_handle *h = hns3_get_handle(netdev);
549
550 /* need ignore the request of removing device address, because
551 * we store the device address and other addresses of uc list
552 * in the function's mac filter list.
553 */
554 if (ether_addr_equal(addr, netdev->dev_addr))
555 return 0;
556
557 if (h->ae_algo->ops->rm_uc_addr)
558 return h->ae_algo->ops->rm_uc_addr(h, addr);
559
560 return 0;
561 }
562
563 static int hns3_nic_mc_sync(struct net_device *netdev,
564 const unsigned char *addr)
565 {
566 struct hnae3_handle *h = hns3_get_handle(netdev);
567
568 if (h->ae_algo->ops->add_mc_addr)
569 return h->ae_algo->ops->add_mc_addr(h, addr);
570
571 return 0;
572 }
573
574 static int hns3_nic_mc_unsync(struct net_device *netdev,
575 const unsigned char *addr)
576 {
577 struct hnae3_handle *h = hns3_get_handle(netdev);
578
579 if (h->ae_algo->ops->rm_mc_addr)
580 return h->ae_algo->ops->rm_mc_addr(h, addr);
581
582 return 0;
583 }
584
585 static u8 hns3_get_netdev_flags(struct net_device *netdev)
586 {
587 u8 flags = 0;
588
589 if (netdev->flags & IFF_PROMISC) {
590 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
591 } else {
592 flags |= HNAE3_VLAN_FLTR;
593 if (netdev->flags & IFF_ALLMULTI)
594 flags |= HNAE3_USER_MPE;
595 }
596
597 return flags;
598 }
599
600 static void hns3_nic_set_rx_mode(struct net_device *netdev)
601 {
602 struct hnae3_handle *h = hns3_get_handle(netdev);
603 u8 new_flags;
604
605 new_flags = hns3_get_netdev_flags(netdev);
606
607 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
608 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync);
609
610 /* User mode Promisc mode enable and vlan filtering is disabled to
611 * let all packets in.
612 */
613 h->netdev_flags = new_flags;
614 hns3_request_update_promisc_mode(h);
615 }
616
617 void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
618 {
619 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
620
621 if (ops->request_update_promisc_mode)
622 ops->request_update_promisc_mode(handle);
623 }
624
625 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags)
626 {
627 struct hns3_nic_priv *priv = netdev_priv(netdev);
628 struct hnae3_handle *h = priv->ae_handle;
629
630 if (h->ae_algo->ops->set_promisc_mode) {
631 return h->ae_algo->ops->set_promisc_mode(h,
632 promisc_flags & HNAE3_UPE,
633 promisc_flags & HNAE3_MPE);
634 }
635
636 return 0;
637 }
638
639 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable)
640 {
641 struct hns3_nic_priv *priv = netdev_priv(netdev);
642 struct hnae3_handle *h = priv->ae_handle;
643 bool last_state;
644
645 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) {
646 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;
647 if (enable != last_state) {
648 netdev_info(netdev,
649 "%s vlan filter\n",
650 enable ? "enable" : "disable");
651 h->ae_algo->ops->enable_vlan_filter(h, enable);
652 }
653 }
654 }
655
656 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
657 u16 *mss, u32 *type_cs_vlan_tso)
658 {
659 u32 l4_offset, hdr_len;
660 union l3_hdr_info l3;
661 union l4_hdr_info l4;
662 u32 l4_paylen;
663 int ret;
664
665 if (!skb_is_gso(skb))
666 return 0;
667
668 ret = skb_cow_head(skb, 0);
669 if (unlikely(ret < 0))
670 return ret;
671
672 l3.hdr = skb_network_header(skb);
673 l4.hdr = skb_transport_header(skb);
674
675 /* Software should clear the IPv4's checksum field when tso is
676 * needed.
677 */
678 if (l3.v4->version == 4)
679 l3.v4->check = 0;
680
681 /* tunnel packet */
682 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
683 SKB_GSO_GRE_CSUM |
684 SKB_GSO_UDP_TUNNEL |
685 SKB_GSO_UDP_TUNNEL_CSUM)) {
686 if ((!(skb_shinfo(skb)->gso_type &
687 SKB_GSO_PARTIAL)) &&
688 (skb_shinfo(skb)->gso_type &
689 SKB_GSO_UDP_TUNNEL_CSUM)) {
690 /* Software should clear the udp's checksum
691 * field when tso is needed.
692 */
693 l4.udp->check = 0;
694 }
695 /* reset l3&l4 pointers from outer to inner headers */
696 l3.hdr = skb_inner_network_header(skb);
697 l4.hdr = skb_inner_transport_header(skb);
698
699 /* Software should clear the IPv4's checksum field when
700 * tso is needed.
701 */
702 if (l3.v4->version == 4)
703 l3.v4->check = 0;
704 }
705
706 /* normal or tunnel packet */
707 l4_offset = l4.hdr - skb->data;
708 hdr_len = (l4.tcp->doff << 2) + l4_offset;
709
710 /* remove payload length from inner pseudo checksum when tso */
711 l4_paylen = skb->len - l4_offset;
712 csum_replace_by_diff(&l4.tcp->check,
713 (__force __wsum)htonl(l4_paylen));
714
715 /* find the txbd field values */
716 *paylen = skb->len - hdr_len;
717 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
718
719 /* get MSS for TSO */
720 *mss = skb_shinfo(skb)->gso_size;
721
722 trace_hns3_tso(skb);
723
724 return 0;
725 }
726
727 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
728 u8 *il4_proto)
729 {
730 union l3_hdr_info l3;
731 unsigned char *l4_hdr;
732 unsigned char *exthdr;
733 u8 l4_proto_tmp;
734 __be16 frag_off;
735
736 /* find outer header point */
737 l3.hdr = skb_network_header(skb);
738 l4_hdr = skb_transport_header(skb);
739
740 if (skb->protocol == htons(ETH_P_IPV6)) {
741 exthdr = l3.hdr + sizeof(*l3.v6);
742 l4_proto_tmp = l3.v6->nexthdr;
743 if (l4_hdr != exthdr)
744 ipv6_skip_exthdr(skb, exthdr - skb->data,
745 &l4_proto_tmp, &frag_off);
746 } else if (skb->protocol == htons(ETH_P_IP)) {
747 l4_proto_tmp = l3.v4->protocol;
748 } else {
749 return -EINVAL;
750 }
751
752 *ol4_proto = l4_proto_tmp;
753
754 /* tunnel packet */
755 if (!skb->encapsulation) {
756 *il4_proto = 0;
757 return 0;
758 }
759
760 /* find inner header point */
761 l3.hdr = skb_inner_network_header(skb);
762 l4_hdr = skb_inner_transport_header(skb);
763
764 if (l3.v6->version == 6) {
765 exthdr = l3.hdr + sizeof(*l3.v6);
766 l4_proto_tmp = l3.v6->nexthdr;
767 if (l4_hdr != exthdr)
768 ipv6_skip_exthdr(skb, exthdr - skb->data,
769 &l4_proto_tmp, &frag_off);
770 } else if (l3.v4->version == 4) {
771 l4_proto_tmp = l3.v4->protocol;
772 }
773
774 *il4_proto = l4_proto_tmp;
775
776 return 0;
777 }
778
779 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
780 * and it is udp packet, which has a dest port as the IANA assigned.
781 * the hardware is expected to do the checksum offload, but the
782 * hardware will not do the checksum offload when udp dest port is
783 * 4789.
784 */
785 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
786 {
787 union l4_hdr_info l4;
788
789 l4.hdr = skb_transport_header(skb);
790
791 if (!(!skb->encapsulation &&
792 l4.udp->dest == htons(IANA_VXLAN_UDP_PORT)))
793 return false;
794
795 skb_checksum_help(skb);
796
797 return true;
798 }
799
800 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
801 u32 *ol_type_vlan_len_msec)
802 {
803 u32 l2_len, l3_len, l4_len;
804 unsigned char *il2_hdr;
805 union l3_hdr_info l3;
806 union l4_hdr_info l4;
807
808 l3.hdr = skb_network_header(skb);
809 l4.hdr = skb_transport_header(skb);
810
811 /* compute OL2 header size, defined in 2 Bytes */
812 l2_len = l3.hdr - skb->data;
813 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
814
815 /* compute OL3 header size, defined in 4 Bytes */
816 l3_len = l4.hdr - l3.hdr;
817 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
818
819 il2_hdr = skb_inner_mac_header(skb);
820 /* compute OL4 header size, defined in 4 Bytes */
821 l4_len = il2_hdr - l4.hdr;
822 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
823
824 /* define outer network header type */
825 if (skb->protocol == htons(ETH_P_IP)) {
826 if (skb_is_gso(skb))
827 hns3_set_field(*ol_type_vlan_len_msec,
828 HNS3_TXD_OL3T_S,
829 HNS3_OL3T_IPV4_CSUM);
830 else
831 hns3_set_field(*ol_type_vlan_len_msec,
832 HNS3_TXD_OL3T_S,
833 HNS3_OL3T_IPV4_NO_CSUM);
834
835 } else if (skb->protocol == htons(ETH_P_IPV6)) {
836 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
837 HNS3_OL3T_IPV6);
838 }
839
840 if (ol4_proto == IPPROTO_UDP)
841 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
842 HNS3_TUN_MAC_IN_UDP);
843 else if (ol4_proto == IPPROTO_GRE)
844 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
845 HNS3_TUN_NVGRE);
846 }
847
848 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
849 u8 il4_proto, u32 *type_cs_vlan_tso,
850 u32 *ol_type_vlan_len_msec)
851 {
852 unsigned char *l2_hdr = skb->data;
853 u32 l4_proto = ol4_proto;
854 union l4_hdr_info l4;
855 union l3_hdr_info l3;
856 u32 l2_len, l3_len;
857
858 l4.hdr = skb_transport_header(skb);
859 l3.hdr = skb_network_header(skb);
860
861 /* handle encapsulation skb */
862 if (skb->encapsulation) {
863 /* If this is a not UDP/GRE encapsulation skb */
864 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
865 /* drop the skb tunnel packet if hardware don't support,
866 * because hardware can't calculate csum when TSO.
867 */
868 if (skb_is_gso(skb))
869 return -EDOM;
870
871 /* the stack computes the IP header already,
872 * driver calculate l4 checksum when not TSO.
873 */
874 skb_checksum_help(skb);
875 return 0;
876 }
877
878 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
879
880 /* switch to inner header */
881 l2_hdr = skb_inner_mac_header(skb);
882 l3.hdr = skb_inner_network_header(skb);
883 l4.hdr = skb_inner_transport_header(skb);
884 l4_proto = il4_proto;
885 }
886
887 if (l3.v4->version == 4) {
888 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
889 HNS3_L3T_IPV4);
890
891 /* the stack computes the IP header already, the only time we
892 * need the hardware to recompute it is in the case of TSO.
893 */
894 if (skb_is_gso(skb))
895 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
896 } else if (l3.v6->version == 6) {
897 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
898 HNS3_L3T_IPV6);
899 }
900
901 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
902 l2_len = l3.hdr - l2_hdr;
903 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
904
905 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
906 l3_len = l4.hdr - l3.hdr;
907 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
908
909 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
910 switch (l4_proto) {
911 case IPPROTO_TCP:
912 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
913 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
914 HNS3_L4T_TCP);
915 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
916 l4.tcp->doff);
917 break;
918 case IPPROTO_UDP:
919 if (hns3_tunnel_csum_bug(skb))
920 break;
921
922 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
923 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
924 HNS3_L4T_UDP);
925 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
926 (sizeof(struct udphdr) >> 2));
927 break;
928 case IPPROTO_SCTP:
929 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
930 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
931 HNS3_L4T_SCTP);
932 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
933 (sizeof(struct sctphdr) >> 2));
934 break;
935 default:
936 /* drop the skb tunnel packet if hardware don't support,
937 * because hardware can't calculate csum when TSO.
938 */
939 if (skb_is_gso(skb))
940 return -EDOM;
941
942 /* the stack computes the IP header already,
943 * driver calculate l4 checksum when not TSO.
944 */
945 skb_checksum_help(skb);
946 return 0;
947 }
948
949 return 0;
950 }
951
952 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
953 struct sk_buff *skb)
954 {
955 struct hnae3_handle *handle = tx_ring->tqp->handle;
956 struct vlan_ethhdr *vhdr;
957 int rc;
958
959 if (!(skb->protocol == htons(ETH_P_8021Q) ||
960 skb_vlan_tag_present(skb)))
961 return 0;
962
963 /* Since HW limitation, if port based insert VLAN enabled, only one VLAN
964 * header is allowed in skb, otherwise it will cause RAS error.
965 */
966 if (unlikely(skb_vlan_tagged_multi(skb) &&
967 handle->port_base_vlan_state ==
968 HNAE3_PORT_BASE_VLAN_ENABLE))
969 return -EINVAL;
970
971 if (skb->protocol == htons(ETH_P_8021Q) &&
972 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
973 /* When HW VLAN acceleration is turned off, and the stack
974 * sets the protocol to 802.1q, the driver just need to
975 * set the protocol to the encapsulated ethertype.
976 */
977 skb->protocol = vlan_get_protocol(skb);
978 return 0;
979 }
980
981 if (skb_vlan_tag_present(skb)) {
982 /* Based on hw strategy, use out_vtag in two layer tag case,
983 * and use inner_vtag in one tag case.
984 */
985 if (skb->protocol == htons(ETH_P_8021Q) &&
986 handle->port_base_vlan_state ==
987 HNAE3_PORT_BASE_VLAN_DISABLE)
988 rc = HNS3_OUTER_VLAN_TAG;
989 else
990 rc = HNS3_INNER_VLAN_TAG;
991
992 skb->protocol = vlan_get_protocol(skb);
993 return rc;
994 }
995
996 rc = skb_cow_head(skb, 0);
997 if (unlikely(rc < 0))
998 return rc;
999
1000 vhdr = (struct vlan_ethhdr *)skb->data;
1001 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1002 & VLAN_PRIO_MASK);
1003
1004 skb->protocol = vlan_get_protocol(skb);
1005 return 0;
1006 }
1007
1008 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
1009 struct sk_buff *skb, struct hns3_desc *desc)
1010 {
1011 u32 ol_type_vlan_len_msec = 0;
1012 u32 type_cs_vlan_tso = 0;
1013 u32 paylen = skb->len;
1014 u16 inner_vtag = 0;
1015 u16 out_vtag = 0;
1016 u16 mss = 0;
1017 int ret;
1018
1019 ret = hns3_handle_vtags(ring, skb);
1020 if (unlikely(ret < 0)) {
1021 u64_stats_update_begin(&ring->syncp);
1022 ring->stats.tx_vlan_err++;
1023 u64_stats_update_end(&ring->syncp);
1024 return ret;
1025 } else if (ret == HNS3_INNER_VLAN_TAG) {
1026 inner_vtag = skb_vlan_tag_get(skb);
1027 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1028 VLAN_PRIO_MASK;
1029 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1030 } else if (ret == HNS3_OUTER_VLAN_TAG) {
1031 out_vtag = skb_vlan_tag_get(skb);
1032 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1033 VLAN_PRIO_MASK;
1034 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1035 1);
1036 }
1037
1038 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1039 u8 ol4_proto, il4_proto;
1040
1041 skb_reset_mac_len(skb);
1042
1043 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1044 if (unlikely(ret < 0)) {
1045 u64_stats_update_begin(&ring->syncp);
1046 ring->stats.tx_l4_proto_err++;
1047 u64_stats_update_end(&ring->syncp);
1048 return ret;
1049 }
1050
1051 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1052 &type_cs_vlan_tso,
1053 &ol_type_vlan_len_msec);
1054 if (unlikely(ret < 0)) {
1055 u64_stats_update_begin(&ring->syncp);
1056 ring->stats.tx_l2l3l4_err++;
1057 u64_stats_update_end(&ring->syncp);
1058 return ret;
1059 }
1060
1061 ret = hns3_set_tso(skb, &paylen, &mss,
1062 &type_cs_vlan_tso);
1063 if (unlikely(ret < 0)) {
1064 u64_stats_update_begin(&ring->syncp);
1065 ring->stats.tx_tso_err++;
1066 u64_stats_update_end(&ring->syncp);
1067 return ret;
1068 }
1069 }
1070
1071 /* Set txbd */
1072 desc->tx.ol_type_vlan_len_msec =
1073 cpu_to_le32(ol_type_vlan_len_msec);
1074 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso);
1075 desc->tx.paylen = cpu_to_le32(paylen);
1076 desc->tx.mss = cpu_to_le16(mss);
1077 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1078 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
1079
1080 return 0;
1081 }
1082
1083 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
1084 unsigned int size, enum hns_desc_type type)
1085 {
1086 #define HNS3_LIKELY_BD_NUM 1
1087
1088 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1089 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1090 struct device *dev = ring_to_dev(ring);
1091 skb_frag_t *frag;
1092 unsigned int frag_buf_num;
1093 int k, sizeoflast;
1094 dma_addr_t dma;
1095
1096 if (type == DESC_TYPE_FRAGLIST_SKB ||
1097 type == DESC_TYPE_SKB) {
1098 struct sk_buff *skb = (struct sk_buff *)priv;
1099
1100 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1101 } else {
1102 frag = (skb_frag_t *)priv;
1103 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1104 }
1105
1106 if (unlikely(dma_mapping_error(dev, dma))) {
1107 u64_stats_update_begin(&ring->syncp);
1108 ring->stats.sw_err_cnt++;
1109 u64_stats_update_end(&ring->syncp);
1110 return -ENOMEM;
1111 }
1112
1113 desc_cb->priv = priv;
1114 desc_cb->length = size;
1115 desc_cb->dma = dma;
1116 desc_cb->type = type;
1117
1118 if (likely(size <= HNS3_MAX_BD_SIZE)) {
1119 desc->addr = cpu_to_le64(dma);
1120 desc->tx.send_size = cpu_to_le16(size);
1121 desc->tx.bdtp_fe_sc_vld_ra_ri =
1122 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1123
1124 trace_hns3_tx_desc(ring, ring->next_to_use);
1125 ring_ptr_move_fw(ring, next_to_use);
1126 return HNS3_LIKELY_BD_NUM;
1127 }
1128
1129 frag_buf_num = hns3_tx_bd_count(size);
1130 sizeoflast = size % HNS3_MAX_BD_SIZE;
1131 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1132
1133 /* When frag size is bigger than hardware limit, split this frag */
1134 for (k = 0; k < frag_buf_num; k++) {
1135 /* now, fill the descriptor */
1136 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
1137 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1138 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1139 desc->tx.bdtp_fe_sc_vld_ra_ri =
1140 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1141
1142 trace_hns3_tx_desc(ring, ring->next_to_use);
1143 /* move ring pointer to next */
1144 ring_ptr_move_fw(ring, next_to_use);
1145
1146 desc = &ring->desc[ring->next_to_use];
1147 }
1148
1149 return frag_buf_num;
1150 }
1151
1152 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1153 unsigned int bd_num)
1154 {
1155 unsigned int size;
1156 int i;
1157
1158 size = skb_headlen(skb);
1159 while (size > HNS3_MAX_BD_SIZE) {
1160 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1161 size -= HNS3_MAX_BD_SIZE;
1162
1163 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1164 return bd_num;
1165 }
1166
1167 if (size) {
1168 bd_size[bd_num++] = size;
1169 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1170 return bd_num;
1171 }
1172
1173 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1174 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1175 size = skb_frag_size(frag);
1176 if (!size)
1177 continue;
1178
1179 while (size > HNS3_MAX_BD_SIZE) {
1180 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1181 size -= HNS3_MAX_BD_SIZE;
1182
1183 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1184 return bd_num;
1185 }
1186
1187 bd_size[bd_num++] = size;
1188 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1189 return bd_num;
1190 }
1191
1192 return bd_num;
1193 }
1194
1195 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size)
1196 {
1197 struct sk_buff *frag_skb;
1198 unsigned int bd_num = 0;
1199
1200 /* If the total len is within the max bd limit */
1201 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !skb_has_frag_list(skb) &&
1202 skb_shinfo(skb)->nr_frags < HNS3_MAX_NON_TSO_BD_NUM))
1203 return skb_shinfo(skb)->nr_frags + 1U;
1204
1205 /* The below case will always be linearized, return
1206 * HNS3_MAX_BD_NUM_TSO + 1U to make sure it is linearized.
1207 */
1208 if (unlikely(skb->len > HNS3_MAX_TSO_SIZE ||
1209 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)))
1210 return HNS3_MAX_TSO_BD_NUM + 1U;
1211
1212 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1213
1214 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1215 return bd_num;
1216
1217 skb_walk_frags(skb, frag_skb) {
1218 bd_num = hns3_skb_bd_num(frag_skb, bd_size, bd_num);
1219 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1220 return bd_num;
1221 }
1222
1223 return bd_num;
1224 }
1225
1226 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1227 {
1228 if (!skb->encapsulation)
1229 return skb_transport_offset(skb) + tcp_hdrlen(skb);
1230
1231 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
1232 }
1233
1234 /* HW need every continuous 8 buffer data to be larger than MSS,
1235 * we simplify it by ensuring skb_headlen + the first continuous
1236 * 7 frags to to be larger than gso header len + mss, and the remaining
1237 * continuous 7 frags to be larger than MSS except the last 7 frags.
1238 */
1239 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
1240 unsigned int bd_num)
1241 {
1242 unsigned int tot_len = 0;
1243 int i;
1244
1245 for (i = 0; i < HNS3_MAX_NON_TSO_BD_NUM - 1U; i++)
1246 tot_len += bd_size[i];
1247
1248 /* ensure the first 8 frags is greater than mss + header */
1249 if (tot_len + bd_size[HNS3_MAX_NON_TSO_BD_NUM - 1U] <
1250 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
1251 return true;
1252
1253 /* ensure every continuous 7 buffer is greater than mss
1254 * except the last one.
1255 */
1256 for (i = 0; i < bd_num - HNS3_MAX_NON_TSO_BD_NUM; i++) {
1257 tot_len -= bd_size[i];
1258 tot_len += bd_size[i + HNS3_MAX_NON_TSO_BD_NUM - 1U];
1259
1260 if (tot_len < skb_shinfo(skb)->gso_size)
1261 return true;
1262 }
1263
1264 return false;
1265 }
1266
1267 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1268 {
1269 int i = 0;
1270
1271 for (i = 0; i < MAX_SKB_FRAGS; i++)
1272 size[i] = skb_frag_size(&shinfo->frags[i]);
1273 }
1274
1275 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
1276 struct net_device *netdev,
1277 struct sk_buff *skb)
1278 {
1279 struct hns3_nic_priv *priv = netdev_priv(netdev);
1280 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
1281 unsigned int bd_num;
1282
1283 bd_num = hns3_tx_bd_num(skb, bd_size);
1284 if (unlikely(bd_num > HNS3_MAX_NON_TSO_BD_NUM)) {
1285 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
1286 !hns3_skb_need_linearized(skb, bd_size, bd_num)) {
1287 trace_hns3_over_8bd(skb);
1288 goto out;
1289 }
1290
1291 if (__skb_linearize(skb))
1292 return -ENOMEM;
1293
1294 bd_num = hns3_tx_bd_count(skb->len);
1295 if ((skb_is_gso(skb) && bd_num > HNS3_MAX_TSO_BD_NUM) ||
1296 (!skb_is_gso(skb) &&
1297 bd_num > HNS3_MAX_NON_TSO_BD_NUM)) {
1298 trace_hns3_over_8bd(skb);
1299 return -ENOMEM;
1300 }
1301
1302 u64_stats_update_begin(&ring->syncp);
1303 ring->stats.tx_copy++;
1304 u64_stats_update_end(&ring->syncp);
1305 }
1306
1307 out:
1308 if (likely(ring_space(ring) >= bd_num))
1309 return bd_num;
1310
1311 netif_stop_subqueue(netdev, ring->queue_index);
1312 smp_mb(); /* Memory barrier before checking ring_space */
1313
1314 /* Start queue in case hns3_clean_tx_ring has just made room
1315 * available and has not seen the queue stopped state performed
1316 * by netif_stop_subqueue above.
1317 */
1318 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1319 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1320 netif_start_subqueue(netdev, ring->queue_index);
1321 return bd_num;
1322 }
1323
1324 return -EBUSY;
1325 }
1326
1327 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
1328 {
1329 struct device *dev = ring_to_dev(ring);
1330 unsigned int i;
1331
1332 for (i = 0; i < ring->desc_num; i++) {
1333 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1334
1335 memset(desc, 0, sizeof(*desc));
1336
1337 /* check if this is where we started */
1338 if (ring->next_to_use == next_to_use_orig)
1339 break;
1340
1341 /* rollback one */
1342 ring_ptr_move_bw(ring, next_to_use);
1343
1344 if (!ring->desc_cb[ring->next_to_use].dma)
1345 continue;
1346
1347 /* unmap the descriptor dma address */
1348 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB ||
1349 ring->desc_cb[ring->next_to_use].type ==
1350 DESC_TYPE_FRAGLIST_SKB)
1351 dma_unmap_single(dev,
1352 ring->desc_cb[ring->next_to_use].dma,
1353 ring->desc_cb[ring->next_to_use].length,
1354 DMA_TO_DEVICE);
1355 else if (ring->desc_cb[ring->next_to_use].length)
1356 dma_unmap_page(dev,
1357 ring->desc_cb[ring->next_to_use].dma,
1358 ring->desc_cb[ring->next_to_use].length,
1359 DMA_TO_DEVICE);
1360
1361 ring->desc_cb[ring->next_to_use].length = 0;
1362 ring->desc_cb[ring->next_to_use].dma = 0;
1363 ring->desc_cb[ring->next_to_use].type = DESC_TYPE_UNKNOWN;
1364 }
1365 }
1366
1367 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
1368 struct sk_buff *skb, enum hns_desc_type type)
1369 {
1370 unsigned int size = skb_headlen(skb);
1371 int i, ret, bd_num = 0;
1372
1373 if (size) {
1374 ret = hns3_fill_desc(ring, skb, size, type);
1375 if (unlikely(ret < 0))
1376 return ret;
1377
1378 bd_num += ret;
1379 }
1380
1381 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1382 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1383
1384 size = skb_frag_size(frag);
1385 if (!size)
1386 continue;
1387
1388 ret = hns3_fill_desc(ring, frag, size, DESC_TYPE_PAGE);
1389 if (unlikely(ret < 0))
1390 return ret;
1391
1392 bd_num += ret;
1393 }
1394
1395 return bd_num;
1396 }
1397
1398 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
1399 {
1400 struct hns3_nic_priv *priv = netdev_priv(netdev);
1401 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
1402 struct netdev_queue *dev_queue;
1403 int pre_ntu, next_to_use_head;
1404 struct sk_buff *frag_skb;
1405 int bd_num = 0;
1406 int ret;
1407
1408 /* Hardware can only handle short frames above 32 bytes */
1409 if (skb_put_padto(skb, HNS3_MIN_TX_LEN))
1410 return NETDEV_TX_OK;
1411
1412 /* Prefetch the data used later */
1413 prefetch(skb->data);
1414
1415 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
1416 if (unlikely(ret <= 0)) {
1417 if (ret == -EBUSY) {
1418 u64_stats_update_begin(&ring->syncp);
1419 ring->stats.tx_busy++;
1420 u64_stats_update_end(&ring->syncp);
1421 return NETDEV_TX_BUSY;
1422 } else if (ret == -ENOMEM) {
1423 u64_stats_update_begin(&ring->syncp);
1424 ring->stats.sw_err_cnt++;
1425 u64_stats_update_end(&ring->syncp);
1426 }
1427
1428 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
1429 goto out_err_tx_ok;
1430 }
1431
1432 next_to_use_head = ring->next_to_use;
1433
1434 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use]);
1435 if (unlikely(ret < 0))
1436 goto fill_err;
1437
1438 ret = hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
1439 if (unlikely(ret < 0))
1440 goto fill_err;
1441
1442 bd_num += ret;
1443
1444 skb_walk_frags(skb, frag_skb) {
1445 ret = hns3_fill_skb_to_desc(ring, frag_skb,
1446 DESC_TYPE_FRAGLIST_SKB);
1447 if (unlikely(ret < 0))
1448 goto fill_err;
1449
1450 bd_num += ret;
1451 }
1452
1453 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
1454 (ring->desc_num - 1);
1455 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
1456 cpu_to_le16(BIT(HNS3_TXD_FE_B));
1457 trace_hns3_tx_desc(ring, pre_ntu);
1458
1459 /* Complete translate all packets */
1460 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
1461 netdev_tx_sent_queue(dev_queue, skb->len);
1462
1463 wmb(); /* Commit all data before submit */
1464
1465 hnae3_queue_xmit(ring->tqp, bd_num);
1466
1467 return NETDEV_TX_OK;
1468
1469 fill_err:
1470 hns3_clear_desc(ring, next_to_use_head);
1471
1472 out_err_tx_ok:
1473 dev_kfree_skb_any(skb);
1474 return NETDEV_TX_OK;
1475 }
1476
1477 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1478 {
1479 struct hnae3_handle *h = hns3_get_handle(netdev);
1480 struct sockaddr *mac_addr = p;
1481 int ret;
1482
1483 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1484 return -EADDRNOTAVAIL;
1485
1486 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1487 netdev_info(netdev, "already using mac address %pM\n",
1488 mac_addr->sa_data);
1489 return 0;
1490 }
1491
1492 /* For VF device, if there is a perm_addr, then the user will not
1493 * be allowed to change the address.
1494 */
1495 if (!hns3_is_phys_func(h->pdev) &&
1496 !is_zero_ether_addr(netdev->perm_addr)) {
1497 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n",
1498 netdev->perm_addr, mac_addr->sa_data);
1499 return -EPERM;
1500 }
1501
1502 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
1503 if (ret) {
1504 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1505 return ret;
1506 }
1507
1508 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1509
1510 return 0;
1511 }
1512
1513 static int hns3_nic_do_ioctl(struct net_device *netdev,
1514 struct ifreq *ifr, int cmd)
1515 {
1516 struct hnae3_handle *h = hns3_get_handle(netdev);
1517
1518 if (!netif_running(netdev))
1519 return -EINVAL;
1520
1521 if (!h->ae_algo->ops->do_ioctl)
1522 return -EOPNOTSUPP;
1523
1524 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1525 }
1526
1527 static int hns3_nic_set_features(struct net_device *netdev,
1528 netdev_features_t features)
1529 {
1530 netdev_features_t changed = netdev->features ^ features;
1531 struct hns3_nic_priv *priv = netdev_priv(netdev);
1532 struct hnae3_handle *h = priv->ae_handle;
1533 bool enable;
1534 int ret;
1535
1536 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1537 enable = !!(features & NETIF_F_GRO_HW);
1538 ret = h->ae_algo->ops->set_gro_en(h, enable);
1539 if (ret)
1540 return ret;
1541 }
1542
1543 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1544 h->ae_algo->ops->enable_hw_strip_rxvtag) {
1545 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
1546 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
1547 if (ret)
1548 return ret;
1549 }
1550
1551 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1552 enable = !!(features & NETIF_F_NTUPLE);
1553 h->ae_algo->ops->enable_fd(h, enable);
1554 }
1555
1556 netdev->features = features;
1557 return 0;
1558 }
1559
1560 static netdev_features_t hns3_features_check(struct sk_buff *skb,
1561 struct net_device *dev,
1562 netdev_features_t features)
1563 {
1564 #define HNS3_MAX_HDR_LEN 480U
1565 #define HNS3_MAX_L4_HDR_LEN 60U
1566
1567 size_t len;
1568
1569 if (skb->ip_summed != CHECKSUM_PARTIAL)
1570 return features;
1571
1572 if (skb->encapsulation)
1573 len = skb_inner_transport_header(skb) - skb->data;
1574 else
1575 len = skb_transport_header(skb) - skb->data;
1576
1577 /* Assume L4 is 60 byte as TCP is the only protocol with a
1578 * a flexible value, and it's max len is 60 bytes.
1579 */
1580 len += HNS3_MAX_L4_HDR_LEN;
1581
1582 /* Hardware only supports checksum on the skb with a max header
1583 * len of 480 bytes.
1584 */
1585 if (len > HNS3_MAX_HDR_LEN)
1586 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
1587
1588 return features;
1589 }
1590
1591 static void hns3_nic_get_stats64(struct net_device *netdev,
1592 struct rtnl_link_stats64 *stats)
1593 {
1594 struct hns3_nic_priv *priv = netdev_priv(netdev);
1595 int queue_num = priv->ae_handle->kinfo.num_tqps;
1596 struct hnae3_handle *handle = priv->ae_handle;
1597 struct hns3_enet_ring *ring;
1598 u64 rx_length_errors = 0;
1599 u64 rx_crc_errors = 0;
1600 u64 rx_multicast = 0;
1601 unsigned int start;
1602 u64 tx_errors = 0;
1603 u64 rx_errors = 0;
1604 unsigned int idx;
1605 u64 tx_bytes = 0;
1606 u64 rx_bytes = 0;
1607 u64 tx_pkts = 0;
1608 u64 rx_pkts = 0;
1609 u64 tx_drop = 0;
1610 u64 rx_drop = 0;
1611
1612 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1613 return;
1614
1615 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1616
1617 for (idx = 0; idx < queue_num; idx++) {
1618 /* fetch the tx stats */
1619 ring = &priv->ring[idx];
1620 do {
1621 start = u64_stats_fetch_begin_irq(&ring->syncp);
1622 tx_bytes += ring->stats.tx_bytes;
1623 tx_pkts += ring->stats.tx_pkts;
1624 tx_drop += ring->stats.sw_err_cnt;
1625 tx_drop += ring->stats.tx_vlan_err;
1626 tx_drop += ring->stats.tx_l4_proto_err;
1627 tx_drop += ring->stats.tx_l2l3l4_err;
1628 tx_drop += ring->stats.tx_tso_err;
1629 tx_errors += ring->stats.sw_err_cnt;
1630 tx_errors += ring->stats.tx_vlan_err;
1631 tx_errors += ring->stats.tx_l4_proto_err;
1632 tx_errors += ring->stats.tx_l2l3l4_err;
1633 tx_errors += ring->stats.tx_tso_err;
1634 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1635
1636 /* fetch the rx stats */
1637 ring = &priv->ring[idx + queue_num];
1638 do {
1639 start = u64_stats_fetch_begin_irq(&ring->syncp);
1640 rx_bytes += ring->stats.rx_bytes;
1641 rx_pkts += ring->stats.rx_pkts;
1642 rx_drop += ring->stats.l2_err;
1643 rx_errors += ring->stats.l2_err;
1644 rx_errors += ring->stats.l3l4_csum_err;
1645 rx_crc_errors += ring->stats.l2_err;
1646 rx_multicast += ring->stats.rx_multicast;
1647 rx_length_errors += ring->stats.err_pkt_len;
1648 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1649 }
1650
1651 stats->tx_bytes = tx_bytes;
1652 stats->tx_packets = tx_pkts;
1653 stats->rx_bytes = rx_bytes;
1654 stats->rx_packets = rx_pkts;
1655
1656 stats->rx_errors = rx_errors;
1657 stats->multicast = rx_multicast;
1658 stats->rx_length_errors = rx_length_errors;
1659 stats->rx_crc_errors = rx_crc_errors;
1660 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1661
1662 stats->tx_errors = tx_errors;
1663 stats->rx_dropped = rx_drop;
1664 stats->tx_dropped = tx_drop;
1665 stats->collisions = netdev->stats.collisions;
1666 stats->rx_over_errors = netdev->stats.rx_over_errors;
1667 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1668 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1669 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1670 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1671 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1672 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1673 stats->tx_window_errors = netdev->stats.tx_window_errors;
1674 stats->rx_compressed = netdev->stats.rx_compressed;
1675 stats->tx_compressed = netdev->stats.tx_compressed;
1676 }
1677
1678 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
1679 {
1680 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
1681 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
1682 struct hnae3_knic_private_info *kinfo;
1683 u8 tc = mqprio_qopt->qopt.num_tc;
1684 u16 mode = mqprio_qopt->mode;
1685 u8 hw = mqprio_qopt->qopt.hw;
1686 struct hnae3_handle *h;
1687
1688 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1689 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1690 return -EOPNOTSUPP;
1691
1692 if (tc > HNAE3_MAX_TC)
1693 return -EINVAL;
1694
1695 if (!netdev)
1696 return -EINVAL;
1697
1698 h = hns3_get_handle(netdev);
1699 kinfo = &h->kinfo;
1700
1701 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
1702
1703 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
1704 kinfo->dcb_ops->setup_tc(h, tc ? tc : 1, prio_tc) : -EOPNOTSUPP;
1705 }
1706
1707 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
1708 void *type_data)
1709 {
1710 if (type != TC_SETUP_QDISC_MQPRIO)
1711 return -EOPNOTSUPP;
1712
1713 return hns3_setup_tc(dev, type_data);
1714 }
1715
1716 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1717 __be16 proto, u16 vid)
1718 {
1719 struct hnae3_handle *h = hns3_get_handle(netdev);
1720 int ret = -EIO;
1721
1722 if (h->ae_algo->ops->set_vlan_filter)
1723 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1724
1725 return ret;
1726 }
1727
1728 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1729 __be16 proto, u16 vid)
1730 {
1731 struct hnae3_handle *h = hns3_get_handle(netdev);
1732 int ret = -EIO;
1733
1734 if (h->ae_algo->ops->set_vlan_filter)
1735 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1736
1737 return ret;
1738 }
1739
1740 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1741 u8 qos, __be16 vlan_proto)
1742 {
1743 struct hnae3_handle *h = hns3_get_handle(netdev);
1744 int ret = -EIO;
1745
1746 netif_dbg(h, drv, netdev,
1747 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
1748 vf, vlan, qos, ntohs(vlan_proto));
1749
1750 if (h->ae_algo->ops->set_vf_vlan_filter)
1751 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
1752 qos, vlan_proto);
1753
1754 return ret;
1755 }
1756
1757 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
1758 {
1759 struct hnae3_handle *handle = hns3_get_handle(netdev);
1760
1761 if (hns3_nic_resetting(netdev))
1762 return -EBUSY;
1763
1764 if (!handle->ae_algo->ops->set_vf_spoofchk)
1765 return -EOPNOTSUPP;
1766
1767 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
1768 }
1769
1770 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
1771 {
1772 struct hnae3_handle *handle = hns3_get_handle(netdev);
1773
1774 if (!handle->ae_algo->ops->set_vf_trust)
1775 return -EOPNOTSUPP;
1776
1777 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
1778 }
1779
1780 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1781 {
1782 struct hnae3_handle *h = hns3_get_handle(netdev);
1783 int ret;
1784
1785 if (hns3_nic_resetting(netdev))
1786 return -EBUSY;
1787
1788 if (!h->ae_algo->ops->set_mtu)
1789 return -EOPNOTSUPP;
1790
1791 netif_dbg(h, drv, netdev,
1792 "change mtu from %u to %d\n", netdev->mtu, new_mtu);
1793
1794 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
1795 if (ret)
1796 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1797 ret);
1798 else
1799 netdev->mtu = new_mtu;
1800
1801 return ret;
1802 }
1803
1804 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1805 {
1806 struct hns3_nic_priv *priv = netdev_priv(ndev);
1807 struct hnae3_handle *h = hns3_get_handle(ndev);
1808 struct hns3_enet_ring *tx_ring;
1809 struct napi_struct *napi;
1810 int timeout_queue = 0;
1811 int hw_head, hw_tail;
1812 int fbd_num, fbd_oft;
1813 int ebd_num, ebd_oft;
1814 int bd_num, bd_err;
1815 int ring_en, tc;
1816 int i;
1817
1818 /* Find the stopped queue the same way the stack does */
1819 for (i = 0; i < ndev->num_tx_queues; i++) {
1820 struct netdev_queue *q;
1821 unsigned long trans_start;
1822
1823 q = netdev_get_tx_queue(ndev, i);
1824 trans_start = q->trans_start;
1825 if (netif_xmit_stopped(q) &&
1826 time_after(jiffies,
1827 (trans_start + ndev->watchdog_timeo))) {
1828 timeout_queue = i;
1829 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
1830 q->state,
1831 jiffies_to_msecs(jiffies - trans_start));
1832 break;
1833 }
1834 }
1835
1836 if (i == ndev->num_tx_queues) {
1837 netdev_info(ndev,
1838 "no netdev TX timeout queue found, timeout count: %llu\n",
1839 priv->tx_timeout_count);
1840 return false;
1841 }
1842
1843 priv->tx_timeout_count++;
1844
1845 tx_ring = &priv->ring[timeout_queue];
1846 napi = &tx_ring->tqp_vector->napi;
1847
1848 netdev_info(ndev,
1849 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
1850 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
1851 tx_ring->next_to_clean, napi->state);
1852
1853 netdev_info(ndev,
1854 "tx_pkts: %llu, tx_bytes: %llu, io_err_cnt: %llu, sw_err_cnt: %llu\n",
1855 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
1856 tx_ring->stats.io_err_cnt, tx_ring->stats.sw_err_cnt);
1857
1858 netdev_info(ndev,
1859 "seg_pkt_cnt: %llu, tx_err_cnt: %llu, restart_queue: %llu, tx_busy: %llu\n",
1860 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_err_cnt,
1861 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
1862
1863 /* When mac received many pause frames continuous, it's unable to send
1864 * packets, which may cause tx timeout
1865 */
1866 if (h->ae_algo->ops->get_mac_stats) {
1867 struct hns3_mac_stats mac_stats;
1868
1869 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
1870 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
1871 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
1872 }
1873
1874 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1875 HNS3_RING_TX_RING_HEAD_REG);
1876 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1877 HNS3_RING_TX_RING_TAIL_REG);
1878 fbd_num = readl_relaxed(tx_ring->tqp->io_base +
1879 HNS3_RING_TX_RING_FBDNUM_REG);
1880 fbd_oft = readl_relaxed(tx_ring->tqp->io_base +
1881 HNS3_RING_TX_RING_OFFSET_REG);
1882 ebd_num = readl_relaxed(tx_ring->tqp->io_base +
1883 HNS3_RING_TX_RING_EBDNUM_REG);
1884 ebd_oft = readl_relaxed(tx_ring->tqp->io_base +
1885 HNS3_RING_TX_RING_EBD_OFFSET_REG);
1886 bd_num = readl_relaxed(tx_ring->tqp->io_base +
1887 HNS3_RING_TX_RING_BD_NUM_REG);
1888 bd_err = readl_relaxed(tx_ring->tqp->io_base +
1889 HNS3_RING_TX_RING_BD_ERR_REG);
1890 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG);
1891 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG);
1892
1893 netdev_info(ndev,
1894 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
1895 bd_num, hw_head, hw_tail, bd_err,
1896 readl(tx_ring->tqp_vector->mask_addr));
1897 netdev_info(ndev,
1898 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
1899 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft);
1900
1901 return true;
1902 }
1903
1904 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
1905 {
1906 struct hns3_nic_priv *priv = netdev_priv(ndev);
1907 struct hnae3_handle *h = priv->ae_handle;
1908
1909 if (!hns3_get_tx_timeo_queue_info(ndev))
1910 return;
1911
1912 /* request the reset, and let the hclge to determine
1913 * which reset level should be done
1914 */
1915 if (h->ae_algo->ops->reset_event)
1916 h->ae_algo->ops->reset_event(h->pdev, h);
1917 }
1918
1919 #ifdef CONFIG_RFS_ACCEL
1920 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
1921 u16 rxq_index, u32 flow_id)
1922 {
1923 struct hnae3_handle *h = hns3_get_handle(dev);
1924 struct flow_keys fkeys;
1925
1926 if (!h->ae_algo->ops->add_arfs_entry)
1927 return -EOPNOTSUPP;
1928
1929 if (skb->encapsulation)
1930 return -EPROTONOSUPPORT;
1931
1932 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
1933 return -EPROTONOSUPPORT;
1934
1935 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
1936 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
1937 (fkeys.basic.ip_proto != IPPROTO_TCP &&
1938 fkeys.basic.ip_proto != IPPROTO_UDP))
1939 return -EPROTONOSUPPORT;
1940
1941 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
1942 }
1943 #endif
1944
1945 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
1946 struct ifla_vf_info *ivf)
1947 {
1948 struct hnae3_handle *h = hns3_get_handle(ndev);
1949
1950 if (!h->ae_algo->ops->get_vf_config)
1951 return -EOPNOTSUPP;
1952
1953 return h->ae_algo->ops->get_vf_config(h, vf, ivf);
1954 }
1955
1956 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
1957 int link_state)
1958 {
1959 struct hnae3_handle *h = hns3_get_handle(ndev);
1960
1961 if (!h->ae_algo->ops->set_vf_link_state)
1962 return -EOPNOTSUPP;
1963
1964 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
1965 }
1966
1967 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
1968 int min_tx_rate, int max_tx_rate)
1969 {
1970 struct hnae3_handle *h = hns3_get_handle(ndev);
1971
1972 if (!h->ae_algo->ops->set_vf_rate)
1973 return -EOPNOTSUPP;
1974
1975 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
1976 false);
1977 }
1978
1979 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
1980 {
1981 struct hnae3_handle *h = hns3_get_handle(netdev);
1982
1983 if (!h->ae_algo->ops->set_vf_mac)
1984 return -EOPNOTSUPP;
1985
1986 if (is_multicast_ether_addr(mac)) {
1987 netdev_err(netdev,
1988 "Invalid MAC:%pM specified. Could not set MAC\n",
1989 mac);
1990 return -EINVAL;
1991 }
1992
1993 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
1994 }
1995
1996 static const struct net_device_ops hns3_nic_netdev_ops = {
1997 .ndo_open = hns3_nic_net_open,
1998 .ndo_stop = hns3_nic_net_stop,
1999 .ndo_start_xmit = hns3_nic_net_xmit,
2000 .ndo_tx_timeout = hns3_nic_net_timeout,
2001 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
2002 .ndo_do_ioctl = hns3_nic_do_ioctl,
2003 .ndo_change_mtu = hns3_nic_change_mtu,
2004 .ndo_set_features = hns3_nic_set_features,
2005 .ndo_features_check = hns3_features_check,
2006 .ndo_get_stats64 = hns3_nic_get_stats64,
2007 .ndo_setup_tc = hns3_nic_setup_tc,
2008 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
2009 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
2010 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
2011 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
2012 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk,
2013 .ndo_set_vf_trust = hns3_set_vf_trust,
2014 #ifdef CONFIG_RFS_ACCEL
2015 .ndo_rx_flow_steer = hns3_rx_flow_steer,
2016 #endif
2017 .ndo_get_vf_config = hns3_nic_get_vf_config,
2018 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state,
2019 .ndo_set_vf_rate = hns3_nic_set_vf_rate,
2020 .ndo_set_vf_mac = hns3_nic_set_vf_mac,
2021 };
2022
2023 bool hns3_is_phys_func(struct pci_dev *pdev)
2024 {
2025 u32 dev_id = pdev->device;
2026
2027 switch (dev_id) {
2028 case HNAE3_DEV_ID_GE:
2029 case HNAE3_DEV_ID_25GE:
2030 case HNAE3_DEV_ID_25GE_RDMA:
2031 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
2032 case HNAE3_DEV_ID_50GE_RDMA:
2033 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
2034 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
2035 return true;
2036 case HNAE3_DEV_ID_100G_VF:
2037 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
2038 return false;
2039 default:
2040 dev_warn(&pdev->dev, "un-recognized pci device-id %u",
2041 dev_id);
2042 }
2043
2044 return false;
2045 }
2046
2047 static void hns3_disable_sriov(struct pci_dev *pdev)
2048 {
2049 /* If our VFs are assigned we cannot shut down SR-IOV
2050 * without causing issues, so just leave the hardware
2051 * available but disabled
2052 */
2053 if (pci_vfs_assigned(pdev)) {
2054 dev_warn(&pdev->dev,
2055 "disabling driver while VFs are assigned\n");
2056 return;
2057 }
2058
2059 pci_disable_sriov(pdev);
2060 }
2061
2062 static void hns3_get_dev_capability(struct pci_dev *pdev,
2063 struct hnae3_ae_dev *ae_dev)
2064 {
2065 if (pdev->revision >= 0x21) {
2066 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
2067 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
2068 }
2069 }
2070
2071 /* hns3_probe - Device initialization routine
2072 * @pdev: PCI device information struct
2073 * @ent: entry in hns3_pci_tbl
2074 *
2075 * hns3_probe initializes a PF identified by a pci_dev structure.
2076 * The OS initialization, configuring of the PF private structure,
2077 * and a hardware reset occur.
2078 *
2079 * Returns 0 on success, negative on failure
2080 */
2081 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2082 {
2083 struct hnae3_ae_dev *ae_dev;
2084 int ret;
2085
2086 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
2087 if (!ae_dev)
2088 return -ENOMEM;
2089
2090 ae_dev->pdev = pdev;
2091 ae_dev->flag = ent->driver_data;
2092 hns3_get_dev_capability(pdev, ae_dev);
2093 pci_set_drvdata(pdev, ae_dev);
2094
2095 ret = hnae3_register_ae_dev(ae_dev);
2096 if (ret)
2097 pci_set_drvdata(pdev, NULL);
2098
2099 return ret;
2100 }
2101
2102 /* hns3_remove - Device removal routine
2103 * @pdev: PCI device information struct
2104 */
2105 static void hns3_remove(struct pci_dev *pdev)
2106 {
2107 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2108
2109 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
2110 hns3_disable_sriov(pdev);
2111
2112 hnae3_unregister_ae_dev(ae_dev);
2113 pci_set_drvdata(pdev, NULL);
2114 }
2115
2116 /**
2117 * hns3_pci_sriov_configure
2118 * @pdev: pointer to a pci_dev structure
2119 * @num_vfs: number of VFs to allocate
2120 *
2121 * Enable or change the number of VFs. Called when the user updates the number
2122 * of VFs in sysfs.
2123 **/
2124 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
2125 {
2126 int ret;
2127
2128 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
2129 dev_warn(&pdev->dev, "Can not config SRIOV\n");
2130 return -EINVAL;
2131 }
2132
2133 if (num_vfs) {
2134 ret = pci_enable_sriov(pdev, num_vfs);
2135 if (ret)
2136 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
2137 else
2138 return num_vfs;
2139 } else if (!pci_vfs_assigned(pdev)) {
2140 pci_disable_sriov(pdev);
2141 } else {
2142 dev_warn(&pdev->dev,
2143 "Unable to free VFs because some are assigned to VMs.\n");
2144 }
2145
2146 return 0;
2147 }
2148
2149 static void hns3_shutdown(struct pci_dev *pdev)
2150 {
2151 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2152
2153 hnae3_unregister_ae_dev(ae_dev);
2154 pci_set_drvdata(pdev, NULL);
2155
2156 if (system_state == SYSTEM_POWER_OFF)
2157 pci_set_power_state(pdev, PCI_D3hot);
2158 }
2159
2160 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
2161 pci_channel_state_t state)
2162 {
2163 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2164 pci_ers_result_t ret;
2165
2166 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
2167
2168 if (state == pci_channel_io_perm_failure)
2169 return PCI_ERS_RESULT_DISCONNECT;
2170
2171 if (!ae_dev || !ae_dev->ops) {
2172 dev_err(&pdev->dev,
2173 "Can't recover - error happened before device initialized\n");
2174 return PCI_ERS_RESULT_NONE;
2175 }
2176
2177 if (ae_dev->ops->handle_hw_ras_error)
2178 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
2179 else
2180 return PCI_ERS_RESULT_NONE;
2181
2182 return ret;
2183 }
2184
2185 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
2186 {
2187 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2188 const struct hnae3_ae_ops *ops;
2189 enum hnae3_reset_type reset_type;
2190 struct device *dev = &pdev->dev;
2191
2192 if (!ae_dev || !ae_dev->ops)
2193 return PCI_ERS_RESULT_NONE;
2194
2195 ops = ae_dev->ops;
2196 /* request the reset */
2197 if (ops->reset_event && ops->get_reset_level &&
2198 ops->set_default_reset_request) {
2199 if (ae_dev->hw_err_reset_req) {
2200 reset_type = ops->get_reset_level(ae_dev,
2201 &ae_dev->hw_err_reset_req);
2202 ops->set_default_reset_request(ae_dev, reset_type);
2203 dev_info(dev, "requesting reset due to PCI error\n");
2204 ops->reset_event(pdev, NULL);
2205 }
2206
2207 return PCI_ERS_RESULT_RECOVERED;
2208 }
2209
2210 return PCI_ERS_RESULT_DISCONNECT;
2211 }
2212
2213 static void hns3_reset_prepare(struct pci_dev *pdev)
2214 {
2215 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2216
2217 dev_info(&pdev->dev, "FLR prepare\n");
2218 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare)
2219 ae_dev->ops->flr_prepare(ae_dev);
2220 }
2221
2222 static void hns3_reset_done(struct pci_dev *pdev)
2223 {
2224 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2225
2226 dev_info(&pdev->dev, "FLR done\n");
2227 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done)
2228 ae_dev->ops->flr_done(ae_dev);
2229 }
2230
2231 static const struct pci_error_handlers hns3_err_handler = {
2232 .error_detected = hns3_error_detected,
2233 .slot_reset = hns3_slot_reset,
2234 .reset_prepare = hns3_reset_prepare,
2235 .reset_done = hns3_reset_done,
2236 };
2237
2238 static struct pci_driver hns3_driver = {
2239 .name = hns3_driver_name,
2240 .id_table = hns3_pci_tbl,
2241 .probe = hns3_probe,
2242 .remove = hns3_remove,
2243 .shutdown = hns3_shutdown,
2244 .sriov_configure = hns3_pci_sriov_configure,
2245 .err_handler = &hns3_err_handler,
2246 };
2247
2248 /* set default feature to hns3 */
2249 static void hns3_set_default_feature(struct net_device *netdev)
2250 {
2251 struct hnae3_handle *h = hns3_get_handle(netdev);
2252 struct pci_dev *pdev = h->pdev;
2253
2254 netdev->priv_flags |= IFF_UNICAST_FLT;
2255
2256 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2257 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2258 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2259 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2260 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2261 NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST;
2262
2263 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
2264
2265 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2266 NETIF_F_HW_VLAN_CTAG_FILTER |
2267 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2268 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2269 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2270 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2271 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2272 NETIF_F_FRAGLIST;
2273
2274 netdev->vlan_features |=
2275 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
2276 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
2277 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2278 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2279 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2280 NETIF_F_FRAGLIST;
2281
2282 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2283 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2284 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2285 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2286 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2287 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2288 NETIF_F_FRAGLIST;
2289
2290 if (pdev->revision >= 0x21) {
2291 netdev->hw_features |= NETIF_F_GRO_HW;
2292 netdev->features |= NETIF_F_GRO_HW;
2293
2294 if (!(h->flags & HNAE3_SUPPORT_VF)) {
2295 netdev->hw_features |= NETIF_F_NTUPLE;
2296 netdev->features |= NETIF_F_NTUPLE;
2297 }
2298 }
2299 }
2300
2301 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
2302 struct hns3_desc_cb *cb)
2303 {
2304 unsigned int order = hns3_page_order(ring);
2305 struct page *p;
2306
2307 p = dev_alloc_pages(order);
2308 if (!p)
2309 return -ENOMEM;
2310
2311 cb->priv = p;
2312 cb->page_offset = 0;
2313 cb->reuse_flag = 0;
2314 cb->buf = page_address(p);
2315 cb->length = hns3_page_size(ring);
2316 cb->type = DESC_TYPE_PAGE;
2317
2318 return 0;
2319 }
2320
2321 static void hns3_free_buffer(struct hns3_enet_ring *ring,
2322 struct hns3_desc_cb *cb)
2323 {
2324 if (cb->type == DESC_TYPE_SKB)
2325 dev_kfree_skb_any((struct sk_buff *)cb->priv);
2326 else if (!HNAE3_IS_TX_RING(ring))
2327 put_page((struct page *)cb->priv);
2328 memset(cb, 0, sizeof(*cb));
2329 }
2330
2331 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
2332 {
2333 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
2334 cb->length, ring_to_dma_dir(ring));
2335
2336 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
2337 return -EIO;
2338
2339 return 0;
2340 }
2341
2342 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
2343 struct hns3_desc_cb *cb)
2344 {
2345 if (cb->type == DESC_TYPE_SKB || cb->type == DESC_TYPE_FRAGLIST_SKB)
2346 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
2347 ring_to_dma_dir(ring));
2348 else if (cb->length)
2349 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
2350 ring_to_dma_dir(ring));
2351 }
2352
2353 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
2354 {
2355 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2356 ring->desc[i].addr = 0;
2357 }
2358
2359 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
2360 {
2361 struct hns3_desc_cb *cb = &ring->desc_cb[i];
2362
2363 if (!ring->desc_cb[i].dma)
2364 return;
2365
2366 hns3_buffer_detach(ring, i);
2367 hns3_free_buffer(ring, cb);
2368 }
2369
2370 static void hns3_free_buffers(struct hns3_enet_ring *ring)
2371 {
2372 int i;
2373
2374 for (i = 0; i < ring->desc_num; i++)
2375 hns3_free_buffer_detach(ring, i);
2376 }
2377
2378 /* free desc along with its attached buffer */
2379 static void hns3_free_desc(struct hns3_enet_ring *ring)
2380 {
2381 int size = ring->desc_num * sizeof(ring->desc[0]);
2382
2383 hns3_free_buffers(ring);
2384
2385 if (ring->desc) {
2386 dma_free_coherent(ring_to_dev(ring), size,
2387 ring->desc, ring->desc_dma_addr);
2388 ring->desc = NULL;
2389 }
2390 }
2391
2392 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
2393 {
2394 int size = ring->desc_num * sizeof(ring->desc[0]);
2395
2396 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
2397 &ring->desc_dma_addr, GFP_KERNEL);
2398 if (!ring->desc)
2399 return -ENOMEM;
2400
2401 return 0;
2402 }
2403
2404 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring,
2405 struct hns3_desc_cb *cb)
2406 {
2407 int ret;
2408
2409 ret = hns3_alloc_buffer(ring, cb);
2410 if (ret)
2411 goto out;
2412
2413 ret = hns3_map_buffer(ring, cb);
2414 if (ret)
2415 goto out_with_buf;
2416
2417 return 0;
2418
2419 out_with_buf:
2420 hns3_free_buffer(ring, cb);
2421 out:
2422 return ret;
2423 }
2424
2425 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i)
2426 {
2427 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]);
2428
2429 if (ret)
2430 return ret;
2431
2432 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2433
2434 return 0;
2435 }
2436
2437 /* Allocate memory for raw pkg, and map with dma */
2438 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
2439 {
2440 int i, j, ret;
2441
2442 for (i = 0; i < ring->desc_num; i++) {
2443 ret = hns3_alloc_and_attach_buffer(ring, i);
2444 if (ret)
2445 goto out_buffer_fail;
2446 }
2447
2448 return 0;
2449
2450 out_buffer_fail:
2451 for (j = i - 1; j >= 0; j--)
2452 hns3_free_buffer_detach(ring, j);
2453 return ret;
2454 }
2455
2456 /* detach a in-used buffer and replace with a reserved one */
2457 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
2458 struct hns3_desc_cb *res_cb)
2459 {
2460 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2461 ring->desc_cb[i] = *res_cb;
2462 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2463 ring->desc[i].rx.bd_base_info = 0;
2464 }
2465
2466 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
2467 {
2468 ring->desc_cb[i].reuse_flag = 0;
2469 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
2470 ring->desc_cb[i].page_offset);
2471 ring->desc[i].rx.bd_base_info = 0;
2472
2473 dma_sync_single_for_device(ring_to_dev(ring),
2474 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset,
2475 hns3_buf_size(ring),
2476 DMA_FROM_DEVICE);
2477 }
2478
2479 static void hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, int head,
2480 int *bytes, int *pkts)
2481 {
2482 int ntc = ring->next_to_clean;
2483 struct hns3_desc_cb *desc_cb;
2484
2485 while (head != ntc) {
2486 desc_cb = &ring->desc_cb[ntc];
2487 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
2488 (*bytes) += desc_cb->length;
2489 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
2490 hns3_free_buffer_detach(ring, ntc);
2491
2492 if (++ntc == ring->desc_num)
2493 ntc = 0;
2494
2495 /* Issue prefetch for next Tx descriptor */
2496 prefetch(&ring->desc_cb[ntc]);
2497 }
2498
2499 /* This smp_store_release() pairs with smp_load_acquire() in
2500 * ring_space called by hns3_nic_net_xmit.
2501 */
2502 smp_store_release(&ring->next_to_clean, ntc);
2503 }
2504
2505 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
2506 {
2507 int u = ring->next_to_use;
2508 int c = ring->next_to_clean;
2509
2510 if (unlikely(h > ring->desc_num))
2511 return 0;
2512
2513 return u > c ? (h > c && h <= u) : (h > c || h <= u);
2514 }
2515
2516 void hns3_clean_tx_ring(struct hns3_enet_ring *ring)
2517 {
2518 struct net_device *netdev = ring_to_netdev(ring);
2519 struct hns3_nic_priv *priv = netdev_priv(netdev);
2520 struct netdev_queue *dev_queue;
2521 int bytes, pkts;
2522 int head;
2523
2524 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
2525
2526 if (is_ring_empty(ring) || head == ring->next_to_clean)
2527 return; /* no data to poll */
2528
2529 rmb(); /* Make sure head is ready before touch any data */
2530
2531 if (unlikely(!is_valid_clean_head(ring, head))) {
2532 hns3_rl_err(netdev, "wrong head (%d, %d-%d)\n", head,
2533 ring->next_to_use, ring->next_to_clean);
2534
2535 u64_stats_update_begin(&ring->syncp);
2536 ring->stats.io_err_cnt++;
2537 u64_stats_update_end(&ring->syncp);
2538 return;
2539 }
2540
2541 bytes = 0;
2542 pkts = 0;
2543 hns3_nic_reclaim_desc(ring, head, &bytes, &pkts);
2544
2545 ring->tqp_vector->tx_group.total_bytes += bytes;
2546 ring->tqp_vector->tx_group.total_packets += pkts;
2547
2548 u64_stats_update_begin(&ring->syncp);
2549 ring->stats.tx_bytes += bytes;
2550 ring->stats.tx_pkts += pkts;
2551 u64_stats_update_end(&ring->syncp);
2552
2553 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2554 netdev_tx_completed_queue(dev_queue, pkts, bytes);
2555
2556 if (unlikely(netif_carrier_ok(netdev) &&
2557 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
2558 /* Make sure that anybody stopping the queue after this
2559 * sees the new next_to_clean.
2560 */
2561 smp_mb();
2562 if (netif_tx_queue_stopped(dev_queue) &&
2563 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
2564 netif_tx_wake_queue(dev_queue);
2565 ring->stats.restart_queue++;
2566 }
2567 }
2568 }
2569
2570 static int hns3_desc_unused(struct hns3_enet_ring *ring)
2571 {
2572 int ntc = ring->next_to_clean;
2573 int ntu = ring->next_to_use;
2574
2575 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2576 }
2577
2578 static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
2579 int cleand_count)
2580 {
2581 struct hns3_desc_cb *desc_cb;
2582 struct hns3_desc_cb res_cbs;
2583 int i, ret;
2584
2585 for (i = 0; i < cleand_count; i++) {
2586 desc_cb = &ring->desc_cb[ring->next_to_use];
2587 if (desc_cb->reuse_flag) {
2588 u64_stats_update_begin(&ring->syncp);
2589 ring->stats.reuse_pg_cnt++;
2590 u64_stats_update_end(&ring->syncp);
2591
2592 hns3_reuse_buffer(ring, ring->next_to_use);
2593 } else {
2594 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
2595 if (ret) {
2596 u64_stats_update_begin(&ring->syncp);
2597 ring->stats.sw_err_cnt++;
2598 u64_stats_update_end(&ring->syncp);
2599
2600 hns3_rl_err(ring_to_netdev(ring),
2601 "alloc rx buffer failed: %d\n",
2602 ret);
2603 break;
2604 }
2605 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
2606
2607 u64_stats_update_begin(&ring->syncp);
2608 ring->stats.non_reuse_pg++;
2609 u64_stats_update_end(&ring->syncp);
2610 }
2611
2612 ring_ptr_move_fw(ring, next_to_use);
2613 }
2614
2615 wmb(); /* Make all data has been write before submit */
2616 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2617 }
2618
2619 static bool hns3_page_is_reusable(struct page *page)
2620 {
2621 return page_to_nid(page) == numa_mem_id() &&
2622 !page_is_pfmemalloc(page);
2623 }
2624
2625 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2626 struct hns3_enet_ring *ring, int pull_len,
2627 struct hns3_desc_cb *desc_cb)
2628 {
2629 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
2630 int size = le16_to_cpu(desc->rx.size);
2631 u32 truesize = hns3_buf_size(ring);
2632
2633 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
2634 size - pull_len, truesize);
2635
2636 /* Avoid re-using remote pages, or the stack is still using the page
2637 * when page_offset rollback to zero, flag default unreuse
2638 */
2639 if (unlikely(!hns3_page_is_reusable(desc_cb->priv)) ||
2640 (!desc_cb->page_offset && page_count(desc_cb->priv) > 1))
2641 return;
2642
2643 /* Move offset up to the next cache line */
2644 desc_cb->page_offset += truesize;
2645
2646 if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) {
2647 desc_cb->reuse_flag = 1;
2648 /* Bump ref count on page before it is given */
2649 get_page(desc_cb->priv);
2650 } else if (page_count(desc_cb->priv) == 1) {
2651 desc_cb->reuse_flag = 1;
2652 desc_cb->page_offset = 0;
2653 get_page(desc_cb->priv);
2654 }
2655 }
2656
2657 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
2658 {
2659 __be16 type = skb->protocol;
2660 struct tcphdr *th;
2661 int depth = 0;
2662
2663 while (eth_type_vlan(type)) {
2664 struct vlan_hdr *vh;
2665
2666 if ((depth + VLAN_HLEN) > skb_headlen(skb))
2667 return -EFAULT;
2668
2669 vh = (struct vlan_hdr *)(skb->data + depth);
2670 type = vh->h_vlan_encapsulated_proto;
2671 depth += VLAN_HLEN;
2672 }
2673
2674 skb_set_network_header(skb, depth);
2675
2676 if (type == htons(ETH_P_IP)) {
2677 const struct iphdr *iph = ip_hdr(skb);
2678
2679 depth += sizeof(struct iphdr);
2680 skb_set_transport_header(skb, depth);
2681 th = tcp_hdr(skb);
2682 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
2683 iph->daddr, 0);
2684 } else if (type == htons(ETH_P_IPV6)) {
2685 const struct ipv6hdr *iph = ipv6_hdr(skb);
2686
2687 depth += sizeof(struct ipv6hdr);
2688 skb_set_transport_header(skb, depth);
2689 th = tcp_hdr(skb);
2690 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
2691 &iph->daddr, 0);
2692 } else {
2693 hns3_rl_err(skb->dev,
2694 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
2695 be16_to_cpu(type), depth);
2696 return -EFAULT;
2697 }
2698
2699 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
2700 if (th->cwr)
2701 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
2702
2703 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
2704 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
2705
2706 skb->csum_start = (unsigned char *)th - skb->head;
2707 skb->csum_offset = offsetof(struct tcphdr, check);
2708 skb->ip_summed = CHECKSUM_PARTIAL;
2709
2710 trace_hns3_gro(skb);
2711
2712 return 0;
2713 }
2714
2715 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
2716 u32 l234info, u32 bd_base_info, u32 ol_info)
2717 {
2718 struct net_device *netdev = ring_to_netdev(ring);
2719 int l3_type, l4_type;
2720 int ol4_type;
2721
2722 skb->ip_summed = CHECKSUM_NONE;
2723
2724 skb_checksum_none_assert(skb);
2725
2726 if (!(netdev->features & NETIF_F_RXCSUM))
2727 return;
2728
2729 /* check if hardware has done checksum */
2730 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
2731 return;
2732
2733 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
2734 BIT(HNS3_RXD_OL3E_B) |
2735 BIT(HNS3_RXD_OL4E_B)))) {
2736 u64_stats_update_begin(&ring->syncp);
2737 ring->stats.l3l4_csum_err++;
2738 u64_stats_update_end(&ring->syncp);
2739
2740 return;
2741 }
2742
2743 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
2744 HNS3_RXD_OL4ID_S);
2745 switch (ol4_type) {
2746 case HNS3_OL4_TYPE_MAC_IN_UDP:
2747 case HNS3_OL4_TYPE_NVGRE:
2748 skb->csum_level = 1;
2749 fallthrough;
2750 case HNS3_OL4_TYPE_NO_TUN:
2751 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2752 HNS3_RXD_L3ID_S);
2753 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2754 HNS3_RXD_L4ID_S);
2755
2756 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
2757 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2758 l3_type == HNS3_L3_TYPE_IPV6) &&
2759 (l4_type == HNS3_L4_TYPE_UDP ||
2760 l4_type == HNS3_L4_TYPE_TCP ||
2761 l4_type == HNS3_L4_TYPE_SCTP))
2762 skb->ip_summed = CHECKSUM_UNNECESSARY;
2763 break;
2764 default:
2765 break;
2766 }
2767 }
2768
2769 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2770 {
2771 if (skb_has_frag_list(skb))
2772 napi_gro_flush(&ring->tqp_vector->napi, false);
2773
2774 napi_gro_receive(&ring->tqp_vector->napi, skb);
2775 }
2776
2777 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2778 struct hns3_desc *desc, u32 l234info,
2779 u16 *vlan_tag)
2780 {
2781 struct hnae3_handle *handle = ring->tqp->handle;
2782 struct pci_dev *pdev = ring->tqp->handle->pdev;
2783
2784 if (pdev->revision == 0x20) {
2785 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2786 if (!(*vlan_tag & VLAN_VID_MASK))
2787 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2788
2789 return (*vlan_tag != 0);
2790 }
2791
2792 #define HNS3_STRP_OUTER_VLAN 0x1
2793 #define HNS3_STRP_INNER_VLAN 0x2
2794 #define HNS3_STRP_BOTH 0x3
2795
2796 /* Hardware always insert VLAN tag into RX descriptor when
2797 * remove the tag from packet, driver needs to determine
2798 * reporting which tag to stack.
2799 */
2800 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2801 HNS3_RXD_STRP_TAGP_S)) {
2802 case HNS3_STRP_OUTER_VLAN:
2803 if (handle->port_base_vlan_state !=
2804 HNAE3_PORT_BASE_VLAN_DISABLE)
2805 return false;
2806
2807 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2808 return true;
2809 case HNS3_STRP_INNER_VLAN:
2810 if (handle->port_base_vlan_state !=
2811 HNAE3_PORT_BASE_VLAN_DISABLE)
2812 return false;
2813
2814 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2815 return true;
2816 case HNS3_STRP_BOTH:
2817 if (handle->port_base_vlan_state ==
2818 HNAE3_PORT_BASE_VLAN_DISABLE)
2819 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2820 else
2821 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2822
2823 return true;
2824 default:
2825 return false;
2826 }
2827 }
2828
2829 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
2830 unsigned char *va)
2831 {
2832 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2833 struct net_device *netdev = ring_to_netdev(ring);
2834 struct sk_buff *skb;
2835
2836 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
2837 skb = ring->skb;
2838 if (unlikely(!skb)) {
2839 hns3_rl_err(netdev, "alloc rx skb fail\n");
2840
2841 u64_stats_update_begin(&ring->syncp);
2842 ring->stats.sw_err_cnt++;
2843 u64_stats_update_end(&ring->syncp);
2844
2845 return -ENOMEM;
2846 }
2847
2848 trace_hns3_rx_desc(ring);
2849 prefetchw(skb->data);
2850
2851 ring->pending_buf = 1;
2852 ring->frag_num = 0;
2853 ring->tail_skb = NULL;
2854 if (length <= HNS3_RX_HEAD_SIZE) {
2855 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2856
2857 /* We can reuse buffer as-is, just make sure it is local */
2858 if (likely(hns3_page_is_reusable(desc_cb->priv)))
2859 desc_cb->reuse_flag = 1;
2860 else /* This page cannot be reused so discard it */
2861 put_page(desc_cb->priv);
2862
2863 ring_ptr_move_fw(ring, next_to_clean);
2864 return 0;
2865 }
2866 u64_stats_update_begin(&ring->syncp);
2867 ring->stats.seg_pkt_cnt++;
2868 u64_stats_update_end(&ring->syncp);
2869
2870 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
2871 __skb_put(skb, ring->pull_len);
2872 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
2873 desc_cb);
2874 ring_ptr_move_fw(ring, next_to_clean);
2875
2876 return 0;
2877 }
2878
2879 static int hns3_add_frag(struct hns3_enet_ring *ring)
2880 {
2881 struct sk_buff *skb = ring->skb;
2882 struct sk_buff *head_skb = skb;
2883 struct sk_buff *new_skb;
2884 struct hns3_desc_cb *desc_cb;
2885 struct hns3_desc *desc;
2886 u32 bd_base_info;
2887
2888 do {
2889 desc = &ring->desc[ring->next_to_clean];
2890 desc_cb = &ring->desc_cb[ring->next_to_clean];
2891 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2892 /* make sure HW write desc complete */
2893 dma_rmb();
2894 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
2895 return -ENXIO;
2896
2897 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
2898 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
2899 if (unlikely(!new_skb)) {
2900 hns3_rl_err(ring_to_netdev(ring),
2901 "alloc rx fraglist skb fail\n");
2902 return -ENXIO;
2903 }
2904 ring->frag_num = 0;
2905
2906 if (ring->tail_skb) {
2907 ring->tail_skb->next = new_skb;
2908 ring->tail_skb = new_skb;
2909 } else {
2910 skb_shinfo(skb)->frag_list = new_skb;
2911 ring->tail_skb = new_skb;
2912 }
2913 }
2914
2915 if (ring->tail_skb) {
2916 head_skb->truesize += hns3_buf_size(ring);
2917 head_skb->data_len += le16_to_cpu(desc->rx.size);
2918 head_skb->len += le16_to_cpu(desc->rx.size);
2919 skb = ring->tail_skb;
2920 }
2921
2922 dma_sync_single_for_cpu(ring_to_dev(ring),
2923 desc_cb->dma + desc_cb->page_offset,
2924 hns3_buf_size(ring),
2925 DMA_FROM_DEVICE);
2926
2927 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
2928 trace_hns3_rx_desc(ring);
2929 ring_ptr_move_fw(ring, next_to_clean);
2930 ring->pending_buf++;
2931 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
2932
2933 return 0;
2934 }
2935
2936 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
2937 struct sk_buff *skb, u32 l234info,
2938 u32 bd_base_info, u32 ol_info)
2939 {
2940 u32 l3_type;
2941
2942 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
2943 HNS3_RXD_GRO_SIZE_M,
2944 HNS3_RXD_GRO_SIZE_S);
2945 /* if there is no HW GRO, do not set gro params */
2946 if (!skb_shinfo(skb)->gso_size) {
2947 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info);
2948 return 0;
2949 }
2950
2951 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
2952 HNS3_RXD_GRO_COUNT_M,
2953 HNS3_RXD_GRO_COUNT_S);
2954
2955 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
2956 if (l3_type == HNS3_L3_TYPE_IPV4)
2957 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
2958 else if (l3_type == HNS3_L3_TYPE_IPV6)
2959 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
2960 else
2961 return -EFAULT;
2962
2963 return hns3_gro_complete(skb, l234info);
2964 }
2965
2966 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
2967 struct sk_buff *skb, u32 rss_hash)
2968 {
2969 struct hnae3_handle *handle = ring->tqp->handle;
2970 enum pkt_hash_types rss_type;
2971
2972 if (rss_hash)
2973 rss_type = handle->kinfo.rss_type;
2974 else
2975 rss_type = PKT_HASH_TYPE_NONE;
2976
2977 skb_set_hash(skb, rss_hash, rss_type);
2978 }
2979
2980 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
2981 {
2982 struct net_device *netdev = ring_to_netdev(ring);
2983 enum hns3_pkt_l2t_type l2_frame_type;
2984 u32 bd_base_info, l234info, ol_info;
2985 struct hns3_desc *desc;
2986 unsigned int len;
2987 int pre_ntc, ret;
2988
2989 /* bdinfo handled below is only valid on the last BD of the
2990 * current packet, and ring->next_to_clean indicates the first
2991 * descriptor of next packet, so need - 1 below.
2992 */
2993 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
2994 (ring->desc_num - 1);
2995 desc = &ring->desc[pre_ntc];
2996 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2997 l234info = le32_to_cpu(desc->rx.l234_info);
2998 ol_info = le32_to_cpu(desc->rx.ol_info);
2999
3000 /* Based on hw strategy, the tag offloaded will be stored at
3001 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
3002 * in one layer tag case.
3003 */
3004 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
3005 u16 vlan_tag;
3006
3007 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
3008 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
3009 vlan_tag);
3010 }
3011
3012 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
3013 BIT(HNS3_RXD_L2E_B))))) {
3014 u64_stats_update_begin(&ring->syncp);
3015 if (l234info & BIT(HNS3_RXD_L2E_B))
3016 ring->stats.l2_err++;
3017 else
3018 ring->stats.err_pkt_len++;
3019 u64_stats_update_end(&ring->syncp);
3020
3021 return -EFAULT;
3022 }
3023
3024 len = skb->len;
3025
3026 /* Do update ip stack process */
3027 skb->protocol = eth_type_trans(skb, netdev);
3028
3029 /* This is needed in order to enable forwarding support */
3030 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
3031 bd_base_info, ol_info);
3032 if (unlikely(ret)) {
3033 u64_stats_update_begin(&ring->syncp);
3034 ring->stats.rx_err_cnt++;
3035 u64_stats_update_end(&ring->syncp);
3036 return ret;
3037 }
3038
3039 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
3040 HNS3_RXD_DMAC_S);
3041
3042 u64_stats_update_begin(&ring->syncp);
3043 ring->stats.rx_pkts++;
3044 ring->stats.rx_bytes += len;
3045
3046 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
3047 ring->stats.rx_multicast++;
3048
3049 u64_stats_update_end(&ring->syncp);
3050
3051 ring->tqp_vector->rx_group.total_bytes += len;
3052
3053 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash));
3054 return 0;
3055 }
3056
3057 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
3058 {
3059 struct sk_buff *skb = ring->skb;
3060 struct hns3_desc_cb *desc_cb;
3061 struct hns3_desc *desc;
3062 unsigned int length;
3063 u32 bd_base_info;
3064 int ret;
3065
3066 desc = &ring->desc[ring->next_to_clean];
3067 desc_cb = &ring->desc_cb[ring->next_to_clean];
3068
3069 prefetch(desc);
3070
3071 length = le16_to_cpu(desc->rx.size);
3072 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
3073
3074 /* Check valid BD */
3075 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
3076 return -ENXIO;
3077
3078 if (!skb) {
3079 ring->va = desc_cb->buf + desc_cb->page_offset;
3080
3081 dma_sync_single_for_cpu(ring_to_dev(ring),
3082 desc_cb->dma + desc_cb->page_offset,
3083 hns3_buf_size(ring),
3084 DMA_FROM_DEVICE);
3085 }
3086
3087 /* Prefetch first cache line of first page
3088 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
3089 * line size is 64B so need to prefetch twice to make it 128B. But in
3090 * actual we can have greater size of caches with 128B Level 1 cache
3091 * lines. In such a case, single fetch would suffice to cache in the
3092 * relevant part of the header.
3093 */
3094 prefetch(ring->va);
3095 #if L1_CACHE_BYTES < 128
3096 prefetch(ring->va + L1_CACHE_BYTES);
3097 #endif
3098
3099 if (!skb) {
3100 ret = hns3_alloc_skb(ring, length, ring->va);
3101 skb = ring->skb;
3102
3103 if (ret < 0) /* alloc buffer fail */
3104 return ret;
3105 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
3106 ret = hns3_add_frag(ring);
3107 if (ret)
3108 return ret;
3109 }
3110 } else {
3111 ret = hns3_add_frag(ring);
3112 if (ret)
3113 return ret;
3114 }
3115
3116 /* As the head data may be changed when GRO enable, copy
3117 * the head data in after other data rx completed
3118 */
3119 if (skb->len > HNS3_RX_HEAD_SIZE)
3120 memcpy(skb->data, ring->va,
3121 ALIGN(ring->pull_len, sizeof(long)));
3122
3123 ret = hns3_handle_bdinfo(ring, skb);
3124 if (unlikely(ret)) {
3125 dev_kfree_skb_any(skb);
3126 return ret;
3127 }
3128
3129 skb_record_rx_queue(skb, ring->tqp->tqp_index);
3130 return 0;
3131 }
3132
3133 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
3134 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
3135 {
3136 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
3137 int unused_count = hns3_desc_unused(ring);
3138 int recv_pkts = 0;
3139 int recv_bds = 0;
3140 int err, num;
3141
3142 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
3143 num -= unused_count;
3144 unused_count -= ring->pending_buf;
3145
3146 if (num <= 0)
3147 goto out;
3148
3149 rmb(); /* Make sure num taken effect before the other data is touched */
3150
3151 while (recv_pkts < budget && recv_bds < num) {
3152 /* Reuse or realloc buffers */
3153 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
3154 hns3_nic_alloc_rx_buffers(ring, unused_count);
3155 unused_count = hns3_desc_unused(ring) -
3156 ring->pending_buf;
3157 }
3158
3159 /* Poll one pkt */
3160 err = hns3_handle_rx_bd(ring);
3161 /* Do not get FE for the packet or failed to alloc skb */
3162 if (unlikely(!ring->skb || err == -ENXIO)) {
3163 goto out;
3164 } else if (likely(!err)) {
3165 rx_fn(ring, ring->skb);
3166 recv_pkts++;
3167 }
3168
3169 recv_bds += ring->pending_buf;
3170 unused_count += ring->pending_buf;
3171 ring->skb = NULL;
3172 ring->pending_buf = 0;
3173 }
3174
3175 out:
3176 /* Make all data has been write before submit */
3177 if (unused_count > 0)
3178 hns3_nic_alloc_rx_buffers(ring, unused_count);
3179
3180 return recv_pkts;
3181 }
3182
3183 static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group)
3184 {
3185 #define HNS3_RX_LOW_BYTE_RATE 10000
3186 #define HNS3_RX_MID_BYTE_RATE 20000
3187 #define HNS3_RX_ULTRA_PACKET_RATE 40
3188
3189 enum hns3_flow_level_range new_flow_level;
3190 struct hns3_enet_tqp_vector *tqp_vector;
3191 int packets_per_msecs, bytes_per_msecs;
3192 u32 time_passed_ms;
3193
3194 tqp_vector = ring_group->ring->tqp_vector;
3195 time_passed_ms =
3196 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
3197 if (!time_passed_ms)
3198 return false;
3199
3200 do_div(ring_group->total_packets, time_passed_ms);
3201 packets_per_msecs = ring_group->total_packets;
3202
3203 do_div(ring_group->total_bytes, time_passed_ms);
3204 bytes_per_msecs = ring_group->total_bytes;
3205
3206 new_flow_level = ring_group->coal.flow_level;
3207
3208 /* Simple throttlerate management
3209 * 0-10MB/s lower (50000 ints/s)
3210 * 10-20MB/s middle (20000 ints/s)
3211 * 20-1249MB/s high (18000 ints/s)
3212 * > 40000pps ultra (8000 ints/s)
3213 */
3214 switch (new_flow_level) {
3215 case HNS3_FLOW_LOW:
3216 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
3217 new_flow_level = HNS3_FLOW_MID;
3218 break;
3219 case HNS3_FLOW_MID:
3220 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
3221 new_flow_level = HNS3_FLOW_HIGH;
3222 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
3223 new_flow_level = HNS3_FLOW_LOW;
3224 break;
3225 case HNS3_FLOW_HIGH:
3226 case HNS3_FLOW_ULTRA:
3227 default:
3228 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
3229 new_flow_level = HNS3_FLOW_MID;
3230 break;
3231 }
3232
3233 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
3234 &tqp_vector->rx_group == ring_group)
3235 new_flow_level = HNS3_FLOW_ULTRA;
3236
3237 ring_group->total_bytes = 0;
3238 ring_group->total_packets = 0;
3239 ring_group->coal.flow_level = new_flow_level;
3240
3241 return true;
3242 }
3243
3244 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
3245 {
3246 struct hns3_enet_tqp_vector *tqp_vector;
3247 u16 new_int_gl;
3248
3249 if (!ring_group->ring)
3250 return false;
3251
3252 tqp_vector = ring_group->ring->tqp_vector;
3253 if (!tqp_vector->last_jiffies)
3254 return false;
3255
3256 if (ring_group->total_packets == 0) {
3257 ring_group->coal.int_gl = HNS3_INT_GL_50K;
3258 ring_group->coal.flow_level = HNS3_FLOW_LOW;
3259 return true;
3260 }
3261
3262 if (!hns3_get_new_flow_lvl(ring_group))
3263 return false;
3264
3265 new_int_gl = ring_group->coal.int_gl;
3266 switch (ring_group->coal.flow_level) {
3267 case HNS3_FLOW_LOW:
3268 new_int_gl = HNS3_INT_GL_50K;
3269 break;
3270 case HNS3_FLOW_MID:
3271 new_int_gl = HNS3_INT_GL_20K;
3272 break;
3273 case HNS3_FLOW_HIGH:
3274 new_int_gl = HNS3_INT_GL_18K;
3275 break;
3276 case HNS3_FLOW_ULTRA:
3277 new_int_gl = HNS3_INT_GL_8K;
3278 break;
3279 default:
3280 break;
3281 }
3282
3283 if (new_int_gl != ring_group->coal.int_gl) {
3284 ring_group->coal.int_gl = new_int_gl;
3285 return true;
3286 }
3287 return false;
3288 }
3289
3290 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
3291 {
3292 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
3293 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
3294 bool rx_update, tx_update;
3295
3296 /* update param every 1000ms */
3297 if (time_before(jiffies,
3298 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
3299 return;
3300
3301 if (rx_group->coal.gl_adapt_enable) {
3302 rx_update = hns3_get_new_int_gl(rx_group);
3303 if (rx_update)
3304 hns3_set_vector_coalesce_rx_gl(tqp_vector,
3305 rx_group->coal.int_gl);
3306 }
3307
3308 if (tx_group->coal.gl_adapt_enable) {
3309 tx_update = hns3_get_new_int_gl(tx_group);
3310 if (tx_update)
3311 hns3_set_vector_coalesce_tx_gl(tqp_vector,
3312 tx_group->coal.int_gl);
3313 }
3314
3315 tqp_vector->last_jiffies = jiffies;
3316 }
3317
3318 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
3319 {
3320 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
3321 struct hns3_enet_ring *ring;
3322 int rx_pkt_total = 0;
3323
3324 struct hns3_enet_tqp_vector *tqp_vector =
3325 container_of(napi, struct hns3_enet_tqp_vector, napi);
3326 bool clean_complete = true;
3327 int rx_budget = budget;
3328
3329 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
3330 napi_complete(napi);
3331 return 0;
3332 }
3333
3334 /* Since the actual Tx work is minimal, we can give the Tx a larger
3335 * budget and be more aggressive about cleaning up the Tx descriptors.
3336 */
3337 hns3_for_each_ring(ring, tqp_vector->tx_group)
3338 hns3_clean_tx_ring(ring);
3339
3340 /* make sure rx ring budget not smaller than 1 */
3341 if (tqp_vector->num_tqps > 1)
3342 rx_budget = max(budget / tqp_vector->num_tqps, 1);
3343
3344 hns3_for_each_ring(ring, tqp_vector->rx_group) {
3345 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
3346 hns3_rx_skb);
3347
3348 if (rx_cleaned >= rx_budget)
3349 clean_complete = false;
3350
3351 rx_pkt_total += rx_cleaned;
3352 }
3353
3354 tqp_vector->rx_group.total_packets += rx_pkt_total;
3355
3356 if (!clean_complete)
3357 return budget;
3358
3359 if (napi_complete(napi) &&
3360 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
3361 hns3_update_new_int_gl(tqp_vector);
3362 hns3_mask_vector_irq(tqp_vector, 1);
3363 }
3364
3365 return rx_pkt_total;
3366 }
3367
3368 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3369 struct hnae3_ring_chain_node *head)
3370 {
3371 struct pci_dev *pdev = tqp_vector->handle->pdev;
3372 struct hnae3_ring_chain_node *cur_chain = head;
3373 struct hnae3_ring_chain_node *chain;
3374 struct hns3_enet_ring *tx_ring;
3375 struct hns3_enet_ring *rx_ring;
3376
3377 tx_ring = tqp_vector->tx_group.ring;
3378 if (tx_ring) {
3379 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
3380 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3381 HNAE3_RING_TYPE_TX);
3382 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3383 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
3384
3385 cur_chain->next = NULL;
3386
3387 while (tx_ring->next) {
3388 tx_ring = tx_ring->next;
3389
3390 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
3391 GFP_KERNEL);
3392 if (!chain)
3393 goto err_free_chain;
3394
3395 cur_chain->next = chain;
3396 chain->tqp_index = tx_ring->tqp->tqp_index;
3397 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3398 HNAE3_RING_TYPE_TX);
3399 hnae3_set_field(chain->int_gl_idx,
3400 HNAE3_RING_GL_IDX_M,
3401 HNAE3_RING_GL_IDX_S,
3402 HNAE3_RING_GL_TX);
3403
3404 cur_chain = chain;
3405 }
3406 }
3407
3408 rx_ring = tqp_vector->rx_group.ring;
3409 if (!tx_ring && rx_ring) {
3410 cur_chain->next = NULL;
3411 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
3412 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3413 HNAE3_RING_TYPE_RX);
3414 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3415 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
3416
3417 rx_ring = rx_ring->next;
3418 }
3419
3420 while (rx_ring) {
3421 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
3422 if (!chain)
3423 goto err_free_chain;
3424
3425 cur_chain->next = chain;
3426 chain->tqp_index = rx_ring->tqp->tqp_index;
3427 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3428 HNAE3_RING_TYPE_RX);
3429 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3430 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
3431
3432 cur_chain = chain;
3433
3434 rx_ring = rx_ring->next;
3435 }
3436
3437 return 0;
3438
3439 err_free_chain:
3440 cur_chain = head->next;
3441 while (cur_chain) {
3442 chain = cur_chain->next;
3443 devm_kfree(&pdev->dev, cur_chain);
3444 cur_chain = chain;
3445 }
3446 head->next = NULL;
3447
3448 return -ENOMEM;
3449 }
3450
3451 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3452 struct hnae3_ring_chain_node *head)
3453 {
3454 struct pci_dev *pdev = tqp_vector->handle->pdev;
3455 struct hnae3_ring_chain_node *chain_tmp, *chain;
3456
3457 chain = head->next;
3458
3459 while (chain) {
3460 chain_tmp = chain->next;
3461 devm_kfree(&pdev->dev, chain);
3462 chain = chain_tmp;
3463 }
3464 }
3465
3466 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
3467 struct hns3_enet_ring *ring)
3468 {
3469 ring->next = group->ring;
3470 group->ring = ring;
3471
3472 group->count++;
3473 }
3474
3475 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
3476 {
3477 struct pci_dev *pdev = priv->ae_handle->pdev;
3478 struct hns3_enet_tqp_vector *tqp_vector;
3479 int num_vectors = priv->vector_num;
3480 int numa_node;
3481 int vector_i;
3482
3483 numa_node = dev_to_node(&pdev->dev);
3484
3485 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
3486 tqp_vector = &priv->tqp_vector[vector_i];
3487 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
3488 &tqp_vector->affinity_mask);
3489 }
3490 }
3491
3492 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
3493 {
3494 struct hnae3_ring_chain_node vector_ring_chain;
3495 struct hnae3_handle *h = priv->ae_handle;
3496 struct hns3_enet_tqp_vector *tqp_vector;
3497 int ret = 0;
3498 int i;
3499
3500 hns3_nic_set_cpumask(priv);
3501
3502 for (i = 0; i < priv->vector_num; i++) {
3503 tqp_vector = &priv->tqp_vector[i];
3504 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
3505 tqp_vector->num_tqps = 0;
3506 }
3507
3508 for (i = 0; i < h->kinfo.num_tqps; i++) {
3509 u16 vector_i = i % priv->vector_num;
3510 u16 tqp_num = h->kinfo.num_tqps;
3511
3512 tqp_vector = &priv->tqp_vector[vector_i];
3513
3514 hns3_add_ring_to_group(&tqp_vector->tx_group,
3515 &priv->ring[i]);
3516
3517 hns3_add_ring_to_group(&tqp_vector->rx_group,
3518 &priv->ring[i + tqp_num]);
3519
3520 priv->ring[i].tqp_vector = tqp_vector;
3521 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
3522 tqp_vector->num_tqps++;
3523 }
3524
3525 for (i = 0; i < priv->vector_num; i++) {
3526 tqp_vector = &priv->tqp_vector[i];
3527
3528 tqp_vector->rx_group.total_bytes = 0;
3529 tqp_vector->rx_group.total_packets = 0;
3530 tqp_vector->tx_group.total_bytes = 0;
3531 tqp_vector->tx_group.total_packets = 0;
3532 tqp_vector->handle = h;
3533
3534 ret = hns3_get_vector_ring_chain(tqp_vector,
3535 &vector_ring_chain);
3536 if (ret)
3537 goto map_ring_fail;
3538
3539 ret = h->ae_algo->ops->map_ring_to_vector(h,
3540 tqp_vector->vector_irq, &vector_ring_chain);
3541
3542 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3543
3544 if (ret)
3545 goto map_ring_fail;
3546
3547 netif_napi_add(priv->netdev, &tqp_vector->napi,
3548 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
3549 }
3550
3551 return 0;
3552
3553 map_ring_fail:
3554 while (i--)
3555 netif_napi_del(&priv->tqp_vector[i].napi);
3556
3557 return ret;
3558 }
3559
3560 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
3561 {
3562 #define HNS3_VECTOR_PF_MAX_NUM 64
3563
3564 struct hnae3_handle *h = priv->ae_handle;
3565 struct hns3_enet_tqp_vector *tqp_vector;
3566 struct hnae3_vector_info *vector;
3567 struct pci_dev *pdev = h->pdev;
3568 u16 tqp_num = h->kinfo.num_tqps;
3569 u16 vector_num;
3570 int ret = 0;
3571 u16 i;
3572
3573 /* RSS size, cpu online and vector_num should be the same */
3574 /* Should consider 2p/4p later */
3575 vector_num = min_t(u16, num_online_cpus(), tqp_num);
3576 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
3577
3578 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
3579 GFP_KERNEL);
3580 if (!vector)
3581 return -ENOMEM;
3582
3583 /* save the actual available vector number */
3584 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
3585
3586 priv->vector_num = vector_num;
3587 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
3588 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
3589 GFP_KERNEL);
3590 if (!priv->tqp_vector) {
3591 ret = -ENOMEM;
3592 goto out;
3593 }
3594
3595 for (i = 0; i < priv->vector_num; i++) {
3596 tqp_vector = &priv->tqp_vector[i];
3597 tqp_vector->idx = i;
3598 tqp_vector->mask_addr = vector[i].io_addr;
3599 tqp_vector->vector_irq = vector[i].vector;
3600 hns3_vector_gl_rl_init(tqp_vector, priv);
3601 }
3602
3603 out:
3604 devm_kfree(&pdev->dev, vector);
3605 return ret;
3606 }
3607
3608 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
3609 {
3610 group->ring = NULL;
3611 group->count = 0;
3612 }
3613
3614 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
3615 {
3616 struct hnae3_ring_chain_node vector_ring_chain;
3617 struct hnae3_handle *h = priv->ae_handle;
3618 struct hns3_enet_tqp_vector *tqp_vector;
3619 int i;
3620
3621 for (i = 0; i < priv->vector_num; i++) {
3622 tqp_vector = &priv->tqp_vector[i];
3623
3624 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
3625 continue;
3626
3627 /* Since the mapping can be overwritten, when fail to get the
3628 * chain between vector and ring, we should go on to deal with
3629 * the remaining options.
3630 */
3631 if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain))
3632 dev_warn(priv->dev, "failed to get ring chain\n");
3633
3634 h->ae_algo->ops->unmap_ring_from_vector(h,
3635 tqp_vector->vector_irq, &vector_ring_chain);
3636
3637 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3638
3639 hns3_clear_ring_group(&tqp_vector->rx_group);
3640 hns3_clear_ring_group(&tqp_vector->tx_group);
3641 netif_napi_del(&priv->tqp_vector[i].napi);
3642 }
3643 }
3644
3645 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
3646 {
3647 struct hnae3_handle *h = priv->ae_handle;
3648 struct pci_dev *pdev = h->pdev;
3649 int i, ret;
3650
3651 for (i = 0; i < priv->vector_num; i++) {
3652 struct hns3_enet_tqp_vector *tqp_vector;
3653
3654 tqp_vector = &priv->tqp_vector[i];
3655 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
3656 if (ret)
3657 return;
3658 }
3659
3660 devm_kfree(&pdev->dev, priv->tqp_vector);
3661 }
3662
3663 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
3664 unsigned int ring_type)
3665 {
3666 int queue_num = priv->ae_handle->kinfo.num_tqps;
3667 struct hns3_enet_ring *ring;
3668 int desc_num;
3669
3670 if (ring_type == HNAE3_RING_TYPE_TX) {
3671 ring = &priv->ring[q->tqp_index];
3672 desc_num = priv->ae_handle->kinfo.num_tx_desc;
3673 ring->queue_index = q->tqp_index;
3674 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
3675 } else {
3676 ring = &priv->ring[q->tqp_index + queue_num];
3677 desc_num = priv->ae_handle->kinfo.num_rx_desc;
3678 ring->queue_index = q->tqp_index;
3679 ring->io_base = q->io_base;
3680 }
3681
3682 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
3683
3684 ring->tqp = q;
3685 ring->desc = NULL;
3686 ring->desc_cb = NULL;
3687 ring->dev = priv->dev;
3688 ring->desc_dma_addr = 0;
3689 ring->buf_size = q->buf_size;
3690 ring->desc_num = desc_num;
3691 ring->next_to_use = 0;
3692 ring->next_to_clean = 0;
3693 }
3694
3695 static void hns3_queue_to_ring(struct hnae3_queue *tqp,
3696 struct hns3_nic_priv *priv)
3697 {
3698 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
3699 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
3700 }
3701
3702 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
3703 {
3704 struct hnae3_handle *h = priv->ae_handle;
3705 struct pci_dev *pdev = h->pdev;
3706 int i;
3707
3708 priv->ring = devm_kzalloc(&pdev->dev,
3709 array3_size(h->kinfo.num_tqps,
3710 sizeof(*priv->ring), 2),
3711 GFP_KERNEL);
3712 if (!priv->ring)
3713 return -ENOMEM;
3714
3715 for (i = 0; i < h->kinfo.num_tqps; i++)
3716 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
3717
3718 return 0;
3719 }
3720
3721 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
3722 {
3723 if (!priv->ring)
3724 return;
3725
3726 devm_kfree(priv->dev, priv->ring);
3727 priv->ring = NULL;
3728 }
3729
3730 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
3731 {
3732 int ret;
3733
3734 if (ring->desc_num <= 0 || ring->buf_size <= 0)
3735 return -EINVAL;
3736
3737 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
3738 sizeof(ring->desc_cb[0]), GFP_KERNEL);
3739 if (!ring->desc_cb) {
3740 ret = -ENOMEM;
3741 goto out;
3742 }
3743
3744 ret = hns3_alloc_desc(ring);
3745 if (ret)
3746 goto out_with_desc_cb;
3747
3748 if (!HNAE3_IS_TX_RING(ring)) {
3749 ret = hns3_alloc_ring_buffers(ring);
3750 if (ret)
3751 goto out_with_desc;
3752 }
3753
3754 return 0;
3755
3756 out_with_desc:
3757 hns3_free_desc(ring);
3758 out_with_desc_cb:
3759 devm_kfree(ring_to_dev(ring), ring->desc_cb);
3760 ring->desc_cb = NULL;
3761 out:
3762 return ret;
3763 }
3764
3765 void hns3_fini_ring(struct hns3_enet_ring *ring)
3766 {
3767 hns3_free_desc(ring);
3768 devm_kfree(ring_to_dev(ring), ring->desc_cb);
3769 ring->desc_cb = NULL;
3770 ring->next_to_clean = 0;
3771 ring->next_to_use = 0;
3772 ring->pending_buf = 0;
3773 if (ring->skb) {
3774 dev_kfree_skb_any(ring->skb);
3775 ring->skb = NULL;
3776 }
3777 }
3778
3779 static int hns3_buf_size2type(u32 buf_size)
3780 {
3781 int bd_size_type;
3782
3783 switch (buf_size) {
3784 case 512:
3785 bd_size_type = HNS3_BD_SIZE_512_TYPE;
3786 break;
3787 case 1024:
3788 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3789 break;
3790 case 2048:
3791 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3792 break;
3793 case 4096:
3794 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3795 break;
3796 default:
3797 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3798 }
3799
3800 return bd_size_type;
3801 }
3802
3803 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3804 {
3805 dma_addr_t dma = ring->desc_dma_addr;
3806 struct hnae3_queue *q = ring->tqp;
3807
3808 if (!HNAE3_IS_TX_RING(ring)) {
3809 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
3810 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3811 (u32)((dma >> 31) >> 1));
3812
3813 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3814 hns3_buf_size2type(ring->buf_size));
3815 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3816 ring->desc_num / 8 - 1);
3817
3818 } else {
3819 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3820 (u32)dma);
3821 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3822 (u32)((dma >> 31) >> 1));
3823
3824 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3825 ring->desc_num / 8 - 1);
3826 }
3827 }
3828
3829 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3830 {
3831 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3832 int i;
3833
3834 for (i = 0; i < HNAE3_MAX_TC; i++) {
3835 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3836 int j;
3837
3838 if (!tc_info->enable)
3839 continue;
3840
3841 for (j = 0; j < tc_info->tqp_count; j++) {
3842 struct hnae3_queue *q;
3843
3844 q = priv->ring[tc_info->tqp_offset + j].tqp;
3845 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3846 tc_info->tc);
3847 }
3848 }
3849 }
3850
3851 int hns3_init_all_ring(struct hns3_nic_priv *priv)
3852 {
3853 struct hnae3_handle *h = priv->ae_handle;
3854 int ring_num = h->kinfo.num_tqps * 2;
3855 int i, j;
3856 int ret;
3857
3858 for (i = 0; i < ring_num; i++) {
3859 ret = hns3_alloc_ring_memory(&priv->ring[i]);
3860 if (ret) {
3861 dev_err(priv->dev,
3862 "Alloc ring memory fail! ret=%d\n", ret);
3863 goto out_when_alloc_ring_memory;
3864 }
3865
3866 u64_stats_init(&priv->ring[i].syncp);
3867 }
3868
3869 return 0;
3870
3871 out_when_alloc_ring_memory:
3872 for (j = i - 1; j >= 0; j--)
3873 hns3_fini_ring(&priv->ring[j]);
3874
3875 return -ENOMEM;
3876 }
3877
3878 int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
3879 {
3880 struct hnae3_handle *h = priv->ae_handle;
3881 int i;
3882
3883 for (i = 0; i < h->kinfo.num_tqps; i++) {
3884 hns3_fini_ring(&priv->ring[i]);
3885 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
3886 }
3887 return 0;
3888 }
3889
3890 /* Set mac addr if it is configured. or leave it to the AE driver */
3891 static int hns3_init_mac_addr(struct net_device *netdev)
3892 {
3893 struct hns3_nic_priv *priv = netdev_priv(netdev);
3894 struct hnae3_handle *h = priv->ae_handle;
3895 u8 mac_addr_temp[ETH_ALEN];
3896 int ret = 0;
3897
3898 if (h->ae_algo->ops->get_mac_addr)
3899 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
3900
3901 /* Check if the MAC address is valid, if not get a random one */
3902 if (!is_valid_ether_addr(mac_addr_temp)) {
3903 eth_hw_addr_random(netdev);
3904 dev_warn(priv->dev, "using random MAC address %pM\n",
3905 netdev->dev_addr);
3906 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) {
3907 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3908 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
3909 } else {
3910 return 0;
3911 }
3912
3913 if (h->ae_algo->ops->set_mac_addr)
3914 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
3915
3916 return ret;
3917 }
3918
3919 static int hns3_init_phy(struct net_device *netdev)
3920 {
3921 struct hnae3_handle *h = hns3_get_handle(netdev);
3922 int ret = 0;
3923
3924 if (h->ae_algo->ops->mac_connect_phy)
3925 ret = h->ae_algo->ops->mac_connect_phy(h);
3926
3927 return ret;
3928 }
3929
3930 static void hns3_uninit_phy(struct net_device *netdev)
3931 {
3932 struct hnae3_handle *h = hns3_get_handle(netdev);
3933
3934 if (h->ae_algo->ops->mac_disconnect_phy)
3935 h->ae_algo->ops->mac_disconnect_phy(h);
3936 }
3937
3938 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
3939 {
3940 struct hnae3_handle *h = hns3_get_handle(netdev);
3941
3942 if (h->ae_algo->ops->del_all_fd_entries)
3943 h->ae_algo->ops->del_all_fd_entries(h, clear_list);
3944 }
3945
3946 static int hns3_client_start(struct hnae3_handle *handle)
3947 {
3948 if (!handle->ae_algo->ops->client_start)
3949 return 0;
3950
3951 return handle->ae_algo->ops->client_start(handle);
3952 }
3953
3954 static void hns3_client_stop(struct hnae3_handle *handle)
3955 {
3956 if (!handle->ae_algo->ops->client_stop)
3957 return;
3958
3959 handle->ae_algo->ops->client_stop(handle);
3960 }
3961
3962 static void hns3_info_show(struct hns3_nic_priv *priv)
3963 {
3964 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3965
3966 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr);
3967 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
3968 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
3969 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
3970 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
3971 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
3972 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
3973 dev_info(priv->dev, "Total number of enabled TCs: %u\n", kinfo->num_tc);
3974 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
3975 }
3976
3977 static int hns3_client_init(struct hnae3_handle *handle)
3978 {
3979 struct pci_dev *pdev = handle->pdev;
3980 u16 alloc_tqps, max_rss_size;
3981 struct hns3_nic_priv *priv;
3982 struct net_device *netdev;
3983 int ret;
3984
3985 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
3986 &max_rss_size);
3987 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
3988 if (!netdev)
3989 return -ENOMEM;
3990
3991 priv = netdev_priv(netdev);
3992 priv->dev = &pdev->dev;
3993 priv->netdev = netdev;
3994 priv->ae_handle = handle;
3995 priv->tx_timeout_count = 0;
3996 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
3997
3998 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
3999
4000 handle->kinfo.netdev = netdev;
4001 handle->priv = (void *)priv;
4002
4003 hns3_init_mac_addr(netdev);
4004
4005 hns3_set_default_feature(netdev);
4006
4007 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
4008 netdev->priv_flags |= IFF_UNICAST_FLT;
4009 netdev->netdev_ops = &hns3_nic_netdev_ops;
4010 SET_NETDEV_DEV(netdev, &pdev->dev);
4011 hns3_ethtool_set_ops(netdev);
4012
4013 /* Carrier off reporting is important to ethtool even BEFORE open */
4014 netif_carrier_off(netdev);
4015
4016 ret = hns3_get_ring_config(priv);
4017 if (ret) {
4018 ret = -ENOMEM;
4019 goto out_get_ring_cfg;
4020 }
4021
4022 ret = hns3_nic_alloc_vector_data(priv);
4023 if (ret) {
4024 ret = -ENOMEM;
4025 goto out_alloc_vector_data;
4026 }
4027
4028 ret = hns3_nic_init_vector_data(priv);
4029 if (ret) {
4030 ret = -ENOMEM;
4031 goto out_init_vector_data;
4032 }
4033
4034 ret = hns3_init_all_ring(priv);
4035 if (ret) {
4036 ret = -ENOMEM;
4037 goto out_init_ring;
4038 }
4039
4040 ret = hns3_init_phy(netdev);
4041 if (ret)
4042 goto out_init_phy;
4043
4044 ret = register_netdev(netdev);
4045 if (ret) {
4046 dev_err(priv->dev, "probe register netdev fail!\n");
4047 goto out_reg_netdev_fail;
4048 }
4049
4050 /* the device can work without cpu rmap, only aRFS needs it */
4051 ret = hns3_set_rx_cpu_rmap(netdev);
4052 if (ret)
4053 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
4054
4055 ret = hns3_nic_init_irq(priv);
4056 if (ret) {
4057 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
4058 hns3_free_rx_cpu_rmap(netdev);
4059 goto out_init_irq_fail;
4060 }
4061
4062 ret = hns3_client_start(handle);
4063 if (ret) {
4064 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
4065 goto out_client_start;
4066 }
4067
4068 hns3_dcbnl_setup(handle);
4069
4070 hns3_dbg_init(handle);
4071
4072 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */
4073 netdev->max_mtu = HNS3_MAX_MTU;
4074
4075 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4076
4077 if (netif_msg_drv(handle))
4078 hns3_info_show(priv);
4079
4080 return ret;
4081
4082 out_client_start:
4083 hns3_free_rx_cpu_rmap(netdev);
4084 hns3_nic_uninit_irq(priv);
4085 out_init_irq_fail:
4086 unregister_netdev(netdev);
4087 out_reg_netdev_fail:
4088 hns3_uninit_phy(netdev);
4089 out_init_phy:
4090 hns3_uninit_all_ring(priv);
4091 out_init_ring:
4092 hns3_nic_uninit_vector_data(priv);
4093 out_init_vector_data:
4094 hns3_nic_dealloc_vector_data(priv);
4095 out_alloc_vector_data:
4096 priv->ring = NULL;
4097 out_get_ring_cfg:
4098 priv->ae_handle = NULL;
4099 free_netdev(netdev);
4100 return ret;
4101 }
4102
4103 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
4104 {
4105 struct net_device *netdev = handle->kinfo.netdev;
4106 struct hns3_nic_priv *priv = netdev_priv(netdev);
4107 int ret;
4108
4109 if (netdev->reg_state != NETREG_UNINITIALIZED)
4110 unregister_netdev(netdev);
4111
4112 hns3_client_stop(handle);
4113
4114 hns3_uninit_phy(netdev);
4115
4116 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4117 netdev_warn(netdev, "already uninitialized\n");
4118 goto out_netdev_free;
4119 }
4120
4121 hns3_free_rx_cpu_rmap(netdev);
4122
4123 hns3_nic_uninit_irq(priv);
4124
4125 hns3_del_all_fd_rules(netdev, true);
4126
4127 hns3_clear_all_ring(handle, true);
4128
4129 hns3_nic_uninit_vector_data(priv);
4130
4131 hns3_nic_dealloc_vector_data(priv);
4132
4133 ret = hns3_uninit_all_ring(priv);
4134 if (ret)
4135 netdev_err(netdev, "uninit ring error\n");
4136
4137 hns3_put_ring_config(priv);
4138
4139 out_netdev_free:
4140 hns3_dbg_uninit(handle);
4141 free_netdev(netdev);
4142 }
4143
4144 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
4145 {
4146 struct net_device *netdev = handle->kinfo.netdev;
4147
4148 if (!netdev)
4149 return;
4150
4151 if (linkup) {
4152 netif_tx_wake_all_queues(netdev);
4153 netif_carrier_on(netdev);
4154 if (netif_msg_link(handle))
4155 netdev_info(netdev, "link up\n");
4156 } else {
4157 netif_carrier_off(netdev);
4158 netif_tx_stop_all_queues(netdev);
4159 if (netif_msg_link(handle))
4160 netdev_info(netdev, "link down\n");
4161 }
4162 }
4163
4164 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
4165 {
4166 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4167 struct net_device *ndev = kinfo->netdev;
4168
4169 if (tc > HNAE3_MAX_TC)
4170 return -EINVAL;
4171
4172 if (!ndev)
4173 return -ENODEV;
4174
4175 return hns3_nic_set_real_num_queue(ndev);
4176 }
4177
4178 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
4179 {
4180 while (ring->next_to_clean != ring->next_to_use) {
4181 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
4182 hns3_free_buffer_detach(ring, ring->next_to_clean);
4183 ring_ptr_move_fw(ring, next_to_clean);
4184 }
4185 }
4186
4187 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
4188 {
4189 struct hns3_desc_cb res_cbs;
4190 int ret;
4191
4192 while (ring->next_to_use != ring->next_to_clean) {
4193 /* When a buffer is not reused, it's memory has been
4194 * freed in hns3_handle_rx_bd or will be freed by
4195 * stack, so we need to replace the buffer here.
4196 */
4197 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4198 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
4199 if (ret) {
4200 u64_stats_update_begin(&ring->syncp);
4201 ring->stats.sw_err_cnt++;
4202 u64_stats_update_end(&ring->syncp);
4203 /* if alloc new buffer fail, exit directly
4204 * and reclear in up flow.
4205 */
4206 netdev_warn(ring_to_netdev(ring),
4207 "reserve buffer map failed, ret = %d\n",
4208 ret);
4209 return ret;
4210 }
4211 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
4212 }
4213 ring_ptr_move_fw(ring, next_to_use);
4214 }
4215
4216 /* Free the pending skb in rx ring */
4217 if (ring->skb) {
4218 dev_kfree_skb_any(ring->skb);
4219 ring->skb = NULL;
4220 ring->pending_buf = 0;
4221 }
4222
4223 return 0;
4224 }
4225
4226 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
4227 {
4228 while (ring->next_to_use != ring->next_to_clean) {
4229 /* When a buffer is not reused, it's memory has been
4230 * freed in hns3_handle_rx_bd or will be freed by
4231 * stack, so only need to unmap the buffer here.
4232 */
4233 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4234 hns3_unmap_buffer(ring,
4235 &ring->desc_cb[ring->next_to_use]);
4236 ring->desc_cb[ring->next_to_use].dma = 0;
4237 }
4238
4239 ring_ptr_move_fw(ring, next_to_use);
4240 }
4241 }
4242
4243 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
4244 {
4245 struct net_device *ndev = h->kinfo.netdev;
4246 struct hns3_nic_priv *priv = netdev_priv(ndev);
4247 u32 i;
4248
4249 for (i = 0; i < h->kinfo.num_tqps; i++) {
4250 struct hns3_enet_ring *ring;
4251
4252 ring = &priv->ring[i];
4253 hns3_clear_tx_ring(ring);
4254
4255 ring = &priv->ring[i + h->kinfo.num_tqps];
4256 /* Continue to clear other rings even if clearing some
4257 * rings failed.
4258 */
4259 if (force)
4260 hns3_force_clear_rx_ring(ring);
4261 else
4262 hns3_clear_rx_ring(ring);
4263 }
4264 }
4265
4266 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
4267 {
4268 struct net_device *ndev = h->kinfo.netdev;
4269 struct hns3_nic_priv *priv = netdev_priv(ndev);
4270 struct hns3_enet_ring *rx_ring;
4271 int i, j;
4272 int ret;
4273
4274 for (i = 0; i < h->kinfo.num_tqps; i++) {
4275 ret = h->ae_algo->ops->reset_queue(h, i);
4276 if (ret)
4277 return ret;
4278
4279 hns3_init_ring_hw(&priv->ring[i]);
4280
4281 /* We need to clear tx ring here because self test will
4282 * use the ring and will not run down before up
4283 */
4284 hns3_clear_tx_ring(&priv->ring[i]);
4285 priv->ring[i].next_to_clean = 0;
4286 priv->ring[i].next_to_use = 0;
4287
4288 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
4289 hns3_init_ring_hw(rx_ring);
4290 ret = hns3_clear_rx_ring(rx_ring);
4291 if (ret)
4292 return ret;
4293
4294 /* We can not know the hardware head and tail when this
4295 * function is called in reset flow, so we reuse all desc.
4296 */
4297 for (j = 0; j < rx_ring->desc_num; j++)
4298 hns3_reuse_buffer(rx_ring, j);
4299
4300 rx_ring->next_to_clean = 0;
4301 rx_ring->next_to_use = 0;
4302 }
4303
4304 hns3_init_tx_ring_tc(priv);
4305
4306 return 0;
4307 }
4308
4309 static void hns3_store_coal(struct hns3_nic_priv *priv)
4310 {
4311 /* ethtool only support setting and querying one coal
4312 * configuration for now, so save the vector 0' coal
4313 * configuration here in order to restore it.
4314 */
4315 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
4316 sizeof(struct hns3_enet_coalesce));
4317 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
4318 sizeof(struct hns3_enet_coalesce));
4319 }
4320
4321 static void hns3_restore_coal(struct hns3_nic_priv *priv)
4322 {
4323 u16 vector_num = priv->vector_num;
4324 int i;
4325
4326 for (i = 0; i < vector_num; i++) {
4327 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
4328 sizeof(struct hns3_enet_coalesce));
4329 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
4330 sizeof(struct hns3_enet_coalesce));
4331 }
4332 }
4333
4334 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
4335 {
4336 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4337 struct net_device *ndev = kinfo->netdev;
4338 struct hns3_nic_priv *priv = netdev_priv(ndev);
4339
4340 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
4341 return 0;
4342
4343 if (!netif_running(ndev))
4344 return 0;
4345
4346 return hns3_nic_net_stop(ndev);
4347 }
4348
4349 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
4350 {
4351 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4352 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
4353 int ret = 0;
4354
4355 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4356
4357 if (netif_running(kinfo->netdev)) {
4358 ret = hns3_nic_net_open(kinfo->netdev);
4359 if (ret) {
4360 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4361 netdev_err(kinfo->netdev,
4362 "net up fail, ret=%d!\n", ret);
4363 return ret;
4364 }
4365 }
4366
4367 return ret;
4368 }
4369
4370 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
4371 {
4372 struct net_device *netdev = handle->kinfo.netdev;
4373 struct hns3_nic_priv *priv = netdev_priv(netdev);
4374 int ret;
4375
4376 /* Carrier off reporting is important to ethtool even BEFORE open */
4377 netif_carrier_off(netdev);
4378
4379 ret = hns3_get_ring_config(priv);
4380 if (ret)
4381 return ret;
4382
4383 ret = hns3_nic_alloc_vector_data(priv);
4384 if (ret)
4385 goto err_put_ring;
4386
4387 hns3_restore_coal(priv);
4388
4389 ret = hns3_nic_init_vector_data(priv);
4390 if (ret)
4391 goto err_dealloc_vector;
4392
4393 ret = hns3_init_all_ring(priv);
4394 if (ret)
4395 goto err_uninit_vector;
4396
4397 /* the device can work without cpu rmap, only aRFS needs it */
4398 ret = hns3_set_rx_cpu_rmap(netdev);
4399 if (ret)
4400 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
4401
4402 ret = hns3_nic_init_irq(priv);
4403 if (ret) {
4404 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
4405 hns3_free_rx_cpu_rmap(netdev);
4406 goto err_init_irq_fail;
4407 }
4408
4409 if (!hns3_is_phys_func(handle->pdev))
4410 hns3_init_mac_addr(netdev);
4411
4412 ret = hns3_client_start(handle);
4413 if (ret) {
4414 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
4415 goto err_client_start_fail;
4416 }
4417
4418 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4419
4420 return ret;
4421
4422 err_client_start_fail:
4423 hns3_free_rx_cpu_rmap(netdev);
4424 hns3_nic_uninit_irq(priv);
4425 err_init_irq_fail:
4426 hns3_uninit_all_ring(priv);
4427 err_uninit_vector:
4428 hns3_nic_uninit_vector_data(priv);
4429 err_dealloc_vector:
4430 hns3_nic_dealloc_vector_data(priv);
4431 err_put_ring:
4432 hns3_put_ring_config(priv);
4433
4434 return ret;
4435 }
4436
4437 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
4438 {
4439 struct net_device *netdev = handle->kinfo.netdev;
4440 struct hns3_nic_priv *priv = netdev_priv(netdev);
4441 int ret;
4442
4443 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4444 netdev_warn(netdev, "already uninitialized\n");
4445 return 0;
4446 }
4447
4448 hns3_free_rx_cpu_rmap(netdev);
4449 hns3_nic_uninit_irq(priv);
4450 hns3_clear_all_ring(handle, true);
4451 hns3_reset_tx_queue(priv->ae_handle);
4452
4453 hns3_nic_uninit_vector_data(priv);
4454
4455 hns3_store_coal(priv);
4456
4457 hns3_nic_dealloc_vector_data(priv);
4458
4459 ret = hns3_uninit_all_ring(priv);
4460 if (ret)
4461 netdev_err(netdev, "uninit ring error\n");
4462
4463 hns3_put_ring_config(priv);
4464
4465 return ret;
4466 }
4467
4468 static int hns3_reset_notify(struct hnae3_handle *handle,
4469 enum hnae3_reset_notify_type type)
4470 {
4471 int ret = 0;
4472
4473 switch (type) {
4474 case HNAE3_UP_CLIENT:
4475 ret = hns3_reset_notify_up_enet(handle);
4476 break;
4477 case HNAE3_DOWN_CLIENT:
4478 ret = hns3_reset_notify_down_enet(handle);
4479 break;
4480 case HNAE3_INIT_CLIENT:
4481 ret = hns3_reset_notify_init_enet(handle);
4482 break;
4483 case HNAE3_UNINIT_CLIENT:
4484 ret = hns3_reset_notify_uninit_enet(handle);
4485 break;
4486 default:
4487 break;
4488 }
4489
4490 return ret;
4491 }
4492
4493 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
4494 bool rxfh_configured)
4495 {
4496 int ret;
4497
4498 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
4499 rxfh_configured);
4500 if (ret) {
4501 dev_err(&handle->pdev->dev,
4502 "Change tqp num(%u) fail.\n", new_tqp_num);
4503 return ret;
4504 }
4505
4506 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
4507 if (ret)
4508 return ret;
4509
4510 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT);
4511 if (ret)
4512 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
4513
4514 return ret;
4515 }
4516
4517 int hns3_set_channels(struct net_device *netdev,
4518 struct ethtool_channels *ch)
4519 {
4520 struct hnae3_handle *h = hns3_get_handle(netdev);
4521 struct hnae3_knic_private_info *kinfo = &h->kinfo;
4522 bool rxfh_configured = netif_is_rxfh_configured(netdev);
4523 u32 new_tqp_num = ch->combined_count;
4524 u16 org_tqp_num;
4525 int ret;
4526
4527 if (hns3_nic_resetting(netdev))
4528 return -EBUSY;
4529
4530 if (ch->rx_count || ch->tx_count)
4531 return -EINVAL;
4532
4533 if (new_tqp_num > hns3_get_max_available_channels(h) ||
4534 new_tqp_num < 1) {
4535 dev_err(&netdev->dev,
4536 "Change tqps fail, the tqp range is from 1 to %u",
4537 hns3_get_max_available_channels(h));
4538 return -EINVAL;
4539 }
4540
4541 if (kinfo->rss_size == new_tqp_num)
4542 return 0;
4543
4544 netif_dbg(h, drv, netdev,
4545 "set channels: tqp_num=%u, rxfh=%d\n",
4546 new_tqp_num, rxfh_configured);
4547
4548 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
4549 if (ret)
4550 return ret;
4551
4552 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
4553 if (ret)
4554 return ret;
4555
4556 org_tqp_num = h->kinfo.num_tqps;
4557 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
4558 if (ret) {
4559 int ret1;
4560
4561 netdev_warn(netdev,
4562 "Change channels fail, revert to old value\n");
4563 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
4564 if (ret1) {
4565 netdev_err(netdev,
4566 "revert to old channel fail\n");
4567 return ret1;
4568 }
4569
4570 return ret;
4571 }
4572
4573 return 0;
4574 }
4575
4576 static const struct hns3_hw_error_info hns3_hw_err[] = {
4577 { .type = HNAE3_PPU_POISON_ERROR,
4578 .msg = "PPU poison" },
4579 { .type = HNAE3_CMDQ_ECC_ERROR,
4580 .msg = "IMP CMDQ error" },
4581 { .type = HNAE3_IMP_RD_POISON_ERROR,
4582 .msg = "IMP RD poison" },
4583 };
4584
4585 static void hns3_process_hw_error(struct hnae3_handle *handle,
4586 enum hnae3_hw_error_type type)
4587 {
4588 int i;
4589
4590 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
4591 if (hns3_hw_err[i].type == type) {
4592 dev_err(&handle->pdev->dev, "Detected %s!\n",
4593 hns3_hw_err[i].msg);
4594 break;
4595 }
4596 }
4597 }
4598
4599 static const struct hnae3_client_ops client_ops = {
4600 .init_instance = hns3_client_init,
4601 .uninit_instance = hns3_client_uninit,
4602 .link_status_change = hns3_link_status_change,
4603 .setup_tc = hns3_client_setup_tc,
4604 .reset_notify = hns3_reset_notify,
4605 .process_hw_error = hns3_process_hw_error,
4606 };
4607
4608 /* hns3_init_module - Driver registration routine
4609 * hns3_init_module is the first routine called when the driver is
4610 * loaded. All it does is register with the PCI subsystem.
4611 */
4612 static int __init hns3_init_module(void)
4613 {
4614 int ret;
4615
4616 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
4617 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
4618
4619 client.type = HNAE3_CLIENT_KNIC;
4620 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
4621 hns3_driver_name);
4622
4623 client.ops = &client_ops;
4624
4625 INIT_LIST_HEAD(&client.node);
4626
4627 hns3_dbg_register_debugfs(hns3_driver_name);
4628
4629 ret = hnae3_register_client(&client);
4630 if (ret)
4631 goto err_reg_client;
4632
4633 ret = pci_register_driver(&hns3_driver);
4634 if (ret)
4635 goto err_reg_driver;
4636
4637 return ret;
4638
4639 err_reg_driver:
4640 hnae3_unregister_client(&client);
4641 err_reg_client:
4642 hns3_dbg_unregister_debugfs();
4643 return ret;
4644 }
4645 module_init(hns3_init_module);
4646
4647 /* hns3_exit_module - Driver exit cleanup routine
4648 * hns3_exit_module is called just before the driver is removed
4649 * from memory.
4650 */
4651 static void __exit hns3_exit_module(void)
4652 {
4653 pci_unregister_driver(&hns3_driver);
4654 hnae3_unregister_client(&client);
4655 hns3_dbg_unregister_debugfs();
4656 }
4657 module_exit(hns3_exit_module);
4658
4659 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
4660 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4661 MODULE_LICENSE("GPL");
4662 MODULE_ALIAS("pci:hns-nic");