drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c

   1 /*
   2  * Copyright (c) 2016~2017 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/dma-mapping.h>
  11 #include <linux/slab.h>
  12 #include <linux/pci.h>
  13 #include <linux/device.h>
  14 #include <linux/err.h>
  15 #include <linux/dma-direction.h>
  16 #include "hclge_cmd.h"
  17 #include "hnae3.h"
  18 #include "hclge_main.h"
  19
  20 #define hclge_is_csq(ring) ((ring)->flag & HCLGE_TYPE_CSQ)
  21 #define hclge_ring_to_dma_dir(ring) (hclge_is_csq(ring) ? \
  22         DMA_TO_DEVICE : DMA_FROM_DEVICE)
  23 #define cmq_ring_to_dev(ring)   (&(ring)->dev->pdev->dev)
  24
  25 static int hclge_ring_space(struct hclge_cmq_ring *ring)
  26 {
  27         int ntu = ring->next_to_use;
  28         int ntc = ring->next_to_clean;
  29         int used = (ntu - ntc + ring->desc_num) % ring->desc_num;
  30
  31         return ring->desc_num - used - 1;
  32 }
  33
  34 static int hclge_alloc_cmd_desc(struct hclge_cmq_ring *ring)
  35 {
  36         int size  = ring->desc_num * sizeof(struct hclge_desc);
  37
  38         ring->desc = kzalloc(size, GFP_KERNEL);
  39         if (!ring->desc)
  40                 return -ENOMEM;
  41
  42         ring->desc_dma_addr = dma_map_single(cmq_ring_to_dev(ring), ring->desc,
  43                                              size, DMA_BIDIRECTIONAL);
  44         if (dma_mapping_error(cmq_ring_to_dev(ring), ring->desc_dma_addr)) {
  45                 ring->desc_dma_addr = 0;
  46                 kfree(ring->desc);
  47                 ring->desc = NULL;
  48                 return -ENOMEM;
  49         }
  50
  51         return 0;
  52 }
  53
  54 static void hclge_free_cmd_desc(struct hclge_cmq_ring *ring)
  55 {
  56         dma_unmap_single(cmq_ring_to_dev(ring), ring->desc_dma_addr,
  57                          ring->desc_num * sizeof(ring->desc[0]),
  58                          DMA_BIDIRECTIONAL);
  59
  60         ring->desc_dma_addr = 0;
  61         kfree(ring->desc);
  62         ring->desc = NULL;
  63 }
  64
  65 static int hclge_init_cmd_queue(struct hclge_dev *hdev, int ring_type)
  66 {
  67         struct hclge_hw *hw = &hdev->hw;
  68         struct hclge_cmq_ring *ring =
  69                 (ring_type == HCLGE_TYPE_CSQ) ? &hw->cmq.csq : &hw->cmq.crq;
  70         int ret;
  71
  72         ring->flag = ring_type;
  73         ring->dev = hdev;
  74
  75         ret = hclge_alloc_cmd_desc(ring);
  76         if (ret) {
  77                 dev_err(&hdev->pdev->dev, "descriptor %s alloc error %d\n",
  78                         (ring_type == HCLGE_TYPE_CSQ) ? "CSQ" : "CRQ", ret);
  79                 return ret;
  80         }
  81
  82         ring->next_to_clean = 0;
  83         ring->next_to_use = 0;
  84
  85         return 0;
  86 }
  87
  88 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read)
  89 {
  90         desc->flag = cpu_to_le16(HCLGE_CMD_FLAG_NO_INTR | HCLGE_CMD_FLAG_IN);
  91         if (is_read)
  92                 desc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_WR);
  93         else
  94                 desc->flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
  95 }
  96
  97 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
  98                                 enum hclge_opcode_type opcode, bool is_read)
  99 {
 100         memset((void *)desc, 0, sizeof(struct hclge_desc));
 101         desc->opcode = cpu_to_le16(opcode);
 102         desc->flag = cpu_to_le16(HCLGE_CMD_FLAG_NO_INTR | HCLGE_CMD_FLAG_IN);
 103
 104         if (is_read)
 105                 desc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_WR);
 106         else
 107                 desc->flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
 108 }
 109
 110 static void hclge_cmd_config_regs(struct hclge_cmq_ring *ring)
 111 {
 112         dma_addr_t dma = ring->desc_dma_addr;
 113         struct hclge_dev *hdev = ring->dev;
 114         struct hclge_hw *hw = &hdev->hw;
 115
 116         if (ring->flag == HCLGE_TYPE_CSQ) {
 117                 hclge_write_dev(hw, HCLGE_NIC_CSQ_BASEADDR_L_REG,
 118                                 (u32)dma);
 119                 hclge_write_dev(hw, HCLGE_NIC_CSQ_BASEADDR_H_REG,
 120                                 (u32)((dma >> 31) >> 1));
 121                 hclge_write_dev(hw, HCLGE_NIC_CSQ_DEPTH_REG,
 122                                 (ring->desc_num >> HCLGE_NIC_CMQ_DESC_NUM_S) |
 123                                 HCLGE_NIC_CMQ_ENABLE);
 124                 hclge_write_dev(hw, HCLGE_NIC_CSQ_TAIL_REG, 0);
 125                 hclge_write_dev(hw, HCLGE_NIC_CSQ_HEAD_REG, 0);
 126         } else {
 127                 hclge_write_dev(hw, HCLGE_NIC_CRQ_BASEADDR_L_REG,
 128                                 (u32)dma);
 129                 hclge_write_dev(hw, HCLGE_NIC_CRQ_BASEADDR_H_REG,
 130                                 (u32)((dma >> 31) >> 1));
 131                 hclge_write_dev(hw, HCLGE_NIC_CRQ_DEPTH_REG,
 132                                 (ring->desc_num >> HCLGE_NIC_CMQ_DESC_NUM_S) |
 133                                 HCLGE_NIC_CMQ_ENABLE);
 134                 hclge_write_dev(hw, HCLGE_NIC_CRQ_TAIL_REG, 0);
 135                 hclge_write_dev(hw, HCLGE_NIC_CRQ_HEAD_REG, 0);
 136         }
 137 }
 138
 139 static void hclge_cmd_init_regs(struct hclge_hw *hw)
 140 {
 141         hclge_cmd_config_regs(&hw->cmq.csq);
 142         hclge_cmd_config_regs(&hw->cmq.crq);
 143 }
 144
 145 static int hclge_cmd_csq_clean(struct hclge_hw *hw)
 146 {
 147         struct hclge_cmq_ring *csq = &hw->cmq.csq;
 148         u16 ntc = csq->next_to_clean;
 149         struct hclge_desc *desc;
 150         int clean = 0;
 151         u32 head;
 152
 153         desc = &csq->desc[ntc];
 154         head = hclge_read_dev(hw, HCLGE_NIC_CSQ_HEAD_REG);
 155
 156         while (head != ntc) {
 157                 memset(desc, 0, sizeof(*desc));
 158                 ntc++;
 159                 if (ntc == csq->desc_num)
 160                         ntc = 0;
 161                 desc = &csq->desc[ntc];
 162                 clean++;
 163         }
 164         csq->next_to_clean = ntc;
 165
 166         return clean;
 167 }
 168
 169 static int hclge_cmd_csq_done(struct hclge_hw *hw)
 170 {
 171         u32 head = hclge_read_dev(hw, HCLGE_NIC_CSQ_HEAD_REG);
 172         return head == hw->cmq.csq.next_to_use;
 173 }
 174
 175 static bool hclge_is_special_opcode(u16 opcode)
 176 {
 177         u16 spec_opcode[3] = {0x0030, 0x0031, 0x0032};
 178         int i;
 179
 180         for (i = 0; i < ARRAY_SIZE(spec_opcode); i++) {
 181                 if (spec_opcode[i] == opcode)
 182                         return true;
 183         }
 184
 185         return false;
 186 }
 187
 188 /**
 189  * hclge_cmd_send - send command to command queue
 190  * @hw: pointer to the hw struct
 191  * @desc: prefilled descriptor for describing the command
 192  * @num : the number of descriptors to be sent
 193  *
 194  * This is the main send command for command queue, it
 195  * sends the queue, cleans the queue, etc
 196  **/
 197 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
 198 {
 199         struct hclge_dev *hdev = (struct hclge_dev *)hw->back;
 200         struct hclge_desc *desc_to_use;
 201         bool complete = false;
 202         u32 timeout = 0;
 203         int handle = 0;
 204         int retval = 0;
 205         u16 opcode, desc_ret;
 206         int ntc;
 207
 208         spin_lock_bh(&hw->cmq.csq.lock);
 209
 210         if (num > hclge_ring_space(&hw->cmq.csq)) {
 211                 spin_unlock_bh(&hw->cmq.csq.lock);
 212                 return -EBUSY;
 213         }
 214
 215         /**
 216          * Record the location of desc in the ring for this time
 217          * which will be use for hardware to write back
 218          */
 219         ntc = hw->cmq.csq.next_to_use;
 220         opcode = le16_to_cpu(desc[0].opcode);
 221         while (handle < num) {
 222                 desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use];
 223                 *desc_to_use = desc[handle];
 224                 (hw->cmq.csq.next_to_use)++;
 225                 if (hw->cmq.csq.next_to_use == hw->cmq.csq.desc_num)
 226                         hw->cmq.csq.next_to_use = 0;
 227                 handle++;
 228         }
 229
 230         /* Write to hardware */
 231         hclge_write_dev(hw, HCLGE_NIC_CSQ_TAIL_REG, hw->cmq.csq.next_to_use);
 232
 233         /**
 234          * If the command is sync, wait for the firmware to write back,
 235          * if multi descriptors to be sent, use the first one to check
 236          */
 237         if (HCLGE_SEND_SYNC(le16_to_cpu(desc->flag))) {
 238                 do {
 239                         if (hclge_cmd_csq_done(hw))
 240                                 break;
 241                         udelay(1);
 242                         timeout++;
 243                 } while (timeout < hw->cmq.tx_timeout);
 244         }
 245
 246         if (hclge_cmd_csq_done(hw)) {
 247                 complete = true;
 248                 handle = 0;
 249                 while (handle < num) {
 250                         /* Get the result of hardware write back */
 251                         desc_to_use = &hw->cmq.csq.desc[ntc];
 252                         desc[handle] = *desc_to_use;
 253                         pr_debug("Get cmd desc:\n");
 254
 255                         if (likely(!hclge_is_special_opcode(opcode)))
 256                                 desc_ret = le16_to_cpu(desc[handle].retval);
 257                         else
 258                                 desc_ret = le16_to_cpu(desc[0].retval);
 259
 260                         if ((enum hclge_cmd_return_status)desc_ret ==
 261                             HCLGE_CMD_EXEC_SUCCESS)
 262                                 retval = 0;
 263                         else
 264                                 retval = -EIO;
 265                         hw->cmq.last_status = (enum hclge_cmd_status)desc_ret;
 266                         ntc++;
 267                         handle++;
 268                         if (ntc == hw->cmq.csq.desc_num)
 269                                 ntc = 0;
 270                 }
 271         }
 272
 273         if (!complete)
 274                 retval = -EAGAIN;
 275
 276         /* Clean the command send queue */
 277         handle = hclge_cmd_csq_clean(hw);
 278         if (handle != num) {
 279                 dev_warn(&hdev->pdev->dev,
 280                          "cleaned %d, need to clean %d\n", handle, num);
 281         }
 282
 283         spin_unlock_bh(&hw->cmq.csq.lock);
 284
 285         return retval;
 286 }
 287
 288 static enum hclge_cmd_status hclge_cmd_query_firmware_version(
 289                 struct hclge_hw *hw, u32 *version)
 290 {
 291         struct hclge_query_version_cmd *resp;
 292         struct hclge_desc desc;
 293         int ret;
 294
 295         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FW_VER, 1);
 296         resp = (struct hclge_query_version_cmd *)desc.data;
 297
 298         ret = hclge_cmd_send(hw, &desc, 1);
 299         if (!ret)
 300                 *version = le32_to_cpu(resp->firmware);
 301
 302         return ret;
 303 }
 304
 305 int hclge_cmd_init(struct hclge_dev *hdev)
 306 {
 307         u32 version;
 308         int ret;
 309
 310         /* Setup the queue entries for use cmd queue */
 311         hdev->hw.cmq.csq.desc_num = HCLGE_NIC_CMQ_DESC_NUM;
 312         hdev->hw.cmq.crq.desc_num = HCLGE_NIC_CMQ_DESC_NUM;
 313
 314         /* Setup the lock for command queue */
 315         spin_lock_init(&hdev->hw.cmq.csq.lock);
 316         spin_lock_init(&hdev->hw.cmq.crq.lock);
 317
 318         /* Setup Tx write back timeout */
 319         hdev->hw.cmq.tx_timeout = HCLGE_CMDQ_TX_TIMEOUT;
 320
 321         /* Setup queue rings */
 322         ret = hclge_init_cmd_queue(hdev, HCLGE_TYPE_CSQ);
 323         if (ret) {
 324                 dev_err(&hdev->pdev->dev,
 325                         "CSQ ring setup error %d\n", ret);
 326                 return ret;
 327         }
 328
 329         ret = hclge_init_cmd_queue(hdev, HCLGE_TYPE_CRQ);
 330         if (ret) {
 331                 dev_err(&hdev->pdev->dev,
 332                         "CRQ ring setup error %d\n", ret);
 333                 goto err_csq;
 334         }
 335
 336         hclge_cmd_init_regs(&hdev->hw);
 337
 338         ret = hclge_cmd_query_firmware_version(&hdev->hw, &version);
 339         if (ret) {
 340                 dev_err(&hdev->pdev->dev,
 341                         "firmware version query failed %d\n", ret);
 342                 return ret;
 343         }
 344         hdev->fw_version = version;
 345
 346         dev_info(&hdev->pdev->dev, "The firmware version is %08x\n", version);
 347
 348         return 0;
 349 err_csq:
 350         hclge_free_cmd_desc(&hdev->hw.cmq.csq);
 351         return ret;
 352 }
 353
 354 static void hclge_destroy_queue(struct hclge_cmq_ring *ring)
 355 {
 356         spin_lock_bh(&ring->lock);
 357         hclge_free_cmd_desc(ring);
 358         spin_unlock_bh(&ring->lock);
 359 }
 360
 361 void hclge_destroy_cmd_queue(struct hclge_hw *hw)
 362 {
 363         hclge_destroy_queue(&hw->cmq.csq);
 364         hclge_destroy_queue(&hw->cmq.crq);
 365 }