drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c

   1 /*
   2  * Copyright (c) 2016~2017 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/dma-mapping.h>
  11 #include <linux/slab.h>
  12 #include <linux/pci.h>
  13 #include <linux/device.h>
  14 #include <linux/err.h>
  15 #include <linux/dma-direction.h>
  16 #include "hclge_cmd.h"
  17 #include "hnae3.h"
  18 #include "hclge_main.h"
  19
  20 #define hclge_is_csq(ring) ((ring)->flag & HCLGE_TYPE_CSQ)
  21
  22 #define cmq_ring_to_dev(ring)   (&(ring)->dev->pdev->dev)
  23
  24 static int hclge_ring_space(struct hclge_cmq_ring *ring)
  25 {
  26         int ntu = ring->next_to_use;
  27         int ntc = ring->next_to_clean;
  28         int used = (ntu - ntc + ring->desc_num) % ring->desc_num;
  29
  30         return ring->desc_num - used - 1;
  31 }
  32
  33 static int is_valid_csq_clean_head(struct hclge_cmq_ring *ring, int h)
  34 {
  35         int u = ring->next_to_use;
  36         int c = ring->next_to_clean;
  37
  38         if (unlikely(h >= ring->desc_num))
  39                 return 0;
  40
  41         return u > c ? (h > c && h <= u) : (h > c || h <= u);
  42 }
  43
  44 static int hclge_alloc_cmd_desc(struct hclge_cmq_ring *ring)
  45 {
  46         int size  = ring->desc_num * sizeof(struct hclge_desc);
  47
  48         ring->desc = kzalloc(size, GFP_KERNEL);
  49         if (!ring->desc)
  50                 return -ENOMEM;
  51
  52         ring->desc_dma_addr = dma_map_single(cmq_ring_to_dev(ring), ring->desc,
  53                                              size, DMA_BIDIRECTIONAL);
  54         if (dma_mapping_error(cmq_ring_to_dev(ring), ring->desc_dma_addr)) {
  55                 ring->desc_dma_addr = 0;
  56                 kfree(ring->desc);
  57                 ring->desc = NULL;
  58                 return -ENOMEM;
  59         }
  60
  61         return 0;
  62 }
  63
  64 static void hclge_free_cmd_desc(struct hclge_cmq_ring *ring)
  65 {
  66         dma_unmap_single(cmq_ring_to_dev(ring), ring->desc_dma_addr,
  67                          ring->desc_num * sizeof(ring->desc[0]),
  68                          DMA_BIDIRECTIONAL);
  69
  70         ring->desc_dma_addr = 0;
  71         kfree(ring->desc);
  72         ring->desc = NULL;
  73 }
  74
  75 static int hclge_alloc_cmd_queue(struct hclge_dev *hdev, int ring_type)
  76 {
  77         struct hclge_hw *hw = &hdev->hw;
  78         struct hclge_cmq_ring *ring =
  79                 (ring_type == HCLGE_TYPE_CSQ) ? &hw->cmq.csq : &hw->cmq.crq;
  80         int ret;
  81
  82         ring->flag = ring_type;
  83         ring->dev = hdev;
  84
  85         ret = hclge_alloc_cmd_desc(ring);
  86         if (ret) {
  87                 dev_err(&hdev->pdev->dev, "descriptor %s alloc error %d\n",
  88                         (ring_type == HCLGE_TYPE_CSQ) ? "CSQ" : "CRQ", ret);
  89                 return ret;
  90         }
  91
  92         return 0;
  93 }
  94
  95 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read)
  96 {
  97         desc->flag = cpu_to_le16(HCLGE_CMD_FLAG_NO_INTR | HCLGE_CMD_FLAG_IN);
  98         if (is_read)
  99                 desc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_WR);
 100         else
 101                 desc->flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
 102 }
 103
 104 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
 105                                 enum hclge_opcode_type opcode, bool is_read)
 106 {
 107         memset((void *)desc, 0, sizeof(struct hclge_desc));
 108         desc->opcode = cpu_to_le16(opcode);
 109         desc->flag = cpu_to_le16(HCLGE_CMD_FLAG_NO_INTR | HCLGE_CMD_FLAG_IN);
 110
 111         if (is_read)
 112                 desc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_WR);
 113         else
 114                 desc->flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
 115 }
 116
 117 static void hclge_cmd_config_regs(struct hclge_cmq_ring *ring)
 118 {
 119         dma_addr_t dma = ring->desc_dma_addr;
 120         struct hclge_dev *hdev = ring->dev;
 121         struct hclge_hw *hw = &hdev->hw;
 122
 123         if (ring->flag == HCLGE_TYPE_CSQ) {
 124                 hclge_write_dev(hw, HCLGE_NIC_CSQ_BASEADDR_L_REG,
 125                                 lower_32_bits(dma));
 126                 hclge_write_dev(hw, HCLGE_NIC_CSQ_BASEADDR_H_REG,
 127                                 upper_32_bits(dma));
 128                 hclge_write_dev(hw, HCLGE_NIC_CSQ_DEPTH_REG,
 129                                 (ring->desc_num >> HCLGE_NIC_CMQ_DESC_NUM_S) |
 130                                 HCLGE_NIC_CMQ_ENABLE);
 131                 hclge_write_dev(hw, HCLGE_NIC_CSQ_TAIL_REG, 0);
 132                 hclge_write_dev(hw, HCLGE_NIC_CSQ_HEAD_REG, 0);
 133         } else {
 134                 hclge_write_dev(hw, HCLGE_NIC_CRQ_BASEADDR_L_REG,
 135                                 lower_32_bits(dma));
 136                 hclge_write_dev(hw, HCLGE_NIC_CRQ_BASEADDR_H_REG,
 137                                 upper_32_bits(dma));
 138                 hclge_write_dev(hw, HCLGE_NIC_CRQ_DEPTH_REG,
 139                                 (ring->desc_num >> HCLGE_NIC_CMQ_DESC_NUM_S) |
 140                                 HCLGE_NIC_CMQ_ENABLE);
 141                 hclge_write_dev(hw, HCLGE_NIC_CRQ_TAIL_REG, 0);
 142                 hclge_write_dev(hw, HCLGE_NIC_CRQ_HEAD_REG, 0);
 143         }
 144 }
 145
 146 static void hclge_cmd_init_regs(struct hclge_hw *hw)
 147 {
 148         hclge_cmd_config_regs(&hw->cmq.csq);
 149         hclge_cmd_config_regs(&hw->cmq.crq);
 150 }
 151
 152 static int hclge_cmd_csq_clean(struct hclge_hw *hw)
 153 {
 154         struct hclge_dev *hdev = container_of(hw, struct hclge_dev, hw);
 155         struct hclge_cmq_ring *csq = &hw->cmq.csq;
 156         u16 ntc = csq->next_to_clean;
 157         struct hclge_desc *desc;
 158         int clean = 0;
 159         u32 head;
 160
 161         desc = &csq->desc[ntc];
 162         head = hclge_read_dev(hw, HCLGE_NIC_CSQ_HEAD_REG);
 163         rmb(); /* Make sure head is ready before touch any data */
 164
 165         if (!is_valid_csq_clean_head(csq, head)) {
 166                 dev_warn(&hdev->pdev->dev, "wrong head (%d, %d-%d)\n", head,
 167                            csq->next_to_use, csq->next_to_clean);
 168                 return 0;
 169         }
 170
 171         while (head != ntc) {
 172                 memset(desc, 0, sizeof(*desc));
 173                 ntc++;
 174                 if (ntc == csq->desc_num)
 175                         ntc = 0;
 176                 desc = &csq->desc[ntc];
 177                 clean++;
 178         }
 179         csq->next_to_clean = ntc;
 180
 181         return clean;
 182 }
 183
 184 static int hclge_cmd_csq_done(struct hclge_hw *hw)
 185 {
 186         u32 head = hclge_read_dev(hw, HCLGE_NIC_CSQ_HEAD_REG);
 187         return head == hw->cmq.csq.next_to_use;
 188 }
 189
 190 static bool hclge_is_special_opcode(u16 opcode)
 191 {
 192         /* these commands have several descriptors,
 193          * and use the first one to save opcode and return value
 194          */
 195         u16 spec_opcode[3] = {HCLGE_OPC_STATS_64_BIT,
 196                 HCLGE_OPC_STATS_32_BIT, HCLGE_OPC_STATS_MAC};
 197         int i;
 198
 199         for (i = 0; i < ARRAY_SIZE(spec_opcode); i++) {
 200                 if (spec_opcode[i] == opcode)
 201                         return true;
 202         }
 203
 204         return false;
 205 }
 206
 207 /**
 208  * hclge_cmd_send - send command to command queue
 209  * @hw: pointer to the hw struct
 210  * @desc: prefilled descriptor for describing the command
 211  * @num : the number of descriptors to be sent
 212  *
 213  * This is the main send command for command queue, it
 214  * sends the queue, cleans the queue, etc
 215  **/
 216 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
 217 {
 218         struct hclge_dev *hdev = container_of(hw, struct hclge_dev, hw);
 219         struct hclge_desc *desc_to_use;
 220         bool complete = false;
 221         u32 timeout = 0;
 222         int handle = 0;
 223         int retval = 0;
 224         u16 opcode, desc_ret;
 225         int ntc;
 226
 227         spin_lock_bh(&hw->cmq.csq.lock);
 228
 229         if (num > hclge_ring_space(&hw->cmq.csq)) {
 230                 spin_unlock_bh(&hw->cmq.csq.lock);
 231                 return -EBUSY;
 232         }
 233
 234         /**
 235          * Record the location of desc in the ring for this time
 236          * which will be use for hardware to write back
 237          */
 238         ntc = hw->cmq.csq.next_to_use;
 239         opcode = le16_to_cpu(desc[0].opcode);
 240         while (handle < num) {
 241                 desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use];
 242                 *desc_to_use = desc[handle];
 243                 (hw->cmq.csq.next_to_use)++;
 244                 if (hw->cmq.csq.next_to_use == hw->cmq.csq.desc_num)
 245                         hw->cmq.csq.next_to_use = 0;
 246                 handle++;
 247         }
 248
 249         /* Write to hardware */
 250         hclge_write_dev(hw, HCLGE_NIC_CSQ_TAIL_REG, hw->cmq.csq.next_to_use);
 251
 252         /**
 253          * If the command is sync, wait for the firmware to write back,
 254          * if multi descriptors to be sent, use the first one to check
 255          */
 256         if (HCLGE_SEND_SYNC(le16_to_cpu(desc->flag))) {
 257                 do {
 258                         if (hclge_cmd_csq_done(hw))
 259                                 break;
 260                         udelay(1);
 261                         timeout++;
 262                 } while (timeout < hw->cmq.tx_timeout);
 263         }
 264
 265         if (hclge_cmd_csq_done(hw)) {
 266                 complete = true;
 267                 handle = 0;
 268                 while (handle < num) {
 269                         /* Get the result of hardware write back */
 270                         desc_to_use = &hw->cmq.csq.desc[ntc];
 271                         desc[handle] = *desc_to_use;
 272                         pr_debug("Get cmd desc:\n");
 273
 274                         if (likely(!hclge_is_special_opcode(opcode)))
 275                                 desc_ret = le16_to_cpu(desc[handle].retval);
 276                         else
 277                                 desc_ret = le16_to_cpu(desc[0].retval);
 278
 279                         if ((enum hclge_cmd_return_status)desc_ret ==
 280                             HCLGE_CMD_EXEC_SUCCESS)
 281                                 retval = 0;
 282                         else
 283                                 retval = -EIO;
 284                         hw->cmq.last_status = (enum hclge_cmd_status)desc_ret;
 285                         ntc++;
 286                         handle++;
 287                         if (ntc == hw->cmq.csq.desc_num)
 288                                 ntc = 0;
 289                 }
 290         }
 291
 292         if (!complete)
 293                 retval = -EAGAIN;
 294
 295         /* Clean the command send queue */
 296         handle = hclge_cmd_csq_clean(hw);
 297         if (handle != num) {
 298                 dev_warn(&hdev->pdev->dev,
 299                          "cleaned %d, need to clean %d\n", handle, num);
 300         }
 301
 302         spin_unlock_bh(&hw->cmq.csq.lock);
 303
 304         return retval;
 305 }
 306
 307 static enum hclge_cmd_status hclge_cmd_query_firmware_version(
 308                 struct hclge_hw *hw, u32 *version)
 309 {
 310         struct hclge_query_version_cmd *resp;
 311         struct hclge_desc desc;
 312         int ret;
 313
 314         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FW_VER, 1);
 315         resp = (struct hclge_query_version_cmd *)desc.data;
 316
 317         ret = hclge_cmd_send(hw, &desc, 1);
 318         if (!ret)
 319                 *version = le32_to_cpu(resp->firmware);
 320
 321         return ret;
 322 }
 323
 324 int hclge_cmd_queue_init(struct hclge_dev *hdev)
 325 {
 326         int ret;
 327
 328         /* Setup the queue entries for use cmd queue */
 329         hdev->hw.cmq.csq.desc_num = HCLGE_NIC_CMQ_DESC_NUM;
 330         hdev->hw.cmq.crq.desc_num = HCLGE_NIC_CMQ_DESC_NUM;
 331
 332         /* Setup Tx write back timeout */
 333         hdev->hw.cmq.tx_timeout = HCLGE_CMDQ_TX_TIMEOUT;
 334
 335         /* Setup queue rings */
 336         ret = hclge_alloc_cmd_queue(hdev, HCLGE_TYPE_CSQ);
 337         if (ret) {
 338                 dev_err(&hdev->pdev->dev,
 339                         "CSQ ring setup error %d\n", ret);
 340                 return ret;
 341         }
 342
 343         ret = hclge_alloc_cmd_queue(hdev, HCLGE_TYPE_CRQ);
 344         if (ret) {
 345                 dev_err(&hdev->pdev->dev,
 346                         "CRQ ring setup error %d\n", ret);
 347                 goto err_csq;
 348         }
 349
 350         return 0;
 351 err_csq:
 352         hclge_free_cmd_desc(&hdev->hw.cmq.csq);
 353         return ret;
 354 }
 355
 356 int hclge_cmd_init(struct hclge_dev *hdev)
 357 {
 358         u32 version;
 359         int ret;
 360
 361         hdev->hw.cmq.csq.next_to_clean = 0;
 362         hdev->hw.cmq.csq.next_to_use = 0;
 363         hdev->hw.cmq.crq.next_to_clean = 0;
 364         hdev->hw.cmq.crq.next_to_use = 0;
 365
 366         /* Setup the lock for command queue */
 367         spin_lock_init(&hdev->hw.cmq.csq.lock);
 368         spin_lock_init(&hdev->hw.cmq.crq.lock);
 369
 370         hclge_cmd_init_regs(&hdev->hw);
 371
 372         ret = hclge_cmd_query_firmware_version(&hdev->hw, &version);
 373         if (ret) {
 374                 dev_err(&hdev->pdev->dev,
 375                         "firmware version query failed %d\n", ret);
 376                 return ret;
 377         }
 378         hdev->fw_version = version;
 379
 380         dev_info(&hdev->pdev->dev, "The firmware version is %08x\n", version);
 381
 382         return 0;
 383 }
 384
 385 static void hclge_destroy_queue(struct hclge_cmq_ring *ring)
 386 {
 387         spin_lock(&ring->lock);
 388         hclge_free_cmd_desc(ring);
 389         spin_unlock(&ring->lock);
 390 }
 391
 392 void hclge_destroy_cmd_queue(struct hclge_hw *hw)
 393 {
 394         hclge_destroy_queue(&hw->cmq.csq);
 395         hclge_destroy_queue(&hw->cmq.crq);
 396 }