drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include <linux/dma-mapping.h>
   5 #include <linux/slab.h>
   6 #include <linux/pci.h>
   7 #include <linux/device.h>
   8 #include <linux/err.h>
   9 #include <linux/dma-direction.h>
  10 #include "hclge_cmd.h"
  11 #include "hnae3.h"
  12 #include "hclge_main.h"
  13
  14 #define hclge_is_csq(ring) ((ring)->flag & HCLGE_TYPE_CSQ)
  15
  16 #define cmq_ring_to_dev(ring)   (&(ring)->dev->pdev->dev)
  17
  18 static int hclge_ring_space(struct hclge_cmq_ring *ring)
  19 {
  20         int ntu = ring->next_to_use;
  21         int ntc = ring->next_to_clean;
  22         int used = (ntu - ntc + ring->desc_num) % ring->desc_num;
  23
  24         return ring->desc_num - used - 1;
  25 }
  26
  27 static int is_valid_csq_clean_head(struct hclge_cmq_ring *ring, int h)
  28 {
  29         int u = ring->next_to_use;
  30         int c = ring->next_to_clean;
  31
  32         if (unlikely(h >= ring->desc_num))
  33                 return 0;
  34
  35         return u > c ? (h > c && h <= u) : (h > c || h <= u);
  36 }
  37
  38 static int hclge_alloc_cmd_desc(struct hclge_cmq_ring *ring)
  39 {
  40         int size  = ring->desc_num * sizeof(struct hclge_desc);
  41
  42         ring->desc = dma_zalloc_coherent(cmq_ring_to_dev(ring),
  43                                          size, &ring->desc_dma_addr,
  44                                          GFP_KERNEL);
  45         if (!ring->desc)
  46                 return -ENOMEM;
  47
  48         return 0;
  49 }
  50
  51 static void hclge_free_cmd_desc(struct hclge_cmq_ring *ring)
  52 {
  53         int size  = ring->desc_num * sizeof(struct hclge_desc);
  54
  55         if (ring->desc) {
  56                 dma_free_coherent(cmq_ring_to_dev(ring), size,
  57                                   ring->desc, ring->desc_dma_addr);
  58                 ring->desc = NULL;
  59         }
  60 }
  61
  62 static int hclge_alloc_cmd_queue(struct hclge_dev *hdev, int ring_type)
  63 {
  64         struct hclge_hw *hw = &hdev->hw;
  65         struct hclge_cmq_ring *ring =
  66                 (ring_type == HCLGE_TYPE_CSQ) ? &hw->cmq.csq : &hw->cmq.crq;
  67         int ret;
  68
  69         ring->ring_type = ring_type;
  70         ring->dev = hdev;
  71
  72         ret = hclge_alloc_cmd_desc(ring);
  73         if (ret) {
  74                 dev_err(&hdev->pdev->dev, "descriptor %s alloc error %d\n",
  75                         (ring_type == HCLGE_TYPE_CSQ) ? "CSQ" : "CRQ", ret);
  76                 return ret;
  77         }
  78
  79         return 0;
  80 }
  81
  82 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read)
  83 {
  84         desc->flag = cpu_to_le16(HCLGE_CMD_FLAG_NO_INTR | HCLGE_CMD_FLAG_IN);
  85         if (is_read)
  86                 desc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_WR);
  87         else
  88                 desc->flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
  89 }
  90
  91 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
  92                                 enum hclge_opcode_type opcode, bool is_read)
  93 {
  94         memset((void *)desc, 0, sizeof(struct hclge_desc));
  95         desc->opcode = cpu_to_le16(opcode);
  96         desc->flag = cpu_to_le16(HCLGE_CMD_FLAG_NO_INTR | HCLGE_CMD_FLAG_IN);
  97
  98         if (is_read)
  99                 desc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_WR);
 100 }
 101
 102 static void hclge_cmd_config_regs(struct hclge_cmq_ring *ring)
 103 {
 104         dma_addr_t dma = ring->desc_dma_addr;
 105         struct hclge_dev *hdev = ring->dev;
 106         struct hclge_hw *hw = &hdev->hw;
 107
 108         if (ring->ring_type == HCLGE_TYPE_CSQ) {
 109                 hclge_write_dev(hw, HCLGE_NIC_CSQ_BASEADDR_L_REG,
 110                                 lower_32_bits(dma));
 111                 hclge_write_dev(hw, HCLGE_NIC_CSQ_BASEADDR_H_REG,
 112                                 upper_32_bits(dma));
 113                 hclge_write_dev(hw, HCLGE_NIC_CSQ_DEPTH_REG,
 114                                 (ring->desc_num >> HCLGE_NIC_CMQ_DESC_NUM_S) |
 115                                 HCLGE_NIC_CMQ_ENABLE);
 116                 hclge_write_dev(hw, HCLGE_NIC_CSQ_HEAD_REG, 0);
 117                 hclge_write_dev(hw, HCLGE_NIC_CSQ_TAIL_REG, 0);
 118         } else {
 119                 hclge_write_dev(hw, HCLGE_NIC_CRQ_BASEADDR_L_REG,
 120                                 lower_32_bits(dma));
 121                 hclge_write_dev(hw, HCLGE_NIC_CRQ_BASEADDR_H_REG,
 122                                 upper_32_bits(dma));
 123                 hclge_write_dev(hw, HCLGE_NIC_CRQ_DEPTH_REG,
 124                                 (ring->desc_num >> HCLGE_NIC_CMQ_DESC_NUM_S) |
 125                                 HCLGE_NIC_CMQ_ENABLE);
 126                 hclge_write_dev(hw, HCLGE_NIC_CRQ_HEAD_REG, 0);
 127                 hclge_write_dev(hw, HCLGE_NIC_CRQ_TAIL_REG, 0);
 128         }
 129 }
 130
 131 static void hclge_cmd_init_regs(struct hclge_hw *hw)
 132 {
 133         hclge_cmd_config_regs(&hw->cmq.csq);
 134         hclge_cmd_config_regs(&hw->cmq.crq);
 135 }
 136
 137 static int hclge_cmd_csq_clean(struct hclge_hw *hw)
 138 {
 139         struct hclge_dev *hdev = container_of(hw, struct hclge_dev, hw);
 140         struct hclge_cmq_ring *csq = &hw->cmq.csq;
 141         u32 head;
 142         int clean;
 143
 144         head = hclge_read_dev(hw, HCLGE_NIC_CSQ_HEAD_REG);
 145         rmb(); /* Make sure head is ready before touch any data */
 146
 147         if (!is_valid_csq_clean_head(csq, head)) {
 148                 dev_warn(&hdev->pdev->dev, "wrong cmd head (%d, %d-%d)\n", head,
 149                          csq->next_to_use, csq->next_to_clean);
 150                 return 0;
 151         }
 152
 153         clean = (head - csq->next_to_clean + csq->desc_num) % csq->desc_num;
 154         csq->next_to_clean = head;
 155         return clean;
 156 }
 157
 158 static int hclge_cmd_csq_done(struct hclge_hw *hw)
 159 {
 160         u32 head = hclge_read_dev(hw, HCLGE_NIC_CSQ_HEAD_REG);
 161         return head == hw->cmq.csq.next_to_use;
 162 }
 163
 164 static bool hclge_is_special_opcode(u16 opcode)
 165 {
 166         /* these commands have several descriptors,
 167          * and use the first one to save opcode and return value
 168          */
 169         u16 spec_opcode[3] = {HCLGE_OPC_STATS_64_BIT,
 170                 HCLGE_OPC_STATS_32_BIT, HCLGE_OPC_STATS_MAC};
 171         int i;
 172
 173         for (i = 0; i < ARRAY_SIZE(spec_opcode); i++) {
 174                 if (spec_opcode[i] == opcode)
 175                         return true;
 176         }
 177
 178         return false;
 179 }
 180
 181 /**
 182  * hclge_cmd_send - send command to command queue
 183  * @hw: pointer to the hw struct
 184  * @desc: prefilled descriptor for describing the command
 185  * @num : the number of descriptors to be sent
 186  *
 187  * This is the main send command for command queue, it
 188  * sends the queue, cleans the queue, etc
 189  **/
 190 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
 191 {
 192         struct hclge_dev *hdev = container_of(hw, struct hclge_dev, hw);
 193         struct hclge_desc *desc_to_use;
 194         bool complete = false;
 195         u32 timeout = 0;
 196         int handle = 0;
 197         int retval = 0;
 198         u16 opcode, desc_ret;
 199         int ntc;
 200
 201         spin_lock_bh(&hw->cmq.csq.lock);
 202
 203         if (num > hclge_ring_space(&hw->cmq.csq) ||
 204             test_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state)) {
 205                 spin_unlock_bh(&hw->cmq.csq.lock);
 206                 return -EBUSY;
 207         }
 208
 209         /**
 210          * Record the location of desc in the ring for this time
 211          * which will be use for hardware to write back
 212          */
 213         ntc = hw->cmq.csq.next_to_use;
 214         opcode = le16_to_cpu(desc[0].opcode);
 215         while (handle < num) {
 216                 desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use];
 217                 *desc_to_use = desc[handle];
 218                 (hw->cmq.csq.next_to_use)++;
 219                 hw->cmq.csq.next_to_use %= hw->cmq.csq.desc_num;
 220                 handle++;
 221         }
 222
 223         /* Write to hardware */
 224         hclge_write_dev(hw, HCLGE_NIC_CSQ_TAIL_REG, hw->cmq.csq.next_to_use);
 225
 226         /**
 227          * If the command is sync, wait for the firmware to write back,
 228          * if multi descriptors to be sent, use the first one to check
 229          */
 230         if (HCLGE_SEND_SYNC(le16_to_cpu(desc->flag))) {
 231                 do {
 232                         if (hclge_cmd_csq_done(hw)) {
 233                                 complete = true;
 234                                 break;
 235                         }
 236                         udelay(1);
 237                         timeout++;
 238                 } while (timeout < hw->cmq.tx_timeout);
 239         }
 240
 241         if (!complete) {
 242                 retval = -EAGAIN;
 243         } else {
 244                 handle = 0;
 245                 while (handle < num) {
 246                         /* Get the result of hardware write back */
 247                         desc_to_use = &hw->cmq.csq.desc[ntc];
 248                         desc[handle] = *desc_to_use;
 249
 250                         if (likely(!hclge_is_special_opcode(opcode)))
 251                                 desc_ret = le16_to_cpu(desc[handle].retval);
 252                         else
 253                                 desc_ret = le16_to_cpu(desc[0].retval);
 254
 255                         if (desc_ret == HCLGE_CMD_EXEC_SUCCESS)
 256                                 retval = 0;
 257                         else
 258                                 retval = -EIO;
 259                         hw->cmq.last_status = desc_ret;
 260                         ntc++;
 261                         handle++;
 262                         ntc %= hw->cmq.csq.desc_num;
 263                 }
 264         }
 265
 266         /* Clean the command send queue */
 267         handle = hclge_cmd_csq_clean(hw);
 268         if (handle != num) {
 269                 dev_warn(&hdev->pdev->dev,
 270                          "cleaned %d, need to clean %d\n", handle, num);
 271         }
 272
 273         spin_unlock_bh(&hw->cmq.csq.lock);
 274
 275         return retval;
 276 }
 277
 278 static enum hclge_cmd_status hclge_cmd_query_firmware_version(
 279                 struct hclge_hw *hw, u32 *version)
 280 {
 281         struct hclge_query_version_cmd *resp;
 282         struct hclge_desc desc;
 283         int ret;
 284
 285         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FW_VER, 1);
 286         resp = (struct hclge_query_version_cmd *)desc.data;
 287
 288         ret = hclge_cmd_send(hw, &desc, 1);
 289         if (!ret)
 290                 *version = le32_to_cpu(resp->firmware);
 291
 292         return ret;
 293 }
 294
 295 int hclge_cmd_queue_init(struct hclge_dev *hdev)
 296 {
 297         int ret;
 298
 299         /* Setup the queue entries for use cmd queue */
 300         hdev->hw.cmq.csq.desc_num = HCLGE_NIC_CMQ_DESC_NUM;
 301         hdev->hw.cmq.crq.desc_num = HCLGE_NIC_CMQ_DESC_NUM;
 302
 303         /* Setup Tx write back timeout */
 304         hdev->hw.cmq.tx_timeout = HCLGE_CMDQ_TX_TIMEOUT;
 305
 306         /* Setup queue rings */
 307         ret = hclge_alloc_cmd_queue(hdev, HCLGE_TYPE_CSQ);
 308         if (ret) {
 309                 dev_err(&hdev->pdev->dev,
 310                         "CSQ ring setup error %d\n", ret);
 311                 return ret;
 312         }
 313
 314         ret = hclge_alloc_cmd_queue(hdev, HCLGE_TYPE_CRQ);
 315         if (ret) {
 316                 dev_err(&hdev->pdev->dev,
 317                         "CRQ ring setup error %d\n", ret);
 318                 goto err_csq;
 319         }
 320
 321         return 0;
 322 err_csq:
 323         hclge_free_cmd_desc(&hdev->hw.cmq.csq);
 324         return ret;
 325 }
 326
 327 int hclge_cmd_init(struct hclge_dev *hdev)
 328 {
 329         u32 version;
 330         int ret;
 331
 332         hdev->hw.cmq.csq.next_to_clean = 0;
 333         hdev->hw.cmq.csq.next_to_use = 0;
 334         hdev->hw.cmq.crq.next_to_clean = 0;
 335         hdev->hw.cmq.crq.next_to_use = 0;
 336
 337         /* Setup the lock for command queue */
 338         spin_lock_init(&hdev->hw.cmq.csq.lock);
 339         spin_lock_init(&hdev->hw.cmq.crq.lock);
 340
 341         hclge_cmd_init_regs(&hdev->hw);
 342         clear_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
 343
 344         ret = hclge_cmd_query_firmware_version(&hdev->hw, &version);
 345         if (ret) {
 346                 dev_err(&hdev->pdev->dev,
 347                         "firmware version query failed %d\n", ret);
 348                 return ret;
 349         }
 350         hdev->fw_version = version;
 351
 352         dev_info(&hdev->pdev->dev, "The firmware version is %08x\n", version);
 353
 354         return 0;
 355 }
 356
 357 static void hclge_destroy_queue(struct hclge_cmq_ring *ring)
 358 {
 359         spin_lock(&ring->lock);
 360         hclge_free_cmd_desc(ring);
 361         spin_unlock(&ring->lock);
 362 }
 363
 364 void hclge_destroy_cmd_queue(struct hclge_hw *hw)
 365 {
 366         hclge_destroy_queue(&hw->cmq.csq);
 367         hclge_destroy_queue(&hw->cmq.crq);
 368 }