drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

   1 /*
   2  * Copyright (c) 2016~2017 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #ifndef __HCLGE_CMD_H
  11 #define __HCLGE_CMD_H
  12 #include <linux/types.h>
  13 #include <linux/io.h>
  14
  15 #define HCLGE_CMDQ_TX_TIMEOUT           30000
  16
  17 struct hclge_dev;
  18 struct hclge_desc {
  19         __le16 opcode;
  20
  21 #define HCLGE_CMDQ_RX_INVLD_B           0
  22 #define HCLGE_CMDQ_RX_OUTVLD_B          1
  23
  24         __le16 flag;
  25         __le16 retval;
  26         __le16 rsv;
  27         __le32 data[6];
  28 };
  29
  30 struct hclge_desc_cb {
  31         dma_addr_t dma;
  32         void *va;
  33         u32 length;
  34 };
  35
  36 struct hclge_cmq_ring {
  37         dma_addr_t desc_dma_addr;
  38         struct hclge_desc *desc;
  39         struct hclge_desc_cb *desc_cb;
  40         struct hclge_dev *dev;
  41         u32 head;
  42         u32 tail;
  43
  44         u16 buf_size;
  45         u16 desc_num;
  46         int next_to_use;
  47         int next_to_clean;
  48         u8 flag;
  49         spinlock_t lock; /* Command queue lock */
  50 };
  51
  52 enum hclge_cmd_return_status {
  53         HCLGE_CMD_EXEC_SUCCESS  = 0,
  54         HCLGE_CMD_NO_AUTH       = 1,
  55         HCLGE_CMD_NOT_EXEC      = 2,
  56         HCLGE_CMD_QUEUE_FULL    = 3,
  57 };
  58
  59 enum hclge_cmd_status {
  60         HCLGE_STATUS_SUCCESS    = 0,
  61         HCLGE_ERR_CSQ_FULL      = -1,
  62         HCLGE_ERR_CSQ_TIMEOUT   = -2,
  63         HCLGE_ERR_CSQ_ERROR     = -3,
  64 };
  65
  66 struct hclge_misc_vector {
  67         u8 __iomem *addr;
  68         int vector_irq;
  69 };
  70
  71 struct hclge_cmq {
  72         struct hclge_cmq_ring csq;
  73         struct hclge_cmq_ring crq;
  74         u16 tx_timeout;
  75         enum hclge_cmd_status last_status;
  76 };
  77
  78 #define HCLGE_CMD_FLAG_IN_VALID_SHIFT   0
  79 #define HCLGE_CMD_FLAG_OUT_VALID_SHIFT  1
  80 #define HCLGE_CMD_FLAG_NEXT_SHIFT       2
  81 #define HCLGE_CMD_FLAG_WR_OR_RD_SHIFT   3
  82 #define HCLGE_CMD_FLAG_NO_INTR_SHIFT    4
  83 #define HCLGE_CMD_FLAG_ERR_INTR_SHIFT   5
  84
  85 #define HCLGE_CMD_FLAG_IN       BIT(HCLGE_CMD_FLAG_IN_VALID_SHIFT)
  86 #define HCLGE_CMD_FLAG_OUT      BIT(HCLGE_CMD_FLAG_OUT_VALID_SHIFT)
  87 #define HCLGE_CMD_FLAG_NEXT     BIT(HCLGE_CMD_FLAG_NEXT_SHIFT)
  88 #define HCLGE_CMD_FLAG_WR       BIT(HCLGE_CMD_FLAG_WR_OR_RD_SHIFT)
  89 #define HCLGE_CMD_FLAG_NO_INTR  BIT(HCLGE_CMD_FLAG_NO_INTR_SHIFT)
  90 #define HCLGE_CMD_FLAG_ERR_INTR BIT(HCLGE_CMD_FLAG_ERR_INTR_SHIFT)
  91
  92 enum hclge_opcode_type {
  93         /* Generic commands */
  94         HCLGE_OPC_QUERY_FW_VER          = 0x0001,
  95         HCLGE_OPC_CFG_RST_TRIGGER       = 0x0020,
  96         HCLGE_OPC_GBL_RST_STATUS        = 0x0021,
  97         HCLGE_OPC_QUERY_FUNC_STATUS     = 0x0022,
  98         HCLGE_OPC_QUERY_PF_RSRC         = 0x0023,
  99         HCLGE_OPC_QUERY_VF_RSRC         = 0x0024,
 100         HCLGE_OPC_GET_CFG_PARAM         = 0x0025,
 101
 102         HCLGE_OPC_STATS_64_BIT          = 0x0030,
 103         HCLGE_OPC_STATS_32_BIT          = 0x0031,
 104         HCLGE_OPC_STATS_MAC             = 0x0032,
 105
 106         HCLGE_OPC_QUERY_REG_NUM         = 0x0040,
 107         HCLGE_OPC_QUERY_32_BIT_REG      = 0x0041,
 108         HCLGE_OPC_QUERY_64_BIT_REG      = 0x0042,
 109
 110         /* MAC command */
 111         HCLGE_OPC_CONFIG_MAC_MODE       = 0x0301,
 112         HCLGE_OPC_CONFIG_AN_MODE        = 0x0304,
 113         HCLGE_OPC_QUERY_AN_RESULT       = 0x0306,
 114         HCLGE_OPC_QUERY_LINK_STATUS     = 0x0307,
 115         HCLGE_OPC_CONFIG_MAX_FRM_SIZE   = 0x0308,
 116         HCLGE_OPC_CONFIG_SPEED_DUP      = 0x0309,
 117         HCLGE_OPC_SERDES_LOOPBACK       = 0x0315,
 118
 119         /* PFC/Pause commands*/
 120         HCLGE_OPC_CFG_MAC_PAUSE_EN      = 0x0701,
 121         HCLGE_OPC_CFG_PFC_PAUSE_EN      = 0x0702,
 122         HCLGE_OPC_CFG_MAC_PARA          = 0x0703,
 123         HCLGE_OPC_CFG_PFC_PARA          = 0x0704,
 124         HCLGE_OPC_QUERY_MAC_TX_PKT_CNT  = 0x0705,
 125         HCLGE_OPC_QUERY_MAC_RX_PKT_CNT  = 0x0706,
 126         HCLGE_OPC_QUERY_PFC_TX_PKT_CNT  = 0x0707,
 127         HCLGE_OPC_QUERY_PFC_RX_PKT_CNT  = 0x0708,
 128         HCLGE_OPC_PRI_TO_TC_MAPPING     = 0x0709,
 129         HCLGE_OPC_QOS_MAP               = 0x070A,
 130
 131         /* ETS/scheduler commands */
 132         HCLGE_OPC_TM_PG_TO_PRI_LINK     = 0x0804,
 133         HCLGE_OPC_TM_QS_TO_PRI_LINK     = 0x0805,
 134         HCLGE_OPC_TM_NQ_TO_QS_LINK      = 0x0806,
 135         HCLGE_OPC_TM_RQ_TO_QS_LINK      = 0x0807,
 136         HCLGE_OPC_TM_PORT_WEIGHT        = 0x0808,
 137         HCLGE_OPC_TM_PG_WEIGHT          = 0x0809,
 138         HCLGE_OPC_TM_QS_WEIGHT          = 0x080A,
 139         HCLGE_OPC_TM_PRI_WEIGHT         = 0x080B,
 140         HCLGE_OPC_TM_PRI_C_SHAPPING     = 0x080C,
 141         HCLGE_OPC_TM_PRI_P_SHAPPING     = 0x080D,
 142         HCLGE_OPC_TM_PG_C_SHAPPING      = 0x080E,
 143         HCLGE_OPC_TM_PG_P_SHAPPING      = 0x080F,
 144         HCLGE_OPC_TM_PORT_SHAPPING      = 0x0810,
 145         HCLGE_OPC_TM_PG_SCH_MODE_CFG    = 0x0812,
 146         HCLGE_OPC_TM_PRI_SCH_MODE_CFG   = 0x0813,
 147         HCLGE_OPC_TM_QS_SCH_MODE_CFG    = 0x0814,
 148         HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
 149
 150         /* Packet buffer allocate commands */
 151         HCLGE_OPC_TX_BUFF_ALLOC         = 0x0901,
 152         HCLGE_OPC_RX_PRIV_BUFF_ALLOC    = 0x0902,
 153         HCLGE_OPC_RX_PRIV_WL_ALLOC      = 0x0903,
 154         HCLGE_OPC_RX_COM_THRD_ALLOC     = 0x0904,
 155         HCLGE_OPC_RX_COM_WL_ALLOC       = 0x0905,
 156         HCLGE_OPC_RX_GBL_PKT_CNT        = 0x0906,
 157
 158         /* TQP management command */
 159         HCLGE_OPC_SET_TQP_MAP           = 0x0A01,
 160
 161         /* TQP commands */
 162         HCLGE_OPC_CFG_TX_QUEUE          = 0x0B01,
 163         HCLGE_OPC_QUERY_TX_POINTER      = 0x0B02,
 164         HCLGE_OPC_QUERY_TX_STATUS       = 0x0B03,
 165         HCLGE_OPC_CFG_RX_QUEUE          = 0x0B11,
 166         HCLGE_OPC_QUERY_RX_POINTER      = 0x0B12,
 167         HCLGE_OPC_QUERY_RX_STATUS       = 0x0B13,
 168         HCLGE_OPC_STASH_RX_QUEUE_LRO    = 0x0B16,
 169         HCLGE_OPC_CFG_RX_QUEUE_LRO      = 0x0B17,
 170         HCLGE_OPC_CFG_COM_TQP_QUEUE     = 0x0B20,
 171         HCLGE_OPC_RESET_TQP_QUEUE       = 0x0B22,
 172
 173         /* TSO command */
 174         HCLGE_OPC_TSO_GENERIC_CONFIG    = 0x0C01,
 175
 176         /* RSS commands */
 177         HCLGE_OPC_RSS_GENERIC_CONFIG    = 0x0D01,
 178         HCLGE_OPC_RSS_INDIR_TABLE       = 0x0D07,
 179         HCLGE_OPC_RSS_TC_MODE           = 0x0D08,
 180         HCLGE_OPC_RSS_INPUT_TUPLE       = 0x0D02,
 181
 182         /* Promisuous mode command */
 183         HCLGE_OPC_CFG_PROMISC_MODE      = 0x0E01,
 184
 185         /* Vlan offload commands */
 186         HCLGE_OPC_VLAN_PORT_TX_CFG      = 0x0F01,
 187         HCLGE_OPC_VLAN_PORT_RX_CFG      = 0x0F02,
 188
 189         /* Interrupts commands */
 190         HCLGE_OPC_ADD_RING_TO_VECTOR    = 0x1503,
 191         HCLGE_OPC_DEL_RING_TO_VECTOR    = 0x1504,
 192
 193         /* MAC commands */
 194         HCLGE_OPC_MAC_VLAN_ADD              = 0x1000,
 195         HCLGE_OPC_MAC_VLAN_REMOVE           = 0x1001,
 196         HCLGE_OPC_MAC_VLAN_TYPE_ID          = 0x1002,
 197         HCLGE_OPC_MAC_VLAN_INSERT           = 0x1003,
 198         HCLGE_OPC_MAC_ETHTYPE_ADD           = 0x1010,
 199         HCLGE_OPC_MAC_ETHTYPE_REMOVE    = 0x1011,
 200         HCLGE_OPC_MAC_VLAN_MASK_SET     = 0x1012,
 201
 202         /* Multicast linear table commands */
 203         HCLGE_OPC_MTA_MAC_MODE_CFG          = 0x1020,
 204         HCLGE_OPC_MTA_MAC_FUNC_CFG          = 0x1021,
 205         HCLGE_OPC_MTA_TBL_ITEM_CFG          = 0x1022,
 206         HCLGE_OPC_MTA_TBL_ITEM_QUERY    = 0x1023,
 207
 208         /* VLAN commands */
 209         HCLGE_OPC_VLAN_FILTER_CTRL          = 0x1100,
 210         HCLGE_OPC_VLAN_FILTER_PF_CFG    = 0x1101,
 211         HCLGE_OPC_VLAN_FILTER_VF_CFG    = 0x1102,
 212
 213         /* MDIO command */
 214         HCLGE_OPC_MDIO_CONFIG           = 0x1900,
 215
 216         /* QCN commands */
 217         HCLGE_OPC_QCN_MOD_CFG           = 0x1A01,
 218         HCLGE_OPC_QCN_GRP_TMPLT_CFG     = 0x1A02,
 219         HCLGE_OPC_QCN_SHAPPING_IR_CFG   = 0x1A03,
 220         HCLGE_OPC_QCN_SHAPPING_BS_CFG   = 0x1A04,
 221         HCLGE_OPC_QCN_QSET_LINK_CFG     = 0x1A05,
 222         HCLGE_OPC_QCN_RP_STATUS_GET     = 0x1A06,
 223         HCLGE_OPC_QCN_AJUST_INIT        = 0x1A07,
 224         HCLGE_OPC_QCN_DFX_CNT_STATUS    = 0x1A08,
 225
 226         /* Mailbox command */
 227         HCLGEVF_OPC_MBX_PF_TO_VF        = 0x2000,
 228
 229         /* Led command */
 230         HCLGE_OPC_LED_STATUS_CFG        = 0xB000,
 231 };
 232
 233 #define HCLGE_TQP_REG_OFFSET            0x80000
 234 #define HCLGE_TQP_REG_SIZE              0x200
 235
 236 #define HCLGE_RCB_INIT_QUERY_TIMEOUT    10
 237 #define HCLGE_RCB_INIT_FLAG_EN_B        0
 238 #define HCLGE_RCB_INIT_FLAG_FINI_B      8
 239 struct hclge_config_rcb_init_cmd {
 240         __le16 rcb_init_flag;
 241         u8 rsv[22];
 242 };
 243
 244 struct hclge_tqp_map_cmd {
 245         __le16 tqp_id;  /* Absolute tqp id for in this pf */
 246         u8 tqp_vf;      /* VF id */
 247 #define HCLGE_TQP_MAP_TYPE_PF           0
 248 #define HCLGE_TQP_MAP_TYPE_VF           1
 249 #define HCLGE_TQP_MAP_TYPE_B            0
 250 #define HCLGE_TQP_MAP_EN_B              1
 251         u8 tqp_flag;    /* Indicate it's pf or vf tqp */
 252         __le16 tqp_vid; /* Virtual id in this pf/vf */
 253         u8 rsv[18];
 254 };
 255
 256 #define HCLGE_VECTOR_ELEMENTS_PER_CMD   10
 257
 258 enum hclge_int_type {
 259         HCLGE_INT_TX,
 260         HCLGE_INT_RX,
 261         HCLGE_INT_EVENT,
 262 };
 263
 264 struct hclge_ctrl_vector_chain_cmd {
 265         u8 int_vector_id;
 266         u8 int_cause_num;
 267 #define HCLGE_INT_TYPE_S        0
 268 #define HCLGE_INT_TYPE_M        GENMASK(1, 0)
 269 #define HCLGE_TQP_ID_S          2
 270 #define HCLGE_TQP_ID_M          GENMASK(12, 2)
 271 #define HCLGE_INT_GL_IDX_S      13
 272 #define HCLGE_INT_GL_IDX_M      GENMASK(14, 13)
 273         __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];
 274         u8 vfid;
 275         u8 rsv;
 276 };
 277
 278 #define HCLGE_TC_NUM            8
 279 #define HCLGE_TC0_PRI_BUF_EN_B  15 /* Bit 15 indicate enable or not */
 280 #define HCLGE_BUF_UNIT_S        7  /* Buf size is united by 128 bytes */
 281 struct hclge_tx_buff_alloc_cmd {
 282         __le16 tx_pkt_buff[HCLGE_TC_NUM];
 283         u8 tx_buff_rsv[8];
 284 };
 285
 286 struct hclge_rx_priv_buff_cmd {
 287         __le16 buf_num[HCLGE_TC_NUM];
 288         __le16 shared_buf;
 289         u8 rsv[6];
 290 };
 291
 292 struct hclge_query_version_cmd {
 293         __le32 firmware;
 294         __le32 firmware_rsv[5];
 295 };
 296
 297 #define HCLGE_RX_PRIV_EN_B      15
 298 #define HCLGE_TC_NUM_ONE_DESC   4
 299 struct hclge_priv_wl {
 300         __le16 high;
 301         __le16 low;
 302 };
 303
 304 struct hclge_rx_priv_wl_buf {
 305         struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC];
 306 };
 307
 308 struct hclge_rx_com_thrd {
 309         struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC];
 310 };
 311
 312 struct hclge_rx_com_wl {
 313         struct hclge_priv_wl com_wl;
 314 };
 315
 316 struct hclge_waterline {
 317         u32 low;
 318         u32 high;
 319 };
 320
 321 struct hclge_tc_thrd {
 322         u32 low;
 323         u32 high;
 324 };
 325
 326 struct hclge_priv_buf {
 327         struct hclge_waterline wl;      /* Waterline for low and high*/
 328         u32 buf_size;   /* TC private buffer size */
 329         u32 tx_buf_size;
 330         u32 enable;     /* Enable TC private buffer or not */
 331 };
 332
 333 #define HCLGE_MAX_TC_NUM        8
 334 struct hclge_shared_buf {
 335         struct hclge_waterline self;
 336         struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM];
 337         u32 buf_size;
 338 };
 339
 340 struct hclge_pkt_buf_alloc {
 341         struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM];
 342         struct hclge_shared_buf s_buf;
 343 };
 344
 345 #define HCLGE_RX_COM_WL_EN_B    15
 346 struct hclge_rx_com_wl_buf_cmd {
 347         __le16 high_wl;
 348         __le16 low_wl;
 349         u8 rsv[20];
 350 };
 351
 352 #define HCLGE_RX_PKT_EN_B       15
 353 struct hclge_rx_pkt_buf_cmd {
 354         __le16 high_pkt;
 355         __le16 low_pkt;
 356         u8 rsv[20];
 357 };
 358
 359 #define HCLGE_PF_STATE_DONE_B   0
 360 #define HCLGE_PF_STATE_MAIN_B   1
 361 #define HCLGE_PF_STATE_BOND_B   2
 362 #define HCLGE_PF_STATE_MAC_N_B  6
 363 #define HCLGE_PF_MAC_NUM_MASK   0x3
 364 #define HCLGE_PF_STATE_MAIN     BIT(HCLGE_PF_STATE_MAIN_B)
 365 #define HCLGE_PF_STATE_DONE     BIT(HCLGE_PF_STATE_DONE_B)
 366 struct hclge_func_status_cmd {
 367         __le32  vf_rst_state[4];
 368         u8 pf_state;
 369         u8 mac_id;
 370         u8 rsv1;
 371         u8 pf_cnt_in_mac;
 372         u8 pf_num;
 373         u8 vf_num;
 374         u8 rsv[2];
 375 };
 376
 377 struct hclge_pf_res_cmd {
 378         __le16 tqp_num;
 379         __le16 buf_size;
 380         __le16 msixcap_localid_ba_nic;
 381         __le16 msixcap_localid_ba_rocee;
 382 #define HCLGE_PF_VEC_NUM_S              0
 383 #define HCLGE_PF_VEC_NUM_M              (0xff << HCLGE_PF_VEC_NUM_S)
 384         __le16 pf_intr_vector_number;
 385         __le16 pf_own_fun_number;
 386         __le32 rsv[3];
 387 };
 388
 389 #define HCLGE_CFG_OFFSET_S      0
 390 #define HCLGE_CFG_OFFSET_M      GENMASK(19, 0)
 391 #define HCLGE_CFG_RD_LEN_S      24
 392 #define HCLGE_CFG_RD_LEN_M      GENMASK(27, 24)
 393 #define HCLGE_CFG_RD_LEN_BYTES  16
 394 #define HCLGE_CFG_RD_LEN_UNIT   4
 395
 396 #define HCLGE_CFG_VMDQ_S        0
 397 #define HCLGE_CFG_VMDQ_M        GENMASK(7, 0)
 398 #define HCLGE_CFG_TC_NUM_S      8
 399 #define HCLGE_CFG_TC_NUM_M      GENMASK(15, 8)
 400 #define HCLGE_CFG_TQP_DESC_N_S  16
 401 #define HCLGE_CFG_TQP_DESC_N_M  GENMASK(31, 16)
 402 #define HCLGE_CFG_PHY_ADDR_S    0
 403 #define HCLGE_CFG_PHY_ADDR_M    GENMASK(7, 0)
 404 #define HCLGE_CFG_MEDIA_TP_S    8
 405 #define HCLGE_CFG_MEDIA_TP_M    GENMASK(15, 8)
 406 #define HCLGE_CFG_RX_BUF_LEN_S  16
 407 #define HCLGE_CFG_RX_BUF_LEN_M  GENMASK(31, 16)
 408 #define HCLGE_CFG_MAC_ADDR_H_S  0
 409 #define HCLGE_CFG_MAC_ADDR_H_M  GENMASK(15, 0)
 410 #define HCLGE_CFG_DEFAULT_SPEED_S       16
 411 #define HCLGE_CFG_DEFAULT_SPEED_M       GENMASK(23, 16)
 412 #define HCLGE_CFG_RSS_SIZE_S    24
 413 #define HCLGE_CFG_RSS_SIZE_M    GENMASK(31, 24)
 414 #define HCLGE_CFG_SPEED_ABILITY_S       0
 415 #define HCLGE_CFG_SPEED_ABILITY_M       GENMASK(7, 0)
 416
 417 struct hclge_cfg_param_cmd {
 418         __le32 offset;
 419         __le32 rsv;
 420         __le32 param[4];
 421 };
 422
 423 #define HCLGE_MAC_MODE          0x0
 424 #define HCLGE_DESC_NUM          0x40
 425
 426 #define HCLGE_ALLOC_VALID_B     0
 427 struct hclge_vf_num_cmd {
 428         u8 alloc_valid;
 429         u8 rsv[23];
 430 };
 431
 432 #define HCLGE_RSS_DEFAULT_OUTPORT_B     4
 433 #define HCLGE_RSS_HASH_KEY_OFFSET_B     4
 434 #define HCLGE_RSS_HASH_KEY_NUM          16
 435 struct hclge_rss_config_cmd {
 436         u8 hash_config;
 437         u8 rsv[7];
 438         u8 hash_key[HCLGE_RSS_HASH_KEY_NUM];
 439 };
 440
 441 struct hclge_rss_input_tuple_cmd {
 442         u8 ipv4_tcp_en;
 443         u8 ipv4_udp_en;
 444         u8 ipv4_sctp_en;
 445         u8 ipv4_fragment_en;
 446         u8 ipv6_tcp_en;
 447         u8 ipv6_udp_en;
 448         u8 ipv6_sctp_en;
 449         u8 ipv6_fragment_en;
 450         u8 rsv[16];
 451 };
 452
 453 #define HCLGE_RSS_CFG_TBL_SIZE  16
 454
 455 struct hclge_rss_indirection_table_cmd {
 456         __le16 start_table_index;
 457         __le16 rss_set_bitmap;
 458         u8 rsv[4];
 459         u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE];
 460 };
 461
 462 #define HCLGE_RSS_TC_OFFSET_S           0
 463 #define HCLGE_RSS_TC_OFFSET_M           GENMASK(9, 0)
 464 #define HCLGE_RSS_TC_SIZE_S             12
 465 #define HCLGE_RSS_TC_SIZE_M             GENMASK(14, 12)
 466 #define HCLGE_RSS_TC_VALID_B            15
 467 struct hclge_rss_tc_mode_cmd {
 468         __le16 rss_tc_mode[HCLGE_MAX_TC_NUM];
 469         u8 rsv[8];
 470 };
 471
 472 #define HCLGE_LINK_STS_B        0
 473 #define HCLGE_LINK_STATUS       BIT(HCLGE_LINK_STS_B)
 474 struct hclge_link_status_cmd {
 475         u8 status;
 476         u8 rsv[23];
 477 };
 478
 479 struct hclge_promisc_param {
 480         u8 vf_id;
 481         u8 enable;
 482 };
 483
 484 #define HCLGE_PROMISC_TX_EN_B   BIT(4)
 485 #define HCLGE_PROMISC_RX_EN_B   BIT(5)
 486 #define HCLGE_PROMISC_EN_B      1
 487 #define HCLGE_PROMISC_EN_ALL    0x7
 488 #define HCLGE_PROMISC_EN_UC     0x1
 489 #define HCLGE_PROMISC_EN_MC     0x2
 490 #define HCLGE_PROMISC_EN_BC     0x4
 491 struct hclge_promisc_cfg_cmd {
 492         u8 flag;
 493         u8 vf_id;
 494         __le16 rsv0;
 495         u8 rsv1[20];
 496 };
 497
 498 enum hclge_promisc_type {
 499         HCLGE_UNICAST   = 1,
 500         HCLGE_MULTICAST = 2,
 501         HCLGE_BROADCAST = 3,
 502 };
 503
 504 #define HCLGE_MAC_TX_EN_B       6
 505 #define HCLGE_MAC_RX_EN_B       7
 506 #define HCLGE_MAC_PAD_TX_B      11
 507 #define HCLGE_MAC_PAD_RX_B      12
 508 #define HCLGE_MAC_1588_TX_B     13
 509 #define HCLGE_MAC_1588_RX_B     14
 510 #define HCLGE_MAC_APP_LP_B      15
 511 #define HCLGE_MAC_LINE_LP_B     16
 512 #define HCLGE_MAC_FCS_TX_B      17
 513 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B        18
 514 #define HCLGE_MAC_RX_FCS_STRIP_B        19
 515 #define HCLGE_MAC_RX_FCS_B      20
 516 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B            21
 517 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B        22
 518
 519 struct hclge_config_mac_mode_cmd {
 520         __le32 txrx_pad_fcs_loop_en;
 521         u8 rsv[20];
 522 };
 523
 524 #define HCLGE_CFG_SPEED_S               0
 525 #define HCLGE_CFG_SPEED_M               GENMASK(5, 0)
 526
 527 #define HCLGE_CFG_DUPLEX_B              7
 528 #define HCLGE_CFG_DUPLEX_M              BIT(HCLGE_CFG_DUPLEX_B)
 529
 530 struct hclge_config_mac_speed_dup_cmd {
 531         u8 speed_dup;
 532
 533 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
 534         u8 mac_change_fec_en;
 535         u8 rsv[22];
 536 };
 537
 538 #define HCLGE_QUERY_SPEED_S             3
 539 #define HCLGE_QUERY_AN_B                0
 540 #define HCLGE_QUERY_DUPLEX_B            2
 541
 542 #define HCLGE_QUERY_SPEED_M             GENMASK(4, 0)
 543 #define HCLGE_QUERY_AN_M                BIT(HCLGE_QUERY_AN_B)
 544 #define HCLGE_QUERY_DUPLEX_M            BIT(HCLGE_QUERY_DUPLEX_B)
 545
 546 struct hclge_query_an_speed_dup_cmd {
 547         u8 an_syn_dup_speed;
 548         u8 pause;
 549         u8 rsv[23];
 550 };
 551
 552 #define HCLGE_RING_ID_MASK              GENMASK(9, 0)
 553 #define HCLGE_TQP_ENABLE_B              0
 554
 555 #define HCLGE_MAC_CFG_AN_EN_B           0
 556 #define HCLGE_MAC_CFG_AN_INT_EN_B       1
 557 #define HCLGE_MAC_CFG_AN_INT_MSK_B      2
 558 #define HCLGE_MAC_CFG_AN_INT_CLR_B      3
 559 #define HCLGE_MAC_CFG_AN_RST_B          4
 560
 561 #define HCLGE_MAC_CFG_AN_EN     BIT(HCLGE_MAC_CFG_AN_EN_B)
 562
 563 struct hclge_config_auto_neg_cmd {
 564         __le32  cfg_an_cmd_flag;
 565         u8      rsv[20];
 566 };
 567
 568 #define HCLGE_MAC_UPLINK_PORT           0x100
 569
 570 struct hclge_config_max_frm_size_cmd {
 571         __le16  max_frm_size;
 572         u8      rsv[22];
 573 };
 574
 575 enum hclge_mac_vlan_tbl_opcode {
 576         HCLGE_MAC_VLAN_ADD,     /* Add new or modify mac_vlan */
 577         HCLGE_MAC_VLAN_UPDATE,  /* Modify other fields of this table */
 578         HCLGE_MAC_VLAN_REMOVE,  /* Remove a entry through mac_vlan key */
 579         HCLGE_MAC_VLAN_LKUP,    /* Lookup a entry through mac_vlan key */
 580 };
 581
 582 #define HCLGE_MAC_VLAN_BIT0_EN_B        0x0
 583 #define HCLGE_MAC_VLAN_BIT1_EN_B        0x1
 584 #define HCLGE_MAC_EPORT_SW_EN_B         0xc
 585 #define HCLGE_MAC_EPORT_TYPE_B          0xb
 586 #define HCLGE_MAC_EPORT_VFID_S          0x3
 587 #define HCLGE_MAC_EPORT_VFID_M          GENMASK(10, 3)
 588 #define HCLGE_MAC_EPORT_PFID_S          0x0
 589 #define HCLGE_MAC_EPORT_PFID_M          GENMASK(2, 0)
 590 struct hclge_mac_vlan_tbl_entry_cmd {
 591         u8      flags;
 592         u8      resp_code;
 593         __le16  vlan_tag;
 594         __le32  mac_addr_hi32;
 595         __le16  mac_addr_lo16;
 596         __le16  rsv1;
 597         u8      entry_type;
 598         u8      mc_mac_en;
 599         __le16  egress_port;
 600         __le16  egress_queue;
 601         u8      rsv2[6];
 602 };
 603
 604 #define HCLGE_VLAN_MASK_EN_B            0x0
 605 struct hclge_mac_vlan_mask_entry_cmd {
 606         u8 rsv0[2];
 607         u8 vlan_mask;
 608         u8 rsv1;
 609         u8 mac_mask[6];
 610         u8 rsv2[14];
 611 };
 612
 613 #define HCLGE_MAC_MGR_MASK_VLAN_B               BIT(0)
 614 #define HCLGE_MAC_MGR_MASK_MAC_B                BIT(1)
 615 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B          BIT(2)
 616 #define HCLGE_MAC_ETHERTYPE_LLDP                0x88cc
 617
 618 struct hclge_mac_mgr_tbl_entry_cmd {
 619         u8      flags;
 620         u8      resp_code;
 621         __le16  vlan_tag;
 622         __le32  mac_addr_hi32;
 623         __le16  mac_addr_lo16;
 624         __le16  rsv1;
 625         __le16  ethter_type;
 626         __le16  egress_port;
 627         __le16  egress_queue;
 628         u8      sw_port_id_aware;
 629         u8      rsv2;
 630         u8      i_port_bitmap;
 631         u8      i_port_direction;
 632         u8      rsv3[2];
 633 };
 634
 635 #define HCLGE_CFG_MTA_MAC_SEL_S         0x0
 636 #define HCLGE_CFG_MTA_MAC_SEL_M         GENMASK(1, 0)
 637 #define HCLGE_CFG_MTA_MAC_EN_B          0x7
 638 struct hclge_mta_filter_mode_cmd {
 639         u8      dmac_sel_en; /* Use lowest 2 bit as sel_mode, bit 7 as enable */
 640         u8      rsv[23];
 641 };
 642
 643 #define HCLGE_CFG_FUNC_MTA_ACCEPT_B     0x0
 644 struct hclge_cfg_func_mta_filter_cmd {
 645         u8      accept; /* Only used lowest 1 bit */
 646         u8      function_id;
 647         u8      rsv[22];
 648 };
 649
 650 #define HCLGE_CFG_MTA_ITEM_ACCEPT_B     0x0
 651 #define HCLGE_CFG_MTA_ITEM_IDX_S        0x0
 652 #define HCLGE_CFG_MTA_ITEM_IDX_M        GENMASK(11, 0)
 653 struct hclge_cfg_func_mta_item_cmd {
 654         __le16  item_idx; /* Only used lowest 12 bit */
 655         u8      accept;   /* Only used lowest 1 bit */
 656         u8      rsv[21];
 657 };
 658
 659 struct hclge_mac_vlan_add_cmd {
 660         __le16  flags;
 661         __le16  mac_addr_hi16;
 662         __le32  mac_addr_lo32;
 663         __le32  mac_addr_msk_hi32;
 664         __le16  mac_addr_msk_lo16;
 665         __le16  vlan_tag;
 666         __le16  ingress_port;
 667         __le16  egress_port;
 668         u8      rsv[4];
 669 };
 670
 671 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0
 672 struct hclge_mac_vlan_remove_cmd {
 673         __le16  flags;
 674         __le16  mac_addr_hi16;
 675         __le32  mac_addr_lo32;
 676         __le32  mac_addr_msk_hi32;
 677         __le16  mac_addr_msk_lo16;
 678         __le16  vlan_tag;
 679         __le16  ingress_port;
 680         __le16  egress_port;
 681         u8      rsv[4];
 682 };
 683
 684 struct hclge_vlan_filter_ctrl_cmd {
 685         u8 vlan_type;
 686         u8 vlan_fe;
 687         u8 rsv[22];
 688 };
 689
 690 struct hclge_vlan_filter_pf_cfg_cmd {
 691         u8 vlan_offset;
 692         u8 vlan_cfg;
 693         u8 rsv[2];
 694         u8 vlan_offset_bitmap[20];
 695 };
 696
 697 struct hclge_vlan_filter_vf_cfg_cmd {
 698         __le16 vlan_id;
 699         u8  resp_code;
 700         u8  rsv;
 701         u8  vlan_cfg;
 702         u8  rsv1[3];
 703         u8  vf_bitmap[16];
 704 };
 705
 706 #define HCLGE_ACCEPT_TAG1_B             0
 707 #define HCLGE_ACCEPT_UNTAG1_B           1
 708 #define HCLGE_PORT_INS_TAG1_EN_B        2
 709 #define HCLGE_PORT_INS_TAG2_EN_B        3
 710 #define HCLGE_CFG_NIC_ROCE_SEL_B        4
 711 #define HCLGE_ACCEPT_TAG2_B             5
 712 #define HCLGE_ACCEPT_UNTAG2_B           6
 713
 714 struct hclge_vport_vtag_tx_cfg_cmd {
 715         u8 vport_vlan_cfg;
 716         u8 vf_offset;
 717         u8 rsv1[2];
 718         __le16 def_vlan_tag1;
 719         __le16 def_vlan_tag2;
 720         u8 vf_bitmap[8];
 721         u8 rsv2[8];
 722 };
 723
 724 #define HCLGE_REM_TAG1_EN_B             0
 725 #define HCLGE_REM_TAG2_EN_B             1
 726 #define HCLGE_SHOW_TAG1_EN_B            2
 727 #define HCLGE_SHOW_TAG2_EN_B            3
 728 struct hclge_vport_vtag_rx_cfg_cmd {
 729         u8 vport_vlan_cfg;
 730         u8 vf_offset;
 731         u8 rsv1[6];
 732         u8 vf_bitmap[8];
 733         u8 rsv2[8];
 734 };
 735
 736 struct hclge_tx_vlan_type_cfg_cmd {
 737         __le16 ot_vlan_type;
 738         __le16 in_vlan_type;
 739         u8 rsv[20];
 740 };
 741
 742 struct hclge_rx_vlan_type_cfg_cmd {
 743         __le16 ot_fst_vlan_type;
 744         __le16 ot_sec_vlan_type;
 745         __le16 in_fst_vlan_type;
 746         __le16 in_sec_vlan_type;
 747         u8 rsv[16];
 748 };
 749
 750 struct hclge_cfg_com_tqp_queue_cmd {
 751         __le16 tqp_id;
 752         __le16 stream_id;
 753         u8 enable;
 754         u8 rsv[19];
 755 };
 756
 757 struct hclge_cfg_tx_queue_pointer_cmd {
 758         __le16 tqp_id;
 759         __le16 tx_tail;
 760         __le16 tx_head;
 761         __le16 fbd_num;
 762         __le16 ring_offset;
 763         u8 rsv[14];
 764 };
 765
 766 #define HCLGE_TSO_MSS_MIN_S     0
 767 #define HCLGE_TSO_MSS_MIN_M     GENMASK(13, 0)
 768
 769 #define HCLGE_TSO_MSS_MAX_S     16
 770 #define HCLGE_TSO_MSS_MAX_M     GENMASK(29, 16)
 771
 772 struct hclge_cfg_tso_status_cmd {
 773         __le16 tso_mss_min;
 774         __le16 tso_mss_max;
 775         u8 rsv[20];
 776 };
 777
 778 #define HCLGE_TSO_MSS_MIN       256
 779 #define HCLGE_TSO_MSS_MAX       9668
 780
 781 #define HCLGE_TQP_RESET_B       0
 782 struct hclge_reset_tqp_queue_cmd {
 783         __le16 tqp_id;
 784         u8 reset_req;
 785         u8 ready_to_reset;
 786         u8 rsv[20];
 787 };
 788
 789 #define HCLGE_CFG_RESET_MAC_B           3
 790 #define HCLGE_CFG_RESET_FUNC_B          7
 791 struct hclge_reset_cmd {
 792         u8 mac_func_reset;
 793         u8 fun_reset_vfid;
 794         u8 rsv[22];
 795 };
 796
 797 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B    BIT(0)
 798 #define HCLGE_CMD_SERDES_DONE_B                 BIT(0)
 799 #define HCLGE_CMD_SERDES_SUCCESS_B              BIT(1)
 800 struct hclge_serdes_lb_cmd {
 801         u8 mask;
 802         u8 enable;
 803         u8 result;
 804         u8 rsv[21];
 805 };
 806
 807 #define HCLGE_DEFAULT_TX_BUF            0x4000   /* 16k  bytes */
 808 #define HCLGE_TOTAL_PKT_BUF             0x108000 /* 1.03125M bytes */
 809 #define HCLGE_DEFAULT_DV                0xA000   /* 40k byte */
 810 #define HCLGE_DEFAULT_NON_DCB_DV        0x7800  /* 30K byte */
 811
 812 #define HCLGE_TYPE_CRQ                  0
 813 #define HCLGE_TYPE_CSQ                  1
 814 #define HCLGE_NIC_CSQ_BASEADDR_L_REG    0x27000
 815 #define HCLGE_NIC_CSQ_BASEADDR_H_REG    0x27004
 816 #define HCLGE_NIC_CSQ_DEPTH_REG         0x27008
 817 #define HCLGE_NIC_CSQ_TAIL_REG          0x27010
 818 #define HCLGE_NIC_CSQ_HEAD_REG          0x27014
 819 #define HCLGE_NIC_CRQ_BASEADDR_L_REG    0x27018
 820 #define HCLGE_NIC_CRQ_BASEADDR_H_REG    0x2701c
 821 #define HCLGE_NIC_CRQ_DEPTH_REG         0x27020
 822 #define HCLGE_NIC_CRQ_TAIL_REG          0x27024
 823 #define HCLGE_NIC_CRQ_HEAD_REG          0x27028
 824 #define HCLGE_NIC_CMQ_EN_B              16
 825 #define HCLGE_NIC_CMQ_ENABLE            BIT(HCLGE_NIC_CMQ_EN_B)
 826 #define HCLGE_NIC_CMQ_DESC_NUM          1024
 827 #define HCLGE_NIC_CMQ_DESC_NUM_S        3
 828
 829 #define HCLGE_LED_LOCATE_STATE_S        0
 830 #define HCLGE_LED_LOCATE_STATE_M        GENMASK(1, 0)
 831
 832 struct hclge_set_led_state_cmd {
 833         u8 rsv1[3];
 834         u8 locate_led_config;
 835         u8 rsv2[20];
 836 };
 837
 838 int hclge_cmd_init(struct hclge_dev *hdev);
 839 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
 840 {
 841         writel(value, base + reg);
 842 }
 843
 844 #define hclge_write_dev(a, reg, value) \
 845         hclge_write_reg((a)->io_base, (reg), (value))
 846 #define hclge_read_dev(a, reg) \
 847         hclge_read_reg((a)->io_base, (reg))
 848
 849 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg)
 850 {
 851         u8 __iomem *reg_addr = READ_ONCE(base);
 852
 853         return readl(reg_addr + reg);
 854 }
 855
 856 #define HCLGE_SEND_SYNC(flag) \
 857         ((flag) & HCLGE_CMD_FLAG_NO_INTR)
 858
 859 struct hclge_hw;
 860 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num);
 861 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
 862                                 enum hclge_opcode_type opcode, bool is_read);
 863 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
 864
 865 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
 866                                struct hclge_promisc_param *param);
 867
 868 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
 869                                            struct hclge_desc *desc);
 870 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
 871                                           struct hclge_desc *desc);
 872
 873 void hclge_destroy_cmd_queue(struct hclge_hw *hw);
 874 int hclge_cmd_queue_init(struct hclge_dev *hdev);
 875 #endif