drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #ifndef __HCLGE_CMD_H
   5 #define __HCLGE_CMD_H
   6 #include <linux/types.h>
   7 #include <linux/io.h>
   8
   9 #define HCLGE_CMDQ_TX_TIMEOUT           30000
  10
  11 struct hclge_dev;
  12 struct hclge_desc {
  13         __le16 opcode;
  14
  15 #define HCLGE_CMDQ_RX_INVLD_B           0
  16 #define HCLGE_CMDQ_RX_OUTVLD_B          1
  17
  18         __le16 flag;
  19         __le16 retval;
  20         __le16 rsv;
  21         __le32 data[6];
  22 };
  23
  24 struct hclge_cmq_ring {
  25         dma_addr_t desc_dma_addr;
  26         struct hclge_desc *desc;
  27         struct hclge_dev *dev;
  28         u32 head;
  29         u32 tail;
  30
  31         u16 buf_size;
  32         u16 desc_num;
  33         int next_to_use;
  34         int next_to_clean;
  35         u8 ring_type; /* cmq ring type */
  36         spinlock_t lock; /* Command queue lock */
  37 };
  38
  39 enum hclge_cmd_return_status {
  40         HCLGE_CMD_EXEC_SUCCESS  = 0,
  41         HCLGE_CMD_NO_AUTH       = 1,
  42         HCLGE_CMD_NOT_EXEC      = 2,
  43         HCLGE_CMD_QUEUE_FULL    = 3,
  44 };
  45
  46 enum hclge_cmd_status {
  47         HCLGE_STATUS_SUCCESS    = 0,
  48         HCLGE_ERR_CSQ_FULL      = -1,
  49         HCLGE_ERR_CSQ_TIMEOUT   = -2,
  50         HCLGE_ERR_CSQ_ERROR     = -3,
  51 };
  52
  53 struct hclge_misc_vector {
  54         u8 __iomem *addr;
  55         int vector_irq;
  56 };
  57
  58 struct hclge_cmq {
  59         struct hclge_cmq_ring csq;
  60         struct hclge_cmq_ring crq;
  61         u16 tx_timeout;
  62         enum hclge_cmd_status last_status;
  63 };
  64
  65 #define HCLGE_CMD_FLAG_IN       BIT(0)
  66 #define HCLGE_CMD_FLAG_OUT      BIT(1)
  67 #define HCLGE_CMD_FLAG_NEXT     BIT(2)
  68 #define HCLGE_CMD_FLAG_WR       BIT(3)
  69 #define HCLGE_CMD_FLAG_NO_INTR  BIT(4)
  70 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5)
  71
  72 enum hclge_opcode_type {
  73         /* Generic commands */
  74         HCLGE_OPC_QUERY_FW_VER          = 0x0001,
  75         HCLGE_OPC_CFG_RST_TRIGGER       = 0x0020,
  76         HCLGE_OPC_GBL_RST_STATUS        = 0x0021,
  77         HCLGE_OPC_QUERY_FUNC_STATUS     = 0x0022,
  78         HCLGE_OPC_QUERY_PF_RSRC         = 0x0023,
  79         HCLGE_OPC_QUERY_VF_RSRC         = 0x0024,
  80         HCLGE_OPC_GET_CFG_PARAM         = 0x0025,
  81
  82         HCLGE_OPC_STATS_64_BIT          = 0x0030,
  83         HCLGE_OPC_STATS_32_BIT          = 0x0031,
  84         HCLGE_OPC_STATS_MAC             = 0x0032,
  85
  86         HCLGE_OPC_QUERY_REG_NUM         = 0x0040,
  87         HCLGE_OPC_QUERY_32_BIT_REG      = 0x0041,
  88         HCLGE_OPC_QUERY_64_BIT_REG      = 0x0042,
  89         HCLGE_OPC_DFX_BD_NUM            = 0x0043,
  90         HCLGE_OPC_DFX_BIOS_COMMON_REG   = 0x0044,
  91         HCLGE_OPC_DFX_SSU_REG_0         = 0x0045,
  92         HCLGE_OPC_DFX_SSU_REG_1         = 0x0046,
  93         HCLGE_OPC_DFX_IGU_EGU_REG       = 0x0047,
  94         HCLGE_OPC_DFX_RPU_REG_0         = 0x0048,
  95         HCLGE_OPC_DFX_RPU_REG_1         = 0x0049,
  96         HCLGE_OPC_DFX_NCSI_REG          = 0x004A,
  97         HCLGE_OPC_DFX_RTC_REG           = 0x004B,
  98         HCLGE_OPC_DFX_PPP_REG           = 0x004C,
  99         HCLGE_OPC_DFX_RCB_REG           = 0x004D,
 100         HCLGE_OPC_DFX_TQP_REG           = 0x004E,
 101         HCLGE_OPC_DFX_SSU_REG_2         = 0x004F,
 102         HCLGE_OPC_DFX_QUERY_CHIP_CAP    = 0x0050,
 103
 104         /* MAC command */
 105         HCLGE_OPC_CONFIG_MAC_MODE       = 0x0301,
 106         HCLGE_OPC_CONFIG_AN_MODE        = 0x0304,
 107         HCLGE_OPC_QUERY_AN_RESULT       = 0x0306,
 108         HCLGE_OPC_QUERY_LINK_STATUS     = 0x0307,
 109         HCLGE_OPC_CONFIG_MAX_FRM_SIZE   = 0x0308,
 110         HCLGE_OPC_CONFIG_SPEED_DUP      = 0x0309,
 111         HCLGE_OPC_SERDES_LOOPBACK       = 0x0315,
 112
 113         /* PFC/Pause commands */
 114         HCLGE_OPC_CFG_MAC_PAUSE_EN      = 0x0701,
 115         HCLGE_OPC_CFG_PFC_PAUSE_EN      = 0x0702,
 116         HCLGE_OPC_CFG_MAC_PARA          = 0x0703,
 117         HCLGE_OPC_CFG_PFC_PARA          = 0x0704,
 118         HCLGE_OPC_QUERY_MAC_TX_PKT_CNT  = 0x0705,
 119         HCLGE_OPC_QUERY_MAC_RX_PKT_CNT  = 0x0706,
 120         HCLGE_OPC_QUERY_PFC_TX_PKT_CNT  = 0x0707,
 121         HCLGE_OPC_QUERY_PFC_RX_PKT_CNT  = 0x0708,
 122         HCLGE_OPC_PRI_TO_TC_MAPPING     = 0x0709,
 123         HCLGE_OPC_QOS_MAP               = 0x070A,
 124
 125         /* ETS/scheduler commands */
 126         HCLGE_OPC_TM_PG_TO_PRI_LINK     = 0x0804,
 127         HCLGE_OPC_TM_QS_TO_PRI_LINK     = 0x0805,
 128         HCLGE_OPC_TM_NQ_TO_QS_LINK      = 0x0806,
 129         HCLGE_OPC_TM_RQ_TO_QS_LINK      = 0x0807,
 130         HCLGE_OPC_TM_PORT_WEIGHT        = 0x0808,
 131         HCLGE_OPC_TM_PG_WEIGHT          = 0x0809,
 132         HCLGE_OPC_TM_QS_WEIGHT          = 0x080A,
 133         HCLGE_OPC_TM_PRI_WEIGHT         = 0x080B,
 134         HCLGE_OPC_TM_PRI_C_SHAPPING     = 0x080C,
 135         HCLGE_OPC_TM_PRI_P_SHAPPING     = 0x080D,
 136         HCLGE_OPC_TM_PG_C_SHAPPING      = 0x080E,
 137         HCLGE_OPC_TM_PG_P_SHAPPING      = 0x080F,
 138         HCLGE_OPC_TM_PORT_SHAPPING      = 0x0810,
 139         HCLGE_OPC_TM_PG_SCH_MODE_CFG    = 0x0812,
 140         HCLGE_OPC_TM_PRI_SCH_MODE_CFG   = 0x0813,
 141         HCLGE_OPC_TM_QS_SCH_MODE_CFG    = 0x0814,
 142         HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
 143         HCLGE_OPC_ETS_TC_WEIGHT         = 0x0843,
 144         HCLGE_OPC_QSET_DFX_STS          = 0x0844,
 145         HCLGE_OPC_PRI_DFX_STS           = 0x0845,
 146         HCLGE_OPC_PG_DFX_STS            = 0x0846,
 147         HCLGE_OPC_PORT_DFX_STS          = 0x0847,
 148         HCLGE_OPC_SCH_NQ_CNT            = 0x0848,
 149         HCLGE_OPC_SCH_RQ_CNT            = 0x0849,
 150         HCLGE_OPC_TM_INTERNAL_STS       = 0x0850,
 151         HCLGE_OPC_TM_INTERNAL_CNT       = 0x0851,
 152         HCLGE_OPC_TM_INTERNAL_STS_1     = 0x0852,
 153
 154         /* Packet buffer allocate commands */
 155         HCLGE_OPC_TX_BUFF_ALLOC         = 0x0901,
 156         HCLGE_OPC_RX_PRIV_BUFF_ALLOC    = 0x0902,
 157         HCLGE_OPC_RX_PRIV_WL_ALLOC      = 0x0903,
 158         HCLGE_OPC_RX_COM_THRD_ALLOC     = 0x0904,
 159         HCLGE_OPC_RX_COM_WL_ALLOC       = 0x0905,
 160         HCLGE_OPC_RX_GBL_PKT_CNT        = 0x0906,
 161
 162         /* TQP management command */
 163         HCLGE_OPC_SET_TQP_MAP           = 0x0A01,
 164
 165         /* TQP commands */
 166         HCLGE_OPC_CFG_TX_QUEUE          = 0x0B01,
 167         HCLGE_OPC_QUERY_TX_POINTER      = 0x0B02,
 168         HCLGE_OPC_QUERY_TX_STATUS       = 0x0B03,
 169         HCLGE_OPC_TQP_TX_QUEUE_TC       = 0x0B04,
 170         HCLGE_OPC_CFG_RX_QUEUE          = 0x0B11,
 171         HCLGE_OPC_QUERY_RX_POINTER      = 0x0B12,
 172         HCLGE_OPC_QUERY_RX_STATUS       = 0x0B13,
 173         HCLGE_OPC_STASH_RX_QUEUE_LRO    = 0x0B16,
 174         HCLGE_OPC_CFG_RX_QUEUE_LRO      = 0x0B17,
 175         HCLGE_OPC_CFG_COM_TQP_QUEUE     = 0x0B20,
 176         HCLGE_OPC_RESET_TQP_QUEUE       = 0x0B22,
 177
 178         /* TSO command */
 179         HCLGE_OPC_TSO_GENERIC_CONFIG    = 0x0C01,
 180         HCLGE_OPC_GRO_GENERIC_CONFIG    = 0x0C10,
 181
 182         /* RSS commands */
 183         HCLGE_OPC_RSS_GENERIC_CONFIG    = 0x0D01,
 184         HCLGE_OPC_RSS_INDIR_TABLE       = 0x0D07,
 185         HCLGE_OPC_RSS_TC_MODE           = 0x0D08,
 186         HCLGE_OPC_RSS_INPUT_TUPLE       = 0x0D02,
 187
 188         /* Promisuous mode command */
 189         HCLGE_OPC_CFG_PROMISC_MODE      = 0x0E01,
 190
 191         /* Vlan offload commands */
 192         HCLGE_OPC_VLAN_PORT_TX_CFG      = 0x0F01,
 193         HCLGE_OPC_VLAN_PORT_RX_CFG      = 0x0F02,
 194
 195         /* Interrupts commands */
 196         HCLGE_OPC_ADD_RING_TO_VECTOR    = 0x1503,
 197         HCLGE_OPC_DEL_RING_TO_VECTOR    = 0x1504,
 198
 199         /* MAC commands */
 200         HCLGE_OPC_MAC_VLAN_ADD              = 0x1000,
 201         HCLGE_OPC_MAC_VLAN_REMOVE           = 0x1001,
 202         HCLGE_OPC_MAC_VLAN_TYPE_ID          = 0x1002,
 203         HCLGE_OPC_MAC_VLAN_INSERT           = 0x1003,
 204         HCLGE_OPC_MAC_VLAN_ALLOCATE         = 0x1004,
 205         HCLGE_OPC_MAC_ETHTYPE_ADD           = 0x1010,
 206         HCLGE_OPC_MAC_ETHTYPE_REMOVE    = 0x1011,
 207
 208         /* VLAN commands */
 209         HCLGE_OPC_VLAN_FILTER_CTRL          = 0x1100,
 210         HCLGE_OPC_VLAN_FILTER_PF_CFG    = 0x1101,
 211         HCLGE_OPC_VLAN_FILTER_VF_CFG    = 0x1102,
 212
 213         /* Flow Director commands */
 214         HCLGE_OPC_FD_MODE_CTRL          = 0x1200,
 215         HCLGE_OPC_FD_GET_ALLOCATION     = 0x1201,
 216         HCLGE_OPC_FD_KEY_CONFIG         = 0x1202,
 217         HCLGE_OPC_FD_TCAM_OP            = 0x1203,
 218         HCLGE_OPC_FD_AD_OP              = 0x1204,
 219
 220         /* MDIO command */
 221         HCLGE_OPC_MDIO_CONFIG           = 0x1900,
 222
 223         /* QCN commands */
 224         HCLGE_OPC_QCN_MOD_CFG           = 0x1A01,
 225         HCLGE_OPC_QCN_GRP_TMPLT_CFG     = 0x1A02,
 226         HCLGE_OPC_QCN_SHAPPING_IR_CFG   = 0x1A03,
 227         HCLGE_OPC_QCN_SHAPPING_BS_CFG   = 0x1A04,
 228         HCLGE_OPC_QCN_QSET_LINK_CFG     = 0x1A05,
 229         HCLGE_OPC_QCN_RP_STATUS_GET     = 0x1A06,
 230         HCLGE_OPC_QCN_AJUST_INIT        = 0x1A07,
 231         HCLGE_OPC_QCN_DFX_CNT_STATUS    = 0x1A08,
 232
 233         /* Mailbox command */
 234         HCLGEVF_OPC_MBX_PF_TO_VF        = 0x2000,
 235
 236         /* Led command */
 237         HCLGE_OPC_LED_STATUS_CFG        = 0xB000,
 238
 239         /* Error INT commands */
 240         HCLGE_MAC_COMMON_INT_EN         = 0x030E,
 241         HCLGE_TM_SCH_ECC_INT_EN         = 0x0829,
 242         HCLGE_SSU_ECC_INT_CMD           = 0x0989,
 243         HCLGE_SSU_COMMON_INT_CMD        = 0x098C,
 244         HCLGE_PPU_MPF_ECC_INT_CMD       = 0x0B40,
 245         HCLGE_PPU_MPF_OTHER_INT_CMD     = 0x0B41,
 246         HCLGE_PPU_PF_OTHER_INT_CMD      = 0x0B42,
 247         HCLGE_COMMON_ECC_INT_CFG        = 0x1505,
 248         HCLGE_QUERY_RAS_INT_STS_BD_NUM  = 0x1510,
 249         HCLGE_QUERY_CLEAR_MPF_RAS_INT   = 0x1511,
 250         HCLGE_QUERY_CLEAR_PF_RAS_INT    = 0x1512,
 251         HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
 252         HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT      = 0x1514,
 253         HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT       = 0x1515,
 254         HCLGE_CONFIG_ROCEE_RAS_INT_EN   = 0x1580,
 255         HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
 256         HCLGE_ROCEE_PF_RAS_INT_CMD      = 0x1584,
 257         HCLGE_IGU_EGU_TNL_INT_EN        = 0x1803,
 258         HCLGE_IGU_COMMON_INT_EN         = 0x1806,
 259         HCLGE_TM_QCN_MEM_INT_CFG        = 0x1A14,
 260         HCLGE_PPP_CMD0_INT_CMD          = 0x2100,
 261         HCLGE_PPP_CMD1_INT_CMD          = 0x2101,
 262         HCLGE_MAC_ETHERTYPE_IDX_RD      = 0x2105,
 263         HCLGE_NCSI_INT_EN               = 0x2401,
 264 };
 265
 266 #define HCLGE_TQP_REG_OFFSET            0x80000
 267 #define HCLGE_TQP_REG_SIZE              0x200
 268
 269 #define HCLGE_RCB_INIT_QUERY_TIMEOUT    10
 270 #define HCLGE_RCB_INIT_FLAG_EN_B        0
 271 #define HCLGE_RCB_INIT_FLAG_FINI_B      8
 272 struct hclge_config_rcb_init_cmd {
 273         __le16 rcb_init_flag;
 274         u8 rsv[22];
 275 };
 276
 277 struct hclge_tqp_map_cmd {
 278         __le16 tqp_id;  /* Absolute tqp id for in this pf */
 279         u8 tqp_vf;      /* VF id */
 280 #define HCLGE_TQP_MAP_TYPE_PF           0
 281 #define HCLGE_TQP_MAP_TYPE_VF           1
 282 #define HCLGE_TQP_MAP_TYPE_B            0
 283 #define HCLGE_TQP_MAP_EN_B              1
 284         u8 tqp_flag;    /* Indicate it's pf or vf tqp */
 285         __le16 tqp_vid; /* Virtual id in this pf/vf */
 286         u8 rsv[18];
 287 };
 288
 289 #define HCLGE_VECTOR_ELEMENTS_PER_CMD   10
 290
 291 enum hclge_int_type {
 292         HCLGE_INT_TX,
 293         HCLGE_INT_RX,
 294         HCLGE_INT_EVENT,
 295 };
 296
 297 struct hclge_ctrl_vector_chain_cmd {
 298         u8 int_vector_id;
 299         u8 int_cause_num;
 300 #define HCLGE_INT_TYPE_S        0
 301 #define HCLGE_INT_TYPE_M        GENMASK(1, 0)
 302 #define HCLGE_TQP_ID_S          2
 303 #define HCLGE_TQP_ID_M          GENMASK(12, 2)
 304 #define HCLGE_INT_GL_IDX_S      13
 305 #define HCLGE_INT_GL_IDX_M      GENMASK(14, 13)
 306         __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];
 307         u8 vfid;
 308         u8 rsv;
 309 };
 310
 311 #define HCLGE_TC_NUM            8
 312 #define HCLGE_TC0_PRI_BUF_EN_B  15 /* Bit 15 indicate enable or not */
 313 #define HCLGE_BUF_UNIT_S        7  /* Buf size is united by 128 bytes */
 314 struct hclge_tx_buff_alloc_cmd {
 315         __le16 tx_pkt_buff[HCLGE_TC_NUM];
 316         u8 tx_buff_rsv[8];
 317 };
 318
 319 struct hclge_rx_priv_buff_cmd {
 320         __le16 buf_num[HCLGE_TC_NUM];
 321         __le16 shared_buf;
 322         u8 rsv[6];
 323 };
 324
 325 struct hclge_query_version_cmd {
 326         __le32 firmware;
 327         __le32 firmware_rsv[5];
 328 };
 329
 330 #define HCLGE_RX_PRIV_EN_B      15
 331 #define HCLGE_TC_NUM_ONE_DESC   4
 332 struct hclge_priv_wl {
 333         __le16 high;
 334         __le16 low;
 335 };
 336
 337 struct hclge_rx_priv_wl_buf {
 338         struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC];
 339 };
 340
 341 struct hclge_rx_com_thrd {
 342         struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC];
 343 };
 344
 345 struct hclge_rx_com_wl {
 346         struct hclge_priv_wl com_wl;
 347 };
 348
 349 struct hclge_waterline {
 350         u32 low;
 351         u32 high;
 352 };
 353
 354 struct hclge_tc_thrd {
 355         u32 low;
 356         u32 high;
 357 };
 358
 359 struct hclge_priv_buf {
 360         struct hclge_waterline wl;      /* Waterline for low and high*/
 361         u32 buf_size;   /* TC private buffer size */
 362         u32 tx_buf_size;
 363         u32 enable;     /* Enable TC private buffer or not */
 364 };
 365
 366 #define HCLGE_MAX_TC_NUM        8
 367 struct hclge_shared_buf {
 368         struct hclge_waterline self;
 369         struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM];
 370         u32 buf_size;
 371 };
 372
 373 struct hclge_pkt_buf_alloc {
 374         struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM];
 375         struct hclge_shared_buf s_buf;
 376 };
 377
 378 #define HCLGE_RX_COM_WL_EN_B    15
 379 struct hclge_rx_com_wl_buf_cmd {
 380         __le16 high_wl;
 381         __le16 low_wl;
 382         u8 rsv[20];
 383 };
 384
 385 #define HCLGE_RX_PKT_EN_B       15
 386 struct hclge_rx_pkt_buf_cmd {
 387         __le16 high_pkt;
 388         __le16 low_pkt;
 389         u8 rsv[20];
 390 };
 391
 392 #define HCLGE_PF_STATE_DONE_B   0
 393 #define HCLGE_PF_STATE_MAIN_B   1
 394 #define HCLGE_PF_STATE_BOND_B   2
 395 #define HCLGE_PF_STATE_MAC_N_B  6
 396 #define HCLGE_PF_MAC_NUM_MASK   0x3
 397 #define HCLGE_PF_STATE_MAIN     BIT(HCLGE_PF_STATE_MAIN_B)
 398 #define HCLGE_PF_STATE_DONE     BIT(HCLGE_PF_STATE_DONE_B)
 399 struct hclge_func_status_cmd {
 400         __le32  vf_rst_state[4];
 401         u8 pf_state;
 402         u8 mac_id;
 403         u8 rsv1;
 404         u8 pf_cnt_in_mac;
 405         u8 pf_num;
 406         u8 vf_num;
 407         u8 rsv[2];
 408 };
 409
 410 struct hclge_pf_res_cmd {
 411         __le16 tqp_num;
 412         __le16 buf_size;
 413         __le16 msixcap_localid_ba_nic;
 414         __le16 msixcap_localid_ba_rocee;
 415 #define HCLGE_MSIX_OFT_ROCEE_S          0
 416 #define HCLGE_MSIX_OFT_ROCEE_M          GENMASK(15, 0)
 417 #define HCLGE_PF_VEC_NUM_S              0
 418 #define HCLGE_PF_VEC_NUM_M              GENMASK(7, 0)
 419         __le16 pf_intr_vector_number;
 420         __le16 pf_own_fun_number;
 421         __le32 rsv[3];
 422 };
 423
 424 #define HCLGE_CFG_OFFSET_S      0
 425 #define HCLGE_CFG_OFFSET_M      GENMASK(19, 0)
 426 #define HCLGE_CFG_RD_LEN_S      24
 427 #define HCLGE_CFG_RD_LEN_M      GENMASK(27, 24)
 428 #define HCLGE_CFG_RD_LEN_BYTES  16
 429 #define HCLGE_CFG_RD_LEN_UNIT   4
 430
 431 #define HCLGE_CFG_VMDQ_S        0
 432 #define HCLGE_CFG_VMDQ_M        GENMASK(7, 0)
 433 #define HCLGE_CFG_TC_NUM_S      8
 434 #define HCLGE_CFG_TC_NUM_M      GENMASK(15, 8)
 435 #define HCLGE_CFG_TQP_DESC_N_S  16
 436 #define HCLGE_CFG_TQP_DESC_N_M  GENMASK(31, 16)
 437 #define HCLGE_CFG_PHY_ADDR_S    0
 438 #define HCLGE_CFG_PHY_ADDR_M    GENMASK(7, 0)
 439 #define HCLGE_CFG_MEDIA_TP_S    8
 440 #define HCLGE_CFG_MEDIA_TP_M    GENMASK(15, 8)
 441 #define HCLGE_CFG_RX_BUF_LEN_S  16
 442 #define HCLGE_CFG_RX_BUF_LEN_M  GENMASK(31, 16)
 443 #define HCLGE_CFG_MAC_ADDR_H_S  0
 444 #define HCLGE_CFG_MAC_ADDR_H_M  GENMASK(15, 0)
 445 #define HCLGE_CFG_DEFAULT_SPEED_S       16
 446 #define HCLGE_CFG_DEFAULT_SPEED_M       GENMASK(23, 16)
 447 #define HCLGE_CFG_RSS_SIZE_S    24
 448 #define HCLGE_CFG_RSS_SIZE_M    GENMASK(31, 24)
 449 #define HCLGE_CFG_SPEED_ABILITY_S       0
 450 #define HCLGE_CFG_SPEED_ABILITY_M       GENMASK(7, 0)
 451 #define HCLGE_CFG_UMV_TBL_SPACE_S       16
 452 #define HCLGE_CFG_UMV_TBL_SPACE_M       GENMASK(31, 16)
 453
 454 struct hclge_cfg_param_cmd {
 455         __le32 offset;
 456         __le32 rsv;
 457         __le32 param[4];
 458 };
 459
 460 #define HCLGE_MAC_MODE          0x0
 461 #define HCLGE_DESC_NUM          0x40
 462
 463 #define HCLGE_ALLOC_VALID_B     0
 464 struct hclge_vf_num_cmd {
 465         u8 alloc_valid;
 466         u8 rsv[23];
 467 };
 468
 469 #define HCLGE_RSS_DEFAULT_OUTPORT_B     4
 470 #define HCLGE_RSS_HASH_KEY_OFFSET_B     4
 471 #define HCLGE_RSS_HASH_KEY_NUM          16
 472 struct hclge_rss_config_cmd {
 473         u8 hash_config;
 474         u8 rsv[7];
 475         u8 hash_key[HCLGE_RSS_HASH_KEY_NUM];
 476 };
 477
 478 struct hclge_rss_input_tuple_cmd {
 479         u8 ipv4_tcp_en;
 480         u8 ipv4_udp_en;
 481         u8 ipv4_sctp_en;
 482         u8 ipv4_fragment_en;
 483         u8 ipv6_tcp_en;
 484         u8 ipv6_udp_en;
 485         u8 ipv6_sctp_en;
 486         u8 ipv6_fragment_en;
 487         u8 rsv[16];
 488 };
 489
 490 #define HCLGE_RSS_CFG_TBL_SIZE  16
 491
 492 struct hclge_rss_indirection_table_cmd {
 493         __le16 start_table_index;
 494         __le16 rss_set_bitmap;
 495         u8 rsv[4];
 496         u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE];
 497 };
 498
 499 #define HCLGE_RSS_TC_OFFSET_S           0
 500 #define HCLGE_RSS_TC_OFFSET_M           GENMASK(9, 0)
 501 #define HCLGE_RSS_TC_SIZE_S             12
 502 #define HCLGE_RSS_TC_SIZE_M             GENMASK(14, 12)
 503 #define HCLGE_RSS_TC_VALID_B            15
 504 struct hclge_rss_tc_mode_cmd {
 505         __le16 rss_tc_mode[HCLGE_MAX_TC_NUM];
 506         u8 rsv[8];
 507 };
 508
 509 #define HCLGE_LINK_STATUS_UP_B  0
 510 #define HCLGE_LINK_STATUS_UP_M  BIT(HCLGE_LINK_STATUS_UP_B)
 511 struct hclge_link_status_cmd {
 512         u8 status;
 513         u8 rsv[23];
 514 };
 515
 516 struct hclge_promisc_param {
 517         u8 vf_id;
 518         u8 enable;
 519 };
 520
 521 #define HCLGE_PROMISC_TX_EN_B   BIT(4)
 522 #define HCLGE_PROMISC_RX_EN_B   BIT(5)
 523 #define HCLGE_PROMISC_EN_B      1
 524 #define HCLGE_PROMISC_EN_ALL    0x7
 525 #define HCLGE_PROMISC_EN_UC     0x1
 526 #define HCLGE_PROMISC_EN_MC     0x2
 527 #define HCLGE_PROMISC_EN_BC     0x4
 528 struct hclge_promisc_cfg_cmd {
 529         u8 flag;
 530         u8 vf_id;
 531         __le16 rsv0;
 532         u8 rsv1[20];
 533 };
 534
 535 enum hclge_promisc_type {
 536         HCLGE_UNICAST   = 1,
 537         HCLGE_MULTICAST = 2,
 538         HCLGE_BROADCAST = 3,
 539 };
 540
 541 #define HCLGE_MAC_TX_EN_B       6
 542 #define HCLGE_MAC_RX_EN_B       7
 543 #define HCLGE_MAC_PAD_TX_B      11
 544 #define HCLGE_MAC_PAD_RX_B      12
 545 #define HCLGE_MAC_1588_TX_B     13
 546 #define HCLGE_MAC_1588_RX_B     14
 547 #define HCLGE_MAC_APP_LP_B      15
 548 #define HCLGE_MAC_LINE_LP_B     16
 549 #define HCLGE_MAC_FCS_TX_B      17
 550 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B        18
 551 #define HCLGE_MAC_RX_FCS_STRIP_B        19
 552 #define HCLGE_MAC_RX_FCS_B      20
 553 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B            21
 554 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B        22
 555
 556 struct hclge_config_mac_mode_cmd {
 557         __le32 txrx_pad_fcs_loop_en;
 558         u8 rsv[20];
 559 };
 560
 561 #define HCLGE_CFG_SPEED_S               0
 562 #define HCLGE_CFG_SPEED_M               GENMASK(5, 0)
 563
 564 #define HCLGE_CFG_DUPLEX_B              7
 565 #define HCLGE_CFG_DUPLEX_M              BIT(HCLGE_CFG_DUPLEX_B)
 566
 567 struct hclge_config_mac_speed_dup_cmd {
 568         u8 speed_dup;
 569
 570 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
 571         u8 mac_change_fec_en;
 572         u8 rsv[22];
 573 };
 574
 575 #define HCLGE_QUERY_SPEED_S             3
 576 #define HCLGE_QUERY_AN_B                0
 577 #define HCLGE_QUERY_DUPLEX_B            2
 578
 579 #define HCLGE_QUERY_SPEED_M             GENMASK(4, 0)
 580 #define HCLGE_QUERY_AN_M                BIT(HCLGE_QUERY_AN_B)
 581 #define HCLGE_QUERY_DUPLEX_M            BIT(HCLGE_QUERY_DUPLEX_B)
 582
 583 struct hclge_query_an_speed_dup_cmd {
 584         u8 an_syn_dup_speed;
 585         u8 pause;
 586         u8 rsv[23];
 587 };
 588
 589 #define HCLGE_RING_ID_MASK              GENMASK(9, 0)
 590 #define HCLGE_TQP_ENABLE_B              0
 591
 592 #define HCLGE_MAC_CFG_AN_EN_B           0
 593 #define HCLGE_MAC_CFG_AN_INT_EN_B       1
 594 #define HCLGE_MAC_CFG_AN_INT_MSK_B      2
 595 #define HCLGE_MAC_CFG_AN_INT_CLR_B      3
 596 #define HCLGE_MAC_CFG_AN_RST_B          4
 597
 598 #define HCLGE_MAC_CFG_AN_EN     BIT(HCLGE_MAC_CFG_AN_EN_B)
 599
 600 struct hclge_config_auto_neg_cmd {
 601         __le32  cfg_an_cmd_flag;
 602         u8      rsv[20];
 603 };
 604
 605 #define HCLGE_MAC_UPLINK_PORT           0x100
 606
 607 struct hclge_config_max_frm_size_cmd {
 608         __le16  max_frm_size;
 609         u8      min_frm_size;
 610         u8      rsv[21];
 611 };
 612
 613 enum hclge_mac_vlan_tbl_opcode {
 614         HCLGE_MAC_VLAN_ADD,     /* Add new or modify mac_vlan */
 615         HCLGE_MAC_VLAN_UPDATE,  /* Modify other fields of this table */
 616         HCLGE_MAC_VLAN_REMOVE,  /* Remove a entry through mac_vlan key */
 617         HCLGE_MAC_VLAN_LKUP,    /* Lookup a entry through mac_vlan key */
 618 };
 619
 620 #define HCLGE_MAC_VLAN_BIT0_EN_B        0
 621 #define HCLGE_MAC_VLAN_BIT1_EN_B        1
 622 #define HCLGE_MAC_EPORT_SW_EN_B         12
 623 #define HCLGE_MAC_EPORT_TYPE_B          11
 624 #define HCLGE_MAC_EPORT_VFID_S          3
 625 #define HCLGE_MAC_EPORT_VFID_M          GENMASK(10, 3)
 626 #define HCLGE_MAC_EPORT_PFID_S          0
 627 #define HCLGE_MAC_EPORT_PFID_M          GENMASK(2, 0)
 628 struct hclge_mac_vlan_tbl_entry_cmd {
 629         u8      flags;
 630         u8      resp_code;
 631         __le16  vlan_tag;
 632         __le32  mac_addr_hi32;
 633         __le16  mac_addr_lo16;
 634         __le16  rsv1;
 635         u8      entry_type;
 636         u8      mc_mac_en;
 637         __le16  egress_port;
 638         __le16  egress_queue;
 639         u8      rsv2[6];
 640 };
 641
 642 #define HCLGE_UMV_SPC_ALC_B     0
 643 struct hclge_umv_spc_alc_cmd {
 644         u8 allocate;
 645         u8 rsv1[3];
 646         __le32 space_size;
 647         u8 rsv2[16];
 648 };
 649
 650 #define HCLGE_MAC_MGR_MASK_VLAN_B               BIT(0)
 651 #define HCLGE_MAC_MGR_MASK_MAC_B                BIT(1)
 652 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B          BIT(2)
 653 #define HCLGE_MAC_ETHERTYPE_LLDP                0x88cc
 654
 655 struct hclge_mac_mgr_tbl_entry_cmd {
 656         u8      flags;
 657         u8      resp_code;
 658         __le16  vlan_tag;
 659         __le32  mac_addr_hi32;
 660         __le16  mac_addr_lo16;
 661         __le16  rsv1;
 662         __le16  ethter_type;
 663         __le16  egress_port;
 664         __le16  egress_queue;
 665         u8      sw_port_id_aware;
 666         u8      rsv2;
 667         u8      i_port_bitmap;
 668         u8      i_port_direction;
 669         u8      rsv3[2];
 670 };
 671
 672 struct hclge_mac_vlan_add_cmd {
 673         __le16  flags;
 674         __le16  mac_addr_hi16;
 675         __le32  mac_addr_lo32;
 676         __le32  mac_addr_msk_hi32;
 677         __le16  mac_addr_msk_lo16;
 678         __le16  vlan_tag;
 679         __le16  ingress_port;
 680         __le16  egress_port;
 681         u8      rsv[4];
 682 };
 683
 684 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0
 685 struct hclge_mac_vlan_remove_cmd {
 686         __le16  flags;
 687         __le16  mac_addr_hi16;
 688         __le32  mac_addr_lo32;
 689         __le32  mac_addr_msk_hi32;
 690         __le16  mac_addr_msk_lo16;
 691         __le16  vlan_tag;
 692         __le16  ingress_port;
 693         __le16  egress_port;
 694         u8      rsv[4];
 695 };
 696
 697 struct hclge_vlan_filter_ctrl_cmd {
 698         u8 vlan_type;
 699         u8 vlan_fe;
 700         u8 rsv[22];
 701 };
 702
 703 struct hclge_vlan_filter_pf_cfg_cmd {
 704         u8 vlan_offset;
 705         u8 vlan_cfg;
 706         u8 rsv[2];
 707         u8 vlan_offset_bitmap[20];
 708 };
 709
 710 struct hclge_vlan_filter_vf_cfg_cmd {
 711         __le16 vlan_id;
 712         u8  resp_code;
 713         u8  rsv;
 714         u8  vlan_cfg;
 715         u8  rsv1[3];
 716         u8  vf_bitmap[16];
 717 };
 718
 719 #define HCLGE_ACCEPT_TAG1_B             0
 720 #define HCLGE_ACCEPT_UNTAG1_B           1
 721 #define HCLGE_PORT_INS_TAG1_EN_B        2
 722 #define HCLGE_PORT_INS_TAG2_EN_B        3
 723 #define HCLGE_CFG_NIC_ROCE_SEL_B        4
 724 #define HCLGE_ACCEPT_TAG2_B             5
 725 #define HCLGE_ACCEPT_UNTAG2_B           6
 726
 727 struct hclge_vport_vtag_tx_cfg_cmd {
 728         u8 vport_vlan_cfg;
 729         u8 vf_offset;
 730         u8 rsv1[2];
 731         __le16 def_vlan_tag1;
 732         __le16 def_vlan_tag2;
 733         u8 vf_bitmap[8];
 734         u8 rsv2[8];
 735 };
 736
 737 #define HCLGE_REM_TAG1_EN_B             0
 738 #define HCLGE_REM_TAG2_EN_B             1
 739 #define HCLGE_SHOW_TAG1_EN_B            2
 740 #define HCLGE_SHOW_TAG2_EN_B            3
 741 struct hclge_vport_vtag_rx_cfg_cmd {
 742         u8 vport_vlan_cfg;
 743         u8 vf_offset;
 744         u8 rsv1[6];
 745         u8 vf_bitmap[8];
 746         u8 rsv2[8];
 747 };
 748
 749 struct hclge_tx_vlan_type_cfg_cmd {
 750         __le16 ot_vlan_type;
 751         __le16 in_vlan_type;
 752         u8 rsv[20];
 753 };
 754
 755 struct hclge_rx_vlan_type_cfg_cmd {
 756         __le16 ot_fst_vlan_type;
 757         __le16 ot_sec_vlan_type;
 758         __le16 in_fst_vlan_type;
 759         __le16 in_sec_vlan_type;
 760         u8 rsv[16];
 761 };
 762
 763 struct hclge_cfg_com_tqp_queue_cmd {
 764         __le16 tqp_id;
 765         __le16 stream_id;
 766         u8 enable;
 767         u8 rsv[19];
 768 };
 769
 770 struct hclge_cfg_tx_queue_pointer_cmd {
 771         __le16 tqp_id;
 772         __le16 tx_tail;
 773         __le16 tx_head;
 774         __le16 fbd_num;
 775         __le16 ring_offset;
 776         u8 rsv[14];
 777 };
 778
 779 #pragma pack(1)
 780 struct hclge_mac_ethertype_idx_rd_cmd {
 781         u8      flags;
 782         u8      resp_code;
 783         __le16  vlan_tag;
 784         u8      mac_add[6];
 785         __le16  index;
 786         __le16  ethter_type;
 787         __le16  egress_port;
 788         __le16  egress_queue;
 789         __le16  rev0;
 790         u8      i_port_bitmap;
 791         u8      i_port_direction;
 792         u8      rev1[2];
 793 };
 794
 795 #pragma pack()
 796
 797 #define HCLGE_TSO_MSS_MIN_S     0
 798 #define HCLGE_TSO_MSS_MIN_M     GENMASK(13, 0)
 799
 800 #define HCLGE_TSO_MSS_MAX_S     16
 801 #define HCLGE_TSO_MSS_MAX_M     GENMASK(29, 16)
 802
 803 struct hclge_cfg_tso_status_cmd {
 804         __le16 tso_mss_min;
 805         __le16 tso_mss_max;
 806         u8 rsv[20];
 807 };
 808
 809 #define HCLGE_GRO_EN_B          0
 810 struct hclge_cfg_gro_status_cmd {
 811         __le16 gro_en;
 812         u8 rsv[22];
 813 };
 814
 815 #define HCLGE_TSO_MSS_MIN       256
 816 #define HCLGE_TSO_MSS_MAX       9668
 817
 818 #define HCLGE_TQP_RESET_B       0
 819 struct hclge_reset_tqp_queue_cmd {
 820         __le16 tqp_id;
 821         u8 reset_req;
 822         u8 ready_to_reset;
 823         u8 rsv[20];
 824 };
 825
 826 #define HCLGE_CFG_RESET_MAC_B           3
 827 #define HCLGE_CFG_RESET_FUNC_B          7
 828 struct hclge_reset_cmd {
 829         u8 mac_func_reset;
 830         u8 fun_reset_vfid;
 831         u8 rsv[22];
 832 };
 833
 834 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B    BIT(0)
 835 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B  BIT(2)
 836 #define HCLGE_CMD_SERDES_DONE_B                 BIT(0)
 837 #define HCLGE_CMD_SERDES_SUCCESS_B              BIT(1)
 838 struct hclge_serdes_lb_cmd {
 839         u8 mask;
 840         u8 enable;
 841         u8 result;
 842         u8 rsv[21];
 843 };
 844
 845 #define HCLGE_DEFAULT_TX_BUF            0x4000   /* 16k  bytes */
 846 #define HCLGE_TOTAL_PKT_BUF             0x108000 /* 1.03125M bytes */
 847 #define HCLGE_DEFAULT_DV                0xA000   /* 40k byte */
 848 #define HCLGE_DEFAULT_NON_DCB_DV        0x7800  /* 30K byte */
 849
 850 #define HCLGE_TYPE_CRQ                  0
 851 #define HCLGE_TYPE_CSQ                  1
 852 #define HCLGE_NIC_CSQ_BASEADDR_L_REG    0x27000
 853 #define HCLGE_NIC_CSQ_BASEADDR_H_REG    0x27004
 854 #define HCLGE_NIC_CSQ_DEPTH_REG         0x27008
 855 #define HCLGE_NIC_CSQ_TAIL_REG          0x27010
 856 #define HCLGE_NIC_CSQ_HEAD_REG          0x27014
 857 #define HCLGE_NIC_CRQ_BASEADDR_L_REG    0x27018
 858 #define HCLGE_NIC_CRQ_BASEADDR_H_REG    0x2701c
 859 #define HCLGE_NIC_CRQ_DEPTH_REG         0x27020
 860 #define HCLGE_NIC_CRQ_TAIL_REG          0x27024
 861 #define HCLGE_NIC_CRQ_HEAD_REG          0x27028
 862 #define HCLGE_NIC_CMQ_EN_B              16
 863 #define HCLGE_NIC_CMQ_ENABLE            BIT(HCLGE_NIC_CMQ_EN_B)
 864 #define HCLGE_NIC_CMQ_DESC_NUM          1024
 865 #define HCLGE_NIC_CMQ_DESC_NUM_S        3
 866
 867 #define HCLGE_LED_LOCATE_STATE_S        0
 868 #define HCLGE_LED_LOCATE_STATE_M        GENMASK(1, 0)
 869
 870 struct hclge_set_led_state_cmd {
 871         u8 rsv1[3];
 872         u8 locate_led_config;
 873         u8 rsv2[20];
 874 };
 875
 876 struct hclge_get_fd_mode_cmd {
 877         u8 mode;
 878         u8 enable;
 879         u8 rsv[22];
 880 };
 881
 882 struct hclge_get_fd_allocation_cmd {
 883         __le32 stage1_entry_num;
 884         __le32 stage2_entry_num;
 885         __le16 stage1_counter_num;
 886         __le16 stage2_counter_num;
 887         u8 rsv[12];
 888 };
 889
 890 struct hclge_set_fd_key_config_cmd {
 891         u8 stage;
 892         u8 key_select;
 893         u8 inner_sipv6_word_en;
 894         u8 inner_dipv6_word_en;
 895         u8 outer_sipv6_word_en;
 896         u8 outer_dipv6_word_en;
 897         u8 rsv1[2];
 898         __le32 tuple_mask;
 899         __le32 meta_data_mask;
 900         u8 rsv2[8];
 901 };
 902
 903 #define HCLGE_FD_EPORT_SW_EN_B          0
 904 struct hclge_fd_tcam_config_1_cmd {
 905         u8 stage;
 906         u8 xy_sel;
 907         u8 port_info;
 908         u8 rsv1[1];
 909         __le32 index;
 910         u8 entry_vld;
 911         u8 rsv2[7];
 912         u8 tcam_data[8];
 913 };
 914
 915 struct hclge_fd_tcam_config_2_cmd {
 916         u8 tcam_data[24];
 917 };
 918
 919 struct hclge_fd_tcam_config_3_cmd {
 920         u8 tcam_data[20];
 921         u8 rsv[4];
 922 };
 923
 924 #define HCLGE_FD_AD_DROP_B              0
 925 #define HCLGE_FD_AD_DIRECT_QID_B        1
 926 #define HCLGE_FD_AD_QID_S               2
 927 #define HCLGE_FD_AD_QID_M               GENMASK(12, 2)
 928 #define HCLGE_FD_AD_USE_COUNTER_B       12
 929 #define HCLGE_FD_AD_COUNTER_NUM_S       13
 930 #define HCLGE_FD_AD_COUNTER_NUM_M       GENMASK(20, 13)
 931 #define HCLGE_FD_AD_NXT_STEP_B          20
 932 #define HCLGE_FD_AD_NXT_KEY_S           21
 933 #define HCLGE_FD_AD_NXT_KEY_M           GENMASK(26, 21)
 934 #define HCLGE_FD_AD_WR_RULE_ID_B        0
 935 #define HCLGE_FD_AD_RULE_ID_S           1
 936 #define HCLGE_FD_AD_RULE_ID_M           GENMASK(13, 1)
 937
 938 struct hclge_fd_ad_config_cmd {
 939         u8 stage;
 940         u8 rsv1[3];
 941         __le32 index;
 942         __le64 ad_data;
 943         u8 rsv2[8];
 944 };
 945
 946 int hclge_cmd_init(struct hclge_dev *hdev);
 947 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
 948 {
 949         writel(value, base + reg);
 950 }
 951
 952 #define hclge_write_dev(a, reg, value) \
 953         hclge_write_reg((a)->io_base, (reg), (value))
 954 #define hclge_read_dev(a, reg) \
 955         hclge_read_reg((a)->io_base, (reg))
 956
 957 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg)
 958 {
 959         u8 __iomem *reg_addr = READ_ONCE(base);
 960
 961         return readl(reg_addr + reg);
 962 }
 963
 964 #define HCLGE_SEND_SYNC(flag) \
 965         ((flag) & HCLGE_CMD_FLAG_NO_INTR)
 966
 967 struct hclge_hw;
 968 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num);
 969 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
 970                                 enum hclge_opcode_type opcode, bool is_read);
 971 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
 972
 973 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
 974                                struct hclge_promisc_param *param);
 975
 976 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
 977                                            struct hclge_desc *desc);
 978 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
 979                                           struct hclge_desc *desc);
 980
 981 void hclge_destroy_cmd_queue(struct hclge_hw *hw);
 982 int hclge_cmd_queue_init(struct hclge_dev *hdev);
 983 #endif