2 * Copyright (c) 2016~2017 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
12 #include <linux/types.h>
15 #define HCLGE_CMDQ_TX_TIMEOUT 30000
21 #define HCLGE_CMDQ_RX_INVLD_B 0
22 #define HCLGE_CMDQ_RX_OUTVLD_B 1
30 struct hclge_desc_cb
{
36 struct hclge_cmq_ring
{
37 dma_addr_t desc_dma_addr
;
38 struct hclge_desc
*desc
;
39 struct hclge_desc_cb
*desc_cb
;
40 struct hclge_dev
*dev
;
49 spinlock_t lock
; /* Command queue lock */
52 enum hclge_cmd_return_status
{
53 HCLGE_CMD_EXEC_SUCCESS
= 0,
54 HCLGE_CMD_NO_AUTH
= 1,
55 HCLGE_CMD_NOT_EXEC
= 2,
56 HCLGE_CMD_QUEUE_FULL
= 3,
59 enum hclge_cmd_status
{
60 HCLGE_STATUS_SUCCESS
= 0,
61 HCLGE_ERR_CSQ_FULL
= -1,
62 HCLGE_ERR_CSQ_TIMEOUT
= -2,
63 HCLGE_ERR_CSQ_ERROR
= -3,
66 struct hclge_misc_vector
{
72 struct hclge_cmq_ring csq
;
73 struct hclge_cmq_ring crq
;
74 u16 tx_timeout
; /* Tx timeout */
75 enum hclge_cmd_status last_status
;
78 #define HCLGE_CMD_FLAG_IN_VALID_SHIFT 0
79 #define HCLGE_CMD_FLAG_OUT_VALID_SHIFT 1
80 #define HCLGE_CMD_FLAG_NEXT_SHIFT 2
81 #define HCLGE_CMD_FLAG_WR_OR_RD_SHIFT 3
82 #define HCLGE_CMD_FLAG_NO_INTR_SHIFT 4
83 #define HCLGE_CMD_FLAG_ERR_INTR_SHIFT 5
85 #define HCLGE_CMD_FLAG_IN BIT(HCLGE_CMD_FLAG_IN_VALID_SHIFT)
86 #define HCLGE_CMD_FLAG_OUT BIT(HCLGE_CMD_FLAG_OUT_VALID_SHIFT)
87 #define HCLGE_CMD_FLAG_NEXT BIT(HCLGE_CMD_FLAG_NEXT_SHIFT)
88 #define HCLGE_CMD_FLAG_WR BIT(HCLGE_CMD_FLAG_WR_OR_RD_SHIFT)
89 #define HCLGE_CMD_FLAG_NO_INTR BIT(HCLGE_CMD_FLAG_NO_INTR_SHIFT)
90 #define HCLGE_CMD_FLAG_ERR_INTR BIT(HCLGE_CMD_FLAG_ERR_INTR_SHIFT)
92 enum hclge_opcode_type
{
94 HCLGE_OPC_QUERY_FW_VER
= 0x0001,
95 HCLGE_OPC_CFG_RST_TRIGGER
= 0x0020,
96 HCLGE_OPC_GBL_RST_STATUS
= 0x0021,
97 HCLGE_OPC_QUERY_FUNC_STATUS
= 0x0022,
98 HCLGE_OPC_QUERY_PF_RSRC
= 0x0023,
99 HCLGE_OPC_QUERY_VF_RSRC
= 0x0024,
100 HCLGE_OPC_GET_CFG_PARAM
= 0x0025,
102 HCLGE_OPC_STATS_64_BIT
= 0x0030,
103 HCLGE_OPC_STATS_32_BIT
= 0x0031,
104 HCLGE_OPC_STATS_MAC
= 0x0032,
106 HCLGE_OPC_QUERY_REG_NUM
= 0x0040,
107 HCLGE_OPC_QUERY_32_BIT_REG
= 0x0041,
108 HCLGE_OPC_QUERY_64_BIT_REG
= 0x0042,
109 /* Device management command */
112 HCLGE_OPC_CONFIG_MAC_MODE
= 0x0301,
113 HCLGE_OPC_CONFIG_AN_MODE
= 0x0304,
114 HCLGE_OPC_QUERY_AN_RESULT
= 0x0306,
115 HCLGE_OPC_QUERY_LINK_STATUS
= 0x0307,
116 HCLGE_OPC_CONFIG_MAX_FRM_SIZE
= 0x0308,
117 HCLGE_OPC_CONFIG_SPEED_DUP
= 0x0309,
118 HCLGE_OPC_STATS_MAC_TRAFFIC
= 0x0314,
122 HCLGE_OPC_CFG_MAC_PAUSE_EN
= 0x0701,
123 HCLGE_OPC_CFG_PFC_PAUSE_EN
= 0x0702,
124 HCLGE_OPC_CFG_MAC_PARA
= 0x0703,
125 HCLGE_OPC_CFG_PFC_PARA
= 0x0704,
126 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT
= 0x0705,
127 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT
= 0x0706,
128 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT
= 0x0707,
129 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT
= 0x0708,
130 HCLGE_OPC_PRI_TO_TC_MAPPING
= 0x0709,
131 HCLGE_OPC_QOS_MAP
= 0x070A,
133 /* ETS/scheduler commands */
134 HCLGE_OPC_TM_PG_TO_PRI_LINK
= 0x0804,
135 HCLGE_OPC_TM_QS_TO_PRI_LINK
= 0x0805,
136 HCLGE_OPC_TM_NQ_TO_QS_LINK
= 0x0806,
137 HCLGE_OPC_TM_RQ_TO_QS_LINK
= 0x0807,
138 HCLGE_OPC_TM_PORT_WEIGHT
= 0x0808,
139 HCLGE_OPC_TM_PG_WEIGHT
= 0x0809,
140 HCLGE_OPC_TM_QS_WEIGHT
= 0x080A,
141 HCLGE_OPC_TM_PRI_WEIGHT
= 0x080B,
142 HCLGE_OPC_TM_PRI_C_SHAPPING
= 0x080C,
143 HCLGE_OPC_TM_PRI_P_SHAPPING
= 0x080D,
144 HCLGE_OPC_TM_PG_C_SHAPPING
= 0x080E,
145 HCLGE_OPC_TM_PG_P_SHAPPING
= 0x080F,
146 HCLGE_OPC_TM_PORT_SHAPPING
= 0x0810,
147 HCLGE_OPC_TM_PG_SCH_MODE_CFG
= 0x0812,
148 HCLGE_OPC_TM_PRI_SCH_MODE_CFG
= 0x0813,
149 HCLGE_OPC_TM_QS_SCH_MODE_CFG
= 0x0814,
150 HCLGE_OPC_TM_BP_TO_QSET_MAPPING
= 0x0815,
152 /* Packet buffer allocate command */
153 HCLGE_OPC_TX_BUFF_ALLOC
= 0x0901,
154 HCLGE_OPC_RX_PRIV_BUFF_ALLOC
= 0x0902,
155 HCLGE_OPC_RX_PRIV_WL_ALLOC
= 0x0903,
156 HCLGE_OPC_RX_COM_THRD_ALLOC
= 0x0904,
157 HCLGE_OPC_RX_COM_WL_ALLOC
= 0x0905,
158 HCLGE_OPC_RX_GBL_PKT_CNT
= 0x0906,
161 /* TQP management command */
162 HCLGE_OPC_SET_TQP_MAP
= 0x0A01,
165 HCLGE_OPC_CFG_TX_QUEUE
= 0x0B01,
166 HCLGE_OPC_QUERY_TX_POINTER
= 0x0B02,
167 HCLGE_OPC_QUERY_TX_STATUS
= 0x0B03,
168 HCLGE_OPC_CFG_RX_QUEUE
= 0x0B11,
169 HCLGE_OPC_QUERY_RX_POINTER
= 0x0B12,
170 HCLGE_OPC_QUERY_RX_STATUS
= 0x0B13,
171 HCLGE_OPC_STASH_RX_QUEUE_LRO
= 0x0B16,
172 HCLGE_OPC_CFG_RX_QUEUE_LRO
= 0x0B17,
173 HCLGE_OPC_CFG_COM_TQP_QUEUE
= 0x0B20,
174 HCLGE_OPC_RESET_TQP_QUEUE
= 0x0B22,
177 HCLGE_OPC_TSO_GENERIC_CONFIG
= 0x0C01,
180 HCLGE_OPC_RSS_GENERIC_CONFIG
= 0x0D01,
181 HCLGE_OPC_RSS_INDIR_TABLE
= 0x0D07,
182 HCLGE_OPC_RSS_TC_MODE
= 0x0D08,
183 HCLGE_OPC_RSS_INPUT_TUPLE
= 0x0D02,
185 /* Promisuous mode command */
186 HCLGE_OPC_CFG_PROMISC_MODE
= 0x0E01,
188 /* Vlan offload command */
189 HCLGE_OPC_VLAN_PORT_TX_CFG
= 0x0F01,
190 HCLGE_OPC_VLAN_PORT_RX_CFG
= 0x0F02,
193 HCLGE_OPC_ADD_RING_TO_VECTOR
= 0x1503,
194 HCLGE_OPC_DEL_RING_TO_VECTOR
= 0x1504,
197 HCLGE_OPC_MAC_VLAN_ADD
= 0x1000,
198 HCLGE_OPC_MAC_VLAN_REMOVE
= 0x1001,
199 HCLGE_OPC_MAC_VLAN_TYPE_ID
= 0x1002,
200 HCLGE_OPC_MAC_VLAN_INSERT
= 0x1003,
201 HCLGE_OPC_MAC_ETHTYPE_ADD
= 0x1010,
202 HCLGE_OPC_MAC_ETHTYPE_REMOVE
= 0x1011,
203 HCLGE_OPC_MAC_VLAN_MASK_SET
= 0x1012,
205 /* Multicast linear table cmd */
206 HCLGE_OPC_MTA_MAC_MODE_CFG
= 0x1020,
207 HCLGE_OPC_MTA_MAC_FUNC_CFG
= 0x1021,
208 HCLGE_OPC_MTA_TBL_ITEM_CFG
= 0x1022,
209 HCLGE_OPC_MTA_TBL_ITEM_QUERY
= 0x1023,
212 HCLGE_OPC_VLAN_FILTER_CTRL
= 0x1100,
213 HCLGE_OPC_VLAN_FILTER_PF_CFG
= 0x1101,
214 HCLGE_OPC_VLAN_FILTER_VF_CFG
= 0x1102,
217 HCLGE_OPC_MDIO_CONFIG
= 0x1900,
220 HCLGE_OPC_QCN_MOD_CFG
= 0x1A01,
221 HCLGE_OPC_QCN_GRP_TMPLT_CFG
= 0x1A02,
222 HCLGE_OPC_QCN_SHAPPING_IR_CFG
= 0x1A03,
223 HCLGE_OPC_QCN_SHAPPING_BS_CFG
= 0x1A04,
224 HCLGE_OPC_QCN_QSET_LINK_CFG
= 0x1A05,
225 HCLGE_OPC_QCN_RP_STATUS_GET
= 0x1A06,
226 HCLGE_OPC_QCN_AJUST_INIT
= 0x1A07,
227 HCLGE_OPC_QCN_DFX_CNT_STATUS
= 0x1A08,
230 HCLGEVF_OPC_MBX_PF_TO_VF
= 0x2000,
233 HCLGE_OPC_LED_STATUS_CFG
= 0xB000,
236 #define HCLGE_TQP_REG_OFFSET 0x80000
237 #define HCLGE_TQP_REG_SIZE 0x200
239 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10
240 #define HCLGE_RCB_INIT_FLAG_EN_B 0
241 #define HCLGE_RCB_INIT_FLAG_FINI_B 8
242 struct hclge_config_rcb_init_cmd
{
243 __le16 rcb_init_flag
;
247 struct hclge_tqp_map_cmd
{
248 __le16 tqp_id
; /* Absolute tqp id for in this pf */
249 u8 tqp_vf
; /* VF id */
250 #define HCLGE_TQP_MAP_TYPE_PF 0
251 #define HCLGE_TQP_MAP_TYPE_VF 1
252 #define HCLGE_TQP_MAP_TYPE_B 0
253 #define HCLGE_TQP_MAP_EN_B 1
254 u8 tqp_flag
; /* Indicate it's pf or vf tqp */
255 __le16 tqp_vid
; /* Virtual id in this pf/vf */
259 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10
261 enum hclge_int_type
{
267 struct hclge_ctrl_vector_chain_cmd
{
270 #define HCLGE_INT_TYPE_S 0
271 #define HCLGE_INT_TYPE_M GENMASK(1, 0)
272 #define HCLGE_TQP_ID_S 2
273 #define HCLGE_TQP_ID_M GENMASK(12, 2)
274 #define HCLGE_INT_GL_IDX_S 13
275 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13)
276 __le16 tqp_type_and_id
[HCLGE_VECTOR_ELEMENTS_PER_CMD
];
281 #define HCLGE_TC_NUM 8
282 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */
283 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */
284 struct hclge_tx_buff_alloc_cmd
{
285 __le16 tx_pkt_buff
[HCLGE_TC_NUM
];
289 struct hclge_rx_priv_buff_cmd
{
290 __le16 buf_num
[HCLGE_TC_NUM
];
295 struct hclge_query_version_cmd
{
297 __le32 firmware_rsv
[5];
300 #define HCLGE_RX_PRIV_EN_B 15
301 #define HCLGE_TC_NUM_ONE_DESC 4
302 struct hclge_priv_wl
{
307 struct hclge_rx_priv_wl_buf
{
308 struct hclge_priv_wl tc_wl
[HCLGE_TC_NUM_ONE_DESC
];
311 struct hclge_rx_com_thrd
{
312 struct hclge_priv_wl com_thrd
[HCLGE_TC_NUM_ONE_DESC
];
315 struct hclge_rx_com_wl
{
316 struct hclge_priv_wl com_wl
;
319 struct hclge_waterline
{
324 struct hclge_tc_thrd
{
329 struct hclge_priv_buf
{
330 struct hclge_waterline wl
; /* Waterline for low and high*/
331 u32 buf_size
; /* TC private buffer size */
333 u32 enable
; /* Enable TC private buffer or not */
336 #define HCLGE_MAX_TC_NUM 8
337 struct hclge_shared_buf
{
338 struct hclge_waterline self
;
339 struct hclge_tc_thrd tc_thrd
[HCLGE_MAX_TC_NUM
];
343 struct hclge_pkt_buf_alloc
{
344 struct hclge_priv_buf priv_buf
[HCLGE_MAX_TC_NUM
];
345 struct hclge_shared_buf s_buf
;
348 #define HCLGE_RX_COM_WL_EN_B 15
349 struct hclge_rx_com_wl_buf_cmd
{
355 #define HCLGE_RX_PKT_EN_B 15
356 struct hclge_rx_pkt_buf_cmd
{
362 #define HCLGE_PF_STATE_DONE_B 0
363 #define HCLGE_PF_STATE_MAIN_B 1
364 #define HCLGE_PF_STATE_BOND_B 2
365 #define HCLGE_PF_STATE_MAC_N_B 6
366 #define HCLGE_PF_MAC_NUM_MASK 0x3
367 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B)
368 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B)
369 struct hclge_func_status_cmd
{
370 __le32 vf_rst_state
[4];
380 struct hclge_pf_res_cmd
{
383 __le16 msixcap_localid_ba_nic
;
384 __le16 msixcap_localid_ba_rocee
;
385 #define HCLGE_PF_VEC_NUM_S 0
386 #define HCLGE_PF_VEC_NUM_M (0xff << HCLGE_PF_VEC_NUM_S)
387 __le16 pf_intr_vector_number
;
388 __le16 pf_own_fun_number
;
392 #define HCLGE_CFG_OFFSET_S 0
393 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0)
394 #define HCLGE_CFG_RD_LEN_S 24
395 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24)
396 #define HCLGE_CFG_RD_LEN_BYTES 16
397 #define HCLGE_CFG_RD_LEN_UNIT 4
399 #define HCLGE_CFG_VMDQ_S 0
400 #define HCLGE_CFG_VMDQ_M GENMASK(7, 0)
401 #define HCLGE_CFG_TC_NUM_S 8
402 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8)
403 #define HCLGE_CFG_TQP_DESC_N_S 16
404 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16)
405 #define HCLGE_CFG_PHY_ADDR_S 0
406 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0)
407 #define HCLGE_CFG_MEDIA_TP_S 8
408 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8)
409 #define HCLGE_CFG_RX_BUF_LEN_S 16
410 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16)
411 #define HCLGE_CFG_MAC_ADDR_H_S 0
412 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0)
413 #define HCLGE_CFG_DEFAULT_SPEED_S 16
414 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16)
415 #define HCLGE_CFG_RSS_SIZE_S 24
416 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24)
417 #define HCLGE_CFG_SPEED_ABILITY_S 0
418 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0)
420 struct hclge_cfg_param_cmd
{
426 #define HCLGE_MAC_MODE 0x0
427 #define HCLGE_DESC_NUM 0x40
429 #define HCLGE_ALLOC_VALID_B 0
430 struct hclge_vf_num_cmd
{
435 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4
436 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4
437 #define HCLGE_RSS_HASH_KEY_NUM 16
438 struct hclge_rss_config_cmd
{
441 u8 hash_key
[HCLGE_RSS_HASH_KEY_NUM
];
444 struct hclge_rss_input_tuple_cmd
{
456 #define HCLGE_RSS_CFG_TBL_SIZE 16
458 struct hclge_rss_indirection_table_cmd
{
459 __le16 start_table_index
;
460 __le16 rss_set_bitmap
;
462 u8 rss_result
[HCLGE_RSS_CFG_TBL_SIZE
];
465 #define HCLGE_RSS_TC_OFFSET_S 0
466 #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0)
467 #define HCLGE_RSS_TC_SIZE_S 12
468 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12)
469 #define HCLGE_RSS_TC_VALID_B 15
470 struct hclge_rss_tc_mode_cmd
{
471 __le16 rss_tc_mode
[HCLGE_MAX_TC_NUM
];
475 #define HCLGE_LINK_STS_B 0
476 #define HCLGE_LINK_STATUS BIT(HCLGE_LINK_STS_B)
477 struct hclge_link_status_cmd
{
482 struct hclge_promisc_param
{
487 #define HCLGE_PROMISC_TX_EN_B BIT(4)
488 #define HCLGE_PROMISC_RX_EN_B BIT(5)
489 #define HCLGE_PROMISC_EN_B 1
490 #define HCLGE_PROMISC_EN_ALL 0x7
491 #define HCLGE_PROMISC_EN_UC 0x1
492 #define HCLGE_PROMISC_EN_MC 0x2
493 #define HCLGE_PROMISC_EN_BC 0x4
494 struct hclge_promisc_cfg_cmd
{
501 enum hclge_promisc_type
{
507 #define HCLGE_MAC_TX_EN_B 6
508 #define HCLGE_MAC_RX_EN_B 7
509 #define HCLGE_MAC_PAD_TX_B 11
510 #define HCLGE_MAC_PAD_RX_B 12
511 #define HCLGE_MAC_1588_TX_B 13
512 #define HCLGE_MAC_1588_RX_B 14
513 #define HCLGE_MAC_APP_LP_B 15
514 #define HCLGE_MAC_LINE_LP_B 16
515 #define HCLGE_MAC_FCS_TX_B 17
516 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18
517 #define HCLGE_MAC_RX_FCS_STRIP_B 19
518 #define HCLGE_MAC_RX_FCS_B 20
519 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21
520 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22
522 struct hclge_config_mac_mode_cmd
{
523 __le32 txrx_pad_fcs_loop_en
;
527 #define HCLGE_CFG_SPEED_S 0
528 #define HCLGE_CFG_SPEED_M GENMASK(5, 0)
530 #define HCLGE_CFG_DUPLEX_B 7
531 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B)
533 struct hclge_config_mac_speed_dup_cmd
{
536 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
537 u8 mac_change_fec_en
;
541 #define HCLGE_QUERY_SPEED_S 3
542 #define HCLGE_QUERY_AN_B 0
543 #define HCLGE_QUERY_DUPLEX_B 2
545 #define HCLGE_QUERY_SPEED_M GENMASK(4, 0)
546 #define HCLGE_QUERY_AN_M BIT(HCLGE_QUERY_AN_B)
547 #define HCLGE_QUERY_DUPLEX_M BIT(HCLGE_QUERY_DUPLEX_B)
549 struct hclge_query_an_speed_dup_cmd
{
555 #define HCLGE_RING_ID_MASK GENMASK(9, 0)
556 #define HCLGE_TQP_ENABLE_B 0
558 #define HCLGE_MAC_CFG_AN_EN_B 0
559 #define HCLGE_MAC_CFG_AN_INT_EN_B 1
560 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2
561 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3
562 #define HCLGE_MAC_CFG_AN_RST_B 4
564 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B)
566 struct hclge_config_auto_neg_cmd
{
567 __le32 cfg_an_cmd_flag
;
571 #define HCLGE_MAC_UPLINK_PORT 0x100
573 struct hclge_config_max_frm_size_cmd
{
578 enum hclge_mac_vlan_tbl_opcode
{
579 HCLGE_MAC_VLAN_ADD
, /* Add new or modify mac_vlan */
580 HCLGE_MAC_VLAN_UPDATE
, /* Modify other fields of this table */
581 HCLGE_MAC_VLAN_REMOVE
, /* Remove a entry through mac_vlan key */
582 HCLGE_MAC_VLAN_LKUP
, /* Lookup a entry through mac_vlan key */
585 #define HCLGE_MAC_VLAN_BIT0_EN_B 0x0
586 #define HCLGE_MAC_VLAN_BIT1_EN_B 0x1
587 #define HCLGE_MAC_EPORT_SW_EN_B 0xc
588 #define HCLGE_MAC_EPORT_TYPE_B 0xb
589 #define HCLGE_MAC_EPORT_VFID_S 0x3
590 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3)
591 #define HCLGE_MAC_EPORT_PFID_S 0x0
592 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0)
593 struct hclge_mac_vlan_tbl_entry_cmd
{
597 __le32 mac_addr_hi32
;
598 __le16 mac_addr_lo16
;
607 #define HCLGE_VLAN_MASK_EN_B 0x0
608 struct hclge_mac_vlan_mask_entry_cmd
{
616 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0)
617 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1)
618 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2)
619 #define HCLGE_MAC_ETHERTYPE_LLDP 0x88cc
621 struct hclge_mac_mgr_tbl_entry_cmd
{
625 __le32 mac_addr_hi32
;
626 __le16 mac_addr_lo16
;
638 #define HCLGE_CFG_MTA_MAC_SEL_S 0x0
639 #define HCLGE_CFG_MTA_MAC_SEL_M GENMASK(1, 0)
640 #define HCLGE_CFG_MTA_MAC_EN_B 0x7
641 struct hclge_mta_filter_mode_cmd
{
642 u8 dmac_sel_en
; /* Use lowest 2 bit as sel_mode, bit 7 as enable */
646 #define HCLGE_CFG_FUNC_MTA_ACCEPT_B 0x0
647 struct hclge_cfg_func_mta_filter_cmd
{
648 u8 accept
; /* Only used lowest 1 bit */
653 #define HCLGE_CFG_MTA_ITEM_ACCEPT_B 0x0
654 #define HCLGE_CFG_MTA_ITEM_IDX_S 0x0
655 #define HCLGE_CFG_MTA_ITEM_IDX_M GENMASK(11, 0)
656 struct hclge_cfg_func_mta_item_cmd
{
657 __le16 item_idx
; /* Only used lowest 12 bit */
658 u8 accept
; /* Only used lowest 1 bit */
662 struct hclge_mac_vlan_add_cmd
{
664 __le16 mac_addr_hi16
;
665 __le32 mac_addr_lo32
;
666 __le32 mac_addr_msk_hi32
;
667 __le16 mac_addr_msk_lo16
;
674 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0
675 struct hclge_mac_vlan_remove_cmd
{
677 __le16 mac_addr_hi16
;
678 __le32 mac_addr_lo32
;
679 __le32 mac_addr_msk_hi32
;
680 __le16 mac_addr_msk_lo16
;
687 struct hclge_vlan_filter_ctrl_cmd
{
693 struct hclge_vlan_filter_pf_cfg_cmd
{
697 u8 vlan_offset_bitmap
[20];
700 struct hclge_vlan_filter_vf_cfg_cmd
{
709 #define HCLGE_ACCEPT_TAG1_B 0
710 #define HCLGE_ACCEPT_UNTAG1_B 1
711 #define HCLGE_PORT_INS_TAG1_EN_B 2
712 #define HCLGE_PORT_INS_TAG2_EN_B 3
713 #define HCLGE_CFG_NIC_ROCE_SEL_B 4
714 #define HCLGE_ACCEPT_TAG2_B 5
715 #define HCLGE_ACCEPT_UNTAG2_B 6
717 struct hclge_vport_vtag_tx_cfg_cmd
{
721 __le16 def_vlan_tag1
;
722 __le16 def_vlan_tag2
;
727 #define HCLGE_REM_TAG1_EN_B 0
728 #define HCLGE_REM_TAG2_EN_B 1
729 #define HCLGE_SHOW_TAG1_EN_B 2
730 #define HCLGE_SHOW_TAG2_EN_B 3
731 struct hclge_vport_vtag_rx_cfg_cmd
{
739 struct hclge_tx_vlan_type_cfg_cmd
{
745 struct hclge_rx_vlan_type_cfg_cmd
{
746 __le16 ot_fst_vlan_type
;
747 __le16 ot_sec_vlan_type
;
748 __le16 in_fst_vlan_type
;
749 __le16 in_sec_vlan_type
;
753 struct hclge_cfg_com_tqp_queue_cmd
{
760 struct hclge_cfg_tx_queue_pointer_cmd
{
769 #define HCLGE_TSO_MSS_MIN_S 0
770 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0)
772 #define HCLGE_TSO_MSS_MAX_S 16
773 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16)
775 struct hclge_cfg_tso_status_cmd
{
781 #define HCLGE_TSO_MSS_MIN 256
782 #define HCLGE_TSO_MSS_MAX 9668
784 #define HCLGE_TQP_RESET_B 0
785 struct hclge_reset_tqp_queue_cmd
{
792 #define HCLGE_CFG_RESET_MAC_B 3
793 #define HCLGE_CFG_RESET_FUNC_B 7
794 struct hclge_reset_cmd
{
799 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */
800 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
801 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */
802 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */
804 #define HCLGE_TYPE_CRQ 0
805 #define HCLGE_TYPE_CSQ 1
806 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000
807 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004
808 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008
809 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010
810 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014
811 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018
812 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c
813 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020
814 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024
815 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028
816 #define HCLGE_NIC_CMQ_EN_B 16
817 #define HCLGE_NIC_CMQ_ENABLE BIT(HCLGE_NIC_CMQ_EN_B)
818 #define HCLGE_NIC_CMQ_DESC_NUM 1024
819 #define HCLGE_NIC_CMQ_DESC_NUM_S 3
821 #define HCLGE_LED_PORT_SPEED_STATE_S 0
822 #define HCLGE_LED_PORT_SPEED_STATE_M GENMASK(5, 0)
823 #define HCLGE_LED_ACTIVITY_STATE_S 0
824 #define HCLGE_LED_ACTIVITY_STATE_M GENMASK(1, 0)
825 #define HCLGE_LED_LINK_STATE_S 0
826 #define HCLGE_LED_LINK_STATE_M GENMASK(1, 0)
827 #define HCLGE_LED_LOCATE_STATE_S 0
828 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0)
830 struct hclge_set_led_state_cmd
{
831 u8 port_speed_led_config
;
833 u8 activity_led_config
;
834 u8 locate_led_config
;
838 int hclge_cmd_init(struct hclge_dev
*hdev
);
839 static inline void hclge_write_reg(void __iomem
*base
, u32 reg
, u32 value
)
841 writel(value
, base
+ reg
);
844 #define hclge_write_dev(a, reg, value) \
845 hclge_write_reg((a)->io_base, (reg), (value))
846 #define hclge_read_dev(a, reg) \
847 hclge_read_reg((a)->io_base, (reg))
849 static inline u32
hclge_read_reg(u8 __iomem
*base
, u32 reg
)
851 u8 __iomem
*reg_addr
= READ_ONCE(base
);
853 return readl(reg_addr
+ reg
);
856 #define HCLGE_SEND_SYNC(flag) \
857 ((flag) & HCLGE_CMD_FLAG_NO_INTR)
860 int hclge_cmd_send(struct hclge_hw
*hw
, struct hclge_desc
*desc
, int num
);
861 void hclge_cmd_setup_basic_desc(struct hclge_desc
*desc
,
862 enum hclge_opcode_type opcode
, bool is_read
);
863 void hclge_cmd_reuse_desc(struct hclge_desc
*desc
, bool is_read
);
865 int hclge_cmd_set_promisc_mode(struct hclge_dev
*hdev
,
866 struct hclge_promisc_param
*param
);
868 enum hclge_cmd_status
hclge_cmd_mdio_write(struct hclge_hw
*hw
,
869 struct hclge_desc
*desc
);
870 enum hclge_cmd_status
hclge_cmd_mdio_read(struct hclge_hw
*hw
,
871 struct hclge_desc
*desc
);
873 void hclge_destroy_cmd_queue(struct hclge_hw
*hw
);
874 int hclge_cmd_queue_init(struct hclge_dev
*hdev
);