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[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_cmd.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #ifndef __HCLGE_CMD_H
5 #define __HCLGE_CMD_H
6 #include <linux/types.h>
7 #include <linux/io.h>
8 #include <linux/etherdevice.h>
9 #include "hnae3.h"
10
11 #define HCLGE_CMDQ_TX_TIMEOUT 30000
12 #define HCLGE_DESC_DATA_LEN 6
13
14 struct hclge_dev;
15 struct hclge_desc {
16 __le16 opcode;
17
18 #define HCLGE_CMDQ_RX_INVLD_B 0
19 #define HCLGE_CMDQ_RX_OUTVLD_B 1
20
21 __le16 flag;
22 __le16 retval;
23 __le16 rsv;
24 __le32 data[HCLGE_DESC_DATA_LEN];
25 };
26
27 struct hclge_cmq_ring {
28 dma_addr_t desc_dma_addr;
29 struct hclge_desc *desc;
30 struct hclge_dev *dev;
31 u32 head;
32 u32 tail;
33
34 u16 buf_size;
35 u16 desc_num;
36 int next_to_use;
37 int next_to_clean;
38 u8 ring_type; /* cmq ring type */
39 spinlock_t lock; /* Command queue lock */
40 };
41
42 enum hclge_cmd_return_status {
43 HCLGE_CMD_EXEC_SUCCESS = 0,
44 HCLGE_CMD_NO_AUTH = 1,
45 HCLGE_CMD_NOT_SUPPORTED = 2,
46 HCLGE_CMD_QUEUE_FULL = 3,
47 HCLGE_CMD_NEXT_ERR = 4,
48 HCLGE_CMD_UNEXE_ERR = 5,
49 HCLGE_CMD_PARA_ERR = 6,
50 HCLGE_CMD_RESULT_ERR = 7,
51 HCLGE_CMD_TIMEOUT = 8,
52 HCLGE_CMD_HILINK_ERR = 9,
53 HCLGE_CMD_QUEUE_ILLEGAL = 10,
54 HCLGE_CMD_INVALID = 11,
55 };
56
57 enum hclge_cmd_status {
58 HCLGE_STATUS_SUCCESS = 0,
59 HCLGE_ERR_CSQ_FULL = -1,
60 HCLGE_ERR_CSQ_TIMEOUT = -2,
61 HCLGE_ERR_CSQ_ERROR = -3,
62 };
63
64 struct hclge_misc_vector {
65 u8 __iomem *addr;
66 int vector_irq;
67 char name[HNAE3_INT_NAME_LEN];
68 };
69
70 struct hclge_cmq {
71 struct hclge_cmq_ring csq;
72 struct hclge_cmq_ring crq;
73 u16 tx_timeout;
74 enum hclge_cmd_status last_status;
75 };
76
77 #define HCLGE_CMD_FLAG_IN BIT(0)
78 #define HCLGE_CMD_FLAG_OUT BIT(1)
79 #define HCLGE_CMD_FLAG_NEXT BIT(2)
80 #define HCLGE_CMD_FLAG_WR BIT(3)
81 #define HCLGE_CMD_FLAG_NO_INTR BIT(4)
82 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5)
83
84 enum hclge_opcode_type {
85 /* Generic commands */
86 HCLGE_OPC_QUERY_FW_VER = 0x0001,
87 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020,
88 HCLGE_OPC_GBL_RST_STATUS = 0x0021,
89 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022,
90 HCLGE_OPC_QUERY_PF_RSRC = 0x0023,
91 HCLGE_OPC_QUERY_VF_RSRC = 0x0024,
92 HCLGE_OPC_GET_CFG_PARAM = 0x0025,
93 HCLGE_OPC_PF_RST_DONE = 0x0026,
94 HCLGE_OPC_QUERY_VF_RST_RDY = 0x0027,
95
96 HCLGE_OPC_STATS_64_BIT = 0x0030,
97 HCLGE_OPC_STATS_32_BIT = 0x0031,
98 HCLGE_OPC_STATS_MAC = 0x0032,
99 HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033,
100 HCLGE_OPC_STATS_MAC_ALL = 0x0034,
101
102 HCLGE_OPC_QUERY_REG_NUM = 0x0040,
103 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041,
104 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042,
105 HCLGE_OPC_DFX_BD_NUM = 0x0043,
106 HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044,
107 HCLGE_OPC_DFX_SSU_REG_0 = 0x0045,
108 HCLGE_OPC_DFX_SSU_REG_1 = 0x0046,
109 HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047,
110 HCLGE_OPC_DFX_RPU_REG_0 = 0x0048,
111 HCLGE_OPC_DFX_RPU_REG_1 = 0x0049,
112 HCLGE_OPC_DFX_NCSI_REG = 0x004A,
113 HCLGE_OPC_DFX_RTC_REG = 0x004B,
114 HCLGE_OPC_DFX_PPP_REG = 0x004C,
115 HCLGE_OPC_DFX_RCB_REG = 0x004D,
116 HCLGE_OPC_DFX_TQP_REG = 0x004E,
117 HCLGE_OPC_DFX_SSU_REG_2 = 0x004F,
118
119 HCLGE_OPC_QUERY_DEV_SPECS = 0x0050,
120
121 /* MAC command */
122 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301,
123 HCLGE_OPC_CONFIG_AN_MODE = 0x0304,
124 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307,
125 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
126 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309,
127 HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310,
128 HCLGE_OPC_MAC_TNL_INT_EN = 0x0311,
129 HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312,
130 HCLGE_OPC_SERDES_LOOPBACK = 0x0315,
131 HCLGE_OPC_CONFIG_FEC_MODE = 0x031A,
132
133 /* PFC/Pause commands */
134 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701,
135 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702,
136 HCLGE_OPC_CFG_MAC_PARA = 0x0703,
137 HCLGE_OPC_CFG_PFC_PARA = 0x0704,
138 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705,
139 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706,
140 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707,
141 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708,
142 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709,
143 HCLGE_OPC_QOS_MAP = 0x070A,
144
145 /* ETS/scheduler commands */
146 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804,
147 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805,
148 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806,
149 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807,
150 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808,
151 HCLGE_OPC_TM_PG_WEIGHT = 0x0809,
152 HCLGE_OPC_TM_QS_WEIGHT = 0x080A,
153 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B,
154 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C,
155 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D,
156 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E,
157 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F,
158 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810,
159 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812,
160 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813,
161 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814,
162 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
163 HCLGE_OPC_ETS_TC_WEIGHT = 0x0843,
164 HCLGE_OPC_QSET_DFX_STS = 0x0844,
165 HCLGE_OPC_PRI_DFX_STS = 0x0845,
166 HCLGE_OPC_PG_DFX_STS = 0x0846,
167 HCLGE_OPC_PORT_DFX_STS = 0x0847,
168 HCLGE_OPC_SCH_NQ_CNT = 0x0848,
169 HCLGE_OPC_SCH_RQ_CNT = 0x0849,
170 HCLGE_OPC_TM_INTERNAL_STS = 0x0850,
171 HCLGE_OPC_TM_INTERNAL_CNT = 0x0851,
172 HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852,
173
174 /* Packet buffer allocate commands */
175 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901,
176 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902,
177 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903,
178 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904,
179 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905,
180 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906,
181
182 /* TQP management command */
183 HCLGE_OPC_SET_TQP_MAP = 0x0A01,
184
185 /* TQP commands */
186 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01,
187 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02,
188 HCLGE_OPC_QUERY_TX_STATS = 0x0B03,
189 HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04,
190 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11,
191 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12,
192 HCLGE_OPC_QUERY_RX_STATS = 0x0B13,
193 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16,
194 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17,
195 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
196 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22,
197
198 /* PPU commands */
199 HCLGE_OPC_PPU_PF_OTHER_INT_DFX = 0x0B4A,
200
201 /* TSO command */
202 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01,
203 HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10,
204
205 /* RSS commands */
206 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01,
207 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07,
208 HCLGE_OPC_RSS_TC_MODE = 0x0D08,
209 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02,
210
211 /* Promisuous mode command */
212 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01,
213
214 /* Vlan offload commands */
215 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01,
216 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02,
217
218 /* Interrupts commands */
219 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503,
220 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504,
221
222 /* MAC commands */
223 HCLGE_OPC_MAC_VLAN_ADD = 0x1000,
224 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001,
225 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002,
226 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003,
227 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004,
228 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010,
229 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011,
230
231 /* MAC VLAN commands */
232 HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033,
233
234 /* VLAN commands */
235 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100,
236 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101,
237 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102,
238
239 /* Flow Director commands */
240 HCLGE_OPC_FD_MODE_CTRL = 0x1200,
241 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201,
242 HCLGE_OPC_FD_KEY_CONFIG = 0x1202,
243 HCLGE_OPC_FD_TCAM_OP = 0x1203,
244 HCLGE_OPC_FD_AD_OP = 0x1204,
245
246 /* MDIO command */
247 HCLGE_OPC_MDIO_CONFIG = 0x1900,
248
249 /* QCN commands */
250 HCLGE_OPC_QCN_MOD_CFG = 0x1A01,
251 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02,
252 HCLGE_OPC_QCN_SHAPPING_CFG = 0x1A03,
253 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04,
254 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05,
255 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06,
256 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07,
257 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08,
258
259 /* Mailbox command */
260 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000,
261
262 /* Led command */
263 HCLGE_OPC_LED_STATUS_CFG = 0xB000,
264
265 /* clear hardware resource command */
266 HCLGE_OPC_CLEAR_HW_RESOURCE = 0x700B,
267
268 /* NCL config command */
269 HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011,
270
271 /* M7 stats command */
272 HCLGE_OPC_M7_STATS_BD = 0x7012,
273 HCLGE_OPC_M7_STATS_INFO = 0x7013,
274 HCLGE_OPC_M7_COMPAT_CFG = 0x701A,
275
276 /* SFP command */
277 HCLGE_OPC_GET_SFP_EEPROM = 0x7100,
278 HCLGE_OPC_GET_SFP_EXIST = 0x7101,
279 HCLGE_OPC_GET_SFP_INFO = 0x7104,
280
281 /* Error INT commands */
282 HCLGE_MAC_COMMON_INT_EN = 0x030E,
283 HCLGE_TM_SCH_ECC_INT_EN = 0x0829,
284 HCLGE_SSU_ECC_INT_CMD = 0x0989,
285 HCLGE_SSU_COMMON_INT_CMD = 0x098C,
286 HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40,
287 HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41,
288 HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42,
289 HCLGE_COMMON_ECC_INT_CFG = 0x1505,
290 HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510,
291 HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511,
292 HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512,
293 HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
294 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,
295 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,
296 HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580,
297 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
298 HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584,
299 HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD = 0x1585,
300 HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD = 0x1586,
301 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803,
302 HCLGE_IGU_COMMON_INT_EN = 0x1806,
303 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14,
304 HCLGE_PPP_CMD0_INT_CMD = 0x2100,
305 HCLGE_PPP_CMD1_INT_CMD = 0x2101,
306 HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105,
307 HCLGE_NCSI_INT_EN = 0x2401,
308 };
309
310 #define HCLGE_TQP_REG_OFFSET 0x80000
311 #define HCLGE_TQP_REG_SIZE 0x200
312
313 #define HCLGE_TQP_MAX_SIZE_DEV_V2 1024
314 #define HCLGE_TQP_EXT_REG_OFFSET 0x100
315
316 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10
317 #define HCLGE_RCB_INIT_FLAG_EN_B 0
318 #define HCLGE_RCB_INIT_FLAG_FINI_B 8
319 struct hclge_config_rcb_init_cmd {
320 __le16 rcb_init_flag;
321 u8 rsv[22];
322 };
323
324 struct hclge_tqp_map_cmd {
325 __le16 tqp_id; /* Absolute tqp id for in this pf */
326 u8 tqp_vf; /* VF id */
327 #define HCLGE_TQP_MAP_TYPE_PF 0
328 #define HCLGE_TQP_MAP_TYPE_VF 1
329 #define HCLGE_TQP_MAP_TYPE_B 0
330 #define HCLGE_TQP_MAP_EN_B 1
331 u8 tqp_flag; /* Indicate it's pf or vf tqp */
332 __le16 tqp_vid; /* Virtual id in this pf/vf */
333 u8 rsv[18];
334 };
335
336 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10
337
338 enum hclge_int_type {
339 HCLGE_INT_TX,
340 HCLGE_INT_RX,
341 HCLGE_INT_EVENT,
342 };
343
344 struct hclge_ctrl_vector_chain_cmd {
345 #define HCLGE_VECTOR_ID_L_S 0
346 #define HCLGE_VECTOR_ID_L_M GENMASK(7, 0)
347 u8 int_vector_id_l;
348 u8 int_cause_num;
349 #define HCLGE_INT_TYPE_S 0
350 #define HCLGE_INT_TYPE_M GENMASK(1, 0)
351 #define HCLGE_TQP_ID_S 2
352 #define HCLGE_TQP_ID_M GENMASK(12, 2)
353 #define HCLGE_INT_GL_IDX_S 13
354 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13)
355 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];
356 u8 vfid;
357 #define HCLGE_VECTOR_ID_H_S 8
358 #define HCLGE_VECTOR_ID_H_M GENMASK(15, 8)
359 u8 int_vector_id_h;
360 };
361
362 #define HCLGE_MAX_TC_NUM 8
363 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */
364 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */
365 struct hclge_tx_buff_alloc_cmd {
366 __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM];
367 u8 tx_buff_rsv[8];
368 };
369
370 struct hclge_rx_priv_buff_cmd {
371 __le16 buf_num[HCLGE_MAX_TC_NUM];
372 __le16 shared_buf;
373 u8 rsv[6];
374 };
375
376 enum HCLGE_CAP_BITS {
377 HCLGE_CAP_UDP_GSO_B,
378 HCLGE_CAP_QB_B,
379 HCLGE_CAP_FD_FORWARD_TC_B,
380 HCLGE_CAP_PTP_B,
381 HCLGE_CAP_INT_QL_B,
382 HCLGE_CAP_HW_TX_CSUM_B,
383 HCLGE_CAP_TX_PUSH_B,
384 HCLGE_CAP_PHY_IMP_B,
385 HCLGE_CAP_TQP_TXRX_INDEP_B,
386 HCLGE_CAP_HW_PAD_B,
387 HCLGE_CAP_STASH_B,
388 HCLGE_CAP_UDP_TUNNEL_CSUM_B,
389 };
390
391 #define HCLGE_QUERY_CAP_LENGTH 3
392 struct hclge_query_version_cmd {
393 __le32 firmware;
394 __le32 hardware;
395 __le32 rsv;
396 __le32 caps[HCLGE_QUERY_CAP_LENGTH]; /* capabilities of device */
397 };
398
399 #define HCLGE_RX_PRIV_EN_B 15
400 #define HCLGE_TC_NUM_ONE_DESC 4
401 struct hclge_priv_wl {
402 __le16 high;
403 __le16 low;
404 };
405
406 struct hclge_rx_priv_wl_buf {
407 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC];
408 };
409
410 struct hclge_rx_com_thrd {
411 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC];
412 };
413
414 struct hclge_rx_com_wl {
415 struct hclge_priv_wl com_wl;
416 };
417
418 struct hclge_waterline {
419 u32 low;
420 u32 high;
421 };
422
423 struct hclge_tc_thrd {
424 u32 low;
425 u32 high;
426 };
427
428 struct hclge_priv_buf {
429 struct hclge_waterline wl; /* Waterline for low and high*/
430 u32 buf_size; /* TC private buffer size */
431 u32 tx_buf_size;
432 u32 enable; /* Enable TC private buffer or not */
433 };
434
435 struct hclge_shared_buf {
436 struct hclge_waterline self;
437 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM];
438 u32 buf_size;
439 };
440
441 struct hclge_pkt_buf_alloc {
442 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM];
443 struct hclge_shared_buf s_buf;
444 };
445
446 #define HCLGE_RX_COM_WL_EN_B 15
447 struct hclge_rx_com_wl_buf_cmd {
448 __le16 high_wl;
449 __le16 low_wl;
450 u8 rsv[20];
451 };
452
453 #define HCLGE_RX_PKT_EN_B 15
454 struct hclge_rx_pkt_buf_cmd {
455 __le16 high_pkt;
456 __le16 low_pkt;
457 u8 rsv[20];
458 };
459
460 #define HCLGE_PF_STATE_DONE_B 0
461 #define HCLGE_PF_STATE_MAIN_B 1
462 #define HCLGE_PF_STATE_BOND_B 2
463 #define HCLGE_PF_STATE_MAC_N_B 6
464 #define HCLGE_PF_MAC_NUM_MASK 0x3
465 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B)
466 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B)
467 #define HCLGE_VF_RST_STATUS_CMD 4
468
469 struct hclge_func_status_cmd {
470 __le32 vf_rst_state[HCLGE_VF_RST_STATUS_CMD];
471 u8 pf_state;
472 u8 mac_id;
473 u8 rsv1;
474 u8 pf_cnt_in_mac;
475 u8 pf_num;
476 u8 vf_num;
477 u8 rsv[2];
478 };
479
480 struct hclge_pf_res_cmd {
481 __le16 tqp_num;
482 __le16 buf_size;
483 __le16 msixcap_localid_ba_nic;
484 __le16 msixcap_localid_number_nic;
485 __le16 pf_intr_vector_number_roce;
486 __le16 pf_own_fun_number;
487 __le16 tx_buf_size;
488 __le16 dv_buf_size;
489 __le16 ext_tqp_num;
490 u8 rsv[6];
491 };
492
493 #define HCLGE_CFG_OFFSET_S 0
494 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0)
495 #define HCLGE_CFG_RD_LEN_S 24
496 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24)
497 #define HCLGE_CFG_RD_LEN_BYTES 16
498 #define HCLGE_CFG_RD_LEN_UNIT 4
499
500 #define HCLGE_CFG_VMDQ_S 0
501 #define HCLGE_CFG_VMDQ_M GENMASK(7, 0)
502 #define HCLGE_CFG_TC_NUM_S 8
503 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8)
504 #define HCLGE_CFG_TQP_DESC_N_S 16
505 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16)
506 #define HCLGE_CFG_PHY_ADDR_S 0
507 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0)
508 #define HCLGE_CFG_MEDIA_TP_S 8
509 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8)
510 #define HCLGE_CFG_RX_BUF_LEN_S 16
511 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16)
512 #define HCLGE_CFG_MAC_ADDR_H_S 0
513 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0)
514 #define HCLGE_CFG_DEFAULT_SPEED_S 16
515 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16)
516 #define HCLGE_CFG_RSS_SIZE_S 24
517 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24)
518 #define HCLGE_CFG_SPEED_ABILITY_S 0
519 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0)
520 #define HCLGE_CFG_SPEED_ABILITY_EXT_S 10
521 #define HCLGE_CFG_SPEED_ABILITY_EXT_M GENMASK(15, 10)
522 #define HCLGE_CFG_UMV_TBL_SPACE_S 16
523 #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16)
524 #define HCLGE_CFG_PF_RSS_SIZE_S 0
525 #define HCLGE_CFG_PF_RSS_SIZE_M GENMASK(3, 0)
526
527 #define HCLGE_CFG_CMD_CNT 4
528
529 struct hclge_cfg_param_cmd {
530 __le32 offset;
531 __le32 rsv;
532 __le32 param[HCLGE_CFG_CMD_CNT];
533 };
534
535 #define HCLGE_MAC_MODE 0x0
536 #define HCLGE_DESC_NUM 0x40
537
538 #define HCLGE_ALLOC_VALID_B 0
539 struct hclge_vf_num_cmd {
540 u8 alloc_valid;
541 u8 rsv[23];
542 };
543
544 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4
545 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4
546 #define HCLGE_RSS_HASH_KEY_NUM 16
547 struct hclge_rss_config_cmd {
548 u8 hash_config;
549 u8 rsv[7];
550 u8 hash_key[HCLGE_RSS_HASH_KEY_NUM];
551 };
552
553 struct hclge_rss_input_tuple_cmd {
554 u8 ipv4_tcp_en;
555 u8 ipv4_udp_en;
556 u8 ipv4_sctp_en;
557 u8 ipv4_fragment_en;
558 u8 ipv6_tcp_en;
559 u8 ipv6_udp_en;
560 u8 ipv6_sctp_en;
561 u8 ipv6_fragment_en;
562 u8 rsv[16];
563 };
564
565 #define HCLGE_RSS_CFG_TBL_SIZE 16
566 #define HCLGE_RSS_CFG_TBL_SIZE_H 4
567 #define HCLGE_RSS_CFG_TBL_BW_H 2U
568 #define HCLGE_RSS_CFG_TBL_BW_L 8U
569
570 struct hclge_rss_indirection_table_cmd {
571 __le16 start_table_index;
572 __le16 rss_set_bitmap;
573 u8 rss_qid_h[HCLGE_RSS_CFG_TBL_SIZE_H];
574 u8 rss_qid_l[HCLGE_RSS_CFG_TBL_SIZE];
575 };
576
577 #define HCLGE_RSS_TC_OFFSET_S 0
578 #define HCLGE_RSS_TC_OFFSET_M GENMASK(10, 0)
579 #define HCLGE_RSS_TC_SIZE_MSB_B 11
580 #define HCLGE_RSS_TC_SIZE_S 12
581 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12)
582 #define HCLGE_RSS_TC_SIZE_MSB_OFFSET 3
583 #define HCLGE_RSS_TC_VALID_B 15
584 struct hclge_rss_tc_mode_cmd {
585 __le16 rss_tc_mode[HCLGE_MAX_TC_NUM];
586 u8 rsv[8];
587 };
588
589 #define HCLGE_LINK_STATUS_UP_B 0
590 #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B)
591 struct hclge_link_status_cmd {
592 u8 status;
593 u8 rsv[23];
594 };
595
596 /* for DEVICE_VERSION_V1/2, reference to promisc cmd byte8 */
597 #define HCLGE_PROMISC_EN_UC 1
598 #define HCLGE_PROMISC_EN_MC 2
599 #define HCLGE_PROMISC_EN_BC 3
600 #define HCLGE_PROMISC_TX_EN 4
601 #define HCLGE_PROMISC_RX_EN 5
602
603 /* for DEVICE_VERSION_V3, reference to promisc cmd byte10 */
604 #define HCLGE_PROMISC_UC_RX_EN 2
605 #define HCLGE_PROMISC_MC_RX_EN 3
606 #define HCLGE_PROMISC_BC_RX_EN 4
607 #define HCLGE_PROMISC_UC_TX_EN 5
608 #define HCLGE_PROMISC_MC_TX_EN 6
609 #define HCLGE_PROMISC_BC_TX_EN 7
610
611 struct hclge_promisc_cfg_cmd {
612 u8 promisc;
613 u8 vf_id;
614 u8 extend_promisc;
615 u8 rsv0[21];
616 };
617
618 enum hclge_promisc_type {
619 HCLGE_UNICAST = 1,
620 HCLGE_MULTICAST = 2,
621 HCLGE_BROADCAST = 3,
622 };
623
624 #define HCLGE_MAC_TX_EN_B 6
625 #define HCLGE_MAC_RX_EN_B 7
626 #define HCLGE_MAC_PAD_TX_B 11
627 #define HCLGE_MAC_PAD_RX_B 12
628 #define HCLGE_MAC_1588_TX_B 13
629 #define HCLGE_MAC_1588_RX_B 14
630 #define HCLGE_MAC_APP_LP_B 15
631 #define HCLGE_MAC_LINE_LP_B 16
632 #define HCLGE_MAC_FCS_TX_B 17
633 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18
634 #define HCLGE_MAC_RX_FCS_STRIP_B 19
635 #define HCLGE_MAC_RX_FCS_B 20
636 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21
637 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22
638
639 struct hclge_config_mac_mode_cmd {
640 __le32 txrx_pad_fcs_loop_en;
641 u8 rsv[20];
642 };
643
644 struct hclge_pf_rst_sync_cmd {
645 #define HCLGE_PF_RST_ALL_VF_RDY_B 0
646 u8 all_vf_ready;
647 u8 rsv[23];
648 };
649
650 #define HCLGE_CFG_SPEED_S 0
651 #define HCLGE_CFG_SPEED_M GENMASK(5, 0)
652
653 #define HCLGE_CFG_DUPLEX_B 7
654 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B)
655
656 struct hclge_config_mac_speed_dup_cmd {
657 u8 speed_dup;
658
659 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
660 u8 mac_change_fec_en;
661 u8 rsv[22];
662 };
663
664 #define HCLGE_TQP_ENABLE_B 0
665
666 #define HCLGE_MAC_CFG_AN_EN_B 0
667 #define HCLGE_MAC_CFG_AN_INT_EN_B 1
668 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2
669 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3
670 #define HCLGE_MAC_CFG_AN_RST_B 4
671
672 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B)
673
674 struct hclge_config_auto_neg_cmd {
675 __le32 cfg_an_cmd_flag;
676 u8 rsv[20];
677 };
678
679 struct hclge_sfp_info_cmd {
680 __le32 speed;
681 u8 query_type; /* 0: sfp speed, 1: active speed */
682 u8 active_fec;
683 u8 autoneg; /* autoneg state */
684 u8 autoneg_ability; /* whether support autoneg */
685 __le32 speed_ability; /* speed ability for current media */
686 __le32 module_type;
687 u8 rsv[8];
688 };
689
690 #define HCLGE_MAC_CFG_FEC_AUTO_EN_B 0
691 #define HCLGE_MAC_CFG_FEC_MODE_S 1
692 #define HCLGE_MAC_CFG_FEC_MODE_M GENMASK(3, 1)
693 #define HCLGE_MAC_CFG_FEC_SET_DEF_B 0
694 #define HCLGE_MAC_CFG_FEC_CLR_DEF_B 1
695
696 #define HCLGE_MAC_FEC_OFF 0
697 #define HCLGE_MAC_FEC_BASER 1
698 #define HCLGE_MAC_FEC_RS 2
699 struct hclge_config_fec_cmd {
700 u8 fec_mode;
701 u8 default_config;
702 u8 rsv[22];
703 };
704
705 #define HCLGE_MAC_UPLINK_PORT 0x100
706
707 struct hclge_config_max_frm_size_cmd {
708 __le16 max_frm_size;
709 u8 min_frm_size;
710 u8 rsv[21];
711 };
712
713 enum hclge_mac_vlan_tbl_opcode {
714 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */
715 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */
716 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */
717 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */
718 };
719
720 enum hclge_mac_vlan_add_resp_code {
721 HCLGE_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */
722 HCLGE_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */
723 };
724
725 #define HCLGE_MAC_VLAN_BIT0_EN_B 0
726 #define HCLGE_MAC_VLAN_BIT1_EN_B 1
727 #define HCLGE_MAC_EPORT_SW_EN_B 12
728 #define HCLGE_MAC_EPORT_TYPE_B 11
729 #define HCLGE_MAC_EPORT_VFID_S 3
730 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3)
731 #define HCLGE_MAC_EPORT_PFID_S 0
732 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0)
733 struct hclge_mac_vlan_tbl_entry_cmd {
734 u8 flags;
735 u8 resp_code;
736 __le16 vlan_tag;
737 __le32 mac_addr_hi32;
738 __le16 mac_addr_lo16;
739 __le16 rsv1;
740 u8 entry_type;
741 u8 mc_mac_en;
742 __le16 egress_port;
743 __le16 egress_queue;
744 u8 rsv2[6];
745 };
746
747 #define HCLGE_UMV_SPC_ALC_B 0
748 struct hclge_umv_spc_alc_cmd {
749 u8 allocate;
750 u8 rsv1[3];
751 __le32 space_size;
752 u8 rsv2[16];
753 };
754
755 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0)
756 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1)
757 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2)
758
759 struct hclge_mac_mgr_tbl_entry_cmd {
760 u8 flags;
761 u8 resp_code;
762 __le16 vlan_tag;
763 u8 mac_addr[ETH_ALEN];
764 __le16 rsv1;
765 __le16 ethter_type;
766 __le16 egress_port;
767 __le16 egress_queue;
768 u8 sw_port_id_aware;
769 u8 rsv2;
770 u8 i_port_bitmap;
771 u8 i_port_direction;
772 u8 rsv3[2];
773 };
774
775 struct hclge_vlan_filter_ctrl_cmd {
776 u8 vlan_type;
777 u8 vlan_fe;
778 u8 rsv1[2];
779 u8 vf_id;
780 u8 rsv2[19];
781 };
782
783 #define HCLGE_VLAN_ID_OFFSET_STEP 160
784 #define HCLGE_VLAN_BYTE_SIZE 8
785 #define HCLGE_VLAN_OFFSET_BITMAP \
786 (HCLGE_VLAN_ID_OFFSET_STEP / HCLGE_VLAN_BYTE_SIZE)
787
788 struct hclge_vlan_filter_pf_cfg_cmd {
789 u8 vlan_offset;
790 u8 vlan_cfg;
791 u8 rsv[2];
792 u8 vlan_offset_bitmap[HCLGE_VLAN_OFFSET_BITMAP];
793 };
794
795 #define HCLGE_MAX_VF_BYTES 16
796
797 struct hclge_vlan_filter_vf_cfg_cmd {
798 __le16 vlan_id;
799 u8 resp_code;
800 u8 rsv;
801 u8 vlan_cfg;
802 u8 rsv1[3];
803 u8 vf_bitmap[HCLGE_MAX_VF_BYTES];
804 };
805
806 #define HCLGE_SWITCH_ANTI_SPOOF_B 0U
807 #define HCLGE_SWITCH_ALW_LPBK_B 1U
808 #define HCLGE_SWITCH_ALW_LCL_LPBK_B 2U
809 #define HCLGE_SWITCH_ALW_DST_OVRD_B 3U
810 #define HCLGE_SWITCH_NO_MASK 0x0
811 #define HCLGE_SWITCH_ANTI_SPOOF_MASK 0xFE
812 #define HCLGE_SWITCH_ALW_LPBK_MASK 0xFD
813 #define HCLGE_SWITCH_ALW_LCL_LPBK_MASK 0xFB
814 #define HCLGE_SWITCH_LW_DST_OVRD_MASK 0xF7
815
816 struct hclge_mac_vlan_switch_cmd {
817 u8 roce_sel;
818 u8 rsv1[3];
819 __le32 func_id;
820 u8 switch_param;
821 u8 rsv2[3];
822 u8 param_mask;
823 u8 rsv3[11];
824 };
825
826 enum hclge_mac_vlan_cfg_sel {
827 HCLGE_MAC_VLAN_NIC_SEL = 0,
828 HCLGE_MAC_VLAN_ROCE_SEL,
829 };
830
831 #define HCLGE_ACCEPT_TAG1_B 0
832 #define HCLGE_ACCEPT_UNTAG1_B 1
833 #define HCLGE_PORT_INS_TAG1_EN_B 2
834 #define HCLGE_PORT_INS_TAG2_EN_B 3
835 #define HCLGE_CFG_NIC_ROCE_SEL_B 4
836 #define HCLGE_ACCEPT_TAG2_B 5
837 #define HCLGE_ACCEPT_UNTAG2_B 6
838 #define HCLGE_TAG_SHIFT_MODE_EN_B 7
839 #define HCLGE_VF_NUM_PER_BYTE 8
840
841 struct hclge_vport_vtag_tx_cfg_cmd {
842 u8 vport_vlan_cfg;
843 u8 vf_offset;
844 u8 rsv1[2];
845 __le16 def_vlan_tag1;
846 __le16 def_vlan_tag2;
847 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
848 u8 rsv2[8];
849 };
850
851 #define HCLGE_REM_TAG1_EN_B 0
852 #define HCLGE_REM_TAG2_EN_B 1
853 #define HCLGE_SHOW_TAG1_EN_B 2
854 #define HCLGE_SHOW_TAG2_EN_B 3
855 #define HCLGE_DISCARD_TAG1_EN_B 5
856 #define HCLGE_DISCARD_TAG2_EN_B 6
857 struct hclge_vport_vtag_rx_cfg_cmd {
858 u8 vport_vlan_cfg;
859 u8 vf_offset;
860 u8 rsv1[6];
861 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
862 u8 rsv2[8];
863 };
864
865 struct hclge_tx_vlan_type_cfg_cmd {
866 __le16 ot_vlan_type;
867 __le16 in_vlan_type;
868 u8 rsv[20];
869 };
870
871 struct hclge_rx_vlan_type_cfg_cmd {
872 __le16 ot_fst_vlan_type;
873 __le16 ot_sec_vlan_type;
874 __le16 in_fst_vlan_type;
875 __le16 in_sec_vlan_type;
876 u8 rsv[16];
877 };
878
879 struct hclge_cfg_com_tqp_queue_cmd {
880 __le16 tqp_id;
881 __le16 stream_id;
882 u8 enable;
883 u8 rsv[19];
884 };
885
886 struct hclge_cfg_tx_queue_pointer_cmd {
887 __le16 tqp_id;
888 __le16 tx_tail;
889 __le16 tx_head;
890 __le16 fbd_num;
891 __le16 ring_offset;
892 u8 rsv[14];
893 };
894
895 #pragma pack(1)
896 struct hclge_mac_ethertype_idx_rd_cmd {
897 u8 flags;
898 u8 resp_code;
899 __le16 vlan_tag;
900 u8 mac_addr[ETH_ALEN];
901 __le16 index;
902 __le16 ethter_type;
903 __le16 egress_port;
904 __le16 egress_queue;
905 __le16 rev0;
906 u8 i_port_bitmap;
907 u8 i_port_direction;
908 u8 rev1[2];
909 };
910
911 #pragma pack()
912
913 #define HCLGE_TSO_MSS_MIN_S 0
914 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0)
915
916 #define HCLGE_TSO_MSS_MAX_S 16
917 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16)
918
919 struct hclge_cfg_tso_status_cmd {
920 __le16 tso_mss_min;
921 __le16 tso_mss_max;
922 u8 rsv[20];
923 };
924
925 #define HCLGE_GRO_EN_B 0
926 struct hclge_cfg_gro_status_cmd {
927 u8 gro_en;
928 u8 rsv[23];
929 };
930
931 #define HCLGE_TSO_MSS_MIN 256
932 #define HCLGE_TSO_MSS_MAX 9668
933
934 #define HCLGE_TQP_RESET_B 0
935 struct hclge_reset_tqp_queue_cmd {
936 __le16 tqp_id;
937 u8 reset_req;
938 u8 ready_to_reset;
939 u8 rsv[20];
940 };
941
942 #define HCLGE_CFG_RESET_MAC_B 3
943 #define HCLGE_CFG_RESET_FUNC_B 7
944 struct hclge_reset_cmd {
945 u8 mac_func_reset;
946 u8 fun_reset_vfid;
947 u8 rsv[22];
948 };
949
950 #define HCLGE_PF_RESET_DONE_BIT BIT(0)
951
952 struct hclge_pf_rst_done_cmd {
953 u8 pf_rst_done;
954 u8 rsv[23];
955 };
956
957 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0)
958 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2)
959 #define HCLGE_CMD_SERDES_DONE_B BIT(0)
960 #define HCLGE_CMD_SERDES_SUCCESS_B BIT(1)
961 struct hclge_serdes_lb_cmd {
962 u8 mask;
963 u8 enable;
964 u8 result;
965 u8 rsv[21];
966 };
967
968 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */
969 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
970 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */
971 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */
972 #define HCLGE_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */
973
974 #define HCLGE_TYPE_CRQ 0
975 #define HCLGE_TYPE_CSQ 1
976 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000
977 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004
978 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008
979 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010
980 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014
981 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018
982 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c
983 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020
984 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024
985 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028
986
987 /* this bit indicates that the driver is ready for hardware reset */
988 #define HCLGE_NIC_SW_RST_RDY_B 16
989 #define HCLGE_NIC_SW_RST_RDY BIT(HCLGE_NIC_SW_RST_RDY_B)
990
991 #define HCLGE_NIC_CMQ_DESC_NUM 1024
992 #define HCLGE_NIC_CMQ_DESC_NUM_S 3
993
994 #define HCLGE_LED_LOCATE_STATE_S 0
995 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0)
996
997 struct hclge_set_led_state_cmd {
998 u8 rsv1[3];
999 u8 locate_led_config;
1000 u8 rsv2[20];
1001 };
1002
1003 struct hclge_get_fd_mode_cmd {
1004 u8 mode;
1005 u8 enable;
1006 u8 rsv[22];
1007 };
1008
1009 struct hclge_get_fd_allocation_cmd {
1010 __le32 stage1_entry_num;
1011 __le32 stage2_entry_num;
1012 __le16 stage1_counter_num;
1013 __le16 stage2_counter_num;
1014 u8 rsv[12];
1015 };
1016
1017 struct hclge_set_fd_key_config_cmd {
1018 u8 stage;
1019 u8 key_select;
1020 u8 inner_sipv6_word_en;
1021 u8 inner_dipv6_word_en;
1022 u8 outer_sipv6_word_en;
1023 u8 outer_dipv6_word_en;
1024 u8 rsv1[2];
1025 __le32 tuple_mask;
1026 __le32 meta_data_mask;
1027 u8 rsv2[8];
1028 };
1029
1030 #define HCLGE_FD_EPORT_SW_EN_B 0
1031 struct hclge_fd_tcam_config_1_cmd {
1032 u8 stage;
1033 u8 xy_sel;
1034 u8 port_info;
1035 u8 rsv1[1];
1036 __le32 index;
1037 u8 entry_vld;
1038 u8 rsv2[7];
1039 u8 tcam_data[8];
1040 };
1041
1042 struct hclge_fd_tcam_config_2_cmd {
1043 u8 tcam_data[24];
1044 };
1045
1046 struct hclge_fd_tcam_config_3_cmd {
1047 u8 tcam_data[20];
1048 u8 rsv[4];
1049 };
1050
1051 #define HCLGE_FD_AD_DROP_B 0
1052 #define HCLGE_FD_AD_DIRECT_QID_B 1
1053 #define HCLGE_FD_AD_QID_S 2
1054 #define HCLGE_FD_AD_QID_M GENMASK(11, 2)
1055 #define HCLGE_FD_AD_USE_COUNTER_B 12
1056 #define HCLGE_FD_AD_COUNTER_NUM_S 13
1057 #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13)
1058 #define HCLGE_FD_AD_NXT_STEP_B 20
1059 #define HCLGE_FD_AD_NXT_KEY_S 21
1060 #define HCLGE_FD_AD_NXT_KEY_M GENMASK(25, 21)
1061 #define HCLGE_FD_AD_WR_RULE_ID_B 0
1062 #define HCLGE_FD_AD_RULE_ID_S 1
1063 #define HCLGE_FD_AD_RULE_ID_M GENMASK(12, 1)
1064 #define HCLGE_FD_AD_TC_OVRD_B 16
1065 #define HCLGE_FD_AD_TC_SIZE_S 17
1066 #define HCLGE_FD_AD_TC_SIZE_M GENMASK(20, 17)
1067
1068 struct hclge_fd_ad_config_cmd {
1069 u8 stage;
1070 u8 rsv1[3];
1071 __le32 index;
1072 __le64 ad_data;
1073 u8 rsv2[8];
1074 };
1075
1076 struct hclge_get_m7_bd_cmd {
1077 __le32 bd_num;
1078 u8 rsv[20];
1079 };
1080
1081 struct hclge_query_ppu_pf_other_int_dfx_cmd {
1082 __le16 over_8bd_no_fe_qid;
1083 __le16 over_8bd_no_fe_vf_id;
1084 __le16 tso_mss_cmp_min_err_qid;
1085 __le16 tso_mss_cmp_min_err_vf_id;
1086 __le16 tso_mss_cmp_max_err_qid;
1087 __le16 tso_mss_cmp_max_err_vf_id;
1088 __le16 tx_rd_fbd_poison_qid;
1089 __le16 tx_rd_fbd_poison_vf_id;
1090 __le16 rx_rd_fbd_poison_qid;
1091 __le16 rx_rd_fbd_poison_vf_id;
1092 u8 rsv[4];
1093 };
1094
1095 #define HCLGE_LINK_EVENT_REPORT_EN_B 0
1096 #define HCLGE_NCSI_ERROR_REPORT_EN_B 1
1097 struct hclge_firmware_compat_cmd {
1098 __le32 compat;
1099 u8 rsv[20];
1100 };
1101
1102 #define HCLGE_SFP_INFO_CMD_NUM 6
1103 #define HCLGE_SFP_INFO_BD0_LEN 20
1104 #define HCLGE_SFP_INFO_BDX_LEN 24
1105 #define HCLGE_SFP_INFO_MAX_LEN \
1106 (HCLGE_SFP_INFO_BD0_LEN + \
1107 (HCLGE_SFP_INFO_CMD_NUM - 1) * HCLGE_SFP_INFO_BDX_LEN)
1108
1109 struct hclge_sfp_info_bd0_cmd {
1110 __le16 offset;
1111 __le16 read_len;
1112 u8 data[HCLGE_SFP_INFO_BD0_LEN];
1113 };
1114
1115 #define HCLGE_QUERY_DEV_SPECS_BD_NUM 4
1116
1117 struct hclge_dev_specs_0_cmd {
1118 __le32 rsv0;
1119 __le32 mac_entry_num;
1120 __le32 mng_entry_num;
1121 __le16 rss_ind_tbl_size;
1122 __le16 rss_key_size;
1123 __le16 int_ql_max;
1124 u8 max_non_tso_bd_num;
1125 u8 rsv1;
1126 __le32 max_tm_rate;
1127 };
1128
1129 #define HCLGE_DEF_MAX_INT_GL 0x1FE0U
1130
1131 struct hclge_dev_specs_1_cmd {
1132 __le32 rsv0;
1133 __le16 max_int_gl;
1134 u8 rsv1[18];
1135 };
1136
1137 int hclge_cmd_init(struct hclge_dev *hdev);
1138 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
1139 {
1140 writel(value, base + reg);
1141 }
1142
1143 #define hclge_write_dev(a, reg, value) \
1144 hclge_write_reg((a)->io_base, (reg), (value))
1145 #define hclge_read_dev(a, reg) \
1146 hclge_read_reg((a)->io_base, (reg))
1147
1148 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg)
1149 {
1150 u8 __iomem *reg_addr = READ_ONCE(base);
1151
1152 return readl(reg_addr + reg);
1153 }
1154
1155 #define HCLGE_SEND_SYNC(flag) \
1156 ((flag) & HCLGE_CMD_FLAG_NO_INTR)
1157
1158 struct hclge_hw;
1159 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num);
1160 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
1161 enum hclge_opcode_type opcode, bool is_read);
1162 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
1163
1164 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
1165 struct hclge_desc *desc);
1166 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
1167 struct hclge_desc *desc);
1168
1169 void hclge_cmd_uninit(struct hclge_dev *hdev);
1170 int hclge_cmd_queue_init(struct hclge_dev *hdev);
1171 #endif
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