1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
6 #include <linux/types.h>
9 #define HCLGE_CMDQ_TX_TIMEOUT 30000
15 #define HCLGE_CMDQ_RX_INVLD_B 0
16 #define HCLGE_CMDQ_RX_OUTVLD_B 1
24 struct hclge_cmq_ring
{
25 dma_addr_t desc_dma_addr
;
26 struct hclge_desc
*desc
;
27 struct hclge_dev
*dev
;
35 u8 ring_type
; /* cmq ring type */
36 spinlock_t lock
; /* Command queue lock */
39 enum hclge_cmd_return_status
{
40 HCLGE_CMD_EXEC_SUCCESS
= 0,
41 HCLGE_CMD_NO_AUTH
= 1,
42 HCLGE_CMD_NOT_SUPPORTED
= 2,
43 HCLGE_CMD_QUEUE_FULL
= 3,
44 HCLGE_CMD_NEXT_ERR
= 4,
45 HCLGE_CMD_UNEXE_ERR
= 5,
46 HCLGE_CMD_PARA_ERR
= 6,
47 HCLGE_CMD_RESULT_ERR
= 7,
48 HCLGE_CMD_TIMEOUT
= 8,
49 HCLGE_CMD_HILINK_ERR
= 9,
50 HCLGE_CMD_QUEUE_ILLEGAL
= 10,
51 HCLGE_CMD_INVALID
= 11,
54 enum hclge_cmd_status
{
55 HCLGE_STATUS_SUCCESS
= 0,
56 HCLGE_ERR_CSQ_FULL
= -1,
57 HCLGE_ERR_CSQ_TIMEOUT
= -2,
58 HCLGE_ERR_CSQ_ERROR
= -3,
61 struct hclge_misc_vector
{
67 struct hclge_cmq_ring csq
;
68 struct hclge_cmq_ring crq
;
70 enum hclge_cmd_status last_status
;
73 #define HCLGE_CMD_FLAG_IN BIT(0)
74 #define HCLGE_CMD_FLAG_OUT BIT(1)
75 #define HCLGE_CMD_FLAG_NEXT BIT(2)
76 #define HCLGE_CMD_FLAG_WR BIT(3)
77 #define HCLGE_CMD_FLAG_NO_INTR BIT(4)
78 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5)
80 enum hclge_opcode_type
{
81 /* Generic commands */
82 HCLGE_OPC_QUERY_FW_VER
= 0x0001,
83 HCLGE_OPC_CFG_RST_TRIGGER
= 0x0020,
84 HCLGE_OPC_GBL_RST_STATUS
= 0x0021,
85 HCLGE_OPC_QUERY_FUNC_STATUS
= 0x0022,
86 HCLGE_OPC_QUERY_PF_RSRC
= 0x0023,
87 HCLGE_OPC_QUERY_VF_RSRC
= 0x0024,
88 HCLGE_OPC_GET_CFG_PARAM
= 0x0025,
90 HCLGE_OPC_STATS_64_BIT
= 0x0030,
91 HCLGE_OPC_STATS_32_BIT
= 0x0031,
92 HCLGE_OPC_STATS_MAC
= 0x0032,
93 HCLGE_OPC_QUERY_MAC_REG_NUM
= 0x0033,
94 HCLGE_OPC_STATS_MAC_ALL
= 0x0034,
96 HCLGE_OPC_QUERY_REG_NUM
= 0x0040,
97 HCLGE_OPC_QUERY_32_BIT_REG
= 0x0041,
98 HCLGE_OPC_QUERY_64_BIT_REG
= 0x0042,
99 HCLGE_OPC_DFX_BD_NUM
= 0x0043,
100 HCLGE_OPC_DFX_BIOS_COMMON_REG
= 0x0044,
101 HCLGE_OPC_DFX_SSU_REG_0
= 0x0045,
102 HCLGE_OPC_DFX_SSU_REG_1
= 0x0046,
103 HCLGE_OPC_DFX_IGU_EGU_REG
= 0x0047,
104 HCLGE_OPC_DFX_RPU_REG_0
= 0x0048,
105 HCLGE_OPC_DFX_RPU_REG_1
= 0x0049,
106 HCLGE_OPC_DFX_NCSI_REG
= 0x004A,
107 HCLGE_OPC_DFX_RTC_REG
= 0x004B,
108 HCLGE_OPC_DFX_PPP_REG
= 0x004C,
109 HCLGE_OPC_DFX_RCB_REG
= 0x004D,
110 HCLGE_OPC_DFX_TQP_REG
= 0x004E,
111 HCLGE_OPC_DFX_SSU_REG_2
= 0x004F,
112 HCLGE_OPC_DFX_QUERY_CHIP_CAP
= 0x0050,
115 HCLGE_OPC_CONFIG_MAC_MODE
= 0x0301,
116 HCLGE_OPC_CONFIG_AN_MODE
= 0x0304,
117 HCLGE_OPC_QUERY_LINK_STATUS
= 0x0307,
118 HCLGE_OPC_CONFIG_MAX_FRM_SIZE
= 0x0308,
119 HCLGE_OPC_CONFIG_SPEED_DUP
= 0x0309,
120 HCLGE_OPC_QUERY_MAC_TNL_INT
= 0x0310,
121 HCLGE_OPC_MAC_TNL_INT_EN
= 0x0311,
122 HCLGE_OPC_CLEAR_MAC_TNL_INT
= 0x0312,
123 HCLGE_OPC_SERDES_LOOPBACK
= 0x0315,
124 HCLGE_OPC_CONFIG_FEC_MODE
= 0x031A,
126 /* PFC/Pause commands */
127 HCLGE_OPC_CFG_MAC_PAUSE_EN
= 0x0701,
128 HCLGE_OPC_CFG_PFC_PAUSE_EN
= 0x0702,
129 HCLGE_OPC_CFG_MAC_PARA
= 0x0703,
130 HCLGE_OPC_CFG_PFC_PARA
= 0x0704,
131 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT
= 0x0705,
132 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT
= 0x0706,
133 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT
= 0x0707,
134 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT
= 0x0708,
135 HCLGE_OPC_PRI_TO_TC_MAPPING
= 0x0709,
136 HCLGE_OPC_QOS_MAP
= 0x070A,
138 /* ETS/scheduler commands */
139 HCLGE_OPC_TM_PG_TO_PRI_LINK
= 0x0804,
140 HCLGE_OPC_TM_QS_TO_PRI_LINK
= 0x0805,
141 HCLGE_OPC_TM_NQ_TO_QS_LINK
= 0x0806,
142 HCLGE_OPC_TM_RQ_TO_QS_LINK
= 0x0807,
143 HCLGE_OPC_TM_PORT_WEIGHT
= 0x0808,
144 HCLGE_OPC_TM_PG_WEIGHT
= 0x0809,
145 HCLGE_OPC_TM_QS_WEIGHT
= 0x080A,
146 HCLGE_OPC_TM_PRI_WEIGHT
= 0x080B,
147 HCLGE_OPC_TM_PRI_C_SHAPPING
= 0x080C,
148 HCLGE_OPC_TM_PRI_P_SHAPPING
= 0x080D,
149 HCLGE_OPC_TM_PG_C_SHAPPING
= 0x080E,
150 HCLGE_OPC_TM_PG_P_SHAPPING
= 0x080F,
151 HCLGE_OPC_TM_PORT_SHAPPING
= 0x0810,
152 HCLGE_OPC_TM_PG_SCH_MODE_CFG
= 0x0812,
153 HCLGE_OPC_TM_PRI_SCH_MODE_CFG
= 0x0813,
154 HCLGE_OPC_TM_QS_SCH_MODE_CFG
= 0x0814,
155 HCLGE_OPC_TM_BP_TO_QSET_MAPPING
= 0x0815,
156 HCLGE_OPC_ETS_TC_WEIGHT
= 0x0843,
157 HCLGE_OPC_QSET_DFX_STS
= 0x0844,
158 HCLGE_OPC_PRI_DFX_STS
= 0x0845,
159 HCLGE_OPC_PG_DFX_STS
= 0x0846,
160 HCLGE_OPC_PORT_DFX_STS
= 0x0847,
161 HCLGE_OPC_SCH_NQ_CNT
= 0x0848,
162 HCLGE_OPC_SCH_RQ_CNT
= 0x0849,
163 HCLGE_OPC_TM_INTERNAL_STS
= 0x0850,
164 HCLGE_OPC_TM_INTERNAL_CNT
= 0x0851,
165 HCLGE_OPC_TM_INTERNAL_STS_1
= 0x0852,
167 /* Packet buffer allocate commands */
168 HCLGE_OPC_TX_BUFF_ALLOC
= 0x0901,
169 HCLGE_OPC_RX_PRIV_BUFF_ALLOC
= 0x0902,
170 HCLGE_OPC_RX_PRIV_WL_ALLOC
= 0x0903,
171 HCLGE_OPC_RX_COM_THRD_ALLOC
= 0x0904,
172 HCLGE_OPC_RX_COM_WL_ALLOC
= 0x0905,
173 HCLGE_OPC_RX_GBL_PKT_CNT
= 0x0906,
175 /* TQP management command */
176 HCLGE_OPC_SET_TQP_MAP
= 0x0A01,
179 HCLGE_OPC_CFG_TX_QUEUE
= 0x0B01,
180 HCLGE_OPC_QUERY_TX_POINTER
= 0x0B02,
181 HCLGE_OPC_QUERY_TX_STATUS
= 0x0B03,
182 HCLGE_OPC_TQP_TX_QUEUE_TC
= 0x0B04,
183 HCLGE_OPC_CFG_RX_QUEUE
= 0x0B11,
184 HCLGE_OPC_QUERY_RX_POINTER
= 0x0B12,
185 HCLGE_OPC_QUERY_RX_STATUS
= 0x0B13,
186 HCLGE_OPC_STASH_RX_QUEUE_LRO
= 0x0B16,
187 HCLGE_OPC_CFG_RX_QUEUE_LRO
= 0x0B17,
188 HCLGE_OPC_CFG_COM_TQP_QUEUE
= 0x0B20,
189 HCLGE_OPC_RESET_TQP_QUEUE
= 0x0B22,
192 HCLGE_OPC_PPU_PF_OTHER_INT_DFX
= 0x0B4A,
195 HCLGE_OPC_TSO_GENERIC_CONFIG
= 0x0C01,
196 HCLGE_OPC_GRO_GENERIC_CONFIG
= 0x0C10,
199 HCLGE_OPC_RSS_GENERIC_CONFIG
= 0x0D01,
200 HCLGE_OPC_RSS_INDIR_TABLE
= 0x0D07,
201 HCLGE_OPC_RSS_TC_MODE
= 0x0D08,
202 HCLGE_OPC_RSS_INPUT_TUPLE
= 0x0D02,
204 /* Promisuous mode command */
205 HCLGE_OPC_CFG_PROMISC_MODE
= 0x0E01,
207 /* Vlan offload commands */
208 HCLGE_OPC_VLAN_PORT_TX_CFG
= 0x0F01,
209 HCLGE_OPC_VLAN_PORT_RX_CFG
= 0x0F02,
211 /* Interrupts commands */
212 HCLGE_OPC_ADD_RING_TO_VECTOR
= 0x1503,
213 HCLGE_OPC_DEL_RING_TO_VECTOR
= 0x1504,
216 HCLGE_OPC_MAC_VLAN_ADD
= 0x1000,
217 HCLGE_OPC_MAC_VLAN_REMOVE
= 0x1001,
218 HCLGE_OPC_MAC_VLAN_TYPE_ID
= 0x1002,
219 HCLGE_OPC_MAC_VLAN_INSERT
= 0x1003,
220 HCLGE_OPC_MAC_VLAN_ALLOCATE
= 0x1004,
221 HCLGE_OPC_MAC_ETHTYPE_ADD
= 0x1010,
222 HCLGE_OPC_MAC_ETHTYPE_REMOVE
= 0x1011,
225 HCLGE_OPC_VLAN_FILTER_CTRL
= 0x1100,
226 HCLGE_OPC_VLAN_FILTER_PF_CFG
= 0x1101,
227 HCLGE_OPC_VLAN_FILTER_VF_CFG
= 0x1102,
229 /* Flow Director commands */
230 HCLGE_OPC_FD_MODE_CTRL
= 0x1200,
231 HCLGE_OPC_FD_GET_ALLOCATION
= 0x1201,
232 HCLGE_OPC_FD_KEY_CONFIG
= 0x1202,
233 HCLGE_OPC_FD_TCAM_OP
= 0x1203,
234 HCLGE_OPC_FD_AD_OP
= 0x1204,
237 HCLGE_OPC_MDIO_CONFIG
= 0x1900,
240 HCLGE_OPC_QCN_MOD_CFG
= 0x1A01,
241 HCLGE_OPC_QCN_GRP_TMPLT_CFG
= 0x1A02,
242 HCLGE_OPC_QCN_SHAPPING_IR_CFG
= 0x1A03,
243 HCLGE_OPC_QCN_SHAPPING_BS_CFG
= 0x1A04,
244 HCLGE_OPC_QCN_QSET_LINK_CFG
= 0x1A05,
245 HCLGE_OPC_QCN_RP_STATUS_GET
= 0x1A06,
246 HCLGE_OPC_QCN_AJUST_INIT
= 0x1A07,
247 HCLGE_OPC_QCN_DFX_CNT_STATUS
= 0x1A08,
249 /* Mailbox command */
250 HCLGEVF_OPC_MBX_PF_TO_VF
= 0x2000,
253 HCLGE_OPC_LED_STATUS_CFG
= 0xB000,
255 /* NCL config command */
256 HCLGE_OPC_QUERY_NCL_CONFIG
= 0x7011,
257 /* M7 stats command */
258 HCLGE_OPC_M7_STATS_BD
= 0x7012,
259 HCLGE_OPC_M7_STATS_INFO
= 0x7013,
262 HCLGE_OPC_GET_SFP_INFO
= 0x7104,
264 /* Error INT commands */
265 HCLGE_MAC_COMMON_INT_EN
= 0x030E,
266 HCLGE_TM_SCH_ECC_INT_EN
= 0x0829,
267 HCLGE_SSU_ECC_INT_CMD
= 0x0989,
268 HCLGE_SSU_COMMON_INT_CMD
= 0x098C,
269 HCLGE_PPU_MPF_ECC_INT_CMD
= 0x0B40,
270 HCLGE_PPU_MPF_OTHER_INT_CMD
= 0x0B41,
271 HCLGE_PPU_PF_OTHER_INT_CMD
= 0x0B42,
272 HCLGE_COMMON_ECC_INT_CFG
= 0x1505,
273 HCLGE_QUERY_RAS_INT_STS_BD_NUM
= 0x1510,
274 HCLGE_QUERY_CLEAR_MPF_RAS_INT
= 0x1511,
275 HCLGE_QUERY_CLEAR_PF_RAS_INT
= 0x1512,
276 HCLGE_QUERY_MSIX_INT_STS_BD_NUM
= 0x1513,
277 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT
= 0x1514,
278 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT
= 0x1515,
279 HCLGE_CONFIG_ROCEE_RAS_INT_EN
= 0x1580,
280 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT
= 0x1581,
281 HCLGE_ROCEE_PF_RAS_INT_CMD
= 0x1584,
282 HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD
= 0x1585,
283 HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD
= 0x1586,
284 HCLGE_IGU_EGU_TNL_INT_EN
= 0x1803,
285 HCLGE_IGU_COMMON_INT_EN
= 0x1806,
286 HCLGE_TM_QCN_MEM_INT_CFG
= 0x1A14,
287 HCLGE_PPP_CMD0_INT_CMD
= 0x2100,
288 HCLGE_PPP_CMD1_INT_CMD
= 0x2101,
289 HCLGE_MAC_ETHERTYPE_IDX_RD
= 0x2105,
290 HCLGE_NCSI_INT_EN
= 0x2401,
293 #define HCLGE_TQP_REG_OFFSET 0x80000
294 #define HCLGE_TQP_REG_SIZE 0x200
296 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10
297 #define HCLGE_RCB_INIT_FLAG_EN_B 0
298 #define HCLGE_RCB_INIT_FLAG_FINI_B 8
299 struct hclge_config_rcb_init_cmd
{
300 __le16 rcb_init_flag
;
304 struct hclge_tqp_map_cmd
{
305 __le16 tqp_id
; /* Absolute tqp id for in this pf */
306 u8 tqp_vf
; /* VF id */
307 #define HCLGE_TQP_MAP_TYPE_PF 0
308 #define HCLGE_TQP_MAP_TYPE_VF 1
309 #define HCLGE_TQP_MAP_TYPE_B 0
310 #define HCLGE_TQP_MAP_EN_B 1
311 u8 tqp_flag
; /* Indicate it's pf or vf tqp */
312 __le16 tqp_vid
; /* Virtual id in this pf/vf */
316 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10
318 enum hclge_int_type
{
324 struct hclge_ctrl_vector_chain_cmd
{
327 #define HCLGE_INT_TYPE_S 0
328 #define HCLGE_INT_TYPE_M GENMASK(1, 0)
329 #define HCLGE_TQP_ID_S 2
330 #define HCLGE_TQP_ID_M GENMASK(12, 2)
331 #define HCLGE_INT_GL_IDX_S 13
332 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13)
333 __le16 tqp_type_and_id
[HCLGE_VECTOR_ELEMENTS_PER_CMD
];
338 #define HCLGE_MAX_TC_NUM 8
339 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */
340 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */
341 struct hclge_tx_buff_alloc_cmd
{
342 __le16 tx_pkt_buff
[HCLGE_MAX_TC_NUM
];
346 struct hclge_rx_priv_buff_cmd
{
347 __le16 buf_num
[HCLGE_MAX_TC_NUM
];
352 struct hclge_query_version_cmd
{
354 __le32 firmware_rsv
[5];
357 #define HCLGE_RX_PRIV_EN_B 15
358 #define HCLGE_TC_NUM_ONE_DESC 4
359 struct hclge_priv_wl
{
364 struct hclge_rx_priv_wl_buf
{
365 struct hclge_priv_wl tc_wl
[HCLGE_TC_NUM_ONE_DESC
];
368 struct hclge_rx_com_thrd
{
369 struct hclge_priv_wl com_thrd
[HCLGE_TC_NUM_ONE_DESC
];
372 struct hclge_rx_com_wl
{
373 struct hclge_priv_wl com_wl
;
376 struct hclge_waterline
{
381 struct hclge_tc_thrd
{
386 struct hclge_priv_buf
{
387 struct hclge_waterline wl
; /* Waterline for low and high*/
388 u32 buf_size
; /* TC private buffer size */
390 u32 enable
; /* Enable TC private buffer or not */
393 struct hclge_shared_buf
{
394 struct hclge_waterline self
;
395 struct hclge_tc_thrd tc_thrd
[HCLGE_MAX_TC_NUM
];
399 struct hclge_pkt_buf_alloc
{
400 struct hclge_priv_buf priv_buf
[HCLGE_MAX_TC_NUM
];
401 struct hclge_shared_buf s_buf
;
404 #define HCLGE_RX_COM_WL_EN_B 15
405 struct hclge_rx_com_wl_buf_cmd
{
411 #define HCLGE_RX_PKT_EN_B 15
412 struct hclge_rx_pkt_buf_cmd
{
418 #define HCLGE_PF_STATE_DONE_B 0
419 #define HCLGE_PF_STATE_MAIN_B 1
420 #define HCLGE_PF_STATE_BOND_B 2
421 #define HCLGE_PF_STATE_MAC_N_B 6
422 #define HCLGE_PF_MAC_NUM_MASK 0x3
423 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B)
424 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B)
425 struct hclge_func_status_cmd
{
426 __le32 vf_rst_state
[4];
436 struct hclge_pf_res_cmd
{
439 __le16 msixcap_localid_ba_nic
;
440 __le16 msixcap_localid_ba_rocee
;
441 #define HCLGE_MSIX_OFT_ROCEE_S 0
442 #define HCLGE_MSIX_OFT_ROCEE_M GENMASK(15, 0)
443 #define HCLGE_PF_VEC_NUM_S 0
444 #define HCLGE_PF_VEC_NUM_M GENMASK(7, 0)
445 __le16 pf_intr_vector_number
;
446 __le16 pf_own_fun_number
;
452 #define HCLGE_CFG_OFFSET_S 0
453 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0)
454 #define HCLGE_CFG_RD_LEN_S 24
455 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24)
456 #define HCLGE_CFG_RD_LEN_BYTES 16
457 #define HCLGE_CFG_RD_LEN_UNIT 4
459 #define HCLGE_CFG_VMDQ_S 0
460 #define HCLGE_CFG_VMDQ_M GENMASK(7, 0)
461 #define HCLGE_CFG_TC_NUM_S 8
462 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8)
463 #define HCLGE_CFG_TQP_DESC_N_S 16
464 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16)
465 #define HCLGE_CFG_PHY_ADDR_S 0
466 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0)
467 #define HCLGE_CFG_MEDIA_TP_S 8
468 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8)
469 #define HCLGE_CFG_RX_BUF_LEN_S 16
470 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16)
471 #define HCLGE_CFG_MAC_ADDR_H_S 0
472 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0)
473 #define HCLGE_CFG_DEFAULT_SPEED_S 16
474 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16)
475 #define HCLGE_CFG_RSS_SIZE_S 24
476 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24)
477 #define HCLGE_CFG_SPEED_ABILITY_S 0
478 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0)
479 #define HCLGE_CFG_UMV_TBL_SPACE_S 16
480 #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16)
482 struct hclge_cfg_param_cmd
{
488 #define HCLGE_MAC_MODE 0x0
489 #define HCLGE_DESC_NUM 0x40
491 #define HCLGE_ALLOC_VALID_B 0
492 struct hclge_vf_num_cmd
{
497 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4
498 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4
499 #define HCLGE_RSS_HASH_KEY_NUM 16
500 struct hclge_rss_config_cmd
{
503 u8 hash_key
[HCLGE_RSS_HASH_KEY_NUM
];
506 struct hclge_rss_input_tuple_cmd
{
518 #define HCLGE_RSS_CFG_TBL_SIZE 16
520 struct hclge_rss_indirection_table_cmd
{
521 __le16 start_table_index
;
522 __le16 rss_set_bitmap
;
524 u8 rss_result
[HCLGE_RSS_CFG_TBL_SIZE
];
527 #define HCLGE_RSS_TC_OFFSET_S 0
528 #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0)
529 #define HCLGE_RSS_TC_SIZE_S 12
530 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12)
531 #define HCLGE_RSS_TC_VALID_B 15
532 struct hclge_rss_tc_mode_cmd
{
533 __le16 rss_tc_mode
[HCLGE_MAX_TC_NUM
];
537 #define HCLGE_LINK_STATUS_UP_B 0
538 #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B)
539 struct hclge_link_status_cmd
{
544 struct hclge_promisc_param
{
549 #define HCLGE_PROMISC_TX_EN_B BIT(4)
550 #define HCLGE_PROMISC_RX_EN_B BIT(5)
551 #define HCLGE_PROMISC_EN_B 1
552 #define HCLGE_PROMISC_EN_ALL 0x7
553 #define HCLGE_PROMISC_EN_UC 0x1
554 #define HCLGE_PROMISC_EN_MC 0x2
555 #define HCLGE_PROMISC_EN_BC 0x4
556 struct hclge_promisc_cfg_cmd
{
563 enum hclge_promisc_type
{
569 #define HCLGE_MAC_TX_EN_B 6
570 #define HCLGE_MAC_RX_EN_B 7
571 #define HCLGE_MAC_PAD_TX_B 11
572 #define HCLGE_MAC_PAD_RX_B 12
573 #define HCLGE_MAC_1588_TX_B 13
574 #define HCLGE_MAC_1588_RX_B 14
575 #define HCLGE_MAC_APP_LP_B 15
576 #define HCLGE_MAC_LINE_LP_B 16
577 #define HCLGE_MAC_FCS_TX_B 17
578 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18
579 #define HCLGE_MAC_RX_FCS_STRIP_B 19
580 #define HCLGE_MAC_RX_FCS_B 20
581 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21
582 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22
584 struct hclge_config_mac_mode_cmd
{
585 __le32 txrx_pad_fcs_loop_en
;
589 #define HCLGE_CFG_SPEED_S 0
590 #define HCLGE_CFG_SPEED_M GENMASK(5, 0)
592 #define HCLGE_CFG_DUPLEX_B 7
593 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B)
595 struct hclge_config_mac_speed_dup_cmd
{
598 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
599 u8 mac_change_fec_en
;
603 #define HCLGE_RING_ID_MASK GENMASK(9, 0)
604 #define HCLGE_TQP_ENABLE_B 0
606 #define HCLGE_MAC_CFG_AN_EN_B 0
607 #define HCLGE_MAC_CFG_AN_INT_EN_B 1
608 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2
609 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3
610 #define HCLGE_MAC_CFG_AN_RST_B 4
612 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B)
614 struct hclge_config_auto_neg_cmd
{
615 __le32 cfg_an_cmd_flag
;
619 struct hclge_sfp_info_cmd
{
621 u8 query_type
; /* 0: sfp speed, 1: active speed */
623 u8 autoneg
; /* autoneg state */
624 u8 autoneg_ability
; /* whether support autoneg */
625 __le32 speed_ability
; /* speed ability for current media */
630 #define HCLGE_MAC_CFG_FEC_AUTO_EN_B 0
631 #define HCLGE_MAC_CFG_FEC_MODE_S 1
632 #define HCLGE_MAC_CFG_FEC_MODE_M GENMASK(3, 1)
633 #define HCLGE_MAC_CFG_FEC_SET_DEF_B 0
634 #define HCLGE_MAC_CFG_FEC_CLR_DEF_B 1
636 #define HCLGE_MAC_FEC_OFF 0
637 #define HCLGE_MAC_FEC_BASER 1
638 #define HCLGE_MAC_FEC_RS 2
639 struct hclge_config_fec_cmd
{
645 #define HCLGE_MAC_UPLINK_PORT 0x100
647 struct hclge_config_max_frm_size_cmd
{
653 enum hclge_mac_vlan_tbl_opcode
{
654 HCLGE_MAC_VLAN_ADD
, /* Add new or modify mac_vlan */
655 HCLGE_MAC_VLAN_UPDATE
, /* Modify other fields of this table */
656 HCLGE_MAC_VLAN_REMOVE
, /* Remove a entry through mac_vlan key */
657 HCLGE_MAC_VLAN_LKUP
, /* Lookup a entry through mac_vlan key */
660 enum hclge_mac_vlan_add_resp_code
{
661 HCLGE_ADD_UC_OVERFLOW
= 2, /* ADD failed for UC overflow */
662 HCLGE_ADD_MC_OVERFLOW
, /* ADD failed for MC overflow */
665 #define HCLGE_MAC_VLAN_BIT0_EN_B 0
666 #define HCLGE_MAC_VLAN_BIT1_EN_B 1
667 #define HCLGE_MAC_EPORT_SW_EN_B 12
668 #define HCLGE_MAC_EPORT_TYPE_B 11
669 #define HCLGE_MAC_EPORT_VFID_S 3
670 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3)
671 #define HCLGE_MAC_EPORT_PFID_S 0
672 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0)
673 struct hclge_mac_vlan_tbl_entry_cmd
{
677 __le32 mac_addr_hi32
;
678 __le16 mac_addr_lo16
;
687 #define HCLGE_UMV_SPC_ALC_B 0
688 struct hclge_umv_spc_alc_cmd
{
695 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0)
696 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1)
697 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2)
699 struct hclge_mac_mgr_tbl_entry_cmd
{
703 __le32 mac_addr_hi32
;
704 __le16 mac_addr_lo16
;
716 struct hclge_mac_vlan_add_cmd
{
718 __le16 mac_addr_hi16
;
719 __le32 mac_addr_lo32
;
720 __le32 mac_addr_msk_hi32
;
721 __le16 mac_addr_msk_lo16
;
728 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0
729 struct hclge_mac_vlan_remove_cmd
{
731 __le16 mac_addr_hi16
;
732 __le32 mac_addr_lo32
;
733 __le32 mac_addr_msk_hi32
;
734 __le16 mac_addr_msk_lo16
;
741 struct hclge_vlan_filter_ctrl_cmd
{
749 struct hclge_vlan_filter_pf_cfg_cmd
{
753 u8 vlan_offset_bitmap
[20];
756 struct hclge_vlan_filter_vf_cfg_cmd
{
765 #define HCLGE_ACCEPT_TAG1_B 0
766 #define HCLGE_ACCEPT_UNTAG1_B 1
767 #define HCLGE_PORT_INS_TAG1_EN_B 2
768 #define HCLGE_PORT_INS_TAG2_EN_B 3
769 #define HCLGE_CFG_NIC_ROCE_SEL_B 4
770 #define HCLGE_ACCEPT_TAG2_B 5
771 #define HCLGE_ACCEPT_UNTAG2_B 6
773 struct hclge_vport_vtag_tx_cfg_cmd
{
777 __le16 def_vlan_tag1
;
778 __le16 def_vlan_tag2
;
783 #define HCLGE_REM_TAG1_EN_B 0
784 #define HCLGE_REM_TAG2_EN_B 1
785 #define HCLGE_SHOW_TAG1_EN_B 2
786 #define HCLGE_SHOW_TAG2_EN_B 3
787 struct hclge_vport_vtag_rx_cfg_cmd
{
795 struct hclge_tx_vlan_type_cfg_cmd
{
801 struct hclge_rx_vlan_type_cfg_cmd
{
802 __le16 ot_fst_vlan_type
;
803 __le16 ot_sec_vlan_type
;
804 __le16 in_fst_vlan_type
;
805 __le16 in_sec_vlan_type
;
809 struct hclge_cfg_com_tqp_queue_cmd
{
816 struct hclge_cfg_tx_queue_pointer_cmd
{
826 struct hclge_mac_ethertype_idx_rd_cmd
{
843 #define HCLGE_TSO_MSS_MIN_S 0
844 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0)
846 #define HCLGE_TSO_MSS_MAX_S 16
847 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16)
849 struct hclge_cfg_tso_status_cmd
{
855 #define HCLGE_GRO_EN_B 0
856 struct hclge_cfg_gro_status_cmd
{
861 #define HCLGE_TSO_MSS_MIN 256
862 #define HCLGE_TSO_MSS_MAX 9668
864 #define HCLGE_TQP_RESET_B 0
865 struct hclge_reset_tqp_queue_cmd
{
872 #define HCLGE_CFG_RESET_MAC_B 3
873 #define HCLGE_CFG_RESET_FUNC_B 7
874 struct hclge_reset_cmd
{
880 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0)
881 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2)
882 #define HCLGE_CMD_SERDES_DONE_B BIT(0)
883 #define HCLGE_CMD_SERDES_SUCCESS_B BIT(1)
884 struct hclge_serdes_lb_cmd
{
891 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */
892 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
893 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */
894 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */
895 #define HCLGE_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */
897 #define HCLGE_TYPE_CRQ 0
898 #define HCLGE_TYPE_CSQ 1
899 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000
900 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004
901 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008
902 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010
903 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014
904 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018
905 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c
906 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020
907 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024
908 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028
909 #define HCLGE_NIC_CMQ_EN_B 16
910 #define HCLGE_NIC_CMQ_ENABLE BIT(HCLGE_NIC_CMQ_EN_B)
911 #define HCLGE_NIC_CMQ_DESC_NUM 1024
912 #define HCLGE_NIC_CMQ_DESC_NUM_S 3
914 #define HCLGE_LED_LOCATE_STATE_S 0
915 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0)
917 struct hclge_set_led_state_cmd
{
919 u8 locate_led_config
;
923 struct hclge_get_fd_mode_cmd
{
929 struct hclge_get_fd_allocation_cmd
{
930 __le32 stage1_entry_num
;
931 __le32 stage2_entry_num
;
932 __le16 stage1_counter_num
;
933 __le16 stage2_counter_num
;
937 struct hclge_set_fd_key_config_cmd
{
940 u8 inner_sipv6_word_en
;
941 u8 inner_dipv6_word_en
;
942 u8 outer_sipv6_word_en
;
943 u8 outer_dipv6_word_en
;
946 __le32 meta_data_mask
;
950 #define HCLGE_FD_EPORT_SW_EN_B 0
951 struct hclge_fd_tcam_config_1_cmd
{
962 struct hclge_fd_tcam_config_2_cmd
{
966 struct hclge_fd_tcam_config_3_cmd
{
971 #define HCLGE_FD_AD_DROP_B 0
972 #define HCLGE_FD_AD_DIRECT_QID_B 1
973 #define HCLGE_FD_AD_QID_S 2
974 #define HCLGE_FD_AD_QID_M GENMASK(12, 2)
975 #define HCLGE_FD_AD_USE_COUNTER_B 12
976 #define HCLGE_FD_AD_COUNTER_NUM_S 13
977 #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13)
978 #define HCLGE_FD_AD_NXT_STEP_B 20
979 #define HCLGE_FD_AD_NXT_KEY_S 21
980 #define HCLGE_FD_AD_NXT_KEY_M GENMASK(26, 21)
981 #define HCLGE_FD_AD_WR_RULE_ID_B 0
982 #define HCLGE_FD_AD_RULE_ID_S 1
983 #define HCLGE_FD_AD_RULE_ID_M GENMASK(13, 1)
985 struct hclge_fd_ad_config_cmd
{
993 struct hclge_get_m7_bd_cmd
{
998 struct hclge_query_ppu_pf_other_int_dfx_cmd
{
999 __le16 over_8bd_no_fe_qid
;
1000 __le16 over_8bd_no_fe_vf_id
;
1001 __le16 tso_mss_cmp_min_err_qid
;
1002 __le16 tso_mss_cmp_min_err_vf_id
;
1003 __le16 tso_mss_cmp_max_err_qid
;
1004 __le16 tso_mss_cmp_max_err_vf_id
;
1005 __le16 tx_rd_fbd_poison_qid
;
1006 __le16 tx_rd_fbd_poison_vf_id
;
1007 __le16 rx_rd_fbd_poison_qid
;
1008 __le16 rx_rd_fbd_poison_vf_id
;
1012 int hclge_cmd_init(struct hclge_dev
*hdev
);
1013 static inline void hclge_write_reg(void __iomem
*base
, u32 reg
, u32 value
)
1015 writel(value
, base
+ reg
);
1018 #define hclge_write_dev(a, reg, value) \
1019 hclge_write_reg((a)->io_base, (reg), (value))
1020 #define hclge_read_dev(a, reg) \
1021 hclge_read_reg((a)->io_base, (reg))
1023 static inline u32
hclge_read_reg(u8 __iomem
*base
, u32 reg
)
1025 u8 __iomem
*reg_addr
= READ_ONCE(base
);
1027 return readl(reg_addr
+ reg
);
1030 #define HCLGE_SEND_SYNC(flag) \
1031 ((flag) & HCLGE_CMD_FLAG_NO_INTR)
1034 int hclge_cmd_send(struct hclge_hw
*hw
, struct hclge_desc
*desc
, int num
);
1035 void hclge_cmd_setup_basic_desc(struct hclge_desc
*desc
,
1036 enum hclge_opcode_type opcode
, bool is_read
);
1037 void hclge_cmd_reuse_desc(struct hclge_desc
*desc
, bool is_read
);
1039 int hclge_cmd_set_promisc_mode(struct hclge_dev
*hdev
,
1040 struct hclge_promisc_param
*param
);
1042 enum hclge_cmd_status
hclge_cmd_mdio_write(struct hclge_hw
*hw
,
1043 struct hclge_desc
*desc
);
1044 enum hclge_cmd_status
hclge_cmd_mdio_read(struct hclge_hw
*hw
,
1045 struct hclge_desc
*desc
);
1047 void hclge_cmd_uninit(struct hclge_dev
*hdev
);
1048 int hclge_cmd_queue_init(struct hclge_dev
*hdev
);