1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
6 #include <linux/types.h>
9 #define HCLGE_CMDQ_TX_TIMEOUT 30000
15 #define HCLGE_CMDQ_RX_INVLD_B 0
16 #define HCLGE_CMDQ_RX_OUTVLD_B 1
24 struct hclge_cmq_ring
{
25 dma_addr_t desc_dma_addr
;
26 struct hclge_desc
*desc
;
27 struct hclge_dev
*dev
;
35 u8 ring_type
; /* cmq ring type */
36 spinlock_t lock
; /* Command queue lock */
39 enum hclge_cmd_return_status
{
40 HCLGE_CMD_EXEC_SUCCESS
= 0,
41 HCLGE_CMD_NO_AUTH
= 1,
42 HCLGE_CMD_NOT_EXEC
= 2,
43 HCLGE_CMD_QUEUE_FULL
= 3,
46 enum hclge_cmd_status
{
47 HCLGE_STATUS_SUCCESS
= 0,
48 HCLGE_ERR_CSQ_FULL
= -1,
49 HCLGE_ERR_CSQ_TIMEOUT
= -2,
50 HCLGE_ERR_CSQ_ERROR
= -3,
53 struct hclge_misc_vector
{
59 struct hclge_cmq_ring csq
;
60 struct hclge_cmq_ring crq
;
62 enum hclge_cmd_status last_status
;
65 #define HCLGE_CMD_FLAG_IN BIT(0)
66 #define HCLGE_CMD_FLAG_OUT BIT(1)
67 #define HCLGE_CMD_FLAG_NEXT BIT(2)
68 #define HCLGE_CMD_FLAG_WR BIT(3)
69 #define HCLGE_CMD_FLAG_NO_INTR BIT(4)
70 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5)
72 enum hclge_opcode_type
{
73 /* Generic commands */
74 HCLGE_OPC_QUERY_FW_VER
= 0x0001,
75 HCLGE_OPC_CFG_RST_TRIGGER
= 0x0020,
76 HCLGE_OPC_GBL_RST_STATUS
= 0x0021,
77 HCLGE_OPC_QUERY_FUNC_STATUS
= 0x0022,
78 HCLGE_OPC_QUERY_PF_RSRC
= 0x0023,
79 HCLGE_OPC_QUERY_VF_RSRC
= 0x0024,
80 HCLGE_OPC_GET_CFG_PARAM
= 0x0025,
82 HCLGE_OPC_STATS_64_BIT
= 0x0030,
83 HCLGE_OPC_STATS_32_BIT
= 0x0031,
84 HCLGE_OPC_STATS_MAC
= 0x0032,
86 HCLGE_OPC_QUERY_REG_NUM
= 0x0040,
87 HCLGE_OPC_QUERY_32_BIT_REG
= 0x0041,
88 HCLGE_OPC_QUERY_64_BIT_REG
= 0x0042,
91 HCLGE_OPC_CONFIG_MAC_MODE
= 0x0301,
92 HCLGE_OPC_CONFIG_AN_MODE
= 0x0304,
93 HCLGE_OPC_QUERY_AN_RESULT
= 0x0306,
94 HCLGE_OPC_QUERY_LINK_STATUS
= 0x0307,
95 HCLGE_OPC_CONFIG_MAX_FRM_SIZE
= 0x0308,
96 HCLGE_OPC_CONFIG_SPEED_DUP
= 0x0309,
97 HCLGE_OPC_SERDES_LOOPBACK
= 0x0315,
99 /* PFC/Pause commands */
100 HCLGE_OPC_CFG_MAC_PAUSE_EN
= 0x0701,
101 HCLGE_OPC_CFG_PFC_PAUSE_EN
= 0x0702,
102 HCLGE_OPC_CFG_MAC_PARA
= 0x0703,
103 HCLGE_OPC_CFG_PFC_PARA
= 0x0704,
104 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT
= 0x0705,
105 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT
= 0x0706,
106 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT
= 0x0707,
107 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT
= 0x0708,
108 HCLGE_OPC_PRI_TO_TC_MAPPING
= 0x0709,
109 HCLGE_OPC_QOS_MAP
= 0x070A,
111 /* ETS/scheduler commands */
112 HCLGE_OPC_TM_PG_TO_PRI_LINK
= 0x0804,
113 HCLGE_OPC_TM_QS_TO_PRI_LINK
= 0x0805,
114 HCLGE_OPC_TM_NQ_TO_QS_LINK
= 0x0806,
115 HCLGE_OPC_TM_RQ_TO_QS_LINK
= 0x0807,
116 HCLGE_OPC_TM_PORT_WEIGHT
= 0x0808,
117 HCLGE_OPC_TM_PG_WEIGHT
= 0x0809,
118 HCLGE_OPC_TM_QS_WEIGHT
= 0x080A,
119 HCLGE_OPC_TM_PRI_WEIGHT
= 0x080B,
120 HCLGE_OPC_TM_PRI_C_SHAPPING
= 0x080C,
121 HCLGE_OPC_TM_PRI_P_SHAPPING
= 0x080D,
122 HCLGE_OPC_TM_PG_C_SHAPPING
= 0x080E,
123 HCLGE_OPC_TM_PG_P_SHAPPING
= 0x080F,
124 HCLGE_OPC_TM_PORT_SHAPPING
= 0x0810,
125 HCLGE_OPC_TM_PG_SCH_MODE_CFG
= 0x0812,
126 HCLGE_OPC_TM_PRI_SCH_MODE_CFG
= 0x0813,
127 HCLGE_OPC_TM_QS_SCH_MODE_CFG
= 0x0814,
128 HCLGE_OPC_TM_BP_TO_QSET_MAPPING
= 0x0815,
130 /* Packet buffer allocate commands */
131 HCLGE_OPC_TX_BUFF_ALLOC
= 0x0901,
132 HCLGE_OPC_RX_PRIV_BUFF_ALLOC
= 0x0902,
133 HCLGE_OPC_RX_PRIV_WL_ALLOC
= 0x0903,
134 HCLGE_OPC_RX_COM_THRD_ALLOC
= 0x0904,
135 HCLGE_OPC_RX_COM_WL_ALLOC
= 0x0905,
136 HCLGE_OPC_RX_GBL_PKT_CNT
= 0x0906,
138 /* TQP management command */
139 HCLGE_OPC_SET_TQP_MAP
= 0x0A01,
142 HCLGE_OPC_CFG_TX_QUEUE
= 0x0B01,
143 HCLGE_OPC_QUERY_TX_POINTER
= 0x0B02,
144 HCLGE_OPC_QUERY_TX_STATUS
= 0x0B03,
145 HCLGE_OPC_CFG_RX_QUEUE
= 0x0B11,
146 HCLGE_OPC_QUERY_RX_POINTER
= 0x0B12,
147 HCLGE_OPC_QUERY_RX_STATUS
= 0x0B13,
148 HCLGE_OPC_STASH_RX_QUEUE_LRO
= 0x0B16,
149 HCLGE_OPC_CFG_RX_QUEUE_LRO
= 0x0B17,
150 HCLGE_OPC_CFG_COM_TQP_QUEUE
= 0x0B20,
151 HCLGE_OPC_RESET_TQP_QUEUE
= 0x0B22,
154 HCLGE_OPC_TSO_GENERIC_CONFIG
= 0x0C01,
157 HCLGE_OPC_RSS_GENERIC_CONFIG
= 0x0D01,
158 HCLGE_OPC_RSS_INDIR_TABLE
= 0x0D07,
159 HCLGE_OPC_RSS_TC_MODE
= 0x0D08,
160 HCLGE_OPC_RSS_INPUT_TUPLE
= 0x0D02,
162 /* Promisuous mode command */
163 HCLGE_OPC_CFG_PROMISC_MODE
= 0x0E01,
165 /* Vlan offload commands */
166 HCLGE_OPC_VLAN_PORT_TX_CFG
= 0x0F01,
167 HCLGE_OPC_VLAN_PORT_RX_CFG
= 0x0F02,
169 /* Interrupts commands */
170 HCLGE_OPC_ADD_RING_TO_VECTOR
= 0x1503,
171 HCLGE_OPC_DEL_RING_TO_VECTOR
= 0x1504,
174 HCLGE_OPC_MAC_VLAN_ADD
= 0x1000,
175 HCLGE_OPC_MAC_VLAN_REMOVE
= 0x1001,
176 HCLGE_OPC_MAC_VLAN_TYPE_ID
= 0x1002,
177 HCLGE_OPC_MAC_VLAN_INSERT
= 0x1003,
178 HCLGE_OPC_MAC_ETHTYPE_ADD
= 0x1010,
179 HCLGE_OPC_MAC_ETHTYPE_REMOVE
= 0x1011,
180 HCLGE_OPC_MAC_VLAN_MASK_SET
= 0x1012,
182 /* Multicast linear table commands */
183 HCLGE_OPC_MTA_MAC_MODE_CFG
= 0x1020,
184 HCLGE_OPC_MTA_MAC_FUNC_CFG
= 0x1021,
185 HCLGE_OPC_MTA_TBL_ITEM_CFG
= 0x1022,
186 HCLGE_OPC_MTA_TBL_ITEM_QUERY
= 0x1023,
189 HCLGE_OPC_VLAN_FILTER_CTRL
= 0x1100,
190 HCLGE_OPC_VLAN_FILTER_PF_CFG
= 0x1101,
191 HCLGE_OPC_VLAN_FILTER_VF_CFG
= 0x1102,
194 HCLGE_OPC_MDIO_CONFIG
= 0x1900,
197 HCLGE_OPC_QCN_MOD_CFG
= 0x1A01,
198 HCLGE_OPC_QCN_GRP_TMPLT_CFG
= 0x1A02,
199 HCLGE_OPC_QCN_SHAPPING_IR_CFG
= 0x1A03,
200 HCLGE_OPC_QCN_SHAPPING_BS_CFG
= 0x1A04,
201 HCLGE_OPC_QCN_QSET_LINK_CFG
= 0x1A05,
202 HCLGE_OPC_QCN_RP_STATUS_GET
= 0x1A06,
203 HCLGE_OPC_QCN_AJUST_INIT
= 0x1A07,
204 HCLGE_OPC_QCN_DFX_CNT_STATUS
= 0x1A08,
206 /* Mailbox command */
207 HCLGEVF_OPC_MBX_PF_TO_VF
= 0x2000,
210 HCLGE_OPC_LED_STATUS_CFG
= 0xB000,
213 #define HCLGE_TQP_REG_OFFSET 0x80000
214 #define HCLGE_TQP_REG_SIZE 0x200
216 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10
217 #define HCLGE_RCB_INIT_FLAG_EN_B 0
218 #define HCLGE_RCB_INIT_FLAG_FINI_B 8
219 struct hclge_config_rcb_init_cmd
{
220 __le16 rcb_init_flag
;
224 struct hclge_tqp_map_cmd
{
225 __le16 tqp_id
; /* Absolute tqp id for in this pf */
226 u8 tqp_vf
; /* VF id */
227 #define HCLGE_TQP_MAP_TYPE_PF 0
228 #define HCLGE_TQP_MAP_TYPE_VF 1
229 #define HCLGE_TQP_MAP_TYPE_B 0
230 #define HCLGE_TQP_MAP_EN_B 1
231 u8 tqp_flag
; /* Indicate it's pf or vf tqp */
232 __le16 tqp_vid
; /* Virtual id in this pf/vf */
236 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10
238 enum hclge_int_type
{
244 struct hclge_ctrl_vector_chain_cmd
{
247 #define HCLGE_INT_TYPE_S 0
248 #define HCLGE_INT_TYPE_M GENMASK(1, 0)
249 #define HCLGE_TQP_ID_S 2
250 #define HCLGE_TQP_ID_M GENMASK(12, 2)
251 #define HCLGE_INT_GL_IDX_S 13
252 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13)
253 __le16 tqp_type_and_id
[HCLGE_VECTOR_ELEMENTS_PER_CMD
];
258 #define HCLGE_TC_NUM 8
259 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */
260 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */
261 struct hclge_tx_buff_alloc_cmd
{
262 __le16 tx_pkt_buff
[HCLGE_TC_NUM
];
266 struct hclge_rx_priv_buff_cmd
{
267 __le16 buf_num
[HCLGE_TC_NUM
];
272 struct hclge_query_version_cmd
{
274 __le32 firmware_rsv
[5];
277 #define HCLGE_RX_PRIV_EN_B 15
278 #define HCLGE_TC_NUM_ONE_DESC 4
279 struct hclge_priv_wl
{
284 struct hclge_rx_priv_wl_buf
{
285 struct hclge_priv_wl tc_wl
[HCLGE_TC_NUM_ONE_DESC
];
288 struct hclge_rx_com_thrd
{
289 struct hclge_priv_wl com_thrd
[HCLGE_TC_NUM_ONE_DESC
];
292 struct hclge_rx_com_wl
{
293 struct hclge_priv_wl com_wl
;
296 struct hclge_waterline
{
301 struct hclge_tc_thrd
{
306 struct hclge_priv_buf
{
307 struct hclge_waterline wl
; /* Waterline for low and high*/
308 u32 buf_size
; /* TC private buffer size */
310 u32 enable
; /* Enable TC private buffer or not */
313 #define HCLGE_MAX_TC_NUM 8
314 struct hclge_shared_buf
{
315 struct hclge_waterline self
;
316 struct hclge_tc_thrd tc_thrd
[HCLGE_MAX_TC_NUM
];
320 struct hclge_pkt_buf_alloc
{
321 struct hclge_priv_buf priv_buf
[HCLGE_MAX_TC_NUM
];
322 struct hclge_shared_buf s_buf
;
325 #define HCLGE_RX_COM_WL_EN_B 15
326 struct hclge_rx_com_wl_buf_cmd
{
332 #define HCLGE_RX_PKT_EN_B 15
333 struct hclge_rx_pkt_buf_cmd
{
339 #define HCLGE_PF_STATE_DONE_B 0
340 #define HCLGE_PF_STATE_MAIN_B 1
341 #define HCLGE_PF_STATE_BOND_B 2
342 #define HCLGE_PF_STATE_MAC_N_B 6
343 #define HCLGE_PF_MAC_NUM_MASK 0x3
344 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B)
345 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B)
346 struct hclge_func_status_cmd
{
347 __le32 vf_rst_state
[4];
357 struct hclge_pf_res_cmd
{
360 __le16 msixcap_localid_ba_nic
;
361 __le16 msixcap_localid_ba_rocee
;
362 #define HCLGE_MSIX_OFT_ROCEE_S 0
363 #define HCLGE_MSIX_OFT_ROCEE_M GENMASK(15, 0)
364 #define HCLGE_PF_VEC_NUM_S 0
365 #define HCLGE_PF_VEC_NUM_M GENMASK(7, 0)
366 __le16 pf_intr_vector_number
;
367 __le16 pf_own_fun_number
;
371 #define HCLGE_CFG_OFFSET_S 0
372 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0)
373 #define HCLGE_CFG_RD_LEN_S 24
374 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24)
375 #define HCLGE_CFG_RD_LEN_BYTES 16
376 #define HCLGE_CFG_RD_LEN_UNIT 4
378 #define HCLGE_CFG_VMDQ_S 0
379 #define HCLGE_CFG_VMDQ_M GENMASK(7, 0)
380 #define HCLGE_CFG_TC_NUM_S 8
381 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8)
382 #define HCLGE_CFG_TQP_DESC_N_S 16
383 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16)
384 #define HCLGE_CFG_PHY_ADDR_S 0
385 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0)
386 #define HCLGE_CFG_MEDIA_TP_S 8
387 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8)
388 #define HCLGE_CFG_RX_BUF_LEN_S 16
389 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16)
390 #define HCLGE_CFG_MAC_ADDR_H_S 0
391 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0)
392 #define HCLGE_CFG_DEFAULT_SPEED_S 16
393 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16)
394 #define HCLGE_CFG_RSS_SIZE_S 24
395 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24)
396 #define HCLGE_CFG_SPEED_ABILITY_S 0
397 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0)
399 struct hclge_cfg_param_cmd
{
405 #define HCLGE_MAC_MODE 0x0
406 #define HCLGE_DESC_NUM 0x40
408 #define HCLGE_ALLOC_VALID_B 0
409 struct hclge_vf_num_cmd
{
414 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4
415 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4
416 #define HCLGE_RSS_HASH_KEY_NUM 16
417 struct hclge_rss_config_cmd
{
420 u8 hash_key
[HCLGE_RSS_HASH_KEY_NUM
];
423 struct hclge_rss_input_tuple_cmd
{
435 #define HCLGE_RSS_CFG_TBL_SIZE 16
437 struct hclge_rss_indirection_table_cmd
{
438 __le16 start_table_index
;
439 __le16 rss_set_bitmap
;
441 u8 rss_result
[HCLGE_RSS_CFG_TBL_SIZE
];
444 #define HCLGE_RSS_TC_OFFSET_S 0
445 #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0)
446 #define HCLGE_RSS_TC_SIZE_S 12
447 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12)
448 #define HCLGE_RSS_TC_VALID_B 15
449 struct hclge_rss_tc_mode_cmd
{
450 __le16 rss_tc_mode
[HCLGE_MAX_TC_NUM
];
454 #define HCLGE_LINK_STATUS_UP_B 0
455 #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B)
456 struct hclge_link_status_cmd
{
461 struct hclge_promisc_param
{
466 #define HCLGE_PROMISC_TX_EN_B BIT(4)
467 #define HCLGE_PROMISC_RX_EN_B BIT(5)
468 #define HCLGE_PROMISC_EN_B 1
469 #define HCLGE_PROMISC_EN_ALL 0x7
470 #define HCLGE_PROMISC_EN_UC 0x1
471 #define HCLGE_PROMISC_EN_MC 0x2
472 #define HCLGE_PROMISC_EN_BC 0x4
473 struct hclge_promisc_cfg_cmd
{
480 enum hclge_promisc_type
{
486 #define HCLGE_MAC_TX_EN_B 6
487 #define HCLGE_MAC_RX_EN_B 7
488 #define HCLGE_MAC_PAD_TX_B 11
489 #define HCLGE_MAC_PAD_RX_B 12
490 #define HCLGE_MAC_1588_TX_B 13
491 #define HCLGE_MAC_1588_RX_B 14
492 #define HCLGE_MAC_APP_LP_B 15
493 #define HCLGE_MAC_LINE_LP_B 16
494 #define HCLGE_MAC_FCS_TX_B 17
495 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18
496 #define HCLGE_MAC_RX_FCS_STRIP_B 19
497 #define HCLGE_MAC_RX_FCS_B 20
498 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21
499 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22
501 struct hclge_config_mac_mode_cmd
{
502 __le32 txrx_pad_fcs_loop_en
;
506 #define HCLGE_CFG_SPEED_S 0
507 #define HCLGE_CFG_SPEED_M GENMASK(5, 0)
509 #define HCLGE_CFG_DUPLEX_B 7
510 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B)
512 struct hclge_config_mac_speed_dup_cmd
{
515 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
516 u8 mac_change_fec_en
;
520 #define HCLGE_QUERY_SPEED_S 3
521 #define HCLGE_QUERY_AN_B 0
522 #define HCLGE_QUERY_DUPLEX_B 2
524 #define HCLGE_QUERY_SPEED_M GENMASK(4, 0)
525 #define HCLGE_QUERY_AN_M BIT(HCLGE_QUERY_AN_B)
526 #define HCLGE_QUERY_DUPLEX_M BIT(HCLGE_QUERY_DUPLEX_B)
528 struct hclge_query_an_speed_dup_cmd
{
534 #define HCLGE_RING_ID_MASK GENMASK(9, 0)
535 #define HCLGE_TQP_ENABLE_B 0
537 #define HCLGE_MAC_CFG_AN_EN_B 0
538 #define HCLGE_MAC_CFG_AN_INT_EN_B 1
539 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2
540 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3
541 #define HCLGE_MAC_CFG_AN_RST_B 4
543 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B)
545 struct hclge_config_auto_neg_cmd
{
546 __le32 cfg_an_cmd_flag
;
550 #define HCLGE_MAC_UPLINK_PORT 0x100
552 struct hclge_config_max_frm_size_cmd
{
558 enum hclge_mac_vlan_tbl_opcode
{
559 HCLGE_MAC_VLAN_ADD
, /* Add new or modify mac_vlan */
560 HCLGE_MAC_VLAN_UPDATE
, /* Modify other fields of this table */
561 HCLGE_MAC_VLAN_REMOVE
, /* Remove a entry through mac_vlan key */
562 HCLGE_MAC_VLAN_LKUP
, /* Lookup a entry through mac_vlan key */
565 #define HCLGE_MAC_VLAN_BIT0_EN_B 0
566 #define HCLGE_MAC_VLAN_BIT1_EN_B 1
567 #define HCLGE_MAC_EPORT_SW_EN_B 12
568 #define HCLGE_MAC_EPORT_TYPE_B 11
569 #define HCLGE_MAC_EPORT_VFID_S 3
570 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3)
571 #define HCLGE_MAC_EPORT_PFID_S 0
572 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0)
573 struct hclge_mac_vlan_tbl_entry_cmd
{
577 __le32 mac_addr_hi32
;
578 __le16 mac_addr_lo16
;
587 #define HCLGE_VLAN_MASK_EN_B 0
588 struct hclge_mac_vlan_mask_entry_cmd
{
596 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0)
597 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1)
598 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2)
599 #define HCLGE_MAC_ETHERTYPE_LLDP 0x88cc
601 struct hclge_mac_mgr_tbl_entry_cmd
{
605 __le32 mac_addr_hi32
;
606 __le16 mac_addr_lo16
;
618 #define HCLGE_CFG_MTA_MAC_SEL_S 0
619 #define HCLGE_CFG_MTA_MAC_SEL_M GENMASK(1, 0)
620 #define HCLGE_CFG_MTA_MAC_EN_B 7
621 struct hclge_mta_filter_mode_cmd
{
622 u8 dmac_sel_en
; /* Use lowest 2 bit as sel_mode, bit 7 as enable */
626 #define HCLGE_CFG_FUNC_MTA_ACCEPT_B 0
627 struct hclge_cfg_func_mta_filter_cmd
{
628 u8 accept
; /* Only used lowest 1 bit */
633 #define HCLGE_CFG_MTA_ITEM_ACCEPT_B 0
634 #define HCLGE_CFG_MTA_ITEM_IDX_S 0
635 #define HCLGE_CFG_MTA_ITEM_IDX_M GENMASK(11, 0)
636 struct hclge_cfg_func_mta_item_cmd
{
637 __le16 item_idx
; /* Only used lowest 12 bit */
638 u8 accept
; /* Only used lowest 1 bit */
642 struct hclge_mac_vlan_add_cmd
{
644 __le16 mac_addr_hi16
;
645 __le32 mac_addr_lo32
;
646 __le32 mac_addr_msk_hi32
;
647 __le16 mac_addr_msk_lo16
;
654 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0
655 struct hclge_mac_vlan_remove_cmd
{
657 __le16 mac_addr_hi16
;
658 __le32 mac_addr_lo32
;
659 __le32 mac_addr_msk_hi32
;
660 __le16 mac_addr_msk_lo16
;
667 struct hclge_vlan_filter_ctrl_cmd
{
673 struct hclge_vlan_filter_pf_cfg_cmd
{
677 u8 vlan_offset_bitmap
[20];
680 struct hclge_vlan_filter_vf_cfg_cmd
{
689 #define HCLGE_ACCEPT_TAG1_B 0
690 #define HCLGE_ACCEPT_UNTAG1_B 1
691 #define HCLGE_PORT_INS_TAG1_EN_B 2
692 #define HCLGE_PORT_INS_TAG2_EN_B 3
693 #define HCLGE_CFG_NIC_ROCE_SEL_B 4
694 #define HCLGE_ACCEPT_TAG2_B 5
695 #define HCLGE_ACCEPT_UNTAG2_B 6
697 struct hclge_vport_vtag_tx_cfg_cmd
{
701 __le16 def_vlan_tag1
;
702 __le16 def_vlan_tag2
;
707 #define HCLGE_REM_TAG1_EN_B 0
708 #define HCLGE_REM_TAG2_EN_B 1
709 #define HCLGE_SHOW_TAG1_EN_B 2
710 #define HCLGE_SHOW_TAG2_EN_B 3
711 struct hclge_vport_vtag_rx_cfg_cmd
{
719 struct hclge_tx_vlan_type_cfg_cmd
{
725 struct hclge_rx_vlan_type_cfg_cmd
{
726 __le16 ot_fst_vlan_type
;
727 __le16 ot_sec_vlan_type
;
728 __le16 in_fst_vlan_type
;
729 __le16 in_sec_vlan_type
;
733 struct hclge_cfg_com_tqp_queue_cmd
{
740 struct hclge_cfg_tx_queue_pointer_cmd
{
749 #define HCLGE_TSO_MSS_MIN_S 0
750 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0)
752 #define HCLGE_TSO_MSS_MAX_S 16
753 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16)
755 struct hclge_cfg_tso_status_cmd
{
761 #define HCLGE_TSO_MSS_MIN 256
762 #define HCLGE_TSO_MSS_MAX 9668
764 #define HCLGE_TQP_RESET_B 0
765 struct hclge_reset_tqp_queue_cmd
{
772 #define HCLGE_CFG_RESET_MAC_B 3
773 #define HCLGE_CFG_RESET_FUNC_B 7
774 struct hclge_reset_cmd
{
780 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0)
781 #define HCLGE_CMD_SERDES_DONE_B BIT(0)
782 #define HCLGE_CMD_SERDES_SUCCESS_B BIT(1)
783 struct hclge_serdes_lb_cmd
{
790 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */
791 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
792 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */
793 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */
795 #define HCLGE_TYPE_CRQ 0
796 #define HCLGE_TYPE_CSQ 1
797 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000
798 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004
799 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008
800 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010
801 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014
802 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018
803 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c
804 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020
805 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024
806 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028
807 #define HCLGE_NIC_CMQ_EN_B 16
808 #define HCLGE_NIC_CMQ_ENABLE BIT(HCLGE_NIC_CMQ_EN_B)
809 #define HCLGE_NIC_CMQ_DESC_NUM 1024
810 #define HCLGE_NIC_CMQ_DESC_NUM_S 3
812 #define HCLGE_LED_LOCATE_STATE_S 0
813 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0)
815 struct hclge_set_led_state_cmd
{
817 u8 locate_led_config
;
821 int hclge_cmd_init(struct hclge_dev
*hdev
);
822 static inline void hclge_write_reg(void __iomem
*base
, u32 reg
, u32 value
)
824 writel(value
, base
+ reg
);
827 #define hclge_write_dev(a, reg, value) \
828 hclge_write_reg((a)->io_base, (reg), (value))
829 #define hclge_read_dev(a, reg) \
830 hclge_read_reg((a)->io_base, (reg))
832 static inline u32
hclge_read_reg(u8 __iomem
*base
, u32 reg
)
834 u8 __iomem
*reg_addr
= READ_ONCE(base
);
836 return readl(reg_addr
+ reg
);
839 #define HCLGE_SEND_SYNC(flag) \
840 ((flag) & HCLGE_CMD_FLAG_NO_INTR)
843 int hclge_cmd_send(struct hclge_hw
*hw
, struct hclge_desc
*desc
, int num
);
844 void hclge_cmd_setup_basic_desc(struct hclge_desc
*desc
,
845 enum hclge_opcode_type opcode
, bool is_read
);
846 void hclge_cmd_reuse_desc(struct hclge_desc
*desc
, bool is_read
);
848 int hclge_cmd_set_promisc_mode(struct hclge_dev
*hdev
,
849 struct hclge_promisc_param
*param
);
851 enum hclge_cmd_status
hclge_cmd_mdio_write(struct hclge_hw
*hw
,
852 struct hclge_desc
*desc
);
853 enum hclge_cmd_status
hclge_cmd_mdio_read(struct hclge_hw
*hw
,
854 struct hclge_desc
*desc
);
856 void hclge_destroy_cmd_queue(struct hclge_hw
*hw
);
857 int hclge_cmd_queue_init(struct hclge_dev
*hdev
);