2 * Copyright (c) 2016~2017 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
12 #include <linux/types.h>
15 #define HCLGE_CMDQ_TX_TIMEOUT 1000
21 #define HCLGE_CMDQ_RX_INVLD_B 0
22 #define HCLGE_CMDQ_RX_OUTVLD_B 1
30 struct hclge_desc_cb
{
36 struct hclge_cmq_ring
{
37 dma_addr_t desc_dma_addr
;
38 struct hclge_desc
*desc
;
39 struct hclge_desc_cb
*desc_cb
;
40 struct hclge_dev
*dev
;
49 spinlock_t lock
; /* Command queue lock */
52 enum hclge_cmd_return_status
{
53 HCLGE_CMD_EXEC_SUCCESS
= 0,
54 HCLGE_CMD_NO_AUTH
= 1,
55 HCLGE_CMD_NOT_EXEC
= 2,
56 HCLGE_CMD_QUEUE_FULL
= 3,
59 enum hclge_cmd_status
{
60 HCLGE_STATUS_SUCCESS
= 0,
61 HCLGE_ERR_CSQ_FULL
= -1,
62 HCLGE_ERR_CSQ_TIMEOUT
= -2,
63 HCLGE_ERR_CSQ_ERROR
= -3,
66 struct hclge_misc_vector
{
72 struct hclge_cmq_ring csq
;
73 struct hclge_cmq_ring crq
;
74 u16 tx_timeout
; /* Tx timeout */
75 enum hclge_cmd_status last_status
;
78 #define HCLGE_CMD_FLAG_IN_VALID_SHIFT 0
79 #define HCLGE_CMD_FLAG_OUT_VALID_SHIFT 1
80 #define HCLGE_CMD_FLAG_NEXT_SHIFT 2
81 #define HCLGE_CMD_FLAG_WR_OR_RD_SHIFT 3
82 #define HCLGE_CMD_FLAG_NO_INTR_SHIFT 4
83 #define HCLGE_CMD_FLAG_ERR_INTR_SHIFT 5
85 #define HCLGE_CMD_FLAG_IN BIT(HCLGE_CMD_FLAG_IN_VALID_SHIFT)
86 #define HCLGE_CMD_FLAG_OUT BIT(HCLGE_CMD_FLAG_OUT_VALID_SHIFT)
87 #define HCLGE_CMD_FLAG_NEXT BIT(HCLGE_CMD_FLAG_NEXT_SHIFT)
88 #define HCLGE_CMD_FLAG_WR BIT(HCLGE_CMD_FLAG_WR_OR_RD_SHIFT)
89 #define HCLGE_CMD_FLAG_NO_INTR BIT(HCLGE_CMD_FLAG_NO_INTR_SHIFT)
90 #define HCLGE_CMD_FLAG_ERR_INTR BIT(HCLGE_CMD_FLAG_ERR_INTR_SHIFT)
92 enum hclge_opcode_type
{
94 HCLGE_OPC_QUERY_FW_VER
= 0x0001,
95 HCLGE_OPC_CFG_RST_TRIGGER
= 0x0020,
96 HCLGE_OPC_GBL_RST_STATUS
= 0x0021,
97 HCLGE_OPC_QUERY_FUNC_STATUS
= 0x0022,
98 HCLGE_OPC_QUERY_PF_RSRC
= 0x0023,
99 HCLGE_OPC_QUERY_VF_RSRC
= 0x0024,
100 HCLGE_OPC_GET_CFG_PARAM
= 0x0025,
102 HCLGE_OPC_STATS_64_BIT
= 0x0030,
103 HCLGE_OPC_STATS_32_BIT
= 0x0031,
104 HCLGE_OPC_STATS_MAC
= 0x0032,
105 /* Device management command */
108 HCLGE_OPC_CONFIG_MAC_MODE
= 0x0301,
109 HCLGE_OPC_CONFIG_AN_MODE
= 0x0304,
110 HCLGE_OPC_QUERY_AN_RESULT
= 0x0306,
111 HCLGE_OPC_QUERY_LINK_STATUS
= 0x0307,
112 HCLGE_OPC_CONFIG_MAX_FRM_SIZE
= 0x0308,
113 HCLGE_OPC_CONFIG_SPEED_DUP
= 0x0309,
117 HCLGE_OPC_CFG_MAC_PAUSE_EN
= 0x0701,
118 HCLGE_OPC_CFG_PFC_PAUSE_EN
= 0x0702,
119 HCLGE_OPC_CFG_MAC_PARA
= 0x0703,
120 HCLGE_OPC_CFG_PFC_PARA
= 0x0704,
121 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT
= 0x0705,
122 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT
= 0x0706,
123 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT
= 0x0707,
124 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT
= 0x0708,
125 HCLGE_OPC_PRI_TO_TC_MAPPING
= 0x0709,
126 HCLGE_OPC_QOS_MAP
= 0x070A,
128 /* ETS/scheduler commands */
129 HCLGE_OPC_TM_PG_TO_PRI_LINK
= 0x0804,
130 HCLGE_OPC_TM_QS_TO_PRI_LINK
= 0x0805,
131 HCLGE_OPC_TM_NQ_TO_QS_LINK
= 0x0806,
132 HCLGE_OPC_TM_RQ_TO_QS_LINK
= 0x0807,
133 HCLGE_OPC_TM_PORT_WEIGHT
= 0x0808,
134 HCLGE_OPC_TM_PG_WEIGHT
= 0x0809,
135 HCLGE_OPC_TM_QS_WEIGHT
= 0x080A,
136 HCLGE_OPC_TM_PRI_WEIGHT
= 0x080B,
137 HCLGE_OPC_TM_PRI_C_SHAPPING
= 0x080C,
138 HCLGE_OPC_TM_PRI_P_SHAPPING
= 0x080D,
139 HCLGE_OPC_TM_PG_C_SHAPPING
= 0x080E,
140 HCLGE_OPC_TM_PG_P_SHAPPING
= 0x080F,
141 HCLGE_OPC_TM_PORT_SHAPPING
= 0x0810,
142 HCLGE_OPC_TM_PG_SCH_MODE_CFG
= 0x0812,
143 HCLGE_OPC_TM_PRI_SCH_MODE_CFG
= 0x0813,
144 HCLGE_OPC_TM_QS_SCH_MODE_CFG
= 0x0814,
145 HCLGE_OPC_TM_BP_TO_QSET_MAPPING
= 0x0815,
147 /* Packet buffer allocate command */
148 HCLGE_OPC_TX_BUFF_ALLOC
= 0x0901,
149 HCLGE_OPC_RX_PRIV_BUFF_ALLOC
= 0x0902,
150 HCLGE_OPC_RX_PRIV_WL_ALLOC
= 0x0903,
151 HCLGE_OPC_RX_COM_THRD_ALLOC
= 0x0904,
152 HCLGE_OPC_RX_COM_WL_ALLOC
= 0x0905,
153 HCLGE_OPC_RX_GBL_PKT_CNT
= 0x0906,
156 /* TQP management command */
157 HCLGE_OPC_SET_TQP_MAP
= 0x0A01,
160 HCLGE_OPC_CFG_TX_QUEUE
= 0x0B01,
161 HCLGE_OPC_QUERY_TX_POINTER
= 0x0B02,
162 HCLGE_OPC_QUERY_TX_STATUS
= 0x0B03,
163 HCLGE_OPC_CFG_RX_QUEUE
= 0x0B11,
164 HCLGE_OPC_QUERY_RX_POINTER
= 0x0B12,
165 HCLGE_OPC_QUERY_RX_STATUS
= 0x0B13,
166 HCLGE_OPC_STASH_RX_QUEUE_LRO
= 0x0B16,
167 HCLGE_OPC_CFG_RX_QUEUE_LRO
= 0x0B17,
168 HCLGE_OPC_CFG_COM_TQP_QUEUE
= 0x0B20,
169 HCLGE_OPC_RESET_TQP_QUEUE
= 0x0B22,
172 HCLGE_OPC_TSO_GENERIC_CONFIG
= 0x0C01,
175 HCLGE_OPC_RSS_GENERIC_CONFIG
= 0x0D01,
176 HCLGE_OPC_RSS_INDIR_TABLE
= 0x0D07,
177 HCLGE_OPC_RSS_TC_MODE
= 0x0D08,
178 HCLGE_OPC_RSS_INPUT_TUPLE
= 0x0D02,
180 /* Promisuous mode command */
181 HCLGE_OPC_CFG_PROMISC_MODE
= 0x0E01,
184 HCLGE_OPC_ADD_RING_TO_VECTOR
= 0x1503,
185 HCLGE_OPC_DEL_RING_TO_VECTOR
= 0x1504,
188 HCLGE_OPC_MAC_VLAN_ADD
= 0x1000,
189 HCLGE_OPC_MAC_VLAN_REMOVE
= 0x1001,
190 HCLGE_OPC_MAC_VLAN_TYPE_ID
= 0x1002,
191 HCLGE_OPC_MAC_VLAN_INSERT
= 0x1003,
192 HCLGE_OPC_MAC_ETHTYPE_ADD
= 0x1010,
193 HCLGE_OPC_MAC_ETHTYPE_REMOVE
= 0x1011,
195 /* Multicast linear table cmd */
196 HCLGE_OPC_MTA_MAC_MODE_CFG
= 0x1020,
197 HCLGE_OPC_MTA_MAC_FUNC_CFG
= 0x1021,
198 HCLGE_OPC_MTA_TBL_ITEM_CFG
= 0x1022,
199 HCLGE_OPC_MTA_TBL_ITEM_QUERY
= 0x1023,
202 HCLGE_OPC_VLAN_FILTER_CTRL
= 0x1100,
203 HCLGE_OPC_VLAN_FILTER_PF_CFG
= 0x1101,
204 HCLGE_OPC_VLAN_FILTER_VF_CFG
= 0x1102,
207 HCLGE_OPC_MDIO_CONFIG
= 0x1900,
210 HCLGE_OPC_QCN_MOD_CFG
= 0x1A01,
211 HCLGE_OPC_QCN_GRP_TMPLT_CFG
= 0x1A02,
212 HCLGE_OPC_QCN_SHAPPING_IR_CFG
= 0x1A03,
213 HCLGE_OPC_QCN_SHAPPING_BS_CFG
= 0x1A04,
214 HCLGE_OPC_QCN_QSET_LINK_CFG
= 0x1A05,
215 HCLGE_OPC_QCN_RP_STATUS_GET
= 0x1A06,
216 HCLGE_OPC_QCN_AJUST_INIT
= 0x1A07,
217 HCLGE_OPC_QCN_DFX_CNT_STATUS
= 0x1A08,
220 HCLGEVF_OPC_MBX_PF_TO_VF
= 0x2000,
223 #define HCLGE_TQP_REG_OFFSET 0x80000
224 #define HCLGE_TQP_REG_SIZE 0x200
226 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10
227 #define HCLGE_RCB_INIT_FLAG_EN_B 0
228 #define HCLGE_RCB_INIT_FLAG_FINI_B 8
229 struct hclge_config_rcb_init_cmd
{
230 __le16 rcb_init_flag
;
234 struct hclge_tqp_map_cmd
{
235 __le16 tqp_id
; /* Absolute tqp id for in this pf */
236 u8 tqp_vf
; /* VF id */
237 #define HCLGE_TQP_MAP_TYPE_PF 0
238 #define HCLGE_TQP_MAP_TYPE_VF 1
239 #define HCLGE_TQP_MAP_TYPE_B 0
240 #define HCLGE_TQP_MAP_EN_B 1
241 u8 tqp_flag
; /* Indicate it's pf or vf tqp */
242 __le16 tqp_vid
; /* Virtual id in this pf/vf */
246 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10
248 enum hclge_int_type
{
254 struct hclge_ctrl_vector_chain_cmd
{
257 #define HCLGE_INT_TYPE_S 0
258 #define HCLGE_INT_TYPE_M GENMASK(1, 0)
259 #define HCLGE_TQP_ID_S 2
260 #define HCLGE_TQP_ID_M GENMASK(12, 2)
261 #define HCLGE_INT_GL_IDX_S 13
262 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13)
263 __le16 tqp_type_and_id
[HCLGE_VECTOR_ELEMENTS_PER_CMD
];
268 #define HCLGE_TC_NUM 8
269 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */
270 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */
271 struct hclge_tx_buff_alloc_cmd
{
272 __le16 tx_pkt_buff
[HCLGE_TC_NUM
];
276 struct hclge_rx_priv_buff_cmd
{
277 __le16 buf_num
[HCLGE_TC_NUM
];
282 struct hclge_query_version_cmd
{
284 __le32 firmware_rsv
[5];
287 #define HCLGE_RX_PRIV_EN_B 15
288 #define HCLGE_TC_NUM_ONE_DESC 4
289 struct hclge_priv_wl
{
294 struct hclge_rx_priv_wl_buf
{
295 struct hclge_priv_wl tc_wl
[HCLGE_TC_NUM_ONE_DESC
];
298 struct hclge_rx_com_thrd
{
299 struct hclge_priv_wl com_thrd
[HCLGE_TC_NUM_ONE_DESC
];
302 struct hclge_rx_com_wl
{
303 struct hclge_priv_wl com_wl
;
306 struct hclge_waterline
{
311 struct hclge_tc_thrd
{
316 struct hclge_priv_buf
{
317 struct hclge_waterline wl
; /* Waterline for low and high*/
318 u32 buf_size
; /* TC private buffer size */
320 u32 enable
; /* Enable TC private buffer or not */
323 #define HCLGE_MAX_TC_NUM 8
324 struct hclge_shared_buf
{
325 struct hclge_waterline self
;
326 struct hclge_tc_thrd tc_thrd
[HCLGE_MAX_TC_NUM
];
330 struct hclge_pkt_buf_alloc
{
331 struct hclge_priv_buf priv_buf
[HCLGE_MAX_TC_NUM
];
332 struct hclge_shared_buf s_buf
;
335 #define HCLGE_RX_COM_WL_EN_B 15
336 struct hclge_rx_com_wl_buf_cmd
{
342 #define HCLGE_RX_PKT_EN_B 15
343 struct hclge_rx_pkt_buf_cmd
{
349 #define HCLGE_PF_STATE_DONE_B 0
350 #define HCLGE_PF_STATE_MAIN_B 1
351 #define HCLGE_PF_STATE_BOND_B 2
352 #define HCLGE_PF_STATE_MAC_N_B 6
353 #define HCLGE_PF_MAC_NUM_MASK 0x3
354 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B)
355 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B)
356 struct hclge_func_status_cmd
{
357 __le32 vf_rst_state
[4];
367 struct hclge_pf_res_cmd
{
370 __le16 msixcap_localid_ba_nic
;
371 __le16 msixcap_localid_ba_rocee
;
372 #define HCLGE_PF_VEC_NUM_S 0
373 #define HCLGE_PF_VEC_NUM_M (0xff << HCLGE_PF_VEC_NUM_S)
374 __le16 pf_intr_vector_number
;
375 __le16 pf_own_fun_number
;
379 #define HCLGE_CFG_OFFSET_S 0
380 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0)
381 #define HCLGE_CFG_RD_LEN_S 24
382 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24)
383 #define HCLGE_CFG_RD_LEN_BYTES 16
384 #define HCLGE_CFG_RD_LEN_UNIT 4
386 #define HCLGE_CFG_VMDQ_S 0
387 #define HCLGE_CFG_VMDQ_M GENMASK(7, 0)
388 #define HCLGE_CFG_TC_NUM_S 8
389 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8)
390 #define HCLGE_CFG_TQP_DESC_N_S 16
391 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16)
392 #define HCLGE_CFG_PHY_ADDR_S 0
393 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0)
394 #define HCLGE_CFG_MEDIA_TP_S 8
395 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8)
396 #define HCLGE_CFG_RX_BUF_LEN_S 16
397 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16)
398 #define HCLGE_CFG_MAC_ADDR_H_S 0
399 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0)
400 #define HCLGE_CFG_DEFAULT_SPEED_S 16
401 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16)
403 struct hclge_cfg_param_cmd
{
409 #define HCLGE_MAC_MODE 0x0
410 #define HCLGE_DESC_NUM 0x40
412 #define HCLGE_ALLOC_VALID_B 0
413 struct hclge_vf_num_cmd
{
418 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4
419 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4
420 #define HCLGE_RSS_HASH_KEY_NUM 16
421 struct hclge_rss_config_cmd
{
424 u8 hash_key
[HCLGE_RSS_HASH_KEY_NUM
];
427 struct hclge_rss_input_tuple_cmd
{
439 #define HCLGE_RSS_CFG_TBL_SIZE 16
441 struct hclge_rss_indirection_table_cmd
{
442 __le16 start_table_index
;
443 __le16 rss_set_bitmap
;
445 u8 rss_result
[HCLGE_RSS_CFG_TBL_SIZE
];
448 #define HCLGE_RSS_TC_OFFSET_S 0
449 #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0)
450 #define HCLGE_RSS_TC_SIZE_S 12
451 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12)
452 #define HCLGE_RSS_TC_VALID_B 15
453 struct hclge_rss_tc_mode_cmd
{
454 __le16 rss_tc_mode
[HCLGE_MAX_TC_NUM
];
458 #define HCLGE_LINK_STS_B 0
459 #define HCLGE_LINK_STATUS BIT(HCLGE_LINK_STS_B)
460 struct hclge_link_status_cmd
{
465 struct hclge_promisc_param
{
470 #define HCLGE_PROMISC_EN_B 1
471 #define HCLGE_PROMISC_EN_ALL 0x7
472 #define HCLGE_PROMISC_EN_UC 0x1
473 #define HCLGE_PROMISC_EN_MC 0x2
474 #define HCLGE_PROMISC_EN_BC 0x4
475 struct hclge_promisc_cfg_cmd
{
482 enum hclge_promisc_type
{
488 #define HCLGE_MAC_TX_EN_B 6
489 #define HCLGE_MAC_RX_EN_B 7
490 #define HCLGE_MAC_PAD_TX_B 11
491 #define HCLGE_MAC_PAD_RX_B 12
492 #define HCLGE_MAC_1588_TX_B 13
493 #define HCLGE_MAC_1588_RX_B 14
494 #define HCLGE_MAC_APP_LP_B 15
495 #define HCLGE_MAC_LINE_LP_B 16
496 #define HCLGE_MAC_FCS_TX_B 17
497 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18
498 #define HCLGE_MAC_RX_FCS_STRIP_B 19
499 #define HCLGE_MAC_RX_FCS_B 20
500 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21
501 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22
503 struct hclge_config_mac_mode_cmd
{
504 __le32 txrx_pad_fcs_loop_en
;
508 #define HCLGE_CFG_SPEED_S 0
509 #define HCLGE_CFG_SPEED_M GENMASK(5, 0)
511 #define HCLGE_CFG_DUPLEX_B 7
512 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B)
514 struct hclge_config_mac_speed_dup_cmd
{
517 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
518 u8 mac_change_fec_en
;
522 #define HCLGE_QUERY_SPEED_S 3
523 #define HCLGE_QUERY_AN_B 0
524 #define HCLGE_QUERY_DUPLEX_B 2
526 #define HCLGE_QUERY_SPEED_M GENMASK(4, 0)
527 #define HCLGE_QUERY_AN_M BIT(HCLGE_QUERY_AN_B)
528 #define HCLGE_QUERY_DUPLEX_M BIT(HCLGE_QUERY_DUPLEX_B)
530 struct hclge_query_an_speed_dup_cmd
{
536 #define HCLGE_RING_ID_MASK GENMASK(9, 0)
537 #define HCLGE_TQP_ENABLE_B 0
539 #define HCLGE_MAC_CFG_AN_EN_B 0
540 #define HCLGE_MAC_CFG_AN_INT_EN_B 1
541 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2
542 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3
543 #define HCLGE_MAC_CFG_AN_RST_B 4
545 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B)
547 struct hclge_config_auto_neg_cmd
{
548 __le32 cfg_an_cmd_flag
;
552 #define HCLGE_MAC_MIN_MTU 64
553 #define HCLGE_MAC_MAX_MTU 9728
554 #define HCLGE_MAC_UPLINK_PORT 0x100
556 struct hclge_config_max_frm_size_cmd
{
561 enum hclge_mac_vlan_tbl_opcode
{
562 HCLGE_MAC_VLAN_ADD
, /* Add new or modify mac_vlan */
563 HCLGE_MAC_VLAN_UPDATE
, /* Modify other fields of this table */
564 HCLGE_MAC_VLAN_REMOVE
, /* Remove a entry through mac_vlan key */
565 HCLGE_MAC_VLAN_LKUP
, /* Lookup a entry through mac_vlan key */
568 #define HCLGE_MAC_VLAN_BIT0_EN_B 0x0
569 #define HCLGE_MAC_VLAN_BIT1_EN_B 0x1
570 #define HCLGE_MAC_EPORT_SW_EN_B 0xc
571 #define HCLGE_MAC_EPORT_TYPE_B 0xb
572 #define HCLGE_MAC_EPORT_VFID_S 0x3
573 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3)
574 #define HCLGE_MAC_EPORT_PFID_S 0x0
575 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0)
576 struct hclge_mac_vlan_tbl_entry_cmd
{
580 __le32 mac_addr_hi32
;
581 __le16 mac_addr_lo16
;
590 #define HCLGE_CFG_MTA_MAC_SEL_S 0x0
591 #define HCLGE_CFG_MTA_MAC_SEL_M GENMASK(1, 0)
592 #define HCLGE_CFG_MTA_MAC_EN_B 0x7
593 struct hclge_mta_filter_mode_cmd
{
594 u8 dmac_sel_en
; /* Use lowest 2 bit as sel_mode, bit 7 as enable */
598 #define HCLGE_CFG_FUNC_MTA_ACCEPT_B 0x0
599 struct hclge_cfg_func_mta_filter_cmd
{
600 u8 accept
; /* Only used lowest 1 bit */
605 #define HCLGE_CFG_MTA_ITEM_ACCEPT_B 0x0
606 #define HCLGE_CFG_MTA_ITEM_IDX_S 0x0
607 #define HCLGE_CFG_MTA_ITEM_IDX_M GENMASK(11, 0)
608 struct hclge_cfg_func_mta_item_cmd
{
609 __le16 item_idx
; /* Only used lowest 12 bit */
610 u8 accept
; /* Only used lowest 1 bit */
614 struct hclge_mac_vlan_add_cmd
{
616 __le16 mac_addr_hi16
;
617 __le32 mac_addr_lo32
;
618 __le32 mac_addr_msk_hi32
;
619 __le16 mac_addr_msk_lo16
;
626 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0
627 struct hclge_mac_vlan_remove_cmd
{
629 __le16 mac_addr_hi16
;
630 __le32 mac_addr_lo32
;
631 __le32 mac_addr_msk_hi32
;
632 __le16 mac_addr_msk_lo16
;
639 struct hclge_vlan_filter_ctrl_cmd
{
645 struct hclge_vlan_filter_pf_cfg_cmd
{
649 u8 vlan_offset_bitmap
[20];
652 struct hclge_vlan_filter_vf_cfg_cmd
{
661 struct hclge_cfg_com_tqp_queue_cmd
{
668 struct hclge_cfg_tx_queue_pointer_cmd
{
677 #define HCLGE_TSO_MSS_MIN_S 0
678 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0)
680 #define HCLGE_TSO_MSS_MAX_S 16
681 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16)
683 struct hclge_cfg_tso_status_cmd
{
689 #define HCLGE_TSO_MSS_MIN 256
690 #define HCLGE_TSO_MSS_MAX 9668
692 #define HCLGE_TQP_RESET_B 0
693 struct hclge_reset_tqp_queue_cmd
{
700 #define HCLGE_CFG_RESET_MAC_B 3
701 #define HCLGE_CFG_RESET_FUNC_B 7
702 struct hclge_reset_cmd
{
707 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */
708 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
709 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */
710 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */
712 #define HCLGE_TYPE_CRQ 0
713 #define HCLGE_TYPE_CSQ 1
714 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000
715 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004
716 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008
717 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010
718 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014
719 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018
720 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c
721 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020
722 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024
723 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028
724 #define HCLGE_NIC_CMQ_EN_B 16
725 #define HCLGE_NIC_CMQ_ENABLE BIT(HCLGE_NIC_CMQ_EN_B)
726 #define HCLGE_NIC_CMQ_DESC_NUM 1024
727 #define HCLGE_NIC_CMQ_DESC_NUM_S 3
729 int hclge_cmd_init(struct hclge_dev
*hdev
);
730 static inline void hclge_write_reg(void __iomem
*base
, u32 reg
, u32 value
)
732 writel(value
, base
+ reg
);
735 #define hclge_write_dev(a, reg, value) \
736 hclge_write_reg((a)->io_base, (reg), (value))
737 #define hclge_read_dev(a, reg) \
738 hclge_read_reg((a)->io_base, (reg))
740 static inline u32
hclge_read_reg(u8 __iomem
*base
, u32 reg
)
742 u8 __iomem
*reg_addr
= READ_ONCE(base
);
744 return readl(reg_addr
+ reg
);
747 #define HCLGE_SEND_SYNC(flag) \
748 ((flag) & HCLGE_CMD_FLAG_NO_INTR)
751 int hclge_cmd_send(struct hclge_hw
*hw
, struct hclge_desc
*desc
, int num
);
752 void hclge_cmd_setup_basic_desc(struct hclge_desc
*desc
,
753 enum hclge_opcode_type opcode
, bool is_read
);
754 void hclge_cmd_reuse_desc(struct hclge_desc
*desc
, bool is_read
);
756 int hclge_cmd_set_promisc_mode(struct hclge_dev
*hdev
,
757 struct hclge_promisc_param
*param
);
759 enum hclge_cmd_status
hclge_cmd_mdio_write(struct hclge_hw
*hw
,
760 struct hclge_desc
*desc
);
761 enum hclge_cmd_status
hclge_cmd_mdio_read(struct hclge_hw
*hw
,
762 struct hclge_desc
*desc
);
764 void hclge_destroy_cmd_queue(struct hclge_hw
*hw
);
765 int hclge_cmd_queue_init(struct hclge_dev
*hdev
);