drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

   1 /*
   2  * Copyright (c) 2016~2017 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #ifndef __HCLGE_CMD_H
  11 #define __HCLGE_CMD_H
  12 #include <linux/types.h>
  13 #include <linux/io.h>
  14
  15 #define HCLGE_CMDQ_TX_TIMEOUT           30000
  16
  17 struct hclge_dev;
  18 struct hclge_desc {
  19         __le16 opcode;
  20
  21 #define HCLGE_CMDQ_RX_INVLD_B           0
  22 #define HCLGE_CMDQ_RX_OUTVLD_B          1
  23
  24         __le16 flag;
  25         __le16 retval;
  26         __le16 rsv;
  27         __le32 data[6];
  28 };
  29
  30 struct hclge_cmq_ring {
  31         dma_addr_t desc_dma_addr;
  32         struct hclge_desc *desc;
  33         struct hclge_dev *dev;
  34         u32 head;
  35         u32 tail;
  36
  37         u16 buf_size;
  38         u16 desc_num;
  39         int next_to_use;
  40         int next_to_clean;
  41         u8 ring_type; /* cmq ring type */
  42         spinlock_t lock; /* Command queue lock */
  43 };
  44
  45 enum hclge_cmd_return_status {
  46         HCLGE_CMD_EXEC_SUCCESS  = 0,
  47         HCLGE_CMD_NO_AUTH       = 1,
  48         HCLGE_CMD_NOT_EXEC      = 2,
  49         HCLGE_CMD_QUEUE_FULL    = 3,
  50 };
  51
  52 enum hclge_cmd_status {
  53         HCLGE_STATUS_SUCCESS    = 0,
  54         HCLGE_ERR_CSQ_FULL      = -1,
  55         HCLGE_ERR_CSQ_TIMEOUT   = -2,
  56         HCLGE_ERR_CSQ_ERROR     = -3,
  57 };
  58
  59 struct hclge_misc_vector {
  60         u8 __iomem *addr;
  61         int vector_irq;
  62 };
  63
  64 struct hclge_cmq {
  65         struct hclge_cmq_ring csq;
  66         struct hclge_cmq_ring crq;
  67         u16 tx_timeout;
  68         enum hclge_cmd_status last_status;
  69 };
  70
  71 #define HCLGE_CMD_FLAG_IN       BIT(0)
  72 #define HCLGE_CMD_FLAG_OUT      BIT(1)
  73 #define HCLGE_CMD_FLAG_NEXT     BIT(2)
  74 #define HCLGE_CMD_FLAG_WR       BIT(3)
  75 #define HCLGE_CMD_FLAG_NO_INTR  BIT(4)
  76 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5)
  77
  78 enum hclge_opcode_type {
  79         /* Generic commands */
  80         HCLGE_OPC_QUERY_FW_VER          = 0x0001,
  81         HCLGE_OPC_CFG_RST_TRIGGER       = 0x0020,
  82         HCLGE_OPC_GBL_RST_STATUS        = 0x0021,
  83         HCLGE_OPC_QUERY_FUNC_STATUS     = 0x0022,
  84         HCLGE_OPC_QUERY_PF_RSRC         = 0x0023,
  85         HCLGE_OPC_QUERY_VF_RSRC         = 0x0024,
  86         HCLGE_OPC_GET_CFG_PARAM         = 0x0025,
  87
  88         HCLGE_OPC_STATS_64_BIT          = 0x0030,
  89         HCLGE_OPC_STATS_32_BIT          = 0x0031,
  90         HCLGE_OPC_STATS_MAC             = 0x0032,
  91
  92         HCLGE_OPC_QUERY_REG_NUM         = 0x0040,
  93         HCLGE_OPC_QUERY_32_BIT_REG      = 0x0041,
  94         HCLGE_OPC_QUERY_64_BIT_REG      = 0x0042,
  95
  96         /* MAC command */
  97         HCLGE_OPC_CONFIG_MAC_MODE       = 0x0301,
  98         HCLGE_OPC_CONFIG_AN_MODE        = 0x0304,
  99         HCLGE_OPC_QUERY_AN_RESULT       = 0x0306,
 100         HCLGE_OPC_QUERY_LINK_STATUS     = 0x0307,
 101         HCLGE_OPC_CONFIG_MAX_FRM_SIZE   = 0x0308,
 102         HCLGE_OPC_CONFIG_SPEED_DUP      = 0x0309,
 103         HCLGE_OPC_SERDES_LOOPBACK       = 0x0315,
 104
 105         /* PFC/Pause commands*/
 106         HCLGE_OPC_CFG_MAC_PAUSE_EN      = 0x0701,
 107         HCLGE_OPC_CFG_PFC_PAUSE_EN      = 0x0702,
 108         HCLGE_OPC_CFG_MAC_PARA          = 0x0703,
 109         HCLGE_OPC_CFG_PFC_PARA          = 0x0704,
 110         HCLGE_OPC_QUERY_MAC_TX_PKT_CNT  = 0x0705,
 111         HCLGE_OPC_QUERY_MAC_RX_PKT_CNT  = 0x0706,
 112         HCLGE_OPC_QUERY_PFC_TX_PKT_CNT  = 0x0707,
 113         HCLGE_OPC_QUERY_PFC_RX_PKT_CNT  = 0x0708,
 114         HCLGE_OPC_PRI_TO_TC_MAPPING     = 0x0709,
 115         HCLGE_OPC_QOS_MAP               = 0x070A,
 116
 117         /* ETS/scheduler commands */
 118         HCLGE_OPC_TM_PG_TO_PRI_LINK     = 0x0804,
 119         HCLGE_OPC_TM_QS_TO_PRI_LINK     = 0x0805,
 120         HCLGE_OPC_TM_NQ_TO_QS_LINK      = 0x0806,
 121         HCLGE_OPC_TM_RQ_TO_QS_LINK      = 0x0807,
 122         HCLGE_OPC_TM_PORT_WEIGHT        = 0x0808,
 123         HCLGE_OPC_TM_PG_WEIGHT          = 0x0809,
 124         HCLGE_OPC_TM_QS_WEIGHT          = 0x080A,
 125         HCLGE_OPC_TM_PRI_WEIGHT         = 0x080B,
 126         HCLGE_OPC_TM_PRI_C_SHAPPING     = 0x080C,
 127         HCLGE_OPC_TM_PRI_P_SHAPPING     = 0x080D,
 128         HCLGE_OPC_TM_PG_C_SHAPPING      = 0x080E,
 129         HCLGE_OPC_TM_PG_P_SHAPPING      = 0x080F,
 130         HCLGE_OPC_TM_PORT_SHAPPING      = 0x0810,
 131         HCLGE_OPC_TM_PG_SCH_MODE_CFG    = 0x0812,
 132         HCLGE_OPC_TM_PRI_SCH_MODE_CFG   = 0x0813,
 133         HCLGE_OPC_TM_QS_SCH_MODE_CFG    = 0x0814,
 134         HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
 135
 136         /* Packet buffer allocate commands */
 137         HCLGE_OPC_TX_BUFF_ALLOC         = 0x0901,
 138         HCLGE_OPC_RX_PRIV_BUFF_ALLOC    = 0x0902,
 139         HCLGE_OPC_RX_PRIV_WL_ALLOC      = 0x0903,
 140         HCLGE_OPC_RX_COM_THRD_ALLOC     = 0x0904,
 141         HCLGE_OPC_RX_COM_WL_ALLOC       = 0x0905,
 142         HCLGE_OPC_RX_GBL_PKT_CNT        = 0x0906,
 143
 144         /* TQP management command */
 145         HCLGE_OPC_SET_TQP_MAP           = 0x0A01,
 146
 147         /* TQP commands */
 148         HCLGE_OPC_CFG_TX_QUEUE          = 0x0B01,
 149         HCLGE_OPC_QUERY_TX_POINTER      = 0x0B02,
 150         HCLGE_OPC_QUERY_TX_STATUS       = 0x0B03,
 151         HCLGE_OPC_CFG_RX_QUEUE          = 0x0B11,
 152         HCLGE_OPC_QUERY_RX_POINTER      = 0x0B12,
 153         HCLGE_OPC_QUERY_RX_STATUS       = 0x0B13,
 154         HCLGE_OPC_STASH_RX_QUEUE_LRO    = 0x0B16,
 155         HCLGE_OPC_CFG_RX_QUEUE_LRO      = 0x0B17,
 156         HCLGE_OPC_CFG_COM_TQP_QUEUE     = 0x0B20,
 157         HCLGE_OPC_RESET_TQP_QUEUE       = 0x0B22,
 158
 159         /* TSO command */
 160         HCLGE_OPC_TSO_GENERIC_CONFIG    = 0x0C01,
 161
 162         /* RSS commands */
 163         HCLGE_OPC_RSS_GENERIC_CONFIG    = 0x0D01,
 164         HCLGE_OPC_RSS_INDIR_TABLE       = 0x0D07,
 165         HCLGE_OPC_RSS_TC_MODE           = 0x0D08,
 166         HCLGE_OPC_RSS_INPUT_TUPLE       = 0x0D02,
 167
 168         /* Promisuous mode command */
 169         HCLGE_OPC_CFG_PROMISC_MODE      = 0x0E01,
 170
 171         /* Vlan offload commands */
 172         HCLGE_OPC_VLAN_PORT_TX_CFG      = 0x0F01,
 173         HCLGE_OPC_VLAN_PORT_RX_CFG      = 0x0F02,
 174
 175         /* Interrupts commands */
 176         HCLGE_OPC_ADD_RING_TO_VECTOR    = 0x1503,
 177         HCLGE_OPC_DEL_RING_TO_VECTOR    = 0x1504,
 178
 179         /* MAC commands */
 180         HCLGE_OPC_MAC_VLAN_ADD              = 0x1000,
 181         HCLGE_OPC_MAC_VLAN_REMOVE           = 0x1001,
 182         HCLGE_OPC_MAC_VLAN_TYPE_ID          = 0x1002,
 183         HCLGE_OPC_MAC_VLAN_INSERT           = 0x1003,
 184         HCLGE_OPC_MAC_ETHTYPE_ADD           = 0x1010,
 185         HCLGE_OPC_MAC_ETHTYPE_REMOVE    = 0x1011,
 186         HCLGE_OPC_MAC_VLAN_MASK_SET     = 0x1012,
 187
 188         /* Multicast linear table commands */
 189         HCLGE_OPC_MTA_MAC_MODE_CFG          = 0x1020,
 190         HCLGE_OPC_MTA_MAC_FUNC_CFG          = 0x1021,
 191         HCLGE_OPC_MTA_TBL_ITEM_CFG          = 0x1022,
 192         HCLGE_OPC_MTA_TBL_ITEM_QUERY    = 0x1023,
 193
 194         /* VLAN commands */
 195         HCLGE_OPC_VLAN_FILTER_CTRL          = 0x1100,
 196         HCLGE_OPC_VLAN_FILTER_PF_CFG    = 0x1101,
 197         HCLGE_OPC_VLAN_FILTER_VF_CFG    = 0x1102,
 198
 199         /* MDIO command */
 200         HCLGE_OPC_MDIO_CONFIG           = 0x1900,
 201
 202         /* QCN commands */
 203         HCLGE_OPC_QCN_MOD_CFG           = 0x1A01,
 204         HCLGE_OPC_QCN_GRP_TMPLT_CFG     = 0x1A02,
 205         HCLGE_OPC_QCN_SHAPPING_IR_CFG   = 0x1A03,
 206         HCLGE_OPC_QCN_SHAPPING_BS_CFG   = 0x1A04,
 207         HCLGE_OPC_QCN_QSET_LINK_CFG     = 0x1A05,
 208         HCLGE_OPC_QCN_RP_STATUS_GET     = 0x1A06,
 209         HCLGE_OPC_QCN_AJUST_INIT        = 0x1A07,
 210         HCLGE_OPC_QCN_DFX_CNT_STATUS    = 0x1A08,
 211
 212         /* Mailbox command */
 213         HCLGEVF_OPC_MBX_PF_TO_VF        = 0x2000,
 214
 215         /* Led command */
 216         HCLGE_OPC_LED_STATUS_CFG        = 0xB000,
 217 };
 218
 219 #define HCLGE_TQP_REG_OFFSET            0x80000
 220 #define HCLGE_TQP_REG_SIZE              0x200
 221
 222 #define HCLGE_RCB_INIT_QUERY_TIMEOUT    10
 223 #define HCLGE_RCB_INIT_FLAG_EN_B        0
 224 #define HCLGE_RCB_INIT_FLAG_FINI_B      8
 225 struct hclge_config_rcb_init_cmd {
 226         __le16 rcb_init_flag;
 227         u8 rsv[22];
 228 };
 229
 230 struct hclge_tqp_map_cmd {
 231         __le16 tqp_id;  /* Absolute tqp id for in this pf */
 232         u8 tqp_vf;      /* VF id */
 233 #define HCLGE_TQP_MAP_TYPE_PF           0
 234 #define HCLGE_TQP_MAP_TYPE_VF           1
 235 #define HCLGE_TQP_MAP_TYPE_B            0
 236 #define HCLGE_TQP_MAP_EN_B              1
 237         u8 tqp_flag;    /* Indicate it's pf or vf tqp */
 238         __le16 tqp_vid; /* Virtual id in this pf/vf */
 239         u8 rsv[18];
 240 };
 241
 242 #define HCLGE_VECTOR_ELEMENTS_PER_CMD   10
 243
 244 enum hclge_int_type {
 245         HCLGE_INT_TX,
 246         HCLGE_INT_RX,
 247         HCLGE_INT_EVENT,
 248 };
 249
 250 struct hclge_ctrl_vector_chain_cmd {
 251         u8 int_vector_id;
 252         u8 int_cause_num;
 253 #define HCLGE_INT_TYPE_S        0
 254 #define HCLGE_INT_TYPE_M        GENMASK(1, 0)
 255 #define HCLGE_TQP_ID_S          2
 256 #define HCLGE_TQP_ID_M          GENMASK(12, 2)
 257 #define HCLGE_INT_GL_IDX_S      13
 258 #define HCLGE_INT_GL_IDX_M      GENMASK(14, 13)
 259         __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];
 260         u8 vfid;
 261         u8 rsv;
 262 };
 263
 264 #define HCLGE_TC_NUM            8
 265 #define HCLGE_TC0_PRI_BUF_EN_B  15 /* Bit 15 indicate enable or not */
 266 #define HCLGE_BUF_UNIT_S        7  /* Buf size is united by 128 bytes */
 267 struct hclge_tx_buff_alloc_cmd {
 268         __le16 tx_pkt_buff[HCLGE_TC_NUM];
 269         u8 tx_buff_rsv[8];
 270 };
 271
 272 struct hclge_rx_priv_buff_cmd {
 273         __le16 buf_num[HCLGE_TC_NUM];
 274         __le16 shared_buf;
 275         u8 rsv[6];
 276 };
 277
 278 struct hclge_query_version_cmd {
 279         __le32 firmware;
 280         __le32 firmware_rsv[5];
 281 };
 282
 283 #define HCLGE_RX_PRIV_EN_B      15
 284 #define HCLGE_TC_NUM_ONE_DESC   4
 285 struct hclge_priv_wl {
 286         __le16 high;
 287         __le16 low;
 288 };
 289
 290 struct hclge_rx_priv_wl_buf {
 291         struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC];
 292 };
 293
 294 struct hclge_rx_com_thrd {
 295         struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC];
 296 };
 297
 298 struct hclge_rx_com_wl {
 299         struct hclge_priv_wl com_wl;
 300 };
 301
 302 struct hclge_waterline {
 303         u32 low;
 304         u32 high;
 305 };
 306
 307 struct hclge_tc_thrd {
 308         u32 low;
 309         u32 high;
 310 };
 311
 312 struct hclge_priv_buf {
 313         struct hclge_waterline wl;      /* Waterline for low and high*/
 314         u32 buf_size;   /* TC private buffer size */
 315         u32 tx_buf_size;
 316         u32 enable;     /* Enable TC private buffer or not */
 317 };
 318
 319 #define HCLGE_MAX_TC_NUM        8
 320 struct hclge_shared_buf {
 321         struct hclge_waterline self;
 322         struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM];
 323         u32 buf_size;
 324 };
 325
 326 struct hclge_pkt_buf_alloc {
 327         struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM];
 328         struct hclge_shared_buf s_buf;
 329 };
 330
 331 #define HCLGE_RX_COM_WL_EN_B    15
 332 struct hclge_rx_com_wl_buf_cmd {
 333         __le16 high_wl;
 334         __le16 low_wl;
 335         u8 rsv[20];
 336 };
 337
 338 #define HCLGE_RX_PKT_EN_B       15
 339 struct hclge_rx_pkt_buf_cmd {
 340         __le16 high_pkt;
 341         __le16 low_pkt;
 342         u8 rsv[20];
 343 };
 344
 345 #define HCLGE_PF_STATE_DONE_B   0
 346 #define HCLGE_PF_STATE_MAIN_B   1
 347 #define HCLGE_PF_STATE_BOND_B   2
 348 #define HCLGE_PF_STATE_MAC_N_B  6
 349 #define HCLGE_PF_MAC_NUM_MASK   0x3
 350 #define HCLGE_PF_STATE_MAIN     BIT(HCLGE_PF_STATE_MAIN_B)
 351 #define HCLGE_PF_STATE_DONE     BIT(HCLGE_PF_STATE_DONE_B)
 352 struct hclge_func_status_cmd {
 353         __le32  vf_rst_state[4];
 354         u8 pf_state;
 355         u8 mac_id;
 356         u8 rsv1;
 357         u8 pf_cnt_in_mac;
 358         u8 pf_num;
 359         u8 vf_num;
 360         u8 rsv[2];
 361 };
 362
 363 struct hclge_pf_res_cmd {
 364         __le16 tqp_num;
 365         __le16 buf_size;
 366         __le16 msixcap_localid_ba_nic;
 367         __le16 msixcap_localid_ba_rocee;
 368 #define HCLGE_PF_VEC_NUM_S              0
 369 #define HCLGE_PF_VEC_NUM_M              GENMASK(7, 0)
 370         __le16 pf_intr_vector_number;
 371         __le16 pf_own_fun_number;
 372         __le32 rsv[3];
 373 };
 374
 375 #define HCLGE_CFG_OFFSET_S      0
 376 #define HCLGE_CFG_OFFSET_M      GENMASK(19, 0)
 377 #define HCLGE_CFG_RD_LEN_S      24
 378 #define HCLGE_CFG_RD_LEN_M      GENMASK(27, 24)
 379 #define HCLGE_CFG_RD_LEN_BYTES  16
 380 #define HCLGE_CFG_RD_LEN_UNIT   4
 381
 382 #define HCLGE_CFG_VMDQ_S        0
 383 #define HCLGE_CFG_VMDQ_M        GENMASK(7, 0)
 384 #define HCLGE_CFG_TC_NUM_S      8
 385 #define HCLGE_CFG_TC_NUM_M      GENMASK(15, 8)
 386 #define HCLGE_CFG_TQP_DESC_N_S  16
 387 #define HCLGE_CFG_TQP_DESC_N_M  GENMASK(31, 16)
 388 #define HCLGE_CFG_PHY_ADDR_S    0
 389 #define HCLGE_CFG_PHY_ADDR_M    GENMASK(7, 0)
 390 #define HCLGE_CFG_MEDIA_TP_S    8
 391 #define HCLGE_CFG_MEDIA_TP_M    GENMASK(15, 8)
 392 #define HCLGE_CFG_RX_BUF_LEN_S  16
 393 #define HCLGE_CFG_RX_BUF_LEN_M  GENMASK(31, 16)
 394 #define HCLGE_CFG_MAC_ADDR_H_S  0
 395 #define HCLGE_CFG_MAC_ADDR_H_M  GENMASK(15, 0)
 396 #define HCLGE_CFG_DEFAULT_SPEED_S       16
 397 #define HCLGE_CFG_DEFAULT_SPEED_M       GENMASK(23, 16)
 398 #define HCLGE_CFG_RSS_SIZE_S    24
 399 #define HCLGE_CFG_RSS_SIZE_M    GENMASK(31, 24)
 400 #define HCLGE_CFG_SPEED_ABILITY_S       0
 401 #define HCLGE_CFG_SPEED_ABILITY_M       GENMASK(7, 0)
 402
 403 struct hclge_cfg_param_cmd {
 404         __le32 offset;
 405         __le32 rsv;
 406         __le32 param[4];
 407 };
 408
 409 #define HCLGE_MAC_MODE          0x0
 410 #define HCLGE_DESC_NUM          0x40
 411
 412 #define HCLGE_ALLOC_VALID_B     0
 413 struct hclge_vf_num_cmd {
 414         u8 alloc_valid;
 415         u8 rsv[23];
 416 };
 417
 418 #define HCLGE_RSS_DEFAULT_OUTPORT_B     4
 419 #define HCLGE_RSS_HASH_KEY_OFFSET_B     4
 420 #define HCLGE_RSS_HASH_KEY_NUM          16
 421 struct hclge_rss_config_cmd {
 422         u8 hash_config;
 423         u8 rsv[7];
 424         u8 hash_key[HCLGE_RSS_HASH_KEY_NUM];
 425 };
 426
 427 struct hclge_rss_input_tuple_cmd {
 428         u8 ipv4_tcp_en;
 429         u8 ipv4_udp_en;
 430         u8 ipv4_sctp_en;
 431         u8 ipv4_fragment_en;
 432         u8 ipv6_tcp_en;
 433         u8 ipv6_udp_en;
 434         u8 ipv6_sctp_en;
 435         u8 ipv6_fragment_en;
 436         u8 rsv[16];
 437 };
 438
 439 #define HCLGE_RSS_CFG_TBL_SIZE  16
 440
 441 struct hclge_rss_indirection_table_cmd {
 442         __le16 start_table_index;
 443         __le16 rss_set_bitmap;
 444         u8 rsv[4];
 445         u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE];
 446 };
 447
 448 #define HCLGE_RSS_TC_OFFSET_S           0
 449 #define HCLGE_RSS_TC_OFFSET_M           GENMASK(9, 0)
 450 #define HCLGE_RSS_TC_SIZE_S             12
 451 #define HCLGE_RSS_TC_SIZE_M             GENMASK(14, 12)
 452 #define HCLGE_RSS_TC_VALID_B            15
 453 struct hclge_rss_tc_mode_cmd {
 454         __le16 rss_tc_mode[HCLGE_MAX_TC_NUM];
 455         u8 rsv[8];
 456 };
 457
 458 #define HCLGE_LINK_STATUS_UP_B  0
 459 #define HCLGE_LINK_STATUS_UP_M  BIT(HCLGE_LINK_STATUS_UP_B)
 460 struct hclge_link_status_cmd {
 461         u8 status;
 462         u8 rsv[23];
 463 };
 464
 465 struct hclge_promisc_param {
 466         u8 vf_id;
 467         u8 enable;
 468 };
 469
 470 #define HCLGE_PROMISC_TX_EN_B   BIT(4)
 471 #define HCLGE_PROMISC_RX_EN_B   BIT(5)
 472 #define HCLGE_PROMISC_EN_B      1
 473 #define HCLGE_PROMISC_EN_ALL    0x7
 474 #define HCLGE_PROMISC_EN_UC     0x1
 475 #define HCLGE_PROMISC_EN_MC     0x2
 476 #define HCLGE_PROMISC_EN_BC     0x4
 477 struct hclge_promisc_cfg_cmd {
 478         u8 flag;
 479         u8 vf_id;
 480         __le16 rsv0;
 481         u8 rsv1[20];
 482 };
 483
 484 enum hclge_promisc_type {
 485         HCLGE_UNICAST   = 1,
 486         HCLGE_MULTICAST = 2,
 487         HCLGE_BROADCAST = 3,
 488 };
 489
 490 #define HCLGE_MAC_TX_EN_B       6
 491 #define HCLGE_MAC_RX_EN_B       7
 492 #define HCLGE_MAC_PAD_TX_B      11
 493 #define HCLGE_MAC_PAD_RX_B      12
 494 #define HCLGE_MAC_1588_TX_B     13
 495 #define HCLGE_MAC_1588_RX_B     14
 496 #define HCLGE_MAC_APP_LP_B      15
 497 #define HCLGE_MAC_LINE_LP_B     16
 498 #define HCLGE_MAC_FCS_TX_B      17
 499 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B        18
 500 #define HCLGE_MAC_RX_FCS_STRIP_B        19
 501 #define HCLGE_MAC_RX_FCS_B      20
 502 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B            21
 503 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B        22
 504
 505 struct hclge_config_mac_mode_cmd {
 506         __le32 txrx_pad_fcs_loop_en;
 507         u8 rsv[20];
 508 };
 509
 510 #define HCLGE_CFG_SPEED_S               0
 511 #define HCLGE_CFG_SPEED_M               GENMASK(5, 0)
 512
 513 #define HCLGE_CFG_DUPLEX_B              7
 514 #define HCLGE_CFG_DUPLEX_M              BIT(HCLGE_CFG_DUPLEX_B)
 515
 516 struct hclge_config_mac_speed_dup_cmd {
 517         u8 speed_dup;
 518
 519 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
 520         u8 mac_change_fec_en;
 521         u8 rsv[22];
 522 };
 523
 524 #define HCLGE_QUERY_SPEED_S             3
 525 #define HCLGE_QUERY_AN_B                0
 526 #define HCLGE_QUERY_DUPLEX_B            2
 527
 528 #define HCLGE_QUERY_SPEED_M             GENMASK(4, 0)
 529 #define HCLGE_QUERY_AN_M                BIT(HCLGE_QUERY_AN_B)
 530 #define HCLGE_QUERY_DUPLEX_M            BIT(HCLGE_QUERY_DUPLEX_B)
 531
 532 struct hclge_query_an_speed_dup_cmd {
 533         u8 an_syn_dup_speed;
 534         u8 pause;
 535         u8 rsv[23];
 536 };
 537
 538 #define HCLGE_RING_ID_MASK              GENMASK(9, 0)
 539 #define HCLGE_TQP_ENABLE_B              0
 540
 541 #define HCLGE_MAC_CFG_AN_EN_B           0
 542 #define HCLGE_MAC_CFG_AN_INT_EN_B       1
 543 #define HCLGE_MAC_CFG_AN_INT_MSK_B      2
 544 #define HCLGE_MAC_CFG_AN_INT_CLR_B      3
 545 #define HCLGE_MAC_CFG_AN_RST_B          4
 546
 547 #define HCLGE_MAC_CFG_AN_EN     BIT(HCLGE_MAC_CFG_AN_EN_B)
 548
 549 struct hclge_config_auto_neg_cmd {
 550         __le32  cfg_an_cmd_flag;
 551         u8      rsv[20];
 552 };
 553
 554 #define HCLGE_MAC_UPLINK_PORT           0x100
 555
 556 struct hclge_config_max_frm_size_cmd {
 557         __le16  max_frm_size;
 558         u8      rsv[22];
 559 };
 560
 561 enum hclge_mac_vlan_tbl_opcode {
 562         HCLGE_MAC_VLAN_ADD,     /* Add new or modify mac_vlan */
 563         HCLGE_MAC_VLAN_UPDATE,  /* Modify other fields of this table */
 564         HCLGE_MAC_VLAN_REMOVE,  /* Remove a entry through mac_vlan key */
 565         HCLGE_MAC_VLAN_LKUP,    /* Lookup a entry through mac_vlan key */
 566 };
 567
 568 #define HCLGE_MAC_VLAN_BIT0_EN_B        0
 569 #define HCLGE_MAC_VLAN_BIT1_EN_B        1
 570 #define HCLGE_MAC_EPORT_SW_EN_B         12
 571 #define HCLGE_MAC_EPORT_TYPE_B          11
 572 #define HCLGE_MAC_EPORT_VFID_S          3
 573 #define HCLGE_MAC_EPORT_VFID_M          GENMASK(10, 3)
 574 #define HCLGE_MAC_EPORT_PFID_S          0
 575 #define HCLGE_MAC_EPORT_PFID_M          GENMASK(2, 0)
 576 struct hclge_mac_vlan_tbl_entry_cmd {
 577         u8      flags;
 578         u8      resp_code;
 579         __le16  vlan_tag;
 580         __le32  mac_addr_hi32;
 581         __le16  mac_addr_lo16;
 582         __le16  rsv1;
 583         u8      entry_type;
 584         u8      mc_mac_en;
 585         __le16  egress_port;
 586         __le16  egress_queue;
 587         u8      rsv2[6];
 588 };
 589
 590 #define HCLGE_VLAN_MASK_EN_B            0
 591 struct hclge_mac_vlan_mask_entry_cmd {
 592         u8 rsv0[2];
 593         u8 vlan_mask;
 594         u8 rsv1;
 595         u8 mac_mask[6];
 596         u8 rsv2[14];
 597 };
 598
 599 #define HCLGE_MAC_MGR_MASK_VLAN_B               BIT(0)
 600 #define HCLGE_MAC_MGR_MASK_MAC_B                BIT(1)
 601 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B          BIT(2)
 602 #define HCLGE_MAC_ETHERTYPE_LLDP                0x88cc
 603
 604 struct hclge_mac_mgr_tbl_entry_cmd {
 605         u8      flags;
 606         u8      resp_code;
 607         __le16  vlan_tag;
 608         __le32  mac_addr_hi32;
 609         __le16  mac_addr_lo16;
 610         __le16  rsv1;
 611         __le16  ethter_type;
 612         __le16  egress_port;
 613         __le16  egress_queue;
 614         u8      sw_port_id_aware;
 615         u8      rsv2;
 616         u8      i_port_bitmap;
 617         u8      i_port_direction;
 618         u8      rsv3[2];
 619 };
 620
 621 #define HCLGE_CFG_MTA_MAC_SEL_S         0
 622 #define HCLGE_CFG_MTA_MAC_SEL_M         GENMASK(1, 0)
 623 #define HCLGE_CFG_MTA_MAC_EN_B          7
 624 struct hclge_mta_filter_mode_cmd {
 625         u8      dmac_sel_en; /* Use lowest 2 bit as sel_mode, bit 7 as enable */
 626         u8      rsv[23];
 627 };
 628
 629 #define HCLGE_CFG_FUNC_MTA_ACCEPT_B     0
 630 struct hclge_cfg_func_mta_filter_cmd {
 631         u8      accept; /* Only used lowest 1 bit */
 632         u8      function_id;
 633         u8      rsv[22];
 634 };
 635
 636 #define HCLGE_CFG_MTA_ITEM_ACCEPT_B     0
 637 #define HCLGE_CFG_MTA_ITEM_IDX_S        0
 638 #define HCLGE_CFG_MTA_ITEM_IDX_M        GENMASK(11, 0)
 639 struct hclge_cfg_func_mta_item_cmd {
 640         __le16  item_idx; /* Only used lowest 12 bit */
 641         u8      accept;   /* Only used lowest 1 bit */
 642         u8      rsv[21];
 643 };
 644
 645 struct hclge_mac_vlan_add_cmd {
 646         __le16  flags;
 647         __le16  mac_addr_hi16;
 648         __le32  mac_addr_lo32;
 649         __le32  mac_addr_msk_hi32;
 650         __le16  mac_addr_msk_lo16;
 651         __le16  vlan_tag;
 652         __le16  ingress_port;
 653         __le16  egress_port;
 654         u8      rsv[4];
 655 };
 656
 657 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0
 658 struct hclge_mac_vlan_remove_cmd {
 659         __le16  flags;
 660         __le16  mac_addr_hi16;
 661         __le32  mac_addr_lo32;
 662         __le32  mac_addr_msk_hi32;
 663         __le16  mac_addr_msk_lo16;
 664         __le16  vlan_tag;
 665         __le16  ingress_port;
 666         __le16  egress_port;
 667         u8      rsv[4];
 668 };
 669
 670 struct hclge_vlan_filter_ctrl_cmd {
 671         u8 vlan_type;
 672         u8 vlan_fe;
 673         u8 rsv[22];
 674 };
 675
 676 struct hclge_vlan_filter_pf_cfg_cmd {
 677         u8 vlan_offset;
 678         u8 vlan_cfg;
 679         u8 rsv[2];
 680         u8 vlan_offset_bitmap[20];
 681 };
 682
 683 struct hclge_vlan_filter_vf_cfg_cmd {
 684         __le16 vlan_id;
 685         u8  resp_code;
 686         u8  rsv;
 687         u8  vlan_cfg;
 688         u8  rsv1[3];
 689         u8  vf_bitmap[16];
 690 };
 691
 692 #define HCLGE_ACCEPT_TAG1_B             0
 693 #define HCLGE_ACCEPT_UNTAG1_B           1
 694 #define HCLGE_PORT_INS_TAG1_EN_B        2
 695 #define HCLGE_PORT_INS_TAG2_EN_B        3
 696 #define HCLGE_CFG_NIC_ROCE_SEL_B        4
 697 #define HCLGE_ACCEPT_TAG2_B             5
 698 #define HCLGE_ACCEPT_UNTAG2_B           6
 699
 700 struct hclge_vport_vtag_tx_cfg_cmd {
 701         u8 vport_vlan_cfg;
 702         u8 vf_offset;
 703         u8 rsv1[2];
 704         __le16 def_vlan_tag1;
 705         __le16 def_vlan_tag2;
 706         u8 vf_bitmap[8];
 707         u8 rsv2[8];
 708 };
 709
 710 #define HCLGE_REM_TAG1_EN_B             0
 711 #define HCLGE_REM_TAG2_EN_B             1
 712 #define HCLGE_SHOW_TAG1_EN_B            2
 713 #define HCLGE_SHOW_TAG2_EN_B            3
 714 struct hclge_vport_vtag_rx_cfg_cmd {
 715         u8 vport_vlan_cfg;
 716         u8 vf_offset;
 717         u8 rsv1[6];
 718         u8 vf_bitmap[8];
 719         u8 rsv2[8];
 720 };
 721
 722 struct hclge_tx_vlan_type_cfg_cmd {
 723         __le16 ot_vlan_type;
 724         __le16 in_vlan_type;
 725         u8 rsv[20];
 726 };
 727
 728 struct hclge_rx_vlan_type_cfg_cmd {
 729         __le16 ot_fst_vlan_type;
 730         __le16 ot_sec_vlan_type;
 731         __le16 in_fst_vlan_type;
 732         __le16 in_sec_vlan_type;
 733         u8 rsv[16];
 734 };
 735
 736 struct hclge_cfg_com_tqp_queue_cmd {
 737         __le16 tqp_id;
 738         __le16 stream_id;
 739         u8 enable;
 740         u8 rsv[19];
 741 };
 742
 743 struct hclge_cfg_tx_queue_pointer_cmd {
 744         __le16 tqp_id;
 745         __le16 tx_tail;
 746         __le16 tx_head;
 747         __le16 fbd_num;
 748         __le16 ring_offset;
 749         u8 rsv[14];
 750 };
 751
 752 #define HCLGE_TSO_MSS_MIN_S     0
 753 #define HCLGE_TSO_MSS_MIN_M     GENMASK(13, 0)
 754
 755 #define HCLGE_TSO_MSS_MAX_S     16
 756 #define HCLGE_TSO_MSS_MAX_M     GENMASK(29, 16)
 757
 758 struct hclge_cfg_tso_status_cmd {
 759         __le16 tso_mss_min;
 760         __le16 tso_mss_max;
 761         u8 rsv[20];
 762 };
 763
 764 #define HCLGE_TSO_MSS_MIN       256
 765 #define HCLGE_TSO_MSS_MAX       9668
 766
 767 #define HCLGE_TQP_RESET_B       0
 768 struct hclge_reset_tqp_queue_cmd {
 769         __le16 tqp_id;
 770         u8 reset_req;
 771         u8 ready_to_reset;
 772         u8 rsv[20];
 773 };
 774
 775 #define HCLGE_CFG_RESET_MAC_B           3
 776 #define HCLGE_CFG_RESET_FUNC_B          7
 777 struct hclge_reset_cmd {
 778         u8 mac_func_reset;
 779         u8 fun_reset_vfid;
 780         u8 rsv[22];
 781 };
 782
 783 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B    BIT(0)
 784 #define HCLGE_CMD_SERDES_DONE_B                 BIT(0)
 785 #define HCLGE_CMD_SERDES_SUCCESS_B              BIT(1)
 786 struct hclge_serdes_lb_cmd {
 787         u8 mask;
 788         u8 enable;
 789         u8 result;
 790         u8 rsv[21];
 791 };
 792
 793 #define HCLGE_DEFAULT_TX_BUF            0x4000   /* 16k  bytes */
 794 #define HCLGE_TOTAL_PKT_BUF             0x108000 /* 1.03125M bytes */
 795 #define HCLGE_DEFAULT_DV                0xA000   /* 40k byte */
 796 #define HCLGE_DEFAULT_NON_DCB_DV        0x7800  /* 30K byte */
 797
 798 #define HCLGE_TYPE_CRQ                  0
 799 #define HCLGE_TYPE_CSQ                  1
 800 #define HCLGE_NIC_CSQ_BASEADDR_L_REG    0x27000
 801 #define HCLGE_NIC_CSQ_BASEADDR_H_REG    0x27004
 802 #define HCLGE_NIC_CSQ_DEPTH_REG         0x27008
 803 #define HCLGE_NIC_CSQ_TAIL_REG          0x27010
 804 #define HCLGE_NIC_CSQ_HEAD_REG          0x27014
 805 #define HCLGE_NIC_CRQ_BASEADDR_L_REG    0x27018
 806 #define HCLGE_NIC_CRQ_BASEADDR_H_REG    0x2701c
 807 #define HCLGE_NIC_CRQ_DEPTH_REG         0x27020
 808 #define HCLGE_NIC_CRQ_TAIL_REG          0x27024
 809 #define HCLGE_NIC_CRQ_HEAD_REG          0x27028
 810 #define HCLGE_NIC_CMQ_EN_B              16
 811 #define HCLGE_NIC_CMQ_ENABLE            BIT(HCLGE_NIC_CMQ_EN_B)
 812 #define HCLGE_NIC_CMQ_DESC_NUM          1024
 813 #define HCLGE_NIC_CMQ_DESC_NUM_S        3
 814
 815 #define HCLGE_LED_LOCATE_STATE_S        0
 816 #define HCLGE_LED_LOCATE_STATE_M        GENMASK(1, 0)
 817
 818 struct hclge_set_led_state_cmd {
 819         u8 rsv1[3];
 820         u8 locate_led_config;
 821         u8 rsv2[20];
 822 };
 823
 824 int hclge_cmd_init(struct hclge_dev *hdev);
 825 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
 826 {
 827         writel(value, base + reg);
 828 }
 829
 830 #define hclge_write_dev(a, reg, value) \
 831         hclge_write_reg((a)->io_base, (reg), (value))
 832 #define hclge_read_dev(a, reg) \
 833         hclge_read_reg((a)->io_base, (reg))
 834
 835 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg)
 836 {
 837         u8 __iomem *reg_addr = READ_ONCE(base);
 838
 839         return readl(reg_addr + reg);
 840 }
 841
 842 #define HCLGE_SEND_SYNC(flag) \
 843         ((flag) & HCLGE_CMD_FLAG_NO_INTR)
 844
 845 struct hclge_hw;
 846 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num);
 847 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
 848                                 enum hclge_opcode_type opcode, bool is_read);
 849 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
 850
 851 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
 852                                struct hclge_promisc_param *param);
 853
 854 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
 855                                            struct hclge_desc *desc);
 856 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
 857                                           struct hclge_desc *desc);
 858
 859 void hclge_destroy_cmd_queue(struct hclge_hw *hw);
 860 int hclge_cmd_queue_init(struct hclge_dev *hdev);
 861 #endif