2 * Copyright (c) 2016-2017 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/acpi.h>
11 #include <linux/device.h>
12 #include <linux/etherdevice.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
21 #include "hclge_cmd.h"
22 #include "hclge_dcb.h"
23 #include "hclge_main.h"
24 #include "hclge_mdio.h"
28 #define HCLGE_NAME "hclge"
29 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
30 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
31 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
32 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
34 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
35 enum hclge_mta_dmac_sel_type mta_mac_sel
,
37 static int hclge_init_vlan_config(struct hclge_dev
*hdev
);
38 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
);
40 static struct hnae3_ae_algo ae_algo
;
42 static const struct pci_device_id ae_algo_pci_tbl
[] = {
43 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_GE
), 0},
44 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE
), 0},
45 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA
), 0},
46 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA_MACSEC
), 0},
47 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA
), 0},
48 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA_MACSEC
), 0},
49 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_100G_RDMA_MACSEC
), 0},
50 /* required last entry */
54 static const char hns3_nic_test_strs
[][ETH_GSTRING_LEN
] = {
56 "Serdes Loopback test",
60 static const struct hclge_comm_stats_str g_all_64bit_stats_string
[] = {
61 {"igu_rx_oversize_pkt",
62 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt
)},
63 {"igu_rx_undersize_pkt",
64 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt
)},
65 {"igu_rx_out_all_pkt",
66 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt
)},
68 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt
)},
70 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt
)},
72 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt
)},
73 {"egu_tx_out_all_pkt",
74 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt
)},
76 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt
)},
78 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt
)},
80 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt
)},
81 {"ssu_ppp_mac_key_num",
82 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num
)},
83 {"ssu_ppp_host_key_num",
84 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num
)},
85 {"ppp_ssu_mac_rlt_num",
86 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num
)},
87 {"ppp_ssu_host_rlt_num",
88 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num
)},
90 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num
)},
92 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num
)},
94 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num
)},
96 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num
)}
99 static const struct hclge_comm_stats_str g_all_32bit_stats_string
[] = {
101 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt
)},
102 {"igu_rx_no_eof_pkt",
103 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt
)},
104 {"igu_rx_no_sof_pkt",
105 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt
)},
107 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt
)},
108 {"ssu_full_drop_num",
109 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num
)},
110 {"ssu_part_drop_num",
111 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num
)},
113 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num
)},
115 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num
)},
117 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num
)},
119 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt
)},
121 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt
)},
123 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt
)},
124 {"qcn_fb_invaild_cnt",
125 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt
)},
126 {"rx_packet_tc0_in_cnt",
127 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt
)},
128 {"rx_packet_tc1_in_cnt",
129 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt
)},
130 {"rx_packet_tc2_in_cnt",
131 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt
)},
132 {"rx_packet_tc3_in_cnt",
133 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt
)},
134 {"rx_packet_tc4_in_cnt",
135 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt
)},
136 {"rx_packet_tc5_in_cnt",
137 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt
)},
138 {"rx_packet_tc6_in_cnt",
139 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt
)},
140 {"rx_packet_tc7_in_cnt",
141 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt
)},
142 {"rx_packet_tc0_out_cnt",
143 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt
)},
144 {"rx_packet_tc1_out_cnt",
145 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt
)},
146 {"rx_packet_tc2_out_cnt",
147 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt
)},
148 {"rx_packet_tc3_out_cnt",
149 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt
)},
150 {"rx_packet_tc4_out_cnt",
151 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt
)},
152 {"rx_packet_tc5_out_cnt",
153 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt
)},
154 {"rx_packet_tc6_out_cnt",
155 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt
)},
156 {"rx_packet_tc7_out_cnt",
157 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt
)},
158 {"tx_packet_tc0_in_cnt",
159 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt
)},
160 {"tx_packet_tc1_in_cnt",
161 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt
)},
162 {"tx_packet_tc2_in_cnt",
163 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt
)},
164 {"tx_packet_tc3_in_cnt",
165 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt
)},
166 {"tx_packet_tc4_in_cnt",
167 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt
)},
168 {"tx_packet_tc5_in_cnt",
169 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt
)},
170 {"tx_packet_tc6_in_cnt",
171 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt
)},
172 {"tx_packet_tc7_in_cnt",
173 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt
)},
174 {"tx_packet_tc0_out_cnt",
175 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt
)},
176 {"tx_packet_tc1_out_cnt",
177 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt
)},
178 {"tx_packet_tc2_out_cnt",
179 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt
)},
180 {"tx_packet_tc3_out_cnt",
181 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt
)},
182 {"tx_packet_tc4_out_cnt",
183 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt
)},
184 {"tx_packet_tc5_out_cnt",
185 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt
)},
186 {"tx_packet_tc6_out_cnt",
187 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt
)},
188 {"tx_packet_tc7_out_cnt",
189 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt
)},
190 {"pkt_curr_buf_tc0_cnt",
191 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt
)},
192 {"pkt_curr_buf_tc1_cnt",
193 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt
)},
194 {"pkt_curr_buf_tc2_cnt",
195 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt
)},
196 {"pkt_curr_buf_tc3_cnt",
197 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt
)},
198 {"pkt_curr_buf_tc4_cnt",
199 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt
)},
200 {"pkt_curr_buf_tc5_cnt",
201 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt
)},
202 {"pkt_curr_buf_tc6_cnt",
203 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt
)},
204 {"pkt_curr_buf_tc7_cnt",
205 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt
)},
207 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num
)},
208 {"lo_pri_unicast_rlt_drop_num",
209 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num
)},
210 {"hi_pri_multicast_rlt_drop_num",
211 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num
)},
212 {"lo_pri_multicast_rlt_drop_num",
213 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num
)},
214 {"rx_oq_drop_pkt_cnt",
215 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt
)},
216 {"tx_oq_drop_pkt_cnt",
217 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt
)},
218 {"nic_l2_err_drop_pkt_cnt",
219 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt
)},
220 {"roc_l2_err_drop_pkt_cnt",
221 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt
)}
224 static const struct hclge_comm_stats_str g_mac_stats_string
[] = {
225 {"mac_tx_mac_pause_num",
226 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num
)},
227 {"mac_rx_mac_pause_num",
228 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num
)},
229 {"mac_tx_pfc_pri0_pkt_num",
230 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num
)},
231 {"mac_tx_pfc_pri1_pkt_num",
232 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num
)},
233 {"mac_tx_pfc_pri2_pkt_num",
234 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num
)},
235 {"mac_tx_pfc_pri3_pkt_num",
236 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num
)},
237 {"mac_tx_pfc_pri4_pkt_num",
238 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num
)},
239 {"mac_tx_pfc_pri5_pkt_num",
240 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num
)},
241 {"mac_tx_pfc_pri6_pkt_num",
242 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num
)},
243 {"mac_tx_pfc_pri7_pkt_num",
244 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num
)},
245 {"mac_rx_pfc_pri0_pkt_num",
246 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num
)},
247 {"mac_rx_pfc_pri1_pkt_num",
248 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num
)},
249 {"mac_rx_pfc_pri2_pkt_num",
250 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num
)},
251 {"mac_rx_pfc_pri3_pkt_num",
252 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num
)},
253 {"mac_rx_pfc_pri4_pkt_num",
254 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num
)},
255 {"mac_rx_pfc_pri5_pkt_num",
256 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num
)},
257 {"mac_rx_pfc_pri6_pkt_num",
258 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num
)},
259 {"mac_rx_pfc_pri7_pkt_num",
260 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num
)},
261 {"mac_tx_total_pkt_num",
262 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num
)},
263 {"mac_tx_total_oct_num",
264 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num
)},
265 {"mac_tx_good_pkt_num",
266 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num
)},
267 {"mac_tx_bad_pkt_num",
268 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num
)},
269 {"mac_tx_good_oct_num",
270 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num
)},
271 {"mac_tx_bad_oct_num",
272 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num
)},
273 {"mac_tx_uni_pkt_num",
274 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num
)},
275 {"mac_tx_multi_pkt_num",
276 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num
)},
277 {"mac_tx_broad_pkt_num",
278 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num
)},
279 {"mac_tx_undersize_pkt_num",
280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num
)},
281 {"mac_tx_overrsize_pkt_num",
282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_overrsize_pkt_num
)},
283 {"mac_tx_64_oct_pkt_num",
284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num
)},
285 {"mac_tx_65_127_oct_pkt_num",
286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num
)},
287 {"mac_tx_128_255_oct_pkt_num",
288 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num
)},
289 {"mac_tx_256_511_oct_pkt_num",
290 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num
)},
291 {"mac_tx_512_1023_oct_pkt_num",
292 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num
)},
293 {"mac_tx_1024_1518_oct_pkt_num",
294 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num
)},
295 {"mac_tx_1519_max_oct_pkt_num",
296 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_oct_pkt_num
)},
297 {"mac_rx_total_pkt_num",
298 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num
)},
299 {"mac_rx_total_oct_num",
300 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num
)},
301 {"mac_rx_good_pkt_num",
302 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num
)},
303 {"mac_rx_bad_pkt_num",
304 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num
)},
305 {"mac_rx_good_oct_num",
306 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num
)},
307 {"mac_rx_bad_oct_num",
308 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num
)},
309 {"mac_rx_uni_pkt_num",
310 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num
)},
311 {"mac_rx_multi_pkt_num",
312 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num
)},
313 {"mac_rx_broad_pkt_num",
314 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num
)},
315 {"mac_rx_undersize_pkt_num",
316 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num
)},
317 {"mac_rx_overrsize_pkt_num",
318 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_overrsize_pkt_num
)},
319 {"mac_rx_64_oct_pkt_num",
320 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num
)},
321 {"mac_rx_65_127_oct_pkt_num",
322 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num
)},
323 {"mac_rx_128_255_oct_pkt_num",
324 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num
)},
325 {"mac_rx_256_511_oct_pkt_num",
326 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num
)},
327 {"mac_rx_512_1023_oct_pkt_num",
328 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num
)},
329 {"mac_rx_1024_1518_oct_pkt_num",
330 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num
)},
331 {"mac_rx_1519_max_oct_pkt_num",
332 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_oct_pkt_num
)},
334 {"mac_trans_fragment_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_fragment_pkt_num
)},
336 {"mac_trans_undermin_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_undermin_pkt_num
)},
338 {"mac_trans_jabber_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_jabber_pkt_num
)},
340 {"mac_trans_err_all_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_err_all_pkt_num
)},
342 {"mac_trans_from_app_good_pkt_num",
343 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_good_pkt_num
)},
344 {"mac_trans_from_app_bad_pkt_num",
345 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_bad_pkt_num
)},
346 {"mac_rcv_fragment_pkt_num",
347 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fragment_pkt_num
)},
348 {"mac_rcv_undermin_pkt_num",
349 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_undermin_pkt_num
)},
350 {"mac_rcv_jabber_pkt_num",
351 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_jabber_pkt_num
)},
352 {"mac_rcv_fcs_err_pkt_num",
353 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fcs_err_pkt_num
)},
354 {"mac_rcv_send_app_good_pkt_num",
355 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_good_pkt_num
)},
356 {"mac_rcv_send_app_bad_pkt_num",
357 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_bad_pkt_num
)}
360 static int hclge_64_bit_update_stats(struct hclge_dev
*hdev
)
362 #define HCLGE_64_BIT_CMD_NUM 5
363 #define HCLGE_64_BIT_RTN_DATANUM 4
364 u64
*data
= (u64
*)(&hdev
->hw_stats
.all_64_bit_stats
);
365 struct hclge_desc desc
[HCLGE_64_BIT_CMD_NUM
];
370 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_64_BIT
, true);
371 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_64_BIT_CMD_NUM
);
373 dev_err(&hdev
->pdev
->dev
,
374 "Get 64 bit pkt stats fail, status = %d.\n", ret
);
378 for (i
= 0; i
< HCLGE_64_BIT_CMD_NUM
; i
++) {
379 if (unlikely(i
== 0)) {
380 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
381 n
= HCLGE_64_BIT_RTN_DATANUM
- 1;
383 desc_data
= (__le64
*)(&desc
[i
]);
384 n
= HCLGE_64_BIT_RTN_DATANUM
;
386 for (k
= 0; k
< n
; k
++) {
387 *data
++ += le64_to_cpu(*desc_data
);
395 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats
*stats
)
397 stats
->pkt_curr_buf_cnt
= 0;
398 stats
->pkt_curr_buf_tc0_cnt
= 0;
399 stats
->pkt_curr_buf_tc1_cnt
= 0;
400 stats
->pkt_curr_buf_tc2_cnt
= 0;
401 stats
->pkt_curr_buf_tc3_cnt
= 0;
402 stats
->pkt_curr_buf_tc4_cnt
= 0;
403 stats
->pkt_curr_buf_tc5_cnt
= 0;
404 stats
->pkt_curr_buf_tc6_cnt
= 0;
405 stats
->pkt_curr_buf_tc7_cnt
= 0;
408 static int hclge_32_bit_update_stats(struct hclge_dev
*hdev
)
410 #define HCLGE_32_BIT_CMD_NUM 8
411 #define HCLGE_32_BIT_RTN_DATANUM 8
413 struct hclge_desc desc
[HCLGE_32_BIT_CMD_NUM
];
414 struct hclge_32_bit_stats
*all_32_bit_stats
;
420 all_32_bit_stats
= &hdev
->hw_stats
.all_32_bit_stats
;
421 data
= (u64
*)(&all_32_bit_stats
->egu_tx_1588_pkt
);
423 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_32_BIT
, true);
424 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_32_BIT_CMD_NUM
);
426 dev_err(&hdev
->pdev
->dev
,
427 "Get 32 bit pkt stats fail, status = %d.\n", ret
);
432 hclge_reset_partial_32bit_counter(all_32_bit_stats
);
433 for (i
= 0; i
< HCLGE_32_BIT_CMD_NUM
; i
++) {
434 if (unlikely(i
== 0)) {
435 __le16
*desc_data_16bit
;
437 all_32_bit_stats
->igu_rx_err_pkt
+=
438 le32_to_cpu(desc
[i
].data
[0]);
440 desc_data_16bit
= (__le16
*)&desc
[i
].data
[1];
441 all_32_bit_stats
->igu_rx_no_eof_pkt
+=
442 le16_to_cpu(*desc_data_16bit
);
445 all_32_bit_stats
->igu_rx_no_sof_pkt
+=
446 le16_to_cpu(*desc_data_16bit
);
448 desc_data
= &desc
[i
].data
[2];
449 n
= HCLGE_32_BIT_RTN_DATANUM
- 4;
451 desc_data
= (__le32
*)&desc
[i
];
452 n
= HCLGE_32_BIT_RTN_DATANUM
;
454 for (k
= 0; k
< n
; k
++) {
455 *data
++ += le32_to_cpu(*desc_data
);
463 static int hclge_mac_update_stats(struct hclge_dev
*hdev
)
465 #define HCLGE_MAC_CMD_NUM 17
466 #define HCLGE_RTN_DATA_NUM 4
468 u64
*data
= (u64
*)(&hdev
->hw_stats
.mac_stats
);
469 struct hclge_desc desc
[HCLGE_MAC_CMD_NUM
];
474 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_MAC
, true);
475 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_MAC_CMD_NUM
);
477 dev_err(&hdev
->pdev
->dev
,
478 "Get MAC pkt stats fail, status = %d.\n", ret
);
483 for (i
= 0; i
< HCLGE_MAC_CMD_NUM
; i
++) {
484 if (unlikely(i
== 0)) {
485 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
486 n
= HCLGE_RTN_DATA_NUM
- 2;
488 desc_data
= (__le64
*)(&desc
[i
]);
489 n
= HCLGE_RTN_DATA_NUM
;
491 for (k
= 0; k
< n
; k
++) {
492 *data
++ += le64_to_cpu(*desc_data
);
500 static int hclge_tqps_update_stats(struct hnae3_handle
*handle
)
502 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
503 struct hclge_vport
*vport
= hclge_get_vport(handle
);
504 struct hclge_dev
*hdev
= vport
->back
;
505 struct hnae3_queue
*queue
;
506 struct hclge_desc desc
[1];
507 struct hclge_tqp
*tqp
;
510 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
511 queue
= handle
->kinfo
.tqp
[i
];
512 tqp
= container_of(queue
, struct hclge_tqp
, q
);
513 /* command : HCLGE_OPC_QUERY_IGU_STAT */
514 hclge_cmd_setup_basic_desc(&desc
[0],
515 HCLGE_OPC_QUERY_RX_STATUS
,
518 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
519 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
521 dev_err(&hdev
->pdev
->dev
,
522 "Query tqp stat fail, status = %d,queue = %d\n",
526 tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
+=
527 le32_to_cpu(desc
[0].data
[4]);
530 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
531 queue
= handle
->kinfo
.tqp
[i
];
532 tqp
= container_of(queue
, struct hclge_tqp
, q
);
533 /* command : HCLGE_OPC_QUERY_IGU_STAT */
534 hclge_cmd_setup_basic_desc(&desc
[0],
535 HCLGE_OPC_QUERY_TX_STATUS
,
538 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
539 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
541 dev_err(&hdev
->pdev
->dev
,
542 "Query tqp stat fail, status = %d,queue = %d\n",
546 tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
+=
547 le32_to_cpu(desc
[0].data
[4]);
553 static u64
*hclge_tqps_get_stats(struct hnae3_handle
*handle
, u64
*data
)
555 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
556 struct hclge_tqp
*tqp
;
560 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
561 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
562 *buff
++ = tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
;
565 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
566 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
567 *buff
++ = tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
;
573 static int hclge_tqps_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
575 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
577 return kinfo
->num_tqps
* (2);
580 static u8
*hclge_tqps_get_strings(struct hnae3_handle
*handle
, u8
*data
)
582 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
586 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
587 struct hclge_tqp
*tqp
= container_of(handle
->kinfo
.tqp
[i
],
588 struct hclge_tqp
, q
);
589 snprintf(buff
, ETH_GSTRING_LEN
, "rcb_q%d_tx_pktnum_rcd",
591 buff
= buff
+ ETH_GSTRING_LEN
;
594 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
595 struct hclge_tqp
*tqp
= container_of(kinfo
->tqp
[i
],
596 struct hclge_tqp
, q
);
597 snprintf(buff
, ETH_GSTRING_LEN
, "rcb_q%d_rx_pktnum_rcd",
599 buff
= buff
+ ETH_GSTRING_LEN
;
605 static u64
*hclge_comm_get_stats(void *comm_stats
,
606 const struct hclge_comm_stats_str strs
[],
612 for (i
= 0; i
< size
; i
++)
613 buf
[i
] = HCLGE_STATS_READ(comm_stats
, strs
[i
].offset
);
618 static u8
*hclge_comm_get_strings(u32 stringset
,
619 const struct hclge_comm_stats_str strs
[],
622 char *buff
= (char *)data
;
625 if (stringset
!= ETH_SS_STATS
)
628 for (i
= 0; i
< size
; i
++) {
629 snprintf(buff
, ETH_GSTRING_LEN
,
631 buff
= buff
+ ETH_GSTRING_LEN
;
637 static void hclge_update_netstat(struct hclge_hw_stats
*hw_stats
,
638 struct net_device_stats
*net_stats
)
640 net_stats
->tx_dropped
= 0;
641 net_stats
->rx_dropped
= hw_stats
->all_32_bit_stats
.ssu_full_drop_num
;
642 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ppp_key_drop_num
;
643 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ssu_key_drop_num
;
645 net_stats
->rx_errors
= hw_stats
->mac_stats
.mac_rx_overrsize_pkt_num
;
646 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
647 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_err_pkt
;
648 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_eof_pkt
;
649 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_sof_pkt
;
650 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rcv_fcs_err_pkt_num
;
652 net_stats
->multicast
= hw_stats
->mac_stats
.mac_tx_multi_pkt_num
;
653 net_stats
->multicast
+= hw_stats
->mac_stats
.mac_rx_multi_pkt_num
;
655 net_stats
->rx_crc_errors
= hw_stats
->mac_stats
.mac_rcv_fcs_err_pkt_num
;
656 net_stats
->rx_length_errors
=
657 hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
658 net_stats
->rx_length_errors
+=
659 hw_stats
->mac_stats
.mac_rx_overrsize_pkt_num
;
660 net_stats
->rx_over_errors
=
661 hw_stats
->mac_stats
.mac_rx_overrsize_pkt_num
;
664 static void hclge_update_stats_for_all(struct hclge_dev
*hdev
)
666 struct hnae3_handle
*handle
;
669 handle
= &hdev
->vport
[0].nic
;
670 if (handle
->client
) {
671 status
= hclge_tqps_update_stats(handle
);
673 dev_err(&hdev
->pdev
->dev
,
674 "Update TQPS stats fail, status = %d.\n",
679 status
= hclge_mac_update_stats(hdev
);
681 dev_err(&hdev
->pdev
->dev
,
682 "Update MAC stats fail, status = %d.\n", status
);
684 status
= hclge_32_bit_update_stats(hdev
);
686 dev_err(&hdev
->pdev
->dev
,
687 "Update 32 bit stats fail, status = %d.\n",
690 hclge_update_netstat(&hdev
->hw_stats
, &handle
->kinfo
.netdev
->stats
);
693 static void hclge_update_stats(struct hnae3_handle
*handle
,
694 struct net_device_stats
*net_stats
)
696 struct hclge_vport
*vport
= hclge_get_vport(handle
);
697 struct hclge_dev
*hdev
= vport
->back
;
698 struct hclge_hw_stats
*hw_stats
= &hdev
->hw_stats
;
701 status
= hclge_mac_update_stats(hdev
);
703 dev_err(&hdev
->pdev
->dev
,
704 "Update MAC stats fail, status = %d.\n",
707 status
= hclge_32_bit_update_stats(hdev
);
709 dev_err(&hdev
->pdev
->dev
,
710 "Update 32 bit stats fail, status = %d.\n",
713 status
= hclge_64_bit_update_stats(hdev
);
715 dev_err(&hdev
->pdev
->dev
,
716 "Update 64 bit stats fail, status = %d.\n",
719 status
= hclge_tqps_update_stats(handle
);
721 dev_err(&hdev
->pdev
->dev
,
722 "Update TQPS stats fail, status = %d.\n",
725 hclge_update_netstat(hw_stats
, net_stats
);
728 static int hclge_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
730 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
732 struct hclge_vport
*vport
= hclge_get_vport(handle
);
733 struct hclge_dev
*hdev
= vport
->back
;
736 /* Loopback test support rules:
737 * mac: only GE mode support
738 * serdes: all mac mode will support include GE/XGE/LGE/CGE
739 * phy: only support when phy device exist on board
741 if (stringset
== ETH_SS_TEST
) {
742 /* clear loopback bit flags at first */
743 handle
->flags
= (handle
->flags
& (~HCLGE_LOOPBACK_TEST_FLAGS
));
744 if (hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_10M
||
745 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_100M
||
746 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_1G
) {
748 handle
->flags
|= HNAE3_SUPPORT_MAC_LOOPBACK
;
752 } else if (stringset
== ETH_SS_STATS
) {
753 count
= ARRAY_SIZE(g_mac_stats_string
) +
754 ARRAY_SIZE(g_all_32bit_stats_string
) +
755 ARRAY_SIZE(g_all_64bit_stats_string
) +
756 hclge_tqps_get_sset_count(handle
, stringset
);
762 static void hclge_get_strings(struct hnae3_handle
*handle
,
766 u8
*p
= (char *)data
;
769 if (stringset
== ETH_SS_STATS
) {
770 size
= ARRAY_SIZE(g_mac_stats_string
);
771 p
= hclge_comm_get_strings(stringset
,
775 size
= ARRAY_SIZE(g_all_32bit_stats_string
);
776 p
= hclge_comm_get_strings(stringset
,
777 g_all_32bit_stats_string
,
780 size
= ARRAY_SIZE(g_all_64bit_stats_string
);
781 p
= hclge_comm_get_strings(stringset
,
782 g_all_64bit_stats_string
,
785 p
= hclge_tqps_get_strings(handle
, p
);
786 } else if (stringset
== ETH_SS_TEST
) {
787 if (handle
->flags
& HNAE3_SUPPORT_MAC_LOOPBACK
) {
789 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_MAC
],
791 p
+= ETH_GSTRING_LEN
;
793 if (handle
->flags
& HNAE3_SUPPORT_SERDES_LOOPBACK
) {
795 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_SERDES
],
797 p
+= ETH_GSTRING_LEN
;
799 if (handle
->flags
& HNAE3_SUPPORT_PHY_LOOPBACK
) {
801 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_PHY
],
803 p
+= ETH_GSTRING_LEN
;
808 static void hclge_get_stats(struct hnae3_handle
*handle
, u64
*data
)
810 struct hclge_vport
*vport
= hclge_get_vport(handle
);
811 struct hclge_dev
*hdev
= vport
->back
;
814 p
= hclge_comm_get_stats(&hdev
->hw_stats
.mac_stats
,
816 ARRAY_SIZE(g_mac_stats_string
),
818 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_32_bit_stats
,
819 g_all_32bit_stats_string
,
820 ARRAY_SIZE(g_all_32bit_stats_string
),
822 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_64_bit_stats
,
823 g_all_64bit_stats_string
,
824 ARRAY_SIZE(g_all_64bit_stats_string
),
826 p
= hclge_tqps_get_stats(handle
, p
);
829 static int hclge_parse_func_status(struct hclge_dev
*hdev
,
830 struct hclge_func_status_cmd
*status
)
832 if (!(status
->pf_state
& HCLGE_PF_STATE_DONE
))
835 /* Set the pf to main pf */
836 if (status
->pf_state
& HCLGE_PF_STATE_MAIN
)
837 hdev
->flag
|= HCLGE_FLAG_MAIN
;
839 hdev
->flag
&= ~HCLGE_FLAG_MAIN
;
844 static int hclge_query_function_status(struct hclge_dev
*hdev
)
846 struct hclge_func_status_cmd
*req
;
847 struct hclge_desc desc
;
851 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_FUNC_STATUS
, true);
852 req
= (struct hclge_func_status_cmd
*)desc
.data
;
855 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
857 dev_err(&hdev
->pdev
->dev
,
858 "query function status failed %d.\n",
864 /* Check pf reset is done */
867 usleep_range(1000, 2000);
868 } while (timeout
++ < 5);
870 ret
= hclge_parse_func_status(hdev
, req
);
875 static int hclge_query_pf_resource(struct hclge_dev
*hdev
)
877 struct hclge_pf_res_cmd
*req
;
878 struct hclge_desc desc
;
881 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_PF_RSRC
, true);
882 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
884 dev_err(&hdev
->pdev
->dev
,
885 "query pf resource failed %d.\n", ret
);
889 req
= (struct hclge_pf_res_cmd
*)desc
.data
;
890 hdev
->num_tqps
= __le16_to_cpu(req
->tqp_num
);
891 hdev
->pkt_buf_size
= __le16_to_cpu(req
->buf_size
) << HCLGE_BUF_UNIT_S
;
893 if (hnae3_dev_roce_supported(hdev
)) {
895 hnae_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
896 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
898 /* PF should have NIC vectors and Roce vectors,
899 * NIC vectors are queued before Roce vectors.
901 hdev
->num_msi
= hdev
->num_roce_msi
+ HCLGE_ROCE_VECTOR_OFFSET
;
904 hnae_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
905 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
911 static int hclge_parse_speed(int speed_cmd
, int *speed
)
915 *speed
= HCLGE_MAC_SPEED_10M
;
918 *speed
= HCLGE_MAC_SPEED_100M
;
921 *speed
= HCLGE_MAC_SPEED_1G
;
924 *speed
= HCLGE_MAC_SPEED_10G
;
927 *speed
= HCLGE_MAC_SPEED_25G
;
930 *speed
= HCLGE_MAC_SPEED_40G
;
933 *speed
= HCLGE_MAC_SPEED_50G
;
936 *speed
= HCLGE_MAC_SPEED_100G
;
945 static void hclge_parse_cfg(struct hclge_cfg
*cfg
, struct hclge_desc
*desc
)
947 struct hclge_cfg_param_cmd
*req
;
948 u64 mac_addr_tmp_high
;
952 req
= (struct hclge_cfg_param_cmd
*)desc
[0].data
;
954 /* get the configuration */
955 cfg
->vmdq_vport_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
958 cfg
->tc_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
959 HCLGE_CFG_TC_NUM_M
, HCLGE_CFG_TC_NUM_S
);
960 cfg
->tqp_desc_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
961 HCLGE_CFG_TQP_DESC_N_M
,
962 HCLGE_CFG_TQP_DESC_N_S
);
964 cfg
->phy_addr
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
965 HCLGE_CFG_PHY_ADDR_M
,
966 HCLGE_CFG_PHY_ADDR_S
);
967 cfg
->media_type
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
968 HCLGE_CFG_MEDIA_TP_M
,
969 HCLGE_CFG_MEDIA_TP_S
);
970 cfg
->rx_buf_len
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
971 HCLGE_CFG_RX_BUF_LEN_M
,
972 HCLGE_CFG_RX_BUF_LEN_S
);
973 /* get mac_address */
974 mac_addr_tmp
= __le32_to_cpu(req
->param
[2]);
975 mac_addr_tmp_high
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
976 HCLGE_CFG_MAC_ADDR_H_M
,
977 HCLGE_CFG_MAC_ADDR_H_S
);
979 mac_addr_tmp
|= (mac_addr_tmp_high
<< 31) << 1;
981 cfg
->default_speed
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
982 HCLGE_CFG_DEFAULT_SPEED_M
,
983 HCLGE_CFG_DEFAULT_SPEED_S
);
984 for (i
= 0; i
< ETH_ALEN
; i
++)
985 cfg
->mac_addr
[i
] = (mac_addr_tmp
>> (8 * i
)) & 0xff;
987 req
= (struct hclge_cfg_param_cmd
*)desc
[1].data
;
988 cfg
->numa_node_map
= __le32_to_cpu(req
->param
[0]);
991 /* hclge_get_cfg: query the static parameter from flash
992 * @hdev: pointer to struct hclge_dev
993 * @hcfg: the config structure to be getted
995 static int hclge_get_cfg(struct hclge_dev
*hdev
, struct hclge_cfg
*hcfg
)
997 struct hclge_desc desc
[HCLGE_PF_CFG_DESC_NUM
];
998 struct hclge_cfg_param_cmd
*req
;
1001 for (i
= 0; i
< HCLGE_PF_CFG_DESC_NUM
; i
++) {
1004 req
= (struct hclge_cfg_param_cmd
*)desc
[i
].data
;
1005 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_GET_CFG_PARAM
,
1007 hnae_set_field(offset
, HCLGE_CFG_OFFSET_M
,
1008 HCLGE_CFG_OFFSET_S
, i
* HCLGE_CFG_RD_LEN_BYTES
);
1009 /* Len should be united by 4 bytes when send to hardware */
1010 hnae_set_field(offset
, HCLGE_CFG_RD_LEN_M
, HCLGE_CFG_RD_LEN_S
,
1011 HCLGE_CFG_RD_LEN_BYTES
/ HCLGE_CFG_RD_LEN_UNIT
);
1012 req
->offset
= cpu_to_le32(offset
);
1015 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_PF_CFG_DESC_NUM
);
1017 dev_err(&hdev
->pdev
->dev
,
1018 "get config failed %d.\n", ret
);
1022 hclge_parse_cfg(hcfg
, desc
);
1026 static int hclge_get_cap(struct hclge_dev
*hdev
)
1030 ret
= hclge_query_function_status(hdev
);
1032 dev_err(&hdev
->pdev
->dev
,
1033 "query function status error %d.\n", ret
);
1037 /* get pf resource */
1038 ret
= hclge_query_pf_resource(hdev
);
1040 dev_err(&hdev
->pdev
->dev
,
1041 "query pf resource error %d.\n", ret
);
1048 static int hclge_configure(struct hclge_dev
*hdev
)
1050 struct hclge_cfg cfg
;
1053 ret
= hclge_get_cfg(hdev
, &cfg
);
1055 dev_err(&hdev
->pdev
->dev
, "get mac mode error %d.\n", ret
);
1059 hdev
->num_vmdq_vport
= cfg
.vmdq_vport_num
;
1060 hdev
->base_tqp_pid
= 0;
1061 hdev
->rss_size_max
= 1;
1062 hdev
->rx_buf_len
= cfg
.rx_buf_len
;
1063 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, cfg
.mac_addr
);
1064 hdev
->hw
.mac
.media_type
= cfg
.media_type
;
1065 hdev
->hw
.mac
.phy_addr
= cfg
.phy_addr
;
1066 hdev
->num_desc
= cfg
.tqp_desc_num
;
1067 hdev
->tm_info
.num_pg
= 1;
1068 hdev
->tc_max
= cfg
.tc_num
;
1069 hdev
->tm_info
.hw_pfc_map
= 0;
1071 ret
= hclge_parse_speed(cfg
.default_speed
, &hdev
->hw
.mac
.speed
);
1073 dev_err(&hdev
->pdev
->dev
, "Get wrong speed ret=%d.\n", ret
);
1077 if ((hdev
->tc_max
> HNAE3_MAX_TC
) ||
1078 (hdev
->tc_max
< 1)) {
1079 dev_warn(&hdev
->pdev
->dev
, "TC num = %d.\n",
1084 /* Dev does not support DCB */
1085 if (!hnae3_dev_dcb_supported(hdev
)) {
1089 hdev
->pfc_max
= hdev
->tc_max
;
1092 hdev
->tm_info
.num_tc
= hdev
->tc_max
;
1094 /* Currently not support uncontiuous tc */
1095 for (i
= 0; i
< hdev
->tm_info
.num_tc
; i
++)
1096 hnae_set_bit(hdev
->hw_tc_map
, i
, 1);
1098 if (!hdev
->num_vmdq_vport
&& !hdev
->num_req_vfs
)
1099 hdev
->tx_sch_mode
= HCLGE_FLAG_TC_BASE_SCH_MODE
;
1101 hdev
->tx_sch_mode
= HCLGE_FLAG_VNET_BASE_SCH_MODE
;
1106 static int hclge_config_tso(struct hclge_dev
*hdev
, int tso_mss_min
,
1109 struct hclge_cfg_tso_status_cmd
*req
;
1110 struct hclge_desc desc
;
1113 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TSO_GENERIC_CONFIG
, false);
1115 req
= (struct hclge_cfg_tso_status_cmd
*)desc
.data
;
1118 hnae_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1119 HCLGE_TSO_MSS_MIN_S
, tso_mss_min
);
1120 req
->tso_mss_min
= cpu_to_le16(tso_mss
);
1123 hnae_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1124 HCLGE_TSO_MSS_MIN_S
, tso_mss_max
);
1125 req
->tso_mss_max
= cpu_to_le16(tso_mss
);
1127 return hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1130 static int hclge_alloc_tqps(struct hclge_dev
*hdev
)
1132 struct hclge_tqp
*tqp
;
1135 hdev
->htqp
= devm_kcalloc(&hdev
->pdev
->dev
, hdev
->num_tqps
,
1136 sizeof(struct hclge_tqp
), GFP_KERNEL
);
1142 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
1143 tqp
->dev
= &hdev
->pdev
->dev
;
1146 tqp
->q
.ae_algo
= &ae_algo
;
1147 tqp
->q
.buf_size
= hdev
->rx_buf_len
;
1148 tqp
->q
.desc_num
= hdev
->num_desc
;
1149 tqp
->q
.io_base
= hdev
->hw
.io_base
+ HCLGE_TQP_REG_OFFSET
+
1150 i
* HCLGE_TQP_REG_SIZE
;
1158 static int hclge_map_tqps_to_func(struct hclge_dev
*hdev
, u16 func_id
,
1159 u16 tqp_pid
, u16 tqp_vid
, bool is_pf
)
1161 struct hclge_tqp_map_cmd
*req
;
1162 struct hclge_desc desc
;
1165 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SET_TQP_MAP
, false);
1167 req
= (struct hclge_tqp_map_cmd
*)desc
.data
;
1168 req
->tqp_id
= cpu_to_le16(tqp_pid
);
1169 req
->tqp_vf
= func_id
;
1170 req
->tqp_flag
= !is_pf
<< HCLGE_TQP_MAP_TYPE_B
|
1171 1 << HCLGE_TQP_MAP_EN_B
;
1172 req
->tqp_vid
= cpu_to_le16(tqp_vid
);
1174 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1176 dev_err(&hdev
->pdev
->dev
, "TQP map failed %d.\n",
1184 static int hclge_assign_tqp(struct hclge_vport
*vport
,
1185 struct hnae3_queue
**tqp
, u16 num_tqps
)
1187 struct hclge_dev
*hdev
= vport
->back
;
1190 for (i
= 0, alloced
= 0; i
< hdev
->num_tqps
&&
1191 alloced
< num_tqps
; i
++) {
1192 if (!hdev
->htqp
[i
].alloced
) {
1193 hdev
->htqp
[i
].q
.handle
= &vport
->nic
;
1194 hdev
->htqp
[i
].q
.tqp_index
= alloced
;
1195 tqp
[alloced
] = &hdev
->htqp
[i
].q
;
1196 hdev
->htqp
[i
].alloced
= true;
1200 vport
->alloc_tqps
= num_tqps
;
1205 static int hclge_knic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1207 struct hnae3_handle
*nic
= &vport
->nic
;
1208 struct hnae3_knic_private_info
*kinfo
= &nic
->kinfo
;
1209 struct hclge_dev
*hdev
= vport
->back
;
1212 kinfo
->num_desc
= hdev
->num_desc
;
1213 kinfo
->rx_buf_len
= hdev
->rx_buf_len
;
1214 kinfo
->num_tc
= min_t(u16
, num_tqps
, hdev
->tm_info
.num_tc
);
1216 = min_t(u16
, hdev
->rss_size_max
, num_tqps
/ kinfo
->num_tc
);
1217 kinfo
->num_tqps
= kinfo
->rss_size
* kinfo
->num_tc
;
1219 for (i
= 0; i
< HNAE3_MAX_TC
; i
++) {
1220 if (hdev
->hw_tc_map
& BIT(i
)) {
1221 kinfo
->tc_info
[i
].enable
= true;
1222 kinfo
->tc_info
[i
].tqp_offset
= i
* kinfo
->rss_size
;
1223 kinfo
->tc_info
[i
].tqp_count
= kinfo
->rss_size
;
1224 kinfo
->tc_info
[i
].tc
= i
;
1226 /* Set to default queue if TC is disable */
1227 kinfo
->tc_info
[i
].enable
= false;
1228 kinfo
->tc_info
[i
].tqp_offset
= 0;
1229 kinfo
->tc_info
[i
].tqp_count
= 1;
1230 kinfo
->tc_info
[i
].tc
= 0;
1234 kinfo
->tqp
= devm_kcalloc(&hdev
->pdev
->dev
, kinfo
->num_tqps
,
1235 sizeof(struct hnae3_queue
*), GFP_KERNEL
);
1239 ret
= hclge_assign_tqp(vport
, kinfo
->tqp
, kinfo
->num_tqps
);
1241 dev_err(&hdev
->pdev
->dev
, "fail to assign TQPs %d.\n", ret
);
1248 static int hclge_map_tqp_to_vport(struct hclge_dev
*hdev
,
1249 struct hclge_vport
*vport
)
1251 struct hnae3_handle
*nic
= &vport
->nic
;
1252 struct hnae3_knic_private_info
*kinfo
;
1255 kinfo
= &nic
->kinfo
;
1256 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
1257 struct hclge_tqp
*q
=
1258 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
1262 is_pf
= !(vport
->vport_id
);
1263 ret
= hclge_map_tqps_to_func(hdev
, vport
->vport_id
, q
->index
,
1272 static int hclge_map_tqp(struct hclge_dev
*hdev
)
1274 struct hclge_vport
*vport
= hdev
->vport
;
1277 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1278 for (i
= 0; i
< num_vport
; i
++) {
1281 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
1291 static void hclge_unic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1293 /* this would be initialized later */
1296 static int hclge_vport_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1298 struct hnae3_handle
*nic
= &vport
->nic
;
1299 struct hclge_dev
*hdev
= vport
->back
;
1302 nic
->pdev
= hdev
->pdev
;
1303 nic
->ae_algo
= &ae_algo
;
1304 nic
->numa_node_mask
= hdev
->numa_node_mask
;
1306 if (hdev
->ae_dev
->dev_type
== HNAE3_DEV_KNIC
) {
1307 ret
= hclge_knic_setup(vport
, num_tqps
);
1309 dev_err(&hdev
->pdev
->dev
, "knic setup failed %d\n",
1314 hclge_unic_setup(vport
, num_tqps
);
1320 static int hclge_alloc_vport(struct hclge_dev
*hdev
)
1322 struct pci_dev
*pdev
= hdev
->pdev
;
1323 struct hclge_vport
*vport
;
1329 /* We need to alloc a vport for main NIC of PF */
1330 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1332 if (hdev
->num_tqps
< num_vport
)
1333 num_vport
= hdev
->num_tqps
;
1335 /* Alloc the same number of TQPs for every vport */
1336 tqp_per_vport
= hdev
->num_tqps
/ num_vport
;
1337 tqp_main_vport
= tqp_per_vport
+ hdev
->num_tqps
% num_vport
;
1339 vport
= devm_kcalloc(&pdev
->dev
, num_vport
, sizeof(struct hclge_vport
),
1344 hdev
->vport
= vport
;
1345 hdev
->num_alloc_vport
= num_vport
;
1347 #ifdef CONFIG_PCI_IOV
1349 if (hdev
->num_req_vfs
) {
1350 dev_info(&pdev
->dev
, "active VFs(%d) found, enabling SRIOV\n",
1352 ret
= pci_enable_sriov(hdev
->pdev
, hdev
->num_req_vfs
);
1354 hdev
->num_alloc_vfs
= 0;
1355 dev_err(&pdev
->dev
, "SRIOV enable failed %d\n",
1360 hdev
->num_alloc_vfs
= hdev
->num_req_vfs
;
1363 for (i
= 0; i
< num_vport
; i
++) {
1365 vport
->vport_id
= i
;
1368 ret
= hclge_vport_setup(vport
, tqp_main_vport
);
1370 ret
= hclge_vport_setup(vport
, tqp_per_vport
);
1373 "vport setup failed for vport %d, %d\n",
1384 static int hclge_cmd_alloc_tx_buff(struct hclge_dev
*hdev
,
1385 struct hclge_pkt_buf_alloc
*buf_alloc
)
1387 /* TX buffer size is unit by 128 byte */
1388 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1389 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1390 struct hclge_tx_buff_alloc_cmd
*req
;
1391 struct hclge_desc desc
;
1395 req
= (struct hclge_tx_buff_alloc_cmd
*)desc
.data
;
1397 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TX_BUFF_ALLOC
, 0);
1398 for (i
= 0; i
< HCLGE_TC_NUM
; i
++) {
1399 u32 buf_size
= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1401 req
->tx_pkt_buff
[i
] =
1402 cpu_to_le16((buf_size
>> HCLGE_BUF_SIZE_UNIT_SHIFT
) |
1403 HCLGE_BUF_SIZE_UPDATE_EN_MSK
);
1406 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1408 dev_err(&hdev
->pdev
->dev
, "tx buffer alloc cmd failed %d.\n",
1416 static int hclge_tx_buffer_alloc(struct hclge_dev
*hdev
,
1417 struct hclge_pkt_buf_alloc
*buf_alloc
)
1419 int ret
= hclge_cmd_alloc_tx_buff(hdev
, buf_alloc
);
1422 dev_err(&hdev
->pdev
->dev
,
1423 "tx buffer alloc failed %d\n", ret
);
1430 static int hclge_get_tc_num(struct hclge_dev
*hdev
)
1434 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1435 if (hdev
->hw_tc_map
& BIT(i
))
1440 static int hclge_get_pfc_enalbe_num(struct hclge_dev
*hdev
)
1444 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1445 if (hdev
->hw_tc_map
& BIT(i
) &&
1446 hdev
->tm_info
.hw_pfc_map
& BIT(i
))
1451 /* Get the number of pfc enabled TCs, which have private buffer */
1452 static int hclge_get_pfc_priv_num(struct hclge_dev
*hdev
,
1453 struct hclge_pkt_buf_alloc
*buf_alloc
)
1455 struct hclge_priv_buf
*priv
;
1458 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1459 priv
= &buf_alloc
->priv_buf
[i
];
1460 if ((hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1468 /* Get the number of pfc disabled TCs, which have private buffer */
1469 static int hclge_get_no_pfc_priv_num(struct hclge_dev
*hdev
,
1470 struct hclge_pkt_buf_alloc
*buf_alloc
)
1472 struct hclge_priv_buf
*priv
;
1475 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1476 priv
= &buf_alloc
->priv_buf
[i
];
1477 if (hdev
->hw_tc_map
& BIT(i
) &&
1478 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1486 static u32
hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1488 struct hclge_priv_buf
*priv
;
1492 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1493 priv
= &buf_alloc
->priv_buf
[i
];
1495 rx_priv
+= priv
->buf_size
;
1500 static u32
hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1502 u32 i
, total_tx_size
= 0;
1504 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1505 total_tx_size
+= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1507 return total_tx_size
;
1510 static bool hclge_is_rx_buf_ok(struct hclge_dev
*hdev
,
1511 struct hclge_pkt_buf_alloc
*buf_alloc
,
1514 u32 shared_buf_min
, shared_buf_tc
, shared_std
;
1515 int tc_num
, pfc_enable_num
;
1520 tc_num
= hclge_get_tc_num(hdev
);
1521 pfc_enable_num
= hclge_get_pfc_enalbe_num(hdev
);
1523 if (hnae3_dev_dcb_supported(hdev
))
1524 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_DV
;
1526 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_NON_DCB_DV
;
1528 shared_buf_tc
= pfc_enable_num
* hdev
->mps
+
1529 (tc_num
- pfc_enable_num
) * hdev
->mps
/ 2 +
1531 shared_std
= max_t(u32
, shared_buf_min
, shared_buf_tc
);
1533 rx_priv
= hclge_get_rx_priv_buff_alloced(buf_alloc
);
1534 if (rx_all
<= rx_priv
+ shared_std
)
1537 shared_buf
= rx_all
- rx_priv
;
1538 buf_alloc
->s_buf
.buf_size
= shared_buf
;
1539 buf_alloc
->s_buf
.self
.high
= shared_buf
;
1540 buf_alloc
->s_buf
.self
.low
= 2 * hdev
->mps
;
1542 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1543 if ((hdev
->hw_tc_map
& BIT(i
)) &&
1544 (hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1545 buf_alloc
->s_buf
.tc_thrd
[i
].low
= hdev
->mps
;
1546 buf_alloc
->s_buf
.tc_thrd
[i
].high
= 2 * hdev
->mps
;
1548 buf_alloc
->s_buf
.tc_thrd
[i
].low
= 0;
1549 buf_alloc
->s_buf
.tc_thrd
[i
].high
= hdev
->mps
;
1556 static int hclge_tx_buffer_calc(struct hclge_dev
*hdev
,
1557 struct hclge_pkt_buf_alloc
*buf_alloc
)
1561 total_size
= hdev
->pkt_buf_size
;
1563 /* alloc tx buffer for all enabled tc */
1564 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1565 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1567 if (total_size
< HCLGE_DEFAULT_TX_BUF
)
1570 if (hdev
->hw_tc_map
& BIT(i
))
1571 priv
->tx_buf_size
= HCLGE_DEFAULT_TX_BUF
;
1573 priv
->tx_buf_size
= 0;
1575 total_size
-= priv
->tx_buf_size
;
1581 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1582 * @hdev: pointer to struct hclge_dev
1583 * @buf_alloc: pointer to buffer calculation data
1584 * @return: 0: calculate sucessful, negative: fail
1586 static int hclge_rx_buffer_calc(struct hclge_dev
*hdev
,
1587 struct hclge_pkt_buf_alloc
*buf_alloc
)
1589 u32 rx_all
= hdev
->pkt_buf_size
;
1590 int no_pfc_priv_num
, pfc_priv_num
;
1591 struct hclge_priv_buf
*priv
;
1594 rx_all
-= hclge_get_tx_buff_alloced(buf_alloc
);
1596 /* When DCB is not supported, rx private
1597 * buffer is not allocated.
1599 if (!hnae3_dev_dcb_supported(hdev
)) {
1600 if (!hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1606 /* step 1, try to alloc private buffer for all enabled tc */
1607 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1608 priv
= &buf_alloc
->priv_buf
[i
];
1609 if (hdev
->hw_tc_map
& BIT(i
)) {
1611 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1612 priv
->wl
.low
= hdev
->mps
;
1613 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1614 priv
->buf_size
= priv
->wl
.high
+
1618 priv
->wl
.high
= 2 * hdev
->mps
;
1619 priv
->buf_size
= priv
->wl
.high
;
1629 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1632 /* step 2, try to decrease the buffer size of
1633 * no pfc TC's private buffer
1635 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1636 priv
= &buf_alloc
->priv_buf
[i
];
1643 if (!(hdev
->hw_tc_map
& BIT(i
)))
1648 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1650 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1651 priv
->buf_size
= priv
->wl
.high
+ HCLGE_DEFAULT_DV
;
1654 priv
->wl
.high
= hdev
->mps
;
1655 priv
->buf_size
= priv
->wl
.high
;
1659 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1662 /* step 3, try to reduce the number of pfc disabled TCs,
1663 * which have private buffer
1665 /* get the total no pfc enable TC number, which have private buffer */
1666 no_pfc_priv_num
= hclge_get_no_pfc_priv_num(hdev
, buf_alloc
);
1668 /* let the last to be cleared first */
1669 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1670 priv
= &buf_alloc
->priv_buf
[i
];
1672 if (hdev
->hw_tc_map
& BIT(i
) &&
1673 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1674 /* Clear the no pfc TC private buffer */
1682 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1683 no_pfc_priv_num
== 0)
1687 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1690 /* step 4, try to reduce the number of pfc enabled TCs
1691 * which have private buffer.
1693 pfc_priv_num
= hclge_get_pfc_priv_num(hdev
, buf_alloc
);
1695 /* let the last to be cleared first */
1696 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1697 priv
= &buf_alloc
->priv_buf
[i
];
1699 if (hdev
->hw_tc_map
& BIT(i
) &&
1700 hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1701 /* Reduce the number of pfc TC with private buffer */
1709 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1713 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1719 static int hclge_rx_priv_buf_alloc(struct hclge_dev
*hdev
,
1720 struct hclge_pkt_buf_alloc
*buf_alloc
)
1722 struct hclge_rx_priv_buff_cmd
*req
;
1723 struct hclge_desc desc
;
1727 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_PRIV_BUFF_ALLOC
, false);
1728 req
= (struct hclge_rx_priv_buff_cmd
*)desc
.data
;
1730 /* Alloc private buffer TCs */
1731 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1732 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1735 cpu_to_le16(priv
->buf_size
>> HCLGE_BUF_UNIT_S
);
1737 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B
);
1741 cpu_to_le16((buf_alloc
->s_buf
.buf_size
>> HCLGE_BUF_UNIT_S
) |
1742 (1 << HCLGE_TC0_PRI_BUF_EN_B
));
1744 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1746 dev_err(&hdev
->pdev
->dev
,
1747 "rx private buffer alloc cmd failed %d\n", ret
);
1754 #define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1756 static int hclge_rx_priv_wl_config(struct hclge_dev
*hdev
,
1757 struct hclge_pkt_buf_alloc
*buf_alloc
)
1759 struct hclge_rx_priv_wl_buf
*req
;
1760 struct hclge_priv_buf
*priv
;
1761 struct hclge_desc desc
[2];
1765 for (i
= 0; i
< 2; i
++) {
1766 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_RX_PRIV_WL_ALLOC
,
1768 req
= (struct hclge_rx_priv_wl_buf
*)desc
[i
].data
;
1770 /* The first descriptor set the NEXT bit to 1 */
1772 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1774 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1776 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1777 u32 idx
= i
* HCLGE_TC_NUM_ONE_DESC
+ j
;
1779 priv
= &buf_alloc
->priv_buf
[idx
];
1780 req
->tc_wl
[j
].high
=
1781 cpu_to_le16(priv
->wl
.high
>> HCLGE_BUF_UNIT_S
);
1782 req
->tc_wl
[j
].high
|=
1783 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.high
) <<
1784 HCLGE_RX_PRIV_EN_B
);
1786 cpu_to_le16(priv
->wl
.low
>> HCLGE_BUF_UNIT_S
);
1787 req
->tc_wl
[j
].low
|=
1788 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.low
) <<
1789 HCLGE_RX_PRIV_EN_B
);
1793 /* Send 2 descriptor at one time */
1794 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1796 dev_err(&hdev
->pdev
->dev
,
1797 "rx private waterline config cmd failed %d\n",
1804 static int hclge_common_thrd_config(struct hclge_dev
*hdev
,
1805 struct hclge_pkt_buf_alloc
*buf_alloc
)
1807 struct hclge_shared_buf
*s_buf
= &buf_alloc
->s_buf
;
1808 struct hclge_rx_com_thrd
*req
;
1809 struct hclge_desc desc
[2];
1810 struct hclge_tc_thrd
*tc
;
1814 for (i
= 0; i
< 2; i
++) {
1815 hclge_cmd_setup_basic_desc(&desc
[i
],
1816 HCLGE_OPC_RX_COM_THRD_ALLOC
, false);
1817 req
= (struct hclge_rx_com_thrd
*)&desc
[i
].data
;
1819 /* The first descriptor set the NEXT bit to 1 */
1821 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1823 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1825 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1826 tc
= &s_buf
->tc_thrd
[i
* HCLGE_TC_NUM_ONE_DESC
+ j
];
1828 req
->com_thrd
[j
].high
=
1829 cpu_to_le16(tc
->high
>> HCLGE_BUF_UNIT_S
);
1830 req
->com_thrd
[j
].high
|=
1831 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->high
) <<
1832 HCLGE_RX_PRIV_EN_B
);
1833 req
->com_thrd
[j
].low
=
1834 cpu_to_le16(tc
->low
>> HCLGE_BUF_UNIT_S
);
1835 req
->com_thrd
[j
].low
|=
1836 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->low
) <<
1837 HCLGE_RX_PRIV_EN_B
);
1841 /* Send 2 descriptors at one time */
1842 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1844 dev_err(&hdev
->pdev
->dev
,
1845 "common threshold config cmd failed %d\n", ret
);
1851 static int hclge_common_wl_config(struct hclge_dev
*hdev
,
1852 struct hclge_pkt_buf_alloc
*buf_alloc
)
1854 struct hclge_shared_buf
*buf
= &buf_alloc
->s_buf
;
1855 struct hclge_rx_com_wl
*req
;
1856 struct hclge_desc desc
;
1859 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_COM_WL_ALLOC
, false);
1861 req
= (struct hclge_rx_com_wl
*)desc
.data
;
1862 req
->com_wl
.high
= cpu_to_le16(buf
->self
.high
>> HCLGE_BUF_UNIT_S
);
1864 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.high
) <<
1865 HCLGE_RX_PRIV_EN_B
);
1867 req
->com_wl
.low
= cpu_to_le16(buf
->self
.low
>> HCLGE_BUF_UNIT_S
);
1869 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.low
) <<
1870 HCLGE_RX_PRIV_EN_B
);
1872 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1874 dev_err(&hdev
->pdev
->dev
,
1875 "common waterline config cmd failed %d\n", ret
);
1882 int hclge_buffer_alloc(struct hclge_dev
*hdev
)
1884 struct hclge_pkt_buf_alloc
*pkt_buf
;
1887 pkt_buf
= kzalloc(sizeof(*pkt_buf
), GFP_KERNEL
);
1891 ret
= hclge_tx_buffer_calc(hdev
, pkt_buf
);
1893 dev_err(&hdev
->pdev
->dev
,
1894 "could not calc tx buffer size for all TCs %d\n", ret
);
1898 ret
= hclge_tx_buffer_alloc(hdev
, pkt_buf
);
1900 dev_err(&hdev
->pdev
->dev
,
1901 "could not alloc tx buffers %d\n", ret
);
1905 ret
= hclge_rx_buffer_calc(hdev
, pkt_buf
);
1907 dev_err(&hdev
->pdev
->dev
,
1908 "could not calc rx priv buffer size for all TCs %d\n",
1913 ret
= hclge_rx_priv_buf_alloc(hdev
, pkt_buf
);
1915 dev_err(&hdev
->pdev
->dev
, "could not alloc rx priv buffer %d\n",
1920 if (hnae3_dev_dcb_supported(hdev
)) {
1921 ret
= hclge_rx_priv_wl_config(hdev
, pkt_buf
);
1923 dev_err(&hdev
->pdev
->dev
,
1924 "could not configure rx private waterline %d\n",
1929 ret
= hclge_common_thrd_config(hdev
, pkt_buf
);
1931 dev_err(&hdev
->pdev
->dev
,
1932 "could not configure common threshold %d\n",
1938 ret
= hclge_common_wl_config(hdev
, pkt_buf
);
1940 dev_err(&hdev
->pdev
->dev
,
1941 "could not configure common waterline %d\n", ret
);
1948 static int hclge_init_roce_base_info(struct hclge_vport
*vport
)
1950 struct hnae3_handle
*roce
= &vport
->roce
;
1951 struct hnae3_handle
*nic
= &vport
->nic
;
1953 roce
->rinfo
.num_vectors
= vport
->back
->num_roce_msi
;
1955 if (vport
->back
->num_msi_left
< vport
->roce
.rinfo
.num_vectors
||
1956 vport
->back
->num_msi_left
== 0)
1959 roce
->rinfo
.base_vector
= vport
->back
->roce_base_vector
;
1961 roce
->rinfo
.netdev
= nic
->kinfo
.netdev
;
1962 roce
->rinfo
.roce_io_base
= vport
->back
->hw
.io_base
;
1964 roce
->pdev
= nic
->pdev
;
1965 roce
->ae_algo
= nic
->ae_algo
;
1966 roce
->numa_node_mask
= nic
->numa_node_mask
;
1971 static int hclge_init_msi(struct hclge_dev
*hdev
)
1973 struct pci_dev
*pdev
= hdev
->pdev
;
1977 vectors
= pci_alloc_irq_vectors(pdev
, 1, hdev
->num_msi
,
1978 PCI_IRQ_MSI
| PCI_IRQ_MSIX
);
1981 "failed(%d) to allocate MSI/MSI-X vectors\n",
1985 if (vectors
< hdev
->num_msi
)
1986 dev_warn(&hdev
->pdev
->dev
,
1987 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1988 hdev
->num_msi
, vectors
);
1990 hdev
->num_msi
= vectors
;
1991 hdev
->num_msi_left
= vectors
;
1992 hdev
->base_msi_vector
= pdev
->irq
;
1993 hdev
->roce_base_vector
= hdev
->base_msi_vector
+
1994 HCLGE_ROCE_VECTOR_OFFSET
;
1996 hdev
->vector_status
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
1997 sizeof(u16
), GFP_KERNEL
);
1998 if (!hdev
->vector_status
) {
1999 pci_free_irq_vectors(pdev
);
2003 for (i
= 0; i
< hdev
->num_msi
; i
++)
2004 hdev
->vector_status
[i
] = HCLGE_INVALID_VPORT
;
2006 hdev
->vector_irq
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2007 sizeof(int), GFP_KERNEL
);
2008 if (!hdev
->vector_irq
) {
2009 pci_free_irq_vectors(pdev
);
2016 static void hclge_check_speed_dup(struct hclge_dev
*hdev
, int duplex
, int speed
)
2018 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2020 if ((speed
== HCLGE_MAC_SPEED_10M
) || (speed
== HCLGE_MAC_SPEED_100M
))
2021 mac
->duplex
= (u8
)duplex
;
2023 mac
->duplex
= HCLGE_MAC_FULL
;
2028 int hclge_cfg_mac_speed_dup(struct hclge_dev
*hdev
, int speed
, u8 duplex
)
2030 struct hclge_config_mac_speed_dup_cmd
*req
;
2031 struct hclge_desc desc
;
2034 req
= (struct hclge_config_mac_speed_dup_cmd
*)desc
.data
;
2036 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_SPEED_DUP
, false);
2038 hnae_set_bit(req
->speed_dup
, HCLGE_CFG_DUPLEX_B
, !!duplex
);
2041 case HCLGE_MAC_SPEED_10M
:
2042 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2043 HCLGE_CFG_SPEED_S
, 6);
2045 case HCLGE_MAC_SPEED_100M
:
2046 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2047 HCLGE_CFG_SPEED_S
, 7);
2049 case HCLGE_MAC_SPEED_1G
:
2050 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2051 HCLGE_CFG_SPEED_S
, 0);
2053 case HCLGE_MAC_SPEED_10G
:
2054 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2055 HCLGE_CFG_SPEED_S
, 1);
2057 case HCLGE_MAC_SPEED_25G
:
2058 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2059 HCLGE_CFG_SPEED_S
, 2);
2061 case HCLGE_MAC_SPEED_40G
:
2062 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2063 HCLGE_CFG_SPEED_S
, 3);
2065 case HCLGE_MAC_SPEED_50G
:
2066 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2067 HCLGE_CFG_SPEED_S
, 4);
2069 case HCLGE_MAC_SPEED_100G
:
2070 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2071 HCLGE_CFG_SPEED_S
, 5);
2074 dev_err(&hdev
->pdev
->dev
, "invalid speed (%d)\n", speed
);
2078 hnae_set_bit(req
->mac_change_fec_en
, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B
,
2081 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2083 dev_err(&hdev
->pdev
->dev
,
2084 "mac speed/duplex config cmd failed %d.\n", ret
);
2088 hclge_check_speed_dup(hdev
, duplex
, speed
);
2093 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle
*handle
, int speed
,
2096 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2097 struct hclge_dev
*hdev
= vport
->back
;
2099 return hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2102 static int hclge_query_mac_an_speed_dup(struct hclge_dev
*hdev
, int *speed
,
2105 struct hclge_query_an_speed_dup_cmd
*req
;
2106 struct hclge_desc desc
;
2110 req
= (struct hclge_query_an_speed_dup_cmd
*)desc
.data
;
2112 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_AN_RESULT
, true);
2113 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2115 dev_err(&hdev
->pdev
->dev
,
2116 "mac speed/autoneg/duplex query cmd failed %d\n",
2121 *duplex
= hnae_get_bit(req
->an_syn_dup_speed
, HCLGE_QUERY_DUPLEX_B
);
2122 speed_tmp
= hnae_get_field(req
->an_syn_dup_speed
, HCLGE_QUERY_SPEED_M
,
2123 HCLGE_QUERY_SPEED_S
);
2125 ret
= hclge_parse_speed(speed_tmp
, speed
);
2127 dev_err(&hdev
->pdev
->dev
,
2128 "could not parse speed(=%d), %d\n", speed_tmp
, ret
);
2135 static int hclge_query_autoneg_result(struct hclge_dev
*hdev
)
2137 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2138 struct hclge_query_an_speed_dup_cmd
*req
;
2139 struct hclge_desc desc
;
2142 req
= (struct hclge_query_an_speed_dup_cmd
*)desc
.data
;
2144 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_AN_RESULT
, true);
2145 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2147 dev_err(&hdev
->pdev
->dev
,
2148 "autoneg result query cmd failed %d.\n", ret
);
2152 mac
->autoneg
= hnae_get_bit(req
->an_syn_dup_speed
, HCLGE_QUERY_AN_B
);
2157 static int hclge_set_autoneg_en(struct hclge_dev
*hdev
, bool enable
)
2159 struct hclge_config_auto_neg_cmd
*req
;
2160 struct hclge_desc desc
;
2164 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_AN_MODE
, false);
2166 req
= (struct hclge_config_auto_neg_cmd
*)desc
.data
;
2167 hnae_set_bit(flag
, HCLGE_MAC_CFG_AN_EN_B
, !!enable
);
2168 req
->cfg_an_cmd_flag
= cpu_to_le32(flag
);
2170 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2172 dev_err(&hdev
->pdev
->dev
, "auto neg set cmd failed %d.\n",
2180 static int hclge_set_autoneg(struct hnae3_handle
*handle
, bool enable
)
2182 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2183 struct hclge_dev
*hdev
= vport
->back
;
2185 return hclge_set_autoneg_en(hdev
, enable
);
2188 static int hclge_get_autoneg(struct hnae3_handle
*handle
)
2190 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2191 struct hclge_dev
*hdev
= vport
->back
;
2193 hclge_query_autoneg_result(hdev
);
2195 return hdev
->hw
.mac
.autoneg
;
2198 static int hclge_mac_init(struct hclge_dev
*hdev
)
2200 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2203 ret
= hclge_cfg_mac_speed_dup(hdev
, hdev
->hw
.mac
.speed
, HCLGE_MAC_FULL
);
2205 dev_err(&hdev
->pdev
->dev
,
2206 "Config mac speed dup fail ret=%d\n", ret
);
2212 /* Initialize the MTA table work mode */
2213 hdev
->accept_mta_mc
= true;
2214 hdev
->enable_mta
= true;
2215 hdev
->mta_mac_sel_type
= HCLGE_MAC_ADDR_47_36
;
2217 ret
= hclge_set_mta_filter_mode(hdev
,
2218 hdev
->mta_mac_sel_type
,
2221 dev_err(&hdev
->pdev
->dev
, "set mta filter mode failed %d\n",
2226 return hclge_cfg_func_mta_filter(hdev
, 0, hdev
->accept_mta_mc
);
2229 static void hclge_reset_task_schedule(struct hclge_dev
*hdev
)
2231 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
))
2232 schedule_work(&hdev
->rst_service_task
);
2235 static void hclge_task_schedule(struct hclge_dev
*hdev
)
2237 if (!test_bit(HCLGE_STATE_DOWN
, &hdev
->state
) &&
2238 !test_bit(HCLGE_STATE_REMOVING
, &hdev
->state
) &&
2239 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
))
2240 (void)schedule_work(&hdev
->service_task
);
2243 static int hclge_get_mac_link_status(struct hclge_dev
*hdev
)
2245 struct hclge_link_status_cmd
*req
;
2246 struct hclge_desc desc
;
2250 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_LINK_STATUS
, true);
2251 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2253 dev_err(&hdev
->pdev
->dev
, "get link status cmd failed %d\n",
2258 req
= (struct hclge_link_status_cmd
*)desc
.data
;
2259 link_status
= req
->status
& HCLGE_LINK_STATUS
;
2261 return !!link_status
;
2264 static int hclge_get_mac_phy_link(struct hclge_dev
*hdev
)
2269 mac_state
= hclge_get_mac_link_status(hdev
);
2271 if (hdev
->hw
.mac
.phydev
) {
2272 if (!genphy_read_status(hdev
->hw
.mac
.phydev
))
2273 link_stat
= mac_state
&
2274 hdev
->hw
.mac
.phydev
->link
;
2279 link_stat
= mac_state
;
2285 static void hclge_update_link_status(struct hclge_dev
*hdev
)
2287 struct hnae3_client
*client
= hdev
->nic_client
;
2288 struct hnae3_handle
*handle
;
2294 state
= hclge_get_mac_phy_link(hdev
);
2295 if (state
!= hdev
->hw
.mac
.link
) {
2296 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2297 handle
= &hdev
->vport
[i
].nic
;
2298 client
->ops
->link_status_change(handle
, state
);
2300 hdev
->hw
.mac
.link
= state
;
2304 static int hclge_update_speed_duplex(struct hclge_dev
*hdev
)
2306 struct hclge_mac mac
= hdev
->hw
.mac
;
2311 /* get the speed and duplex as autoneg'result from mac cmd when phy
2314 if (mac
.phydev
|| !mac
.autoneg
)
2317 ret
= hclge_query_mac_an_speed_dup(hdev
, &speed
, &duplex
);
2319 dev_err(&hdev
->pdev
->dev
,
2320 "mac autoneg/speed/duplex query failed %d\n", ret
);
2324 if ((mac
.speed
!= speed
) || (mac
.duplex
!= duplex
)) {
2325 ret
= hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2327 dev_err(&hdev
->pdev
->dev
,
2328 "mac speed/duplex config failed %d\n", ret
);
2336 static int hclge_update_speed_duplex_h(struct hnae3_handle
*handle
)
2338 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2339 struct hclge_dev
*hdev
= vport
->back
;
2341 return hclge_update_speed_duplex(hdev
);
2344 static int hclge_get_status(struct hnae3_handle
*handle
)
2346 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2347 struct hclge_dev
*hdev
= vport
->back
;
2349 hclge_update_link_status(hdev
);
2351 return hdev
->hw
.mac
.link
;
2354 static void hclge_service_timer(struct timer_list
*t
)
2356 struct hclge_dev
*hdev
= from_timer(hdev
, t
, service_timer
);
2358 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
2359 hclge_task_schedule(hdev
);
2362 static void hclge_service_complete(struct hclge_dev
*hdev
)
2364 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
));
2366 /* Flush memory before next watchdog */
2367 smp_mb__before_atomic();
2368 clear_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
);
2371 static u32
hclge_check_event_cause(struct hclge_dev
*hdev
, u32
*clearval
)
2375 /* fetch the events from their corresponding regs */
2376 rst_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
);
2378 /* check for vector0 reset event sources */
2379 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
) & rst_src_reg
) {
2380 set_bit(HNAE3_GLOBAL_RESET
, &hdev
->reset_pending
);
2381 *clearval
= BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
);
2382 return HCLGE_VECTOR0_EVENT_RST
;
2385 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B
) & rst_src_reg
) {
2386 set_bit(HNAE3_CORE_RESET
, &hdev
->reset_pending
);
2387 *clearval
= BIT(HCLGE_VECTOR0_CORERESET_INT_B
);
2388 return HCLGE_VECTOR0_EVENT_RST
;
2391 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B
) & rst_src_reg
) {
2392 set_bit(HNAE3_IMP_RESET
, &hdev
->reset_pending
);
2393 *clearval
= BIT(HCLGE_VECTOR0_IMPRESET_INT_B
);
2394 return HCLGE_VECTOR0_EVENT_RST
;
2397 /* mailbox event sharing vector 0 interrupt would be placed here */
2399 return HCLGE_VECTOR0_EVENT_OTHER
;
2402 static void hclge_clear_event_cause(struct hclge_dev
*hdev
, u32 event_type
,
2405 if (event_type
== HCLGE_VECTOR0_EVENT_RST
)
2406 hclge_write_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
, regclr
);
2408 /* mailbox event sharing vector 0 interrupt would be placed here */
2411 static void hclge_enable_vector(struct hclge_misc_vector
*vector
, bool enable
)
2413 writel(enable
? 1 : 0, vector
->addr
);
2416 static irqreturn_t
hclge_misc_irq_handle(int irq
, void *data
)
2418 struct hclge_dev
*hdev
= data
;
2422 hclge_enable_vector(&hdev
->misc_vector
, false);
2423 event_cause
= hclge_check_event_cause(hdev
, &clearval
);
2425 /* vector 0 interrupt is shared with reset and mailbox source events.
2426 * For now, we are not handling mailbox events.
2428 switch (event_cause
) {
2429 case HCLGE_VECTOR0_EVENT_RST
:
2430 hclge_reset_task_schedule(hdev
);
2433 dev_dbg(&hdev
->pdev
->dev
,
2434 "received unknown or unhandled event of vector0\n");
2438 /* we should clear the source of interrupt */
2439 hclge_clear_event_cause(hdev
, event_cause
, clearval
);
2440 hclge_enable_vector(&hdev
->misc_vector
, true);
2445 static void hclge_free_vector(struct hclge_dev
*hdev
, int vector_id
)
2447 hdev
->vector_status
[vector_id
] = HCLGE_INVALID_VPORT
;
2448 hdev
->num_msi_left
+= 1;
2449 hdev
->num_msi_used
-= 1;
2452 static void hclge_get_misc_vector(struct hclge_dev
*hdev
)
2454 struct hclge_misc_vector
*vector
= &hdev
->misc_vector
;
2456 vector
->vector_irq
= pci_irq_vector(hdev
->pdev
, 0);
2458 vector
->addr
= hdev
->hw
.io_base
+ HCLGE_MISC_VECTOR_REG_BASE
;
2459 hdev
->vector_status
[0] = 0;
2461 hdev
->num_msi_left
-= 1;
2462 hdev
->num_msi_used
+= 1;
2465 static int hclge_misc_irq_init(struct hclge_dev
*hdev
)
2469 hclge_get_misc_vector(hdev
);
2471 /* this would be explicitly freed in the end */
2472 ret
= request_irq(hdev
->misc_vector
.vector_irq
, hclge_misc_irq_handle
,
2473 0, "hclge_misc", hdev
);
2475 hclge_free_vector(hdev
, 0);
2476 dev_err(&hdev
->pdev
->dev
, "request misc irq(%d) fail\n",
2477 hdev
->misc_vector
.vector_irq
);
2483 static void hclge_misc_irq_uninit(struct hclge_dev
*hdev
)
2485 free_irq(hdev
->misc_vector
.vector_irq
, hdev
);
2486 hclge_free_vector(hdev
, 0);
2489 static int hclge_notify_client(struct hclge_dev
*hdev
,
2490 enum hnae3_reset_notify_type type
)
2492 struct hnae3_client
*client
= hdev
->nic_client
;
2495 if (!client
->ops
->reset_notify
)
2498 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2499 struct hnae3_handle
*handle
= &hdev
->vport
[i
].nic
;
2502 ret
= client
->ops
->reset_notify(handle
, type
);
2510 static int hclge_reset_wait(struct hclge_dev
*hdev
)
2512 #define HCLGE_RESET_WATI_MS 100
2513 #define HCLGE_RESET_WAIT_CNT 5
2514 u32 val
, reg
, reg_bit
;
2517 switch (hdev
->reset_type
) {
2518 case HNAE3_GLOBAL_RESET
:
2519 reg
= HCLGE_GLOBAL_RESET_REG
;
2520 reg_bit
= HCLGE_GLOBAL_RESET_BIT
;
2522 case HNAE3_CORE_RESET
:
2523 reg
= HCLGE_GLOBAL_RESET_REG
;
2524 reg_bit
= HCLGE_CORE_RESET_BIT
;
2526 case HNAE3_FUNC_RESET
:
2527 reg
= HCLGE_FUN_RST_ING
;
2528 reg_bit
= HCLGE_FUN_RST_ING_B
;
2531 dev_err(&hdev
->pdev
->dev
,
2532 "Wait for unsupported reset type: %d\n",
2537 val
= hclge_read_dev(&hdev
->hw
, reg
);
2538 while (hnae_get_bit(val
, reg_bit
) && cnt
< HCLGE_RESET_WAIT_CNT
) {
2539 msleep(HCLGE_RESET_WATI_MS
);
2540 val
= hclge_read_dev(&hdev
->hw
, reg
);
2544 if (cnt
>= HCLGE_RESET_WAIT_CNT
) {
2545 dev_warn(&hdev
->pdev
->dev
,
2546 "Wait for reset timeout: %d\n", hdev
->reset_type
);
2553 static int hclge_func_reset_cmd(struct hclge_dev
*hdev
, int func_id
)
2555 struct hclge_desc desc
;
2556 struct hclge_reset_cmd
*req
= (struct hclge_reset_cmd
*)desc
.data
;
2559 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_RST_TRIGGER
, false);
2560 hnae_set_bit(req
->mac_func_reset
, HCLGE_CFG_RESET_MAC_B
, 0);
2561 hnae_set_bit(req
->mac_func_reset
, HCLGE_CFG_RESET_FUNC_B
, 1);
2562 req
->fun_reset_vfid
= func_id
;
2564 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2566 dev_err(&hdev
->pdev
->dev
,
2567 "send function reset cmd fail, status =%d\n", ret
);
2572 static void hclge_do_reset(struct hclge_dev
*hdev
, enum hnae3_reset_type type
)
2574 struct pci_dev
*pdev
= hdev
->pdev
;
2578 case HNAE3_GLOBAL_RESET
:
2579 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2580 hnae_set_bit(val
, HCLGE_GLOBAL_RESET_BIT
, 1);
2581 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2582 dev_info(&pdev
->dev
, "Global Reset requested\n");
2584 case HNAE3_CORE_RESET
:
2585 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2586 hnae_set_bit(val
, HCLGE_CORE_RESET_BIT
, 1);
2587 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2588 dev_info(&pdev
->dev
, "Core Reset requested\n");
2590 case HNAE3_FUNC_RESET
:
2591 dev_info(&pdev
->dev
, "PF Reset requested\n");
2592 hclge_func_reset_cmd(hdev
, 0);
2593 /* schedule again to check later */
2594 set_bit(HNAE3_FUNC_RESET
, &hdev
->reset_pending
);
2595 hclge_reset_task_schedule(hdev
);
2598 dev_warn(&pdev
->dev
,
2599 "Unsupported reset type: %d\n", type
);
2604 static void hclge_reset_event(struct hnae3_handle
*handle
,
2605 enum hnae3_reset_type reset
)
2607 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2608 struct hclge_dev
*hdev
= vport
->back
;
2610 dev_info(&hdev
->pdev
->dev
,
2611 "Receive reset event , reset_type is %d", reset
);
2614 case HNAE3_FUNC_RESET
:
2615 case HNAE3_CORE_RESET
:
2616 case HNAE3_GLOBAL_RESET
:
2617 /* request reset & schedule reset task */
2618 set_bit(reset
, &hdev
->reset_request
);
2619 hclge_reset_task_schedule(hdev
);
2622 dev_warn(&hdev
->pdev
->dev
, "Unsupported reset event:%d", reset
);
2627 static void hclge_reset_subtask(struct hclge_dev
*hdev
)
2631 do_reset
= hdev
->reset_type
!= HNAE3_NONE_RESET
;
2634 if (hdev
->reset_type
== HNAE3_NONE_RESET
)
2637 switch (hdev
->reset_type
) {
2638 case HNAE3_FUNC_RESET
:
2639 case HNAE3_CORE_RESET
:
2640 case HNAE3_GLOBAL_RESET
:
2641 case HNAE3_IMP_RESET
:
2642 hclge_notify_client(hdev
, HNAE3_DOWN_CLIENT
);
2645 hclge_do_reset(hdev
, hdev
->reset_type
);
2647 set_bit(HCLGE_STATE_RESET_INT
, &hdev
->state
);
2649 if (!hclge_reset_wait(hdev
)) {
2650 hclge_notify_client(hdev
, HNAE3_UNINIT_CLIENT
);
2651 hclge_reset_ae_dev(hdev
->ae_dev
);
2652 hclge_notify_client(hdev
, HNAE3_INIT_CLIENT
);
2653 clear_bit(HCLGE_STATE_RESET_INT
, &hdev
->state
);
2655 hclge_notify_client(hdev
, HNAE3_UP_CLIENT
);
2658 dev_err(&hdev
->pdev
->dev
, "Unsupported reset type:%d\n",
2662 hdev
->reset_type
= HNAE3_NONE_RESET
;
2665 static void hclge_reset_service_task(struct work_struct
*work
)
2667 struct hclge_dev
*hdev
=
2668 container_of(work
, struct hclge_dev
, rst_service_task
);
2670 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
2673 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
2675 hclge_reset_subtask(hdev
);
2677 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
2680 static void hclge_service_task(struct work_struct
*work
)
2682 struct hclge_dev
*hdev
=
2683 container_of(work
, struct hclge_dev
, service_task
);
2685 hclge_update_speed_duplex(hdev
);
2686 hclge_update_link_status(hdev
);
2687 hclge_update_stats_for_all(hdev
);
2688 hclge_service_complete(hdev
);
2691 static void hclge_disable_sriov(struct hclge_dev
*hdev
)
2693 /* If our VFs are assigned we cannot shut down SR-IOV
2694 * without causing issues, so just leave the hardware
2695 * available but disabled
2697 if (pci_vfs_assigned(hdev
->pdev
)) {
2698 dev_warn(&hdev
->pdev
->dev
,
2699 "disabling driver while VFs are assigned\n");
2703 pci_disable_sriov(hdev
->pdev
);
2706 struct hclge_vport
*hclge_get_vport(struct hnae3_handle
*handle
)
2708 /* VF handle has no client */
2709 if (!handle
->client
)
2710 return container_of(handle
, struct hclge_vport
, nic
);
2711 else if (handle
->client
->type
== HNAE3_CLIENT_ROCE
)
2712 return container_of(handle
, struct hclge_vport
, roce
);
2714 return container_of(handle
, struct hclge_vport
, nic
);
2717 static int hclge_get_vector(struct hnae3_handle
*handle
, u16 vector_num
,
2718 struct hnae3_vector_info
*vector_info
)
2720 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2721 struct hnae3_vector_info
*vector
= vector_info
;
2722 struct hclge_dev
*hdev
= vport
->back
;
2726 vector_num
= min(hdev
->num_msi_left
, vector_num
);
2728 for (j
= 0; j
< vector_num
; j
++) {
2729 for (i
= 1; i
< hdev
->num_msi
; i
++) {
2730 if (hdev
->vector_status
[i
] == HCLGE_INVALID_VPORT
) {
2731 vector
->vector
= pci_irq_vector(hdev
->pdev
, i
);
2732 vector
->io_addr
= hdev
->hw
.io_base
+
2733 HCLGE_VECTOR_REG_BASE
+
2734 (i
- 1) * HCLGE_VECTOR_REG_OFFSET
+
2736 HCLGE_VECTOR_VF_OFFSET
;
2737 hdev
->vector_status
[i
] = vport
->vport_id
;
2738 hdev
->vector_irq
[i
] = vector
->vector
;
2747 hdev
->num_msi_left
-= alloc
;
2748 hdev
->num_msi_used
+= alloc
;
2753 static int hclge_get_vector_index(struct hclge_dev
*hdev
, int vector
)
2757 for (i
= 0; i
< hdev
->num_msi
; i
++)
2758 if (vector
== hdev
->vector_irq
[i
])
2764 static u32
hclge_get_rss_key_size(struct hnae3_handle
*handle
)
2766 return HCLGE_RSS_KEY_SIZE
;
2769 static u32
hclge_get_rss_indir_size(struct hnae3_handle
*handle
)
2771 return HCLGE_RSS_IND_TBL_SIZE
;
2774 static int hclge_get_rss_algo(struct hclge_dev
*hdev
)
2776 struct hclge_rss_config_cmd
*req
;
2777 struct hclge_desc desc
;
2781 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_GENERIC_CONFIG
, true);
2783 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2785 dev_err(&hdev
->pdev
->dev
,
2786 "Get link status error, status =%d\n", ret
);
2790 req
= (struct hclge_rss_config_cmd
*)desc
.data
;
2791 rss_hash_algo
= (req
->hash_config
& HCLGE_RSS_HASH_ALGO_MASK
);
2793 if (rss_hash_algo
== HCLGE_RSS_HASH_ALGO_TOEPLITZ
)
2794 return ETH_RSS_HASH_TOP
;
2799 static int hclge_set_rss_algo_key(struct hclge_dev
*hdev
,
2800 const u8 hfunc
, const u8
*key
)
2802 struct hclge_rss_config_cmd
*req
;
2803 struct hclge_desc desc
;
2808 req
= (struct hclge_rss_config_cmd
*)desc
.data
;
2810 for (key_offset
= 0; key_offset
< 3; key_offset
++) {
2811 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_GENERIC_CONFIG
,
2814 req
->hash_config
|= (hfunc
& HCLGE_RSS_HASH_ALGO_MASK
);
2815 req
->hash_config
|= (key_offset
<< HCLGE_RSS_HASH_KEY_OFFSET_B
);
2817 if (key_offset
== 2)
2819 HCLGE_RSS_KEY_SIZE
- HCLGE_RSS_HASH_KEY_NUM
* 2;
2821 key_size
= HCLGE_RSS_HASH_KEY_NUM
;
2823 memcpy(req
->hash_key
,
2824 key
+ key_offset
* HCLGE_RSS_HASH_KEY_NUM
, key_size
);
2826 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2828 dev_err(&hdev
->pdev
->dev
,
2829 "Configure RSS config fail, status = %d\n",
2837 static int hclge_set_rss_indir_table(struct hclge_dev
*hdev
, const u32
*indir
)
2839 struct hclge_rss_indirection_table_cmd
*req
;
2840 struct hclge_desc desc
;
2844 req
= (struct hclge_rss_indirection_table_cmd
*)desc
.data
;
2846 for (i
= 0; i
< HCLGE_RSS_CFG_TBL_NUM
; i
++) {
2847 hclge_cmd_setup_basic_desc
2848 (&desc
, HCLGE_OPC_RSS_INDIR_TABLE
, false);
2850 req
->start_table_index
=
2851 cpu_to_le16(i
* HCLGE_RSS_CFG_TBL_SIZE
);
2852 req
->rss_set_bitmap
= cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK
);
2854 for (j
= 0; j
< HCLGE_RSS_CFG_TBL_SIZE
; j
++)
2855 req
->rss_result
[j
] =
2856 indir
[i
* HCLGE_RSS_CFG_TBL_SIZE
+ j
];
2858 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2860 dev_err(&hdev
->pdev
->dev
,
2861 "Configure rss indir table fail,status = %d\n",
2869 static int hclge_set_rss_tc_mode(struct hclge_dev
*hdev
, u16
*tc_valid
,
2870 u16
*tc_size
, u16
*tc_offset
)
2872 struct hclge_rss_tc_mode_cmd
*req
;
2873 struct hclge_desc desc
;
2877 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_TC_MODE
, false);
2878 req
= (struct hclge_rss_tc_mode_cmd
*)desc
.data
;
2880 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
2883 hnae_set_bit(mode
, HCLGE_RSS_TC_VALID_B
, (tc_valid
[i
] & 0x1));
2884 hnae_set_field(mode
, HCLGE_RSS_TC_SIZE_M
,
2885 HCLGE_RSS_TC_SIZE_S
, tc_size
[i
]);
2886 hnae_set_field(mode
, HCLGE_RSS_TC_OFFSET_M
,
2887 HCLGE_RSS_TC_OFFSET_S
, tc_offset
[i
]);
2889 req
->rss_tc_mode
[i
] = cpu_to_le16(mode
);
2892 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2894 dev_err(&hdev
->pdev
->dev
,
2895 "Configure rss tc mode fail, status = %d\n", ret
);
2902 static int hclge_set_rss_input_tuple(struct hclge_dev
*hdev
)
2904 struct hclge_rss_input_tuple_cmd
*req
;
2905 struct hclge_desc desc
;
2908 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
2910 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
2911 req
->ipv4_tcp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
2912 req
->ipv4_udp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
2913 req
->ipv4_sctp_en
= HCLGE_RSS_INPUT_TUPLE_SCTP
;
2914 req
->ipv4_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
2915 req
->ipv6_tcp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
2916 req
->ipv6_udp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
2917 req
->ipv6_sctp_en
= HCLGE_RSS_INPUT_TUPLE_SCTP
;
2918 req
->ipv6_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
2919 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2921 dev_err(&hdev
->pdev
->dev
,
2922 "Configure rss input fail, status = %d\n", ret
);
2929 static int hclge_get_rss(struct hnae3_handle
*handle
, u32
*indir
,
2932 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2933 struct hclge_dev
*hdev
= vport
->back
;
2936 /* Get hash algorithm */
2938 *hfunc
= hclge_get_rss_algo(hdev
);
2940 /* Get the RSS Key required by the user */
2942 memcpy(key
, vport
->rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
2944 /* Get indirect table */
2946 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
2947 indir
[i
] = vport
->rss_indirection_tbl
[i
];
2952 static int hclge_set_rss(struct hnae3_handle
*handle
, const u32
*indir
,
2953 const u8
*key
, const u8 hfunc
)
2955 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2956 struct hclge_dev
*hdev
= vport
->back
;
2960 /* Set the RSS Hash Key if specififed by the user */
2962 /* Update the shadow RSS key with user specified qids */
2963 memcpy(vport
->rss_hash_key
, key
, HCLGE_RSS_KEY_SIZE
);
2965 if (hfunc
== ETH_RSS_HASH_TOP
||
2966 hfunc
== ETH_RSS_HASH_NO_CHANGE
)
2967 hash_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
2970 ret
= hclge_set_rss_algo_key(hdev
, hash_algo
, key
);
2975 /* Update the shadow RSS table with user specified qids */
2976 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
2977 vport
->rss_indirection_tbl
[i
] = indir
[i
];
2979 /* Update the hardware */
2980 ret
= hclge_set_rss_indir_table(hdev
, indir
);
2984 static u8
hclge_get_rss_hash_bits(struct ethtool_rxnfc
*nfc
)
2986 u8 hash_sets
= nfc
->data
& RXH_L4_B_0_1
? HCLGE_S_PORT_BIT
: 0;
2988 if (nfc
->data
& RXH_L4_B_2_3
)
2989 hash_sets
|= HCLGE_D_PORT_BIT
;
2991 hash_sets
&= ~HCLGE_D_PORT_BIT
;
2993 if (nfc
->data
& RXH_IP_SRC
)
2994 hash_sets
|= HCLGE_S_IP_BIT
;
2996 hash_sets
&= ~HCLGE_S_IP_BIT
;
2998 if (nfc
->data
& RXH_IP_DST
)
2999 hash_sets
|= HCLGE_D_IP_BIT
;
3001 hash_sets
&= ~HCLGE_D_IP_BIT
;
3003 if (nfc
->flow_type
== SCTP_V4_FLOW
|| nfc
->flow_type
== SCTP_V6_FLOW
)
3004 hash_sets
|= HCLGE_V_TAG_BIT
;
3009 static int hclge_set_rss_tuple(struct hnae3_handle
*handle
,
3010 struct ethtool_rxnfc
*nfc
)
3012 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3013 struct hclge_dev
*hdev
= vport
->back
;
3014 struct hclge_rss_input_tuple_cmd
*req
;
3015 struct hclge_desc desc
;
3019 if (nfc
->data
& ~(RXH_IP_SRC
| RXH_IP_DST
|
3020 RXH_L4_B_0_1
| RXH_L4_B_2_3
))
3023 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3024 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, true);
3025 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3027 dev_err(&hdev
->pdev
->dev
,
3028 "Read rss tuple fail, status = %d\n", ret
);
3032 hclge_cmd_reuse_desc(&desc
, false);
3034 tuple_sets
= hclge_get_rss_hash_bits(nfc
);
3035 switch (nfc
->flow_type
) {
3037 req
->ipv4_tcp_en
= tuple_sets
;
3040 req
->ipv6_tcp_en
= tuple_sets
;
3043 req
->ipv4_udp_en
= tuple_sets
;
3046 req
->ipv6_udp_en
= tuple_sets
;
3049 req
->ipv4_sctp_en
= tuple_sets
;
3052 if ((nfc
->data
& RXH_L4_B_0_1
) ||
3053 (nfc
->data
& RXH_L4_B_2_3
))
3056 req
->ipv6_sctp_en
= tuple_sets
;
3059 req
->ipv4_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3062 req
->ipv6_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3068 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3070 dev_err(&hdev
->pdev
->dev
,
3071 "Set rss tuple fail, status = %d\n", ret
);
3076 static int hclge_get_rss_tuple(struct hnae3_handle
*handle
,
3077 struct ethtool_rxnfc
*nfc
)
3079 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3080 struct hclge_dev
*hdev
= vport
->back
;
3081 struct hclge_rss_input_tuple_cmd
*req
;
3082 struct hclge_desc desc
;
3088 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3089 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, true);
3090 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3092 dev_err(&hdev
->pdev
->dev
,
3093 "Read rss tuple fail, status = %d\n", ret
);
3097 switch (nfc
->flow_type
) {
3099 tuple_sets
= req
->ipv4_tcp_en
;
3102 tuple_sets
= req
->ipv4_udp_en
;
3105 tuple_sets
= req
->ipv6_tcp_en
;
3108 tuple_sets
= req
->ipv6_udp_en
;
3111 tuple_sets
= req
->ipv4_sctp_en
;
3114 tuple_sets
= req
->ipv6_sctp_en
;
3118 tuple_sets
= HCLGE_S_IP_BIT
| HCLGE_D_IP_BIT
;
3127 if (tuple_sets
& HCLGE_D_PORT_BIT
)
3128 nfc
->data
|= RXH_L4_B_2_3
;
3129 if (tuple_sets
& HCLGE_S_PORT_BIT
)
3130 nfc
->data
|= RXH_L4_B_0_1
;
3131 if (tuple_sets
& HCLGE_D_IP_BIT
)
3132 nfc
->data
|= RXH_IP_DST
;
3133 if (tuple_sets
& HCLGE_S_IP_BIT
)
3134 nfc
->data
|= RXH_IP_SRC
;
3139 static int hclge_get_tc_size(struct hnae3_handle
*handle
)
3141 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3142 struct hclge_dev
*hdev
= vport
->back
;
3144 return hdev
->rss_size_max
;
3147 int hclge_rss_init_hw(struct hclge_dev
*hdev
)
3149 const u8 hfunc
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3150 struct hclge_vport
*vport
= hdev
->vport
;
3151 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
3152 u8 rss_key
[HCLGE_RSS_KEY_SIZE
];
3153 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
3154 u16 tc_size
[HCLGE_MAX_TC_NUM
];
3155 u32
*rss_indir
= NULL
;
3156 u16 rss_size
= 0, roundup_size
;
3160 rss_indir
= kcalloc(HCLGE_RSS_IND_TBL_SIZE
, sizeof(u32
), GFP_KERNEL
);
3164 /* Get default RSS key */
3165 netdev_rss_key_fill(rss_key
, HCLGE_RSS_KEY_SIZE
);
3167 /* Initialize RSS indirect table for each vport */
3168 for (j
= 0; j
< hdev
->num_vmdq_vport
+ 1; j
++) {
3169 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++) {
3170 vport
[j
].rss_indirection_tbl
[i
] =
3171 i
% vport
[j
].alloc_rss_size
;
3173 /* vport 0 is for PF */
3177 rss_size
= vport
[j
].alloc_rss_size
;
3178 rss_indir
[i
] = vport
[j
].rss_indirection_tbl
[i
];
3181 ret
= hclge_set_rss_indir_table(hdev
, rss_indir
);
3186 ret
= hclge_set_rss_algo_key(hdev
, hfunc
, key
);
3190 ret
= hclge_set_rss_input_tuple(hdev
);
3194 /* Each TC have the same queue size, and tc_size set to hardware is
3195 * the log2 of roundup power of two of rss_size, the acutal queue
3196 * size is limited by indirection table.
3198 if (rss_size
> HCLGE_RSS_TC_SIZE_7
|| rss_size
== 0) {
3199 dev_err(&hdev
->pdev
->dev
,
3200 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3206 roundup_size
= roundup_pow_of_two(rss_size
);
3207 roundup_size
= ilog2(roundup_size
);
3209 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3212 if (!(hdev
->hw_tc_map
& BIT(i
)))
3216 tc_size
[i
] = roundup_size
;
3217 tc_offset
[i
] = rss_size
* i
;
3220 ret
= hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
3228 int hclge_map_vport_ring_to_vector(struct hclge_vport
*vport
, int vector_id
,
3229 struct hnae3_ring_chain_node
*ring_chain
)
3231 struct hclge_dev
*hdev
= vport
->back
;
3232 struct hclge_ctrl_vector_chain_cmd
*req
;
3233 struct hnae3_ring_chain_node
*node
;
3234 struct hclge_desc desc
;
3238 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_ADD_RING_TO_VECTOR
, false);
3240 req
= (struct hclge_ctrl_vector_chain_cmd
*)desc
.data
;
3241 req
->int_vector_id
= vector_id
;
3244 for (node
= ring_chain
; node
; node
= node
->next
) {
3245 u16 type_and_id
= 0;
3247 hnae_set_field(type_and_id
, HCLGE_INT_TYPE_M
, HCLGE_INT_TYPE_S
,
3248 hnae_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
3249 hnae_set_field(type_and_id
, HCLGE_TQP_ID_M
, HCLGE_TQP_ID_S
,
3251 hnae_set_field(type_and_id
, HCLGE_INT_GL_IDX_M
,
3253 hnae_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
3254 req
->tqp_type_and_id
[i
] = cpu_to_le16(type_and_id
);
3255 req
->vfid
= vport
->vport_id
;
3257 if (++i
>= HCLGE_VECTOR_ELEMENTS_PER_CMD
) {
3258 req
->int_cause_num
= HCLGE_VECTOR_ELEMENTS_PER_CMD
;
3260 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3262 dev_err(&hdev
->pdev
->dev
,
3263 "Map TQP fail, status is %d.\n",
3269 hclge_cmd_setup_basic_desc(&desc
,
3270 HCLGE_OPC_ADD_RING_TO_VECTOR
,
3272 req
->int_vector_id
= vector_id
;
3277 req
->int_cause_num
= i
;
3279 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3281 dev_err(&hdev
->pdev
->dev
,
3282 "Map TQP fail, status is %d.\n", ret
);
3290 static int hclge_map_handle_ring_to_vector(
3291 struct hnae3_handle
*handle
, int vector
,
3292 struct hnae3_ring_chain_node
*ring_chain
)
3294 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3295 struct hclge_dev
*hdev
= vport
->back
;
3298 vector_id
= hclge_get_vector_index(hdev
, vector
);
3299 if (vector_id
< 0) {
3300 dev_err(&hdev
->pdev
->dev
,
3301 "Get vector index fail. ret =%d\n", vector_id
);
3305 return hclge_map_vport_ring_to_vector(vport
, vector_id
, ring_chain
);
3308 static int hclge_unmap_ring_from_vector(
3309 struct hnae3_handle
*handle
, int vector
,
3310 struct hnae3_ring_chain_node
*ring_chain
)
3312 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3313 struct hclge_dev
*hdev
= vport
->back
;
3314 struct hclge_ctrl_vector_chain_cmd
*req
;
3315 struct hnae3_ring_chain_node
*node
;
3316 struct hclge_desc desc
;
3320 vector_id
= hclge_get_vector_index(hdev
, vector
);
3321 if (vector_id
< 0) {
3322 dev_err(&handle
->pdev
->dev
,
3323 "Get vector index fail. ret =%d\n", vector_id
);
3327 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_DEL_RING_TO_VECTOR
, false);
3329 req
= (struct hclge_ctrl_vector_chain_cmd
*)desc
.data
;
3330 req
->int_vector_id
= vector_id
;
3333 for (node
= ring_chain
; node
; node
= node
->next
) {
3334 u16 type_and_id
= 0;
3336 hnae_set_field(type_and_id
, HCLGE_INT_TYPE_M
, HCLGE_INT_TYPE_S
,
3337 hnae_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
3338 hnae_set_field(type_and_id
, HCLGE_TQP_ID_M
, HCLGE_TQP_ID_S
,
3340 hnae_set_field(type_and_id
, HCLGE_INT_GL_IDX_M
,
3342 hnae_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
3344 req
->tqp_type_and_id
[i
] = cpu_to_le16(type_and_id
);
3345 req
->vfid
= vport
->vport_id
;
3347 if (++i
>= HCLGE_VECTOR_ELEMENTS_PER_CMD
) {
3348 req
->int_cause_num
= HCLGE_VECTOR_ELEMENTS_PER_CMD
;
3350 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3352 dev_err(&hdev
->pdev
->dev
,
3353 "Unmap TQP fail, status is %d.\n",
3358 hclge_cmd_setup_basic_desc(&desc
,
3359 HCLGE_OPC_DEL_RING_TO_VECTOR
,
3361 req
->int_vector_id
= vector_id
;
3366 req
->int_cause_num
= i
;
3368 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3370 dev_err(&hdev
->pdev
->dev
,
3371 "Unmap TQP fail, status is %d.\n", ret
);
3379 int hclge_cmd_set_promisc_mode(struct hclge_dev
*hdev
,
3380 struct hclge_promisc_param
*param
)
3382 struct hclge_promisc_cfg_cmd
*req
;
3383 struct hclge_desc desc
;
3386 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_PROMISC_MODE
, false);
3388 req
= (struct hclge_promisc_cfg_cmd
*)desc
.data
;
3389 req
->vf_id
= param
->vf_id
;
3390 req
->flag
= (param
->enable
<< HCLGE_PROMISC_EN_B
);
3392 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3394 dev_err(&hdev
->pdev
->dev
,
3395 "Set promisc mode fail, status is %d.\n", ret
);
3401 void hclge_promisc_param_init(struct hclge_promisc_param
*param
, bool en_uc
,
3402 bool en_mc
, bool en_bc
, int vport_id
)
3407 memset(param
, 0, sizeof(struct hclge_promisc_param
));
3409 param
->enable
= HCLGE_PROMISC_EN_UC
;
3411 param
->enable
|= HCLGE_PROMISC_EN_MC
;
3413 param
->enable
|= HCLGE_PROMISC_EN_BC
;
3414 param
->vf_id
= vport_id
;
3417 static void hclge_set_promisc_mode(struct hnae3_handle
*handle
, u32 en
)
3419 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3420 struct hclge_dev
*hdev
= vport
->back
;
3421 struct hclge_promisc_param param
;
3423 hclge_promisc_param_init(¶m
, en
, en
, true, vport
->vport_id
);
3424 hclge_cmd_set_promisc_mode(hdev
, ¶m
);
3427 static void hclge_cfg_mac_mode(struct hclge_dev
*hdev
, bool enable
)
3429 struct hclge_desc desc
;
3430 struct hclge_config_mac_mode_cmd
*req
=
3431 (struct hclge_config_mac_mode_cmd
*)desc
.data
;
3435 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAC_MODE
, false);
3436 hnae_set_bit(loop_en
, HCLGE_MAC_TX_EN_B
, enable
);
3437 hnae_set_bit(loop_en
, HCLGE_MAC_RX_EN_B
, enable
);
3438 hnae_set_bit(loop_en
, HCLGE_MAC_PAD_TX_B
, enable
);
3439 hnae_set_bit(loop_en
, HCLGE_MAC_PAD_RX_B
, enable
);
3440 hnae_set_bit(loop_en
, HCLGE_MAC_1588_TX_B
, 0);
3441 hnae_set_bit(loop_en
, HCLGE_MAC_1588_RX_B
, 0);
3442 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 0);
3443 hnae_set_bit(loop_en
, HCLGE_MAC_LINE_LP_B
, 0);
3444 hnae_set_bit(loop_en
, HCLGE_MAC_FCS_TX_B
, enable
);
3445 hnae_set_bit(loop_en
, HCLGE_MAC_RX_FCS_B
, enable
);
3446 hnae_set_bit(loop_en
, HCLGE_MAC_RX_FCS_STRIP_B
, enable
);
3447 hnae_set_bit(loop_en
, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B
, enable
);
3448 hnae_set_bit(loop_en
, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B
, enable
);
3449 hnae_set_bit(loop_en
, HCLGE_MAC_TX_UNDER_MIN_ERR_B
, enable
);
3450 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3452 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3454 dev_err(&hdev
->pdev
->dev
,
3455 "mac enable fail, ret =%d.\n", ret
);
3458 static int hclge_set_loopback(struct hnae3_handle
*handle
,
3459 enum hnae3_loop loop_mode
, bool en
)
3461 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3462 struct hclge_config_mac_mode_cmd
*req
;
3463 struct hclge_dev
*hdev
= vport
->back
;
3464 struct hclge_desc desc
;
3468 switch (loop_mode
) {
3469 case HNAE3_MAC_INTER_LOOP_MAC
:
3470 req
= (struct hclge_config_mac_mode_cmd
*)&desc
.data
[0];
3471 /* 1 Read out the MAC mode config at first */
3472 hclge_cmd_setup_basic_desc(&desc
,
3473 HCLGE_OPC_CONFIG_MAC_MODE
,
3475 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3477 dev_err(&hdev
->pdev
->dev
,
3478 "mac loopback get fail, ret =%d.\n",
3483 /* 2 Then setup the loopback flag */
3484 loop_en
= le32_to_cpu(req
->txrx_pad_fcs_loop_en
);
3486 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 1);
3488 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 0);
3490 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3492 /* 3 Config mac work mode with loopback flag
3493 * and its original configure parameters
3495 hclge_cmd_reuse_desc(&desc
, false);
3496 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3498 dev_err(&hdev
->pdev
->dev
,
3499 "mac loopback set fail, ret =%d.\n", ret
);
3503 dev_err(&hdev
->pdev
->dev
,
3504 "loop_mode %d is not supported\n", loop_mode
);
3511 static int hclge_tqp_enable(struct hclge_dev
*hdev
, int tqp_id
,
3512 int stream_id
, bool enable
)
3514 struct hclge_desc desc
;
3515 struct hclge_cfg_com_tqp_queue_cmd
*req
=
3516 (struct hclge_cfg_com_tqp_queue_cmd
*)desc
.data
;
3519 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_COM_TQP_QUEUE
, false);
3520 req
->tqp_id
= cpu_to_le16(tqp_id
& HCLGE_RING_ID_MASK
);
3521 req
->stream_id
= cpu_to_le16(stream_id
);
3522 req
->enable
|= enable
<< HCLGE_TQP_ENABLE_B
;
3524 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3526 dev_err(&hdev
->pdev
->dev
,
3527 "Tqp enable fail, status =%d.\n", ret
);
3531 static void hclge_reset_tqp_stats(struct hnae3_handle
*handle
)
3533 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3534 struct hnae3_queue
*queue
;
3535 struct hclge_tqp
*tqp
;
3538 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
3539 queue
= handle
->kinfo
.tqp
[i
];
3540 tqp
= container_of(queue
, struct hclge_tqp
, q
);
3541 memset(&tqp
->tqp_stats
, 0, sizeof(tqp
->tqp_stats
));
3545 static int hclge_ae_start(struct hnae3_handle
*handle
)
3547 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3548 struct hclge_dev
*hdev
= vport
->back
;
3549 int i
, queue_id
, ret
;
3551 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
3552 /* todo clear interrupt */
3554 queue_id
= hclge_get_queue_id(handle
->kinfo
.tqp
[i
]);
3556 dev_warn(&hdev
->pdev
->dev
,
3557 "Get invalid queue id, ignore it\n");
3561 hclge_tqp_enable(hdev
, queue_id
, 0, true);
3564 hclge_cfg_mac_mode(hdev
, true);
3565 clear_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
3566 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
3568 ret
= hclge_mac_start_phy(hdev
);
3572 /* reset tqp stats */
3573 hclge_reset_tqp_stats(handle
);
3578 static void hclge_ae_stop(struct hnae3_handle
*handle
)
3580 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3581 struct hclge_dev
*hdev
= vport
->back
;
3584 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
3586 queue_id
= hclge_get_queue_id(handle
->kinfo
.tqp
[i
]);
3588 dev_warn(&hdev
->pdev
->dev
,
3589 "Get invalid queue id, ignore it\n");
3593 hclge_tqp_enable(hdev
, queue_id
, 0, false);
3596 hclge_cfg_mac_mode(hdev
, false);
3598 hclge_mac_stop_phy(hdev
);
3600 /* reset tqp stats */
3601 hclge_reset_tqp_stats(handle
);
3604 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport
*vport
,
3605 u16 cmdq_resp
, u8 resp_code
,
3606 enum hclge_mac_vlan_tbl_opcode op
)
3608 struct hclge_dev
*hdev
= vport
->back
;
3609 int return_status
= -EIO
;
3612 dev_err(&hdev
->pdev
->dev
,
3613 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3618 if (op
== HCLGE_MAC_VLAN_ADD
) {
3619 if ((!resp_code
) || (resp_code
== 1)) {
3621 } else if (resp_code
== 2) {
3622 return_status
= -EIO
;
3623 dev_err(&hdev
->pdev
->dev
,
3624 "add mac addr failed for uc_overflow.\n");
3625 } else if (resp_code
== 3) {
3626 return_status
= -EIO
;
3627 dev_err(&hdev
->pdev
->dev
,
3628 "add mac addr failed for mc_overflow.\n");
3630 dev_err(&hdev
->pdev
->dev
,
3631 "add mac addr failed for undefined, code=%d.\n",
3634 } else if (op
== HCLGE_MAC_VLAN_REMOVE
) {
3637 } else if (resp_code
== 1) {
3638 return_status
= -EIO
;
3639 dev_dbg(&hdev
->pdev
->dev
,
3640 "remove mac addr failed for miss.\n");
3642 dev_err(&hdev
->pdev
->dev
,
3643 "remove mac addr failed for undefined, code=%d.\n",
3646 } else if (op
== HCLGE_MAC_VLAN_LKUP
) {
3649 } else if (resp_code
== 1) {
3650 return_status
= -EIO
;
3651 dev_dbg(&hdev
->pdev
->dev
,
3652 "lookup mac addr failed for miss.\n");
3654 dev_err(&hdev
->pdev
->dev
,
3655 "lookup mac addr failed for undefined, code=%d.\n",
3659 return_status
= -EIO
;
3660 dev_err(&hdev
->pdev
->dev
,
3661 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3665 return return_status
;
3668 static int hclge_update_desc_vfid(struct hclge_desc
*desc
, int vfid
, bool clr
)
3673 if (vfid
> 255 || vfid
< 0)
3676 if (vfid
>= 0 && vfid
<= 191) {
3677 word_num
= vfid
/ 32;
3678 bit_num
= vfid
% 32;
3680 desc
[1].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3682 desc
[1].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3684 word_num
= (vfid
- 192) / 32;
3685 bit_num
= vfid
% 32;
3687 desc
[2].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3689 desc
[2].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3695 static bool hclge_is_all_function_id_zero(struct hclge_desc
*desc
)
3697 #define HCLGE_DESC_NUMBER 3
3698 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3701 for (i
= 0; i
< HCLGE_DESC_NUMBER
; i
++)
3702 for (j
= 0; j
< HCLGE_FUNC_NUMBER_PER_DESC
; j
++)
3703 if (desc
[i
].data
[j
])
3709 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd
*new_req
,
3712 const unsigned char *mac_addr
= addr
;
3713 u32 high_val
= mac_addr
[2] << 16 | (mac_addr
[3] << 24) |
3714 (mac_addr
[0]) | (mac_addr
[1] << 8);
3715 u32 low_val
= mac_addr
[4] | (mac_addr
[5] << 8);
3717 new_req
->mac_addr_hi32
= cpu_to_le32(high_val
);
3718 new_req
->mac_addr_lo16
= cpu_to_le16(low_val
& 0xffff);
3721 static u16
hclge_get_mac_addr_to_mta_index(struct hclge_vport
*vport
,
3724 u16 high_val
= addr
[1] | (addr
[0] << 8);
3725 struct hclge_dev
*hdev
= vport
->back
;
3726 u32 rsh
= 4 - hdev
->mta_mac_sel_type
;
3727 u16 ret_val
= (high_val
>> rsh
) & 0xfff;
3732 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
3733 enum hclge_mta_dmac_sel_type mta_mac_sel
,
3736 struct hclge_mta_filter_mode_cmd
*req
;
3737 struct hclge_desc desc
;
3740 req
= (struct hclge_mta_filter_mode_cmd
*)desc
.data
;
3741 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_MODE_CFG
, false);
3743 hnae_set_bit(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_EN_B
,
3745 hnae_set_field(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_SEL_M
,
3746 HCLGE_CFG_MTA_MAC_SEL_S
, mta_mac_sel
);
3748 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3750 dev_err(&hdev
->pdev
->dev
,
3751 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3759 int hclge_cfg_func_mta_filter(struct hclge_dev
*hdev
,
3763 struct hclge_cfg_func_mta_filter_cmd
*req
;
3764 struct hclge_desc desc
;
3767 req
= (struct hclge_cfg_func_mta_filter_cmd
*)desc
.data
;
3768 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_FUNC_CFG
, false);
3770 hnae_set_bit(req
->accept
, HCLGE_CFG_FUNC_MTA_ACCEPT_B
,
3772 req
->function_id
= func_id
;
3774 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3776 dev_err(&hdev
->pdev
->dev
,
3777 "Config func_id enable failed for cmd_send, ret =%d.\n",
3785 static int hclge_set_mta_table_item(struct hclge_vport
*vport
,
3789 struct hclge_dev
*hdev
= vport
->back
;
3790 struct hclge_cfg_func_mta_item_cmd
*req
;
3791 struct hclge_desc desc
;
3795 req
= (struct hclge_cfg_func_mta_item_cmd
*)desc
.data
;
3796 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_TBL_ITEM_CFG
, false);
3797 hnae_set_bit(req
->accept
, HCLGE_CFG_MTA_ITEM_ACCEPT_B
, enable
);
3799 hnae_set_field(item_idx
, HCLGE_CFG_MTA_ITEM_IDX_M
,
3800 HCLGE_CFG_MTA_ITEM_IDX_S
, idx
);
3801 req
->item_idx
= cpu_to_le16(item_idx
);
3803 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3805 dev_err(&hdev
->pdev
->dev
,
3806 "Config mta table item failed for cmd_send, ret =%d.\n",
3814 static int hclge_remove_mac_vlan_tbl(struct hclge_vport
*vport
,
3815 struct hclge_mac_vlan_tbl_entry_cmd
*req
)
3817 struct hclge_dev
*hdev
= vport
->back
;
3818 struct hclge_desc desc
;
3823 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_REMOVE
, false);
3825 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
3827 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3829 dev_err(&hdev
->pdev
->dev
,
3830 "del mac addr failed for cmd_send, ret =%d.\n",
3834 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
3835 retval
= le16_to_cpu(desc
.retval
);
3837 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
3838 HCLGE_MAC_VLAN_REMOVE
);
3841 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport
*vport
,
3842 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
3843 struct hclge_desc
*desc
,
3846 struct hclge_dev
*hdev
= vport
->back
;
3851 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_MAC_VLAN_ADD
, true);
3853 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
3854 memcpy(desc
[0].data
,
3856 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
3857 hclge_cmd_setup_basic_desc(&desc
[1],
3858 HCLGE_OPC_MAC_VLAN_ADD
,
3860 desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
3861 hclge_cmd_setup_basic_desc(&desc
[2],
3862 HCLGE_OPC_MAC_VLAN_ADD
,
3864 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 3);
3866 memcpy(desc
[0].data
,
3868 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
3869 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
3872 dev_err(&hdev
->pdev
->dev
,
3873 "lookup mac addr failed for cmd_send, ret =%d.\n",
3877 resp_code
= (le32_to_cpu(desc
[0].data
[0]) >> 8) & 0xff;
3878 retval
= le16_to_cpu(desc
[0].retval
);
3880 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
3881 HCLGE_MAC_VLAN_LKUP
);
3884 static int hclge_add_mac_vlan_tbl(struct hclge_vport
*vport
,
3885 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
3886 struct hclge_desc
*mc_desc
)
3888 struct hclge_dev
*hdev
= vport
->back
;
3895 struct hclge_desc desc
;
3897 hclge_cmd_setup_basic_desc(&desc
,
3898 HCLGE_OPC_MAC_VLAN_ADD
,
3900 memcpy(desc
.data
, req
,
3901 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
3902 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3903 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
3904 retval
= le16_to_cpu(desc
.retval
);
3906 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
3908 HCLGE_MAC_VLAN_ADD
);
3910 hclge_cmd_reuse_desc(&mc_desc
[0], false);
3911 mc_desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
3912 hclge_cmd_reuse_desc(&mc_desc
[1], false);
3913 mc_desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
3914 hclge_cmd_reuse_desc(&mc_desc
[2], false);
3915 mc_desc
[2].flag
&= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT
);
3916 memcpy(mc_desc
[0].data
, req
,
3917 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
3918 ret
= hclge_cmd_send(&hdev
->hw
, mc_desc
, 3);
3919 resp_code
= (le32_to_cpu(mc_desc
[0].data
[0]) >> 8) & 0xff;
3920 retval
= le16_to_cpu(mc_desc
[0].retval
);
3922 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
3924 HCLGE_MAC_VLAN_ADD
);
3928 dev_err(&hdev
->pdev
->dev
,
3929 "add mac addr failed for cmd_send, ret =%d.\n",
3937 static int hclge_add_uc_addr(struct hnae3_handle
*handle
,
3938 const unsigned char *addr
)
3940 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3942 return hclge_add_uc_addr_common(vport
, addr
);
3945 int hclge_add_uc_addr_common(struct hclge_vport
*vport
,
3946 const unsigned char *addr
)
3948 struct hclge_dev
*hdev
= vport
->back
;
3949 struct hclge_mac_vlan_tbl_entry_cmd req
;
3950 enum hclge_cmd_status status
;
3951 u16 egress_port
= 0;
3953 /* mac addr check */
3954 if (is_zero_ether_addr(addr
) ||
3955 is_broadcast_ether_addr(addr
) ||
3956 is_multicast_ether_addr(addr
)) {
3957 dev_err(&hdev
->pdev
->dev
,
3958 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
3960 is_zero_ether_addr(addr
),
3961 is_broadcast_ether_addr(addr
),
3962 is_multicast_ether_addr(addr
));
3966 memset(&req
, 0, sizeof(req
));
3967 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
3968 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
3969 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 0);
3970 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
3972 hnae_set_bit(egress_port
, HCLGE_MAC_EPORT_SW_EN_B
, 0);
3973 hnae_set_bit(egress_port
, HCLGE_MAC_EPORT_TYPE_B
, 0);
3974 hnae_set_field(egress_port
, HCLGE_MAC_EPORT_VFID_M
,
3975 HCLGE_MAC_EPORT_VFID_S
, vport
->vport_id
);
3976 hnae_set_field(egress_port
, HCLGE_MAC_EPORT_PFID_M
,
3977 HCLGE_MAC_EPORT_PFID_S
, 0);
3979 req
.egress_port
= cpu_to_le16(egress_port
);
3981 hclge_prepare_mac_addr(&req
, addr
);
3983 status
= hclge_add_mac_vlan_tbl(vport
, &req
, NULL
);
3988 static int hclge_rm_uc_addr(struct hnae3_handle
*handle
,
3989 const unsigned char *addr
)
3991 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3993 return hclge_rm_uc_addr_common(vport
, addr
);
3996 int hclge_rm_uc_addr_common(struct hclge_vport
*vport
,
3997 const unsigned char *addr
)
3999 struct hclge_dev
*hdev
= vport
->back
;
4000 struct hclge_mac_vlan_tbl_entry_cmd req
;
4001 enum hclge_cmd_status status
;
4003 /* mac addr check */
4004 if (is_zero_ether_addr(addr
) ||
4005 is_broadcast_ether_addr(addr
) ||
4006 is_multicast_ether_addr(addr
)) {
4007 dev_dbg(&hdev
->pdev
->dev
,
4008 "Remove mac err! invalid mac:%pM.\n",
4013 memset(&req
, 0, sizeof(req
));
4014 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4015 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4016 hclge_prepare_mac_addr(&req
, addr
);
4017 status
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4022 static int hclge_add_mc_addr(struct hnae3_handle
*handle
,
4023 const unsigned char *addr
)
4025 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4027 return hclge_add_mc_addr_common(vport
, addr
);
4030 int hclge_add_mc_addr_common(struct hclge_vport
*vport
,
4031 const unsigned char *addr
)
4033 struct hclge_dev
*hdev
= vport
->back
;
4034 struct hclge_mac_vlan_tbl_entry_cmd req
;
4035 struct hclge_desc desc
[3];
4039 /* mac addr check */
4040 if (!is_multicast_ether_addr(addr
)) {
4041 dev_err(&hdev
->pdev
->dev
,
4042 "Add mc mac err! invalid mac:%pM.\n",
4046 memset(&req
, 0, sizeof(req
));
4047 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4048 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4049 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4050 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4051 hclge_prepare_mac_addr(&req
, addr
);
4052 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4054 /* This mac addr exist, update VFID for it */
4055 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4056 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4058 /* This mac addr do not exist, add new entry for it */
4059 memset(desc
[0].data
, 0, sizeof(desc
[0].data
));
4060 memset(desc
[1].data
, 0, sizeof(desc
[0].data
));
4061 memset(desc
[2].data
, 0, sizeof(desc
[0].data
));
4062 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4063 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4066 /* Set MTA table for this MAC address */
4067 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
4068 status
= hclge_set_mta_table_item(vport
, tbl_idx
, true);
4073 static int hclge_rm_mc_addr(struct hnae3_handle
*handle
,
4074 const unsigned char *addr
)
4076 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4078 return hclge_rm_mc_addr_common(vport
, addr
);
4081 int hclge_rm_mc_addr_common(struct hclge_vport
*vport
,
4082 const unsigned char *addr
)
4084 struct hclge_dev
*hdev
= vport
->back
;
4085 struct hclge_mac_vlan_tbl_entry_cmd req
;
4086 enum hclge_cmd_status status
;
4087 struct hclge_desc desc
[3];
4090 /* mac addr check */
4091 if (!is_multicast_ether_addr(addr
)) {
4092 dev_dbg(&hdev
->pdev
->dev
,
4093 "Remove mc mac err! invalid mac:%pM.\n",
4098 memset(&req
, 0, sizeof(req
));
4099 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4100 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4101 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4102 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4103 hclge_prepare_mac_addr(&req
, addr
);
4104 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4106 /* This mac addr exist, remove this handle's VFID for it */
4107 hclge_update_desc_vfid(desc
, vport
->vport_id
, true);
4109 if (hclge_is_all_function_id_zero(desc
))
4110 /* All the vfid is zero, so need to delete this entry */
4111 status
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4113 /* Not all the vfid is zero, update the vfid */
4114 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4117 /* This mac addr do not exist, can't delete it */
4118 dev_err(&hdev
->pdev
->dev
,
4119 "Rm multicast mac addr failed, ret = %d.\n",
4124 /* Set MTB table for this MAC address */
4125 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
4126 status
= hclge_set_mta_table_item(vport
, tbl_idx
, false);
4131 static void hclge_get_mac_addr(struct hnae3_handle
*handle
, u8
*p
)
4133 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4134 struct hclge_dev
*hdev
= vport
->back
;
4136 ether_addr_copy(p
, hdev
->hw
.mac
.mac_addr
);
4139 static int hclge_set_mac_addr(struct hnae3_handle
*handle
, void *p
)
4141 const unsigned char *new_addr
= (const unsigned char *)p
;
4142 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4143 struct hclge_dev
*hdev
= vport
->back
;
4145 /* mac addr check */
4146 if (is_zero_ether_addr(new_addr
) ||
4147 is_broadcast_ether_addr(new_addr
) ||
4148 is_multicast_ether_addr(new_addr
)) {
4149 dev_err(&hdev
->pdev
->dev
,
4150 "Change uc mac err! invalid mac:%p.\n",
4155 hclge_rm_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
);
4157 if (!hclge_add_uc_addr(handle
, new_addr
)) {
4158 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, new_addr
);
4165 static int hclge_set_vlan_filter_ctrl(struct hclge_dev
*hdev
, u8 vlan_type
,
4168 struct hclge_vlan_filter_ctrl_cmd
*req
;
4169 struct hclge_desc desc
;
4172 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_CTRL
, false);
4174 req
= (struct hclge_vlan_filter_ctrl_cmd
*)desc
.data
;
4175 req
->vlan_type
= vlan_type
;
4176 req
->vlan_fe
= filter_en
;
4178 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4180 dev_err(&hdev
->pdev
->dev
, "set vlan filter fail, ret =%d.\n",
4188 int hclge_set_vf_vlan_common(struct hclge_dev
*hdev
, int vfid
,
4189 bool is_kill
, u16 vlan
, u8 qos
, __be16 proto
)
4191 #define HCLGE_MAX_VF_BYTES 16
4192 struct hclge_vlan_filter_vf_cfg_cmd
*req0
;
4193 struct hclge_vlan_filter_vf_cfg_cmd
*req1
;
4194 struct hclge_desc desc
[2];
4199 hclge_cmd_setup_basic_desc(&desc
[0],
4200 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4201 hclge_cmd_setup_basic_desc(&desc
[1],
4202 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4204 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4206 vf_byte_off
= vfid
/ 8;
4207 vf_byte_val
= 1 << (vfid
% 8);
4209 req0
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[0].data
;
4210 req1
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[1].data
;
4212 req0
->vlan_id
= cpu_to_le16(vlan
);
4213 req0
->vlan_cfg
= is_kill
;
4215 if (vf_byte_off
< HCLGE_MAX_VF_BYTES
)
4216 req0
->vf_bitmap
[vf_byte_off
] = vf_byte_val
;
4218 req1
->vf_bitmap
[vf_byte_off
- HCLGE_MAX_VF_BYTES
] = vf_byte_val
;
4220 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
4222 dev_err(&hdev
->pdev
->dev
,
4223 "Send vf vlan command fail, ret =%d.\n",
4229 if (!req0
->resp_code
|| req0
->resp_code
== 1)
4232 dev_err(&hdev
->pdev
->dev
,
4233 "Add vf vlan filter fail, ret =%d.\n",
4236 if (!req0
->resp_code
)
4239 dev_err(&hdev
->pdev
->dev
,
4240 "Kill vf vlan filter fail, ret =%d.\n",
4247 static int hclge_set_port_vlan_filter(struct hnae3_handle
*handle
,
4248 __be16 proto
, u16 vlan_id
,
4251 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4252 struct hclge_dev
*hdev
= vport
->back
;
4253 struct hclge_vlan_filter_pf_cfg_cmd
*req
;
4254 struct hclge_desc desc
;
4255 u8 vlan_offset_byte_val
;
4256 u8 vlan_offset_byte
;
4260 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_PF_CFG
, false);
4262 vlan_offset_160
= vlan_id
/ 160;
4263 vlan_offset_byte
= (vlan_id
% 160) / 8;
4264 vlan_offset_byte_val
= 1 << (vlan_id
% 8);
4266 req
= (struct hclge_vlan_filter_pf_cfg_cmd
*)desc
.data
;
4267 req
->vlan_offset
= vlan_offset_160
;
4268 req
->vlan_cfg
= is_kill
;
4269 req
->vlan_offset_bitmap
[vlan_offset_byte
] = vlan_offset_byte_val
;
4271 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4273 dev_err(&hdev
->pdev
->dev
,
4274 "port vlan command, send fail, ret =%d.\n",
4279 ret
= hclge_set_vf_vlan_common(hdev
, 0, is_kill
, vlan_id
, 0, proto
);
4281 dev_err(&hdev
->pdev
->dev
,
4282 "Set pf vlan filter config fail, ret =%d.\n",
4290 static int hclge_set_vf_vlan_filter(struct hnae3_handle
*handle
, int vfid
,
4291 u16 vlan
, u8 qos
, __be16 proto
)
4293 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4294 struct hclge_dev
*hdev
= vport
->back
;
4296 if ((vfid
>= hdev
->num_alloc_vfs
) || (vlan
> 4095) || (qos
> 7))
4298 if (proto
!= htons(ETH_P_8021Q
))
4299 return -EPROTONOSUPPORT
;
4301 return hclge_set_vf_vlan_common(hdev
, vfid
, false, vlan
, qos
, proto
);
4304 static int hclge_init_vlan_config(struct hclge_dev
*hdev
)
4306 #define HCLGE_VLAN_TYPE_VF_TABLE 0
4307 #define HCLGE_VLAN_TYPE_PORT_TABLE 1
4308 struct hnae3_handle
*handle
;
4311 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_VLAN_TYPE_VF_TABLE
,
4316 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_VLAN_TYPE_PORT_TABLE
,
4321 handle
= &hdev
->vport
[0].nic
;
4322 return hclge_set_port_vlan_filter(handle
, htons(ETH_P_8021Q
), 0, false);
4325 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
)
4327 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4328 struct hclge_config_max_frm_size_cmd
*req
;
4329 struct hclge_dev
*hdev
= vport
->back
;
4330 struct hclge_desc desc
;
4333 if ((new_mtu
< HCLGE_MAC_MIN_MTU
) || (new_mtu
> HCLGE_MAC_MAX_MTU
))
4336 hdev
->mps
= new_mtu
;
4337 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAX_FRM_SIZE
, false);
4339 req
= (struct hclge_config_max_frm_size_cmd
*)desc
.data
;
4340 req
->max_frm_size
= cpu_to_le16(new_mtu
);
4342 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4344 dev_err(&hdev
->pdev
->dev
, "set mtu fail, ret =%d.\n", ret
);
4351 static int hclge_send_reset_tqp_cmd(struct hclge_dev
*hdev
, u16 queue_id
,
4354 struct hclge_reset_tqp_queue_cmd
*req
;
4355 struct hclge_desc desc
;
4358 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, false);
4360 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
4361 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
4362 hnae_set_bit(req
->reset_req
, HCLGE_TQP_RESET_B
, enable
);
4364 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4366 dev_err(&hdev
->pdev
->dev
,
4367 "Send tqp reset cmd error, status =%d\n", ret
);
4374 static int hclge_get_reset_status(struct hclge_dev
*hdev
, u16 queue_id
)
4376 struct hclge_reset_tqp_queue_cmd
*req
;
4377 struct hclge_desc desc
;
4380 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, true);
4382 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
4383 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
4385 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4387 dev_err(&hdev
->pdev
->dev
,
4388 "Get reset status error, status =%d\n", ret
);
4392 return hnae_get_bit(req
->ready_to_reset
, HCLGE_TQP_RESET_B
);
4395 static void hclge_reset_tqp(struct hnae3_handle
*handle
, u16 queue_id
)
4397 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4398 struct hclge_dev
*hdev
= vport
->back
;
4399 int reset_try_times
= 0;
4403 ret
= hclge_tqp_enable(hdev
, queue_id
, 0, false);
4405 dev_warn(&hdev
->pdev
->dev
, "Disable tqp fail, ret = %d\n", ret
);
4409 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_id
, true);
4411 dev_warn(&hdev
->pdev
->dev
,
4412 "Send reset tqp cmd fail, ret = %d\n", ret
);
4416 reset_try_times
= 0;
4417 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
4418 /* Wait for tqp hw reset */
4420 reset_status
= hclge_get_reset_status(hdev
, queue_id
);
4425 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
4426 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
4430 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_id
, false);
4432 dev_warn(&hdev
->pdev
->dev
,
4433 "Deassert the soft reset fail, ret = %d\n", ret
);
4438 static u32
hclge_get_fw_version(struct hnae3_handle
*handle
)
4440 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4441 struct hclge_dev
*hdev
= vport
->back
;
4443 return hdev
->fw_version
;
4446 static void hclge_get_pauseparam(struct hnae3_handle
*handle
, u32
*auto_neg
,
4447 u32
*rx_en
, u32
*tx_en
)
4449 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4450 struct hclge_dev
*hdev
= vport
->back
;
4452 *auto_neg
= hclge_get_autoneg(handle
);
4454 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
4460 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_RX_PAUSE
) {
4463 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_TX_PAUSE
) {
4466 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_FULL
) {
4475 static void hclge_get_ksettings_an_result(struct hnae3_handle
*handle
,
4476 u8
*auto_neg
, u32
*speed
, u8
*duplex
)
4478 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4479 struct hclge_dev
*hdev
= vport
->back
;
4482 *speed
= hdev
->hw
.mac
.speed
;
4484 *duplex
= hdev
->hw
.mac
.duplex
;
4486 *auto_neg
= hdev
->hw
.mac
.autoneg
;
4489 static void hclge_get_media_type(struct hnae3_handle
*handle
, u8
*media_type
)
4491 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4492 struct hclge_dev
*hdev
= vport
->back
;
4495 *media_type
= hdev
->hw
.mac
.media_type
;
4498 static void hclge_get_mdix_mode(struct hnae3_handle
*handle
,
4499 u8
*tp_mdix_ctrl
, u8
*tp_mdix
)
4501 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4502 struct hclge_dev
*hdev
= vport
->back
;
4503 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
4504 int mdix_ctrl
, mdix
, retval
, is_resolved
;
4507 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
4508 *tp_mdix
= ETH_TP_MDI_INVALID
;
4512 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_MDIX
);
4514 retval
= phy_read(phydev
, HCLGE_PHY_CSC_REG
);
4515 mdix_ctrl
= hnae_get_field(retval
, HCLGE_PHY_MDIX_CTRL_M
,
4516 HCLGE_PHY_MDIX_CTRL_S
);
4518 retval
= phy_read(phydev
, HCLGE_PHY_CSS_REG
);
4519 mdix
= hnae_get_bit(retval
, HCLGE_PHY_MDIX_STATUS_B
);
4520 is_resolved
= hnae_get_bit(retval
, HCLGE_PHY_SPEED_DUP_RESOLVE_B
);
4522 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_COPPER
);
4524 switch (mdix_ctrl
) {
4526 *tp_mdix_ctrl
= ETH_TP_MDI
;
4529 *tp_mdix_ctrl
= ETH_TP_MDI_X
;
4532 *tp_mdix_ctrl
= ETH_TP_MDI_AUTO
;
4535 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
4540 *tp_mdix
= ETH_TP_MDI_INVALID
;
4542 *tp_mdix
= ETH_TP_MDI_X
;
4544 *tp_mdix
= ETH_TP_MDI
;
4547 static int hclge_init_client_instance(struct hnae3_client
*client
,
4548 struct hnae3_ae_dev
*ae_dev
)
4550 struct hclge_dev
*hdev
= ae_dev
->priv
;
4551 struct hclge_vport
*vport
;
4554 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
4555 vport
= &hdev
->vport
[i
];
4557 switch (client
->type
) {
4558 case HNAE3_CLIENT_KNIC
:
4560 hdev
->nic_client
= client
;
4561 vport
->nic
.client
= client
;
4562 ret
= client
->ops
->init_instance(&vport
->nic
);
4566 if (hdev
->roce_client
&&
4567 hnae3_dev_roce_supported(hdev
)) {
4568 struct hnae3_client
*rc
= hdev
->roce_client
;
4570 ret
= hclge_init_roce_base_info(vport
);
4574 ret
= rc
->ops
->init_instance(&vport
->roce
);
4580 case HNAE3_CLIENT_UNIC
:
4581 hdev
->nic_client
= client
;
4582 vport
->nic
.client
= client
;
4584 ret
= client
->ops
->init_instance(&vport
->nic
);
4589 case HNAE3_CLIENT_ROCE
:
4590 if (hnae3_dev_roce_supported(hdev
)) {
4591 hdev
->roce_client
= client
;
4592 vport
->roce
.client
= client
;
4595 if (hdev
->roce_client
&& hdev
->nic_client
) {
4596 ret
= hclge_init_roce_base_info(vport
);
4600 ret
= client
->ops
->init_instance(&vport
->roce
);
4612 static void hclge_uninit_client_instance(struct hnae3_client
*client
,
4613 struct hnae3_ae_dev
*ae_dev
)
4615 struct hclge_dev
*hdev
= ae_dev
->priv
;
4616 struct hclge_vport
*vport
;
4619 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
4620 vport
= &hdev
->vport
[i
];
4621 if (hdev
->roce_client
) {
4622 hdev
->roce_client
->ops
->uninit_instance(&vport
->roce
,
4624 hdev
->roce_client
= NULL
;
4625 vport
->roce
.client
= NULL
;
4627 if (client
->type
== HNAE3_CLIENT_ROCE
)
4629 if (client
->ops
->uninit_instance
) {
4630 client
->ops
->uninit_instance(&vport
->nic
, 0);
4631 hdev
->nic_client
= NULL
;
4632 vport
->nic
.client
= NULL
;
4637 static int hclge_pci_init(struct hclge_dev
*hdev
)
4639 struct pci_dev
*pdev
= hdev
->pdev
;
4640 struct hclge_hw
*hw
;
4643 ret
= pci_enable_device(pdev
);
4645 dev_err(&pdev
->dev
, "failed to enable PCI device\n");
4646 goto err_no_drvdata
;
4649 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64));
4651 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32));
4654 "can't set consistent PCI DMA");
4655 goto err_disable_device
;
4657 dev_warn(&pdev
->dev
, "set DMA mask to 32 bits\n");
4660 ret
= pci_request_regions(pdev
, HCLGE_DRIVER_NAME
);
4662 dev_err(&pdev
->dev
, "PCI request regions failed %d\n", ret
);
4663 goto err_disable_device
;
4666 pci_set_master(pdev
);
4669 hw
->io_base
= pcim_iomap(pdev
, 2, 0);
4671 dev_err(&pdev
->dev
, "Can't map configuration register space\n");
4673 goto err_clr_master
;
4676 hdev
->num_req_vfs
= pci_sriov_get_totalvfs(pdev
);
4680 pci_clear_master(pdev
);
4681 pci_release_regions(pdev
);
4683 pci_disable_device(pdev
);
4685 pci_set_drvdata(pdev
, NULL
);
4690 static void hclge_pci_uninit(struct hclge_dev
*hdev
)
4692 struct pci_dev
*pdev
= hdev
->pdev
;
4694 pci_free_irq_vectors(pdev
);
4695 pci_clear_master(pdev
);
4696 pci_release_mem_regions(pdev
);
4697 pci_disable_device(pdev
);
4700 static int hclge_init_ae_dev(struct hnae3_ae_dev
*ae_dev
)
4702 struct pci_dev
*pdev
= ae_dev
->pdev
;
4703 struct hclge_dev
*hdev
;
4706 hdev
= devm_kzalloc(&pdev
->dev
, sizeof(*hdev
), GFP_KERNEL
);
4713 hdev
->ae_dev
= ae_dev
;
4714 hdev
->reset_type
= HNAE3_NONE_RESET
;
4715 hdev
->reset_request
= 0;
4716 hdev
->reset_pending
= 0;
4717 ae_dev
->priv
= hdev
;
4719 ret
= hclge_pci_init(hdev
);
4721 dev_err(&pdev
->dev
, "PCI init failed\n");
4725 /* Firmware command queue initialize */
4726 ret
= hclge_cmd_queue_init(hdev
);
4728 dev_err(&pdev
->dev
, "Cmd queue init failed, ret = %d.\n", ret
);
4732 /* Firmware command initialize */
4733 ret
= hclge_cmd_init(hdev
);
4737 ret
= hclge_get_cap(hdev
);
4739 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
4744 ret
= hclge_configure(hdev
);
4746 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
4750 ret
= hclge_init_msi(hdev
);
4752 dev_err(&pdev
->dev
, "Init MSI/MSI-X error, ret = %d.\n", ret
);
4756 ret
= hclge_misc_irq_init(hdev
);
4759 "Misc IRQ(vector0) init error, ret = %d.\n",
4764 ret
= hclge_alloc_tqps(hdev
);
4766 dev_err(&pdev
->dev
, "Allocate TQPs error, ret = %d.\n", ret
);
4770 ret
= hclge_alloc_vport(hdev
);
4772 dev_err(&pdev
->dev
, "Allocate vport error, ret = %d.\n", ret
);
4776 ret
= hclge_map_tqp(hdev
);
4778 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
4782 ret
= hclge_mac_mdio_config(hdev
);
4784 dev_warn(&hdev
->pdev
->dev
,
4785 "mdio config fail ret=%d\n", ret
);
4789 ret
= hclge_mac_init(hdev
);
4791 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
4794 ret
= hclge_buffer_alloc(hdev
);
4796 dev_err(&pdev
->dev
, "Buffer allocate fail, ret =%d\n", ret
);
4800 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
4802 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
4806 ret
= hclge_init_vlan_config(hdev
);
4808 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
4812 ret
= hclge_tm_schd_init(hdev
);
4814 dev_err(&pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
4818 ret
= hclge_rss_init_hw(hdev
);
4820 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
4824 hclge_dcb_ops_set(hdev
);
4826 timer_setup(&hdev
->service_timer
, hclge_service_timer
, 0);
4827 INIT_WORK(&hdev
->service_task
, hclge_service_task
);
4828 INIT_WORK(&hdev
->rst_service_task
, hclge_reset_service_task
);
4830 /* Enable MISC vector(vector0) */
4831 hclge_enable_vector(&hdev
->misc_vector
, true);
4833 set_bit(HCLGE_STATE_SERVICE_INITED
, &hdev
->state
);
4834 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
4835 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
4836 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
4838 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME
);
4842 pci_release_regions(pdev
);
4844 pci_set_drvdata(pdev
, NULL
);
4849 static void hclge_stats_clear(struct hclge_dev
*hdev
)
4851 memset(&hdev
->hw_stats
, 0, sizeof(hdev
->hw_stats
));
4854 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
)
4856 struct hclge_dev
*hdev
= ae_dev
->priv
;
4857 struct pci_dev
*pdev
= ae_dev
->pdev
;
4860 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
4862 hclge_stats_clear(hdev
);
4864 ret
= hclge_cmd_init(hdev
);
4866 dev_err(&pdev
->dev
, "Cmd queue init failed\n");
4870 ret
= hclge_get_cap(hdev
);
4872 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
4877 ret
= hclge_configure(hdev
);
4879 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
4883 ret
= hclge_map_tqp(hdev
);
4885 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
4889 ret
= hclge_mac_init(hdev
);
4891 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
4895 ret
= hclge_buffer_alloc(hdev
);
4897 dev_err(&pdev
->dev
, "Buffer allocate fail, ret =%d\n", ret
);
4901 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
4903 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
4907 ret
= hclge_init_vlan_config(hdev
);
4909 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
4913 ret
= hclge_tm_schd_init(hdev
);
4915 dev_err(&pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
4919 ret
= hclge_rss_init_hw(hdev
);
4921 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
4925 /* Enable MISC vector(vector0) */
4926 hclge_enable_vector(&hdev
->misc_vector
, true);
4928 dev_info(&pdev
->dev
, "Reset done, %s driver initialization finished.\n",
4934 static void hclge_uninit_ae_dev(struct hnae3_ae_dev
*ae_dev
)
4936 struct hclge_dev
*hdev
= ae_dev
->priv
;
4937 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
4939 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
4941 if (IS_ENABLED(CONFIG_PCI_IOV
))
4942 hclge_disable_sriov(hdev
);
4944 if (hdev
->service_timer
.function
)
4945 del_timer_sync(&hdev
->service_timer
);
4946 if (hdev
->service_task
.func
)
4947 cancel_work_sync(&hdev
->service_task
);
4948 if (hdev
->rst_service_task
.func
)
4949 cancel_work_sync(&hdev
->rst_service_task
);
4952 mdiobus_unregister(mac
->mdio_bus
);
4954 /* Disable MISC vector(vector0) */
4955 hclge_enable_vector(&hdev
->misc_vector
, false);
4956 hclge_destroy_cmd_queue(&hdev
->hw
);
4957 hclge_misc_irq_uninit(hdev
);
4958 hclge_pci_uninit(hdev
);
4959 ae_dev
->priv
= NULL
;
4962 static const struct hnae3_ae_ops hclge_ops
= {
4963 .init_ae_dev
= hclge_init_ae_dev
,
4964 .uninit_ae_dev
= hclge_uninit_ae_dev
,
4965 .init_client_instance
= hclge_init_client_instance
,
4966 .uninit_client_instance
= hclge_uninit_client_instance
,
4967 .map_ring_to_vector
= hclge_map_handle_ring_to_vector
,
4968 .unmap_ring_from_vector
= hclge_unmap_ring_from_vector
,
4969 .get_vector
= hclge_get_vector
,
4970 .set_promisc_mode
= hclge_set_promisc_mode
,
4971 .set_loopback
= hclge_set_loopback
,
4972 .start
= hclge_ae_start
,
4973 .stop
= hclge_ae_stop
,
4974 .get_status
= hclge_get_status
,
4975 .get_ksettings_an_result
= hclge_get_ksettings_an_result
,
4976 .update_speed_duplex_h
= hclge_update_speed_duplex_h
,
4977 .cfg_mac_speed_dup_h
= hclge_cfg_mac_speed_dup_h
,
4978 .get_media_type
= hclge_get_media_type
,
4979 .get_rss_key_size
= hclge_get_rss_key_size
,
4980 .get_rss_indir_size
= hclge_get_rss_indir_size
,
4981 .get_rss
= hclge_get_rss
,
4982 .set_rss
= hclge_set_rss
,
4983 .set_rss_tuple
= hclge_set_rss_tuple
,
4984 .get_rss_tuple
= hclge_get_rss_tuple
,
4985 .get_tc_size
= hclge_get_tc_size
,
4986 .get_mac_addr
= hclge_get_mac_addr
,
4987 .set_mac_addr
= hclge_set_mac_addr
,
4988 .add_uc_addr
= hclge_add_uc_addr
,
4989 .rm_uc_addr
= hclge_rm_uc_addr
,
4990 .add_mc_addr
= hclge_add_mc_addr
,
4991 .rm_mc_addr
= hclge_rm_mc_addr
,
4992 .set_autoneg
= hclge_set_autoneg
,
4993 .get_autoneg
= hclge_get_autoneg
,
4994 .get_pauseparam
= hclge_get_pauseparam
,
4995 .set_mtu
= hclge_set_mtu
,
4996 .reset_queue
= hclge_reset_tqp
,
4997 .get_stats
= hclge_get_stats
,
4998 .update_stats
= hclge_update_stats
,
4999 .get_strings
= hclge_get_strings
,
5000 .get_sset_count
= hclge_get_sset_count
,
5001 .get_fw_version
= hclge_get_fw_version
,
5002 .get_mdix_mode
= hclge_get_mdix_mode
,
5003 .set_vlan_filter
= hclge_set_port_vlan_filter
,
5004 .set_vf_vlan_filter
= hclge_set_vf_vlan_filter
,
5005 .reset_event
= hclge_reset_event
,
5008 static struct hnae3_ae_algo ae_algo
= {
5011 .pdev_id_table
= ae_algo_pci_tbl
,
5014 static int hclge_init(void)
5016 pr_info("%s is initializing\n", HCLGE_NAME
);
5018 return hnae3_register_ae_algo(&ae_algo
);
5021 static void hclge_exit(void)
5023 hnae3_unregister_ae_algo(&ae_algo
);
5025 module_init(hclge_init
);
5026 module_exit(hclge_exit
);
5028 MODULE_LICENSE("GPL");
5029 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
5030 MODULE_DESCRIPTION("HCLGE Driver");
5031 MODULE_VERSION(HCLGE_MOD_VERSION
);