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[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
1 /*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10 #include <linux/acpi.h>
11 #include <linux/device.h>
12 #include <linux/etherdevice.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
20
21 #include "hclge_cmd.h"
22 #include "hclge_dcb.h"
23 #include "hclge_main.h"
24 #include "hclge_mdio.h"
25 #include "hclge_tm.h"
26 #include "hnae3.h"
27
28 #define HCLGE_NAME "hclge"
29 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
30 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
31 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
32 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
33
34 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
35 enum hclge_mta_dmac_sel_type mta_mac_sel,
36 bool enable);
37 static int hclge_init_vlan_config(struct hclge_dev *hdev);
38 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
39
40 static struct hnae3_ae_algo ae_algo;
41
42 static const struct pci_device_id ae_algo_pci_tbl[] = {
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
50 /* required last entry */
51 {0, }
52 };
53
54 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
55 "Mac Loopback test",
56 "Serdes Loopback test",
57 "Phy Loopback test"
58 };
59
60 static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
61 {"igu_rx_oversize_pkt",
62 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
63 {"igu_rx_undersize_pkt",
64 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
65 {"igu_rx_out_all_pkt",
66 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
67 {"igu_rx_uni_pkt",
68 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
69 {"igu_rx_multi_pkt",
70 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
71 {"igu_rx_broad_pkt",
72 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
73 {"egu_tx_out_all_pkt",
74 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
75 {"egu_tx_uni_pkt",
76 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
77 {"egu_tx_multi_pkt",
78 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
79 {"egu_tx_broad_pkt",
80 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
81 {"ssu_ppp_mac_key_num",
82 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
83 {"ssu_ppp_host_key_num",
84 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
85 {"ppp_ssu_mac_rlt_num",
86 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
87 {"ppp_ssu_host_rlt_num",
88 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
89 {"ssu_tx_in_num",
90 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
91 {"ssu_tx_out_num",
92 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
93 {"ssu_rx_in_num",
94 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
95 {"ssu_rx_out_num",
96 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
97 };
98
99 static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
100 {"igu_rx_err_pkt",
101 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
102 {"igu_rx_no_eof_pkt",
103 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
104 {"igu_rx_no_sof_pkt",
105 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
106 {"egu_tx_1588_pkt",
107 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
108 {"ssu_full_drop_num",
109 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
110 {"ssu_part_drop_num",
111 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
112 {"ppp_key_drop_num",
113 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
114 {"ppp_rlt_drop_num",
115 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
116 {"ssu_key_drop_num",
117 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
118 {"pkt_curr_buf_cnt",
119 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
120 {"qcn_fb_rcv_cnt",
121 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
122 {"qcn_fb_drop_cnt",
123 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
124 {"qcn_fb_invaild_cnt",
125 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
126 {"rx_packet_tc0_in_cnt",
127 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
128 {"rx_packet_tc1_in_cnt",
129 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
130 {"rx_packet_tc2_in_cnt",
131 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
132 {"rx_packet_tc3_in_cnt",
133 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
134 {"rx_packet_tc4_in_cnt",
135 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
136 {"rx_packet_tc5_in_cnt",
137 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
138 {"rx_packet_tc6_in_cnt",
139 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
140 {"rx_packet_tc7_in_cnt",
141 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
142 {"rx_packet_tc0_out_cnt",
143 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
144 {"rx_packet_tc1_out_cnt",
145 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
146 {"rx_packet_tc2_out_cnt",
147 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
148 {"rx_packet_tc3_out_cnt",
149 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
150 {"rx_packet_tc4_out_cnt",
151 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
152 {"rx_packet_tc5_out_cnt",
153 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
154 {"rx_packet_tc6_out_cnt",
155 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
156 {"rx_packet_tc7_out_cnt",
157 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
158 {"tx_packet_tc0_in_cnt",
159 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
160 {"tx_packet_tc1_in_cnt",
161 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
162 {"tx_packet_tc2_in_cnt",
163 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
164 {"tx_packet_tc3_in_cnt",
165 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
166 {"tx_packet_tc4_in_cnt",
167 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
168 {"tx_packet_tc5_in_cnt",
169 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
170 {"tx_packet_tc6_in_cnt",
171 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
172 {"tx_packet_tc7_in_cnt",
173 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
174 {"tx_packet_tc0_out_cnt",
175 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
176 {"tx_packet_tc1_out_cnt",
177 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
178 {"tx_packet_tc2_out_cnt",
179 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
180 {"tx_packet_tc3_out_cnt",
181 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
182 {"tx_packet_tc4_out_cnt",
183 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
184 {"tx_packet_tc5_out_cnt",
185 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
186 {"tx_packet_tc6_out_cnt",
187 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
188 {"tx_packet_tc7_out_cnt",
189 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
190 {"pkt_curr_buf_tc0_cnt",
191 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
192 {"pkt_curr_buf_tc1_cnt",
193 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
194 {"pkt_curr_buf_tc2_cnt",
195 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
196 {"pkt_curr_buf_tc3_cnt",
197 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
198 {"pkt_curr_buf_tc4_cnt",
199 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
200 {"pkt_curr_buf_tc5_cnt",
201 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
202 {"pkt_curr_buf_tc6_cnt",
203 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
204 {"pkt_curr_buf_tc7_cnt",
205 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
206 {"mb_uncopy_num",
207 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
208 {"lo_pri_unicast_rlt_drop_num",
209 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
210 {"hi_pri_multicast_rlt_drop_num",
211 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
212 {"lo_pri_multicast_rlt_drop_num",
213 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
214 {"rx_oq_drop_pkt_cnt",
215 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
216 {"tx_oq_drop_pkt_cnt",
217 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
218 {"nic_l2_err_drop_pkt_cnt",
219 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
220 {"roc_l2_err_drop_pkt_cnt",
221 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
222 };
223
224 static const struct hclge_comm_stats_str g_mac_stats_string[] = {
225 {"mac_tx_mac_pause_num",
226 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
227 {"mac_rx_mac_pause_num",
228 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
229 {"mac_tx_pfc_pri0_pkt_num",
230 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
231 {"mac_tx_pfc_pri1_pkt_num",
232 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
233 {"mac_tx_pfc_pri2_pkt_num",
234 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
235 {"mac_tx_pfc_pri3_pkt_num",
236 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
237 {"mac_tx_pfc_pri4_pkt_num",
238 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
239 {"mac_tx_pfc_pri5_pkt_num",
240 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
241 {"mac_tx_pfc_pri6_pkt_num",
242 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
243 {"mac_tx_pfc_pri7_pkt_num",
244 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
245 {"mac_rx_pfc_pri0_pkt_num",
246 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
247 {"mac_rx_pfc_pri1_pkt_num",
248 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
249 {"mac_rx_pfc_pri2_pkt_num",
250 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
251 {"mac_rx_pfc_pri3_pkt_num",
252 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
253 {"mac_rx_pfc_pri4_pkt_num",
254 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
255 {"mac_rx_pfc_pri5_pkt_num",
256 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
257 {"mac_rx_pfc_pri6_pkt_num",
258 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
259 {"mac_rx_pfc_pri7_pkt_num",
260 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
261 {"mac_tx_total_pkt_num",
262 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
263 {"mac_tx_total_oct_num",
264 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
265 {"mac_tx_good_pkt_num",
266 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
267 {"mac_tx_bad_pkt_num",
268 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
269 {"mac_tx_good_oct_num",
270 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
271 {"mac_tx_bad_oct_num",
272 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
273 {"mac_tx_uni_pkt_num",
274 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
275 {"mac_tx_multi_pkt_num",
276 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
277 {"mac_tx_broad_pkt_num",
278 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
279 {"mac_tx_undersize_pkt_num",
280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
281 {"mac_tx_overrsize_pkt_num",
282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_overrsize_pkt_num)},
283 {"mac_tx_64_oct_pkt_num",
284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
285 {"mac_tx_65_127_oct_pkt_num",
286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
287 {"mac_tx_128_255_oct_pkt_num",
288 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
289 {"mac_tx_256_511_oct_pkt_num",
290 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
291 {"mac_tx_512_1023_oct_pkt_num",
292 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
293 {"mac_tx_1024_1518_oct_pkt_num",
294 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
295 {"mac_tx_1519_max_oct_pkt_num",
296 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_oct_pkt_num)},
297 {"mac_rx_total_pkt_num",
298 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
299 {"mac_rx_total_oct_num",
300 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
301 {"mac_rx_good_pkt_num",
302 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
303 {"mac_rx_bad_pkt_num",
304 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
305 {"mac_rx_good_oct_num",
306 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
307 {"mac_rx_bad_oct_num",
308 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
309 {"mac_rx_uni_pkt_num",
310 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
311 {"mac_rx_multi_pkt_num",
312 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
313 {"mac_rx_broad_pkt_num",
314 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
315 {"mac_rx_undersize_pkt_num",
316 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
317 {"mac_rx_overrsize_pkt_num",
318 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_overrsize_pkt_num)},
319 {"mac_rx_64_oct_pkt_num",
320 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
321 {"mac_rx_65_127_oct_pkt_num",
322 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
323 {"mac_rx_128_255_oct_pkt_num",
324 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
325 {"mac_rx_256_511_oct_pkt_num",
326 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
327 {"mac_rx_512_1023_oct_pkt_num",
328 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
329 {"mac_rx_1024_1518_oct_pkt_num",
330 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
331 {"mac_rx_1519_max_oct_pkt_num",
332 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_oct_pkt_num)},
333
334 {"mac_trans_fragment_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_fragment_pkt_num)},
336 {"mac_trans_undermin_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_undermin_pkt_num)},
338 {"mac_trans_jabber_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_jabber_pkt_num)},
340 {"mac_trans_err_all_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_err_all_pkt_num)},
342 {"mac_trans_from_app_good_pkt_num",
343 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_good_pkt_num)},
344 {"mac_trans_from_app_bad_pkt_num",
345 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_bad_pkt_num)},
346 {"mac_rcv_fragment_pkt_num",
347 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fragment_pkt_num)},
348 {"mac_rcv_undermin_pkt_num",
349 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_undermin_pkt_num)},
350 {"mac_rcv_jabber_pkt_num",
351 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_jabber_pkt_num)},
352 {"mac_rcv_fcs_err_pkt_num",
353 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fcs_err_pkt_num)},
354 {"mac_rcv_send_app_good_pkt_num",
355 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_good_pkt_num)},
356 {"mac_rcv_send_app_bad_pkt_num",
357 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_bad_pkt_num)}
358 };
359
360 static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
361 {
362 #define HCLGE_64_BIT_CMD_NUM 5
363 #define HCLGE_64_BIT_RTN_DATANUM 4
364 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
365 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
366 __le64 *desc_data;
367 int i, k, n;
368 int ret;
369
370 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
371 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
372 if (ret) {
373 dev_err(&hdev->pdev->dev,
374 "Get 64 bit pkt stats fail, status = %d.\n", ret);
375 return ret;
376 }
377
378 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
379 if (unlikely(i == 0)) {
380 desc_data = (__le64 *)(&desc[i].data[0]);
381 n = HCLGE_64_BIT_RTN_DATANUM - 1;
382 } else {
383 desc_data = (__le64 *)(&desc[i]);
384 n = HCLGE_64_BIT_RTN_DATANUM;
385 }
386 for (k = 0; k < n; k++) {
387 *data++ += le64_to_cpu(*desc_data);
388 desc_data++;
389 }
390 }
391
392 return 0;
393 }
394
395 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
396 {
397 stats->pkt_curr_buf_cnt = 0;
398 stats->pkt_curr_buf_tc0_cnt = 0;
399 stats->pkt_curr_buf_tc1_cnt = 0;
400 stats->pkt_curr_buf_tc2_cnt = 0;
401 stats->pkt_curr_buf_tc3_cnt = 0;
402 stats->pkt_curr_buf_tc4_cnt = 0;
403 stats->pkt_curr_buf_tc5_cnt = 0;
404 stats->pkt_curr_buf_tc6_cnt = 0;
405 stats->pkt_curr_buf_tc7_cnt = 0;
406 }
407
408 static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
409 {
410 #define HCLGE_32_BIT_CMD_NUM 8
411 #define HCLGE_32_BIT_RTN_DATANUM 8
412
413 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
414 struct hclge_32_bit_stats *all_32_bit_stats;
415 __le32 *desc_data;
416 int i, k, n;
417 u64 *data;
418 int ret;
419
420 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
421 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
422
423 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
424 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
425 if (ret) {
426 dev_err(&hdev->pdev->dev,
427 "Get 32 bit pkt stats fail, status = %d.\n", ret);
428
429 return ret;
430 }
431
432 hclge_reset_partial_32bit_counter(all_32_bit_stats);
433 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
434 if (unlikely(i == 0)) {
435 __le16 *desc_data_16bit;
436
437 all_32_bit_stats->igu_rx_err_pkt +=
438 le32_to_cpu(desc[i].data[0]);
439
440 desc_data_16bit = (__le16 *)&desc[i].data[1];
441 all_32_bit_stats->igu_rx_no_eof_pkt +=
442 le16_to_cpu(*desc_data_16bit);
443
444 desc_data_16bit++;
445 all_32_bit_stats->igu_rx_no_sof_pkt +=
446 le16_to_cpu(*desc_data_16bit);
447
448 desc_data = &desc[i].data[2];
449 n = HCLGE_32_BIT_RTN_DATANUM - 4;
450 } else {
451 desc_data = (__le32 *)&desc[i];
452 n = HCLGE_32_BIT_RTN_DATANUM;
453 }
454 for (k = 0; k < n; k++) {
455 *data++ += le32_to_cpu(*desc_data);
456 desc_data++;
457 }
458 }
459
460 return 0;
461 }
462
463 static int hclge_mac_update_stats(struct hclge_dev *hdev)
464 {
465 #define HCLGE_MAC_CMD_NUM 17
466 #define HCLGE_RTN_DATA_NUM 4
467
468 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
469 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
470 __le64 *desc_data;
471 int i, k, n;
472 int ret;
473
474 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
475 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
476 if (ret) {
477 dev_err(&hdev->pdev->dev,
478 "Get MAC pkt stats fail, status = %d.\n", ret);
479
480 return ret;
481 }
482
483 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
484 if (unlikely(i == 0)) {
485 desc_data = (__le64 *)(&desc[i].data[0]);
486 n = HCLGE_RTN_DATA_NUM - 2;
487 } else {
488 desc_data = (__le64 *)(&desc[i]);
489 n = HCLGE_RTN_DATA_NUM;
490 }
491 for (k = 0; k < n; k++) {
492 *data++ += le64_to_cpu(*desc_data);
493 desc_data++;
494 }
495 }
496
497 return 0;
498 }
499
500 static int hclge_tqps_update_stats(struct hnae3_handle *handle)
501 {
502 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
503 struct hclge_vport *vport = hclge_get_vport(handle);
504 struct hclge_dev *hdev = vport->back;
505 struct hnae3_queue *queue;
506 struct hclge_desc desc[1];
507 struct hclge_tqp *tqp;
508 int ret, i;
509
510 for (i = 0; i < kinfo->num_tqps; i++) {
511 queue = handle->kinfo.tqp[i];
512 tqp = container_of(queue, struct hclge_tqp, q);
513 /* command : HCLGE_OPC_QUERY_IGU_STAT */
514 hclge_cmd_setup_basic_desc(&desc[0],
515 HCLGE_OPC_QUERY_RX_STATUS,
516 true);
517
518 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
519 ret = hclge_cmd_send(&hdev->hw, desc, 1);
520 if (ret) {
521 dev_err(&hdev->pdev->dev,
522 "Query tqp stat fail, status = %d,queue = %d\n",
523 ret, i);
524 return ret;
525 }
526 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
527 le32_to_cpu(desc[0].data[4]);
528 }
529
530 for (i = 0; i < kinfo->num_tqps; i++) {
531 queue = handle->kinfo.tqp[i];
532 tqp = container_of(queue, struct hclge_tqp, q);
533 /* command : HCLGE_OPC_QUERY_IGU_STAT */
534 hclge_cmd_setup_basic_desc(&desc[0],
535 HCLGE_OPC_QUERY_TX_STATUS,
536 true);
537
538 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
539 ret = hclge_cmd_send(&hdev->hw, desc, 1);
540 if (ret) {
541 dev_err(&hdev->pdev->dev,
542 "Query tqp stat fail, status = %d,queue = %d\n",
543 ret, i);
544 return ret;
545 }
546 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
547 le32_to_cpu(desc[0].data[4]);
548 }
549
550 return 0;
551 }
552
553 static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
554 {
555 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
556 struct hclge_tqp *tqp;
557 u64 *buff = data;
558 int i;
559
560 for (i = 0; i < kinfo->num_tqps; i++) {
561 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
562 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
563 }
564
565 for (i = 0; i < kinfo->num_tqps; i++) {
566 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
567 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
568 }
569
570 return buff;
571 }
572
573 static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
574 {
575 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
576
577 return kinfo->num_tqps * (2);
578 }
579
580 static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
581 {
582 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
583 u8 *buff = data;
584 int i = 0;
585
586 for (i = 0; i < kinfo->num_tqps; i++) {
587 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
588 struct hclge_tqp, q);
589 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_tx_pktnum_rcd",
590 tqp->index);
591 buff = buff + ETH_GSTRING_LEN;
592 }
593
594 for (i = 0; i < kinfo->num_tqps; i++) {
595 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
596 struct hclge_tqp, q);
597 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_rx_pktnum_rcd",
598 tqp->index);
599 buff = buff + ETH_GSTRING_LEN;
600 }
601
602 return buff;
603 }
604
605 static u64 *hclge_comm_get_stats(void *comm_stats,
606 const struct hclge_comm_stats_str strs[],
607 int size, u64 *data)
608 {
609 u64 *buf = data;
610 u32 i;
611
612 for (i = 0; i < size; i++)
613 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
614
615 return buf + size;
616 }
617
618 static u8 *hclge_comm_get_strings(u32 stringset,
619 const struct hclge_comm_stats_str strs[],
620 int size, u8 *data)
621 {
622 char *buff = (char *)data;
623 u32 i;
624
625 if (stringset != ETH_SS_STATS)
626 return buff;
627
628 for (i = 0; i < size; i++) {
629 snprintf(buff, ETH_GSTRING_LEN,
630 strs[i].desc);
631 buff = buff + ETH_GSTRING_LEN;
632 }
633
634 return (u8 *)buff;
635 }
636
637 static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
638 struct net_device_stats *net_stats)
639 {
640 net_stats->tx_dropped = 0;
641 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
642 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
643 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
644
645 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
646 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
647 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_err_pkt;
648 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
649 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
650 net_stats->rx_errors += hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
651
652 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
653 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
654
655 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
656 net_stats->rx_length_errors =
657 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
658 net_stats->rx_length_errors +=
659 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
660 net_stats->rx_over_errors =
661 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
662 }
663
664 static void hclge_update_stats_for_all(struct hclge_dev *hdev)
665 {
666 struct hnae3_handle *handle;
667 int status;
668
669 handle = &hdev->vport[0].nic;
670 if (handle->client) {
671 status = hclge_tqps_update_stats(handle);
672 if (status) {
673 dev_err(&hdev->pdev->dev,
674 "Update TQPS stats fail, status = %d.\n",
675 status);
676 }
677 }
678
679 status = hclge_mac_update_stats(hdev);
680 if (status)
681 dev_err(&hdev->pdev->dev,
682 "Update MAC stats fail, status = %d.\n", status);
683
684 status = hclge_32_bit_update_stats(hdev);
685 if (status)
686 dev_err(&hdev->pdev->dev,
687 "Update 32 bit stats fail, status = %d.\n",
688 status);
689
690 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
691 }
692
693 static void hclge_update_stats(struct hnae3_handle *handle,
694 struct net_device_stats *net_stats)
695 {
696 struct hclge_vport *vport = hclge_get_vport(handle);
697 struct hclge_dev *hdev = vport->back;
698 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
699 int status;
700
701 status = hclge_mac_update_stats(hdev);
702 if (status)
703 dev_err(&hdev->pdev->dev,
704 "Update MAC stats fail, status = %d.\n",
705 status);
706
707 status = hclge_32_bit_update_stats(hdev);
708 if (status)
709 dev_err(&hdev->pdev->dev,
710 "Update 32 bit stats fail, status = %d.\n",
711 status);
712
713 status = hclge_64_bit_update_stats(hdev);
714 if (status)
715 dev_err(&hdev->pdev->dev,
716 "Update 64 bit stats fail, status = %d.\n",
717 status);
718
719 status = hclge_tqps_update_stats(handle);
720 if (status)
721 dev_err(&hdev->pdev->dev,
722 "Update TQPS stats fail, status = %d.\n",
723 status);
724
725 hclge_update_netstat(hw_stats, net_stats);
726 }
727
728 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
729 {
730 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
731
732 struct hclge_vport *vport = hclge_get_vport(handle);
733 struct hclge_dev *hdev = vport->back;
734 int count = 0;
735
736 /* Loopback test support rules:
737 * mac: only GE mode support
738 * serdes: all mac mode will support include GE/XGE/LGE/CGE
739 * phy: only support when phy device exist on board
740 */
741 if (stringset == ETH_SS_TEST) {
742 /* clear loopback bit flags at first */
743 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
744 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
745 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
746 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
747 count += 1;
748 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
749 } else {
750 count = -EOPNOTSUPP;
751 }
752 } else if (stringset == ETH_SS_STATS) {
753 count = ARRAY_SIZE(g_mac_stats_string) +
754 ARRAY_SIZE(g_all_32bit_stats_string) +
755 ARRAY_SIZE(g_all_64bit_stats_string) +
756 hclge_tqps_get_sset_count(handle, stringset);
757 }
758
759 return count;
760 }
761
762 static void hclge_get_strings(struct hnae3_handle *handle,
763 u32 stringset,
764 u8 *data)
765 {
766 u8 *p = (char *)data;
767 int size;
768
769 if (stringset == ETH_SS_STATS) {
770 size = ARRAY_SIZE(g_mac_stats_string);
771 p = hclge_comm_get_strings(stringset,
772 g_mac_stats_string,
773 size,
774 p);
775 size = ARRAY_SIZE(g_all_32bit_stats_string);
776 p = hclge_comm_get_strings(stringset,
777 g_all_32bit_stats_string,
778 size,
779 p);
780 size = ARRAY_SIZE(g_all_64bit_stats_string);
781 p = hclge_comm_get_strings(stringset,
782 g_all_64bit_stats_string,
783 size,
784 p);
785 p = hclge_tqps_get_strings(handle, p);
786 } else if (stringset == ETH_SS_TEST) {
787 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
788 memcpy(p,
789 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
790 ETH_GSTRING_LEN);
791 p += ETH_GSTRING_LEN;
792 }
793 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
794 memcpy(p,
795 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
796 ETH_GSTRING_LEN);
797 p += ETH_GSTRING_LEN;
798 }
799 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
800 memcpy(p,
801 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
802 ETH_GSTRING_LEN);
803 p += ETH_GSTRING_LEN;
804 }
805 }
806 }
807
808 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
809 {
810 struct hclge_vport *vport = hclge_get_vport(handle);
811 struct hclge_dev *hdev = vport->back;
812 u64 *p;
813
814 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
815 g_mac_stats_string,
816 ARRAY_SIZE(g_mac_stats_string),
817 data);
818 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
819 g_all_32bit_stats_string,
820 ARRAY_SIZE(g_all_32bit_stats_string),
821 p);
822 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
823 g_all_64bit_stats_string,
824 ARRAY_SIZE(g_all_64bit_stats_string),
825 p);
826 p = hclge_tqps_get_stats(handle, p);
827 }
828
829 static int hclge_parse_func_status(struct hclge_dev *hdev,
830 struct hclge_func_status_cmd *status)
831 {
832 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
833 return -EINVAL;
834
835 /* Set the pf to main pf */
836 if (status->pf_state & HCLGE_PF_STATE_MAIN)
837 hdev->flag |= HCLGE_FLAG_MAIN;
838 else
839 hdev->flag &= ~HCLGE_FLAG_MAIN;
840
841 return 0;
842 }
843
844 static int hclge_query_function_status(struct hclge_dev *hdev)
845 {
846 struct hclge_func_status_cmd *req;
847 struct hclge_desc desc;
848 int timeout = 0;
849 int ret;
850
851 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
852 req = (struct hclge_func_status_cmd *)desc.data;
853
854 do {
855 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
856 if (ret) {
857 dev_err(&hdev->pdev->dev,
858 "query function status failed %d.\n",
859 ret);
860
861 return ret;
862 }
863
864 /* Check pf reset is done */
865 if (req->pf_state)
866 break;
867 usleep_range(1000, 2000);
868 } while (timeout++ < 5);
869
870 ret = hclge_parse_func_status(hdev, req);
871
872 return ret;
873 }
874
875 static int hclge_query_pf_resource(struct hclge_dev *hdev)
876 {
877 struct hclge_pf_res_cmd *req;
878 struct hclge_desc desc;
879 int ret;
880
881 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
882 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
883 if (ret) {
884 dev_err(&hdev->pdev->dev,
885 "query pf resource failed %d.\n", ret);
886 return ret;
887 }
888
889 req = (struct hclge_pf_res_cmd *)desc.data;
890 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
891 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
892
893 if (hnae3_dev_roce_supported(hdev)) {
894 hdev->num_roce_msi =
895 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
896 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
897
898 /* PF should have NIC vectors and Roce vectors,
899 * NIC vectors are queued before Roce vectors.
900 */
901 hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET;
902 } else {
903 hdev->num_msi =
904 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
905 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
906 }
907
908 return 0;
909 }
910
911 static int hclge_parse_speed(int speed_cmd, int *speed)
912 {
913 switch (speed_cmd) {
914 case 6:
915 *speed = HCLGE_MAC_SPEED_10M;
916 break;
917 case 7:
918 *speed = HCLGE_MAC_SPEED_100M;
919 break;
920 case 0:
921 *speed = HCLGE_MAC_SPEED_1G;
922 break;
923 case 1:
924 *speed = HCLGE_MAC_SPEED_10G;
925 break;
926 case 2:
927 *speed = HCLGE_MAC_SPEED_25G;
928 break;
929 case 3:
930 *speed = HCLGE_MAC_SPEED_40G;
931 break;
932 case 4:
933 *speed = HCLGE_MAC_SPEED_50G;
934 break;
935 case 5:
936 *speed = HCLGE_MAC_SPEED_100G;
937 break;
938 default:
939 return -EINVAL;
940 }
941
942 return 0;
943 }
944
945 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
946 {
947 struct hclge_cfg_param_cmd *req;
948 u64 mac_addr_tmp_high;
949 u64 mac_addr_tmp;
950 int i;
951
952 req = (struct hclge_cfg_param_cmd *)desc[0].data;
953
954 /* get the configuration */
955 cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]),
956 HCLGE_CFG_VMDQ_M,
957 HCLGE_CFG_VMDQ_S);
958 cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
959 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
960 cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
961 HCLGE_CFG_TQP_DESC_N_M,
962 HCLGE_CFG_TQP_DESC_N_S);
963
964 cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]),
965 HCLGE_CFG_PHY_ADDR_M,
966 HCLGE_CFG_PHY_ADDR_S);
967 cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]),
968 HCLGE_CFG_MEDIA_TP_M,
969 HCLGE_CFG_MEDIA_TP_S);
970 cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]),
971 HCLGE_CFG_RX_BUF_LEN_M,
972 HCLGE_CFG_RX_BUF_LEN_S);
973 /* get mac_address */
974 mac_addr_tmp = __le32_to_cpu(req->param[2]);
975 mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]),
976 HCLGE_CFG_MAC_ADDR_H_M,
977 HCLGE_CFG_MAC_ADDR_H_S);
978
979 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
980
981 cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]),
982 HCLGE_CFG_DEFAULT_SPEED_M,
983 HCLGE_CFG_DEFAULT_SPEED_S);
984 for (i = 0; i < ETH_ALEN; i++)
985 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
986
987 req = (struct hclge_cfg_param_cmd *)desc[1].data;
988 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
989 }
990
991 /* hclge_get_cfg: query the static parameter from flash
992 * @hdev: pointer to struct hclge_dev
993 * @hcfg: the config structure to be getted
994 */
995 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
996 {
997 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
998 struct hclge_cfg_param_cmd *req;
999 int i, ret;
1000
1001 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
1002 u32 offset = 0;
1003
1004 req = (struct hclge_cfg_param_cmd *)desc[i].data;
1005 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1006 true);
1007 hnae_set_field(offset, HCLGE_CFG_OFFSET_M,
1008 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1009 /* Len should be united by 4 bytes when send to hardware */
1010 hnae_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
1011 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
1012 req->offset = cpu_to_le32(offset);
1013 }
1014
1015 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1016 if (ret) {
1017 dev_err(&hdev->pdev->dev,
1018 "get config failed %d.\n", ret);
1019 return ret;
1020 }
1021
1022 hclge_parse_cfg(hcfg, desc);
1023 return 0;
1024 }
1025
1026 static int hclge_get_cap(struct hclge_dev *hdev)
1027 {
1028 int ret;
1029
1030 ret = hclge_query_function_status(hdev);
1031 if (ret) {
1032 dev_err(&hdev->pdev->dev,
1033 "query function status error %d.\n", ret);
1034 return ret;
1035 }
1036
1037 /* get pf resource */
1038 ret = hclge_query_pf_resource(hdev);
1039 if (ret) {
1040 dev_err(&hdev->pdev->dev,
1041 "query pf resource error %d.\n", ret);
1042 return ret;
1043 }
1044
1045 return 0;
1046 }
1047
1048 static int hclge_configure(struct hclge_dev *hdev)
1049 {
1050 struct hclge_cfg cfg;
1051 int ret, i;
1052
1053 ret = hclge_get_cfg(hdev, &cfg);
1054 if (ret) {
1055 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1056 return ret;
1057 }
1058
1059 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1060 hdev->base_tqp_pid = 0;
1061 hdev->rss_size_max = 1;
1062 hdev->rx_buf_len = cfg.rx_buf_len;
1063 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
1064 hdev->hw.mac.media_type = cfg.media_type;
1065 hdev->hw.mac.phy_addr = cfg.phy_addr;
1066 hdev->num_desc = cfg.tqp_desc_num;
1067 hdev->tm_info.num_pg = 1;
1068 hdev->tc_max = cfg.tc_num;
1069 hdev->tm_info.hw_pfc_map = 0;
1070
1071 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1072 if (ret) {
1073 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1074 return ret;
1075 }
1076
1077 if ((hdev->tc_max > HNAE3_MAX_TC) ||
1078 (hdev->tc_max < 1)) {
1079 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
1080 hdev->tc_max);
1081 hdev->tc_max = 1;
1082 }
1083
1084 /* Dev does not support DCB */
1085 if (!hnae3_dev_dcb_supported(hdev)) {
1086 hdev->tc_max = 1;
1087 hdev->pfc_max = 0;
1088 } else {
1089 hdev->pfc_max = hdev->tc_max;
1090 }
1091
1092 hdev->tm_info.num_tc = hdev->tc_max;
1093
1094 /* Currently not support uncontiuous tc */
1095 for (i = 0; i < hdev->tm_info.num_tc; i++)
1096 hnae_set_bit(hdev->hw_tc_map, i, 1);
1097
1098 if (!hdev->num_vmdq_vport && !hdev->num_req_vfs)
1099 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1100 else
1101 hdev->tx_sch_mode = HCLGE_FLAG_VNET_BASE_SCH_MODE;
1102
1103 return ret;
1104 }
1105
1106 static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1107 int tso_mss_max)
1108 {
1109 struct hclge_cfg_tso_status_cmd *req;
1110 struct hclge_desc desc;
1111 u16 tso_mss;
1112
1113 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1114
1115 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
1116
1117 tso_mss = 0;
1118 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1119 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
1120 req->tso_mss_min = cpu_to_le16(tso_mss);
1121
1122 tso_mss = 0;
1123 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1124 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
1125 req->tso_mss_max = cpu_to_le16(tso_mss);
1126
1127 return hclge_cmd_send(&hdev->hw, &desc, 1);
1128 }
1129
1130 static int hclge_alloc_tqps(struct hclge_dev *hdev)
1131 {
1132 struct hclge_tqp *tqp;
1133 int i;
1134
1135 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1136 sizeof(struct hclge_tqp), GFP_KERNEL);
1137 if (!hdev->htqp)
1138 return -ENOMEM;
1139
1140 tqp = hdev->htqp;
1141
1142 for (i = 0; i < hdev->num_tqps; i++) {
1143 tqp->dev = &hdev->pdev->dev;
1144 tqp->index = i;
1145
1146 tqp->q.ae_algo = &ae_algo;
1147 tqp->q.buf_size = hdev->rx_buf_len;
1148 tqp->q.desc_num = hdev->num_desc;
1149 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1150 i * HCLGE_TQP_REG_SIZE;
1151
1152 tqp++;
1153 }
1154
1155 return 0;
1156 }
1157
1158 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1159 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1160 {
1161 struct hclge_tqp_map_cmd *req;
1162 struct hclge_desc desc;
1163 int ret;
1164
1165 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1166
1167 req = (struct hclge_tqp_map_cmd *)desc.data;
1168 req->tqp_id = cpu_to_le16(tqp_pid);
1169 req->tqp_vf = func_id;
1170 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1171 1 << HCLGE_TQP_MAP_EN_B;
1172 req->tqp_vid = cpu_to_le16(tqp_vid);
1173
1174 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1175 if (ret) {
1176 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n",
1177 ret);
1178 return ret;
1179 }
1180
1181 return 0;
1182 }
1183
1184 static int hclge_assign_tqp(struct hclge_vport *vport,
1185 struct hnae3_queue **tqp, u16 num_tqps)
1186 {
1187 struct hclge_dev *hdev = vport->back;
1188 int i, alloced;
1189
1190 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1191 alloced < num_tqps; i++) {
1192 if (!hdev->htqp[i].alloced) {
1193 hdev->htqp[i].q.handle = &vport->nic;
1194 hdev->htqp[i].q.tqp_index = alloced;
1195 tqp[alloced] = &hdev->htqp[i].q;
1196 hdev->htqp[i].alloced = true;
1197 alloced++;
1198 }
1199 }
1200 vport->alloc_tqps = num_tqps;
1201
1202 return 0;
1203 }
1204
1205 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1206 {
1207 struct hnae3_handle *nic = &vport->nic;
1208 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1209 struct hclge_dev *hdev = vport->back;
1210 int i, ret;
1211
1212 kinfo->num_desc = hdev->num_desc;
1213 kinfo->rx_buf_len = hdev->rx_buf_len;
1214 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1215 kinfo->rss_size
1216 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1217 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1218
1219 for (i = 0; i < HNAE3_MAX_TC; i++) {
1220 if (hdev->hw_tc_map & BIT(i)) {
1221 kinfo->tc_info[i].enable = true;
1222 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1223 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1224 kinfo->tc_info[i].tc = i;
1225 } else {
1226 /* Set to default queue if TC is disable */
1227 kinfo->tc_info[i].enable = false;
1228 kinfo->tc_info[i].tqp_offset = 0;
1229 kinfo->tc_info[i].tqp_count = 1;
1230 kinfo->tc_info[i].tc = 0;
1231 }
1232 }
1233
1234 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1235 sizeof(struct hnae3_queue *), GFP_KERNEL);
1236 if (!kinfo->tqp)
1237 return -ENOMEM;
1238
1239 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
1240 if (ret) {
1241 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1242 return -EINVAL;
1243 }
1244
1245 return 0;
1246 }
1247
1248 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1249 struct hclge_vport *vport)
1250 {
1251 struct hnae3_handle *nic = &vport->nic;
1252 struct hnae3_knic_private_info *kinfo;
1253 u16 i;
1254
1255 kinfo = &nic->kinfo;
1256 for (i = 0; i < kinfo->num_tqps; i++) {
1257 struct hclge_tqp *q =
1258 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1259 bool is_pf;
1260 int ret;
1261
1262 is_pf = !(vport->vport_id);
1263 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1264 i, is_pf);
1265 if (ret)
1266 return ret;
1267 }
1268
1269 return 0;
1270 }
1271
1272 static int hclge_map_tqp(struct hclge_dev *hdev)
1273 {
1274 struct hclge_vport *vport = hdev->vport;
1275 u16 i, num_vport;
1276
1277 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1278 for (i = 0; i < num_vport; i++) {
1279 int ret;
1280
1281 ret = hclge_map_tqp_to_vport(hdev, vport);
1282 if (ret)
1283 return ret;
1284
1285 vport++;
1286 }
1287
1288 return 0;
1289 }
1290
1291 static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1292 {
1293 /* this would be initialized later */
1294 }
1295
1296 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1297 {
1298 struct hnae3_handle *nic = &vport->nic;
1299 struct hclge_dev *hdev = vport->back;
1300 int ret;
1301
1302 nic->pdev = hdev->pdev;
1303 nic->ae_algo = &ae_algo;
1304 nic->numa_node_mask = hdev->numa_node_mask;
1305
1306 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1307 ret = hclge_knic_setup(vport, num_tqps);
1308 if (ret) {
1309 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1310 ret);
1311 return ret;
1312 }
1313 } else {
1314 hclge_unic_setup(vport, num_tqps);
1315 }
1316
1317 return 0;
1318 }
1319
1320 static int hclge_alloc_vport(struct hclge_dev *hdev)
1321 {
1322 struct pci_dev *pdev = hdev->pdev;
1323 struct hclge_vport *vport;
1324 u32 tqp_main_vport;
1325 u32 tqp_per_vport;
1326 int num_vport, i;
1327 int ret;
1328
1329 /* We need to alloc a vport for main NIC of PF */
1330 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1331
1332 if (hdev->num_tqps < num_vport)
1333 num_vport = hdev->num_tqps;
1334
1335 /* Alloc the same number of TQPs for every vport */
1336 tqp_per_vport = hdev->num_tqps / num_vport;
1337 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1338
1339 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1340 GFP_KERNEL);
1341 if (!vport)
1342 return -ENOMEM;
1343
1344 hdev->vport = vport;
1345 hdev->num_alloc_vport = num_vport;
1346
1347 #ifdef CONFIG_PCI_IOV
1348 /* Enable SRIOV */
1349 if (hdev->num_req_vfs) {
1350 dev_info(&pdev->dev, "active VFs(%d) found, enabling SRIOV\n",
1351 hdev->num_req_vfs);
1352 ret = pci_enable_sriov(hdev->pdev, hdev->num_req_vfs);
1353 if (ret) {
1354 hdev->num_alloc_vfs = 0;
1355 dev_err(&pdev->dev, "SRIOV enable failed %d\n",
1356 ret);
1357 return ret;
1358 }
1359 }
1360 hdev->num_alloc_vfs = hdev->num_req_vfs;
1361 #endif
1362
1363 for (i = 0; i < num_vport; i++) {
1364 vport->back = hdev;
1365 vport->vport_id = i;
1366
1367 if (i == 0)
1368 ret = hclge_vport_setup(vport, tqp_main_vport);
1369 else
1370 ret = hclge_vport_setup(vport, tqp_per_vport);
1371 if (ret) {
1372 dev_err(&pdev->dev,
1373 "vport setup failed for vport %d, %d\n",
1374 i, ret);
1375 return ret;
1376 }
1377
1378 vport++;
1379 }
1380
1381 return 0;
1382 }
1383
1384 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1385 struct hclge_pkt_buf_alloc *buf_alloc)
1386 {
1387 /* TX buffer size is unit by 128 byte */
1388 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1389 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1390 struct hclge_tx_buff_alloc_cmd *req;
1391 struct hclge_desc desc;
1392 int ret;
1393 u8 i;
1394
1395 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
1396
1397 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
1398 for (i = 0; i < HCLGE_TC_NUM; i++) {
1399 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1400
1401 req->tx_pkt_buff[i] =
1402 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1403 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
1404 }
1405
1406 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1407 if (ret) {
1408 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1409 ret);
1410 return ret;
1411 }
1412
1413 return 0;
1414 }
1415
1416 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1417 struct hclge_pkt_buf_alloc *buf_alloc)
1418 {
1419 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
1420
1421 if (ret) {
1422 dev_err(&hdev->pdev->dev,
1423 "tx buffer alloc failed %d\n", ret);
1424 return ret;
1425 }
1426
1427 return 0;
1428 }
1429
1430 static int hclge_get_tc_num(struct hclge_dev *hdev)
1431 {
1432 int i, cnt = 0;
1433
1434 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1435 if (hdev->hw_tc_map & BIT(i))
1436 cnt++;
1437 return cnt;
1438 }
1439
1440 static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1441 {
1442 int i, cnt = 0;
1443
1444 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1445 if (hdev->hw_tc_map & BIT(i) &&
1446 hdev->tm_info.hw_pfc_map & BIT(i))
1447 cnt++;
1448 return cnt;
1449 }
1450
1451 /* Get the number of pfc enabled TCs, which have private buffer */
1452 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1453 struct hclge_pkt_buf_alloc *buf_alloc)
1454 {
1455 struct hclge_priv_buf *priv;
1456 int i, cnt = 0;
1457
1458 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1459 priv = &buf_alloc->priv_buf[i];
1460 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1461 priv->enable)
1462 cnt++;
1463 }
1464
1465 return cnt;
1466 }
1467
1468 /* Get the number of pfc disabled TCs, which have private buffer */
1469 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1470 struct hclge_pkt_buf_alloc *buf_alloc)
1471 {
1472 struct hclge_priv_buf *priv;
1473 int i, cnt = 0;
1474
1475 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1476 priv = &buf_alloc->priv_buf[i];
1477 if (hdev->hw_tc_map & BIT(i) &&
1478 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1479 priv->enable)
1480 cnt++;
1481 }
1482
1483 return cnt;
1484 }
1485
1486 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1487 {
1488 struct hclge_priv_buf *priv;
1489 u32 rx_priv = 0;
1490 int i;
1491
1492 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1493 priv = &buf_alloc->priv_buf[i];
1494 if (priv->enable)
1495 rx_priv += priv->buf_size;
1496 }
1497 return rx_priv;
1498 }
1499
1500 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1501 {
1502 u32 i, total_tx_size = 0;
1503
1504 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1505 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
1506
1507 return total_tx_size;
1508 }
1509
1510 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1511 struct hclge_pkt_buf_alloc *buf_alloc,
1512 u32 rx_all)
1513 {
1514 u32 shared_buf_min, shared_buf_tc, shared_std;
1515 int tc_num, pfc_enable_num;
1516 u32 shared_buf;
1517 u32 rx_priv;
1518 int i;
1519
1520 tc_num = hclge_get_tc_num(hdev);
1521 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1522
1523 if (hnae3_dev_dcb_supported(hdev))
1524 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1525 else
1526 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1527
1528 shared_buf_tc = pfc_enable_num * hdev->mps +
1529 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1530 hdev->mps;
1531 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1532
1533 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
1534 if (rx_all <= rx_priv + shared_std)
1535 return false;
1536
1537 shared_buf = rx_all - rx_priv;
1538 buf_alloc->s_buf.buf_size = shared_buf;
1539 buf_alloc->s_buf.self.high = shared_buf;
1540 buf_alloc->s_buf.self.low = 2 * hdev->mps;
1541
1542 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1543 if ((hdev->hw_tc_map & BIT(i)) &&
1544 (hdev->tm_info.hw_pfc_map & BIT(i))) {
1545 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1546 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
1547 } else {
1548 buf_alloc->s_buf.tc_thrd[i].low = 0;
1549 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
1550 }
1551 }
1552
1553 return true;
1554 }
1555
1556 static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1557 struct hclge_pkt_buf_alloc *buf_alloc)
1558 {
1559 u32 i, total_size;
1560
1561 total_size = hdev->pkt_buf_size;
1562
1563 /* alloc tx buffer for all enabled tc */
1564 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1565 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1566
1567 if (total_size < HCLGE_DEFAULT_TX_BUF)
1568 return -ENOMEM;
1569
1570 if (hdev->hw_tc_map & BIT(i))
1571 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1572 else
1573 priv->tx_buf_size = 0;
1574
1575 total_size -= priv->tx_buf_size;
1576 }
1577
1578 return 0;
1579 }
1580
1581 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1582 * @hdev: pointer to struct hclge_dev
1583 * @buf_alloc: pointer to buffer calculation data
1584 * @return: 0: calculate sucessful, negative: fail
1585 */
1586 static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1587 struct hclge_pkt_buf_alloc *buf_alloc)
1588 {
1589 u32 rx_all = hdev->pkt_buf_size;
1590 int no_pfc_priv_num, pfc_priv_num;
1591 struct hclge_priv_buf *priv;
1592 int i;
1593
1594 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
1595
1596 /* When DCB is not supported, rx private
1597 * buffer is not allocated.
1598 */
1599 if (!hnae3_dev_dcb_supported(hdev)) {
1600 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1601 return -ENOMEM;
1602
1603 return 0;
1604 }
1605
1606 /* step 1, try to alloc private buffer for all enabled tc */
1607 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1608 priv = &buf_alloc->priv_buf[i];
1609 if (hdev->hw_tc_map & BIT(i)) {
1610 priv->enable = 1;
1611 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1612 priv->wl.low = hdev->mps;
1613 priv->wl.high = priv->wl.low + hdev->mps;
1614 priv->buf_size = priv->wl.high +
1615 HCLGE_DEFAULT_DV;
1616 } else {
1617 priv->wl.low = 0;
1618 priv->wl.high = 2 * hdev->mps;
1619 priv->buf_size = priv->wl.high;
1620 }
1621 } else {
1622 priv->enable = 0;
1623 priv->wl.low = 0;
1624 priv->wl.high = 0;
1625 priv->buf_size = 0;
1626 }
1627 }
1628
1629 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1630 return 0;
1631
1632 /* step 2, try to decrease the buffer size of
1633 * no pfc TC's private buffer
1634 */
1635 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1636 priv = &buf_alloc->priv_buf[i];
1637
1638 priv->enable = 0;
1639 priv->wl.low = 0;
1640 priv->wl.high = 0;
1641 priv->buf_size = 0;
1642
1643 if (!(hdev->hw_tc_map & BIT(i)))
1644 continue;
1645
1646 priv->enable = 1;
1647
1648 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1649 priv->wl.low = 128;
1650 priv->wl.high = priv->wl.low + hdev->mps;
1651 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1652 } else {
1653 priv->wl.low = 0;
1654 priv->wl.high = hdev->mps;
1655 priv->buf_size = priv->wl.high;
1656 }
1657 }
1658
1659 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1660 return 0;
1661
1662 /* step 3, try to reduce the number of pfc disabled TCs,
1663 * which have private buffer
1664 */
1665 /* get the total no pfc enable TC number, which have private buffer */
1666 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
1667
1668 /* let the last to be cleared first */
1669 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1670 priv = &buf_alloc->priv_buf[i];
1671
1672 if (hdev->hw_tc_map & BIT(i) &&
1673 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1674 /* Clear the no pfc TC private buffer */
1675 priv->wl.low = 0;
1676 priv->wl.high = 0;
1677 priv->buf_size = 0;
1678 priv->enable = 0;
1679 no_pfc_priv_num--;
1680 }
1681
1682 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1683 no_pfc_priv_num == 0)
1684 break;
1685 }
1686
1687 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1688 return 0;
1689
1690 /* step 4, try to reduce the number of pfc enabled TCs
1691 * which have private buffer.
1692 */
1693 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
1694
1695 /* let the last to be cleared first */
1696 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1697 priv = &buf_alloc->priv_buf[i];
1698
1699 if (hdev->hw_tc_map & BIT(i) &&
1700 hdev->tm_info.hw_pfc_map & BIT(i)) {
1701 /* Reduce the number of pfc TC with private buffer */
1702 priv->wl.low = 0;
1703 priv->enable = 0;
1704 priv->wl.high = 0;
1705 priv->buf_size = 0;
1706 pfc_priv_num--;
1707 }
1708
1709 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1710 pfc_priv_num == 0)
1711 break;
1712 }
1713 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1714 return 0;
1715
1716 return -ENOMEM;
1717 }
1718
1719 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1720 struct hclge_pkt_buf_alloc *buf_alloc)
1721 {
1722 struct hclge_rx_priv_buff_cmd *req;
1723 struct hclge_desc desc;
1724 int ret;
1725 int i;
1726
1727 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
1728 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
1729
1730 /* Alloc private buffer TCs */
1731 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1732 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1733
1734 req->buf_num[i] =
1735 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1736 req->buf_num[i] |=
1737 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
1738 }
1739
1740 req->shared_buf =
1741 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
1742 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1743
1744 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1745 if (ret) {
1746 dev_err(&hdev->pdev->dev,
1747 "rx private buffer alloc cmd failed %d\n", ret);
1748 return ret;
1749 }
1750
1751 return 0;
1752 }
1753
1754 #define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1755
1756 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1757 struct hclge_pkt_buf_alloc *buf_alloc)
1758 {
1759 struct hclge_rx_priv_wl_buf *req;
1760 struct hclge_priv_buf *priv;
1761 struct hclge_desc desc[2];
1762 int i, j;
1763 int ret;
1764
1765 for (i = 0; i < 2; i++) {
1766 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1767 false);
1768 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1769
1770 /* The first descriptor set the NEXT bit to 1 */
1771 if (i == 0)
1772 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1773 else
1774 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1775
1776 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1777 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1778
1779 priv = &buf_alloc->priv_buf[idx];
1780 req->tc_wl[j].high =
1781 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1782 req->tc_wl[j].high |=
1783 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
1784 HCLGE_RX_PRIV_EN_B);
1785 req->tc_wl[j].low =
1786 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1787 req->tc_wl[j].low |=
1788 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
1789 HCLGE_RX_PRIV_EN_B);
1790 }
1791 }
1792
1793 /* Send 2 descriptor at one time */
1794 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1795 if (ret) {
1796 dev_err(&hdev->pdev->dev,
1797 "rx private waterline config cmd failed %d\n",
1798 ret);
1799 return ret;
1800 }
1801 return 0;
1802 }
1803
1804 static int hclge_common_thrd_config(struct hclge_dev *hdev,
1805 struct hclge_pkt_buf_alloc *buf_alloc)
1806 {
1807 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
1808 struct hclge_rx_com_thrd *req;
1809 struct hclge_desc desc[2];
1810 struct hclge_tc_thrd *tc;
1811 int i, j;
1812 int ret;
1813
1814 for (i = 0; i < 2; i++) {
1815 hclge_cmd_setup_basic_desc(&desc[i],
1816 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1817 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1818
1819 /* The first descriptor set the NEXT bit to 1 */
1820 if (i == 0)
1821 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1822 else
1823 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1824
1825 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1826 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1827
1828 req->com_thrd[j].high =
1829 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1830 req->com_thrd[j].high |=
1831 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
1832 HCLGE_RX_PRIV_EN_B);
1833 req->com_thrd[j].low =
1834 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1835 req->com_thrd[j].low |=
1836 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
1837 HCLGE_RX_PRIV_EN_B);
1838 }
1839 }
1840
1841 /* Send 2 descriptors at one time */
1842 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1843 if (ret) {
1844 dev_err(&hdev->pdev->dev,
1845 "common threshold config cmd failed %d\n", ret);
1846 return ret;
1847 }
1848 return 0;
1849 }
1850
1851 static int hclge_common_wl_config(struct hclge_dev *hdev,
1852 struct hclge_pkt_buf_alloc *buf_alloc)
1853 {
1854 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
1855 struct hclge_rx_com_wl *req;
1856 struct hclge_desc desc;
1857 int ret;
1858
1859 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1860
1861 req = (struct hclge_rx_com_wl *)desc.data;
1862 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1863 req->com_wl.high |=
1864 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
1865 HCLGE_RX_PRIV_EN_B);
1866
1867 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1868 req->com_wl.low |=
1869 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
1870 HCLGE_RX_PRIV_EN_B);
1871
1872 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1873 if (ret) {
1874 dev_err(&hdev->pdev->dev,
1875 "common waterline config cmd failed %d\n", ret);
1876 return ret;
1877 }
1878
1879 return 0;
1880 }
1881
1882 int hclge_buffer_alloc(struct hclge_dev *hdev)
1883 {
1884 struct hclge_pkt_buf_alloc *pkt_buf;
1885 int ret;
1886
1887 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1888 if (!pkt_buf)
1889 return -ENOMEM;
1890
1891 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
1892 if (ret) {
1893 dev_err(&hdev->pdev->dev,
1894 "could not calc tx buffer size for all TCs %d\n", ret);
1895 goto out;
1896 }
1897
1898 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
1899 if (ret) {
1900 dev_err(&hdev->pdev->dev,
1901 "could not alloc tx buffers %d\n", ret);
1902 goto out;
1903 }
1904
1905 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
1906 if (ret) {
1907 dev_err(&hdev->pdev->dev,
1908 "could not calc rx priv buffer size for all TCs %d\n",
1909 ret);
1910 goto out;
1911 }
1912
1913 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
1914 if (ret) {
1915 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1916 ret);
1917 goto out;
1918 }
1919
1920 if (hnae3_dev_dcb_supported(hdev)) {
1921 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
1922 if (ret) {
1923 dev_err(&hdev->pdev->dev,
1924 "could not configure rx private waterline %d\n",
1925 ret);
1926 goto out;
1927 }
1928
1929 ret = hclge_common_thrd_config(hdev, pkt_buf);
1930 if (ret) {
1931 dev_err(&hdev->pdev->dev,
1932 "could not configure common threshold %d\n",
1933 ret);
1934 goto out;
1935 }
1936 }
1937
1938 ret = hclge_common_wl_config(hdev, pkt_buf);
1939 if (ret)
1940 dev_err(&hdev->pdev->dev,
1941 "could not configure common waterline %d\n", ret);
1942
1943 out:
1944 kfree(pkt_buf);
1945 return ret;
1946 }
1947
1948 static int hclge_init_roce_base_info(struct hclge_vport *vport)
1949 {
1950 struct hnae3_handle *roce = &vport->roce;
1951 struct hnae3_handle *nic = &vport->nic;
1952
1953 roce->rinfo.num_vectors = vport->back->num_roce_msi;
1954
1955 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1956 vport->back->num_msi_left == 0)
1957 return -EINVAL;
1958
1959 roce->rinfo.base_vector = vport->back->roce_base_vector;
1960
1961 roce->rinfo.netdev = nic->kinfo.netdev;
1962 roce->rinfo.roce_io_base = vport->back->hw.io_base;
1963
1964 roce->pdev = nic->pdev;
1965 roce->ae_algo = nic->ae_algo;
1966 roce->numa_node_mask = nic->numa_node_mask;
1967
1968 return 0;
1969 }
1970
1971 static int hclge_init_msi(struct hclge_dev *hdev)
1972 {
1973 struct pci_dev *pdev = hdev->pdev;
1974 int vectors;
1975 int i;
1976
1977 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1978 PCI_IRQ_MSI | PCI_IRQ_MSIX);
1979 if (vectors < 0) {
1980 dev_err(&pdev->dev,
1981 "failed(%d) to allocate MSI/MSI-X vectors\n",
1982 vectors);
1983 return vectors;
1984 }
1985 if (vectors < hdev->num_msi)
1986 dev_warn(&hdev->pdev->dev,
1987 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1988 hdev->num_msi, vectors);
1989
1990 hdev->num_msi = vectors;
1991 hdev->num_msi_left = vectors;
1992 hdev->base_msi_vector = pdev->irq;
1993 hdev->roce_base_vector = hdev->base_msi_vector +
1994 HCLGE_ROCE_VECTOR_OFFSET;
1995
1996 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1997 sizeof(u16), GFP_KERNEL);
1998 if (!hdev->vector_status) {
1999 pci_free_irq_vectors(pdev);
2000 return -ENOMEM;
2001 }
2002
2003 for (i = 0; i < hdev->num_msi; i++)
2004 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2005
2006 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2007 sizeof(int), GFP_KERNEL);
2008 if (!hdev->vector_irq) {
2009 pci_free_irq_vectors(pdev);
2010 return -ENOMEM;
2011 }
2012
2013 return 0;
2014 }
2015
2016 static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
2017 {
2018 struct hclge_mac *mac = &hdev->hw.mac;
2019
2020 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
2021 mac->duplex = (u8)duplex;
2022 else
2023 mac->duplex = HCLGE_MAC_FULL;
2024
2025 mac->speed = speed;
2026 }
2027
2028 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2029 {
2030 struct hclge_config_mac_speed_dup_cmd *req;
2031 struct hclge_desc desc;
2032 int ret;
2033
2034 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
2035
2036 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2037
2038 hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
2039
2040 switch (speed) {
2041 case HCLGE_MAC_SPEED_10M:
2042 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2043 HCLGE_CFG_SPEED_S, 6);
2044 break;
2045 case HCLGE_MAC_SPEED_100M:
2046 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2047 HCLGE_CFG_SPEED_S, 7);
2048 break;
2049 case HCLGE_MAC_SPEED_1G:
2050 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2051 HCLGE_CFG_SPEED_S, 0);
2052 break;
2053 case HCLGE_MAC_SPEED_10G:
2054 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2055 HCLGE_CFG_SPEED_S, 1);
2056 break;
2057 case HCLGE_MAC_SPEED_25G:
2058 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2059 HCLGE_CFG_SPEED_S, 2);
2060 break;
2061 case HCLGE_MAC_SPEED_40G:
2062 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2063 HCLGE_CFG_SPEED_S, 3);
2064 break;
2065 case HCLGE_MAC_SPEED_50G:
2066 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2067 HCLGE_CFG_SPEED_S, 4);
2068 break;
2069 case HCLGE_MAC_SPEED_100G:
2070 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2071 HCLGE_CFG_SPEED_S, 5);
2072 break;
2073 default:
2074 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
2075 return -EINVAL;
2076 }
2077
2078 hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2079 1);
2080
2081 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2082 if (ret) {
2083 dev_err(&hdev->pdev->dev,
2084 "mac speed/duplex config cmd failed %d.\n", ret);
2085 return ret;
2086 }
2087
2088 hclge_check_speed_dup(hdev, duplex, speed);
2089
2090 return 0;
2091 }
2092
2093 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2094 u8 duplex)
2095 {
2096 struct hclge_vport *vport = hclge_get_vport(handle);
2097 struct hclge_dev *hdev = vport->back;
2098
2099 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2100 }
2101
2102 static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2103 u8 *duplex)
2104 {
2105 struct hclge_query_an_speed_dup_cmd *req;
2106 struct hclge_desc desc;
2107 int speed_tmp;
2108 int ret;
2109
2110 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
2111
2112 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2113 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2114 if (ret) {
2115 dev_err(&hdev->pdev->dev,
2116 "mac speed/autoneg/duplex query cmd failed %d\n",
2117 ret);
2118 return ret;
2119 }
2120
2121 *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2122 speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2123 HCLGE_QUERY_SPEED_S);
2124
2125 ret = hclge_parse_speed(speed_tmp, speed);
2126 if (ret) {
2127 dev_err(&hdev->pdev->dev,
2128 "could not parse speed(=%d), %d\n", speed_tmp, ret);
2129 return -EIO;
2130 }
2131
2132 return 0;
2133 }
2134
2135 static int hclge_query_autoneg_result(struct hclge_dev *hdev)
2136 {
2137 struct hclge_mac *mac = &hdev->hw.mac;
2138 struct hclge_query_an_speed_dup_cmd *req;
2139 struct hclge_desc desc;
2140 int ret;
2141
2142 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
2143
2144 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2145 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2146 if (ret) {
2147 dev_err(&hdev->pdev->dev,
2148 "autoneg result query cmd failed %d.\n", ret);
2149 return ret;
2150 }
2151
2152 mac->autoneg = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_AN_B);
2153
2154 return 0;
2155 }
2156
2157 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2158 {
2159 struct hclge_config_auto_neg_cmd *req;
2160 struct hclge_desc desc;
2161 u32 flag = 0;
2162 int ret;
2163
2164 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2165
2166 req = (struct hclge_config_auto_neg_cmd *)desc.data;
2167 hnae_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2168 req->cfg_an_cmd_flag = cpu_to_le32(flag);
2169
2170 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2171 if (ret) {
2172 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2173 ret);
2174 return ret;
2175 }
2176
2177 return 0;
2178 }
2179
2180 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2181 {
2182 struct hclge_vport *vport = hclge_get_vport(handle);
2183 struct hclge_dev *hdev = vport->back;
2184
2185 return hclge_set_autoneg_en(hdev, enable);
2186 }
2187
2188 static int hclge_get_autoneg(struct hnae3_handle *handle)
2189 {
2190 struct hclge_vport *vport = hclge_get_vport(handle);
2191 struct hclge_dev *hdev = vport->back;
2192
2193 hclge_query_autoneg_result(hdev);
2194
2195 return hdev->hw.mac.autoneg;
2196 }
2197
2198 static int hclge_mac_init(struct hclge_dev *hdev)
2199 {
2200 struct hclge_mac *mac = &hdev->hw.mac;
2201 int ret;
2202
2203 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2204 if (ret) {
2205 dev_err(&hdev->pdev->dev,
2206 "Config mac speed dup fail ret=%d\n", ret);
2207 return ret;
2208 }
2209
2210 mac->link = 0;
2211
2212 /* Initialize the MTA table work mode */
2213 hdev->accept_mta_mc = true;
2214 hdev->enable_mta = true;
2215 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2216
2217 ret = hclge_set_mta_filter_mode(hdev,
2218 hdev->mta_mac_sel_type,
2219 hdev->enable_mta);
2220 if (ret) {
2221 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2222 ret);
2223 return ret;
2224 }
2225
2226 return hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc);
2227 }
2228
2229 static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2230 {
2231 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2232 schedule_work(&hdev->rst_service_task);
2233 }
2234
2235 static void hclge_task_schedule(struct hclge_dev *hdev)
2236 {
2237 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2238 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2239 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2240 (void)schedule_work(&hdev->service_task);
2241 }
2242
2243 static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2244 {
2245 struct hclge_link_status_cmd *req;
2246 struct hclge_desc desc;
2247 int link_status;
2248 int ret;
2249
2250 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2251 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2252 if (ret) {
2253 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2254 ret);
2255 return ret;
2256 }
2257
2258 req = (struct hclge_link_status_cmd *)desc.data;
2259 link_status = req->status & HCLGE_LINK_STATUS;
2260
2261 return !!link_status;
2262 }
2263
2264 static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2265 {
2266 int mac_state;
2267 int link_stat;
2268
2269 mac_state = hclge_get_mac_link_status(hdev);
2270
2271 if (hdev->hw.mac.phydev) {
2272 if (!genphy_read_status(hdev->hw.mac.phydev))
2273 link_stat = mac_state &
2274 hdev->hw.mac.phydev->link;
2275 else
2276 link_stat = 0;
2277
2278 } else {
2279 link_stat = mac_state;
2280 }
2281
2282 return !!link_stat;
2283 }
2284
2285 static void hclge_update_link_status(struct hclge_dev *hdev)
2286 {
2287 struct hnae3_client *client = hdev->nic_client;
2288 struct hnae3_handle *handle;
2289 int state;
2290 int i;
2291
2292 if (!client)
2293 return;
2294 state = hclge_get_mac_phy_link(hdev);
2295 if (state != hdev->hw.mac.link) {
2296 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2297 handle = &hdev->vport[i].nic;
2298 client->ops->link_status_change(handle, state);
2299 }
2300 hdev->hw.mac.link = state;
2301 }
2302 }
2303
2304 static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2305 {
2306 struct hclge_mac mac = hdev->hw.mac;
2307 u8 duplex;
2308 int speed;
2309 int ret;
2310
2311 /* get the speed and duplex as autoneg'result from mac cmd when phy
2312 * doesn't exit.
2313 */
2314 if (mac.phydev || !mac.autoneg)
2315 return 0;
2316
2317 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2318 if (ret) {
2319 dev_err(&hdev->pdev->dev,
2320 "mac autoneg/speed/duplex query failed %d\n", ret);
2321 return ret;
2322 }
2323
2324 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2325 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2326 if (ret) {
2327 dev_err(&hdev->pdev->dev,
2328 "mac speed/duplex config failed %d\n", ret);
2329 return ret;
2330 }
2331 }
2332
2333 return 0;
2334 }
2335
2336 static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2337 {
2338 struct hclge_vport *vport = hclge_get_vport(handle);
2339 struct hclge_dev *hdev = vport->back;
2340
2341 return hclge_update_speed_duplex(hdev);
2342 }
2343
2344 static int hclge_get_status(struct hnae3_handle *handle)
2345 {
2346 struct hclge_vport *vport = hclge_get_vport(handle);
2347 struct hclge_dev *hdev = vport->back;
2348
2349 hclge_update_link_status(hdev);
2350
2351 return hdev->hw.mac.link;
2352 }
2353
2354 static void hclge_service_timer(struct timer_list *t)
2355 {
2356 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
2357
2358 mod_timer(&hdev->service_timer, jiffies + HZ);
2359 hclge_task_schedule(hdev);
2360 }
2361
2362 static void hclge_service_complete(struct hclge_dev *hdev)
2363 {
2364 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2365
2366 /* Flush memory before next watchdog */
2367 smp_mb__before_atomic();
2368 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2369 }
2370
2371 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2372 {
2373 u32 rst_src_reg;
2374
2375 /* fetch the events from their corresponding regs */
2376 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);
2377
2378 /* check for vector0 reset event sources */
2379 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2380 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2381 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2382 return HCLGE_VECTOR0_EVENT_RST;
2383 }
2384
2385 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2386 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2387 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2388 return HCLGE_VECTOR0_EVENT_RST;
2389 }
2390
2391 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2392 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2393 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2394 return HCLGE_VECTOR0_EVENT_RST;
2395 }
2396
2397 /* mailbox event sharing vector 0 interrupt would be placed here */
2398
2399 return HCLGE_VECTOR0_EVENT_OTHER;
2400 }
2401
2402 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2403 u32 regclr)
2404 {
2405 if (event_type == HCLGE_VECTOR0_EVENT_RST)
2406 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
2407
2408 /* mailbox event sharing vector 0 interrupt would be placed here */
2409 }
2410
2411 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2412 {
2413 writel(enable ? 1 : 0, vector->addr);
2414 }
2415
2416 static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2417 {
2418 struct hclge_dev *hdev = data;
2419 u32 event_cause;
2420 u32 clearval;
2421
2422 hclge_enable_vector(&hdev->misc_vector, false);
2423 event_cause = hclge_check_event_cause(hdev, &clearval);
2424
2425 /* vector 0 interrupt is shared with reset and mailbox source events.
2426 * For now, we are not handling mailbox events.
2427 */
2428 switch (event_cause) {
2429 case HCLGE_VECTOR0_EVENT_RST:
2430 hclge_reset_task_schedule(hdev);
2431 break;
2432 default:
2433 dev_dbg(&hdev->pdev->dev,
2434 "received unknown or unhandled event of vector0\n");
2435 break;
2436 }
2437
2438 /* we should clear the source of interrupt */
2439 hclge_clear_event_cause(hdev, event_cause, clearval);
2440 hclge_enable_vector(&hdev->misc_vector, true);
2441
2442 return IRQ_HANDLED;
2443 }
2444
2445 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2446 {
2447 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2448 hdev->num_msi_left += 1;
2449 hdev->num_msi_used -= 1;
2450 }
2451
2452 static void hclge_get_misc_vector(struct hclge_dev *hdev)
2453 {
2454 struct hclge_misc_vector *vector = &hdev->misc_vector;
2455
2456 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2457
2458 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2459 hdev->vector_status[0] = 0;
2460
2461 hdev->num_msi_left -= 1;
2462 hdev->num_msi_used += 1;
2463 }
2464
2465 static int hclge_misc_irq_init(struct hclge_dev *hdev)
2466 {
2467 int ret;
2468
2469 hclge_get_misc_vector(hdev);
2470
2471 /* this would be explicitly freed in the end */
2472 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2473 0, "hclge_misc", hdev);
2474 if (ret) {
2475 hclge_free_vector(hdev, 0);
2476 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2477 hdev->misc_vector.vector_irq);
2478 }
2479
2480 return ret;
2481 }
2482
2483 static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2484 {
2485 free_irq(hdev->misc_vector.vector_irq, hdev);
2486 hclge_free_vector(hdev, 0);
2487 }
2488
2489 static int hclge_notify_client(struct hclge_dev *hdev,
2490 enum hnae3_reset_notify_type type)
2491 {
2492 struct hnae3_client *client = hdev->nic_client;
2493 u16 i;
2494
2495 if (!client->ops->reset_notify)
2496 return -EOPNOTSUPP;
2497
2498 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2499 struct hnae3_handle *handle = &hdev->vport[i].nic;
2500 int ret;
2501
2502 ret = client->ops->reset_notify(handle, type);
2503 if (ret)
2504 return ret;
2505 }
2506
2507 return 0;
2508 }
2509
2510 static int hclge_reset_wait(struct hclge_dev *hdev)
2511 {
2512 #define HCLGE_RESET_WATI_MS 100
2513 #define HCLGE_RESET_WAIT_CNT 5
2514 u32 val, reg, reg_bit;
2515 u32 cnt = 0;
2516
2517 switch (hdev->reset_type) {
2518 case HNAE3_GLOBAL_RESET:
2519 reg = HCLGE_GLOBAL_RESET_REG;
2520 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2521 break;
2522 case HNAE3_CORE_RESET:
2523 reg = HCLGE_GLOBAL_RESET_REG;
2524 reg_bit = HCLGE_CORE_RESET_BIT;
2525 break;
2526 case HNAE3_FUNC_RESET:
2527 reg = HCLGE_FUN_RST_ING;
2528 reg_bit = HCLGE_FUN_RST_ING_B;
2529 break;
2530 default:
2531 dev_err(&hdev->pdev->dev,
2532 "Wait for unsupported reset type: %d\n",
2533 hdev->reset_type);
2534 return -EINVAL;
2535 }
2536
2537 val = hclge_read_dev(&hdev->hw, reg);
2538 while (hnae_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
2539 msleep(HCLGE_RESET_WATI_MS);
2540 val = hclge_read_dev(&hdev->hw, reg);
2541 cnt++;
2542 }
2543
2544 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2545 dev_warn(&hdev->pdev->dev,
2546 "Wait for reset timeout: %d\n", hdev->reset_type);
2547 return -EBUSY;
2548 }
2549
2550 return 0;
2551 }
2552
2553 static int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
2554 {
2555 struct hclge_desc desc;
2556 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2557 int ret;
2558
2559 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2560 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_MAC_B, 0);
2561 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2562 req->fun_reset_vfid = func_id;
2563
2564 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2565 if (ret)
2566 dev_err(&hdev->pdev->dev,
2567 "send function reset cmd fail, status =%d\n", ret);
2568
2569 return ret;
2570 }
2571
2572 static void hclge_do_reset(struct hclge_dev *hdev, enum hnae3_reset_type type)
2573 {
2574 struct pci_dev *pdev = hdev->pdev;
2575 u32 val;
2576
2577 switch (type) {
2578 case HNAE3_GLOBAL_RESET:
2579 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2580 hnae_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2581 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2582 dev_info(&pdev->dev, "Global Reset requested\n");
2583 break;
2584 case HNAE3_CORE_RESET:
2585 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2586 hnae_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2587 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2588 dev_info(&pdev->dev, "Core Reset requested\n");
2589 break;
2590 case HNAE3_FUNC_RESET:
2591 dev_info(&pdev->dev, "PF Reset requested\n");
2592 hclge_func_reset_cmd(hdev, 0);
2593 /* schedule again to check later */
2594 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2595 hclge_reset_task_schedule(hdev);
2596 break;
2597 default:
2598 dev_warn(&pdev->dev,
2599 "Unsupported reset type: %d\n", type);
2600 break;
2601 }
2602 }
2603
2604 static void hclge_reset_event(struct hnae3_handle *handle,
2605 enum hnae3_reset_type reset)
2606 {
2607 struct hclge_vport *vport = hclge_get_vport(handle);
2608 struct hclge_dev *hdev = vport->back;
2609
2610 dev_info(&hdev->pdev->dev,
2611 "Receive reset event , reset_type is %d", reset);
2612
2613 switch (reset) {
2614 case HNAE3_FUNC_RESET:
2615 case HNAE3_CORE_RESET:
2616 case HNAE3_GLOBAL_RESET:
2617 /* request reset & schedule reset task */
2618 set_bit(reset, &hdev->reset_request);
2619 hclge_reset_task_schedule(hdev);
2620 break;
2621 default:
2622 dev_warn(&hdev->pdev->dev, "Unsupported reset event:%d", reset);
2623 break;
2624 }
2625 }
2626
2627 static void hclge_reset_subtask(struct hclge_dev *hdev)
2628 {
2629 bool do_reset;
2630
2631 do_reset = hdev->reset_type != HNAE3_NONE_RESET;
2632
2633
2634 if (hdev->reset_type == HNAE3_NONE_RESET)
2635 return;
2636
2637 switch (hdev->reset_type) {
2638 case HNAE3_FUNC_RESET:
2639 case HNAE3_CORE_RESET:
2640 case HNAE3_GLOBAL_RESET:
2641 case HNAE3_IMP_RESET:
2642 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2643
2644 if (do_reset)
2645 hclge_do_reset(hdev, hdev->reset_type);
2646 else
2647 set_bit(HCLGE_STATE_RESET_INT, &hdev->state);
2648
2649 if (!hclge_reset_wait(hdev)) {
2650 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2651 hclge_reset_ae_dev(hdev->ae_dev);
2652 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2653 clear_bit(HCLGE_STATE_RESET_INT, &hdev->state);
2654 }
2655 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2656 break;
2657 default:
2658 dev_err(&hdev->pdev->dev, "Unsupported reset type:%d\n",
2659 hdev->reset_type);
2660 break;
2661 }
2662 hdev->reset_type = HNAE3_NONE_RESET;
2663 }
2664
2665 static void hclge_reset_service_task(struct work_struct *work)
2666 {
2667 struct hclge_dev *hdev =
2668 container_of(work, struct hclge_dev, rst_service_task);
2669
2670 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2671 return;
2672
2673 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2674
2675 hclge_reset_subtask(hdev);
2676
2677 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
2678 }
2679
2680 static void hclge_service_task(struct work_struct *work)
2681 {
2682 struct hclge_dev *hdev =
2683 container_of(work, struct hclge_dev, service_task);
2684
2685 hclge_update_speed_duplex(hdev);
2686 hclge_update_link_status(hdev);
2687 hclge_update_stats_for_all(hdev);
2688 hclge_service_complete(hdev);
2689 }
2690
2691 static void hclge_disable_sriov(struct hclge_dev *hdev)
2692 {
2693 /* If our VFs are assigned we cannot shut down SR-IOV
2694 * without causing issues, so just leave the hardware
2695 * available but disabled
2696 */
2697 if (pci_vfs_assigned(hdev->pdev)) {
2698 dev_warn(&hdev->pdev->dev,
2699 "disabling driver while VFs are assigned\n");
2700 return;
2701 }
2702
2703 pci_disable_sriov(hdev->pdev);
2704 }
2705
2706 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2707 {
2708 /* VF handle has no client */
2709 if (!handle->client)
2710 return container_of(handle, struct hclge_vport, nic);
2711 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2712 return container_of(handle, struct hclge_vport, roce);
2713 else
2714 return container_of(handle, struct hclge_vport, nic);
2715 }
2716
2717 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2718 struct hnae3_vector_info *vector_info)
2719 {
2720 struct hclge_vport *vport = hclge_get_vport(handle);
2721 struct hnae3_vector_info *vector = vector_info;
2722 struct hclge_dev *hdev = vport->back;
2723 int alloc = 0;
2724 int i, j;
2725
2726 vector_num = min(hdev->num_msi_left, vector_num);
2727
2728 for (j = 0; j < vector_num; j++) {
2729 for (i = 1; i < hdev->num_msi; i++) {
2730 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2731 vector->vector = pci_irq_vector(hdev->pdev, i);
2732 vector->io_addr = hdev->hw.io_base +
2733 HCLGE_VECTOR_REG_BASE +
2734 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2735 vport->vport_id *
2736 HCLGE_VECTOR_VF_OFFSET;
2737 hdev->vector_status[i] = vport->vport_id;
2738 hdev->vector_irq[i] = vector->vector;
2739
2740 vector++;
2741 alloc++;
2742
2743 break;
2744 }
2745 }
2746 }
2747 hdev->num_msi_left -= alloc;
2748 hdev->num_msi_used += alloc;
2749
2750 return alloc;
2751 }
2752
2753 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2754 {
2755 int i;
2756
2757 for (i = 0; i < hdev->num_msi; i++)
2758 if (vector == hdev->vector_irq[i])
2759 return i;
2760
2761 return -EINVAL;
2762 }
2763
2764 static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2765 {
2766 return HCLGE_RSS_KEY_SIZE;
2767 }
2768
2769 static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2770 {
2771 return HCLGE_RSS_IND_TBL_SIZE;
2772 }
2773
2774 static int hclge_get_rss_algo(struct hclge_dev *hdev)
2775 {
2776 struct hclge_rss_config_cmd *req;
2777 struct hclge_desc desc;
2778 int rss_hash_algo;
2779 int ret;
2780
2781 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, true);
2782
2783 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2784 if (ret) {
2785 dev_err(&hdev->pdev->dev,
2786 "Get link status error, status =%d\n", ret);
2787 return ret;
2788 }
2789
2790 req = (struct hclge_rss_config_cmd *)desc.data;
2791 rss_hash_algo = (req->hash_config & HCLGE_RSS_HASH_ALGO_MASK);
2792
2793 if (rss_hash_algo == HCLGE_RSS_HASH_ALGO_TOEPLITZ)
2794 return ETH_RSS_HASH_TOP;
2795
2796 return -EINVAL;
2797 }
2798
2799 static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2800 const u8 hfunc, const u8 *key)
2801 {
2802 struct hclge_rss_config_cmd *req;
2803 struct hclge_desc desc;
2804 int key_offset;
2805 int key_size;
2806 int ret;
2807
2808 req = (struct hclge_rss_config_cmd *)desc.data;
2809
2810 for (key_offset = 0; key_offset < 3; key_offset++) {
2811 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2812 false);
2813
2814 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
2815 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
2816
2817 if (key_offset == 2)
2818 key_size =
2819 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
2820 else
2821 key_size = HCLGE_RSS_HASH_KEY_NUM;
2822
2823 memcpy(req->hash_key,
2824 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
2825
2826 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2827 if (ret) {
2828 dev_err(&hdev->pdev->dev,
2829 "Configure RSS config fail, status = %d\n",
2830 ret);
2831 return ret;
2832 }
2833 }
2834 return 0;
2835 }
2836
2837 static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u32 *indir)
2838 {
2839 struct hclge_rss_indirection_table_cmd *req;
2840 struct hclge_desc desc;
2841 int i, j;
2842 int ret;
2843
2844 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
2845
2846 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
2847 hclge_cmd_setup_basic_desc
2848 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
2849
2850 req->start_table_index =
2851 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
2852 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
2853
2854 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
2855 req->rss_result[j] =
2856 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
2857
2858 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2859 if (ret) {
2860 dev_err(&hdev->pdev->dev,
2861 "Configure rss indir table fail,status = %d\n",
2862 ret);
2863 return ret;
2864 }
2865 }
2866 return 0;
2867 }
2868
2869 static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
2870 u16 *tc_size, u16 *tc_offset)
2871 {
2872 struct hclge_rss_tc_mode_cmd *req;
2873 struct hclge_desc desc;
2874 int ret;
2875 int i;
2876
2877 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
2878 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
2879
2880 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2881 u16 mode = 0;
2882
2883 hnae_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
2884 hnae_set_field(mode, HCLGE_RSS_TC_SIZE_M,
2885 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
2886 hnae_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
2887 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
2888
2889 req->rss_tc_mode[i] = cpu_to_le16(mode);
2890 }
2891
2892 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2893 if (ret) {
2894 dev_err(&hdev->pdev->dev,
2895 "Configure rss tc mode fail, status = %d\n", ret);
2896 return ret;
2897 }
2898
2899 return 0;
2900 }
2901
2902 static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
2903 {
2904 struct hclge_rss_input_tuple_cmd *req;
2905 struct hclge_desc desc;
2906 int ret;
2907
2908 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
2909
2910 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
2911 req->ipv4_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2912 req->ipv4_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2913 req->ipv4_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
2914 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2915 req->ipv6_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2916 req->ipv6_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2917 req->ipv6_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
2918 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2919 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2920 if (ret) {
2921 dev_err(&hdev->pdev->dev,
2922 "Configure rss input fail, status = %d\n", ret);
2923 return ret;
2924 }
2925
2926 return 0;
2927 }
2928
2929 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
2930 u8 *key, u8 *hfunc)
2931 {
2932 struct hclge_vport *vport = hclge_get_vport(handle);
2933 struct hclge_dev *hdev = vport->back;
2934 int i;
2935
2936 /* Get hash algorithm */
2937 if (hfunc)
2938 *hfunc = hclge_get_rss_algo(hdev);
2939
2940 /* Get the RSS Key required by the user */
2941 if (key)
2942 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
2943
2944 /* Get indirect table */
2945 if (indir)
2946 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2947 indir[i] = vport->rss_indirection_tbl[i];
2948
2949 return 0;
2950 }
2951
2952 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
2953 const u8 *key, const u8 hfunc)
2954 {
2955 struct hclge_vport *vport = hclge_get_vport(handle);
2956 struct hclge_dev *hdev = vport->back;
2957 u8 hash_algo;
2958 int ret, i;
2959
2960 /* Set the RSS Hash Key if specififed by the user */
2961 if (key) {
2962 /* Update the shadow RSS key with user specified qids */
2963 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
2964
2965 if (hfunc == ETH_RSS_HASH_TOP ||
2966 hfunc == ETH_RSS_HASH_NO_CHANGE)
2967 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
2968 else
2969 return -EINVAL;
2970 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
2971 if (ret)
2972 return ret;
2973 }
2974
2975 /* Update the shadow RSS table with user specified qids */
2976 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2977 vport->rss_indirection_tbl[i] = indir[i];
2978
2979 /* Update the hardware */
2980 ret = hclge_set_rss_indir_table(hdev, indir);
2981 return ret;
2982 }
2983
2984 static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
2985 {
2986 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
2987
2988 if (nfc->data & RXH_L4_B_2_3)
2989 hash_sets |= HCLGE_D_PORT_BIT;
2990 else
2991 hash_sets &= ~HCLGE_D_PORT_BIT;
2992
2993 if (nfc->data & RXH_IP_SRC)
2994 hash_sets |= HCLGE_S_IP_BIT;
2995 else
2996 hash_sets &= ~HCLGE_S_IP_BIT;
2997
2998 if (nfc->data & RXH_IP_DST)
2999 hash_sets |= HCLGE_D_IP_BIT;
3000 else
3001 hash_sets &= ~HCLGE_D_IP_BIT;
3002
3003 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3004 hash_sets |= HCLGE_V_TAG_BIT;
3005
3006 return hash_sets;
3007 }
3008
3009 static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3010 struct ethtool_rxnfc *nfc)
3011 {
3012 struct hclge_vport *vport = hclge_get_vport(handle);
3013 struct hclge_dev *hdev = vport->back;
3014 struct hclge_rss_input_tuple_cmd *req;
3015 struct hclge_desc desc;
3016 u8 tuple_sets;
3017 int ret;
3018
3019 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3020 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3021 return -EINVAL;
3022
3023 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3024 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3025 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3026 if (ret) {
3027 dev_err(&hdev->pdev->dev,
3028 "Read rss tuple fail, status = %d\n", ret);
3029 return ret;
3030 }
3031
3032 hclge_cmd_reuse_desc(&desc, false);
3033
3034 tuple_sets = hclge_get_rss_hash_bits(nfc);
3035 switch (nfc->flow_type) {
3036 case TCP_V4_FLOW:
3037 req->ipv4_tcp_en = tuple_sets;
3038 break;
3039 case TCP_V6_FLOW:
3040 req->ipv6_tcp_en = tuple_sets;
3041 break;
3042 case UDP_V4_FLOW:
3043 req->ipv4_udp_en = tuple_sets;
3044 break;
3045 case UDP_V6_FLOW:
3046 req->ipv6_udp_en = tuple_sets;
3047 break;
3048 case SCTP_V4_FLOW:
3049 req->ipv4_sctp_en = tuple_sets;
3050 break;
3051 case SCTP_V6_FLOW:
3052 if ((nfc->data & RXH_L4_B_0_1) ||
3053 (nfc->data & RXH_L4_B_2_3))
3054 return -EINVAL;
3055
3056 req->ipv6_sctp_en = tuple_sets;
3057 break;
3058 case IPV4_FLOW:
3059 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3060 break;
3061 case IPV6_FLOW:
3062 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3063 break;
3064 default:
3065 return -EINVAL;
3066 }
3067
3068 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3069 if (ret)
3070 dev_err(&hdev->pdev->dev,
3071 "Set rss tuple fail, status = %d\n", ret);
3072
3073 return ret;
3074 }
3075
3076 static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3077 struct ethtool_rxnfc *nfc)
3078 {
3079 struct hclge_vport *vport = hclge_get_vport(handle);
3080 struct hclge_dev *hdev = vport->back;
3081 struct hclge_rss_input_tuple_cmd *req;
3082 struct hclge_desc desc;
3083 u8 tuple_sets;
3084 int ret;
3085
3086 nfc->data = 0;
3087
3088 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3089 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3090 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3091 if (ret) {
3092 dev_err(&hdev->pdev->dev,
3093 "Read rss tuple fail, status = %d\n", ret);
3094 return ret;
3095 }
3096
3097 switch (nfc->flow_type) {
3098 case TCP_V4_FLOW:
3099 tuple_sets = req->ipv4_tcp_en;
3100 break;
3101 case UDP_V4_FLOW:
3102 tuple_sets = req->ipv4_udp_en;
3103 break;
3104 case TCP_V6_FLOW:
3105 tuple_sets = req->ipv6_tcp_en;
3106 break;
3107 case UDP_V6_FLOW:
3108 tuple_sets = req->ipv6_udp_en;
3109 break;
3110 case SCTP_V4_FLOW:
3111 tuple_sets = req->ipv4_sctp_en;
3112 break;
3113 case SCTP_V6_FLOW:
3114 tuple_sets = req->ipv6_sctp_en;
3115 break;
3116 case IPV4_FLOW:
3117 case IPV6_FLOW:
3118 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3119 break;
3120 default:
3121 return -EINVAL;
3122 }
3123
3124 if (!tuple_sets)
3125 return 0;
3126
3127 if (tuple_sets & HCLGE_D_PORT_BIT)
3128 nfc->data |= RXH_L4_B_2_3;
3129 if (tuple_sets & HCLGE_S_PORT_BIT)
3130 nfc->data |= RXH_L4_B_0_1;
3131 if (tuple_sets & HCLGE_D_IP_BIT)
3132 nfc->data |= RXH_IP_DST;
3133 if (tuple_sets & HCLGE_S_IP_BIT)
3134 nfc->data |= RXH_IP_SRC;
3135
3136 return 0;
3137 }
3138
3139 static int hclge_get_tc_size(struct hnae3_handle *handle)
3140 {
3141 struct hclge_vport *vport = hclge_get_vport(handle);
3142 struct hclge_dev *hdev = vport->back;
3143
3144 return hdev->rss_size_max;
3145 }
3146
3147 int hclge_rss_init_hw(struct hclge_dev *hdev)
3148 {
3149 const u8 hfunc = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3150 struct hclge_vport *vport = hdev->vport;
3151 u16 tc_offset[HCLGE_MAX_TC_NUM];
3152 u8 rss_key[HCLGE_RSS_KEY_SIZE];
3153 u16 tc_valid[HCLGE_MAX_TC_NUM];
3154 u16 tc_size[HCLGE_MAX_TC_NUM];
3155 u32 *rss_indir = NULL;
3156 u16 rss_size = 0, roundup_size;
3157 const u8 *key;
3158 int i, ret, j;
3159
3160 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
3161 if (!rss_indir)
3162 return -ENOMEM;
3163
3164 /* Get default RSS key */
3165 netdev_rss_key_fill(rss_key, HCLGE_RSS_KEY_SIZE);
3166
3167 /* Initialize RSS indirect table for each vport */
3168 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3169 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) {
3170 vport[j].rss_indirection_tbl[i] =
3171 i % vport[j].alloc_rss_size;
3172
3173 /* vport 0 is for PF */
3174 if (j != 0)
3175 continue;
3176
3177 rss_size = vport[j].alloc_rss_size;
3178 rss_indir[i] = vport[j].rss_indirection_tbl[i];
3179 }
3180 }
3181 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3182 if (ret)
3183 goto err;
3184
3185 key = rss_key;
3186 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3187 if (ret)
3188 goto err;
3189
3190 ret = hclge_set_rss_input_tuple(hdev);
3191 if (ret)
3192 goto err;
3193
3194 /* Each TC have the same queue size, and tc_size set to hardware is
3195 * the log2 of roundup power of two of rss_size, the acutal queue
3196 * size is limited by indirection table.
3197 */
3198 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3199 dev_err(&hdev->pdev->dev,
3200 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3201 rss_size);
3202 ret = -EINVAL;
3203 goto err;
3204 }
3205
3206 roundup_size = roundup_pow_of_two(rss_size);
3207 roundup_size = ilog2(roundup_size);
3208
3209 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3210 tc_valid[i] = 0;
3211
3212 if (!(hdev->hw_tc_map & BIT(i)))
3213 continue;
3214
3215 tc_valid[i] = 1;
3216 tc_size[i] = roundup_size;
3217 tc_offset[i] = rss_size * i;
3218 }
3219
3220 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3221
3222 err:
3223 kfree(rss_indir);
3224
3225 return ret;
3226 }
3227
3228 int hclge_map_vport_ring_to_vector(struct hclge_vport *vport, int vector_id,
3229 struct hnae3_ring_chain_node *ring_chain)
3230 {
3231 struct hclge_dev *hdev = vport->back;
3232 struct hclge_ctrl_vector_chain_cmd *req;
3233 struct hnae3_ring_chain_node *node;
3234 struct hclge_desc desc;
3235 int ret;
3236 int i;
3237
3238 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ADD_RING_TO_VECTOR, false);
3239
3240 req = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3241 req->int_vector_id = vector_id;
3242
3243 i = 0;
3244 for (node = ring_chain; node; node = node->next) {
3245 u16 type_and_id = 0;
3246
3247 hnae_set_field(type_and_id, HCLGE_INT_TYPE_M, HCLGE_INT_TYPE_S,
3248 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
3249 hnae_set_field(type_and_id, HCLGE_TQP_ID_M, HCLGE_TQP_ID_S,
3250 node->tqp_index);
3251 hnae_set_field(type_and_id, HCLGE_INT_GL_IDX_M,
3252 HCLGE_INT_GL_IDX_S,
3253 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
3254 req->tqp_type_and_id[i] = cpu_to_le16(type_and_id);
3255 req->vfid = vport->vport_id;
3256
3257 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3258 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
3259
3260 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3261 if (ret) {
3262 dev_err(&hdev->pdev->dev,
3263 "Map TQP fail, status is %d.\n",
3264 ret);
3265 return ret;
3266 }
3267 i = 0;
3268
3269 hclge_cmd_setup_basic_desc(&desc,
3270 HCLGE_OPC_ADD_RING_TO_VECTOR,
3271 false);
3272 req->int_vector_id = vector_id;
3273 }
3274 }
3275
3276 if (i > 0) {
3277 req->int_cause_num = i;
3278
3279 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3280 if (ret) {
3281 dev_err(&hdev->pdev->dev,
3282 "Map TQP fail, status is %d.\n", ret);
3283 return ret;
3284 }
3285 }
3286
3287 return 0;
3288 }
3289
3290 static int hclge_map_handle_ring_to_vector(
3291 struct hnae3_handle *handle, int vector,
3292 struct hnae3_ring_chain_node *ring_chain)
3293 {
3294 struct hclge_vport *vport = hclge_get_vport(handle);
3295 struct hclge_dev *hdev = vport->back;
3296 int vector_id;
3297
3298 vector_id = hclge_get_vector_index(hdev, vector);
3299 if (vector_id < 0) {
3300 dev_err(&hdev->pdev->dev,
3301 "Get vector index fail. ret =%d\n", vector_id);
3302 return vector_id;
3303 }
3304
3305 return hclge_map_vport_ring_to_vector(vport, vector_id, ring_chain);
3306 }
3307
3308 static int hclge_unmap_ring_from_vector(
3309 struct hnae3_handle *handle, int vector,
3310 struct hnae3_ring_chain_node *ring_chain)
3311 {
3312 struct hclge_vport *vport = hclge_get_vport(handle);
3313 struct hclge_dev *hdev = vport->back;
3314 struct hclge_ctrl_vector_chain_cmd *req;
3315 struct hnae3_ring_chain_node *node;
3316 struct hclge_desc desc;
3317 int i, vector_id;
3318 int ret;
3319
3320 vector_id = hclge_get_vector_index(hdev, vector);
3321 if (vector_id < 0) {
3322 dev_err(&handle->pdev->dev,
3323 "Get vector index fail. ret =%d\n", vector_id);
3324 return vector_id;
3325 }
3326
3327 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_DEL_RING_TO_VECTOR, false);
3328
3329 req = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3330 req->int_vector_id = vector_id;
3331
3332 i = 0;
3333 for (node = ring_chain; node; node = node->next) {
3334 u16 type_and_id = 0;
3335
3336 hnae_set_field(type_and_id, HCLGE_INT_TYPE_M, HCLGE_INT_TYPE_S,
3337 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
3338 hnae_set_field(type_and_id, HCLGE_TQP_ID_M, HCLGE_TQP_ID_S,
3339 node->tqp_index);
3340 hnae_set_field(type_and_id, HCLGE_INT_GL_IDX_M,
3341 HCLGE_INT_GL_IDX_S,
3342 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
3343
3344 req->tqp_type_and_id[i] = cpu_to_le16(type_and_id);
3345 req->vfid = vport->vport_id;
3346
3347 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3348 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
3349
3350 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3351 if (ret) {
3352 dev_err(&hdev->pdev->dev,
3353 "Unmap TQP fail, status is %d.\n",
3354 ret);
3355 return ret;
3356 }
3357 i = 0;
3358 hclge_cmd_setup_basic_desc(&desc,
3359 HCLGE_OPC_DEL_RING_TO_VECTOR,
3360 false);
3361 req->int_vector_id = vector_id;
3362 }
3363 }
3364
3365 if (i > 0) {
3366 req->int_cause_num = i;
3367
3368 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3369 if (ret) {
3370 dev_err(&hdev->pdev->dev,
3371 "Unmap TQP fail, status is %d.\n", ret);
3372 return ret;
3373 }
3374 }
3375
3376 return 0;
3377 }
3378
3379 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3380 struct hclge_promisc_param *param)
3381 {
3382 struct hclge_promisc_cfg_cmd *req;
3383 struct hclge_desc desc;
3384 int ret;
3385
3386 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3387
3388 req = (struct hclge_promisc_cfg_cmd *)desc.data;
3389 req->vf_id = param->vf_id;
3390 req->flag = (param->enable << HCLGE_PROMISC_EN_B);
3391
3392 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3393 if (ret) {
3394 dev_err(&hdev->pdev->dev,
3395 "Set promisc mode fail, status is %d.\n", ret);
3396 return ret;
3397 }
3398 return 0;
3399 }
3400
3401 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3402 bool en_mc, bool en_bc, int vport_id)
3403 {
3404 if (!param)
3405 return;
3406
3407 memset(param, 0, sizeof(struct hclge_promisc_param));
3408 if (en_uc)
3409 param->enable = HCLGE_PROMISC_EN_UC;
3410 if (en_mc)
3411 param->enable |= HCLGE_PROMISC_EN_MC;
3412 if (en_bc)
3413 param->enable |= HCLGE_PROMISC_EN_BC;
3414 param->vf_id = vport_id;
3415 }
3416
3417 static void hclge_set_promisc_mode(struct hnae3_handle *handle, u32 en)
3418 {
3419 struct hclge_vport *vport = hclge_get_vport(handle);
3420 struct hclge_dev *hdev = vport->back;
3421 struct hclge_promisc_param param;
3422
3423 hclge_promisc_param_init(&param, en, en, true, vport->vport_id);
3424 hclge_cmd_set_promisc_mode(hdev, &param);
3425 }
3426
3427 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3428 {
3429 struct hclge_desc desc;
3430 struct hclge_config_mac_mode_cmd *req =
3431 (struct hclge_config_mac_mode_cmd *)desc.data;
3432 u32 loop_en = 0;
3433 int ret;
3434
3435 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
3436 hnae_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3437 hnae_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3438 hnae_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3439 hnae_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3440 hnae_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3441 hnae_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3442 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3443 hnae_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3444 hnae_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3445 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3446 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3447 hnae_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3448 hnae_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3449 hnae_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
3450 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3451
3452 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3453 if (ret)
3454 dev_err(&hdev->pdev->dev,
3455 "mac enable fail, ret =%d.\n", ret);
3456 }
3457
3458 static int hclge_set_loopback(struct hnae3_handle *handle,
3459 enum hnae3_loop loop_mode, bool en)
3460 {
3461 struct hclge_vport *vport = hclge_get_vport(handle);
3462 struct hclge_config_mac_mode_cmd *req;
3463 struct hclge_dev *hdev = vport->back;
3464 struct hclge_desc desc;
3465 u32 loop_en;
3466 int ret;
3467
3468 switch (loop_mode) {
3469 case HNAE3_MAC_INTER_LOOP_MAC:
3470 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3471 /* 1 Read out the MAC mode config at first */
3472 hclge_cmd_setup_basic_desc(&desc,
3473 HCLGE_OPC_CONFIG_MAC_MODE,
3474 true);
3475 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3476 if (ret) {
3477 dev_err(&hdev->pdev->dev,
3478 "mac loopback get fail, ret =%d.\n",
3479 ret);
3480 return ret;
3481 }
3482
3483 /* 2 Then setup the loopback flag */
3484 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
3485 if (en)
3486 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 1);
3487 else
3488 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3489
3490 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3491
3492 /* 3 Config mac work mode with loopback flag
3493 * and its original configure parameters
3494 */
3495 hclge_cmd_reuse_desc(&desc, false);
3496 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3497 if (ret)
3498 dev_err(&hdev->pdev->dev,
3499 "mac loopback set fail, ret =%d.\n", ret);
3500 break;
3501 default:
3502 ret = -ENOTSUPP;
3503 dev_err(&hdev->pdev->dev,
3504 "loop_mode %d is not supported\n", loop_mode);
3505 break;
3506 }
3507
3508 return ret;
3509 }
3510
3511 static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3512 int stream_id, bool enable)
3513 {
3514 struct hclge_desc desc;
3515 struct hclge_cfg_com_tqp_queue_cmd *req =
3516 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
3517 int ret;
3518
3519 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3520 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3521 req->stream_id = cpu_to_le16(stream_id);
3522 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3523
3524 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3525 if (ret)
3526 dev_err(&hdev->pdev->dev,
3527 "Tqp enable fail, status =%d.\n", ret);
3528 return ret;
3529 }
3530
3531 static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3532 {
3533 struct hclge_vport *vport = hclge_get_vport(handle);
3534 struct hnae3_queue *queue;
3535 struct hclge_tqp *tqp;
3536 int i;
3537
3538 for (i = 0; i < vport->alloc_tqps; i++) {
3539 queue = handle->kinfo.tqp[i];
3540 tqp = container_of(queue, struct hclge_tqp, q);
3541 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3542 }
3543 }
3544
3545 static int hclge_ae_start(struct hnae3_handle *handle)
3546 {
3547 struct hclge_vport *vport = hclge_get_vport(handle);
3548 struct hclge_dev *hdev = vport->back;
3549 int i, queue_id, ret;
3550
3551 for (i = 0; i < vport->alloc_tqps; i++) {
3552 /* todo clear interrupt */
3553 /* ring enable */
3554 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3555 if (queue_id < 0) {
3556 dev_warn(&hdev->pdev->dev,
3557 "Get invalid queue id, ignore it\n");
3558 continue;
3559 }
3560
3561 hclge_tqp_enable(hdev, queue_id, 0, true);
3562 }
3563 /* mac enable */
3564 hclge_cfg_mac_mode(hdev, true);
3565 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
3566 mod_timer(&hdev->service_timer, jiffies + HZ);
3567
3568 ret = hclge_mac_start_phy(hdev);
3569 if (ret)
3570 return ret;
3571
3572 /* reset tqp stats */
3573 hclge_reset_tqp_stats(handle);
3574
3575 return 0;
3576 }
3577
3578 static void hclge_ae_stop(struct hnae3_handle *handle)
3579 {
3580 struct hclge_vport *vport = hclge_get_vport(handle);
3581 struct hclge_dev *hdev = vport->back;
3582 int i, queue_id;
3583
3584 for (i = 0; i < vport->alloc_tqps; i++) {
3585 /* Ring disable */
3586 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3587 if (queue_id < 0) {
3588 dev_warn(&hdev->pdev->dev,
3589 "Get invalid queue id, ignore it\n");
3590 continue;
3591 }
3592
3593 hclge_tqp_enable(hdev, queue_id, 0, false);
3594 }
3595 /* Mac disable */
3596 hclge_cfg_mac_mode(hdev, false);
3597
3598 hclge_mac_stop_phy(hdev);
3599
3600 /* reset tqp stats */
3601 hclge_reset_tqp_stats(handle);
3602 }
3603
3604 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3605 u16 cmdq_resp, u8 resp_code,
3606 enum hclge_mac_vlan_tbl_opcode op)
3607 {
3608 struct hclge_dev *hdev = vport->back;
3609 int return_status = -EIO;
3610
3611 if (cmdq_resp) {
3612 dev_err(&hdev->pdev->dev,
3613 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3614 cmdq_resp);
3615 return -EIO;
3616 }
3617
3618 if (op == HCLGE_MAC_VLAN_ADD) {
3619 if ((!resp_code) || (resp_code == 1)) {
3620 return_status = 0;
3621 } else if (resp_code == 2) {
3622 return_status = -EIO;
3623 dev_err(&hdev->pdev->dev,
3624 "add mac addr failed for uc_overflow.\n");
3625 } else if (resp_code == 3) {
3626 return_status = -EIO;
3627 dev_err(&hdev->pdev->dev,
3628 "add mac addr failed for mc_overflow.\n");
3629 } else {
3630 dev_err(&hdev->pdev->dev,
3631 "add mac addr failed for undefined, code=%d.\n",
3632 resp_code);
3633 }
3634 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3635 if (!resp_code) {
3636 return_status = 0;
3637 } else if (resp_code == 1) {
3638 return_status = -EIO;
3639 dev_dbg(&hdev->pdev->dev,
3640 "remove mac addr failed for miss.\n");
3641 } else {
3642 dev_err(&hdev->pdev->dev,
3643 "remove mac addr failed for undefined, code=%d.\n",
3644 resp_code);
3645 }
3646 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3647 if (!resp_code) {
3648 return_status = 0;
3649 } else if (resp_code == 1) {
3650 return_status = -EIO;
3651 dev_dbg(&hdev->pdev->dev,
3652 "lookup mac addr failed for miss.\n");
3653 } else {
3654 dev_err(&hdev->pdev->dev,
3655 "lookup mac addr failed for undefined, code=%d.\n",
3656 resp_code);
3657 }
3658 } else {
3659 return_status = -EIO;
3660 dev_err(&hdev->pdev->dev,
3661 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3662 op);
3663 }
3664
3665 return return_status;
3666 }
3667
3668 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3669 {
3670 int word_num;
3671 int bit_num;
3672
3673 if (vfid > 255 || vfid < 0)
3674 return -EIO;
3675
3676 if (vfid >= 0 && vfid <= 191) {
3677 word_num = vfid / 32;
3678 bit_num = vfid % 32;
3679 if (clr)
3680 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
3681 else
3682 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
3683 } else {
3684 word_num = (vfid - 192) / 32;
3685 bit_num = vfid % 32;
3686 if (clr)
3687 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
3688 else
3689 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
3690 }
3691
3692 return 0;
3693 }
3694
3695 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3696 {
3697 #define HCLGE_DESC_NUMBER 3
3698 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3699 int i, j;
3700
3701 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3702 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3703 if (desc[i].data[j])
3704 return false;
3705
3706 return true;
3707 }
3708
3709 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
3710 const u8 *addr)
3711 {
3712 const unsigned char *mac_addr = addr;
3713 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3714 (mac_addr[0]) | (mac_addr[1] << 8);
3715 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3716
3717 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3718 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3719 }
3720
3721 static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3722 const u8 *addr)
3723 {
3724 u16 high_val = addr[1] | (addr[0] << 8);
3725 struct hclge_dev *hdev = vport->back;
3726 u32 rsh = 4 - hdev->mta_mac_sel_type;
3727 u16 ret_val = (high_val >> rsh) & 0xfff;
3728
3729 return ret_val;
3730 }
3731
3732 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3733 enum hclge_mta_dmac_sel_type mta_mac_sel,
3734 bool enable)
3735 {
3736 struct hclge_mta_filter_mode_cmd *req;
3737 struct hclge_desc desc;
3738 int ret;
3739
3740 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
3741 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3742
3743 hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3744 enable);
3745 hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3746 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3747
3748 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3749 if (ret) {
3750 dev_err(&hdev->pdev->dev,
3751 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3752 ret);
3753 return ret;
3754 }
3755
3756 return 0;
3757 }
3758
3759 int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3760 u8 func_id,
3761 bool enable)
3762 {
3763 struct hclge_cfg_func_mta_filter_cmd *req;
3764 struct hclge_desc desc;
3765 int ret;
3766
3767 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
3768 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3769
3770 hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3771 enable);
3772 req->function_id = func_id;
3773
3774 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3775 if (ret) {
3776 dev_err(&hdev->pdev->dev,
3777 "Config func_id enable failed for cmd_send, ret =%d.\n",
3778 ret);
3779 return ret;
3780 }
3781
3782 return 0;
3783 }
3784
3785 static int hclge_set_mta_table_item(struct hclge_vport *vport,
3786 u16 idx,
3787 bool enable)
3788 {
3789 struct hclge_dev *hdev = vport->back;
3790 struct hclge_cfg_func_mta_item_cmd *req;
3791 struct hclge_desc desc;
3792 u16 item_idx = 0;
3793 int ret;
3794
3795 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
3796 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
3797 hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
3798
3799 hnae_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
3800 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
3801 req->item_idx = cpu_to_le16(item_idx);
3802
3803 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3804 if (ret) {
3805 dev_err(&hdev->pdev->dev,
3806 "Config mta table item failed for cmd_send, ret =%d.\n",
3807 ret);
3808 return ret;
3809 }
3810
3811 return 0;
3812 }
3813
3814 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
3815 struct hclge_mac_vlan_tbl_entry_cmd *req)
3816 {
3817 struct hclge_dev *hdev = vport->back;
3818 struct hclge_desc desc;
3819 u8 resp_code;
3820 u16 retval;
3821 int ret;
3822
3823 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
3824
3825 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
3826
3827 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3828 if (ret) {
3829 dev_err(&hdev->pdev->dev,
3830 "del mac addr failed for cmd_send, ret =%d.\n",
3831 ret);
3832 return ret;
3833 }
3834 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3835 retval = le16_to_cpu(desc.retval);
3836
3837 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
3838 HCLGE_MAC_VLAN_REMOVE);
3839 }
3840
3841 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
3842 struct hclge_mac_vlan_tbl_entry_cmd *req,
3843 struct hclge_desc *desc,
3844 bool is_mc)
3845 {
3846 struct hclge_dev *hdev = vport->back;
3847 u8 resp_code;
3848 u16 retval;
3849 int ret;
3850
3851 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
3852 if (is_mc) {
3853 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3854 memcpy(desc[0].data,
3855 req,
3856 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
3857 hclge_cmd_setup_basic_desc(&desc[1],
3858 HCLGE_OPC_MAC_VLAN_ADD,
3859 true);
3860 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3861 hclge_cmd_setup_basic_desc(&desc[2],
3862 HCLGE_OPC_MAC_VLAN_ADD,
3863 true);
3864 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3865 } else {
3866 memcpy(desc[0].data,
3867 req,
3868 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
3869 ret = hclge_cmd_send(&hdev->hw, desc, 1);
3870 }
3871 if (ret) {
3872 dev_err(&hdev->pdev->dev,
3873 "lookup mac addr failed for cmd_send, ret =%d.\n",
3874 ret);
3875 return ret;
3876 }
3877 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
3878 retval = le16_to_cpu(desc[0].retval);
3879
3880 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
3881 HCLGE_MAC_VLAN_LKUP);
3882 }
3883
3884 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
3885 struct hclge_mac_vlan_tbl_entry_cmd *req,
3886 struct hclge_desc *mc_desc)
3887 {
3888 struct hclge_dev *hdev = vport->back;
3889 int cfg_status;
3890 u8 resp_code;
3891 u16 retval;
3892 int ret;
3893
3894 if (!mc_desc) {
3895 struct hclge_desc desc;
3896
3897 hclge_cmd_setup_basic_desc(&desc,
3898 HCLGE_OPC_MAC_VLAN_ADD,
3899 false);
3900 memcpy(desc.data, req,
3901 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
3902 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3903 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3904 retval = le16_to_cpu(desc.retval);
3905
3906 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
3907 resp_code,
3908 HCLGE_MAC_VLAN_ADD);
3909 } else {
3910 hclge_cmd_reuse_desc(&mc_desc[0], false);
3911 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3912 hclge_cmd_reuse_desc(&mc_desc[1], false);
3913 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3914 hclge_cmd_reuse_desc(&mc_desc[2], false);
3915 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
3916 memcpy(mc_desc[0].data, req,
3917 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
3918 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
3919 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
3920 retval = le16_to_cpu(mc_desc[0].retval);
3921
3922 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
3923 resp_code,
3924 HCLGE_MAC_VLAN_ADD);
3925 }
3926
3927 if (ret) {
3928 dev_err(&hdev->pdev->dev,
3929 "add mac addr failed for cmd_send, ret =%d.\n",
3930 ret);
3931 return ret;
3932 }
3933
3934 return cfg_status;
3935 }
3936
3937 static int hclge_add_uc_addr(struct hnae3_handle *handle,
3938 const unsigned char *addr)
3939 {
3940 struct hclge_vport *vport = hclge_get_vport(handle);
3941
3942 return hclge_add_uc_addr_common(vport, addr);
3943 }
3944
3945 int hclge_add_uc_addr_common(struct hclge_vport *vport,
3946 const unsigned char *addr)
3947 {
3948 struct hclge_dev *hdev = vport->back;
3949 struct hclge_mac_vlan_tbl_entry_cmd req;
3950 enum hclge_cmd_status status;
3951 u16 egress_port = 0;
3952
3953 /* mac addr check */
3954 if (is_zero_ether_addr(addr) ||
3955 is_broadcast_ether_addr(addr) ||
3956 is_multicast_ether_addr(addr)) {
3957 dev_err(&hdev->pdev->dev,
3958 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
3959 addr,
3960 is_zero_ether_addr(addr),
3961 is_broadcast_ether_addr(addr),
3962 is_multicast_ether_addr(addr));
3963 return -EINVAL;
3964 }
3965
3966 memset(&req, 0, sizeof(req));
3967 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3968 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3969 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0);
3970 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3971
3972 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_SW_EN_B, 0);
3973 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_TYPE_B, 0);
3974 hnae_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
3975 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
3976 hnae_set_field(egress_port, HCLGE_MAC_EPORT_PFID_M,
3977 HCLGE_MAC_EPORT_PFID_S, 0);
3978
3979 req.egress_port = cpu_to_le16(egress_port);
3980
3981 hclge_prepare_mac_addr(&req, addr);
3982
3983 status = hclge_add_mac_vlan_tbl(vport, &req, NULL);
3984
3985 return status;
3986 }
3987
3988 static int hclge_rm_uc_addr(struct hnae3_handle *handle,
3989 const unsigned char *addr)
3990 {
3991 struct hclge_vport *vport = hclge_get_vport(handle);
3992
3993 return hclge_rm_uc_addr_common(vport, addr);
3994 }
3995
3996 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
3997 const unsigned char *addr)
3998 {
3999 struct hclge_dev *hdev = vport->back;
4000 struct hclge_mac_vlan_tbl_entry_cmd req;
4001 enum hclge_cmd_status status;
4002
4003 /* mac addr check */
4004 if (is_zero_ether_addr(addr) ||
4005 is_broadcast_ether_addr(addr) ||
4006 is_multicast_ether_addr(addr)) {
4007 dev_dbg(&hdev->pdev->dev,
4008 "Remove mac err! invalid mac:%pM.\n",
4009 addr);
4010 return -EINVAL;
4011 }
4012
4013 memset(&req, 0, sizeof(req));
4014 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4015 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4016 hclge_prepare_mac_addr(&req, addr);
4017 status = hclge_remove_mac_vlan_tbl(vport, &req);
4018
4019 return status;
4020 }
4021
4022 static int hclge_add_mc_addr(struct hnae3_handle *handle,
4023 const unsigned char *addr)
4024 {
4025 struct hclge_vport *vport = hclge_get_vport(handle);
4026
4027 return hclge_add_mc_addr_common(vport, addr);
4028 }
4029
4030 int hclge_add_mc_addr_common(struct hclge_vport *vport,
4031 const unsigned char *addr)
4032 {
4033 struct hclge_dev *hdev = vport->back;
4034 struct hclge_mac_vlan_tbl_entry_cmd req;
4035 struct hclge_desc desc[3];
4036 u16 tbl_idx;
4037 int status;
4038
4039 /* mac addr check */
4040 if (!is_multicast_ether_addr(addr)) {
4041 dev_err(&hdev->pdev->dev,
4042 "Add mc mac err! invalid mac:%pM.\n",
4043 addr);
4044 return -EINVAL;
4045 }
4046 memset(&req, 0, sizeof(req));
4047 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4048 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4049 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4050 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4051 hclge_prepare_mac_addr(&req, addr);
4052 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4053 if (!status) {
4054 /* This mac addr exist, update VFID for it */
4055 hclge_update_desc_vfid(desc, vport->vport_id, false);
4056 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4057 } else {
4058 /* This mac addr do not exist, add new entry for it */
4059 memset(desc[0].data, 0, sizeof(desc[0].data));
4060 memset(desc[1].data, 0, sizeof(desc[0].data));
4061 memset(desc[2].data, 0, sizeof(desc[0].data));
4062 hclge_update_desc_vfid(desc, vport->vport_id, false);
4063 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4064 }
4065
4066 /* Set MTA table for this MAC address */
4067 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4068 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4069
4070 return status;
4071 }
4072
4073 static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4074 const unsigned char *addr)
4075 {
4076 struct hclge_vport *vport = hclge_get_vport(handle);
4077
4078 return hclge_rm_mc_addr_common(vport, addr);
4079 }
4080
4081 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4082 const unsigned char *addr)
4083 {
4084 struct hclge_dev *hdev = vport->back;
4085 struct hclge_mac_vlan_tbl_entry_cmd req;
4086 enum hclge_cmd_status status;
4087 struct hclge_desc desc[3];
4088 u16 tbl_idx;
4089
4090 /* mac addr check */
4091 if (!is_multicast_ether_addr(addr)) {
4092 dev_dbg(&hdev->pdev->dev,
4093 "Remove mc mac err! invalid mac:%pM.\n",
4094 addr);
4095 return -EINVAL;
4096 }
4097
4098 memset(&req, 0, sizeof(req));
4099 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4100 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4101 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4102 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4103 hclge_prepare_mac_addr(&req, addr);
4104 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4105 if (!status) {
4106 /* This mac addr exist, remove this handle's VFID for it */
4107 hclge_update_desc_vfid(desc, vport->vport_id, true);
4108
4109 if (hclge_is_all_function_id_zero(desc))
4110 /* All the vfid is zero, so need to delete this entry */
4111 status = hclge_remove_mac_vlan_tbl(vport, &req);
4112 else
4113 /* Not all the vfid is zero, update the vfid */
4114 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4115
4116 } else {
4117 /* This mac addr do not exist, can't delete it */
4118 dev_err(&hdev->pdev->dev,
4119 "Rm multicast mac addr failed, ret = %d.\n",
4120 status);
4121 return -EIO;
4122 }
4123
4124 /* Set MTB table for this MAC address */
4125 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4126 status = hclge_set_mta_table_item(vport, tbl_idx, false);
4127
4128 return status;
4129 }
4130
4131 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4132 {
4133 struct hclge_vport *vport = hclge_get_vport(handle);
4134 struct hclge_dev *hdev = vport->back;
4135
4136 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4137 }
4138
4139 static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p)
4140 {
4141 const unsigned char *new_addr = (const unsigned char *)p;
4142 struct hclge_vport *vport = hclge_get_vport(handle);
4143 struct hclge_dev *hdev = vport->back;
4144
4145 /* mac addr check */
4146 if (is_zero_ether_addr(new_addr) ||
4147 is_broadcast_ether_addr(new_addr) ||
4148 is_multicast_ether_addr(new_addr)) {
4149 dev_err(&hdev->pdev->dev,
4150 "Change uc mac err! invalid mac:%p.\n",
4151 new_addr);
4152 return -EINVAL;
4153 }
4154
4155 hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr);
4156
4157 if (!hclge_add_uc_addr(handle, new_addr)) {
4158 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4159 return 0;
4160 }
4161
4162 return -EIO;
4163 }
4164
4165 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4166 bool filter_en)
4167 {
4168 struct hclge_vlan_filter_ctrl_cmd *req;
4169 struct hclge_desc desc;
4170 int ret;
4171
4172 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4173
4174 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
4175 req->vlan_type = vlan_type;
4176 req->vlan_fe = filter_en;
4177
4178 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4179 if (ret) {
4180 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4181 ret);
4182 return ret;
4183 }
4184
4185 return 0;
4186 }
4187
4188 int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4189 bool is_kill, u16 vlan, u8 qos, __be16 proto)
4190 {
4191 #define HCLGE_MAX_VF_BYTES 16
4192 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4193 struct hclge_vlan_filter_vf_cfg_cmd *req1;
4194 struct hclge_desc desc[2];
4195 u8 vf_byte_val;
4196 u8 vf_byte_off;
4197 int ret;
4198
4199 hclge_cmd_setup_basic_desc(&desc[0],
4200 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4201 hclge_cmd_setup_basic_desc(&desc[1],
4202 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4203
4204 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4205
4206 vf_byte_off = vfid / 8;
4207 vf_byte_val = 1 << (vfid % 8);
4208
4209 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4210 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
4211
4212 req0->vlan_id = cpu_to_le16(vlan);
4213 req0->vlan_cfg = is_kill;
4214
4215 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4216 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4217 else
4218 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4219
4220 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4221 if (ret) {
4222 dev_err(&hdev->pdev->dev,
4223 "Send vf vlan command fail, ret =%d.\n",
4224 ret);
4225 return ret;
4226 }
4227
4228 if (!is_kill) {
4229 if (!req0->resp_code || req0->resp_code == 1)
4230 return 0;
4231
4232 dev_err(&hdev->pdev->dev,
4233 "Add vf vlan filter fail, ret =%d.\n",
4234 req0->resp_code);
4235 } else {
4236 if (!req0->resp_code)
4237 return 0;
4238
4239 dev_err(&hdev->pdev->dev,
4240 "Kill vf vlan filter fail, ret =%d.\n",
4241 req0->resp_code);
4242 }
4243
4244 return -EIO;
4245 }
4246
4247 static int hclge_set_port_vlan_filter(struct hnae3_handle *handle,
4248 __be16 proto, u16 vlan_id,
4249 bool is_kill)
4250 {
4251 struct hclge_vport *vport = hclge_get_vport(handle);
4252 struct hclge_dev *hdev = vport->back;
4253 struct hclge_vlan_filter_pf_cfg_cmd *req;
4254 struct hclge_desc desc;
4255 u8 vlan_offset_byte_val;
4256 u8 vlan_offset_byte;
4257 u8 vlan_offset_160;
4258 int ret;
4259
4260 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4261
4262 vlan_offset_160 = vlan_id / 160;
4263 vlan_offset_byte = (vlan_id % 160) / 8;
4264 vlan_offset_byte_val = 1 << (vlan_id % 8);
4265
4266 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
4267 req->vlan_offset = vlan_offset_160;
4268 req->vlan_cfg = is_kill;
4269 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4270
4271 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4272 if (ret) {
4273 dev_err(&hdev->pdev->dev,
4274 "port vlan command, send fail, ret =%d.\n",
4275 ret);
4276 return ret;
4277 }
4278
4279 ret = hclge_set_vf_vlan_common(hdev, 0, is_kill, vlan_id, 0, proto);
4280 if (ret) {
4281 dev_err(&hdev->pdev->dev,
4282 "Set pf vlan filter config fail, ret =%d.\n",
4283 ret);
4284 return -EIO;
4285 }
4286
4287 return 0;
4288 }
4289
4290 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4291 u16 vlan, u8 qos, __be16 proto)
4292 {
4293 struct hclge_vport *vport = hclge_get_vport(handle);
4294 struct hclge_dev *hdev = vport->back;
4295
4296 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4297 return -EINVAL;
4298 if (proto != htons(ETH_P_8021Q))
4299 return -EPROTONOSUPPORT;
4300
4301 return hclge_set_vf_vlan_common(hdev, vfid, false, vlan, qos, proto);
4302 }
4303
4304 static int hclge_init_vlan_config(struct hclge_dev *hdev)
4305 {
4306 #define HCLGE_VLAN_TYPE_VF_TABLE 0
4307 #define HCLGE_VLAN_TYPE_PORT_TABLE 1
4308 struct hnae3_handle *handle;
4309 int ret;
4310
4311 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_VF_TABLE,
4312 true);
4313 if (ret)
4314 return ret;
4315
4316 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_PORT_TABLE,
4317 true);
4318 if (ret)
4319 return ret;
4320
4321 handle = &hdev->vport[0].nic;
4322 return hclge_set_port_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
4323 }
4324
4325 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
4326 {
4327 struct hclge_vport *vport = hclge_get_vport(handle);
4328 struct hclge_config_max_frm_size_cmd *req;
4329 struct hclge_dev *hdev = vport->back;
4330 struct hclge_desc desc;
4331 int ret;
4332
4333 if ((new_mtu < HCLGE_MAC_MIN_MTU) || (new_mtu > HCLGE_MAC_MAX_MTU))
4334 return -EINVAL;
4335
4336 hdev->mps = new_mtu;
4337 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
4338
4339 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
4340 req->max_frm_size = cpu_to_le16(new_mtu);
4341
4342 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4343 if (ret) {
4344 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
4345 return ret;
4346 }
4347
4348 return 0;
4349 }
4350
4351 static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
4352 bool enable)
4353 {
4354 struct hclge_reset_tqp_queue_cmd *req;
4355 struct hclge_desc desc;
4356 int ret;
4357
4358 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
4359
4360 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
4361 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4362 hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
4363
4364 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4365 if (ret) {
4366 dev_err(&hdev->pdev->dev,
4367 "Send tqp reset cmd error, status =%d\n", ret);
4368 return ret;
4369 }
4370
4371 return 0;
4372 }
4373
4374 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
4375 {
4376 struct hclge_reset_tqp_queue_cmd *req;
4377 struct hclge_desc desc;
4378 int ret;
4379
4380 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
4381
4382 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
4383 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4384
4385 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4386 if (ret) {
4387 dev_err(&hdev->pdev->dev,
4388 "Get reset status error, status =%d\n", ret);
4389 return ret;
4390 }
4391
4392 return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
4393 }
4394
4395 static void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
4396 {
4397 struct hclge_vport *vport = hclge_get_vport(handle);
4398 struct hclge_dev *hdev = vport->back;
4399 int reset_try_times = 0;
4400 int reset_status;
4401 int ret;
4402
4403 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
4404 if (ret) {
4405 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
4406 return;
4407 }
4408
4409 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, true);
4410 if (ret) {
4411 dev_warn(&hdev->pdev->dev,
4412 "Send reset tqp cmd fail, ret = %d\n", ret);
4413 return;
4414 }
4415
4416 reset_try_times = 0;
4417 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
4418 /* Wait for tqp hw reset */
4419 msleep(20);
4420 reset_status = hclge_get_reset_status(hdev, queue_id);
4421 if (reset_status)
4422 break;
4423 }
4424
4425 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
4426 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
4427 return;
4428 }
4429
4430 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, false);
4431 if (ret) {
4432 dev_warn(&hdev->pdev->dev,
4433 "Deassert the soft reset fail, ret = %d\n", ret);
4434 return;
4435 }
4436 }
4437
4438 static u32 hclge_get_fw_version(struct hnae3_handle *handle)
4439 {
4440 struct hclge_vport *vport = hclge_get_vport(handle);
4441 struct hclge_dev *hdev = vport->back;
4442
4443 return hdev->fw_version;
4444 }
4445
4446 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
4447 u32 *rx_en, u32 *tx_en)
4448 {
4449 struct hclge_vport *vport = hclge_get_vport(handle);
4450 struct hclge_dev *hdev = vport->back;
4451
4452 *auto_neg = hclge_get_autoneg(handle);
4453
4454 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
4455 *rx_en = 0;
4456 *tx_en = 0;
4457 return;
4458 }
4459
4460 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
4461 *rx_en = 1;
4462 *tx_en = 0;
4463 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
4464 *tx_en = 1;
4465 *rx_en = 0;
4466 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
4467 *rx_en = 1;
4468 *tx_en = 1;
4469 } else {
4470 *rx_en = 0;
4471 *tx_en = 0;
4472 }
4473 }
4474
4475 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
4476 u8 *auto_neg, u32 *speed, u8 *duplex)
4477 {
4478 struct hclge_vport *vport = hclge_get_vport(handle);
4479 struct hclge_dev *hdev = vport->back;
4480
4481 if (speed)
4482 *speed = hdev->hw.mac.speed;
4483 if (duplex)
4484 *duplex = hdev->hw.mac.duplex;
4485 if (auto_neg)
4486 *auto_neg = hdev->hw.mac.autoneg;
4487 }
4488
4489 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
4490 {
4491 struct hclge_vport *vport = hclge_get_vport(handle);
4492 struct hclge_dev *hdev = vport->back;
4493
4494 if (media_type)
4495 *media_type = hdev->hw.mac.media_type;
4496 }
4497
4498 static void hclge_get_mdix_mode(struct hnae3_handle *handle,
4499 u8 *tp_mdix_ctrl, u8 *tp_mdix)
4500 {
4501 struct hclge_vport *vport = hclge_get_vport(handle);
4502 struct hclge_dev *hdev = vport->back;
4503 struct phy_device *phydev = hdev->hw.mac.phydev;
4504 int mdix_ctrl, mdix, retval, is_resolved;
4505
4506 if (!phydev) {
4507 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
4508 *tp_mdix = ETH_TP_MDI_INVALID;
4509 return;
4510 }
4511
4512 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
4513
4514 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
4515 mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
4516 HCLGE_PHY_MDIX_CTRL_S);
4517
4518 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
4519 mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
4520 is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
4521
4522 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
4523
4524 switch (mdix_ctrl) {
4525 case 0x0:
4526 *tp_mdix_ctrl = ETH_TP_MDI;
4527 break;
4528 case 0x1:
4529 *tp_mdix_ctrl = ETH_TP_MDI_X;
4530 break;
4531 case 0x3:
4532 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
4533 break;
4534 default:
4535 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
4536 break;
4537 }
4538
4539 if (!is_resolved)
4540 *tp_mdix = ETH_TP_MDI_INVALID;
4541 else if (mdix)
4542 *tp_mdix = ETH_TP_MDI_X;
4543 else
4544 *tp_mdix = ETH_TP_MDI;
4545 }
4546
4547 static int hclge_init_client_instance(struct hnae3_client *client,
4548 struct hnae3_ae_dev *ae_dev)
4549 {
4550 struct hclge_dev *hdev = ae_dev->priv;
4551 struct hclge_vport *vport;
4552 int i, ret;
4553
4554 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
4555 vport = &hdev->vport[i];
4556
4557 switch (client->type) {
4558 case HNAE3_CLIENT_KNIC:
4559
4560 hdev->nic_client = client;
4561 vport->nic.client = client;
4562 ret = client->ops->init_instance(&vport->nic);
4563 if (ret)
4564 goto err;
4565
4566 if (hdev->roce_client &&
4567 hnae3_dev_roce_supported(hdev)) {
4568 struct hnae3_client *rc = hdev->roce_client;
4569
4570 ret = hclge_init_roce_base_info(vport);
4571 if (ret)
4572 goto err;
4573
4574 ret = rc->ops->init_instance(&vport->roce);
4575 if (ret)
4576 goto err;
4577 }
4578
4579 break;
4580 case HNAE3_CLIENT_UNIC:
4581 hdev->nic_client = client;
4582 vport->nic.client = client;
4583
4584 ret = client->ops->init_instance(&vport->nic);
4585 if (ret)
4586 goto err;
4587
4588 break;
4589 case HNAE3_CLIENT_ROCE:
4590 if (hnae3_dev_roce_supported(hdev)) {
4591 hdev->roce_client = client;
4592 vport->roce.client = client;
4593 }
4594
4595 if (hdev->roce_client && hdev->nic_client) {
4596 ret = hclge_init_roce_base_info(vport);
4597 if (ret)
4598 goto err;
4599
4600 ret = client->ops->init_instance(&vport->roce);
4601 if (ret)
4602 goto err;
4603 }
4604 }
4605 }
4606
4607 return 0;
4608 err:
4609 return ret;
4610 }
4611
4612 static void hclge_uninit_client_instance(struct hnae3_client *client,
4613 struct hnae3_ae_dev *ae_dev)
4614 {
4615 struct hclge_dev *hdev = ae_dev->priv;
4616 struct hclge_vport *vport;
4617 int i;
4618
4619 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
4620 vport = &hdev->vport[i];
4621 if (hdev->roce_client) {
4622 hdev->roce_client->ops->uninit_instance(&vport->roce,
4623 0);
4624 hdev->roce_client = NULL;
4625 vport->roce.client = NULL;
4626 }
4627 if (client->type == HNAE3_CLIENT_ROCE)
4628 return;
4629 if (client->ops->uninit_instance) {
4630 client->ops->uninit_instance(&vport->nic, 0);
4631 hdev->nic_client = NULL;
4632 vport->nic.client = NULL;
4633 }
4634 }
4635 }
4636
4637 static int hclge_pci_init(struct hclge_dev *hdev)
4638 {
4639 struct pci_dev *pdev = hdev->pdev;
4640 struct hclge_hw *hw;
4641 int ret;
4642
4643 ret = pci_enable_device(pdev);
4644 if (ret) {
4645 dev_err(&pdev->dev, "failed to enable PCI device\n");
4646 goto err_no_drvdata;
4647 }
4648
4649 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
4650 if (ret) {
4651 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
4652 if (ret) {
4653 dev_err(&pdev->dev,
4654 "can't set consistent PCI DMA");
4655 goto err_disable_device;
4656 }
4657 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
4658 }
4659
4660 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
4661 if (ret) {
4662 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
4663 goto err_disable_device;
4664 }
4665
4666 pci_set_master(pdev);
4667 hw = &hdev->hw;
4668 hw->back = hdev;
4669 hw->io_base = pcim_iomap(pdev, 2, 0);
4670 if (!hw->io_base) {
4671 dev_err(&pdev->dev, "Can't map configuration register space\n");
4672 ret = -ENOMEM;
4673 goto err_clr_master;
4674 }
4675
4676 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
4677
4678 return 0;
4679 err_clr_master:
4680 pci_clear_master(pdev);
4681 pci_release_regions(pdev);
4682 err_disable_device:
4683 pci_disable_device(pdev);
4684 err_no_drvdata:
4685 pci_set_drvdata(pdev, NULL);
4686
4687 return ret;
4688 }
4689
4690 static void hclge_pci_uninit(struct hclge_dev *hdev)
4691 {
4692 struct pci_dev *pdev = hdev->pdev;
4693
4694 pci_free_irq_vectors(pdev);
4695 pci_clear_master(pdev);
4696 pci_release_mem_regions(pdev);
4697 pci_disable_device(pdev);
4698 }
4699
4700 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
4701 {
4702 struct pci_dev *pdev = ae_dev->pdev;
4703 struct hclge_dev *hdev;
4704 int ret;
4705
4706 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
4707 if (!hdev) {
4708 ret = -ENOMEM;
4709 goto err_hclge_dev;
4710 }
4711
4712 hdev->pdev = pdev;
4713 hdev->ae_dev = ae_dev;
4714 hdev->reset_type = HNAE3_NONE_RESET;
4715 hdev->reset_request = 0;
4716 hdev->reset_pending = 0;
4717 ae_dev->priv = hdev;
4718
4719 ret = hclge_pci_init(hdev);
4720 if (ret) {
4721 dev_err(&pdev->dev, "PCI init failed\n");
4722 goto err_pci_init;
4723 }
4724
4725 /* Firmware command queue initialize */
4726 ret = hclge_cmd_queue_init(hdev);
4727 if (ret) {
4728 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
4729 return ret;
4730 }
4731
4732 /* Firmware command initialize */
4733 ret = hclge_cmd_init(hdev);
4734 if (ret)
4735 goto err_cmd_init;
4736
4737 ret = hclge_get_cap(hdev);
4738 if (ret) {
4739 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
4740 ret);
4741 return ret;
4742 }
4743
4744 ret = hclge_configure(hdev);
4745 if (ret) {
4746 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
4747 return ret;
4748 }
4749
4750 ret = hclge_init_msi(hdev);
4751 if (ret) {
4752 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
4753 return ret;
4754 }
4755
4756 ret = hclge_misc_irq_init(hdev);
4757 if (ret) {
4758 dev_err(&pdev->dev,
4759 "Misc IRQ(vector0) init error, ret = %d.\n",
4760 ret);
4761 return ret;
4762 }
4763
4764 ret = hclge_alloc_tqps(hdev);
4765 if (ret) {
4766 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
4767 return ret;
4768 }
4769
4770 ret = hclge_alloc_vport(hdev);
4771 if (ret) {
4772 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
4773 return ret;
4774 }
4775
4776 ret = hclge_map_tqp(hdev);
4777 if (ret) {
4778 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
4779 return ret;
4780 }
4781
4782 ret = hclge_mac_mdio_config(hdev);
4783 if (ret) {
4784 dev_warn(&hdev->pdev->dev,
4785 "mdio config fail ret=%d\n", ret);
4786 return ret;
4787 }
4788
4789 ret = hclge_mac_init(hdev);
4790 if (ret) {
4791 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
4792 return ret;
4793 }
4794 ret = hclge_buffer_alloc(hdev);
4795 if (ret) {
4796 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
4797 return ret;
4798 }
4799
4800 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
4801 if (ret) {
4802 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
4803 return ret;
4804 }
4805
4806 ret = hclge_init_vlan_config(hdev);
4807 if (ret) {
4808 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
4809 return ret;
4810 }
4811
4812 ret = hclge_tm_schd_init(hdev);
4813 if (ret) {
4814 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
4815 return ret;
4816 }
4817
4818 ret = hclge_rss_init_hw(hdev);
4819 if (ret) {
4820 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
4821 return ret;
4822 }
4823
4824 hclge_dcb_ops_set(hdev);
4825
4826 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
4827 INIT_WORK(&hdev->service_task, hclge_service_task);
4828 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
4829
4830 /* Enable MISC vector(vector0) */
4831 hclge_enable_vector(&hdev->misc_vector, true);
4832
4833 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
4834 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4835 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
4836 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
4837
4838 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
4839 return 0;
4840
4841 err_cmd_init:
4842 pci_release_regions(pdev);
4843 err_pci_init:
4844 pci_set_drvdata(pdev, NULL);
4845 err_hclge_dev:
4846 return ret;
4847 }
4848
4849 static void hclge_stats_clear(struct hclge_dev *hdev)
4850 {
4851 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
4852 }
4853
4854 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
4855 {
4856 struct hclge_dev *hdev = ae_dev->priv;
4857 struct pci_dev *pdev = ae_dev->pdev;
4858 int ret;
4859
4860 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4861
4862 hclge_stats_clear(hdev);
4863
4864 ret = hclge_cmd_init(hdev);
4865 if (ret) {
4866 dev_err(&pdev->dev, "Cmd queue init failed\n");
4867 return ret;
4868 }
4869
4870 ret = hclge_get_cap(hdev);
4871 if (ret) {
4872 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
4873 ret);
4874 return ret;
4875 }
4876
4877 ret = hclge_configure(hdev);
4878 if (ret) {
4879 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
4880 return ret;
4881 }
4882
4883 ret = hclge_map_tqp(hdev);
4884 if (ret) {
4885 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
4886 return ret;
4887 }
4888
4889 ret = hclge_mac_init(hdev);
4890 if (ret) {
4891 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
4892 return ret;
4893 }
4894
4895 ret = hclge_buffer_alloc(hdev);
4896 if (ret) {
4897 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
4898 return ret;
4899 }
4900
4901 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
4902 if (ret) {
4903 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
4904 return ret;
4905 }
4906
4907 ret = hclge_init_vlan_config(hdev);
4908 if (ret) {
4909 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
4910 return ret;
4911 }
4912
4913 ret = hclge_tm_schd_init(hdev);
4914 if (ret) {
4915 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
4916 return ret;
4917 }
4918
4919 ret = hclge_rss_init_hw(hdev);
4920 if (ret) {
4921 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
4922 return ret;
4923 }
4924
4925 /* Enable MISC vector(vector0) */
4926 hclge_enable_vector(&hdev->misc_vector, true);
4927
4928 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
4929 HCLGE_DRIVER_NAME);
4930
4931 return 0;
4932 }
4933
4934 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
4935 {
4936 struct hclge_dev *hdev = ae_dev->priv;
4937 struct hclge_mac *mac = &hdev->hw.mac;
4938
4939 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4940
4941 if (IS_ENABLED(CONFIG_PCI_IOV))
4942 hclge_disable_sriov(hdev);
4943
4944 if (hdev->service_timer.function)
4945 del_timer_sync(&hdev->service_timer);
4946 if (hdev->service_task.func)
4947 cancel_work_sync(&hdev->service_task);
4948 if (hdev->rst_service_task.func)
4949 cancel_work_sync(&hdev->rst_service_task);
4950
4951 if (mac->phydev)
4952 mdiobus_unregister(mac->mdio_bus);
4953
4954 /* Disable MISC vector(vector0) */
4955 hclge_enable_vector(&hdev->misc_vector, false);
4956 hclge_destroy_cmd_queue(&hdev->hw);
4957 hclge_misc_irq_uninit(hdev);
4958 hclge_pci_uninit(hdev);
4959 ae_dev->priv = NULL;
4960 }
4961
4962 static const struct hnae3_ae_ops hclge_ops = {
4963 .init_ae_dev = hclge_init_ae_dev,
4964 .uninit_ae_dev = hclge_uninit_ae_dev,
4965 .init_client_instance = hclge_init_client_instance,
4966 .uninit_client_instance = hclge_uninit_client_instance,
4967 .map_ring_to_vector = hclge_map_handle_ring_to_vector,
4968 .unmap_ring_from_vector = hclge_unmap_ring_from_vector,
4969 .get_vector = hclge_get_vector,
4970 .set_promisc_mode = hclge_set_promisc_mode,
4971 .set_loopback = hclge_set_loopback,
4972 .start = hclge_ae_start,
4973 .stop = hclge_ae_stop,
4974 .get_status = hclge_get_status,
4975 .get_ksettings_an_result = hclge_get_ksettings_an_result,
4976 .update_speed_duplex_h = hclge_update_speed_duplex_h,
4977 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
4978 .get_media_type = hclge_get_media_type,
4979 .get_rss_key_size = hclge_get_rss_key_size,
4980 .get_rss_indir_size = hclge_get_rss_indir_size,
4981 .get_rss = hclge_get_rss,
4982 .set_rss = hclge_set_rss,
4983 .set_rss_tuple = hclge_set_rss_tuple,
4984 .get_rss_tuple = hclge_get_rss_tuple,
4985 .get_tc_size = hclge_get_tc_size,
4986 .get_mac_addr = hclge_get_mac_addr,
4987 .set_mac_addr = hclge_set_mac_addr,
4988 .add_uc_addr = hclge_add_uc_addr,
4989 .rm_uc_addr = hclge_rm_uc_addr,
4990 .add_mc_addr = hclge_add_mc_addr,
4991 .rm_mc_addr = hclge_rm_mc_addr,
4992 .set_autoneg = hclge_set_autoneg,
4993 .get_autoneg = hclge_get_autoneg,
4994 .get_pauseparam = hclge_get_pauseparam,
4995 .set_mtu = hclge_set_mtu,
4996 .reset_queue = hclge_reset_tqp,
4997 .get_stats = hclge_get_stats,
4998 .update_stats = hclge_update_stats,
4999 .get_strings = hclge_get_strings,
5000 .get_sset_count = hclge_get_sset_count,
5001 .get_fw_version = hclge_get_fw_version,
5002 .get_mdix_mode = hclge_get_mdix_mode,
5003 .set_vlan_filter = hclge_set_port_vlan_filter,
5004 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
5005 .reset_event = hclge_reset_event,
5006 };
5007
5008 static struct hnae3_ae_algo ae_algo = {
5009 .ops = &hclge_ops,
5010 .name = HCLGE_NAME,
5011 .pdev_id_table = ae_algo_pci_tbl,
5012 };
5013
5014 static int hclge_init(void)
5015 {
5016 pr_info("%s is initializing\n", HCLGE_NAME);
5017
5018 return hnae3_register_ae_algo(&ae_algo);
5019 }
5020
5021 static void hclge_exit(void)
5022 {
5023 hnae3_unregister_ae_algo(&ae_algo);
5024 }
5025 module_init(hclge_init);
5026 module_exit(hclge_exit);
5027
5028 MODULE_LICENSE("GPL");
5029 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
5030 MODULE_DESCRIPTION("HCLGE Driver");
5031 MODULE_VERSION(HCLGE_MOD_VERSION);
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