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net: hns3: add support for querying advertised pause frame by ethtool ethx
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
1 /*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10 #include <linux/acpi.h>
11 #include <linux/device.h>
12 #include <linux/etherdevice.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
20 #include <net/rtnetlink.h>
21 #include "hclge_cmd.h"
22 #include "hclge_dcb.h"
23 #include "hclge_main.h"
24 #include "hclge_mbx.h"
25 #include "hclge_mdio.h"
26 #include "hclge_tm.h"
27 #include "hnae3.h"
28
29 #define HCLGE_NAME "hclge"
30 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
31 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
32 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
33 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
34
35 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
36 enum hclge_mta_dmac_sel_type mta_mac_sel,
37 bool enable);
38 static int hclge_init_vlan_config(struct hclge_dev *hdev);
39 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
40
41 static struct hnae3_ae_algo ae_algo;
42
43 static const struct pci_device_id ae_algo_pci_tbl[] = {
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
50 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
51 /* required last entry */
52 {0, }
53 };
54
55 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
56 "Mac Loopback test",
57 "Serdes Loopback test",
58 "Phy Loopback test"
59 };
60
61 static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
62 {"igu_rx_oversize_pkt",
63 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
64 {"igu_rx_undersize_pkt",
65 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
66 {"igu_rx_out_all_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
68 {"igu_rx_uni_pkt",
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
70 {"igu_rx_multi_pkt",
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
72 {"igu_rx_broad_pkt",
73 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
74 {"egu_tx_out_all_pkt",
75 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
76 {"egu_tx_uni_pkt",
77 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
78 {"egu_tx_multi_pkt",
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
80 {"egu_tx_broad_pkt",
81 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
82 {"ssu_ppp_mac_key_num",
83 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
84 {"ssu_ppp_host_key_num",
85 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
86 {"ppp_ssu_mac_rlt_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
88 {"ppp_ssu_host_rlt_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
90 {"ssu_tx_in_num",
91 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
92 {"ssu_tx_out_num",
93 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
94 {"ssu_rx_in_num",
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
96 {"ssu_rx_out_num",
97 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
98 };
99
100 static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
101 {"igu_rx_err_pkt",
102 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
103 {"igu_rx_no_eof_pkt",
104 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
105 {"igu_rx_no_sof_pkt",
106 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
107 {"egu_tx_1588_pkt",
108 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
109 {"ssu_full_drop_num",
110 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
111 {"ssu_part_drop_num",
112 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
113 {"ppp_key_drop_num",
114 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
115 {"ppp_rlt_drop_num",
116 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
117 {"ssu_key_drop_num",
118 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
119 {"pkt_curr_buf_cnt",
120 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
121 {"qcn_fb_rcv_cnt",
122 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
123 {"qcn_fb_drop_cnt",
124 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
125 {"qcn_fb_invaild_cnt",
126 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
127 {"rx_packet_tc0_in_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
129 {"rx_packet_tc1_in_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
131 {"rx_packet_tc2_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
133 {"rx_packet_tc3_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
135 {"rx_packet_tc4_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
137 {"rx_packet_tc5_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
139 {"rx_packet_tc6_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
141 {"rx_packet_tc7_in_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
143 {"rx_packet_tc0_out_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
145 {"rx_packet_tc1_out_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
147 {"rx_packet_tc2_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
149 {"rx_packet_tc3_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
151 {"rx_packet_tc4_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
153 {"rx_packet_tc5_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
155 {"rx_packet_tc6_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
157 {"rx_packet_tc7_out_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
159 {"tx_packet_tc0_in_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
161 {"tx_packet_tc1_in_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
163 {"tx_packet_tc2_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
165 {"tx_packet_tc3_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
167 {"tx_packet_tc4_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
169 {"tx_packet_tc5_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
171 {"tx_packet_tc6_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
173 {"tx_packet_tc7_in_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
175 {"tx_packet_tc0_out_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
177 {"tx_packet_tc1_out_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
179 {"tx_packet_tc2_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
181 {"tx_packet_tc3_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
183 {"tx_packet_tc4_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
185 {"tx_packet_tc5_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
187 {"tx_packet_tc6_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
189 {"tx_packet_tc7_out_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
191 {"pkt_curr_buf_tc0_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
193 {"pkt_curr_buf_tc1_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
195 {"pkt_curr_buf_tc2_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
197 {"pkt_curr_buf_tc3_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
199 {"pkt_curr_buf_tc4_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
201 {"pkt_curr_buf_tc5_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
203 {"pkt_curr_buf_tc6_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
205 {"pkt_curr_buf_tc7_cnt",
206 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
207 {"mb_uncopy_num",
208 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
209 {"lo_pri_unicast_rlt_drop_num",
210 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
211 {"hi_pri_multicast_rlt_drop_num",
212 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
213 {"lo_pri_multicast_rlt_drop_num",
214 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
215 {"rx_oq_drop_pkt_cnt",
216 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
217 {"tx_oq_drop_pkt_cnt",
218 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
219 {"nic_l2_err_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
221 {"roc_l2_err_drop_pkt_cnt",
222 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
223 };
224
225 static const struct hclge_comm_stats_str g_mac_stats_string[] = {
226 {"mac_tx_mac_pause_num",
227 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
228 {"mac_rx_mac_pause_num",
229 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
230 {"mac_tx_pfc_pri0_pkt_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
232 {"mac_tx_pfc_pri1_pkt_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
234 {"mac_tx_pfc_pri2_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
236 {"mac_tx_pfc_pri3_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
238 {"mac_tx_pfc_pri4_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
240 {"mac_tx_pfc_pri5_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
242 {"mac_tx_pfc_pri6_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
244 {"mac_tx_pfc_pri7_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
246 {"mac_rx_pfc_pri0_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
248 {"mac_rx_pfc_pri1_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
250 {"mac_rx_pfc_pri2_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
252 {"mac_rx_pfc_pri3_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
254 {"mac_rx_pfc_pri4_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
256 {"mac_rx_pfc_pri5_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
258 {"mac_rx_pfc_pri6_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
260 {"mac_rx_pfc_pri7_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
262 {"mac_tx_total_pkt_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
264 {"mac_tx_total_oct_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
266 {"mac_tx_good_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
268 {"mac_tx_bad_pkt_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
270 {"mac_tx_good_oct_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
272 {"mac_tx_bad_oct_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
274 {"mac_tx_uni_pkt_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
276 {"mac_tx_multi_pkt_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
278 {"mac_tx_broad_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
280 {"mac_tx_undersize_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
282 {"mac_tx_overrsize_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_overrsize_pkt_num)},
284 {"mac_tx_64_oct_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
286 {"mac_tx_65_127_oct_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
288 {"mac_tx_128_255_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
290 {"mac_tx_256_511_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
292 {"mac_tx_512_1023_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
294 {"mac_tx_1024_1518_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
296 {"mac_tx_1519_max_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_oct_pkt_num)},
298 {"mac_rx_total_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
300 {"mac_rx_total_oct_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
302 {"mac_rx_good_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
304 {"mac_rx_bad_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
306 {"mac_rx_good_oct_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
308 {"mac_rx_bad_oct_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
310 {"mac_rx_uni_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
312 {"mac_rx_multi_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
314 {"mac_rx_broad_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
316 {"mac_rx_undersize_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
318 {"mac_rx_overrsize_pkt_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_overrsize_pkt_num)},
320 {"mac_rx_64_oct_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
322 {"mac_rx_65_127_oct_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
324 {"mac_rx_128_255_oct_pkt_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
326 {"mac_rx_256_511_oct_pkt_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
328 {"mac_rx_512_1023_oct_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
330 {"mac_rx_1024_1518_oct_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
332 {"mac_rx_1519_max_oct_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_oct_pkt_num)},
334
335 {"mac_trans_fragment_pkt_num",
336 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_fragment_pkt_num)},
337 {"mac_trans_undermin_pkt_num",
338 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_undermin_pkt_num)},
339 {"mac_trans_jabber_pkt_num",
340 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_jabber_pkt_num)},
341 {"mac_trans_err_all_pkt_num",
342 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_err_all_pkt_num)},
343 {"mac_trans_from_app_good_pkt_num",
344 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_good_pkt_num)},
345 {"mac_trans_from_app_bad_pkt_num",
346 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_bad_pkt_num)},
347 {"mac_rcv_fragment_pkt_num",
348 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fragment_pkt_num)},
349 {"mac_rcv_undermin_pkt_num",
350 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_undermin_pkt_num)},
351 {"mac_rcv_jabber_pkt_num",
352 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_jabber_pkt_num)},
353 {"mac_rcv_fcs_err_pkt_num",
354 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fcs_err_pkt_num)},
355 {"mac_rcv_send_app_good_pkt_num",
356 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_good_pkt_num)},
357 {"mac_rcv_send_app_bad_pkt_num",
358 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_bad_pkt_num)}
359 };
360
361 static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
362 {
363 #define HCLGE_64_BIT_CMD_NUM 5
364 #define HCLGE_64_BIT_RTN_DATANUM 4
365 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
366 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
367 __le64 *desc_data;
368 int i, k, n;
369 int ret;
370
371 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
372 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
373 if (ret) {
374 dev_err(&hdev->pdev->dev,
375 "Get 64 bit pkt stats fail, status = %d.\n", ret);
376 return ret;
377 }
378
379 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
380 if (unlikely(i == 0)) {
381 desc_data = (__le64 *)(&desc[i].data[0]);
382 n = HCLGE_64_BIT_RTN_DATANUM - 1;
383 } else {
384 desc_data = (__le64 *)(&desc[i]);
385 n = HCLGE_64_BIT_RTN_DATANUM;
386 }
387 for (k = 0; k < n; k++) {
388 *data++ += le64_to_cpu(*desc_data);
389 desc_data++;
390 }
391 }
392
393 return 0;
394 }
395
396 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
397 {
398 stats->pkt_curr_buf_cnt = 0;
399 stats->pkt_curr_buf_tc0_cnt = 0;
400 stats->pkt_curr_buf_tc1_cnt = 0;
401 stats->pkt_curr_buf_tc2_cnt = 0;
402 stats->pkt_curr_buf_tc3_cnt = 0;
403 stats->pkt_curr_buf_tc4_cnt = 0;
404 stats->pkt_curr_buf_tc5_cnt = 0;
405 stats->pkt_curr_buf_tc6_cnt = 0;
406 stats->pkt_curr_buf_tc7_cnt = 0;
407 }
408
409 static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
410 {
411 #define HCLGE_32_BIT_CMD_NUM 8
412 #define HCLGE_32_BIT_RTN_DATANUM 8
413
414 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
415 struct hclge_32_bit_stats *all_32_bit_stats;
416 __le32 *desc_data;
417 int i, k, n;
418 u64 *data;
419 int ret;
420
421 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
422 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
423
424 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
425 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
426 if (ret) {
427 dev_err(&hdev->pdev->dev,
428 "Get 32 bit pkt stats fail, status = %d.\n", ret);
429
430 return ret;
431 }
432
433 hclge_reset_partial_32bit_counter(all_32_bit_stats);
434 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
435 if (unlikely(i == 0)) {
436 __le16 *desc_data_16bit;
437
438 all_32_bit_stats->igu_rx_err_pkt +=
439 le32_to_cpu(desc[i].data[0]);
440
441 desc_data_16bit = (__le16 *)&desc[i].data[1];
442 all_32_bit_stats->igu_rx_no_eof_pkt +=
443 le16_to_cpu(*desc_data_16bit);
444
445 desc_data_16bit++;
446 all_32_bit_stats->igu_rx_no_sof_pkt +=
447 le16_to_cpu(*desc_data_16bit);
448
449 desc_data = &desc[i].data[2];
450 n = HCLGE_32_BIT_RTN_DATANUM - 4;
451 } else {
452 desc_data = (__le32 *)&desc[i];
453 n = HCLGE_32_BIT_RTN_DATANUM;
454 }
455 for (k = 0; k < n; k++) {
456 *data++ += le32_to_cpu(*desc_data);
457 desc_data++;
458 }
459 }
460
461 return 0;
462 }
463
464 static int hclge_mac_update_stats(struct hclge_dev *hdev)
465 {
466 #define HCLGE_MAC_CMD_NUM 17
467 #define HCLGE_RTN_DATA_NUM 4
468
469 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
470 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
471 __le64 *desc_data;
472 int i, k, n;
473 int ret;
474
475 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
476 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
477 if (ret) {
478 dev_err(&hdev->pdev->dev,
479 "Get MAC pkt stats fail, status = %d.\n", ret);
480
481 return ret;
482 }
483
484 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
485 if (unlikely(i == 0)) {
486 desc_data = (__le64 *)(&desc[i].data[0]);
487 n = HCLGE_RTN_DATA_NUM - 2;
488 } else {
489 desc_data = (__le64 *)(&desc[i]);
490 n = HCLGE_RTN_DATA_NUM;
491 }
492 for (k = 0; k < n; k++) {
493 *data++ += le64_to_cpu(*desc_data);
494 desc_data++;
495 }
496 }
497
498 return 0;
499 }
500
501 static int hclge_tqps_update_stats(struct hnae3_handle *handle)
502 {
503 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
504 struct hclge_vport *vport = hclge_get_vport(handle);
505 struct hclge_dev *hdev = vport->back;
506 struct hnae3_queue *queue;
507 struct hclge_desc desc[1];
508 struct hclge_tqp *tqp;
509 int ret, i;
510
511 for (i = 0; i < kinfo->num_tqps; i++) {
512 queue = handle->kinfo.tqp[i];
513 tqp = container_of(queue, struct hclge_tqp, q);
514 /* command : HCLGE_OPC_QUERY_IGU_STAT */
515 hclge_cmd_setup_basic_desc(&desc[0],
516 HCLGE_OPC_QUERY_RX_STATUS,
517 true);
518
519 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
520 ret = hclge_cmd_send(&hdev->hw, desc, 1);
521 if (ret) {
522 dev_err(&hdev->pdev->dev,
523 "Query tqp stat fail, status = %d,queue = %d\n",
524 ret, i);
525 return ret;
526 }
527 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
528 le32_to_cpu(desc[0].data[4]);
529 }
530
531 for (i = 0; i < kinfo->num_tqps; i++) {
532 queue = handle->kinfo.tqp[i];
533 tqp = container_of(queue, struct hclge_tqp, q);
534 /* command : HCLGE_OPC_QUERY_IGU_STAT */
535 hclge_cmd_setup_basic_desc(&desc[0],
536 HCLGE_OPC_QUERY_TX_STATUS,
537 true);
538
539 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
540 ret = hclge_cmd_send(&hdev->hw, desc, 1);
541 if (ret) {
542 dev_err(&hdev->pdev->dev,
543 "Query tqp stat fail, status = %d,queue = %d\n",
544 ret, i);
545 return ret;
546 }
547 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
548 le32_to_cpu(desc[0].data[4]);
549 }
550
551 return 0;
552 }
553
554 static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
555 {
556 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
557 struct hclge_tqp *tqp;
558 u64 *buff = data;
559 int i;
560
561 for (i = 0; i < kinfo->num_tqps; i++) {
562 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
563 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
564 }
565
566 for (i = 0; i < kinfo->num_tqps; i++) {
567 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
568 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
569 }
570
571 return buff;
572 }
573
574 static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
575 {
576 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
577
578 return kinfo->num_tqps * (2);
579 }
580
581 static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
582 {
583 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
584 u8 *buff = data;
585 int i = 0;
586
587 for (i = 0; i < kinfo->num_tqps; i++) {
588 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
589 struct hclge_tqp, q);
590 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_tx_pktnum_rcd",
591 tqp->index);
592 buff = buff + ETH_GSTRING_LEN;
593 }
594
595 for (i = 0; i < kinfo->num_tqps; i++) {
596 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
597 struct hclge_tqp, q);
598 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_rx_pktnum_rcd",
599 tqp->index);
600 buff = buff + ETH_GSTRING_LEN;
601 }
602
603 return buff;
604 }
605
606 static u64 *hclge_comm_get_stats(void *comm_stats,
607 const struct hclge_comm_stats_str strs[],
608 int size, u64 *data)
609 {
610 u64 *buf = data;
611 u32 i;
612
613 for (i = 0; i < size; i++)
614 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
615
616 return buf + size;
617 }
618
619 static u8 *hclge_comm_get_strings(u32 stringset,
620 const struct hclge_comm_stats_str strs[],
621 int size, u8 *data)
622 {
623 char *buff = (char *)data;
624 u32 i;
625
626 if (stringset != ETH_SS_STATS)
627 return buff;
628
629 for (i = 0; i < size; i++) {
630 snprintf(buff, ETH_GSTRING_LEN,
631 strs[i].desc);
632 buff = buff + ETH_GSTRING_LEN;
633 }
634
635 return (u8 *)buff;
636 }
637
638 static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
639 struct net_device_stats *net_stats)
640 {
641 net_stats->tx_dropped = 0;
642 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
643 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
644 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
645
646 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
647 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
648 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_err_pkt;
649 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
650 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
651 net_stats->rx_errors += hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
652
653 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
654 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
655
656 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
657 net_stats->rx_length_errors =
658 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
659 net_stats->rx_length_errors +=
660 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
661 net_stats->rx_over_errors =
662 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
663 }
664
665 static void hclge_update_stats_for_all(struct hclge_dev *hdev)
666 {
667 struct hnae3_handle *handle;
668 int status;
669
670 handle = &hdev->vport[0].nic;
671 if (handle->client) {
672 status = hclge_tqps_update_stats(handle);
673 if (status) {
674 dev_err(&hdev->pdev->dev,
675 "Update TQPS stats fail, status = %d.\n",
676 status);
677 }
678 }
679
680 status = hclge_mac_update_stats(hdev);
681 if (status)
682 dev_err(&hdev->pdev->dev,
683 "Update MAC stats fail, status = %d.\n", status);
684
685 status = hclge_32_bit_update_stats(hdev);
686 if (status)
687 dev_err(&hdev->pdev->dev,
688 "Update 32 bit stats fail, status = %d.\n",
689 status);
690
691 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
692 }
693
694 static void hclge_update_stats(struct hnae3_handle *handle,
695 struct net_device_stats *net_stats)
696 {
697 struct hclge_vport *vport = hclge_get_vport(handle);
698 struct hclge_dev *hdev = vport->back;
699 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
700 int status;
701
702 status = hclge_mac_update_stats(hdev);
703 if (status)
704 dev_err(&hdev->pdev->dev,
705 "Update MAC stats fail, status = %d.\n",
706 status);
707
708 status = hclge_32_bit_update_stats(hdev);
709 if (status)
710 dev_err(&hdev->pdev->dev,
711 "Update 32 bit stats fail, status = %d.\n",
712 status);
713
714 status = hclge_64_bit_update_stats(hdev);
715 if (status)
716 dev_err(&hdev->pdev->dev,
717 "Update 64 bit stats fail, status = %d.\n",
718 status);
719
720 status = hclge_tqps_update_stats(handle);
721 if (status)
722 dev_err(&hdev->pdev->dev,
723 "Update TQPS stats fail, status = %d.\n",
724 status);
725
726 hclge_update_netstat(hw_stats, net_stats);
727 }
728
729 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
730 {
731 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
732
733 struct hclge_vport *vport = hclge_get_vport(handle);
734 struct hclge_dev *hdev = vport->back;
735 int count = 0;
736
737 /* Loopback test support rules:
738 * mac: only GE mode support
739 * serdes: all mac mode will support include GE/XGE/LGE/CGE
740 * phy: only support when phy device exist on board
741 */
742 if (stringset == ETH_SS_TEST) {
743 /* clear loopback bit flags at first */
744 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
745 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
746 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
747 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
748 count += 1;
749 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
750 } else {
751 count = -EOPNOTSUPP;
752 }
753 } else if (stringset == ETH_SS_STATS) {
754 count = ARRAY_SIZE(g_mac_stats_string) +
755 ARRAY_SIZE(g_all_32bit_stats_string) +
756 ARRAY_SIZE(g_all_64bit_stats_string) +
757 hclge_tqps_get_sset_count(handle, stringset);
758 }
759
760 return count;
761 }
762
763 static void hclge_get_strings(struct hnae3_handle *handle,
764 u32 stringset,
765 u8 *data)
766 {
767 u8 *p = (char *)data;
768 int size;
769
770 if (stringset == ETH_SS_STATS) {
771 size = ARRAY_SIZE(g_mac_stats_string);
772 p = hclge_comm_get_strings(stringset,
773 g_mac_stats_string,
774 size,
775 p);
776 size = ARRAY_SIZE(g_all_32bit_stats_string);
777 p = hclge_comm_get_strings(stringset,
778 g_all_32bit_stats_string,
779 size,
780 p);
781 size = ARRAY_SIZE(g_all_64bit_stats_string);
782 p = hclge_comm_get_strings(stringset,
783 g_all_64bit_stats_string,
784 size,
785 p);
786 p = hclge_tqps_get_strings(handle, p);
787 } else if (stringset == ETH_SS_TEST) {
788 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
789 memcpy(p,
790 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
791 ETH_GSTRING_LEN);
792 p += ETH_GSTRING_LEN;
793 }
794 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
795 memcpy(p,
796 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
797 ETH_GSTRING_LEN);
798 p += ETH_GSTRING_LEN;
799 }
800 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
801 memcpy(p,
802 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
803 ETH_GSTRING_LEN);
804 p += ETH_GSTRING_LEN;
805 }
806 }
807 }
808
809 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
810 {
811 struct hclge_vport *vport = hclge_get_vport(handle);
812 struct hclge_dev *hdev = vport->back;
813 u64 *p;
814
815 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
816 g_mac_stats_string,
817 ARRAY_SIZE(g_mac_stats_string),
818 data);
819 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
820 g_all_32bit_stats_string,
821 ARRAY_SIZE(g_all_32bit_stats_string),
822 p);
823 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
824 g_all_64bit_stats_string,
825 ARRAY_SIZE(g_all_64bit_stats_string),
826 p);
827 p = hclge_tqps_get_stats(handle, p);
828 }
829
830 static int hclge_parse_func_status(struct hclge_dev *hdev,
831 struct hclge_func_status_cmd *status)
832 {
833 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
834 return -EINVAL;
835
836 /* Set the pf to main pf */
837 if (status->pf_state & HCLGE_PF_STATE_MAIN)
838 hdev->flag |= HCLGE_FLAG_MAIN;
839 else
840 hdev->flag &= ~HCLGE_FLAG_MAIN;
841
842 return 0;
843 }
844
845 static int hclge_query_function_status(struct hclge_dev *hdev)
846 {
847 struct hclge_func_status_cmd *req;
848 struct hclge_desc desc;
849 int timeout = 0;
850 int ret;
851
852 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
853 req = (struct hclge_func_status_cmd *)desc.data;
854
855 do {
856 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
857 if (ret) {
858 dev_err(&hdev->pdev->dev,
859 "query function status failed %d.\n",
860 ret);
861
862 return ret;
863 }
864
865 /* Check pf reset is done */
866 if (req->pf_state)
867 break;
868 usleep_range(1000, 2000);
869 } while (timeout++ < 5);
870
871 ret = hclge_parse_func_status(hdev, req);
872
873 return ret;
874 }
875
876 static int hclge_query_pf_resource(struct hclge_dev *hdev)
877 {
878 struct hclge_pf_res_cmd *req;
879 struct hclge_desc desc;
880 int ret;
881
882 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
883 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
884 if (ret) {
885 dev_err(&hdev->pdev->dev,
886 "query pf resource failed %d.\n", ret);
887 return ret;
888 }
889
890 req = (struct hclge_pf_res_cmd *)desc.data;
891 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
892 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
893
894 if (hnae3_dev_roce_supported(hdev)) {
895 hdev->num_roce_msi =
896 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
897 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
898
899 /* PF should have NIC vectors and Roce vectors,
900 * NIC vectors are queued before Roce vectors.
901 */
902 hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET;
903 } else {
904 hdev->num_msi =
905 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
906 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
907 }
908
909 return 0;
910 }
911
912 static int hclge_parse_speed(int speed_cmd, int *speed)
913 {
914 switch (speed_cmd) {
915 case 6:
916 *speed = HCLGE_MAC_SPEED_10M;
917 break;
918 case 7:
919 *speed = HCLGE_MAC_SPEED_100M;
920 break;
921 case 0:
922 *speed = HCLGE_MAC_SPEED_1G;
923 break;
924 case 1:
925 *speed = HCLGE_MAC_SPEED_10G;
926 break;
927 case 2:
928 *speed = HCLGE_MAC_SPEED_25G;
929 break;
930 case 3:
931 *speed = HCLGE_MAC_SPEED_40G;
932 break;
933 case 4:
934 *speed = HCLGE_MAC_SPEED_50G;
935 break;
936 case 5:
937 *speed = HCLGE_MAC_SPEED_100G;
938 break;
939 default:
940 return -EINVAL;
941 }
942
943 return 0;
944 }
945
946 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
947 {
948 struct hclge_cfg_param_cmd *req;
949 u64 mac_addr_tmp_high;
950 u64 mac_addr_tmp;
951 int i;
952
953 req = (struct hclge_cfg_param_cmd *)desc[0].data;
954
955 /* get the configuration */
956 cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]),
957 HCLGE_CFG_VMDQ_M,
958 HCLGE_CFG_VMDQ_S);
959 cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
960 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
961 cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
962 HCLGE_CFG_TQP_DESC_N_M,
963 HCLGE_CFG_TQP_DESC_N_S);
964
965 cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]),
966 HCLGE_CFG_PHY_ADDR_M,
967 HCLGE_CFG_PHY_ADDR_S);
968 cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]),
969 HCLGE_CFG_MEDIA_TP_M,
970 HCLGE_CFG_MEDIA_TP_S);
971 cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]),
972 HCLGE_CFG_RX_BUF_LEN_M,
973 HCLGE_CFG_RX_BUF_LEN_S);
974 /* get mac_address */
975 mac_addr_tmp = __le32_to_cpu(req->param[2]);
976 mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]),
977 HCLGE_CFG_MAC_ADDR_H_M,
978 HCLGE_CFG_MAC_ADDR_H_S);
979
980 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
981
982 cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]),
983 HCLGE_CFG_DEFAULT_SPEED_M,
984 HCLGE_CFG_DEFAULT_SPEED_S);
985 cfg->rss_size_max = hnae_get_field(__le32_to_cpu(req->param[3]),
986 HCLGE_CFG_RSS_SIZE_M,
987 HCLGE_CFG_RSS_SIZE_S);
988
989 for (i = 0; i < ETH_ALEN; i++)
990 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
991
992 req = (struct hclge_cfg_param_cmd *)desc[1].data;
993 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
994 }
995
996 /* hclge_get_cfg: query the static parameter from flash
997 * @hdev: pointer to struct hclge_dev
998 * @hcfg: the config structure to be getted
999 */
1000 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1001 {
1002 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
1003 struct hclge_cfg_param_cmd *req;
1004 int i, ret;
1005
1006 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
1007 u32 offset = 0;
1008
1009 req = (struct hclge_cfg_param_cmd *)desc[i].data;
1010 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1011 true);
1012 hnae_set_field(offset, HCLGE_CFG_OFFSET_M,
1013 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1014 /* Len should be united by 4 bytes when send to hardware */
1015 hnae_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
1016 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
1017 req->offset = cpu_to_le32(offset);
1018 }
1019
1020 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1021 if (ret) {
1022 dev_err(&hdev->pdev->dev,
1023 "get config failed %d.\n", ret);
1024 return ret;
1025 }
1026
1027 hclge_parse_cfg(hcfg, desc);
1028 return 0;
1029 }
1030
1031 static int hclge_get_cap(struct hclge_dev *hdev)
1032 {
1033 int ret;
1034
1035 ret = hclge_query_function_status(hdev);
1036 if (ret) {
1037 dev_err(&hdev->pdev->dev,
1038 "query function status error %d.\n", ret);
1039 return ret;
1040 }
1041
1042 /* get pf resource */
1043 ret = hclge_query_pf_resource(hdev);
1044 if (ret) {
1045 dev_err(&hdev->pdev->dev,
1046 "query pf resource error %d.\n", ret);
1047 return ret;
1048 }
1049
1050 return 0;
1051 }
1052
1053 static int hclge_configure(struct hclge_dev *hdev)
1054 {
1055 struct hclge_cfg cfg;
1056 int ret, i;
1057
1058 ret = hclge_get_cfg(hdev, &cfg);
1059 if (ret) {
1060 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1061 return ret;
1062 }
1063
1064 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1065 hdev->base_tqp_pid = 0;
1066 hdev->rss_size_max = cfg.rss_size_max;
1067 hdev->rx_buf_len = cfg.rx_buf_len;
1068 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
1069 hdev->hw.mac.media_type = cfg.media_type;
1070 hdev->hw.mac.phy_addr = cfg.phy_addr;
1071 hdev->num_desc = cfg.tqp_desc_num;
1072 hdev->tm_info.num_pg = 1;
1073 hdev->tc_max = cfg.tc_num;
1074 hdev->tm_info.hw_pfc_map = 0;
1075
1076 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1077 if (ret) {
1078 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1079 return ret;
1080 }
1081
1082 if ((hdev->tc_max > HNAE3_MAX_TC) ||
1083 (hdev->tc_max < 1)) {
1084 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
1085 hdev->tc_max);
1086 hdev->tc_max = 1;
1087 }
1088
1089 /* Dev does not support DCB */
1090 if (!hnae3_dev_dcb_supported(hdev)) {
1091 hdev->tc_max = 1;
1092 hdev->pfc_max = 0;
1093 } else {
1094 hdev->pfc_max = hdev->tc_max;
1095 }
1096
1097 hdev->tm_info.num_tc = hdev->tc_max;
1098
1099 /* Currently not support uncontiuous tc */
1100 for (i = 0; i < hdev->tm_info.num_tc; i++)
1101 hnae_set_bit(hdev->hw_tc_map, i, 1);
1102
1103 if (!hdev->num_vmdq_vport && !hdev->num_req_vfs)
1104 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1105 else
1106 hdev->tx_sch_mode = HCLGE_FLAG_VNET_BASE_SCH_MODE;
1107
1108 return ret;
1109 }
1110
1111 static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1112 int tso_mss_max)
1113 {
1114 struct hclge_cfg_tso_status_cmd *req;
1115 struct hclge_desc desc;
1116 u16 tso_mss;
1117
1118 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1119
1120 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
1121
1122 tso_mss = 0;
1123 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1124 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
1125 req->tso_mss_min = cpu_to_le16(tso_mss);
1126
1127 tso_mss = 0;
1128 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1129 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
1130 req->tso_mss_max = cpu_to_le16(tso_mss);
1131
1132 return hclge_cmd_send(&hdev->hw, &desc, 1);
1133 }
1134
1135 static int hclge_alloc_tqps(struct hclge_dev *hdev)
1136 {
1137 struct hclge_tqp *tqp;
1138 int i;
1139
1140 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1141 sizeof(struct hclge_tqp), GFP_KERNEL);
1142 if (!hdev->htqp)
1143 return -ENOMEM;
1144
1145 tqp = hdev->htqp;
1146
1147 for (i = 0; i < hdev->num_tqps; i++) {
1148 tqp->dev = &hdev->pdev->dev;
1149 tqp->index = i;
1150
1151 tqp->q.ae_algo = &ae_algo;
1152 tqp->q.buf_size = hdev->rx_buf_len;
1153 tqp->q.desc_num = hdev->num_desc;
1154 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1155 i * HCLGE_TQP_REG_SIZE;
1156
1157 tqp++;
1158 }
1159
1160 return 0;
1161 }
1162
1163 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1164 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1165 {
1166 struct hclge_tqp_map_cmd *req;
1167 struct hclge_desc desc;
1168 int ret;
1169
1170 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1171
1172 req = (struct hclge_tqp_map_cmd *)desc.data;
1173 req->tqp_id = cpu_to_le16(tqp_pid);
1174 req->tqp_vf = func_id;
1175 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1176 1 << HCLGE_TQP_MAP_EN_B;
1177 req->tqp_vid = cpu_to_le16(tqp_vid);
1178
1179 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1180 if (ret) {
1181 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n",
1182 ret);
1183 return ret;
1184 }
1185
1186 return 0;
1187 }
1188
1189 static int hclge_assign_tqp(struct hclge_vport *vport,
1190 struct hnae3_queue **tqp, u16 num_tqps)
1191 {
1192 struct hclge_dev *hdev = vport->back;
1193 int i, alloced;
1194
1195 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1196 alloced < num_tqps; i++) {
1197 if (!hdev->htqp[i].alloced) {
1198 hdev->htqp[i].q.handle = &vport->nic;
1199 hdev->htqp[i].q.tqp_index = alloced;
1200 tqp[alloced] = &hdev->htqp[i].q;
1201 hdev->htqp[i].alloced = true;
1202 alloced++;
1203 }
1204 }
1205 vport->alloc_tqps = num_tqps;
1206
1207 return 0;
1208 }
1209
1210 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1211 {
1212 struct hnae3_handle *nic = &vport->nic;
1213 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1214 struct hclge_dev *hdev = vport->back;
1215 int i, ret;
1216
1217 kinfo->num_desc = hdev->num_desc;
1218 kinfo->rx_buf_len = hdev->rx_buf_len;
1219 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1220 kinfo->rss_size
1221 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1222 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1223
1224 for (i = 0; i < HNAE3_MAX_TC; i++) {
1225 if (hdev->hw_tc_map & BIT(i)) {
1226 kinfo->tc_info[i].enable = true;
1227 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1228 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1229 kinfo->tc_info[i].tc = i;
1230 } else {
1231 /* Set to default queue if TC is disable */
1232 kinfo->tc_info[i].enable = false;
1233 kinfo->tc_info[i].tqp_offset = 0;
1234 kinfo->tc_info[i].tqp_count = 1;
1235 kinfo->tc_info[i].tc = 0;
1236 }
1237 }
1238
1239 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1240 sizeof(struct hnae3_queue *), GFP_KERNEL);
1241 if (!kinfo->tqp)
1242 return -ENOMEM;
1243
1244 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
1245 if (ret) {
1246 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1247 return -EINVAL;
1248 }
1249
1250 return 0;
1251 }
1252
1253 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1254 struct hclge_vport *vport)
1255 {
1256 struct hnae3_handle *nic = &vport->nic;
1257 struct hnae3_knic_private_info *kinfo;
1258 u16 i;
1259
1260 kinfo = &nic->kinfo;
1261 for (i = 0; i < kinfo->num_tqps; i++) {
1262 struct hclge_tqp *q =
1263 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1264 bool is_pf;
1265 int ret;
1266
1267 is_pf = !(vport->vport_id);
1268 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1269 i, is_pf);
1270 if (ret)
1271 return ret;
1272 }
1273
1274 return 0;
1275 }
1276
1277 static int hclge_map_tqp(struct hclge_dev *hdev)
1278 {
1279 struct hclge_vport *vport = hdev->vport;
1280 u16 i, num_vport;
1281
1282 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1283 for (i = 0; i < num_vport; i++) {
1284 int ret;
1285
1286 ret = hclge_map_tqp_to_vport(hdev, vport);
1287 if (ret)
1288 return ret;
1289
1290 vport++;
1291 }
1292
1293 return 0;
1294 }
1295
1296 static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1297 {
1298 /* this would be initialized later */
1299 }
1300
1301 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1302 {
1303 struct hnae3_handle *nic = &vport->nic;
1304 struct hclge_dev *hdev = vport->back;
1305 int ret;
1306
1307 nic->pdev = hdev->pdev;
1308 nic->ae_algo = &ae_algo;
1309 nic->numa_node_mask = hdev->numa_node_mask;
1310
1311 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1312 ret = hclge_knic_setup(vport, num_tqps);
1313 if (ret) {
1314 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1315 ret);
1316 return ret;
1317 }
1318 } else {
1319 hclge_unic_setup(vport, num_tqps);
1320 }
1321
1322 return 0;
1323 }
1324
1325 static int hclge_alloc_vport(struct hclge_dev *hdev)
1326 {
1327 struct pci_dev *pdev = hdev->pdev;
1328 struct hclge_vport *vport;
1329 u32 tqp_main_vport;
1330 u32 tqp_per_vport;
1331 int num_vport, i;
1332 int ret;
1333
1334 /* We need to alloc a vport for main NIC of PF */
1335 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1336
1337 if (hdev->num_tqps < num_vport)
1338 num_vport = hdev->num_tqps;
1339
1340 /* Alloc the same number of TQPs for every vport */
1341 tqp_per_vport = hdev->num_tqps / num_vport;
1342 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1343
1344 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1345 GFP_KERNEL);
1346 if (!vport)
1347 return -ENOMEM;
1348
1349 hdev->vport = vport;
1350 hdev->num_alloc_vport = num_vport;
1351
1352 #ifdef CONFIG_PCI_IOV
1353 /* Enable SRIOV */
1354 if (hdev->num_req_vfs) {
1355 dev_info(&pdev->dev, "active VFs(%d) found, enabling SRIOV\n",
1356 hdev->num_req_vfs);
1357 ret = pci_enable_sriov(hdev->pdev, hdev->num_req_vfs);
1358 if (ret) {
1359 hdev->num_alloc_vfs = 0;
1360 dev_err(&pdev->dev, "SRIOV enable failed %d\n",
1361 ret);
1362 return ret;
1363 }
1364 }
1365 hdev->num_alloc_vfs = hdev->num_req_vfs;
1366 #endif
1367
1368 for (i = 0; i < num_vport; i++) {
1369 vport->back = hdev;
1370 vport->vport_id = i;
1371
1372 if (i == 0)
1373 ret = hclge_vport_setup(vport, tqp_main_vport);
1374 else
1375 ret = hclge_vport_setup(vport, tqp_per_vport);
1376 if (ret) {
1377 dev_err(&pdev->dev,
1378 "vport setup failed for vport %d, %d\n",
1379 i, ret);
1380 return ret;
1381 }
1382
1383 vport++;
1384 }
1385
1386 return 0;
1387 }
1388
1389 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1390 struct hclge_pkt_buf_alloc *buf_alloc)
1391 {
1392 /* TX buffer size is unit by 128 byte */
1393 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1394 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1395 struct hclge_tx_buff_alloc_cmd *req;
1396 struct hclge_desc desc;
1397 int ret;
1398 u8 i;
1399
1400 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
1401
1402 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
1403 for (i = 0; i < HCLGE_TC_NUM; i++) {
1404 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1405
1406 req->tx_pkt_buff[i] =
1407 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1408 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
1409 }
1410
1411 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1412 if (ret) {
1413 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1414 ret);
1415 return ret;
1416 }
1417
1418 return 0;
1419 }
1420
1421 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1422 struct hclge_pkt_buf_alloc *buf_alloc)
1423 {
1424 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
1425
1426 if (ret) {
1427 dev_err(&hdev->pdev->dev,
1428 "tx buffer alloc failed %d\n", ret);
1429 return ret;
1430 }
1431
1432 return 0;
1433 }
1434
1435 static int hclge_get_tc_num(struct hclge_dev *hdev)
1436 {
1437 int i, cnt = 0;
1438
1439 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1440 if (hdev->hw_tc_map & BIT(i))
1441 cnt++;
1442 return cnt;
1443 }
1444
1445 static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1446 {
1447 int i, cnt = 0;
1448
1449 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1450 if (hdev->hw_tc_map & BIT(i) &&
1451 hdev->tm_info.hw_pfc_map & BIT(i))
1452 cnt++;
1453 return cnt;
1454 }
1455
1456 /* Get the number of pfc enabled TCs, which have private buffer */
1457 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1458 struct hclge_pkt_buf_alloc *buf_alloc)
1459 {
1460 struct hclge_priv_buf *priv;
1461 int i, cnt = 0;
1462
1463 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1464 priv = &buf_alloc->priv_buf[i];
1465 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1466 priv->enable)
1467 cnt++;
1468 }
1469
1470 return cnt;
1471 }
1472
1473 /* Get the number of pfc disabled TCs, which have private buffer */
1474 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1475 struct hclge_pkt_buf_alloc *buf_alloc)
1476 {
1477 struct hclge_priv_buf *priv;
1478 int i, cnt = 0;
1479
1480 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1481 priv = &buf_alloc->priv_buf[i];
1482 if (hdev->hw_tc_map & BIT(i) &&
1483 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1484 priv->enable)
1485 cnt++;
1486 }
1487
1488 return cnt;
1489 }
1490
1491 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1492 {
1493 struct hclge_priv_buf *priv;
1494 u32 rx_priv = 0;
1495 int i;
1496
1497 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1498 priv = &buf_alloc->priv_buf[i];
1499 if (priv->enable)
1500 rx_priv += priv->buf_size;
1501 }
1502 return rx_priv;
1503 }
1504
1505 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1506 {
1507 u32 i, total_tx_size = 0;
1508
1509 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1510 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
1511
1512 return total_tx_size;
1513 }
1514
1515 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1516 struct hclge_pkt_buf_alloc *buf_alloc,
1517 u32 rx_all)
1518 {
1519 u32 shared_buf_min, shared_buf_tc, shared_std;
1520 int tc_num, pfc_enable_num;
1521 u32 shared_buf;
1522 u32 rx_priv;
1523 int i;
1524
1525 tc_num = hclge_get_tc_num(hdev);
1526 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1527
1528 if (hnae3_dev_dcb_supported(hdev))
1529 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1530 else
1531 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1532
1533 shared_buf_tc = pfc_enable_num * hdev->mps +
1534 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1535 hdev->mps;
1536 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1537
1538 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
1539 if (rx_all <= rx_priv + shared_std)
1540 return false;
1541
1542 shared_buf = rx_all - rx_priv;
1543 buf_alloc->s_buf.buf_size = shared_buf;
1544 buf_alloc->s_buf.self.high = shared_buf;
1545 buf_alloc->s_buf.self.low = 2 * hdev->mps;
1546
1547 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1548 if ((hdev->hw_tc_map & BIT(i)) &&
1549 (hdev->tm_info.hw_pfc_map & BIT(i))) {
1550 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1551 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
1552 } else {
1553 buf_alloc->s_buf.tc_thrd[i].low = 0;
1554 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
1555 }
1556 }
1557
1558 return true;
1559 }
1560
1561 static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1562 struct hclge_pkt_buf_alloc *buf_alloc)
1563 {
1564 u32 i, total_size;
1565
1566 total_size = hdev->pkt_buf_size;
1567
1568 /* alloc tx buffer for all enabled tc */
1569 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1570 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1571
1572 if (total_size < HCLGE_DEFAULT_TX_BUF)
1573 return -ENOMEM;
1574
1575 if (hdev->hw_tc_map & BIT(i))
1576 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1577 else
1578 priv->tx_buf_size = 0;
1579
1580 total_size -= priv->tx_buf_size;
1581 }
1582
1583 return 0;
1584 }
1585
1586 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1587 * @hdev: pointer to struct hclge_dev
1588 * @buf_alloc: pointer to buffer calculation data
1589 * @return: 0: calculate sucessful, negative: fail
1590 */
1591 static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1592 struct hclge_pkt_buf_alloc *buf_alloc)
1593 {
1594 u32 rx_all = hdev->pkt_buf_size;
1595 int no_pfc_priv_num, pfc_priv_num;
1596 struct hclge_priv_buf *priv;
1597 int i;
1598
1599 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
1600
1601 /* When DCB is not supported, rx private
1602 * buffer is not allocated.
1603 */
1604 if (!hnae3_dev_dcb_supported(hdev)) {
1605 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1606 return -ENOMEM;
1607
1608 return 0;
1609 }
1610
1611 /* step 1, try to alloc private buffer for all enabled tc */
1612 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1613 priv = &buf_alloc->priv_buf[i];
1614 if (hdev->hw_tc_map & BIT(i)) {
1615 priv->enable = 1;
1616 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1617 priv->wl.low = hdev->mps;
1618 priv->wl.high = priv->wl.low + hdev->mps;
1619 priv->buf_size = priv->wl.high +
1620 HCLGE_DEFAULT_DV;
1621 } else {
1622 priv->wl.low = 0;
1623 priv->wl.high = 2 * hdev->mps;
1624 priv->buf_size = priv->wl.high;
1625 }
1626 } else {
1627 priv->enable = 0;
1628 priv->wl.low = 0;
1629 priv->wl.high = 0;
1630 priv->buf_size = 0;
1631 }
1632 }
1633
1634 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1635 return 0;
1636
1637 /* step 2, try to decrease the buffer size of
1638 * no pfc TC's private buffer
1639 */
1640 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1641 priv = &buf_alloc->priv_buf[i];
1642
1643 priv->enable = 0;
1644 priv->wl.low = 0;
1645 priv->wl.high = 0;
1646 priv->buf_size = 0;
1647
1648 if (!(hdev->hw_tc_map & BIT(i)))
1649 continue;
1650
1651 priv->enable = 1;
1652
1653 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1654 priv->wl.low = 128;
1655 priv->wl.high = priv->wl.low + hdev->mps;
1656 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1657 } else {
1658 priv->wl.low = 0;
1659 priv->wl.high = hdev->mps;
1660 priv->buf_size = priv->wl.high;
1661 }
1662 }
1663
1664 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1665 return 0;
1666
1667 /* step 3, try to reduce the number of pfc disabled TCs,
1668 * which have private buffer
1669 */
1670 /* get the total no pfc enable TC number, which have private buffer */
1671 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
1672
1673 /* let the last to be cleared first */
1674 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1675 priv = &buf_alloc->priv_buf[i];
1676
1677 if (hdev->hw_tc_map & BIT(i) &&
1678 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1679 /* Clear the no pfc TC private buffer */
1680 priv->wl.low = 0;
1681 priv->wl.high = 0;
1682 priv->buf_size = 0;
1683 priv->enable = 0;
1684 no_pfc_priv_num--;
1685 }
1686
1687 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1688 no_pfc_priv_num == 0)
1689 break;
1690 }
1691
1692 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1693 return 0;
1694
1695 /* step 4, try to reduce the number of pfc enabled TCs
1696 * which have private buffer.
1697 */
1698 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
1699
1700 /* let the last to be cleared first */
1701 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1702 priv = &buf_alloc->priv_buf[i];
1703
1704 if (hdev->hw_tc_map & BIT(i) &&
1705 hdev->tm_info.hw_pfc_map & BIT(i)) {
1706 /* Reduce the number of pfc TC with private buffer */
1707 priv->wl.low = 0;
1708 priv->enable = 0;
1709 priv->wl.high = 0;
1710 priv->buf_size = 0;
1711 pfc_priv_num--;
1712 }
1713
1714 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1715 pfc_priv_num == 0)
1716 break;
1717 }
1718 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1719 return 0;
1720
1721 return -ENOMEM;
1722 }
1723
1724 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1725 struct hclge_pkt_buf_alloc *buf_alloc)
1726 {
1727 struct hclge_rx_priv_buff_cmd *req;
1728 struct hclge_desc desc;
1729 int ret;
1730 int i;
1731
1732 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
1733 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
1734
1735 /* Alloc private buffer TCs */
1736 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1737 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1738
1739 req->buf_num[i] =
1740 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1741 req->buf_num[i] |=
1742 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
1743 }
1744
1745 req->shared_buf =
1746 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
1747 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1748
1749 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1750 if (ret) {
1751 dev_err(&hdev->pdev->dev,
1752 "rx private buffer alloc cmd failed %d\n", ret);
1753 return ret;
1754 }
1755
1756 return 0;
1757 }
1758
1759 #define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1760
1761 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1762 struct hclge_pkt_buf_alloc *buf_alloc)
1763 {
1764 struct hclge_rx_priv_wl_buf *req;
1765 struct hclge_priv_buf *priv;
1766 struct hclge_desc desc[2];
1767 int i, j;
1768 int ret;
1769
1770 for (i = 0; i < 2; i++) {
1771 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1772 false);
1773 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1774
1775 /* The first descriptor set the NEXT bit to 1 */
1776 if (i == 0)
1777 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1778 else
1779 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1780
1781 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1782 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1783
1784 priv = &buf_alloc->priv_buf[idx];
1785 req->tc_wl[j].high =
1786 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1787 req->tc_wl[j].high |=
1788 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
1789 HCLGE_RX_PRIV_EN_B);
1790 req->tc_wl[j].low =
1791 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1792 req->tc_wl[j].low |=
1793 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
1794 HCLGE_RX_PRIV_EN_B);
1795 }
1796 }
1797
1798 /* Send 2 descriptor at one time */
1799 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1800 if (ret) {
1801 dev_err(&hdev->pdev->dev,
1802 "rx private waterline config cmd failed %d\n",
1803 ret);
1804 return ret;
1805 }
1806 return 0;
1807 }
1808
1809 static int hclge_common_thrd_config(struct hclge_dev *hdev,
1810 struct hclge_pkt_buf_alloc *buf_alloc)
1811 {
1812 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
1813 struct hclge_rx_com_thrd *req;
1814 struct hclge_desc desc[2];
1815 struct hclge_tc_thrd *tc;
1816 int i, j;
1817 int ret;
1818
1819 for (i = 0; i < 2; i++) {
1820 hclge_cmd_setup_basic_desc(&desc[i],
1821 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1822 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1823
1824 /* The first descriptor set the NEXT bit to 1 */
1825 if (i == 0)
1826 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1827 else
1828 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1829
1830 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1831 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1832
1833 req->com_thrd[j].high =
1834 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1835 req->com_thrd[j].high |=
1836 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
1837 HCLGE_RX_PRIV_EN_B);
1838 req->com_thrd[j].low =
1839 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1840 req->com_thrd[j].low |=
1841 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
1842 HCLGE_RX_PRIV_EN_B);
1843 }
1844 }
1845
1846 /* Send 2 descriptors at one time */
1847 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1848 if (ret) {
1849 dev_err(&hdev->pdev->dev,
1850 "common threshold config cmd failed %d\n", ret);
1851 return ret;
1852 }
1853 return 0;
1854 }
1855
1856 static int hclge_common_wl_config(struct hclge_dev *hdev,
1857 struct hclge_pkt_buf_alloc *buf_alloc)
1858 {
1859 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
1860 struct hclge_rx_com_wl *req;
1861 struct hclge_desc desc;
1862 int ret;
1863
1864 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1865
1866 req = (struct hclge_rx_com_wl *)desc.data;
1867 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1868 req->com_wl.high |=
1869 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
1870 HCLGE_RX_PRIV_EN_B);
1871
1872 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1873 req->com_wl.low |=
1874 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
1875 HCLGE_RX_PRIV_EN_B);
1876
1877 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1878 if (ret) {
1879 dev_err(&hdev->pdev->dev,
1880 "common waterline config cmd failed %d\n", ret);
1881 return ret;
1882 }
1883
1884 return 0;
1885 }
1886
1887 int hclge_buffer_alloc(struct hclge_dev *hdev)
1888 {
1889 struct hclge_pkt_buf_alloc *pkt_buf;
1890 int ret;
1891
1892 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1893 if (!pkt_buf)
1894 return -ENOMEM;
1895
1896 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
1897 if (ret) {
1898 dev_err(&hdev->pdev->dev,
1899 "could not calc tx buffer size for all TCs %d\n", ret);
1900 goto out;
1901 }
1902
1903 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
1904 if (ret) {
1905 dev_err(&hdev->pdev->dev,
1906 "could not alloc tx buffers %d\n", ret);
1907 goto out;
1908 }
1909
1910 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
1911 if (ret) {
1912 dev_err(&hdev->pdev->dev,
1913 "could not calc rx priv buffer size for all TCs %d\n",
1914 ret);
1915 goto out;
1916 }
1917
1918 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
1919 if (ret) {
1920 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1921 ret);
1922 goto out;
1923 }
1924
1925 if (hnae3_dev_dcb_supported(hdev)) {
1926 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
1927 if (ret) {
1928 dev_err(&hdev->pdev->dev,
1929 "could not configure rx private waterline %d\n",
1930 ret);
1931 goto out;
1932 }
1933
1934 ret = hclge_common_thrd_config(hdev, pkt_buf);
1935 if (ret) {
1936 dev_err(&hdev->pdev->dev,
1937 "could not configure common threshold %d\n",
1938 ret);
1939 goto out;
1940 }
1941 }
1942
1943 ret = hclge_common_wl_config(hdev, pkt_buf);
1944 if (ret)
1945 dev_err(&hdev->pdev->dev,
1946 "could not configure common waterline %d\n", ret);
1947
1948 out:
1949 kfree(pkt_buf);
1950 return ret;
1951 }
1952
1953 static int hclge_init_roce_base_info(struct hclge_vport *vport)
1954 {
1955 struct hnae3_handle *roce = &vport->roce;
1956 struct hnae3_handle *nic = &vport->nic;
1957
1958 roce->rinfo.num_vectors = vport->back->num_roce_msi;
1959
1960 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1961 vport->back->num_msi_left == 0)
1962 return -EINVAL;
1963
1964 roce->rinfo.base_vector = vport->back->roce_base_vector;
1965
1966 roce->rinfo.netdev = nic->kinfo.netdev;
1967 roce->rinfo.roce_io_base = vport->back->hw.io_base;
1968
1969 roce->pdev = nic->pdev;
1970 roce->ae_algo = nic->ae_algo;
1971 roce->numa_node_mask = nic->numa_node_mask;
1972
1973 return 0;
1974 }
1975
1976 static int hclge_init_msi(struct hclge_dev *hdev)
1977 {
1978 struct pci_dev *pdev = hdev->pdev;
1979 int vectors;
1980 int i;
1981
1982 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1983 PCI_IRQ_MSI | PCI_IRQ_MSIX);
1984 if (vectors < 0) {
1985 dev_err(&pdev->dev,
1986 "failed(%d) to allocate MSI/MSI-X vectors\n",
1987 vectors);
1988 return vectors;
1989 }
1990 if (vectors < hdev->num_msi)
1991 dev_warn(&hdev->pdev->dev,
1992 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1993 hdev->num_msi, vectors);
1994
1995 hdev->num_msi = vectors;
1996 hdev->num_msi_left = vectors;
1997 hdev->base_msi_vector = pdev->irq;
1998 hdev->roce_base_vector = hdev->base_msi_vector +
1999 HCLGE_ROCE_VECTOR_OFFSET;
2000
2001 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2002 sizeof(u16), GFP_KERNEL);
2003 if (!hdev->vector_status) {
2004 pci_free_irq_vectors(pdev);
2005 return -ENOMEM;
2006 }
2007
2008 for (i = 0; i < hdev->num_msi; i++)
2009 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2010
2011 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2012 sizeof(int), GFP_KERNEL);
2013 if (!hdev->vector_irq) {
2014 pci_free_irq_vectors(pdev);
2015 return -ENOMEM;
2016 }
2017
2018 return 0;
2019 }
2020
2021 static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
2022 {
2023 struct hclge_mac *mac = &hdev->hw.mac;
2024
2025 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
2026 mac->duplex = (u8)duplex;
2027 else
2028 mac->duplex = HCLGE_MAC_FULL;
2029
2030 mac->speed = speed;
2031 }
2032
2033 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2034 {
2035 struct hclge_config_mac_speed_dup_cmd *req;
2036 struct hclge_desc desc;
2037 int ret;
2038
2039 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
2040
2041 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2042
2043 hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
2044
2045 switch (speed) {
2046 case HCLGE_MAC_SPEED_10M:
2047 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2048 HCLGE_CFG_SPEED_S, 6);
2049 break;
2050 case HCLGE_MAC_SPEED_100M:
2051 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2052 HCLGE_CFG_SPEED_S, 7);
2053 break;
2054 case HCLGE_MAC_SPEED_1G:
2055 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2056 HCLGE_CFG_SPEED_S, 0);
2057 break;
2058 case HCLGE_MAC_SPEED_10G:
2059 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2060 HCLGE_CFG_SPEED_S, 1);
2061 break;
2062 case HCLGE_MAC_SPEED_25G:
2063 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2064 HCLGE_CFG_SPEED_S, 2);
2065 break;
2066 case HCLGE_MAC_SPEED_40G:
2067 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2068 HCLGE_CFG_SPEED_S, 3);
2069 break;
2070 case HCLGE_MAC_SPEED_50G:
2071 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2072 HCLGE_CFG_SPEED_S, 4);
2073 break;
2074 case HCLGE_MAC_SPEED_100G:
2075 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2076 HCLGE_CFG_SPEED_S, 5);
2077 break;
2078 default:
2079 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
2080 return -EINVAL;
2081 }
2082
2083 hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2084 1);
2085
2086 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2087 if (ret) {
2088 dev_err(&hdev->pdev->dev,
2089 "mac speed/duplex config cmd failed %d.\n", ret);
2090 return ret;
2091 }
2092
2093 hclge_check_speed_dup(hdev, duplex, speed);
2094
2095 return 0;
2096 }
2097
2098 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2099 u8 duplex)
2100 {
2101 struct hclge_vport *vport = hclge_get_vport(handle);
2102 struct hclge_dev *hdev = vport->back;
2103
2104 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2105 }
2106
2107 static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2108 u8 *duplex)
2109 {
2110 struct hclge_query_an_speed_dup_cmd *req;
2111 struct hclge_desc desc;
2112 int speed_tmp;
2113 int ret;
2114
2115 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
2116
2117 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2118 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2119 if (ret) {
2120 dev_err(&hdev->pdev->dev,
2121 "mac speed/autoneg/duplex query cmd failed %d\n",
2122 ret);
2123 return ret;
2124 }
2125
2126 *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2127 speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2128 HCLGE_QUERY_SPEED_S);
2129
2130 ret = hclge_parse_speed(speed_tmp, speed);
2131 if (ret) {
2132 dev_err(&hdev->pdev->dev,
2133 "could not parse speed(=%d), %d\n", speed_tmp, ret);
2134 return -EIO;
2135 }
2136
2137 return 0;
2138 }
2139
2140 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2141 {
2142 struct hclge_config_auto_neg_cmd *req;
2143 struct hclge_desc desc;
2144 u32 flag = 0;
2145 int ret;
2146
2147 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2148
2149 req = (struct hclge_config_auto_neg_cmd *)desc.data;
2150 hnae_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2151 req->cfg_an_cmd_flag = cpu_to_le32(flag);
2152
2153 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2154 if (ret) {
2155 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2156 ret);
2157 return ret;
2158 }
2159
2160 return 0;
2161 }
2162
2163 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2164 {
2165 struct hclge_vport *vport = hclge_get_vport(handle);
2166 struct hclge_dev *hdev = vport->back;
2167
2168 return hclge_set_autoneg_en(hdev, enable);
2169 }
2170
2171 static int hclge_get_autoneg(struct hnae3_handle *handle)
2172 {
2173 struct hclge_vport *vport = hclge_get_vport(handle);
2174 struct hclge_dev *hdev = vport->back;
2175 struct phy_device *phydev = hdev->hw.mac.phydev;
2176
2177 if (phydev)
2178 return phydev->autoneg;
2179
2180 return hdev->hw.mac.autoneg;
2181 }
2182
2183 static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev,
2184 bool mask_vlan,
2185 u8 *mac_mask)
2186 {
2187 struct hclge_mac_vlan_mask_entry_cmd *req;
2188 struct hclge_desc desc;
2189 int status;
2190
2191 req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data;
2192 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false);
2193
2194 hnae_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B,
2195 mask_vlan ? 1 : 0);
2196 ether_addr_copy(req->mac_mask, mac_mask);
2197
2198 status = hclge_cmd_send(&hdev->hw, &desc, 1);
2199 if (status)
2200 dev_err(&hdev->pdev->dev,
2201 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2202 status);
2203
2204 return status;
2205 }
2206
2207 static int hclge_mac_init(struct hclge_dev *hdev)
2208 {
2209 struct hclge_mac *mac = &hdev->hw.mac;
2210 u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
2211 int ret;
2212
2213 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2214 if (ret) {
2215 dev_err(&hdev->pdev->dev,
2216 "Config mac speed dup fail ret=%d\n", ret);
2217 return ret;
2218 }
2219
2220 mac->link = 0;
2221
2222 /* Initialize the MTA table work mode */
2223 hdev->accept_mta_mc = true;
2224 hdev->enable_mta = true;
2225 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2226
2227 ret = hclge_set_mta_filter_mode(hdev,
2228 hdev->mta_mac_sel_type,
2229 hdev->enable_mta);
2230 if (ret) {
2231 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2232 ret);
2233 return ret;
2234 }
2235
2236 ret = hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc);
2237 if (ret) {
2238 dev_err(&hdev->pdev->dev,
2239 "set mta filter mode fail ret=%d\n", ret);
2240 return ret;
2241 }
2242
2243 ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask);
2244 if (ret)
2245 dev_err(&hdev->pdev->dev,
2246 "set default mac_vlan_mask fail ret=%d\n", ret);
2247
2248 return ret;
2249 }
2250
2251 static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2252 {
2253 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2254 schedule_work(&hdev->mbx_service_task);
2255 }
2256
2257 static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2258 {
2259 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2260 schedule_work(&hdev->rst_service_task);
2261 }
2262
2263 static void hclge_task_schedule(struct hclge_dev *hdev)
2264 {
2265 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2266 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2267 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2268 (void)schedule_work(&hdev->service_task);
2269 }
2270
2271 static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2272 {
2273 struct hclge_link_status_cmd *req;
2274 struct hclge_desc desc;
2275 int link_status;
2276 int ret;
2277
2278 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2279 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2280 if (ret) {
2281 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2282 ret);
2283 return ret;
2284 }
2285
2286 req = (struct hclge_link_status_cmd *)desc.data;
2287 link_status = req->status & HCLGE_LINK_STATUS;
2288
2289 return !!link_status;
2290 }
2291
2292 static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2293 {
2294 int mac_state;
2295 int link_stat;
2296
2297 mac_state = hclge_get_mac_link_status(hdev);
2298
2299 if (hdev->hw.mac.phydev) {
2300 if (!genphy_read_status(hdev->hw.mac.phydev))
2301 link_stat = mac_state &
2302 hdev->hw.mac.phydev->link;
2303 else
2304 link_stat = 0;
2305
2306 } else {
2307 link_stat = mac_state;
2308 }
2309
2310 return !!link_stat;
2311 }
2312
2313 static void hclge_update_link_status(struct hclge_dev *hdev)
2314 {
2315 struct hnae3_client *client = hdev->nic_client;
2316 struct hnae3_handle *handle;
2317 int state;
2318 int i;
2319
2320 if (!client)
2321 return;
2322 state = hclge_get_mac_phy_link(hdev);
2323 if (state != hdev->hw.mac.link) {
2324 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2325 handle = &hdev->vport[i].nic;
2326 client->ops->link_status_change(handle, state);
2327 }
2328 hdev->hw.mac.link = state;
2329 }
2330 }
2331
2332 static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2333 {
2334 struct hclge_mac mac = hdev->hw.mac;
2335 u8 duplex;
2336 int speed;
2337 int ret;
2338
2339 /* get the speed and duplex as autoneg'result from mac cmd when phy
2340 * doesn't exit.
2341 */
2342 if (mac.phydev || !mac.autoneg)
2343 return 0;
2344
2345 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2346 if (ret) {
2347 dev_err(&hdev->pdev->dev,
2348 "mac autoneg/speed/duplex query failed %d\n", ret);
2349 return ret;
2350 }
2351
2352 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2353 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2354 if (ret) {
2355 dev_err(&hdev->pdev->dev,
2356 "mac speed/duplex config failed %d\n", ret);
2357 return ret;
2358 }
2359 }
2360
2361 return 0;
2362 }
2363
2364 static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2365 {
2366 struct hclge_vport *vport = hclge_get_vport(handle);
2367 struct hclge_dev *hdev = vport->back;
2368
2369 return hclge_update_speed_duplex(hdev);
2370 }
2371
2372 static int hclge_get_status(struct hnae3_handle *handle)
2373 {
2374 struct hclge_vport *vport = hclge_get_vport(handle);
2375 struct hclge_dev *hdev = vport->back;
2376
2377 hclge_update_link_status(hdev);
2378
2379 return hdev->hw.mac.link;
2380 }
2381
2382 static void hclge_service_timer(struct timer_list *t)
2383 {
2384 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
2385
2386 mod_timer(&hdev->service_timer, jiffies + HZ);
2387 hclge_task_schedule(hdev);
2388 }
2389
2390 static void hclge_service_complete(struct hclge_dev *hdev)
2391 {
2392 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2393
2394 /* Flush memory before next watchdog */
2395 smp_mb__before_atomic();
2396 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2397 }
2398
2399 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2400 {
2401 u32 rst_src_reg;
2402 u32 cmdq_src_reg;
2403
2404 /* fetch the events from their corresponding regs */
2405 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);
2406 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2407
2408 /* Assumption: If by any chance reset and mailbox events are reported
2409 * together then we will only process reset event in this go and will
2410 * defer the processing of the mailbox events. Since, we would have not
2411 * cleared RX CMDQ event this time we would receive again another
2412 * interrupt from H/W just for the mailbox.
2413 */
2414
2415 /* check for vector0 reset event sources */
2416 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2417 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2418 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2419 return HCLGE_VECTOR0_EVENT_RST;
2420 }
2421
2422 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2423 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2424 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2425 return HCLGE_VECTOR0_EVENT_RST;
2426 }
2427
2428 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2429 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2430 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2431 return HCLGE_VECTOR0_EVENT_RST;
2432 }
2433
2434 /* check for vector0 mailbox(=CMDQ RX) event source */
2435 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2436 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2437 *clearval = cmdq_src_reg;
2438 return HCLGE_VECTOR0_EVENT_MBX;
2439 }
2440
2441 return HCLGE_VECTOR0_EVENT_OTHER;
2442 }
2443
2444 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2445 u32 regclr)
2446 {
2447 switch (event_type) {
2448 case HCLGE_VECTOR0_EVENT_RST:
2449 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
2450 break;
2451 case HCLGE_VECTOR0_EVENT_MBX:
2452 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2453 break;
2454 }
2455 }
2456
2457 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2458 {
2459 writel(enable ? 1 : 0, vector->addr);
2460 }
2461
2462 static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2463 {
2464 struct hclge_dev *hdev = data;
2465 u32 event_cause;
2466 u32 clearval;
2467
2468 hclge_enable_vector(&hdev->misc_vector, false);
2469 event_cause = hclge_check_event_cause(hdev, &clearval);
2470
2471 /* vector 0 interrupt is shared with reset and mailbox source events.*/
2472 switch (event_cause) {
2473 case HCLGE_VECTOR0_EVENT_RST:
2474 hclge_reset_task_schedule(hdev);
2475 break;
2476 case HCLGE_VECTOR0_EVENT_MBX:
2477 /* If we are here then,
2478 * 1. Either we are not handling any mbx task and we are not
2479 * scheduled as well
2480 * OR
2481 * 2. We could be handling a mbx task but nothing more is
2482 * scheduled.
2483 * In both cases, we should schedule mbx task as there are more
2484 * mbx messages reported by this interrupt.
2485 */
2486 hclge_mbx_task_schedule(hdev);
2487
2488 default:
2489 dev_dbg(&hdev->pdev->dev,
2490 "received unknown or unhandled event of vector0\n");
2491 break;
2492 }
2493
2494 /* we should clear the source of interrupt */
2495 hclge_clear_event_cause(hdev, event_cause, clearval);
2496 hclge_enable_vector(&hdev->misc_vector, true);
2497
2498 return IRQ_HANDLED;
2499 }
2500
2501 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2502 {
2503 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2504 hdev->num_msi_left += 1;
2505 hdev->num_msi_used -= 1;
2506 }
2507
2508 static void hclge_get_misc_vector(struct hclge_dev *hdev)
2509 {
2510 struct hclge_misc_vector *vector = &hdev->misc_vector;
2511
2512 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2513
2514 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2515 hdev->vector_status[0] = 0;
2516
2517 hdev->num_msi_left -= 1;
2518 hdev->num_msi_used += 1;
2519 }
2520
2521 static int hclge_misc_irq_init(struct hclge_dev *hdev)
2522 {
2523 int ret;
2524
2525 hclge_get_misc_vector(hdev);
2526
2527 /* this would be explicitly freed in the end */
2528 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2529 0, "hclge_misc", hdev);
2530 if (ret) {
2531 hclge_free_vector(hdev, 0);
2532 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2533 hdev->misc_vector.vector_irq);
2534 }
2535
2536 return ret;
2537 }
2538
2539 static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2540 {
2541 free_irq(hdev->misc_vector.vector_irq, hdev);
2542 hclge_free_vector(hdev, 0);
2543 }
2544
2545 static int hclge_notify_client(struct hclge_dev *hdev,
2546 enum hnae3_reset_notify_type type)
2547 {
2548 struct hnae3_client *client = hdev->nic_client;
2549 u16 i;
2550
2551 if (!client->ops->reset_notify)
2552 return -EOPNOTSUPP;
2553
2554 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2555 struct hnae3_handle *handle = &hdev->vport[i].nic;
2556 int ret;
2557
2558 ret = client->ops->reset_notify(handle, type);
2559 if (ret)
2560 return ret;
2561 }
2562
2563 return 0;
2564 }
2565
2566 static int hclge_reset_wait(struct hclge_dev *hdev)
2567 {
2568 #define HCLGE_RESET_WATI_MS 100
2569 #define HCLGE_RESET_WAIT_CNT 5
2570 u32 val, reg, reg_bit;
2571 u32 cnt = 0;
2572
2573 switch (hdev->reset_type) {
2574 case HNAE3_GLOBAL_RESET:
2575 reg = HCLGE_GLOBAL_RESET_REG;
2576 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2577 break;
2578 case HNAE3_CORE_RESET:
2579 reg = HCLGE_GLOBAL_RESET_REG;
2580 reg_bit = HCLGE_CORE_RESET_BIT;
2581 break;
2582 case HNAE3_FUNC_RESET:
2583 reg = HCLGE_FUN_RST_ING;
2584 reg_bit = HCLGE_FUN_RST_ING_B;
2585 break;
2586 default:
2587 dev_err(&hdev->pdev->dev,
2588 "Wait for unsupported reset type: %d\n",
2589 hdev->reset_type);
2590 return -EINVAL;
2591 }
2592
2593 val = hclge_read_dev(&hdev->hw, reg);
2594 while (hnae_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
2595 msleep(HCLGE_RESET_WATI_MS);
2596 val = hclge_read_dev(&hdev->hw, reg);
2597 cnt++;
2598 }
2599
2600 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2601 dev_warn(&hdev->pdev->dev,
2602 "Wait for reset timeout: %d\n", hdev->reset_type);
2603 return -EBUSY;
2604 }
2605
2606 return 0;
2607 }
2608
2609 static int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
2610 {
2611 struct hclge_desc desc;
2612 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2613 int ret;
2614
2615 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2616 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_MAC_B, 0);
2617 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2618 req->fun_reset_vfid = func_id;
2619
2620 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2621 if (ret)
2622 dev_err(&hdev->pdev->dev,
2623 "send function reset cmd fail, status =%d\n", ret);
2624
2625 return ret;
2626 }
2627
2628 static void hclge_do_reset(struct hclge_dev *hdev)
2629 {
2630 struct pci_dev *pdev = hdev->pdev;
2631 u32 val;
2632
2633 switch (hdev->reset_type) {
2634 case HNAE3_GLOBAL_RESET:
2635 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2636 hnae_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2637 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2638 dev_info(&pdev->dev, "Global Reset requested\n");
2639 break;
2640 case HNAE3_CORE_RESET:
2641 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2642 hnae_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2643 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2644 dev_info(&pdev->dev, "Core Reset requested\n");
2645 break;
2646 case HNAE3_FUNC_RESET:
2647 dev_info(&pdev->dev, "PF Reset requested\n");
2648 hclge_func_reset_cmd(hdev, 0);
2649 /* schedule again to check later */
2650 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2651 hclge_reset_task_schedule(hdev);
2652 break;
2653 default:
2654 dev_warn(&pdev->dev,
2655 "Unsupported reset type: %d\n", hdev->reset_type);
2656 break;
2657 }
2658 }
2659
2660 static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2661 unsigned long *addr)
2662 {
2663 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2664
2665 /* return the highest priority reset level amongst all */
2666 if (test_bit(HNAE3_GLOBAL_RESET, addr))
2667 rst_level = HNAE3_GLOBAL_RESET;
2668 else if (test_bit(HNAE3_CORE_RESET, addr))
2669 rst_level = HNAE3_CORE_RESET;
2670 else if (test_bit(HNAE3_IMP_RESET, addr))
2671 rst_level = HNAE3_IMP_RESET;
2672 else if (test_bit(HNAE3_FUNC_RESET, addr))
2673 rst_level = HNAE3_FUNC_RESET;
2674
2675 /* now, clear all other resets */
2676 clear_bit(HNAE3_GLOBAL_RESET, addr);
2677 clear_bit(HNAE3_CORE_RESET, addr);
2678 clear_bit(HNAE3_IMP_RESET, addr);
2679 clear_bit(HNAE3_FUNC_RESET, addr);
2680
2681 return rst_level;
2682 }
2683
2684 static void hclge_reset(struct hclge_dev *hdev)
2685 {
2686 /* perform reset of the stack & ae device for a client */
2687
2688 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2689
2690 if (!hclge_reset_wait(hdev)) {
2691 rtnl_lock();
2692 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2693 hclge_reset_ae_dev(hdev->ae_dev);
2694 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2695 rtnl_unlock();
2696 } else {
2697 /* schedule again to check pending resets later */
2698 set_bit(hdev->reset_type, &hdev->reset_pending);
2699 hclge_reset_task_schedule(hdev);
2700 }
2701
2702 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2703 }
2704
2705 static void hclge_reset_event(struct hnae3_handle *handle,
2706 enum hnae3_reset_type reset)
2707 {
2708 struct hclge_vport *vport = hclge_get_vport(handle);
2709 struct hclge_dev *hdev = vport->back;
2710
2711 dev_info(&hdev->pdev->dev,
2712 "Receive reset event , reset_type is %d", reset);
2713
2714 switch (reset) {
2715 case HNAE3_FUNC_RESET:
2716 case HNAE3_CORE_RESET:
2717 case HNAE3_GLOBAL_RESET:
2718 /* request reset & schedule reset task */
2719 set_bit(reset, &hdev->reset_request);
2720 hclge_reset_task_schedule(hdev);
2721 break;
2722 default:
2723 dev_warn(&hdev->pdev->dev, "Unsupported reset event:%d", reset);
2724 break;
2725 }
2726 }
2727
2728 static void hclge_reset_subtask(struct hclge_dev *hdev)
2729 {
2730 /* check if there is any ongoing reset in the hardware. This status can
2731 * be checked from reset_pending. If there is then, we need to wait for
2732 * hardware to complete reset.
2733 * a. If we are able to figure out in reasonable time that hardware
2734 * has fully resetted then, we can proceed with driver, client
2735 * reset.
2736 * b. else, we can come back later to check this status so re-sched
2737 * now.
2738 */
2739 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2740 if (hdev->reset_type != HNAE3_NONE_RESET)
2741 hclge_reset(hdev);
2742
2743 /* check if we got any *new* reset requests to be honored */
2744 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2745 if (hdev->reset_type != HNAE3_NONE_RESET)
2746 hclge_do_reset(hdev);
2747
2748 hdev->reset_type = HNAE3_NONE_RESET;
2749 }
2750
2751 static void hclge_reset_service_task(struct work_struct *work)
2752 {
2753 struct hclge_dev *hdev =
2754 container_of(work, struct hclge_dev, rst_service_task);
2755
2756 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2757 return;
2758
2759 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2760
2761 hclge_reset_subtask(hdev);
2762
2763 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
2764 }
2765
2766 static void hclge_mailbox_service_task(struct work_struct *work)
2767 {
2768 struct hclge_dev *hdev =
2769 container_of(work, struct hclge_dev, mbx_service_task);
2770
2771 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2772 return;
2773
2774 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2775
2776 hclge_mbx_handler(hdev);
2777
2778 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2779 }
2780
2781 static void hclge_service_task(struct work_struct *work)
2782 {
2783 struct hclge_dev *hdev =
2784 container_of(work, struct hclge_dev, service_task);
2785
2786 hclge_update_speed_duplex(hdev);
2787 hclge_update_link_status(hdev);
2788 hclge_update_stats_for_all(hdev);
2789 hclge_service_complete(hdev);
2790 }
2791
2792 static void hclge_disable_sriov(struct hclge_dev *hdev)
2793 {
2794 /* If our VFs are assigned we cannot shut down SR-IOV
2795 * without causing issues, so just leave the hardware
2796 * available but disabled
2797 */
2798 if (pci_vfs_assigned(hdev->pdev)) {
2799 dev_warn(&hdev->pdev->dev,
2800 "disabling driver while VFs are assigned\n");
2801 return;
2802 }
2803
2804 pci_disable_sriov(hdev->pdev);
2805 }
2806
2807 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2808 {
2809 /* VF handle has no client */
2810 if (!handle->client)
2811 return container_of(handle, struct hclge_vport, nic);
2812 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2813 return container_of(handle, struct hclge_vport, roce);
2814 else
2815 return container_of(handle, struct hclge_vport, nic);
2816 }
2817
2818 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2819 struct hnae3_vector_info *vector_info)
2820 {
2821 struct hclge_vport *vport = hclge_get_vport(handle);
2822 struct hnae3_vector_info *vector = vector_info;
2823 struct hclge_dev *hdev = vport->back;
2824 int alloc = 0;
2825 int i, j;
2826
2827 vector_num = min(hdev->num_msi_left, vector_num);
2828
2829 for (j = 0; j < vector_num; j++) {
2830 for (i = 1; i < hdev->num_msi; i++) {
2831 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2832 vector->vector = pci_irq_vector(hdev->pdev, i);
2833 vector->io_addr = hdev->hw.io_base +
2834 HCLGE_VECTOR_REG_BASE +
2835 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2836 vport->vport_id *
2837 HCLGE_VECTOR_VF_OFFSET;
2838 hdev->vector_status[i] = vport->vport_id;
2839 hdev->vector_irq[i] = vector->vector;
2840
2841 vector++;
2842 alloc++;
2843
2844 break;
2845 }
2846 }
2847 }
2848 hdev->num_msi_left -= alloc;
2849 hdev->num_msi_used += alloc;
2850
2851 return alloc;
2852 }
2853
2854 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2855 {
2856 int i;
2857
2858 for (i = 0; i < hdev->num_msi; i++)
2859 if (vector == hdev->vector_irq[i])
2860 return i;
2861
2862 return -EINVAL;
2863 }
2864
2865 static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2866 {
2867 return HCLGE_RSS_KEY_SIZE;
2868 }
2869
2870 static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2871 {
2872 return HCLGE_RSS_IND_TBL_SIZE;
2873 }
2874
2875 static int hclge_get_rss_algo(struct hclge_dev *hdev)
2876 {
2877 struct hclge_rss_config_cmd *req;
2878 struct hclge_desc desc;
2879 int rss_hash_algo;
2880 int ret;
2881
2882 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, true);
2883
2884 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2885 if (ret) {
2886 dev_err(&hdev->pdev->dev,
2887 "Get link status error, status =%d\n", ret);
2888 return ret;
2889 }
2890
2891 req = (struct hclge_rss_config_cmd *)desc.data;
2892 rss_hash_algo = (req->hash_config & HCLGE_RSS_HASH_ALGO_MASK);
2893
2894 if (rss_hash_algo == HCLGE_RSS_HASH_ALGO_TOEPLITZ)
2895 return ETH_RSS_HASH_TOP;
2896
2897 return -EINVAL;
2898 }
2899
2900 static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2901 const u8 hfunc, const u8 *key)
2902 {
2903 struct hclge_rss_config_cmd *req;
2904 struct hclge_desc desc;
2905 int key_offset;
2906 int key_size;
2907 int ret;
2908
2909 req = (struct hclge_rss_config_cmd *)desc.data;
2910
2911 for (key_offset = 0; key_offset < 3; key_offset++) {
2912 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2913 false);
2914
2915 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
2916 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
2917
2918 if (key_offset == 2)
2919 key_size =
2920 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
2921 else
2922 key_size = HCLGE_RSS_HASH_KEY_NUM;
2923
2924 memcpy(req->hash_key,
2925 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
2926
2927 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2928 if (ret) {
2929 dev_err(&hdev->pdev->dev,
2930 "Configure RSS config fail, status = %d\n",
2931 ret);
2932 return ret;
2933 }
2934 }
2935 return 0;
2936 }
2937
2938 static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u32 *indir)
2939 {
2940 struct hclge_rss_indirection_table_cmd *req;
2941 struct hclge_desc desc;
2942 int i, j;
2943 int ret;
2944
2945 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
2946
2947 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
2948 hclge_cmd_setup_basic_desc
2949 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
2950
2951 req->start_table_index =
2952 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
2953 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
2954
2955 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
2956 req->rss_result[j] =
2957 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
2958
2959 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2960 if (ret) {
2961 dev_err(&hdev->pdev->dev,
2962 "Configure rss indir table fail,status = %d\n",
2963 ret);
2964 return ret;
2965 }
2966 }
2967 return 0;
2968 }
2969
2970 static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
2971 u16 *tc_size, u16 *tc_offset)
2972 {
2973 struct hclge_rss_tc_mode_cmd *req;
2974 struct hclge_desc desc;
2975 int ret;
2976 int i;
2977
2978 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
2979 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
2980
2981 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2982 u16 mode = 0;
2983
2984 hnae_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
2985 hnae_set_field(mode, HCLGE_RSS_TC_SIZE_M,
2986 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
2987 hnae_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
2988 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
2989
2990 req->rss_tc_mode[i] = cpu_to_le16(mode);
2991 }
2992
2993 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2994 if (ret) {
2995 dev_err(&hdev->pdev->dev,
2996 "Configure rss tc mode fail, status = %d\n", ret);
2997 return ret;
2998 }
2999
3000 return 0;
3001 }
3002
3003 static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3004 {
3005 struct hclge_rss_input_tuple_cmd *req;
3006 struct hclge_desc desc;
3007 int ret;
3008
3009 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3010
3011 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3012 req->ipv4_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3013 req->ipv4_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3014 req->ipv4_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
3015 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3016 req->ipv6_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3017 req->ipv6_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3018 req->ipv6_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
3019 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3020 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3021 if (ret) {
3022 dev_err(&hdev->pdev->dev,
3023 "Configure rss input fail, status = %d\n", ret);
3024 return ret;
3025 }
3026
3027 return 0;
3028 }
3029
3030 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3031 u8 *key, u8 *hfunc)
3032 {
3033 struct hclge_vport *vport = hclge_get_vport(handle);
3034 struct hclge_dev *hdev = vport->back;
3035 int i;
3036
3037 /* Get hash algorithm */
3038 if (hfunc)
3039 *hfunc = hclge_get_rss_algo(hdev);
3040
3041 /* Get the RSS Key required by the user */
3042 if (key)
3043 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3044
3045 /* Get indirect table */
3046 if (indir)
3047 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3048 indir[i] = vport->rss_indirection_tbl[i];
3049
3050 return 0;
3051 }
3052
3053 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3054 const u8 *key, const u8 hfunc)
3055 {
3056 struct hclge_vport *vport = hclge_get_vport(handle);
3057 struct hclge_dev *hdev = vport->back;
3058 u8 hash_algo;
3059 int ret, i;
3060
3061 /* Set the RSS Hash Key if specififed by the user */
3062 if (key) {
3063 /* Update the shadow RSS key with user specified qids */
3064 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3065
3066 if (hfunc == ETH_RSS_HASH_TOP ||
3067 hfunc == ETH_RSS_HASH_NO_CHANGE)
3068 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3069 else
3070 return -EINVAL;
3071 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3072 if (ret)
3073 return ret;
3074 }
3075
3076 /* Update the shadow RSS table with user specified qids */
3077 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3078 vport->rss_indirection_tbl[i] = indir[i];
3079
3080 /* Update the hardware */
3081 ret = hclge_set_rss_indir_table(hdev, indir);
3082 return ret;
3083 }
3084
3085 static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3086 {
3087 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3088
3089 if (nfc->data & RXH_L4_B_2_3)
3090 hash_sets |= HCLGE_D_PORT_BIT;
3091 else
3092 hash_sets &= ~HCLGE_D_PORT_BIT;
3093
3094 if (nfc->data & RXH_IP_SRC)
3095 hash_sets |= HCLGE_S_IP_BIT;
3096 else
3097 hash_sets &= ~HCLGE_S_IP_BIT;
3098
3099 if (nfc->data & RXH_IP_DST)
3100 hash_sets |= HCLGE_D_IP_BIT;
3101 else
3102 hash_sets &= ~HCLGE_D_IP_BIT;
3103
3104 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3105 hash_sets |= HCLGE_V_TAG_BIT;
3106
3107 return hash_sets;
3108 }
3109
3110 static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3111 struct ethtool_rxnfc *nfc)
3112 {
3113 struct hclge_vport *vport = hclge_get_vport(handle);
3114 struct hclge_dev *hdev = vport->back;
3115 struct hclge_rss_input_tuple_cmd *req;
3116 struct hclge_desc desc;
3117 u8 tuple_sets;
3118 int ret;
3119
3120 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3121 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3122 return -EINVAL;
3123
3124 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3125 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3126 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3127 if (ret) {
3128 dev_err(&hdev->pdev->dev,
3129 "Read rss tuple fail, status = %d\n", ret);
3130 return ret;
3131 }
3132
3133 hclge_cmd_reuse_desc(&desc, false);
3134
3135 tuple_sets = hclge_get_rss_hash_bits(nfc);
3136 switch (nfc->flow_type) {
3137 case TCP_V4_FLOW:
3138 req->ipv4_tcp_en = tuple_sets;
3139 break;
3140 case TCP_V6_FLOW:
3141 req->ipv6_tcp_en = tuple_sets;
3142 break;
3143 case UDP_V4_FLOW:
3144 req->ipv4_udp_en = tuple_sets;
3145 break;
3146 case UDP_V6_FLOW:
3147 req->ipv6_udp_en = tuple_sets;
3148 break;
3149 case SCTP_V4_FLOW:
3150 req->ipv4_sctp_en = tuple_sets;
3151 break;
3152 case SCTP_V6_FLOW:
3153 if ((nfc->data & RXH_L4_B_0_1) ||
3154 (nfc->data & RXH_L4_B_2_3))
3155 return -EINVAL;
3156
3157 req->ipv6_sctp_en = tuple_sets;
3158 break;
3159 case IPV4_FLOW:
3160 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3161 break;
3162 case IPV6_FLOW:
3163 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3164 break;
3165 default:
3166 return -EINVAL;
3167 }
3168
3169 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3170 if (ret)
3171 dev_err(&hdev->pdev->dev,
3172 "Set rss tuple fail, status = %d\n", ret);
3173
3174 return ret;
3175 }
3176
3177 static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3178 struct ethtool_rxnfc *nfc)
3179 {
3180 struct hclge_vport *vport = hclge_get_vport(handle);
3181 struct hclge_dev *hdev = vport->back;
3182 struct hclge_rss_input_tuple_cmd *req;
3183 struct hclge_desc desc;
3184 u8 tuple_sets;
3185 int ret;
3186
3187 nfc->data = 0;
3188
3189 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3190 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3191 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3192 if (ret) {
3193 dev_err(&hdev->pdev->dev,
3194 "Read rss tuple fail, status = %d\n", ret);
3195 return ret;
3196 }
3197
3198 switch (nfc->flow_type) {
3199 case TCP_V4_FLOW:
3200 tuple_sets = req->ipv4_tcp_en;
3201 break;
3202 case UDP_V4_FLOW:
3203 tuple_sets = req->ipv4_udp_en;
3204 break;
3205 case TCP_V6_FLOW:
3206 tuple_sets = req->ipv6_tcp_en;
3207 break;
3208 case UDP_V6_FLOW:
3209 tuple_sets = req->ipv6_udp_en;
3210 break;
3211 case SCTP_V4_FLOW:
3212 tuple_sets = req->ipv4_sctp_en;
3213 break;
3214 case SCTP_V6_FLOW:
3215 tuple_sets = req->ipv6_sctp_en;
3216 break;
3217 case IPV4_FLOW:
3218 case IPV6_FLOW:
3219 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3220 break;
3221 default:
3222 return -EINVAL;
3223 }
3224
3225 if (!tuple_sets)
3226 return 0;
3227
3228 if (tuple_sets & HCLGE_D_PORT_BIT)
3229 nfc->data |= RXH_L4_B_2_3;
3230 if (tuple_sets & HCLGE_S_PORT_BIT)
3231 nfc->data |= RXH_L4_B_0_1;
3232 if (tuple_sets & HCLGE_D_IP_BIT)
3233 nfc->data |= RXH_IP_DST;
3234 if (tuple_sets & HCLGE_S_IP_BIT)
3235 nfc->data |= RXH_IP_SRC;
3236
3237 return 0;
3238 }
3239
3240 static int hclge_get_tc_size(struct hnae3_handle *handle)
3241 {
3242 struct hclge_vport *vport = hclge_get_vport(handle);
3243 struct hclge_dev *hdev = vport->back;
3244
3245 return hdev->rss_size_max;
3246 }
3247
3248 int hclge_rss_init_hw(struct hclge_dev *hdev)
3249 {
3250 const u8 hfunc = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3251 struct hclge_vport *vport = hdev->vport;
3252 u16 tc_offset[HCLGE_MAX_TC_NUM];
3253 u8 rss_key[HCLGE_RSS_KEY_SIZE];
3254 u16 tc_valid[HCLGE_MAX_TC_NUM];
3255 u16 tc_size[HCLGE_MAX_TC_NUM];
3256 u32 *rss_indir = NULL;
3257 u16 rss_size = 0, roundup_size;
3258 const u8 *key;
3259 int i, ret, j;
3260
3261 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
3262 if (!rss_indir)
3263 return -ENOMEM;
3264
3265 /* Get default RSS key */
3266 netdev_rss_key_fill(rss_key, HCLGE_RSS_KEY_SIZE);
3267
3268 /* Initialize RSS indirect table for each vport */
3269 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3270 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) {
3271 vport[j].rss_indirection_tbl[i] =
3272 i % vport[j].alloc_rss_size;
3273
3274 /* vport 0 is for PF */
3275 if (j != 0)
3276 continue;
3277
3278 rss_size = vport[j].alloc_rss_size;
3279 rss_indir[i] = vport[j].rss_indirection_tbl[i];
3280 }
3281 }
3282 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3283 if (ret)
3284 goto err;
3285
3286 key = rss_key;
3287 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3288 if (ret)
3289 goto err;
3290
3291 ret = hclge_set_rss_input_tuple(hdev);
3292 if (ret)
3293 goto err;
3294
3295 /* Each TC have the same queue size, and tc_size set to hardware is
3296 * the log2 of roundup power of two of rss_size, the acutal queue
3297 * size is limited by indirection table.
3298 */
3299 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3300 dev_err(&hdev->pdev->dev,
3301 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3302 rss_size);
3303 ret = -EINVAL;
3304 goto err;
3305 }
3306
3307 roundup_size = roundup_pow_of_two(rss_size);
3308 roundup_size = ilog2(roundup_size);
3309
3310 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3311 tc_valid[i] = 0;
3312
3313 if (!(hdev->hw_tc_map & BIT(i)))
3314 continue;
3315
3316 tc_valid[i] = 1;
3317 tc_size[i] = roundup_size;
3318 tc_offset[i] = rss_size * i;
3319 }
3320
3321 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3322
3323 err:
3324 kfree(rss_indir);
3325
3326 return ret;
3327 }
3328
3329 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3330 int vector_id, bool en,
3331 struct hnae3_ring_chain_node *ring_chain)
3332 {
3333 struct hclge_dev *hdev = vport->back;
3334 struct hnae3_ring_chain_node *node;
3335 struct hclge_desc desc;
3336 struct hclge_ctrl_vector_chain_cmd *req
3337 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3338 enum hclge_cmd_status status;
3339 enum hclge_opcode_type op;
3340 u16 tqp_type_and_id;
3341 int i;
3342
3343 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3344 hclge_cmd_setup_basic_desc(&desc, op, false);
3345 req->int_vector_id = vector_id;
3346
3347 i = 0;
3348 for (node = ring_chain; node; node = node->next) {
3349 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
3350 hnae_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3351 HCLGE_INT_TYPE_S,
3352 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
3353 hnae_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3354 HCLGE_TQP_ID_S, node->tqp_index);
3355 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
3356 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3357 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
3358 req->vfid = vport->vport_id;
3359
3360 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3361 if (status) {
3362 dev_err(&hdev->pdev->dev,
3363 "Map TQP fail, status is %d.\n",
3364 status);
3365 return -EIO;
3366 }
3367 i = 0;
3368
3369 hclge_cmd_setup_basic_desc(&desc,
3370 op,
3371 false);
3372 req->int_vector_id = vector_id;
3373 }
3374 }
3375
3376 if (i > 0) {
3377 req->int_cause_num = i;
3378 req->vfid = vport->vport_id;
3379 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3380 if (status) {
3381 dev_err(&hdev->pdev->dev,
3382 "Map TQP fail, status is %d.\n", status);
3383 return -EIO;
3384 }
3385 }
3386
3387 return 0;
3388 }
3389
3390 static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3391 int vector,
3392 struct hnae3_ring_chain_node *ring_chain)
3393 {
3394 struct hclge_vport *vport = hclge_get_vport(handle);
3395 struct hclge_dev *hdev = vport->back;
3396 int vector_id;
3397
3398 vector_id = hclge_get_vector_index(hdev, vector);
3399 if (vector_id < 0) {
3400 dev_err(&hdev->pdev->dev,
3401 "Get vector index fail. vector_id =%d\n", vector_id);
3402 return vector_id;
3403 }
3404
3405 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
3406 }
3407
3408 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3409 int vector,
3410 struct hnae3_ring_chain_node *ring_chain)
3411 {
3412 struct hclge_vport *vport = hclge_get_vport(handle);
3413 struct hclge_dev *hdev = vport->back;
3414 int vector_id, ret;
3415
3416 vector_id = hclge_get_vector_index(hdev, vector);
3417 if (vector_id < 0) {
3418 dev_err(&handle->pdev->dev,
3419 "Get vector index fail. ret =%d\n", vector_id);
3420 return vector_id;
3421 }
3422
3423 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
3424 if (ret) {
3425 dev_err(&handle->pdev->dev,
3426 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3427 vector_id,
3428 ret);
3429 return ret;
3430 }
3431
3432 /* Free this MSIX or MSI vector */
3433 hclge_free_vector(hdev, vector_id);
3434
3435 return 0;
3436 }
3437
3438 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3439 struct hclge_promisc_param *param)
3440 {
3441 struct hclge_promisc_cfg_cmd *req;
3442 struct hclge_desc desc;
3443 int ret;
3444
3445 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3446
3447 req = (struct hclge_promisc_cfg_cmd *)desc.data;
3448 req->vf_id = param->vf_id;
3449 req->flag = (param->enable << HCLGE_PROMISC_EN_B);
3450
3451 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3452 if (ret) {
3453 dev_err(&hdev->pdev->dev,
3454 "Set promisc mode fail, status is %d.\n", ret);
3455 return ret;
3456 }
3457 return 0;
3458 }
3459
3460 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3461 bool en_mc, bool en_bc, int vport_id)
3462 {
3463 if (!param)
3464 return;
3465
3466 memset(param, 0, sizeof(struct hclge_promisc_param));
3467 if (en_uc)
3468 param->enable = HCLGE_PROMISC_EN_UC;
3469 if (en_mc)
3470 param->enable |= HCLGE_PROMISC_EN_MC;
3471 if (en_bc)
3472 param->enable |= HCLGE_PROMISC_EN_BC;
3473 param->vf_id = vport_id;
3474 }
3475
3476 static void hclge_set_promisc_mode(struct hnae3_handle *handle, u32 en)
3477 {
3478 struct hclge_vport *vport = hclge_get_vport(handle);
3479 struct hclge_dev *hdev = vport->back;
3480 struct hclge_promisc_param param;
3481
3482 hclge_promisc_param_init(&param, en, en, true, vport->vport_id);
3483 hclge_cmd_set_promisc_mode(hdev, &param);
3484 }
3485
3486 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3487 {
3488 struct hclge_desc desc;
3489 struct hclge_config_mac_mode_cmd *req =
3490 (struct hclge_config_mac_mode_cmd *)desc.data;
3491 u32 loop_en = 0;
3492 int ret;
3493
3494 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
3495 hnae_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3496 hnae_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3497 hnae_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3498 hnae_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3499 hnae_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3500 hnae_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3501 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3502 hnae_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3503 hnae_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3504 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3505 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3506 hnae_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3507 hnae_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3508 hnae_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
3509 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3510
3511 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3512 if (ret)
3513 dev_err(&hdev->pdev->dev,
3514 "mac enable fail, ret =%d.\n", ret);
3515 }
3516
3517 static int hclge_set_loopback(struct hnae3_handle *handle,
3518 enum hnae3_loop loop_mode, bool en)
3519 {
3520 struct hclge_vport *vport = hclge_get_vport(handle);
3521 struct hclge_config_mac_mode_cmd *req;
3522 struct hclge_dev *hdev = vport->back;
3523 struct hclge_desc desc;
3524 u32 loop_en;
3525 int ret;
3526
3527 switch (loop_mode) {
3528 case HNAE3_MAC_INTER_LOOP_MAC:
3529 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3530 /* 1 Read out the MAC mode config at first */
3531 hclge_cmd_setup_basic_desc(&desc,
3532 HCLGE_OPC_CONFIG_MAC_MODE,
3533 true);
3534 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3535 if (ret) {
3536 dev_err(&hdev->pdev->dev,
3537 "mac loopback get fail, ret =%d.\n",
3538 ret);
3539 return ret;
3540 }
3541
3542 /* 2 Then setup the loopback flag */
3543 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
3544 if (en)
3545 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 1);
3546 else
3547 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3548
3549 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3550
3551 /* 3 Config mac work mode with loopback flag
3552 * and its original configure parameters
3553 */
3554 hclge_cmd_reuse_desc(&desc, false);
3555 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3556 if (ret)
3557 dev_err(&hdev->pdev->dev,
3558 "mac loopback set fail, ret =%d.\n", ret);
3559 break;
3560 default:
3561 ret = -ENOTSUPP;
3562 dev_err(&hdev->pdev->dev,
3563 "loop_mode %d is not supported\n", loop_mode);
3564 break;
3565 }
3566
3567 return ret;
3568 }
3569
3570 static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3571 int stream_id, bool enable)
3572 {
3573 struct hclge_desc desc;
3574 struct hclge_cfg_com_tqp_queue_cmd *req =
3575 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
3576 int ret;
3577
3578 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3579 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3580 req->stream_id = cpu_to_le16(stream_id);
3581 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3582
3583 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3584 if (ret)
3585 dev_err(&hdev->pdev->dev,
3586 "Tqp enable fail, status =%d.\n", ret);
3587 return ret;
3588 }
3589
3590 static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3591 {
3592 struct hclge_vport *vport = hclge_get_vport(handle);
3593 struct hnae3_queue *queue;
3594 struct hclge_tqp *tqp;
3595 int i;
3596
3597 for (i = 0; i < vport->alloc_tqps; i++) {
3598 queue = handle->kinfo.tqp[i];
3599 tqp = container_of(queue, struct hclge_tqp, q);
3600 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3601 }
3602 }
3603
3604 static int hclge_ae_start(struct hnae3_handle *handle)
3605 {
3606 struct hclge_vport *vport = hclge_get_vport(handle);
3607 struct hclge_dev *hdev = vport->back;
3608 int i, queue_id, ret;
3609
3610 for (i = 0; i < vport->alloc_tqps; i++) {
3611 /* todo clear interrupt */
3612 /* ring enable */
3613 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3614 if (queue_id < 0) {
3615 dev_warn(&hdev->pdev->dev,
3616 "Get invalid queue id, ignore it\n");
3617 continue;
3618 }
3619
3620 hclge_tqp_enable(hdev, queue_id, 0, true);
3621 }
3622 /* mac enable */
3623 hclge_cfg_mac_mode(hdev, true);
3624 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
3625 mod_timer(&hdev->service_timer, jiffies + HZ);
3626
3627 ret = hclge_mac_start_phy(hdev);
3628 if (ret)
3629 return ret;
3630
3631 /* reset tqp stats */
3632 hclge_reset_tqp_stats(handle);
3633
3634 return 0;
3635 }
3636
3637 static void hclge_ae_stop(struct hnae3_handle *handle)
3638 {
3639 struct hclge_vport *vport = hclge_get_vport(handle);
3640 struct hclge_dev *hdev = vport->back;
3641 int i, queue_id;
3642
3643 for (i = 0; i < vport->alloc_tqps; i++) {
3644 /* Ring disable */
3645 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3646 if (queue_id < 0) {
3647 dev_warn(&hdev->pdev->dev,
3648 "Get invalid queue id, ignore it\n");
3649 continue;
3650 }
3651
3652 hclge_tqp_enable(hdev, queue_id, 0, false);
3653 }
3654 /* Mac disable */
3655 hclge_cfg_mac_mode(hdev, false);
3656
3657 hclge_mac_stop_phy(hdev);
3658
3659 /* reset tqp stats */
3660 hclge_reset_tqp_stats(handle);
3661 }
3662
3663 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3664 u16 cmdq_resp, u8 resp_code,
3665 enum hclge_mac_vlan_tbl_opcode op)
3666 {
3667 struct hclge_dev *hdev = vport->back;
3668 int return_status = -EIO;
3669
3670 if (cmdq_resp) {
3671 dev_err(&hdev->pdev->dev,
3672 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3673 cmdq_resp);
3674 return -EIO;
3675 }
3676
3677 if (op == HCLGE_MAC_VLAN_ADD) {
3678 if ((!resp_code) || (resp_code == 1)) {
3679 return_status = 0;
3680 } else if (resp_code == 2) {
3681 return_status = -EIO;
3682 dev_err(&hdev->pdev->dev,
3683 "add mac addr failed for uc_overflow.\n");
3684 } else if (resp_code == 3) {
3685 return_status = -EIO;
3686 dev_err(&hdev->pdev->dev,
3687 "add mac addr failed for mc_overflow.\n");
3688 } else {
3689 dev_err(&hdev->pdev->dev,
3690 "add mac addr failed for undefined, code=%d.\n",
3691 resp_code);
3692 }
3693 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3694 if (!resp_code) {
3695 return_status = 0;
3696 } else if (resp_code == 1) {
3697 return_status = -EIO;
3698 dev_dbg(&hdev->pdev->dev,
3699 "remove mac addr failed for miss.\n");
3700 } else {
3701 dev_err(&hdev->pdev->dev,
3702 "remove mac addr failed for undefined, code=%d.\n",
3703 resp_code);
3704 }
3705 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3706 if (!resp_code) {
3707 return_status = 0;
3708 } else if (resp_code == 1) {
3709 return_status = -EIO;
3710 dev_dbg(&hdev->pdev->dev,
3711 "lookup mac addr failed for miss.\n");
3712 } else {
3713 dev_err(&hdev->pdev->dev,
3714 "lookup mac addr failed for undefined, code=%d.\n",
3715 resp_code);
3716 }
3717 } else {
3718 return_status = -EIO;
3719 dev_err(&hdev->pdev->dev,
3720 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3721 op);
3722 }
3723
3724 return return_status;
3725 }
3726
3727 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3728 {
3729 int word_num;
3730 int bit_num;
3731
3732 if (vfid > 255 || vfid < 0)
3733 return -EIO;
3734
3735 if (vfid >= 0 && vfid <= 191) {
3736 word_num = vfid / 32;
3737 bit_num = vfid % 32;
3738 if (clr)
3739 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
3740 else
3741 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
3742 } else {
3743 word_num = (vfid - 192) / 32;
3744 bit_num = vfid % 32;
3745 if (clr)
3746 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
3747 else
3748 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
3749 }
3750
3751 return 0;
3752 }
3753
3754 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3755 {
3756 #define HCLGE_DESC_NUMBER 3
3757 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3758 int i, j;
3759
3760 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3761 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3762 if (desc[i].data[j])
3763 return false;
3764
3765 return true;
3766 }
3767
3768 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
3769 const u8 *addr)
3770 {
3771 const unsigned char *mac_addr = addr;
3772 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3773 (mac_addr[0]) | (mac_addr[1] << 8);
3774 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3775
3776 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3777 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3778 }
3779
3780 static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3781 const u8 *addr)
3782 {
3783 u16 high_val = addr[1] | (addr[0] << 8);
3784 struct hclge_dev *hdev = vport->back;
3785 u32 rsh = 4 - hdev->mta_mac_sel_type;
3786 u16 ret_val = (high_val >> rsh) & 0xfff;
3787
3788 return ret_val;
3789 }
3790
3791 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3792 enum hclge_mta_dmac_sel_type mta_mac_sel,
3793 bool enable)
3794 {
3795 struct hclge_mta_filter_mode_cmd *req;
3796 struct hclge_desc desc;
3797 int ret;
3798
3799 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
3800 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3801
3802 hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3803 enable);
3804 hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3805 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3806
3807 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3808 if (ret) {
3809 dev_err(&hdev->pdev->dev,
3810 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3811 ret);
3812 return ret;
3813 }
3814
3815 return 0;
3816 }
3817
3818 int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3819 u8 func_id,
3820 bool enable)
3821 {
3822 struct hclge_cfg_func_mta_filter_cmd *req;
3823 struct hclge_desc desc;
3824 int ret;
3825
3826 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
3827 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3828
3829 hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3830 enable);
3831 req->function_id = func_id;
3832
3833 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3834 if (ret) {
3835 dev_err(&hdev->pdev->dev,
3836 "Config func_id enable failed for cmd_send, ret =%d.\n",
3837 ret);
3838 return ret;
3839 }
3840
3841 return 0;
3842 }
3843
3844 static int hclge_set_mta_table_item(struct hclge_vport *vport,
3845 u16 idx,
3846 bool enable)
3847 {
3848 struct hclge_dev *hdev = vport->back;
3849 struct hclge_cfg_func_mta_item_cmd *req;
3850 struct hclge_desc desc;
3851 u16 item_idx = 0;
3852 int ret;
3853
3854 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
3855 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
3856 hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
3857
3858 hnae_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
3859 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
3860 req->item_idx = cpu_to_le16(item_idx);
3861
3862 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3863 if (ret) {
3864 dev_err(&hdev->pdev->dev,
3865 "Config mta table item failed for cmd_send, ret =%d.\n",
3866 ret);
3867 return ret;
3868 }
3869
3870 return 0;
3871 }
3872
3873 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
3874 struct hclge_mac_vlan_tbl_entry_cmd *req)
3875 {
3876 struct hclge_dev *hdev = vport->back;
3877 struct hclge_desc desc;
3878 u8 resp_code;
3879 u16 retval;
3880 int ret;
3881
3882 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
3883
3884 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
3885
3886 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3887 if (ret) {
3888 dev_err(&hdev->pdev->dev,
3889 "del mac addr failed for cmd_send, ret =%d.\n",
3890 ret);
3891 return ret;
3892 }
3893 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3894 retval = le16_to_cpu(desc.retval);
3895
3896 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
3897 HCLGE_MAC_VLAN_REMOVE);
3898 }
3899
3900 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
3901 struct hclge_mac_vlan_tbl_entry_cmd *req,
3902 struct hclge_desc *desc,
3903 bool is_mc)
3904 {
3905 struct hclge_dev *hdev = vport->back;
3906 u8 resp_code;
3907 u16 retval;
3908 int ret;
3909
3910 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
3911 if (is_mc) {
3912 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3913 memcpy(desc[0].data,
3914 req,
3915 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
3916 hclge_cmd_setup_basic_desc(&desc[1],
3917 HCLGE_OPC_MAC_VLAN_ADD,
3918 true);
3919 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3920 hclge_cmd_setup_basic_desc(&desc[2],
3921 HCLGE_OPC_MAC_VLAN_ADD,
3922 true);
3923 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3924 } else {
3925 memcpy(desc[0].data,
3926 req,
3927 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
3928 ret = hclge_cmd_send(&hdev->hw, desc, 1);
3929 }
3930 if (ret) {
3931 dev_err(&hdev->pdev->dev,
3932 "lookup mac addr failed for cmd_send, ret =%d.\n",
3933 ret);
3934 return ret;
3935 }
3936 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
3937 retval = le16_to_cpu(desc[0].retval);
3938
3939 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
3940 HCLGE_MAC_VLAN_LKUP);
3941 }
3942
3943 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
3944 struct hclge_mac_vlan_tbl_entry_cmd *req,
3945 struct hclge_desc *mc_desc)
3946 {
3947 struct hclge_dev *hdev = vport->back;
3948 int cfg_status;
3949 u8 resp_code;
3950 u16 retval;
3951 int ret;
3952
3953 if (!mc_desc) {
3954 struct hclge_desc desc;
3955
3956 hclge_cmd_setup_basic_desc(&desc,
3957 HCLGE_OPC_MAC_VLAN_ADD,
3958 false);
3959 memcpy(desc.data, req,
3960 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
3961 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3962 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3963 retval = le16_to_cpu(desc.retval);
3964
3965 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
3966 resp_code,
3967 HCLGE_MAC_VLAN_ADD);
3968 } else {
3969 hclge_cmd_reuse_desc(&mc_desc[0], false);
3970 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3971 hclge_cmd_reuse_desc(&mc_desc[1], false);
3972 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3973 hclge_cmd_reuse_desc(&mc_desc[2], false);
3974 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
3975 memcpy(mc_desc[0].data, req,
3976 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
3977 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
3978 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
3979 retval = le16_to_cpu(mc_desc[0].retval);
3980
3981 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
3982 resp_code,
3983 HCLGE_MAC_VLAN_ADD);
3984 }
3985
3986 if (ret) {
3987 dev_err(&hdev->pdev->dev,
3988 "add mac addr failed for cmd_send, ret =%d.\n",
3989 ret);
3990 return ret;
3991 }
3992
3993 return cfg_status;
3994 }
3995
3996 static int hclge_add_uc_addr(struct hnae3_handle *handle,
3997 const unsigned char *addr)
3998 {
3999 struct hclge_vport *vport = hclge_get_vport(handle);
4000
4001 return hclge_add_uc_addr_common(vport, addr);
4002 }
4003
4004 int hclge_add_uc_addr_common(struct hclge_vport *vport,
4005 const unsigned char *addr)
4006 {
4007 struct hclge_dev *hdev = vport->back;
4008 struct hclge_mac_vlan_tbl_entry_cmd req;
4009 enum hclge_cmd_status status;
4010 u16 egress_port = 0;
4011
4012 /* mac addr check */
4013 if (is_zero_ether_addr(addr) ||
4014 is_broadcast_ether_addr(addr) ||
4015 is_multicast_ether_addr(addr)) {
4016 dev_err(&hdev->pdev->dev,
4017 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4018 addr,
4019 is_zero_ether_addr(addr),
4020 is_broadcast_ether_addr(addr),
4021 is_multicast_ether_addr(addr));
4022 return -EINVAL;
4023 }
4024
4025 memset(&req, 0, sizeof(req));
4026 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4027 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4028 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0);
4029 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4030
4031 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_SW_EN_B, 0);
4032 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_TYPE_B, 0);
4033 hnae_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
4034 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
4035 hnae_set_field(egress_port, HCLGE_MAC_EPORT_PFID_M,
4036 HCLGE_MAC_EPORT_PFID_S, 0);
4037
4038 req.egress_port = cpu_to_le16(egress_port);
4039
4040 hclge_prepare_mac_addr(&req, addr);
4041
4042 status = hclge_add_mac_vlan_tbl(vport, &req, NULL);
4043
4044 return status;
4045 }
4046
4047 static int hclge_rm_uc_addr(struct hnae3_handle *handle,
4048 const unsigned char *addr)
4049 {
4050 struct hclge_vport *vport = hclge_get_vport(handle);
4051
4052 return hclge_rm_uc_addr_common(vport, addr);
4053 }
4054
4055 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4056 const unsigned char *addr)
4057 {
4058 struct hclge_dev *hdev = vport->back;
4059 struct hclge_mac_vlan_tbl_entry_cmd req;
4060 enum hclge_cmd_status status;
4061
4062 /* mac addr check */
4063 if (is_zero_ether_addr(addr) ||
4064 is_broadcast_ether_addr(addr) ||
4065 is_multicast_ether_addr(addr)) {
4066 dev_dbg(&hdev->pdev->dev,
4067 "Remove mac err! invalid mac:%pM.\n",
4068 addr);
4069 return -EINVAL;
4070 }
4071
4072 memset(&req, 0, sizeof(req));
4073 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4074 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4075 hclge_prepare_mac_addr(&req, addr);
4076 status = hclge_remove_mac_vlan_tbl(vport, &req);
4077
4078 return status;
4079 }
4080
4081 static int hclge_add_mc_addr(struct hnae3_handle *handle,
4082 const unsigned char *addr)
4083 {
4084 struct hclge_vport *vport = hclge_get_vport(handle);
4085
4086 return hclge_add_mc_addr_common(vport, addr);
4087 }
4088
4089 int hclge_add_mc_addr_common(struct hclge_vport *vport,
4090 const unsigned char *addr)
4091 {
4092 struct hclge_dev *hdev = vport->back;
4093 struct hclge_mac_vlan_tbl_entry_cmd req;
4094 struct hclge_desc desc[3];
4095 u16 tbl_idx;
4096 int status;
4097
4098 /* mac addr check */
4099 if (!is_multicast_ether_addr(addr)) {
4100 dev_err(&hdev->pdev->dev,
4101 "Add mc mac err! invalid mac:%pM.\n",
4102 addr);
4103 return -EINVAL;
4104 }
4105 memset(&req, 0, sizeof(req));
4106 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4107 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4108 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4109 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4110 hclge_prepare_mac_addr(&req, addr);
4111 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4112 if (!status) {
4113 /* This mac addr exist, update VFID for it */
4114 hclge_update_desc_vfid(desc, vport->vport_id, false);
4115 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4116 } else {
4117 /* This mac addr do not exist, add new entry for it */
4118 memset(desc[0].data, 0, sizeof(desc[0].data));
4119 memset(desc[1].data, 0, sizeof(desc[0].data));
4120 memset(desc[2].data, 0, sizeof(desc[0].data));
4121 hclge_update_desc_vfid(desc, vport->vport_id, false);
4122 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4123 }
4124
4125 /* Set MTA table for this MAC address */
4126 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4127 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4128
4129 return status;
4130 }
4131
4132 static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4133 const unsigned char *addr)
4134 {
4135 struct hclge_vport *vport = hclge_get_vport(handle);
4136
4137 return hclge_rm_mc_addr_common(vport, addr);
4138 }
4139
4140 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4141 const unsigned char *addr)
4142 {
4143 struct hclge_dev *hdev = vport->back;
4144 struct hclge_mac_vlan_tbl_entry_cmd req;
4145 enum hclge_cmd_status status;
4146 struct hclge_desc desc[3];
4147 u16 tbl_idx;
4148
4149 /* mac addr check */
4150 if (!is_multicast_ether_addr(addr)) {
4151 dev_dbg(&hdev->pdev->dev,
4152 "Remove mc mac err! invalid mac:%pM.\n",
4153 addr);
4154 return -EINVAL;
4155 }
4156
4157 memset(&req, 0, sizeof(req));
4158 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4159 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4160 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4161 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4162 hclge_prepare_mac_addr(&req, addr);
4163 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4164 if (!status) {
4165 /* This mac addr exist, remove this handle's VFID for it */
4166 hclge_update_desc_vfid(desc, vport->vport_id, true);
4167
4168 if (hclge_is_all_function_id_zero(desc))
4169 /* All the vfid is zero, so need to delete this entry */
4170 status = hclge_remove_mac_vlan_tbl(vport, &req);
4171 else
4172 /* Not all the vfid is zero, update the vfid */
4173 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4174
4175 } else {
4176 /* This mac addr do not exist, can't delete it */
4177 dev_err(&hdev->pdev->dev,
4178 "Rm multicast mac addr failed, ret = %d.\n",
4179 status);
4180 return -EIO;
4181 }
4182
4183 /* Set MTB table for this MAC address */
4184 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4185 status = hclge_set_mta_table_item(vport, tbl_idx, false);
4186
4187 return status;
4188 }
4189
4190 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4191 {
4192 struct hclge_vport *vport = hclge_get_vport(handle);
4193 struct hclge_dev *hdev = vport->back;
4194
4195 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4196 }
4197
4198 static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p)
4199 {
4200 const unsigned char *new_addr = (const unsigned char *)p;
4201 struct hclge_vport *vport = hclge_get_vport(handle);
4202 struct hclge_dev *hdev = vport->back;
4203
4204 /* mac addr check */
4205 if (is_zero_ether_addr(new_addr) ||
4206 is_broadcast_ether_addr(new_addr) ||
4207 is_multicast_ether_addr(new_addr)) {
4208 dev_err(&hdev->pdev->dev,
4209 "Change uc mac err! invalid mac:%p.\n",
4210 new_addr);
4211 return -EINVAL;
4212 }
4213
4214 hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr);
4215
4216 if (!hclge_add_uc_addr(handle, new_addr)) {
4217 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4218 return 0;
4219 }
4220
4221 return -EIO;
4222 }
4223
4224 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4225 bool filter_en)
4226 {
4227 struct hclge_vlan_filter_ctrl_cmd *req;
4228 struct hclge_desc desc;
4229 int ret;
4230
4231 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4232
4233 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
4234 req->vlan_type = vlan_type;
4235 req->vlan_fe = filter_en;
4236
4237 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4238 if (ret) {
4239 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4240 ret);
4241 return ret;
4242 }
4243
4244 return 0;
4245 }
4246
4247 int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4248 bool is_kill, u16 vlan, u8 qos, __be16 proto)
4249 {
4250 #define HCLGE_MAX_VF_BYTES 16
4251 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4252 struct hclge_vlan_filter_vf_cfg_cmd *req1;
4253 struct hclge_desc desc[2];
4254 u8 vf_byte_val;
4255 u8 vf_byte_off;
4256 int ret;
4257
4258 hclge_cmd_setup_basic_desc(&desc[0],
4259 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4260 hclge_cmd_setup_basic_desc(&desc[1],
4261 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4262
4263 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4264
4265 vf_byte_off = vfid / 8;
4266 vf_byte_val = 1 << (vfid % 8);
4267
4268 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4269 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
4270
4271 req0->vlan_id = cpu_to_le16(vlan);
4272 req0->vlan_cfg = is_kill;
4273
4274 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4275 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4276 else
4277 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4278
4279 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4280 if (ret) {
4281 dev_err(&hdev->pdev->dev,
4282 "Send vf vlan command fail, ret =%d.\n",
4283 ret);
4284 return ret;
4285 }
4286
4287 if (!is_kill) {
4288 if (!req0->resp_code || req0->resp_code == 1)
4289 return 0;
4290
4291 dev_err(&hdev->pdev->dev,
4292 "Add vf vlan filter fail, ret =%d.\n",
4293 req0->resp_code);
4294 } else {
4295 if (!req0->resp_code)
4296 return 0;
4297
4298 dev_err(&hdev->pdev->dev,
4299 "Kill vf vlan filter fail, ret =%d.\n",
4300 req0->resp_code);
4301 }
4302
4303 return -EIO;
4304 }
4305
4306 static int hclge_set_port_vlan_filter(struct hnae3_handle *handle,
4307 __be16 proto, u16 vlan_id,
4308 bool is_kill)
4309 {
4310 struct hclge_vport *vport = hclge_get_vport(handle);
4311 struct hclge_dev *hdev = vport->back;
4312 struct hclge_vlan_filter_pf_cfg_cmd *req;
4313 struct hclge_desc desc;
4314 u8 vlan_offset_byte_val;
4315 u8 vlan_offset_byte;
4316 u8 vlan_offset_160;
4317 int ret;
4318
4319 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4320
4321 vlan_offset_160 = vlan_id / 160;
4322 vlan_offset_byte = (vlan_id % 160) / 8;
4323 vlan_offset_byte_val = 1 << (vlan_id % 8);
4324
4325 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
4326 req->vlan_offset = vlan_offset_160;
4327 req->vlan_cfg = is_kill;
4328 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4329
4330 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4331 if (ret) {
4332 dev_err(&hdev->pdev->dev,
4333 "port vlan command, send fail, ret =%d.\n",
4334 ret);
4335 return ret;
4336 }
4337
4338 ret = hclge_set_vf_vlan_common(hdev, 0, is_kill, vlan_id, 0, proto);
4339 if (ret) {
4340 dev_err(&hdev->pdev->dev,
4341 "Set pf vlan filter config fail, ret =%d.\n",
4342 ret);
4343 return -EIO;
4344 }
4345
4346 return 0;
4347 }
4348
4349 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4350 u16 vlan, u8 qos, __be16 proto)
4351 {
4352 struct hclge_vport *vport = hclge_get_vport(handle);
4353 struct hclge_dev *hdev = vport->back;
4354
4355 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4356 return -EINVAL;
4357 if (proto != htons(ETH_P_8021Q))
4358 return -EPROTONOSUPPORT;
4359
4360 return hclge_set_vf_vlan_common(hdev, vfid, false, vlan, qos, proto);
4361 }
4362
4363 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
4364 {
4365 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
4366 struct hclge_vport_vtag_tx_cfg_cmd *req;
4367 struct hclge_dev *hdev = vport->back;
4368 struct hclge_desc desc;
4369 int status;
4370
4371 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
4372
4373 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
4374 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
4375 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
4376 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG_B,
4377 vcfg->accept_tag ? 1 : 0);
4378 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG_B,
4379 vcfg->accept_untag ? 1 : 0);
4380 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
4381 vcfg->insert_tag1_en ? 1 : 0);
4382 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
4383 vcfg->insert_tag2_en ? 1 : 0);
4384 hnae_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
4385
4386 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4387 req->vf_bitmap[req->vf_offset] =
4388 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4389
4390 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4391 if (status)
4392 dev_err(&hdev->pdev->dev,
4393 "Send port txvlan cfg command fail, ret =%d\n",
4394 status);
4395
4396 return status;
4397 }
4398
4399 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
4400 {
4401 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
4402 struct hclge_vport_vtag_rx_cfg_cmd *req;
4403 struct hclge_dev *hdev = vport->back;
4404 struct hclge_desc desc;
4405 int status;
4406
4407 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
4408
4409 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
4410 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
4411 vcfg->strip_tag1_en ? 1 : 0);
4412 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
4413 vcfg->strip_tag2_en ? 1 : 0);
4414 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
4415 vcfg->vlan1_vlan_prionly ? 1 : 0);
4416 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
4417 vcfg->vlan2_vlan_prionly ? 1 : 0);
4418
4419 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4420 req->vf_bitmap[req->vf_offset] =
4421 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4422
4423 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4424 if (status)
4425 dev_err(&hdev->pdev->dev,
4426 "Send port rxvlan cfg command fail, ret =%d\n",
4427 status);
4428
4429 return status;
4430 }
4431
4432 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
4433 {
4434 struct hclge_rx_vlan_type_cfg_cmd *rx_req;
4435 struct hclge_tx_vlan_type_cfg_cmd *tx_req;
4436 struct hclge_desc desc;
4437 int status;
4438
4439 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
4440 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
4441 rx_req->ot_fst_vlan_type =
4442 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
4443 rx_req->ot_sec_vlan_type =
4444 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
4445 rx_req->in_fst_vlan_type =
4446 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
4447 rx_req->in_sec_vlan_type =
4448 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
4449
4450 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4451 if (status) {
4452 dev_err(&hdev->pdev->dev,
4453 "Send rxvlan protocol type command fail, ret =%d\n",
4454 status);
4455 return status;
4456 }
4457
4458 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
4459
4460 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data;
4461 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
4462 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
4463
4464 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4465 if (status)
4466 dev_err(&hdev->pdev->dev,
4467 "Send txvlan protocol type command fail, ret =%d\n",
4468 status);
4469
4470 return status;
4471 }
4472
4473 static int hclge_init_vlan_config(struct hclge_dev *hdev)
4474 {
4475 #define HCLGE_FILTER_TYPE_VF 0
4476 #define HCLGE_FILTER_TYPE_PORT 1
4477 #define HCLGE_DEF_VLAN_TYPE 0x8100
4478
4479 struct hnae3_handle *handle;
4480 struct hclge_vport *vport;
4481 int ret;
4482 int i;
4483
4484 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true);
4485 if (ret)
4486 return ret;
4487
4488 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true);
4489 if (ret)
4490 return ret;
4491
4492 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4493 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4494 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4495 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4496 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
4497 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
4498
4499 ret = hclge_set_vlan_protocol_type(hdev);
4500 if (ret)
4501 return ret;
4502
4503 for (i = 0; i < hdev->num_alloc_vport; i++) {
4504 vport = &hdev->vport[i];
4505 vport->txvlan_cfg.accept_tag = true;
4506 vport->txvlan_cfg.accept_untag = true;
4507 vport->txvlan_cfg.insert_tag1_en = false;
4508 vport->txvlan_cfg.insert_tag2_en = false;
4509 vport->txvlan_cfg.default_tag1 = 0;
4510 vport->txvlan_cfg.default_tag2 = 0;
4511
4512 ret = hclge_set_vlan_tx_offload_cfg(vport);
4513 if (ret)
4514 return ret;
4515
4516 vport->rxvlan_cfg.strip_tag1_en = false;
4517 vport->rxvlan_cfg.strip_tag2_en = true;
4518 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4519 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4520
4521 ret = hclge_set_vlan_rx_offload_cfg(vport);
4522 if (ret)
4523 return ret;
4524 }
4525
4526 handle = &hdev->vport[0].nic;
4527 return hclge_set_port_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
4528 }
4529
4530 static int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
4531 {
4532 struct hclge_vport *vport = hclge_get_vport(handle);
4533
4534 vport->rxvlan_cfg.strip_tag1_en = false;
4535 vport->rxvlan_cfg.strip_tag2_en = enable;
4536 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4537 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4538
4539 return hclge_set_vlan_rx_offload_cfg(vport);
4540 }
4541
4542 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
4543 {
4544 struct hclge_vport *vport = hclge_get_vport(handle);
4545 struct hclge_config_max_frm_size_cmd *req;
4546 struct hclge_dev *hdev = vport->back;
4547 struct hclge_desc desc;
4548 int ret;
4549
4550 if ((new_mtu < HCLGE_MAC_MIN_MTU) || (new_mtu > HCLGE_MAC_MAX_MTU))
4551 return -EINVAL;
4552
4553 hdev->mps = new_mtu;
4554 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
4555
4556 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
4557 req->max_frm_size = cpu_to_le16(new_mtu);
4558
4559 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4560 if (ret) {
4561 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
4562 return ret;
4563 }
4564
4565 return 0;
4566 }
4567
4568 static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
4569 bool enable)
4570 {
4571 struct hclge_reset_tqp_queue_cmd *req;
4572 struct hclge_desc desc;
4573 int ret;
4574
4575 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
4576
4577 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
4578 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4579 hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
4580
4581 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4582 if (ret) {
4583 dev_err(&hdev->pdev->dev,
4584 "Send tqp reset cmd error, status =%d\n", ret);
4585 return ret;
4586 }
4587
4588 return 0;
4589 }
4590
4591 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
4592 {
4593 struct hclge_reset_tqp_queue_cmd *req;
4594 struct hclge_desc desc;
4595 int ret;
4596
4597 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
4598
4599 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
4600 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4601
4602 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4603 if (ret) {
4604 dev_err(&hdev->pdev->dev,
4605 "Get reset status error, status =%d\n", ret);
4606 return ret;
4607 }
4608
4609 return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
4610 }
4611
4612 void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
4613 {
4614 struct hclge_vport *vport = hclge_get_vport(handle);
4615 struct hclge_dev *hdev = vport->back;
4616 int reset_try_times = 0;
4617 int reset_status;
4618 int ret;
4619
4620 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
4621 if (ret) {
4622 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
4623 return;
4624 }
4625
4626 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, true);
4627 if (ret) {
4628 dev_warn(&hdev->pdev->dev,
4629 "Send reset tqp cmd fail, ret = %d\n", ret);
4630 return;
4631 }
4632
4633 reset_try_times = 0;
4634 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
4635 /* Wait for tqp hw reset */
4636 msleep(20);
4637 reset_status = hclge_get_reset_status(hdev, queue_id);
4638 if (reset_status)
4639 break;
4640 }
4641
4642 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
4643 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
4644 return;
4645 }
4646
4647 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, false);
4648 if (ret) {
4649 dev_warn(&hdev->pdev->dev,
4650 "Deassert the soft reset fail, ret = %d\n", ret);
4651 return;
4652 }
4653 }
4654
4655 static u32 hclge_get_fw_version(struct hnae3_handle *handle)
4656 {
4657 struct hclge_vport *vport = hclge_get_vport(handle);
4658 struct hclge_dev *hdev = vport->back;
4659
4660 return hdev->fw_version;
4661 }
4662
4663 static void hclge_get_flowctrl_adv(struct hnae3_handle *handle,
4664 u32 *flowctrl_adv)
4665 {
4666 struct hclge_vport *vport = hclge_get_vport(handle);
4667 struct hclge_dev *hdev = vport->back;
4668 struct phy_device *phydev = hdev->hw.mac.phydev;
4669
4670 if (!phydev)
4671 return;
4672
4673 *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) |
4674 (phydev->advertising & ADVERTISED_Asym_Pause);
4675 }
4676
4677 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
4678 {
4679 struct phy_device *phydev = hdev->hw.mac.phydev;
4680
4681 if (!phydev)
4682 return;
4683
4684 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
4685
4686 if (rx_en)
4687 phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
4688
4689 if (tx_en)
4690 phydev->advertising ^= ADVERTISED_Asym_Pause;
4691 }
4692
4693 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
4694 {
4695 enum hclge_fc_mode fc_mode;
4696 int ret;
4697
4698 if (rx_en && tx_en)
4699 fc_mode = HCLGE_FC_FULL;
4700 else if (rx_en && !tx_en)
4701 fc_mode = HCLGE_FC_RX_PAUSE;
4702 else if (!rx_en && tx_en)
4703 fc_mode = HCLGE_FC_TX_PAUSE;
4704 else
4705 fc_mode = HCLGE_FC_NONE;
4706
4707 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
4708 hdev->fc_mode_last_time = fc_mode;
4709 return 0;
4710 }
4711
4712 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
4713 if (ret) {
4714 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
4715 ret);
4716 return ret;
4717 }
4718
4719 hdev->tm_info.fc_mode = fc_mode;
4720
4721 return 0;
4722 }
4723
4724 int hclge_cfg_flowctrl(struct hclge_dev *hdev)
4725 {
4726 struct phy_device *phydev = hdev->hw.mac.phydev;
4727 u16 remote_advertising = 0;
4728 u16 local_advertising = 0;
4729 u32 rx_pause, tx_pause;
4730 u8 flowctl;
4731
4732 if (!phydev->link || !phydev->autoneg)
4733 return 0;
4734
4735 if (phydev->advertising & ADVERTISED_Pause)
4736 local_advertising = ADVERTISE_PAUSE_CAP;
4737
4738 if (phydev->advertising & ADVERTISED_Asym_Pause)
4739 local_advertising |= ADVERTISE_PAUSE_ASYM;
4740
4741 if (phydev->pause)
4742 remote_advertising = LPA_PAUSE_CAP;
4743
4744 if (phydev->asym_pause)
4745 remote_advertising |= LPA_PAUSE_ASYM;
4746
4747 flowctl = mii_resolve_flowctrl_fdx(local_advertising,
4748 remote_advertising);
4749 tx_pause = flowctl & FLOW_CTRL_TX;
4750 rx_pause = flowctl & FLOW_CTRL_RX;
4751
4752 if (phydev->duplex == HCLGE_MAC_HALF) {
4753 tx_pause = 0;
4754 rx_pause = 0;
4755 }
4756
4757 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
4758 }
4759
4760 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
4761 u32 *rx_en, u32 *tx_en)
4762 {
4763 struct hclge_vport *vport = hclge_get_vport(handle);
4764 struct hclge_dev *hdev = vport->back;
4765
4766 *auto_neg = hclge_get_autoneg(handle);
4767
4768 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
4769 *rx_en = 0;
4770 *tx_en = 0;
4771 return;
4772 }
4773
4774 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
4775 *rx_en = 1;
4776 *tx_en = 0;
4777 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
4778 *tx_en = 1;
4779 *rx_en = 0;
4780 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
4781 *rx_en = 1;
4782 *tx_en = 1;
4783 } else {
4784 *rx_en = 0;
4785 *tx_en = 0;
4786 }
4787 }
4788
4789 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
4790 u32 rx_en, u32 tx_en)
4791 {
4792 struct hclge_vport *vport = hclge_get_vport(handle);
4793 struct hclge_dev *hdev = vport->back;
4794 struct phy_device *phydev = hdev->hw.mac.phydev;
4795 u32 fc_autoneg;
4796
4797 /* Only support flow control negotiation for netdev with
4798 * phy attached for now.
4799 */
4800 if (!phydev)
4801 return -EOPNOTSUPP;
4802
4803 fc_autoneg = hclge_get_autoneg(handle);
4804 if (auto_neg != fc_autoneg) {
4805 dev_info(&hdev->pdev->dev,
4806 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
4807 return -EOPNOTSUPP;
4808 }
4809
4810 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
4811 dev_info(&hdev->pdev->dev,
4812 "Priority flow control enabled. Cannot set link flow control.\n");
4813 return -EOPNOTSUPP;
4814 }
4815
4816 hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
4817
4818 if (!fc_autoneg)
4819 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
4820
4821 return phy_start_aneg(phydev);
4822 }
4823
4824 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
4825 u8 *auto_neg, u32 *speed, u8 *duplex)
4826 {
4827 struct hclge_vport *vport = hclge_get_vport(handle);
4828 struct hclge_dev *hdev = vport->back;
4829
4830 if (speed)
4831 *speed = hdev->hw.mac.speed;
4832 if (duplex)
4833 *duplex = hdev->hw.mac.duplex;
4834 if (auto_neg)
4835 *auto_neg = hdev->hw.mac.autoneg;
4836 }
4837
4838 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
4839 {
4840 struct hclge_vport *vport = hclge_get_vport(handle);
4841 struct hclge_dev *hdev = vport->back;
4842
4843 if (media_type)
4844 *media_type = hdev->hw.mac.media_type;
4845 }
4846
4847 static void hclge_get_mdix_mode(struct hnae3_handle *handle,
4848 u8 *tp_mdix_ctrl, u8 *tp_mdix)
4849 {
4850 struct hclge_vport *vport = hclge_get_vport(handle);
4851 struct hclge_dev *hdev = vport->back;
4852 struct phy_device *phydev = hdev->hw.mac.phydev;
4853 int mdix_ctrl, mdix, retval, is_resolved;
4854
4855 if (!phydev) {
4856 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
4857 *tp_mdix = ETH_TP_MDI_INVALID;
4858 return;
4859 }
4860
4861 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
4862
4863 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
4864 mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
4865 HCLGE_PHY_MDIX_CTRL_S);
4866
4867 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
4868 mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
4869 is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
4870
4871 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
4872
4873 switch (mdix_ctrl) {
4874 case 0x0:
4875 *tp_mdix_ctrl = ETH_TP_MDI;
4876 break;
4877 case 0x1:
4878 *tp_mdix_ctrl = ETH_TP_MDI_X;
4879 break;
4880 case 0x3:
4881 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
4882 break;
4883 default:
4884 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
4885 break;
4886 }
4887
4888 if (!is_resolved)
4889 *tp_mdix = ETH_TP_MDI_INVALID;
4890 else if (mdix)
4891 *tp_mdix = ETH_TP_MDI_X;
4892 else
4893 *tp_mdix = ETH_TP_MDI;
4894 }
4895
4896 static int hclge_init_client_instance(struct hnae3_client *client,
4897 struct hnae3_ae_dev *ae_dev)
4898 {
4899 struct hclge_dev *hdev = ae_dev->priv;
4900 struct hclge_vport *vport;
4901 int i, ret;
4902
4903 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
4904 vport = &hdev->vport[i];
4905
4906 switch (client->type) {
4907 case HNAE3_CLIENT_KNIC:
4908
4909 hdev->nic_client = client;
4910 vport->nic.client = client;
4911 ret = client->ops->init_instance(&vport->nic);
4912 if (ret)
4913 goto err;
4914
4915 if (hdev->roce_client &&
4916 hnae3_dev_roce_supported(hdev)) {
4917 struct hnae3_client *rc = hdev->roce_client;
4918
4919 ret = hclge_init_roce_base_info(vport);
4920 if (ret)
4921 goto err;
4922
4923 ret = rc->ops->init_instance(&vport->roce);
4924 if (ret)
4925 goto err;
4926 }
4927
4928 break;
4929 case HNAE3_CLIENT_UNIC:
4930 hdev->nic_client = client;
4931 vport->nic.client = client;
4932
4933 ret = client->ops->init_instance(&vport->nic);
4934 if (ret)
4935 goto err;
4936
4937 break;
4938 case HNAE3_CLIENT_ROCE:
4939 if (hnae3_dev_roce_supported(hdev)) {
4940 hdev->roce_client = client;
4941 vport->roce.client = client;
4942 }
4943
4944 if (hdev->roce_client && hdev->nic_client) {
4945 ret = hclge_init_roce_base_info(vport);
4946 if (ret)
4947 goto err;
4948
4949 ret = client->ops->init_instance(&vport->roce);
4950 if (ret)
4951 goto err;
4952 }
4953 }
4954 }
4955
4956 return 0;
4957 err:
4958 return ret;
4959 }
4960
4961 static void hclge_uninit_client_instance(struct hnae3_client *client,
4962 struct hnae3_ae_dev *ae_dev)
4963 {
4964 struct hclge_dev *hdev = ae_dev->priv;
4965 struct hclge_vport *vport;
4966 int i;
4967
4968 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
4969 vport = &hdev->vport[i];
4970 if (hdev->roce_client) {
4971 hdev->roce_client->ops->uninit_instance(&vport->roce,
4972 0);
4973 hdev->roce_client = NULL;
4974 vport->roce.client = NULL;
4975 }
4976 if (client->type == HNAE3_CLIENT_ROCE)
4977 return;
4978 if (client->ops->uninit_instance) {
4979 client->ops->uninit_instance(&vport->nic, 0);
4980 hdev->nic_client = NULL;
4981 vport->nic.client = NULL;
4982 }
4983 }
4984 }
4985
4986 static int hclge_pci_init(struct hclge_dev *hdev)
4987 {
4988 struct pci_dev *pdev = hdev->pdev;
4989 struct hclge_hw *hw;
4990 int ret;
4991
4992 ret = pci_enable_device(pdev);
4993 if (ret) {
4994 dev_err(&pdev->dev, "failed to enable PCI device\n");
4995 goto err_no_drvdata;
4996 }
4997
4998 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
4999 if (ret) {
5000 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
5001 if (ret) {
5002 dev_err(&pdev->dev,
5003 "can't set consistent PCI DMA");
5004 goto err_disable_device;
5005 }
5006 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
5007 }
5008
5009 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
5010 if (ret) {
5011 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
5012 goto err_disable_device;
5013 }
5014
5015 pci_set_master(pdev);
5016 hw = &hdev->hw;
5017 hw->back = hdev;
5018 hw->io_base = pcim_iomap(pdev, 2, 0);
5019 if (!hw->io_base) {
5020 dev_err(&pdev->dev, "Can't map configuration register space\n");
5021 ret = -ENOMEM;
5022 goto err_clr_master;
5023 }
5024
5025 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
5026
5027 return 0;
5028 err_clr_master:
5029 pci_clear_master(pdev);
5030 pci_release_regions(pdev);
5031 err_disable_device:
5032 pci_disable_device(pdev);
5033 err_no_drvdata:
5034 pci_set_drvdata(pdev, NULL);
5035
5036 return ret;
5037 }
5038
5039 static void hclge_pci_uninit(struct hclge_dev *hdev)
5040 {
5041 struct pci_dev *pdev = hdev->pdev;
5042
5043 pci_free_irq_vectors(pdev);
5044 pci_clear_master(pdev);
5045 pci_release_mem_regions(pdev);
5046 pci_disable_device(pdev);
5047 }
5048
5049 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
5050 {
5051 struct pci_dev *pdev = ae_dev->pdev;
5052 struct hclge_dev *hdev;
5053 int ret;
5054
5055 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
5056 if (!hdev) {
5057 ret = -ENOMEM;
5058 goto err_hclge_dev;
5059 }
5060
5061 hdev->pdev = pdev;
5062 hdev->ae_dev = ae_dev;
5063 hdev->reset_type = HNAE3_NONE_RESET;
5064 hdev->reset_request = 0;
5065 hdev->reset_pending = 0;
5066 ae_dev->priv = hdev;
5067
5068 ret = hclge_pci_init(hdev);
5069 if (ret) {
5070 dev_err(&pdev->dev, "PCI init failed\n");
5071 goto err_pci_init;
5072 }
5073
5074 /* Firmware command queue initialize */
5075 ret = hclge_cmd_queue_init(hdev);
5076 if (ret) {
5077 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
5078 return ret;
5079 }
5080
5081 /* Firmware command initialize */
5082 ret = hclge_cmd_init(hdev);
5083 if (ret)
5084 goto err_cmd_init;
5085
5086 ret = hclge_get_cap(hdev);
5087 if (ret) {
5088 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5089 ret);
5090 return ret;
5091 }
5092
5093 ret = hclge_configure(hdev);
5094 if (ret) {
5095 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5096 return ret;
5097 }
5098
5099 ret = hclge_init_msi(hdev);
5100 if (ret) {
5101 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
5102 return ret;
5103 }
5104
5105 ret = hclge_misc_irq_init(hdev);
5106 if (ret) {
5107 dev_err(&pdev->dev,
5108 "Misc IRQ(vector0) init error, ret = %d.\n",
5109 ret);
5110 return ret;
5111 }
5112
5113 ret = hclge_alloc_tqps(hdev);
5114 if (ret) {
5115 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
5116 return ret;
5117 }
5118
5119 ret = hclge_alloc_vport(hdev);
5120 if (ret) {
5121 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
5122 return ret;
5123 }
5124
5125 ret = hclge_map_tqp(hdev);
5126 if (ret) {
5127 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5128 return ret;
5129 }
5130
5131 ret = hclge_mac_mdio_config(hdev);
5132 if (ret) {
5133 dev_warn(&hdev->pdev->dev,
5134 "mdio config fail ret=%d\n", ret);
5135 return ret;
5136 }
5137
5138 ret = hclge_mac_init(hdev);
5139 if (ret) {
5140 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5141 return ret;
5142 }
5143 ret = hclge_buffer_alloc(hdev);
5144 if (ret) {
5145 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
5146 return ret;
5147 }
5148
5149 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5150 if (ret) {
5151 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5152 return ret;
5153 }
5154
5155 ret = hclge_init_vlan_config(hdev);
5156 if (ret) {
5157 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5158 return ret;
5159 }
5160
5161 ret = hclge_tm_schd_init(hdev);
5162 if (ret) {
5163 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
5164 return ret;
5165 }
5166
5167 ret = hclge_rss_init_hw(hdev);
5168 if (ret) {
5169 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5170 return ret;
5171 }
5172
5173 hclge_dcb_ops_set(hdev);
5174
5175 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
5176 INIT_WORK(&hdev->service_task, hclge_service_task);
5177 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
5178 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
5179
5180 /* Enable MISC vector(vector0) */
5181 hclge_enable_vector(&hdev->misc_vector, true);
5182
5183 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
5184 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5185 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
5186 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
5187 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
5188 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
5189
5190 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
5191 return 0;
5192
5193 err_cmd_init:
5194 pci_release_regions(pdev);
5195 err_pci_init:
5196 pci_set_drvdata(pdev, NULL);
5197 err_hclge_dev:
5198 return ret;
5199 }
5200
5201 static void hclge_stats_clear(struct hclge_dev *hdev)
5202 {
5203 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
5204 }
5205
5206 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
5207 {
5208 struct hclge_dev *hdev = ae_dev->priv;
5209 struct pci_dev *pdev = ae_dev->pdev;
5210 int ret;
5211
5212 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5213
5214 hclge_stats_clear(hdev);
5215
5216 ret = hclge_cmd_init(hdev);
5217 if (ret) {
5218 dev_err(&pdev->dev, "Cmd queue init failed\n");
5219 return ret;
5220 }
5221
5222 ret = hclge_get_cap(hdev);
5223 if (ret) {
5224 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5225 ret);
5226 return ret;
5227 }
5228
5229 ret = hclge_configure(hdev);
5230 if (ret) {
5231 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5232 return ret;
5233 }
5234
5235 ret = hclge_map_tqp(hdev);
5236 if (ret) {
5237 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5238 return ret;
5239 }
5240
5241 ret = hclge_mac_init(hdev);
5242 if (ret) {
5243 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5244 return ret;
5245 }
5246
5247 ret = hclge_buffer_alloc(hdev);
5248 if (ret) {
5249 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
5250 return ret;
5251 }
5252
5253 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5254 if (ret) {
5255 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5256 return ret;
5257 }
5258
5259 ret = hclge_init_vlan_config(hdev);
5260 if (ret) {
5261 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5262 return ret;
5263 }
5264
5265 ret = hclge_tm_schd_init(hdev);
5266 if (ret) {
5267 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
5268 return ret;
5269 }
5270
5271 ret = hclge_rss_init_hw(hdev);
5272 if (ret) {
5273 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5274 return ret;
5275 }
5276
5277 /* Enable MISC vector(vector0) */
5278 hclge_enable_vector(&hdev->misc_vector, true);
5279
5280 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
5281 HCLGE_DRIVER_NAME);
5282
5283 return 0;
5284 }
5285
5286 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
5287 {
5288 struct hclge_dev *hdev = ae_dev->priv;
5289 struct hclge_mac *mac = &hdev->hw.mac;
5290
5291 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5292
5293 if (IS_ENABLED(CONFIG_PCI_IOV))
5294 hclge_disable_sriov(hdev);
5295
5296 if (hdev->service_timer.function)
5297 del_timer_sync(&hdev->service_timer);
5298 if (hdev->service_task.func)
5299 cancel_work_sync(&hdev->service_task);
5300 if (hdev->rst_service_task.func)
5301 cancel_work_sync(&hdev->rst_service_task);
5302 if (hdev->mbx_service_task.func)
5303 cancel_work_sync(&hdev->mbx_service_task);
5304
5305 if (mac->phydev)
5306 mdiobus_unregister(mac->mdio_bus);
5307
5308 /* Disable MISC vector(vector0) */
5309 hclge_enable_vector(&hdev->misc_vector, false);
5310 hclge_destroy_cmd_queue(&hdev->hw);
5311 hclge_misc_irq_uninit(hdev);
5312 hclge_pci_uninit(hdev);
5313 ae_dev->priv = NULL;
5314 }
5315
5316 static u32 hclge_get_max_channels(struct hnae3_handle *handle)
5317 {
5318 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5319 struct hclge_vport *vport = hclge_get_vport(handle);
5320 struct hclge_dev *hdev = vport->back;
5321
5322 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
5323 }
5324
5325 static void hclge_get_channels(struct hnae3_handle *handle,
5326 struct ethtool_channels *ch)
5327 {
5328 struct hclge_vport *vport = hclge_get_vport(handle);
5329
5330 ch->max_combined = hclge_get_max_channels(handle);
5331 ch->other_count = 1;
5332 ch->max_other = 1;
5333 ch->combined_count = vport->alloc_tqps;
5334 }
5335
5336 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
5337 u16 *free_tqps, u16 *max_rss_size)
5338 {
5339 struct hclge_vport *vport = hclge_get_vport(handle);
5340 struct hclge_dev *hdev = vport->back;
5341 u16 temp_tqps = 0;
5342 int i;
5343
5344 for (i = 0; i < hdev->num_tqps; i++) {
5345 if (!hdev->htqp[i].alloced)
5346 temp_tqps++;
5347 }
5348 *free_tqps = temp_tqps;
5349 *max_rss_size = hdev->rss_size_max;
5350 }
5351
5352 static void hclge_release_tqp(struct hclge_vport *vport)
5353 {
5354 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5355 struct hclge_dev *hdev = vport->back;
5356 int i;
5357
5358 for (i = 0; i < kinfo->num_tqps; i++) {
5359 struct hclge_tqp *tqp =
5360 container_of(kinfo->tqp[i], struct hclge_tqp, q);
5361
5362 tqp->q.handle = NULL;
5363 tqp->q.tqp_index = 0;
5364 tqp->alloced = false;
5365 }
5366
5367 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
5368 kinfo->tqp = NULL;
5369 }
5370
5371 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
5372 {
5373 struct hclge_vport *vport = hclge_get_vport(handle);
5374 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5375 struct hclge_dev *hdev = vport->back;
5376 int cur_rss_size = kinfo->rss_size;
5377 int cur_tqps = kinfo->num_tqps;
5378 u16 tc_offset[HCLGE_MAX_TC_NUM];
5379 u16 tc_valid[HCLGE_MAX_TC_NUM];
5380 u16 tc_size[HCLGE_MAX_TC_NUM];
5381 u16 roundup_size;
5382 u32 *rss_indir;
5383 int ret, i;
5384
5385 hclge_release_tqp(vport);
5386
5387 ret = hclge_knic_setup(vport, new_tqps_num);
5388 if (ret) {
5389 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
5390 return ret;
5391 }
5392
5393 ret = hclge_map_tqp_to_vport(hdev, vport);
5394 if (ret) {
5395 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
5396 return ret;
5397 }
5398
5399 ret = hclge_tm_schd_init(hdev);
5400 if (ret) {
5401 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
5402 return ret;
5403 }
5404
5405 roundup_size = roundup_pow_of_two(kinfo->rss_size);
5406 roundup_size = ilog2(roundup_size);
5407 /* Set the RSS TC mode according to the new RSS size */
5408 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
5409 tc_valid[i] = 0;
5410
5411 if (!(hdev->hw_tc_map & BIT(i)))
5412 continue;
5413
5414 tc_valid[i] = 1;
5415 tc_size[i] = roundup_size;
5416 tc_offset[i] = kinfo->rss_size * i;
5417 }
5418 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
5419 if (ret)
5420 return ret;
5421
5422 /* Reinitializes the rss indirect table according to the new RSS size */
5423 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
5424 if (!rss_indir)
5425 return -ENOMEM;
5426
5427 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
5428 rss_indir[i] = i % kinfo->rss_size;
5429
5430 ret = hclge_set_rss(handle, rss_indir, NULL, 0);
5431 if (ret)
5432 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
5433 ret);
5434
5435 kfree(rss_indir);
5436
5437 if (!ret)
5438 dev_info(&hdev->pdev->dev,
5439 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5440 cur_rss_size, kinfo->rss_size,
5441 cur_tqps, kinfo->rss_size * kinfo->num_tc);
5442
5443 return ret;
5444 }
5445
5446 static const struct hnae3_ae_ops hclge_ops = {
5447 .init_ae_dev = hclge_init_ae_dev,
5448 .uninit_ae_dev = hclge_uninit_ae_dev,
5449 .init_client_instance = hclge_init_client_instance,
5450 .uninit_client_instance = hclge_uninit_client_instance,
5451 .map_ring_to_vector = hclge_map_ring_to_vector,
5452 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
5453 .get_vector = hclge_get_vector,
5454 .set_promisc_mode = hclge_set_promisc_mode,
5455 .set_loopback = hclge_set_loopback,
5456 .start = hclge_ae_start,
5457 .stop = hclge_ae_stop,
5458 .get_status = hclge_get_status,
5459 .get_ksettings_an_result = hclge_get_ksettings_an_result,
5460 .update_speed_duplex_h = hclge_update_speed_duplex_h,
5461 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
5462 .get_media_type = hclge_get_media_type,
5463 .get_rss_key_size = hclge_get_rss_key_size,
5464 .get_rss_indir_size = hclge_get_rss_indir_size,
5465 .get_rss = hclge_get_rss,
5466 .set_rss = hclge_set_rss,
5467 .set_rss_tuple = hclge_set_rss_tuple,
5468 .get_rss_tuple = hclge_get_rss_tuple,
5469 .get_tc_size = hclge_get_tc_size,
5470 .get_mac_addr = hclge_get_mac_addr,
5471 .set_mac_addr = hclge_set_mac_addr,
5472 .add_uc_addr = hclge_add_uc_addr,
5473 .rm_uc_addr = hclge_rm_uc_addr,
5474 .add_mc_addr = hclge_add_mc_addr,
5475 .rm_mc_addr = hclge_rm_mc_addr,
5476 .set_autoneg = hclge_set_autoneg,
5477 .get_autoneg = hclge_get_autoneg,
5478 .get_pauseparam = hclge_get_pauseparam,
5479 .set_pauseparam = hclge_set_pauseparam,
5480 .set_mtu = hclge_set_mtu,
5481 .reset_queue = hclge_reset_tqp,
5482 .get_stats = hclge_get_stats,
5483 .update_stats = hclge_update_stats,
5484 .get_strings = hclge_get_strings,
5485 .get_sset_count = hclge_get_sset_count,
5486 .get_fw_version = hclge_get_fw_version,
5487 .get_mdix_mode = hclge_get_mdix_mode,
5488 .set_vlan_filter = hclge_set_port_vlan_filter,
5489 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
5490 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
5491 .reset_event = hclge_reset_event,
5492 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
5493 .set_channels = hclge_set_channels,
5494 .get_channels = hclge_get_channels,
5495 .get_flowctrl_adv = hclge_get_flowctrl_adv,
5496 };
5497
5498 static struct hnae3_ae_algo ae_algo = {
5499 .ops = &hclge_ops,
5500 .name = HCLGE_NAME,
5501 .pdev_id_table = ae_algo_pci_tbl,
5502 };
5503
5504 static int hclge_init(void)
5505 {
5506 pr_info("%s is initializing\n", HCLGE_NAME);
5507
5508 return hnae3_register_ae_algo(&ae_algo);
5509 }
5510
5511 static void hclge_exit(void)
5512 {
5513 hnae3_unregister_ae_algo(&ae_algo);
5514 }
5515 module_init(hclge_init);
5516 module_exit(hclge_exit);
5517
5518 MODULE_LICENSE("GPL");
5519 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
5520 MODULE_DESCRIPTION("HCLGE Driver");
5521 MODULE_VERSION(HCLGE_MOD_VERSION);
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