2 * Copyright (c) 2016-2017 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/acpi.h>
11 #include <linux/device.h>
12 #include <linux/etherdevice.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
20 #include <linux/if_vlan.h>
21 #include <net/rtnetlink.h>
22 #include "hclge_cmd.h"
23 #include "hclge_dcb.h"
24 #include "hclge_main.h"
25 #include "hclge_mbx.h"
26 #include "hclge_mdio.h"
30 #define HCLGE_NAME "hclge"
31 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
32 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
33 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
34 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
36 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
37 enum hclge_mta_dmac_sel_type mta_mac_sel
,
39 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
);
40 static int hclge_init_vlan_config(struct hclge_dev
*hdev
);
41 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
);
42 static int hclge_update_led_status(struct hclge_dev
*hdev
);
44 static struct hnae3_ae_algo ae_algo
;
46 static const struct pci_device_id ae_algo_pci_tbl
[] = {
47 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_GE
), 0},
48 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE
), 0},
49 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA
), 0},
50 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA_MACSEC
), 0},
51 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA
), 0},
52 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA_MACSEC
), 0},
53 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_100G_RDMA_MACSEC
), 0},
54 /* required last entry */
58 MODULE_DEVICE_TABLE(pci
, ae_algo_pci_tbl
);
60 static const char hns3_nic_test_strs
[][ETH_GSTRING_LEN
] = {
62 "Serdes Loopback test",
66 static const struct hclge_comm_stats_str g_all_64bit_stats_string
[] = {
67 {"igu_rx_oversize_pkt",
68 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt
)},
69 {"igu_rx_undersize_pkt",
70 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt
)},
71 {"igu_rx_out_all_pkt",
72 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt
)},
74 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt
)},
76 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt
)},
78 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt
)},
79 {"egu_tx_out_all_pkt",
80 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt
)},
82 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt
)},
84 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt
)},
86 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt
)},
87 {"ssu_ppp_mac_key_num",
88 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num
)},
89 {"ssu_ppp_host_key_num",
90 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num
)},
91 {"ppp_ssu_mac_rlt_num",
92 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num
)},
93 {"ppp_ssu_host_rlt_num",
94 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num
)},
96 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num
)},
98 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num
)},
100 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num
)},
102 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num
)}
105 static const struct hclge_comm_stats_str g_all_32bit_stats_string
[] = {
107 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt
)},
108 {"igu_rx_no_eof_pkt",
109 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt
)},
110 {"igu_rx_no_sof_pkt",
111 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt
)},
113 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt
)},
114 {"ssu_full_drop_num",
115 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num
)},
116 {"ssu_part_drop_num",
117 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num
)},
119 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num
)},
121 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num
)},
123 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num
)},
125 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt
)},
127 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt
)},
129 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt
)},
130 {"qcn_fb_invaild_cnt",
131 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt
)},
132 {"rx_packet_tc0_in_cnt",
133 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt
)},
134 {"rx_packet_tc1_in_cnt",
135 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt
)},
136 {"rx_packet_tc2_in_cnt",
137 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt
)},
138 {"rx_packet_tc3_in_cnt",
139 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt
)},
140 {"rx_packet_tc4_in_cnt",
141 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt
)},
142 {"rx_packet_tc5_in_cnt",
143 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt
)},
144 {"rx_packet_tc6_in_cnt",
145 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt
)},
146 {"rx_packet_tc7_in_cnt",
147 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt
)},
148 {"rx_packet_tc0_out_cnt",
149 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt
)},
150 {"rx_packet_tc1_out_cnt",
151 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt
)},
152 {"rx_packet_tc2_out_cnt",
153 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt
)},
154 {"rx_packet_tc3_out_cnt",
155 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt
)},
156 {"rx_packet_tc4_out_cnt",
157 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt
)},
158 {"rx_packet_tc5_out_cnt",
159 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt
)},
160 {"rx_packet_tc6_out_cnt",
161 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt
)},
162 {"rx_packet_tc7_out_cnt",
163 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt
)},
164 {"tx_packet_tc0_in_cnt",
165 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt
)},
166 {"tx_packet_tc1_in_cnt",
167 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt
)},
168 {"tx_packet_tc2_in_cnt",
169 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt
)},
170 {"tx_packet_tc3_in_cnt",
171 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt
)},
172 {"tx_packet_tc4_in_cnt",
173 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt
)},
174 {"tx_packet_tc5_in_cnt",
175 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt
)},
176 {"tx_packet_tc6_in_cnt",
177 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt
)},
178 {"tx_packet_tc7_in_cnt",
179 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt
)},
180 {"tx_packet_tc0_out_cnt",
181 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt
)},
182 {"tx_packet_tc1_out_cnt",
183 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt
)},
184 {"tx_packet_tc2_out_cnt",
185 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt
)},
186 {"tx_packet_tc3_out_cnt",
187 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt
)},
188 {"tx_packet_tc4_out_cnt",
189 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt
)},
190 {"tx_packet_tc5_out_cnt",
191 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt
)},
192 {"tx_packet_tc6_out_cnt",
193 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt
)},
194 {"tx_packet_tc7_out_cnt",
195 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt
)},
196 {"pkt_curr_buf_tc0_cnt",
197 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt
)},
198 {"pkt_curr_buf_tc1_cnt",
199 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt
)},
200 {"pkt_curr_buf_tc2_cnt",
201 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt
)},
202 {"pkt_curr_buf_tc3_cnt",
203 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt
)},
204 {"pkt_curr_buf_tc4_cnt",
205 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt
)},
206 {"pkt_curr_buf_tc5_cnt",
207 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt
)},
208 {"pkt_curr_buf_tc6_cnt",
209 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt
)},
210 {"pkt_curr_buf_tc7_cnt",
211 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt
)},
213 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num
)},
214 {"lo_pri_unicast_rlt_drop_num",
215 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num
)},
216 {"hi_pri_multicast_rlt_drop_num",
217 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num
)},
218 {"lo_pri_multicast_rlt_drop_num",
219 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num
)},
220 {"rx_oq_drop_pkt_cnt",
221 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt
)},
222 {"tx_oq_drop_pkt_cnt",
223 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt
)},
224 {"nic_l2_err_drop_pkt_cnt",
225 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt
)},
226 {"roc_l2_err_drop_pkt_cnt",
227 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt
)}
230 static const struct hclge_comm_stats_str g_mac_stats_string
[] = {
231 {"mac_tx_mac_pause_num",
232 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num
)},
233 {"mac_rx_mac_pause_num",
234 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num
)},
235 {"mac_tx_pfc_pri0_pkt_num",
236 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num
)},
237 {"mac_tx_pfc_pri1_pkt_num",
238 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num
)},
239 {"mac_tx_pfc_pri2_pkt_num",
240 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num
)},
241 {"mac_tx_pfc_pri3_pkt_num",
242 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num
)},
243 {"mac_tx_pfc_pri4_pkt_num",
244 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num
)},
245 {"mac_tx_pfc_pri5_pkt_num",
246 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num
)},
247 {"mac_tx_pfc_pri6_pkt_num",
248 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num
)},
249 {"mac_tx_pfc_pri7_pkt_num",
250 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num
)},
251 {"mac_rx_pfc_pri0_pkt_num",
252 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num
)},
253 {"mac_rx_pfc_pri1_pkt_num",
254 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num
)},
255 {"mac_rx_pfc_pri2_pkt_num",
256 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num
)},
257 {"mac_rx_pfc_pri3_pkt_num",
258 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num
)},
259 {"mac_rx_pfc_pri4_pkt_num",
260 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num
)},
261 {"mac_rx_pfc_pri5_pkt_num",
262 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num
)},
263 {"mac_rx_pfc_pri6_pkt_num",
264 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num
)},
265 {"mac_rx_pfc_pri7_pkt_num",
266 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num
)},
267 {"mac_tx_total_pkt_num",
268 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num
)},
269 {"mac_tx_total_oct_num",
270 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num
)},
271 {"mac_tx_good_pkt_num",
272 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num
)},
273 {"mac_tx_bad_pkt_num",
274 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num
)},
275 {"mac_tx_good_oct_num",
276 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num
)},
277 {"mac_tx_bad_oct_num",
278 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num
)},
279 {"mac_tx_uni_pkt_num",
280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num
)},
281 {"mac_tx_multi_pkt_num",
282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num
)},
283 {"mac_tx_broad_pkt_num",
284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num
)},
285 {"mac_tx_undersize_pkt_num",
286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num
)},
287 {"mac_tx_oversize_pkt_num",
288 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num
)},
289 {"mac_tx_64_oct_pkt_num",
290 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num
)},
291 {"mac_tx_65_127_oct_pkt_num",
292 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num
)},
293 {"mac_tx_128_255_oct_pkt_num",
294 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num
)},
295 {"mac_tx_256_511_oct_pkt_num",
296 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num
)},
297 {"mac_tx_512_1023_oct_pkt_num",
298 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num
)},
299 {"mac_tx_1024_1518_oct_pkt_num",
300 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num
)},
301 {"mac_tx_1519_2047_oct_pkt_num",
302 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num
)},
303 {"mac_tx_2048_4095_oct_pkt_num",
304 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num
)},
305 {"mac_tx_4096_8191_oct_pkt_num",
306 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num
)},
307 {"mac_tx_8192_12287_oct_pkt_num",
308 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_12287_oct_pkt_num
)},
309 {"mac_tx_8192_9216_oct_pkt_num",
310 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num
)},
311 {"mac_tx_9217_12287_oct_pkt_num",
312 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num
)},
313 {"mac_tx_12288_16383_oct_pkt_num",
314 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num
)},
315 {"mac_tx_1519_max_good_pkt_num",
316 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num
)},
317 {"mac_tx_1519_max_bad_pkt_num",
318 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num
)},
319 {"mac_rx_total_pkt_num",
320 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num
)},
321 {"mac_rx_total_oct_num",
322 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num
)},
323 {"mac_rx_good_pkt_num",
324 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num
)},
325 {"mac_rx_bad_pkt_num",
326 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num
)},
327 {"mac_rx_good_oct_num",
328 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num
)},
329 {"mac_rx_bad_oct_num",
330 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num
)},
331 {"mac_rx_uni_pkt_num",
332 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num
)},
333 {"mac_rx_multi_pkt_num",
334 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num
)},
335 {"mac_rx_broad_pkt_num",
336 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num
)},
337 {"mac_rx_undersize_pkt_num",
338 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num
)},
339 {"mac_rx_oversize_pkt_num",
340 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num
)},
341 {"mac_rx_64_oct_pkt_num",
342 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num
)},
343 {"mac_rx_65_127_oct_pkt_num",
344 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num
)},
345 {"mac_rx_128_255_oct_pkt_num",
346 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num
)},
347 {"mac_rx_256_511_oct_pkt_num",
348 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num
)},
349 {"mac_rx_512_1023_oct_pkt_num",
350 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num
)},
351 {"mac_rx_1024_1518_oct_pkt_num",
352 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num
)},
353 {"mac_rx_1519_2047_oct_pkt_num",
354 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num
)},
355 {"mac_rx_2048_4095_oct_pkt_num",
356 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num
)},
357 {"mac_rx_4096_8191_oct_pkt_num",
358 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num
)},
359 {"mac_rx_8192_12287_oct_pkt_num",
360 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_12287_oct_pkt_num
)},
361 {"mac_rx_8192_9216_oct_pkt_num",
362 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num
)},
363 {"mac_rx_9217_12287_oct_pkt_num",
364 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num
)},
365 {"mac_rx_12288_16383_oct_pkt_num",
366 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num
)},
367 {"mac_rx_1519_max_good_pkt_num",
368 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num
)},
369 {"mac_rx_1519_max_bad_pkt_num",
370 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num
)},
372 {"mac_tx_fragment_pkt_num",
373 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num
)},
374 {"mac_tx_undermin_pkt_num",
375 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num
)},
376 {"mac_tx_jabber_pkt_num",
377 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num
)},
378 {"mac_tx_err_all_pkt_num",
379 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num
)},
380 {"mac_tx_from_app_good_pkt_num",
381 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num
)},
382 {"mac_tx_from_app_bad_pkt_num",
383 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num
)},
384 {"mac_rx_fragment_pkt_num",
385 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num
)},
386 {"mac_rx_undermin_pkt_num",
387 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num
)},
388 {"mac_rx_jabber_pkt_num",
389 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num
)},
390 {"mac_rx_fcs_err_pkt_num",
391 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num
)},
392 {"mac_rx_send_app_good_pkt_num",
393 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num
)},
394 {"mac_rx_send_app_bad_pkt_num",
395 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num
)}
398 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table
[] = {
400 .flags
= HCLGE_MAC_MGR_MASK_VLAN_B
,
401 .ethter_type
= cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP
),
402 .mac_addr_hi32
= cpu_to_le32(htonl(0x0180C200)),
403 .mac_addr_lo16
= cpu_to_le16(htons(0x000E)),
404 .i_port_bitmap
= 0x1,
408 static int hclge_64_bit_update_stats(struct hclge_dev
*hdev
)
410 #define HCLGE_64_BIT_CMD_NUM 5
411 #define HCLGE_64_BIT_RTN_DATANUM 4
412 u64
*data
= (u64
*)(&hdev
->hw_stats
.all_64_bit_stats
);
413 struct hclge_desc desc
[HCLGE_64_BIT_CMD_NUM
];
418 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_64_BIT
, true);
419 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_64_BIT_CMD_NUM
);
421 dev_err(&hdev
->pdev
->dev
,
422 "Get 64 bit pkt stats fail, status = %d.\n", ret
);
426 for (i
= 0; i
< HCLGE_64_BIT_CMD_NUM
; i
++) {
427 if (unlikely(i
== 0)) {
428 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
429 n
= HCLGE_64_BIT_RTN_DATANUM
- 1;
431 desc_data
= (__le64
*)(&desc
[i
]);
432 n
= HCLGE_64_BIT_RTN_DATANUM
;
434 for (k
= 0; k
< n
; k
++) {
435 *data
++ += le64_to_cpu(*desc_data
);
443 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats
*stats
)
445 stats
->pkt_curr_buf_cnt
= 0;
446 stats
->pkt_curr_buf_tc0_cnt
= 0;
447 stats
->pkt_curr_buf_tc1_cnt
= 0;
448 stats
->pkt_curr_buf_tc2_cnt
= 0;
449 stats
->pkt_curr_buf_tc3_cnt
= 0;
450 stats
->pkt_curr_buf_tc4_cnt
= 0;
451 stats
->pkt_curr_buf_tc5_cnt
= 0;
452 stats
->pkt_curr_buf_tc6_cnt
= 0;
453 stats
->pkt_curr_buf_tc7_cnt
= 0;
456 static int hclge_32_bit_update_stats(struct hclge_dev
*hdev
)
458 #define HCLGE_32_BIT_CMD_NUM 8
459 #define HCLGE_32_BIT_RTN_DATANUM 8
461 struct hclge_desc desc
[HCLGE_32_BIT_CMD_NUM
];
462 struct hclge_32_bit_stats
*all_32_bit_stats
;
468 all_32_bit_stats
= &hdev
->hw_stats
.all_32_bit_stats
;
469 data
= (u64
*)(&all_32_bit_stats
->egu_tx_1588_pkt
);
471 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_32_BIT
, true);
472 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_32_BIT_CMD_NUM
);
474 dev_err(&hdev
->pdev
->dev
,
475 "Get 32 bit pkt stats fail, status = %d.\n", ret
);
480 hclge_reset_partial_32bit_counter(all_32_bit_stats
);
481 for (i
= 0; i
< HCLGE_32_BIT_CMD_NUM
; i
++) {
482 if (unlikely(i
== 0)) {
483 __le16
*desc_data_16bit
;
485 all_32_bit_stats
->igu_rx_err_pkt
+=
486 le32_to_cpu(desc
[i
].data
[0]);
488 desc_data_16bit
= (__le16
*)&desc
[i
].data
[1];
489 all_32_bit_stats
->igu_rx_no_eof_pkt
+=
490 le16_to_cpu(*desc_data_16bit
);
493 all_32_bit_stats
->igu_rx_no_sof_pkt
+=
494 le16_to_cpu(*desc_data_16bit
);
496 desc_data
= &desc
[i
].data
[2];
497 n
= HCLGE_32_BIT_RTN_DATANUM
- 4;
499 desc_data
= (__le32
*)&desc
[i
];
500 n
= HCLGE_32_BIT_RTN_DATANUM
;
502 for (k
= 0; k
< n
; k
++) {
503 *data
++ += le32_to_cpu(*desc_data
);
511 static int hclge_mac_get_traffic_stats(struct hclge_dev
*hdev
)
513 struct hclge_mac_stats
*mac_stats
= &hdev
->hw_stats
.mac_stats
;
514 struct hclge_desc desc
;
518 /* for fiber port, need to query the total rx/tx packets statstics,
519 * used for data transferring checking.
521 if (hdev
->hw
.mac
.media_type
!= HNAE3_MEDIA_TYPE_FIBER
)
524 if (test_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
))
527 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_STATS_MAC_TRAFFIC
, true);
528 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
530 dev_err(&hdev
->pdev
->dev
,
531 "Get MAC total pkt stats fail, ret = %d\n", ret
);
536 desc_data
= (__le64
*)(&desc
.data
[0]);
537 mac_stats
->mac_tx_total_pkt_num
+= le64_to_cpu(*desc_data
++);
538 mac_stats
->mac_rx_total_pkt_num
+= le64_to_cpu(*desc_data
);
543 static int hclge_mac_update_stats(struct hclge_dev
*hdev
)
545 #define HCLGE_MAC_CMD_NUM 21
546 #define HCLGE_RTN_DATA_NUM 4
548 u64
*data
= (u64
*)(&hdev
->hw_stats
.mac_stats
);
549 struct hclge_desc desc
[HCLGE_MAC_CMD_NUM
];
554 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_MAC
, true);
555 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_MAC_CMD_NUM
);
557 dev_err(&hdev
->pdev
->dev
,
558 "Get MAC pkt stats fail, status = %d.\n", ret
);
563 for (i
= 0; i
< HCLGE_MAC_CMD_NUM
; i
++) {
564 if (unlikely(i
== 0)) {
565 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
566 n
= HCLGE_RTN_DATA_NUM
- 2;
568 desc_data
= (__le64
*)(&desc
[i
]);
569 n
= HCLGE_RTN_DATA_NUM
;
571 for (k
= 0; k
< n
; k
++) {
572 *data
++ += le64_to_cpu(*desc_data
);
580 static int hclge_tqps_update_stats(struct hnae3_handle
*handle
)
582 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
583 struct hclge_vport
*vport
= hclge_get_vport(handle
);
584 struct hclge_dev
*hdev
= vport
->back
;
585 struct hnae3_queue
*queue
;
586 struct hclge_desc desc
[1];
587 struct hclge_tqp
*tqp
;
590 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
591 queue
= handle
->kinfo
.tqp
[i
];
592 tqp
= container_of(queue
, struct hclge_tqp
, q
);
593 /* command : HCLGE_OPC_QUERY_IGU_STAT */
594 hclge_cmd_setup_basic_desc(&desc
[0],
595 HCLGE_OPC_QUERY_RX_STATUS
,
598 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
599 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
601 dev_err(&hdev
->pdev
->dev
,
602 "Query tqp stat fail, status = %d,queue = %d\n",
606 tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
+=
607 le32_to_cpu(desc
[0].data
[1]);
610 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
611 queue
= handle
->kinfo
.tqp
[i
];
612 tqp
= container_of(queue
, struct hclge_tqp
, q
);
613 /* command : HCLGE_OPC_QUERY_IGU_STAT */
614 hclge_cmd_setup_basic_desc(&desc
[0],
615 HCLGE_OPC_QUERY_TX_STATUS
,
618 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
619 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
621 dev_err(&hdev
->pdev
->dev
,
622 "Query tqp stat fail, status = %d,queue = %d\n",
626 tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
+=
627 le32_to_cpu(desc
[0].data
[1]);
633 static u64
*hclge_tqps_get_stats(struct hnae3_handle
*handle
, u64
*data
)
635 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
636 struct hclge_tqp
*tqp
;
640 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
641 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
642 *buff
++ = tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
;
645 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
646 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
647 *buff
++ = tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
;
653 static int hclge_tqps_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
655 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
657 return kinfo
->num_tqps
* (2);
660 static u8
*hclge_tqps_get_strings(struct hnae3_handle
*handle
, u8
*data
)
662 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
666 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
667 struct hclge_tqp
*tqp
= container_of(handle
->kinfo
.tqp
[i
],
668 struct hclge_tqp
, q
);
669 snprintf(buff
, ETH_GSTRING_LEN
, "txq#%d_pktnum_rcd",
671 buff
= buff
+ ETH_GSTRING_LEN
;
674 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
675 struct hclge_tqp
*tqp
= container_of(kinfo
->tqp
[i
],
676 struct hclge_tqp
, q
);
677 snprintf(buff
, ETH_GSTRING_LEN
, "rxq#%d_pktnum_rcd",
679 buff
= buff
+ ETH_GSTRING_LEN
;
685 static u64
*hclge_comm_get_stats(void *comm_stats
,
686 const struct hclge_comm_stats_str strs
[],
692 for (i
= 0; i
< size
; i
++)
693 buf
[i
] = HCLGE_STATS_READ(comm_stats
, strs
[i
].offset
);
698 static u8
*hclge_comm_get_strings(u32 stringset
,
699 const struct hclge_comm_stats_str strs
[],
702 char *buff
= (char *)data
;
705 if (stringset
!= ETH_SS_STATS
)
708 for (i
= 0; i
< size
; i
++) {
709 snprintf(buff
, ETH_GSTRING_LEN
,
711 buff
= buff
+ ETH_GSTRING_LEN
;
717 static void hclge_update_netstat(struct hclge_hw_stats
*hw_stats
,
718 struct net_device_stats
*net_stats
)
720 net_stats
->tx_dropped
= 0;
721 net_stats
->rx_dropped
= hw_stats
->all_32_bit_stats
.ssu_full_drop_num
;
722 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ppp_key_drop_num
;
723 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ssu_key_drop_num
;
725 net_stats
->rx_errors
= hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
726 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
727 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_eof_pkt
;
728 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_sof_pkt
;
729 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
731 net_stats
->multicast
= hw_stats
->mac_stats
.mac_tx_multi_pkt_num
;
732 net_stats
->multicast
+= hw_stats
->mac_stats
.mac_rx_multi_pkt_num
;
734 net_stats
->rx_crc_errors
= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
735 net_stats
->rx_length_errors
=
736 hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
737 net_stats
->rx_length_errors
+=
738 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
739 net_stats
->rx_over_errors
=
740 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
743 static void hclge_update_stats_for_all(struct hclge_dev
*hdev
)
745 struct hnae3_handle
*handle
;
748 handle
= &hdev
->vport
[0].nic
;
749 if (handle
->client
) {
750 status
= hclge_tqps_update_stats(handle
);
752 dev_err(&hdev
->pdev
->dev
,
753 "Update TQPS stats fail, status = %d.\n",
758 status
= hclge_mac_update_stats(hdev
);
760 dev_err(&hdev
->pdev
->dev
,
761 "Update MAC stats fail, status = %d.\n", status
);
763 status
= hclge_32_bit_update_stats(hdev
);
765 dev_err(&hdev
->pdev
->dev
,
766 "Update 32 bit stats fail, status = %d.\n",
769 hclge_update_netstat(&hdev
->hw_stats
, &handle
->kinfo
.netdev
->stats
);
772 static void hclge_update_stats(struct hnae3_handle
*handle
,
773 struct net_device_stats
*net_stats
)
775 struct hclge_vport
*vport
= hclge_get_vport(handle
);
776 struct hclge_dev
*hdev
= vport
->back
;
777 struct hclge_hw_stats
*hw_stats
= &hdev
->hw_stats
;
780 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
))
783 status
= hclge_mac_update_stats(hdev
);
785 dev_err(&hdev
->pdev
->dev
,
786 "Update MAC stats fail, status = %d.\n",
789 status
= hclge_32_bit_update_stats(hdev
);
791 dev_err(&hdev
->pdev
->dev
,
792 "Update 32 bit stats fail, status = %d.\n",
795 status
= hclge_64_bit_update_stats(hdev
);
797 dev_err(&hdev
->pdev
->dev
,
798 "Update 64 bit stats fail, status = %d.\n",
801 status
= hclge_tqps_update_stats(handle
);
803 dev_err(&hdev
->pdev
->dev
,
804 "Update TQPS stats fail, status = %d.\n",
807 hclge_update_netstat(hw_stats
, net_stats
);
809 clear_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
);
812 static int hclge_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
814 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
816 struct hclge_vport
*vport
= hclge_get_vport(handle
);
817 struct hclge_dev
*hdev
= vport
->back
;
820 /* Loopback test support rules:
821 * mac: only GE mode support
822 * serdes: all mac mode will support include GE/XGE/LGE/CGE
823 * phy: only support when phy device exist on board
825 if (stringset
== ETH_SS_TEST
) {
826 /* clear loopback bit flags at first */
827 handle
->flags
= (handle
->flags
& (~HCLGE_LOOPBACK_TEST_FLAGS
));
828 if (hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_10M
||
829 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_100M
||
830 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_1G
) {
832 handle
->flags
|= HNAE3_SUPPORT_MAC_LOOPBACK
;
836 } else if (stringset
== ETH_SS_STATS
) {
837 count
= ARRAY_SIZE(g_mac_stats_string
) +
838 ARRAY_SIZE(g_all_32bit_stats_string
) +
839 ARRAY_SIZE(g_all_64bit_stats_string
) +
840 hclge_tqps_get_sset_count(handle
, stringset
);
846 static void hclge_get_strings(struct hnae3_handle
*handle
,
850 u8
*p
= (char *)data
;
853 if (stringset
== ETH_SS_STATS
) {
854 size
= ARRAY_SIZE(g_mac_stats_string
);
855 p
= hclge_comm_get_strings(stringset
,
859 size
= ARRAY_SIZE(g_all_32bit_stats_string
);
860 p
= hclge_comm_get_strings(stringset
,
861 g_all_32bit_stats_string
,
864 size
= ARRAY_SIZE(g_all_64bit_stats_string
);
865 p
= hclge_comm_get_strings(stringset
,
866 g_all_64bit_stats_string
,
869 p
= hclge_tqps_get_strings(handle
, p
);
870 } else if (stringset
== ETH_SS_TEST
) {
871 if (handle
->flags
& HNAE3_SUPPORT_MAC_LOOPBACK
) {
873 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_MAC
],
875 p
+= ETH_GSTRING_LEN
;
877 if (handle
->flags
& HNAE3_SUPPORT_SERDES_LOOPBACK
) {
879 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_SERDES
],
881 p
+= ETH_GSTRING_LEN
;
883 if (handle
->flags
& HNAE3_SUPPORT_PHY_LOOPBACK
) {
885 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_PHY
],
887 p
+= ETH_GSTRING_LEN
;
892 static void hclge_get_stats(struct hnae3_handle
*handle
, u64
*data
)
894 struct hclge_vport
*vport
= hclge_get_vport(handle
);
895 struct hclge_dev
*hdev
= vport
->back
;
898 p
= hclge_comm_get_stats(&hdev
->hw_stats
.mac_stats
,
900 ARRAY_SIZE(g_mac_stats_string
),
902 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_32_bit_stats
,
903 g_all_32bit_stats_string
,
904 ARRAY_SIZE(g_all_32bit_stats_string
),
906 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_64_bit_stats
,
907 g_all_64bit_stats_string
,
908 ARRAY_SIZE(g_all_64bit_stats_string
),
910 p
= hclge_tqps_get_stats(handle
, p
);
913 static int hclge_parse_func_status(struct hclge_dev
*hdev
,
914 struct hclge_func_status_cmd
*status
)
916 if (!(status
->pf_state
& HCLGE_PF_STATE_DONE
))
919 /* Set the pf to main pf */
920 if (status
->pf_state
& HCLGE_PF_STATE_MAIN
)
921 hdev
->flag
|= HCLGE_FLAG_MAIN
;
923 hdev
->flag
&= ~HCLGE_FLAG_MAIN
;
928 static int hclge_query_function_status(struct hclge_dev
*hdev
)
930 struct hclge_func_status_cmd
*req
;
931 struct hclge_desc desc
;
935 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_FUNC_STATUS
, true);
936 req
= (struct hclge_func_status_cmd
*)desc
.data
;
939 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
941 dev_err(&hdev
->pdev
->dev
,
942 "query function status failed %d.\n",
948 /* Check pf reset is done */
951 usleep_range(1000, 2000);
952 } while (timeout
++ < 5);
954 ret
= hclge_parse_func_status(hdev
, req
);
959 static int hclge_query_pf_resource(struct hclge_dev
*hdev
)
961 struct hclge_pf_res_cmd
*req
;
962 struct hclge_desc desc
;
965 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_PF_RSRC
, true);
966 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
968 dev_err(&hdev
->pdev
->dev
,
969 "query pf resource failed %d.\n", ret
);
973 req
= (struct hclge_pf_res_cmd
*)desc
.data
;
974 hdev
->num_tqps
= __le16_to_cpu(req
->tqp_num
);
975 hdev
->pkt_buf_size
= __le16_to_cpu(req
->buf_size
) << HCLGE_BUF_UNIT_S
;
977 if (hnae3_dev_roce_supported(hdev
)) {
979 hnae_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
980 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
982 /* PF should have NIC vectors and Roce vectors,
983 * NIC vectors are queued before Roce vectors.
985 hdev
->num_msi
= hdev
->num_roce_msi
+ HCLGE_ROCE_VECTOR_OFFSET
;
988 hnae_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
989 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
995 static int hclge_parse_speed(int speed_cmd
, int *speed
)
999 *speed
= HCLGE_MAC_SPEED_10M
;
1002 *speed
= HCLGE_MAC_SPEED_100M
;
1005 *speed
= HCLGE_MAC_SPEED_1G
;
1008 *speed
= HCLGE_MAC_SPEED_10G
;
1011 *speed
= HCLGE_MAC_SPEED_25G
;
1014 *speed
= HCLGE_MAC_SPEED_40G
;
1017 *speed
= HCLGE_MAC_SPEED_50G
;
1020 *speed
= HCLGE_MAC_SPEED_100G
;
1029 static void hclge_parse_fiber_link_mode(struct hclge_dev
*hdev
,
1032 unsigned long *supported
= hdev
->hw
.mac
.supported
;
1034 if (speed_ability
& HCLGE_SUPPORT_1G_BIT
)
1035 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT
,
1038 if (speed_ability
& HCLGE_SUPPORT_10G_BIT
)
1039 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT
,
1042 if (speed_ability
& HCLGE_SUPPORT_25G_BIT
)
1043 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT
,
1046 if (speed_ability
& HCLGE_SUPPORT_50G_BIT
)
1047 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT
,
1050 if (speed_ability
& HCLGE_SUPPORT_100G_BIT
)
1051 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT
,
1054 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT
, supported
);
1055 set_bit(ETHTOOL_LINK_MODE_Pause_BIT
, supported
);
1058 static void hclge_parse_link_mode(struct hclge_dev
*hdev
, u8 speed_ability
)
1060 u8 media_type
= hdev
->hw
.mac
.media_type
;
1062 if (media_type
!= HNAE3_MEDIA_TYPE_FIBER
)
1065 hclge_parse_fiber_link_mode(hdev
, speed_ability
);
1068 static void hclge_parse_cfg(struct hclge_cfg
*cfg
, struct hclge_desc
*desc
)
1070 struct hclge_cfg_param_cmd
*req
;
1071 u64 mac_addr_tmp_high
;
1075 req
= (struct hclge_cfg_param_cmd
*)desc
[0].data
;
1077 /* get the configuration */
1078 cfg
->vmdq_vport_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
1081 cfg
->tc_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
1082 HCLGE_CFG_TC_NUM_M
, HCLGE_CFG_TC_NUM_S
);
1083 cfg
->tqp_desc_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
1084 HCLGE_CFG_TQP_DESC_N_M
,
1085 HCLGE_CFG_TQP_DESC_N_S
);
1087 cfg
->phy_addr
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
1088 HCLGE_CFG_PHY_ADDR_M
,
1089 HCLGE_CFG_PHY_ADDR_S
);
1090 cfg
->media_type
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
1091 HCLGE_CFG_MEDIA_TP_M
,
1092 HCLGE_CFG_MEDIA_TP_S
);
1093 cfg
->rx_buf_len
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
1094 HCLGE_CFG_RX_BUF_LEN_M
,
1095 HCLGE_CFG_RX_BUF_LEN_S
);
1096 /* get mac_address */
1097 mac_addr_tmp
= __le32_to_cpu(req
->param
[2]);
1098 mac_addr_tmp_high
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
1099 HCLGE_CFG_MAC_ADDR_H_M
,
1100 HCLGE_CFG_MAC_ADDR_H_S
);
1102 mac_addr_tmp
|= (mac_addr_tmp_high
<< 31) << 1;
1104 cfg
->default_speed
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
1105 HCLGE_CFG_DEFAULT_SPEED_M
,
1106 HCLGE_CFG_DEFAULT_SPEED_S
);
1107 cfg
->rss_size_max
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
1108 HCLGE_CFG_RSS_SIZE_M
,
1109 HCLGE_CFG_RSS_SIZE_S
);
1111 for (i
= 0; i
< ETH_ALEN
; i
++)
1112 cfg
->mac_addr
[i
] = (mac_addr_tmp
>> (8 * i
)) & 0xff;
1114 req
= (struct hclge_cfg_param_cmd
*)desc
[1].data
;
1115 cfg
->numa_node_map
= __le32_to_cpu(req
->param
[0]);
1117 cfg
->speed_ability
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
1118 HCLGE_CFG_SPEED_ABILITY_M
,
1119 HCLGE_CFG_SPEED_ABILITY_S
);
1122 /* hclge_get_cfg: query the static parameter from flash
1123 * @hdev: pointer to struct hclge_dev
1124 * @hcfg: the config structure to be getted
1126 static int hclge_get_cfg(struct hclge_dev
*hdev
, struct hclge_cfg
*hcfg
)
1128 struct hclge_desc desc
[HCLGE_PF_CFG_DESC_NUM
];
1129 struct hclge_cfg_param_cmd
*req
;
1132 for (i
= 0; i
< HCLGE_PF_CFG_DESC_NUM
; i
++) {
1135 req
= (struct hclge_cfg_param_cmd
*)desc
[i
].data
;
1136 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_GET_CFG_PARAM
,
1138 hnae_set_field(offset
, HCLGE_CFG_OFFSET_M
,
1139 HCLGE_CFG_OFFSET_S
, i
* HCLGE_CFG_RD_LEN_BYTES
);
1140 /* Len should be united by 4 bytes when send to hardware */
1141 hnae_set_field(offset
, HCLGE_CFG_RD_LEN_M
, HCLGE_CFG_RD_LEN_S
,
1142 HCLGE_CFG_RD_LEN_BYTES
/ HCLGE_CFG_RD_LEN_UNIT
);
1143 req
->offset
= cpu_to_le32(offset
);
1146 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_PF_CFG_DESC_NUM
);
1148 dev_err(&hdev
->pdev
->dev
,
1149 "get config failed %d.\n", ret
);
1153 hclge_parse_cfg(hcfg
, desc
);
1157 static int hclge_get_cap(struct hclge_dev
*hdev
)
1161 ret
= hclge_query_function_status(hdev
);
1163 dev_err(&hdev
->pdev
->dev
,
1164 "query function status error %d.\n", ret
);
1168 /* get pf resource */
1169 ret
= hclge_query_pf_resource(hdev
);
1171 dev_err(&hdev
->pdev
->dev
,
1172 "query pf resource error %d.\n", ret
);
1179 static int hclge_configure(struct hclge_dev
*hdev
)
1181 struct hclge_cfg cfg
;
1184 ret
= hclge_get_cfg(hdev
, &cfg
);
1186 dev_err(&hdev
->pdev
->dev
, "get mac mode error %d.\n", ret
);
1190 hdev
->num_vmdq_vport
= cfg
.vmdq_vport_num
;
1191 hdev
->base_tqp_pid
= 0;
1192 hdev
->rss_size_max
= cfg
.rss_size_max
;
1193 hdev
->rx_buf_len
= cfg
.rx_buf_len
;
1194 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, cfg
.mac_addr
);
1195 hdev
->hw
.mac
.media_type
= cfg
.media_type
;
1196 hdev
->hw
.mac
.phy_addr
= cfg
.phy_addr
;
1197 hdev
->num_desc
= cfg
.tqp_desc_num
;
1198 hdev
->tm_info
.num_pg
= 1;
1199 hdev
->tc_max
= cfg
.tc_num
;
1200 hdev
->tm_info
.hw_pfc_map
= 0;
1202 ret
= hclge_parse_speed(cfg
.default_speed
, &hdev
->hw
.mac
.speed
);
1204 dev_err(&hdev
->pdev
->dev
, "Get wrong speed ret=%d.\n", ret
);
1208 hclge_parse_link_mode(hdev
, cfg
.speed_ability
);
1210 if ((hdev
->tc_max
> HNAE3_MAX_TC
) ||
1211 (hdev
->tc_max
< 1)) {
1212 dev_warn(&hdev
->pdev
->dev
, "TC num = %d.\n",
1217 /* Dev does not support DCB */
1218 if (!hnae3_dev_dcb_supported(hdev
)) {
1222 hdev
->pfc_max
= hdev
->tc_max
;
1225 hdev
->tm_info
.num_tc
= hdev
->tc_max
;
1227 /* Currently not support uncontiuous tc */
1228 for (i
= 0; i
< hdev
->tm_info
.num_tc
; i
++)
1229 hnae_set_bit(hdev
->hw_tc_map
, i
, 1);
1231 hdev
->tx_sch_mode
= HCLGE_FLAG_TC_BASE_SCH_MODE
;
1236 static int hclge_config_tso(struct hclge_dev
*hdev
, int tso_mss_min
,
1239 struct hclge_cfg_tso_status_cmd
*req
;
1240 struct hclge_desc desc
;
1243 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TSO_GENERIC_CONFIG
, false);
1245 req
= (struct hclge_cfg_tso_status_cmd
*)desc
.data
;
1248 hnae_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1249 HCLGE_TSO_MSS_MIN_S
, tso_mss_min
);
1250 req
->tso_mss_min
= cpu_to_le16(tso_mss
);
1253 hnae_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1254 HCLGE_TSO_MSS_MIN_S
, tso_mss_max
);
1255 req
->tso_mss_max
= cpu_to_le16(tso_mss
);
1257 return hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1260 static int hclge_alloc_tqps(struct hclge_dev
*hdev
)
1262 struct hclge_tqp
*tqp
;
1265 hdev
->htqp
= devm_kcalloc(&hdev
->pdev
->dev
, hdev
->num_tqps
,
1266 sizeof(struct hclge_tqp
), GFP_KERNEL
);
1272 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
1273 tqp
->dev
= &hdev
->pdev
->dev
;
1276 tqp
->q
.ae_algo
= &ae_algo
;
1277 tqp
->q
.buf_size
= hdev
->rx_buf_len
;
1278 tqp
->q
.desc_num
= hdev
->num_desc
;
1279 tqp
->q
.io_base
= hdev
->hw
.io_base
+ HCLGE_TQP_REG_OFFSET
+
1280 i
* HCLGE_TQP_REG_SIZE
;
1288 static int hclge_map_tqps_to_func(struct hclge_dev
*hdev
, u16 func_id
,
1289 u16 tqp_pid
, u16 tqp_vid
, bool is_pf
)
1291 struct hclge_tqp_map_cmd
*req
;
1292 struct hclge_desc desc
;
1295 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SET_TQP_MAP
, false);
1297 req
= (struct hclge_tqp_map_cmd
*)desc
.data
;
1298 req
->tqp_id
= cpu_to_le16(tqp_pid
);
1299 req
->tqp_vf
= func_id
;
1300 req
->tqp_flag
= !is_pf
<< HCLGE_TQP_MAP_TYPE_B
|
1301 1 << HCLGE_TQP_MAP_EN_B
;
1302 req
->tqp_vid
= cpu_to_le16(tqp_vid
);
1304 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1306 dev_err(&hdev
->pdev
->dev
, "TQP map failed %d.\n",
1314 static int hclge_assign_tqp(struct hclge_vport
*vport
,
1315 struct hnae3_queue
**tqp
, u16 num_tqps
)
1317 struct hclge_dev
*hdev
= vport
->back
;
1320 for (i
= 0, alloced
= 0; i
< hdev
->num_tqps
&&
1321 alloced
< num_tqps
; i
++) {
1322 if (!hdev
->htqp
[i
].alloced
) {
1323 hdev
->htqp
[i
].q
.handle
= &vport
->nic
;
1324 hdev
->htqp
[i
].q
.tqp_index
= alloced
;
1325 tqp
[alloced
] = &hdev
->htqp
[i
].q
;
1326 hdev
->htqp
[i
].alloced
= true;
1330 vport
->alloc_tqps
= num_tqps
;
1335 static int hclge_knic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1337 struct hnae3_handle
*nic
= &vport
->nic
;
1338 struct hnae3_knic_private_info
*kinfo
= &nic
->kinfo
;
1339 struct hclge_dev
*hdev
= vport
->back
;
1342 kinfo
->num_desc
= hdev
->num_desc
;
1343 kinfo
->rx_buf_len
= hdev
->rx_buf_len
;
1344 kinfo
->num_tc
= min_t(u16
, num_tqps
, hdev
->tm_info
.num_tc
);
1346 = min_t(u16
, hdev
->rss_size_max
, num_tqps
/ kinfo
->num_tc
);
1347 kinfo
->num_tqps
= kinfo
->rss_size
* kinfo
->num_tc
;
1349 for (i
= 0; i
< HNAE3_MAX_TC
; i
++) {
1350 if (hdev
->hw_tc_map
& BIT(i
)) {
1351 kinfo
->tc_info
[i
].enable
= true;
1352 kinfo
->tc_info
[i
].tqp_offset
= i
* kinfo
->rss_size
;
1353 kinfo
->tc_info
[i
].tqp_count
= kinfo
->rss_size
;
1354 kinfo
->tc_info
[i
].tc
= i
;
1356 /* Set to default queue if TC is disable */
1357 kinfo
->tc_info
[i
].enable
= false;
1358 kinfo
->tc_info
[i
].tqp_offset
= 0;
1359 kinfo
->tc_info
[i
].tqp_count
= 1;
1360 kinfo
->tc_info
[i
].tc
= 0;
1364 kinfo
->tqp
= devm_kcalloc(&hdev
->pdev
->dev
, kinfo
->num_tqps
,
1365 sizeof(struct hnae3_queue
*), GFP_KERNEL
);
1369 ret
= hclge_assign_tqp(vport
, kinfo
->tqp
, kinfo
->num_tqps
);
1371 dev_err(&hdev
->pdev
->dev
, "fail to assign TQPs %d.\n", ret
);
1378 static int hclge_map_tqp_to_vport(struct hclge_dev
*hdev
,
1379 struct hclge_vport
*vport
)
1381 struct hnae3_handle
*nic
= &vport
->nic
;
1382 struct hnae3_knic_private_info
*kinfo
;
1385 kinfo
= &nic
->kinfo
;
1386 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
1387 struct hclge_tqp
*q
=
1388 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
1392 is_pf
= !(vport
->vport_id
);
1393 ret
= hclge_map_tqps_to_func(hdev
, vport
->vport_id
, q
->index
,
1402 static int hclge_map_tqp(struct hclge_dev
*hdev
)
1404 struct hclge_vport
*vport
= hdev
->vport
;
1407 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1408 for (i
= 0; i
< num_vport
; i
++) {
1411 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
1421 static void hclge_unic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1423 /* this would be initialized later */
1426 static int hclge_vport_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1428 struct hnae3_handle
*nic
= &vport
->nic
;
1429 struct hclge_dev
*hdev
= vport
->back
;
1432 nic
->pdev
= hdev
->pdev
;
1433 nic
->ae_algo
= &ae_algo
;
1434 nic
->numa_node_mask
= hdev
->numa_node_mask
;
1436 if (hdev
->ae_dev
->dev_type
== HNAE3_DEV_KNIC
) {
1437 ret
= hclge_knic_setup(vport
, num_tqps
);
1439 dev_err(&hdev
->pdev
->dev
, "knic setup failed %d\n",
1444 hclge_unic_setup(vport
, num_tqps
);
1450 static int hclge_alloc_vport(struct hclge_dev
*hdev
)
1452 struct pci_dev
*pdev
= hdev
->pdev
;
1453 struct hclge_vport
*vport
;
1459 /* We need to alloc a vport for main NIC of PF */
1460 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1462 if (hdev
->num_tqps
< num_vport
) {
1463 dev_err(&hdev
->pdev
->dev
, "tqps(%d) is less than vports(%d)",
1464 hdev
->num_tqps
, num_vport
);
1468 /* Alloc the same number of TQPs for every vport */
1469 tqp_per_vport
= hdev
->num_tqps
/ num_vport
;
1470 tqp_main_vport
= tqp_per_vport
+ hdev
->num_tqps
% num_vport
;
1472 vport
= devm_kcalloc(&pdev
->dev
, num_vport
, sizeof(struct hclge_vport
),
1477 hdev
->vport
= vport
;
1478 hdev
->num_alloc_vport
= num_vport
;
1480 #ifdef CONFIG_PCI_IOV
1482 if (hdev
->num_req_vfs
) {
1483 dev_info(&pdev
->dev
, "active VFs(%d) found, enabling SRIOV\n",
1485 ret
= pci_enable_sriov(hdev
->pdev
, hdev
->num_req_vfs
);
1487 hdev
->num_alloc_vfs
= 0;
1488 dev_err(&pdev
->dev
, "SRIOV enable failed %d\n",
1493 hdev
->num_alloc_vfs
= hdev
->num_req_vfs
;
1496 for (i
= 0; i
< num_vport
; i
++) {
1498 vport
->vport_id
= i
;
1501 ret
= hclge_vport_setup(vport
, tqp_main_vport
);
1503 ret
= hclge_vport_setup(vport
, tqp_per_vport
);
1506 "vport setup failed for vport %d, %d\n",
1517 static int hclge_cmd_alloc_tx_buff(struct hclge_dev
*hdev
,
1518 struct hclge_pkt_buf_alloc
*buf_alloc
)
1520 /* TX buffer size is unit by 128 byte */
1521 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1522 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1523 struct hclge_tx_buff_alloc_cmd
*req
;
1524 struct hclge_desc desc
;
1528 req
= (struct hclge_tx_buff_alloc_cmd
*)desc
.data
;
1530 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TX_BUFF_ALLOC
, 0);
1531 for (i
= 0; i
< HCLGE_TC_NUM
; i
++) {
1532 u32 buf_size
= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1534 req
->tx_pkt_buff
[i
] =
1535 cpu_to_le16((buf_size
>> HCLGE_BUF_SIZE_UNIT_SHIFT
) |
1536 HCLGE_BUF_SIZE_UPDATE_EN_MSK
);
1539 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1541 dev_err(&hdev
->pdev
->dev
, "tx buffer alloc cmd failed %d.\n",
1549 static int hclge_tx_buffer_alloc(struct hclge_dev
*hdev
,
1550 struct hclge_pkt_buf_alloc
*buf_alloc
)
1552 int ret
= hclge_cmd_alloc_tx_buff(hdev
, buf_alloc
);
1555 dev_err(&hdev
->pdev
->dev
,
1556 "tx buffer alloc failed %d\n", ret
);
1563 static int hclge_get_tc_num(struct hclge_dev
*hdev
)
1567 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1568 if (hdev
->hw_tc_map
& BIT(i
))
1573 static int hclge_get_pfc_enalbe_num(struct hclge_dev
*hdev
)
1577 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1578 if (hdev
->hw_tc_map
& BIT(i
) &&
1579 hdev
->tm_info
.hw_pfc_map
& BIT(i
))
1584 /* Get the number of pfc enabled TCs, which have private buffer */
1585 static int hclge_get_pfc_priv_num(struct hclge_dev
*hdev
,
1586 struct hclge_pkt_buf_alloc
*buf_alloc
)
1588 struct hclge_priv_buf
*priv
;
1591 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1592 priv
= &buf_alloc
->priv_buf
[i
];
1593 if ((hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1601 /* Get the number of pfc disabled TCs, which have private buffer */
1602 static int hclge_get_no_pfc_priv_num(struct hclge_dev
*hdev
,
1603 struct hclge_pkt_buf_alloc
*buf_alloc
)
1605 struct hclge_priv_buf
*priv
;
1608 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1609 priv
= &buf_alloc
->priv_buf
[i
];
1610 if (hdev
->hw_tc_map
& BIT(i
) &&
1611 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1619 static u32
hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1621 struct hclge_priv_buf
*priv
;
1625 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1626 priv
= &buf_alloc
->priv_buf
[i
];
1628 rx_priv
+= priv
->buf_size
;
1633 static u32
hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1635 u32 i
, total_tx_size
= 0;
1637 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1638 total_tx_size
+= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1640 return total_tx_size
;
1643 static bool hclge_is_rx_buf_ok(struct hclge_dev
*hdev
,
1644 struct hclge_pkt_buf_alloc
*buf_alloc
,
1647 u32 shared_buf_min
, shared_buf_tc
, shared_std
;
1648 int tc_num
, pfc_enable_num
;
1653 tc_num
= hclge_get_tc_num(hdev
);
1654 pfc_enable_num
= hclge_get_pfc_enalbe_num(hdev
);
1656 if (hnae3_dev_dcb_supported(hdev
))
1657 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_DV
;
1659 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_NON_DCB_DV
;
1661 shared_buf_tc
= pfc_enable_num
* hdev
->mps
+
1662 (tc_num
- pfc_enable_num
) * hdev
->mps
/ 2 +
1664 shared_std
= max_t(u32
, shared_buf_min
, shared_buf_tc
);
1666 rx_priv
= hclge_get_rx_priv_buff_alloced(buf_alloc
);
1667 if (rx_all
<= rx_priv
+ shared_std
)
1670 shared_buf
= rx_all
- rx_priv
;
1671 buf_alloc
->s_buf
.buf_size
= shared_buf
;
1672 buf_alloc
->s_buf
.self
.high
= shared_buf
;
1673 buf_alloc
->s_buf
.self
.low
= 2 * hdev
->mps
;
1675 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1676 if ((hdev
->hw_tc_map
& BIT(i
)) &&
1677 (hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1678 buf_alloc
->s_buf
.tc_thrd
[i
].low
= hdev
->mps
;
1679 buf_alloc
->s_buf
.tc_thrd
[i
].high
= 2 * hdev
->mps
;
1681 buf_alloc
->s_buf
.tc_thrd
[i
].low
= 0;
1682 buf_alloc
->s_buf
.tc_thrd
[i
].high
= hdev
->mps
;
1689 static int hclge_tx_buffer_calc(struct hclge_dev
*hdev
,
1690 struct hclge_pkt_buf_alloc
*buf_alloc
)
1694 total_size
= hdev
->pkt_buf_size
;
1696 /* alloc tx buffer for all enabled tc */
1697 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1698 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1700 if (total_size
< HCLGE_DEFAULT_TX_BUF
)
1703 if (hdev
->hw_tc_map
& BIT(i
))
1704 priv
->tx_buf_size
= HCLGE_DEFAULT_TX_BUF
;
1706 priv
->tx_buf_size
= 0;
1708 total_size
-= priv
->tx_buf_size
;
1714 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1715 * @hdev: pointer to struct hclge_dev
1716 * @buf_alloc: pointer to buffer calculation data
1717 * @return: 0: calculate sucessful, negative: fail
1719 static int hclge_rx_buffer_calc(struct hclge_dev
*hdev
,
1720 struct hclge_pkt_buf_alloc
*buf_alloc
)
1722 u32 rx_all
= hdev
->pkt_buf_size
;
1723 int no_pfc_priv_num
, pfc_priv_num
;
1724 struct hclge_priv_buf
*priv
;
1727 rx_all
-= hclge_get_tx_buff_alloced(buf_alloc
);
1729 /* When DCB is not supported, rx private
1730 * buffer is not allocated.
1732 if (!hnae3_dev_dcb_supported(hdev
)) {
1733 if (!hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1739 /* step 1, try to alloc private buffer for all enabled tc */
1740 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1741 priv
= &buf_alloc
->priv_buf
[i
];
1742 if (hdev
->hw_tc_map
& BIT(i
)) {
1744 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1745 priv
->wl
.low
= hdev
->mps
;
1746 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1747 priv
->buf_size
= priv
->wl
.high
+
1751 priv
->wl
.high
= 2 * hdev
->mps
;
1752 priv
->buf_size
= priv
->wl
.high
;
1762 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1765 /* step 2, try to decrease the buffer size of
1766 * no pfc TC's private buffer
1768 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1769 priv
= &buf_alloc
->priv_buf
[i
];
1776 if (!(hdev
->hw_tc_map
& BIT(i
)))
1781 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1783 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1784 priv
->buf_size
= priv
->wl
.high
+ HCLGE_DEFAULT_DV
;
1787 priv
->wl
.high
= hdev
->mps
;
1788 priv
->buf_size
= priv
->wl
.high
;
1792 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1795 /* step 3, try to reduce the number of pfc disabled TCs,
1796 * which have private buffer
1798 /* get the total no pfc enable TC number, which have private buffer */
1799 no_pfc_priv_num
= hclge_get_no_pfc_priv_num(hdev
, buf_alloc
);
1801 /* let the last to be cleared first */
1802 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1803 priv
= &buf_alloc
->priv_buf
[i
];
1805 if (hdev
->hw_tc_map
& BIT(i
) &&
1806 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1807 /* Clear the no pfc TC private buffer */
1815 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1816 no_pfc_priv_num
== 0)
1820 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1823 /* step 4, try to reduce the number of pfc enabled TCs
1824 * which have private buffer.
1826 pfc_priv_num
= hclge_get_pfc_priv_num(hdev
, buf_alloc
);
1828 /* let the last to be cleared first */
1829 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1830 priv
= &buf_alloc
->priv_buf
[i
];
1832 if (hdev
->hw_tc_map
& BIT(i
) &&
1833 hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1834 /* Reduce the number of pfc TC with private buffer */
1842 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1846 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1852 static int hclge_rx_priv_buf_alloc(struct hclge_dev
*hdev
,
1853 struct hclge_pkt_buf_alloc
*buf_alloc
)
1855 struct hclge_rx_priv_buff_cmd
*req
;
1856 struct hclge_desc desc
;
1860 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_PRIV_BUFF_ALLOC
, false);
1861 req
= (struct hclge_rx_priv_buff_cmd
*)desc
.data
;
1863 /* Alloc private buffer TCs */
1864 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1865 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1868 cpu_to_le16(priv
->buf_size
>> HCLGE_BUF_UNIT_S
);
1870 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B
);
1874 cpu_to_le16((buf_alloc
->s_buf
.buf_size
>> HCLGE_BUF_UNIT_S
) |
1875 (1 << HCLGE_TC0_PRI_BUF_EN_B
));
1877 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1879 dev_err(&hdev
->pdev
->dev
,
1880 "rx private buffer alloc cmd failed %d\n", ret
);
1887 #define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1889 static int hclge_rx_priv_wl_config(struct hclge_dev
*hdev
,
1890 struct hclge_pkt_buf_alloc
*buf_alloc
)
1892 struct hclge_rx_priv_wl_buf
*req
;
1893 struct hclge_priv_buf
*priv
;
1894 struct hclge_desc desc
[2];
1898 for (i
= 0; i
< 2; i
++) {
1899 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_RX_PRIV_WL_ALLOC
,
1901 req
= (struct hclge_rx_priv_wl_buf
*)desc
[i
].data
;
1903 /* The first descriptor set the NEXT bit to 1 */
1905 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1907 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1909 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1910 u32 idx
= i
* HCLGE_TC_NUM_ONE_DESC
+ j
;
1912 priv
= &buf_alloc
->priv_buf
[idx
];
1913 req
->tc_wl
[j
].high
=
1914 cpu_to_le16(priv
->wl
.high
>> HCLGE_BUF_UNIT_S
);
1915 req
->tc_wl
[j
].high
|=
1916 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.high
) <<
1917 HCLGE_RX_PRIV_EN_B
);
1919 cpu_to_le16(priv
->wl
.low
>> HCLGE_BUF_UNIT_S
);
1920 req
->tc_wl
[j
].low
|=
1921 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.low
) <<
1922 HCLGE_RX_PRIV_EN_B
);
1926 /* Send 2 descriptor at one time */
1927 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1929 dev_err(&hdev
->pdev
->dev
,
1930 "rx private waterline config cmd failed %d\n",
1937 static int hclge_common_thrd_config(struct hclge_dev
*hdev
,
1938 struct hclge_pkt_buf_alloc
*buf_alloc
)
1940 struct hclge_shared_buf
*s_buf
= &buf_alloc
->s_buf
;
1941 struct hclge_rx_com_thrd
*req
;
1942 struct hclge_desc desc
[2];
1943 struct hclge_tc_thrd
*tc
;
1947 for (i
= 0; i
< 2; i
++) {
1948 hclge_cmd_setup_basic_desc(&desc
[i
],
1949 HCLGE_OPC_RX_COM_THRD_ALLOC
, false);
1950 req
= (struct hclge_rx_com_thrd
*)&desc
[i
].data
;
1952 /* The first descriptor set the NEXT bit to 1 */
1954 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1956 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1958 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1959 tc
= &s_buf
->tc_thrd
[i
* HCLGE_TC_NUM_ONE_DESC
+ j
];
1961 req
->com_thrd
[j
].high
=
1962 cpu_to_le16(tc
->high
>> HCLGE_BUF_UNIT_S
);
1963 req
->com_thrd
[j
].high
|=
1964 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->high
) <<
1965 HCLGE_RX_PRIV_EN_B
);
1966 req
->com_thrd
[j
].low
=
1967 cpu_to_le16(tc
->low
>> HCLGE_BUF_UNIT_S
);
1968 req
->com_thrd
[j
].low
|=
1969 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->low
) <<
1970 HCLGE_RX_PRIV_EN_B
);
1974 /* Send 2 descriptors at one time */
1975 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1977 dev_err(&hdev
->pdev
->dev
,
1978 "common threshold config cmd failed %d\n", ret
);
1984 static int hclge_common_wl_config(struct hclge_dev
*hdev
,
1985 struct hclge_pkt_buf_alloc
*buf_alloc
)
1987 struct hclge_shared_buf
*buf
= &buf_alloc
->s_buf
;
1988 struct hclge_rx_com_wl
*req
;
1989 struct hclge_desc desc
;
1992 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_COM_WL_ALLOC
, false);
1994 req
= (struct hclge_rx_com_wl
*)desc
.data
;
1995 req
->com_wl
.high
= cpu_to_le16(buf
->self
.high
>> HCLGE_BUF_UNIT_S
);
1997 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.high
) <<
1998 HCLGE_RX_PRIV_EN_B
);
2000 req
->com_wl
.low
= cpu_to_le16(buf
->self
.low
>> HCLGE_BUF_UNIT_S
);
2002 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.low
) <<
2003 HCLGE_RX_PRIV_EN_B
);
2005 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2007 dev_err(&hdev
->pdev
->dev
,
2008 "common waterline config cmd failed %d\n", ret
);
2015 int hclge_buffer_alloc(struct hclge_dev
*hdev
)
2017 struct hclge_pkt_buf_alloc
*pkt_buf
;
2020 pkt_buf
= kzalloc(sizeof(*pkt_buf
), GFP_KERNEL
);
2024 ret
= hclge_tx_buffer_calc(hdev
, pkt_buf
);
2026 dev_err(&hdev
->pdev
->dev
,
2027 "could not calc tx buffer size for all TCs %d\n", ret
);
2031 ret
= hclge_tx_buffer_alloc(hdev
, pkt_buf
);
2033 dev_err(&hdev
->pdev
->dev
,
2034 "could not alloc tx buffers %d\n", ret
);
2038 ret
= hclge_rx_buffer_calc(hdev
, pkt_buf
);
2040 dev_err(&hdev
->pdev
->dev
,
2041 "could not calc rx priv buffer size for all TCs %d\n",
2046 ret
= hclge_rx_priv_buf_alloc(hdev
, pkt_buf
);
2048 dev_err(&hdev
->pdev
->dev
, "could not alloc rx priv buffer %d\n",
2053 if (hnae3_dev_dcb_supported(hdev
)) {
2054 ret
= hclge_rx_priv_wl_config(hdev
, pkt_buf
);
2056 dev_err(&hdev
->pdev
->dev
,
2057 "could not configure rx private waterline %d\n",
2062 ret
= hclge_common_thrd_config(hdev
, pkt_buf
);
2064 dev_err(&hdev
->pdev
->dev
,
2065 "could not configure common threshold %d\n",
2071 ret
= hclge_common_wl_config(hdev
, pkt_buf
);
2073 dev_err(&hdev
->pdev
->dev
,
2074 "could not configure common waterline %d\n", ret
);
2081 static int hclge_init_roce_base_info(struct hclge_vport
*vport
)
2083 struct hnae3_handle
*roce
= &vport
->roce
;
2084 struct hnae3_handle
*nic
= &vport
->nic
;
2086 roce
->rinfo
.num_vectors
= vport
->back
->num_roce_msi
;
2088 if (vport
->back
->num_msi_left
< vport
->roce
.rinfo
.num_vectors
||
2089 vport
->back
->num_msi_left
== 0)
2092 roce
->rinfo
.base_vector
= vport
->back
->roce_base_vector
;
2094 roce
->rinfo
.netdev
= nic
->kinfo
.netdev
;
2095 roce
->rinfo
.roce_io_base
= vport
->back
->hw
.io_base
;
2097 roce
->pdev
= nic
->pdev
;
2098 roce
->ae_algo
= nic
->ae_algo
;
2099 roce
->numa_node_mask
= nic
->numa_node_mask
;
2104 static int hclge_init_msi(struct hclge_dev
*hdev
)
2106 struct pci_dev
*pdev
= hdev
->pdev
;
2110 vectors
= pci_alloc_irq_vectors(pdev
, 1, hdev
->num_msi
,
2111 PCI_IRQ_MSI
| PCI_IRQ_MSIX
);
2114 "failed(%d) to allocate MSI/MSI-X vectors\n",
2118 if (vectors
< hdev
->num_msi
)
2119 dev_warn(&hdev
->pdev
->dev
,
2120 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2121 hdev
->num_msi
, vectors
);
2123 hdev
->num_msi
= vectors
;
2124 hdev
->num_msi_left
= vectors
;
2125 hdev
->base_msi_vector
= pdev
->irq
;
2126 hdev
->roce_base_vector
= hdev
->base_msi_vector
+
2127 HCLGE_ROCE_VECTOR_OFFSET
;
2129 hdev
->vector_status
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2130 sizeof(u16
), GFP_KERNEL
);
2131 if (!hdev
->vector_status
) {
2132 pci_free_irq_vectors(pdev
);
2136 for (i
= 0; i
< hdev
->num_msi
; i
++)
2137 hdev
->vector_status
[i
] = HCLGE_INVALID_VPORT
;
2139 hdev
->vector_irq
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2140 sizeof(int), GFP_KERNEL
);
2141 if (!hdev
->vector_irq
) {
2142 pci_free_irq_vectors(pdev
);
2149 static void hclge_check_speed_dup(struct hclge_dev
*hdev
, int duplex
, int speed
)
2151 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2153 if ((speed
== HCLGE_MAC_SPEED_10M
) || (speed
== HCLGE_MAC_SPEED_100M
))
2154 mac
->duplex
= (u8
)duplex
;
2156 mac
->duplex
= HCLGE_MAC_FULL
;
2161 int hclge_cfg_mac_speed_dup(struct hclge_dev
*hdev
, int speed
, u8 duplex
)
2163 struct hclge_config_mac_speed_dup_cmd
*req
;
2164 struct hclge_desc desc
;
2167 req
= (struct hclge_config_mac_speed_dup_cmd
*)desc
.data
;
2169 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_SPEED_DUP
, false);
2171 hnae_set_bit(req
->speed_dup
, HCLGE_CFG_DUPLEX_B
, !!duplex
);
2174 case HCLGE_MAC_SPEED_10M
:
2175 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2176 HCLGE_CFG_SPEED_S
, 6);
2178 case HCLGE_MAC_SPEED_100M
:
2179 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2180 HCLGE_CFG_SPEED_S
, 7);
2182 case HCLGE_MAC_SPEED_1G
:
2183 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2184 HCLGE_CFG_SPEED_S
, 0);
2186 case HCLGE_MAC_SPEED_10G
:
2187 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2188 HCLGE_CFG_SPEED_S
, 1);
2190 case HCLGE_MAC_SPEED_25G
:
2191 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2192 HCLGE_CFG_SPEED_S
, 2);
2194 case HCLGE_MAC_SPEED_40G
:
2195 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2196 HCLGE_CFG_SPEED_S
, 3);
2198 case HCLGE_MAC_SPEED_50G
:
2199 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2200 HCLGE_CFG_SPEED_S
, 4);
2202 case HCLGE_MAC_SPEED_100G
:
2203 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2204 HCLGE_CFG_SPEED_S
, 5);
2207 dev_err(&hdev
->pdev
->dev
, "invalid speed (%d)\n", speed
);
2211 hnae_set_bit(req
->mac_change_fec_en
, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B
,
2214 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2216 dev_err(&hdev
->pdev
->dev
,
2217 "mac speed/duplex config cmd failed %d.\n", ret
);
2221 hclge_check_speed_dup(hdev
, duplex
, speed
);
2226 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle
*handle
, int speed
,
2229 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2230 struct hclge_dev
*hdev
= vport
->back
;
2232 return hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2235 static int hclge_query_mac_an_speed_dup(struct hclge_dev
*hdev
, int *speed
,
2238 struct hclge_query_an_speed_dup_cmd
*req
;
2239 struct hclge_desc desc
;
2243 req
= (struct hclge_query_an_speed_dup_cmd
*)desc
.data
;
2245 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_AN_RESULT
, true);
2246 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2248 dev_err(&hdev
->pdev
->dev
,
2249 "mac speed/autoneg/duplex query cmd failed %d\n",
2254 *duplex
= hnae_get_bit(req
->an_syn_dup_speed
, HCLGE_QUERY_DUPLEX_B
);
2255 speed_tmp
= hnae_get_field(req
->an_syn_dup_speed
, HCLGE_QUERY_SPEED_M
,
2256 HCLGE_QUERY_SPEED_S
);
2258 ret
= hclge_parse_speed(speed_tmp
, speed
);
2260 dev_err(&hdev
->pdev
->dev
,
2261 "could not parse speed(=%d), %d\n", speed_tmp
, ret
);
2268 static int hclge_set_autoneg_en(struct hclge_dev
*hdev
, bool enable
)
2270 struct hclge_config_auto_neg_cmd
*req
;
2271 struct hclge_desc desc
;
2275 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_AN_MODE
, false);
2277 req
= (struct hclge_config_auto_neg_cmd
*)desc
.data
;
2278 hnae_set_bit(flag
, HCLGE_MAC_CFG_AN_EN_B
, !!enable
);
2279 req
->cfg_an_cmd_flag
= cpu_to_le32(flag
);
2281 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2283 dev_err(&hdev
->pdev
->dev
, "auto neg set cmd failed %d.\n",
2291 static int hclge_set_autoneg(struct hnae3_handle
*handle
, bool enable
)
2293 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2294 struct hclge_dev
*hdev
= vport
->back
;
2296 return hclge_set_autoneg_en(hdev
, enable
);
2299 static int hclge_get_autoneg(struct hnae3_handle
*handle
)
2301 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2302 struct hclge_dev
*hdev
= vport
->back
;
2303 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
2306 return phydev
->autoneg
;
2308 return hdev
->hw
.mac
.autoneg
;
2311 static int hclge_set_default_mac_vlan_mask(struct hclge_dev
*hdev
,
2315 struct hclge_mac_vlan_mask_entry_cmd
*req
;
2316 struct hclge_desc desc
;
2319 req
= (struct hclge_mac_vlan_mask_entry_cmd
*)desc
.data
;
2320 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_MASK_SET
, false);
2322 hnae_set_bit(req
->vlan_mask
, HCLGE_VLAN_MASK_EN_B
,
2324 ether_addr_copy(req
->mac_mask
, mac_mask
);
2326 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2328 dev_err(&hdev
->pdev
->dev
,
2329 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2335 static int hclge_mac_init(struct hclge_dev
*hdev
)
2337 struct hnae3_handle
*handle
= &hdev
->vport
[0].nic
;
2338 struct net_device
*netdev
= handle
->kinfo
.netdev
;
2339 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2340 u8 mac_mask
[ETH_ALEN
] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
2344 ret
= hclge_cfg_mac_speed_dup(hdev
, hdev
->hw
.mac
.speed
, HCLGE_MAC_FULL
);
2346 dev_err(&hdev
->pdev
->dev
,
2347 "Config mac speed dup fail ret=%d\n", ret
);
2353 /* Initialize the MTA table work mode */
2354 hdev
->accept_mta_mc
= true;
2355 hdev
->enable_mta
= true;
2356 hdev
->mta_mac_sel_type
= HCLGE_MAC_ADDR_47_36
;
2358 ret
= hclge_set_mta_filter_mode(hdev
,
2359 hdev
->mta_mac_sel_type
,
2362 dev_err(&hdev
->pdev
->dev
, "set mta filter mode failed %d\n",
2367 ret
= hclge_cfg_func_mta_filter(hdev
, 0, hdev
->accept_mta_mc
);
2369 dev_err(&hdev
->pdev
->dev
,
2370 "set mta filter mode fail ret=%d\n", ret
);
2374 ret
= hclge_set_default_mac_vlan_mask(hdev
, true, mac_mask
);
2376 dev_err(&hdev
->pdev
->dev
,
2377 "set default mac_vlan_mask fail ret=%d\n", ret
);
2386 ret
= hclge_set_mtu(handle
, mtu
);
2388 dev_err(&hdev
->pdev
->dev
,
2389 "set mtu failed ret=%d\n", ret
);
2396 static void hclge_mbx_task_schedule(struct hclge_dev
*hdev
)
2398 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
))
2399 schedule_work(&hdev
->mbx_service_task
);
2402 static void hclge_reset_task_schedule(struct hclge_dev
*hdev
)
2404 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
))
2405 schedule_work(&hdev
->rst_service_task
);
2408 static void hclge_task_schedule(struct hclge_dev
*hdev
)
2410 if (!test_bit(HCLGE_STATE_DOWN
, &hdev
->state
) &&
2411 !test_bit(HCLGE_STATE_REMOVING
, &hdev
->state
) &&
2412 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
))
2413 (void)schedule_work(&hdev
->service_task
);
2416 static int hclge_get_mac_link_status(struct hclge_dev
*hdev
)
2418 struct hclge_link_status_cmd
*req
;
2419 struct hclge_desc desc
;
2423 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_LINK_STATUS
, true);
2424 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2426 dev_err(&hdev
->pdev
->dev
, "get link status cmd failed %d\n",
2431 req
= (struct hclge_link_status_cmd
*)desc
.data
;
2432 link_status
= req
->status
& HCLGE_LINK_STATUS
;
2434 return !!link_status
;
2437 static int hclge_get_mac_phy_link(struct hclge_dev
*hdev
)
2442 mac_state
= hclge_get_mac_link_status(hdev
);
2444 if (hdev
->hw
.mac
.phydev
) {
2445 if (!genphy_read_status(hdev
->hw
.mac
.phydev
))
2446 link_stat
= mac_state
&
2447 hdev
->hw
.mac
.phydev
->link
;
2452 link_stat
= mac_state
;
2458 static void hclge_update_link_status(struct hclge_dev
*hdev
)
2460 struct hnae3_client
*client
= hdev
->nic_client
;
2461 struct hnae3_handle
*handle
;
2467 state
= hclge_get_mac_phy_link(hdev
);
2468 if (state
!= hdev
->hw
.mac
.link
) {
2469 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2470 handle
= &hdev
->vport
[i
].nic
;
2471 client
->ops
->link_status_change(handle
, state
);
2473 hdev
->hw
.mac
.link
= state
;
2477 static int hclge_update_speed_duplex(struct hclge_dev
*hdev
)
2479 struct hclge_mac mac
= hdev
->hw
.mac
;
2484 /* get the speed and duplex as autoneg'result from mac cmd when phy
2487 if (mac
.phydev
|| !mac
.autoneg
)
2490 ret
= hclge_query_mac_an_speed_dup(hdev
, &speed
, &duplex
);
2492 dev_err(&hdev
->pdev
->dev
,
2493 "mac autoneg/speed/duplex query failed %d\n", ret
);
2497 if ((mac
.speed
!= speed
) || (mac
.duplex
!= duplex
)) {
2498 ret
= hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2500 dev_err(&hdev
->pdev
->dev
,
2501 "mac speed/duplex config failed %d\n", ret
);
2509 static int hclge_update_speed_duplex_h(struct hnae3_handle
*handle
)
2511 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2512 struct hclge_dev
*hdev
= vport
->back
;
2514 return hclge_update_speed_duplex(hdev
);
2517 static int hclge_get_status(struct hnae3_handle
*handle
)
2519 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2520 struct hclge_dev
*hdev
= vport
->back
;
2522 hclge_update_link_status(hdev
);
2524 return hdev
->hw
.mac
.link
;
2527 static void hclge_service_timer(struct timer_list
*t
)
2529 struct hclge_dev
*hdev
= from_timer(hdev
, t
, service_timer
);
2531 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
2532 hdev
->hw_stats
.stats_timer
++;
2533 hclge_task_schedule(hdev
);
2536 static void hclge_service_complete(struct hclge_dev
*hdev
)
2538 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
));
2540 /* Flush memory before next watchdog */
2541 smp_mb__before_atomic();
2542 clear_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
);
2545 static u32
hclge_check_event_cause(struct hclge_dev
*hdev
, u32
*clearval
)
2550 /* fetch the events from their corresponding regs */
2551 rst_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
);
2552 cmdq_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
);
2554 /* Assumption: If by any chance reset and mailbox events are reported
2555 * together then we will only process reset event in this go and will
2556 * defer the processing of the mailbox events. Since, we would have not
2557 * cleared RX CMDQ event this time we would receive again another
2558 * interrupt from H/W just for the mailbox.
2561 /* check for vector0 reset event sources */
2562 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
) & rst_src_reg
) {
2563 set_bit(HNAE3_GLOBAL_RESET
, &hdev
->reset_pending
);
2564 *clearval
= BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
);
2565 return HCLGE_VECTOR0_EVENT_RST
;
2568 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B
) & rst_src_reg
) {
2569 set_bit(HNAE3_CORE_RESET
, &hdev
->reset_pending
);
2570 *clearval
= BIT(HCLGE_VECTOR0_CORERESET_INT_B
);
2571 return HCLGE_VECTOR0_EVENT_RST
;
2574 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B
) & rst_src_reg
) {
2575 set_bit(HNAE3_IMP_RESET
, &hdev
->reset_pending
);
2576 *clearval
= BIT(HCLGE_VECTOR0_IMPRESET_INT_B
);
2577 return HCLGE_VECTOR0_EVENT_RST
;
2580 /* check for vector0 mailbox(=CMDQ RX) event source */
2581 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
) & cmdq_src_reg
) {
2582 cmdq_src_reg
&= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
);
2583 *clearval
= cmdq_src_reg
;
2584 return HCLGE_VECTOR0_EVENT_MBX
;
2587 return HCLGE_VECTOR0_EVENT_OTHER
;
2590 static void hclge_clear_event_cause(struct hclge_dev
*hdev
, u32 event_type
,
2593 switch (event_type
) {
2594 case HCLGE_VECTOR0_EVENT_RST
:
2595 hclge_write_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
, regclr
);
2597 case HCLGE_VECTOR0_EVENT_MBX
:
2598 hclge_write_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
, regclr
);
2603 static void hclge_enable_vector(struct hclge_misc_vector
*vector
, bool enable
)
2605 writel(enable
? 1 : 0, vector
->addr
);
2608 static irqreturn_t
hclge_misc_irq_handle(int irq
, void *data
)
2610 struct hclge_dev
*hdev
= data
;
2614 hclge_enable_vector(&hdev
->misc_vector
, false);
2615 event_cause
= hclge_check_event_cause(hdev
, &clearval
);
2617 /* vector 0 interrupt is shared with reset and mailbox source events.*/
2618 switch (event_cause
) {
2619 case HCLGE_VECTOR0_EVENT_RST
:
2620 hclge_reset_task_schedule(hdev
);
2622 case HCLGE_VECTOR0_EVENT_MBX
:
2623 /* If we are here then,
2624 * 1. Either we are not handling any mbx task and we are not
2627 * 2. We could be handling a mbx task but nothing more is
2629 * In both cases, we should schedule mbx task as there are more
2630 * mbx messages reported by this interrupt.
2632 hclge_mbx_task_schedule(hdev
);
2635 dev_dbg(&hdev
->pdev
->dev
,
2636 "received unknown or unhandled event of vector0\n");
2640 /* we should clear the source of interrupt */
2641 hclge_clear_event_cause(hdev
, event_cause
, clearval
);
2642 hclge_enable_vector(&hdev
->misc_vector
, true);
2647 static void hclge_free_vector(struct hclge_dev
*hdev
, int vector_id
)
2649 hdev
->vector_status
[vector_id
] = HCLGE_INVALID_VPORT
;
2650 hdev
->num_msi_left
+= 1;
2651 hdev
->num_msi_used
-= 1;
2654 static void hclge_get_misc_vector(struct hclge_dev
*hdev
)
2656 struct hclge_misc_vector
*vector
= &hdev
->misc_vector
;
2658 vector
->vector_irq
= pci_irq_vector(hdev
->pdev
, 0);
2660 vector
->addr
= hdev
->hw
.io_base
+ HCLGE_MISC_VECTOR_REG_BASE
;
2661 hdev
->vector_status
[0] = 0;
2663 hdev
->num_msi_left
-= 1;
2664 hdev
->num_msi_used
+= 1;
2667 static int hclge_misc_irq_init(struct hclge_dev
*hdev
)
2671 hclge_get_misc_vector(hdev
);
2673 /* this would be explicitly freed in the end */
2674 ret
= request_irq(hdev
->misc_vector
.vector_irq
, hclge_misc_irq_handle
,
2675 0, "hclge_misc", hdev
);
2677 hclge_free_vector(hdev
, 0);
2678 dev_err(&hdev
->pdev
->dev
, "request misc irq(%d) fail\n",
2679 hdev
->misc_vector
.vector_irq
);
2685 static void hclge_misc_irq_uninit(struct hclge_dev
*hdev
)
2687 free_irq(hdev
->misc_vector
.vector_irq
, hdev
);
2688 hclge_free_vector(hdev
, 0);
2691 static int hclge_notify_client(struct hclge_dev
*hdev
,
2692 enum hnae3_reset_notify_type type
)
2694 struct hnae3_client
*client
= hdev
->nic_client
;
2697 if (!client
->ops
->reset_notify
)
2700 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2701 struct hnae3_handle
*handle
= &hdev
->vport
[i
].nic
;
2704 ret
= client
->ops
->reset_notify(handle
, type
);
2712 static int hclge_reset_wait(struct hclge_dev
*hdev
)
2714 #define HCLGE_RESET_WATI_MS 100
2715 #define HCLGE_RESET_WAIT_CNT 5
2716 u32 val
, reg
, reg_bit
;
2719 switch (hdev
->reset_type
) {
2720 case HNAE3_GLOBAL_RESET
:
2721 reg
= HCLGE_GLOBAL_RESET_REG
;
2722 reg_bit
= HCLGE_GLOBAL_RESET_BIT
;
2724 case HNAE3_CORE_RESET
:
2725 reg
= HCLGE_GLOBAL_RESET_REG
;
2726 reg_bit
= HCLGE_CORE_RESET_BIT
;
2728 case HNAE3_FUNC_RESET
:
2729 reg
= HCLGE_FUN_RST_ING
;
2730 reg_bit
= HCLGE_FUN_RST_ING_B
;
2733 dev_err(&hdev
->pdev
->dev
,
2734 "Wait for unsupported reset type: %d\n",
2739 val
= hclge_read_dev(&hdev
->hw
, reg
);
2740 while (hnae_get_bit(val
, reg_bit
) && cnt
< HCLGE_RESET_WAIT_CNT
) {
2741 msleep(HCLGE_RESET_WATI_MS
);
2742 val
= hclge_read_dev(&hdev
->hw
, reg
);
2746 if (cnt
>= HCLGE_RESET_WAIT_CNT
) {
2747 dev_warn(&hdev
->pdev
->dev
,
2748 "Wait for reset timeout: %d\n", hdev
->reset_type
);
2755 int hclge_func_reset_cmd(struct hclge_dev
*hdev
, int func_id
)
2757 struct hclge_desc desc
;
2758 struct hclge_reset_cmd
*req
= (struct hclge_reset_cmd
*)desc
.data
;
2761 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_RST_TRIGGER
, false);
2762 hnae_set_bit(req
->mac_func_reset
, HCLGE_CFG_RESET_MAC_B
, 0);
2763 hnae_set_bit(req
->mac_func_reset
, HCLGE_CFG_RESET_FUNC_B
, 1);
2764 req
->fun_reset_vfid
= func_id
;
2766 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2768 dev_err(&hdev
->pdev
->dev
,
2769 "send function reset cmd fail, status =%d\n", ret
);
2774 static void hclge_do_reset(struct hclge_dev
*hdev
)
2776 struct pci_dev
*pdev
= hdev
->pdev
;
2779 switch (hdev
->reset_type
) {
2780 case HNAE3_GLOBAL_RESET
:
2781 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2782 hnae_set_bit(val
, HCLGE_GLOBAL_RESET_BIT
, 1);
2783 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2784 dev_info(&pdev
->dev
, "Global Reset requested\n");
2786 case HNAE3_CORE_RESET
:
2787 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2788 hnae_set_bit(val
, HCLGE_CORE_RESET_BIT
, 1);
2789 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2790 dev_info(&pdev
->dev
, "Core Reset requested\n");
2792 case HNAE3_FUNC_RESET
:
2793 dev_info(&pdev
->dev
, "PF Reset requested\n");
2794 hclge_func_reset_cmd(hdev
, 0);
2795 /* schedule again to check later */
2796 set_bit(HNAE3_FUNC_RESET
, &hdev
->reset_pending
);
2797 hclge_reset_task_schedule(hdev
);
2800 dev_warn(&pdev
->dev
,
2801 "Unsupported reset type: %d\n", hdev
->reset_type
);
2806 static enum hnae3_reset_type
hclge_get_reset_level(struct hclge_dev
*hdev
,
2807 unsigned long *addr
)
2809 enum hnae3_reset_type rst_level
= HNAE3_NONE_RESET
;
2811 /* return the highest priority reset level amongst all */
2812 if (test_bit(HNAE3_GLOBAL_RESET
, addr
))
2813 rst_level
= HNAE3_GLOBAL_RESET
;
2814 else if (test_bit(HNAE3_CORE_RESET
, addr
))
2815 rst_level
= HNAE3_CORE_RESET
;
2816 else if (test_bit(HNAE3_IMP_RESET
, addr
))
2817 rst_level
= HNAE3_IMP_RESET
;
2818 else if (test_bit(HNAE3_FUNC_RESET
, addr
))
2819 rst_level
= HNAE3_FUNC_RESET
;
2821 /* now, clear all other resets */
2822 clear_bit(HNAE3_GLOBAL_RESET
, addr
);
2823 clear_bit(HNAE3_CORE_RESET
, addr
);
2824 clear_bit(HNAE3_IMP_RESET
, addr
);
2825 clear_bit(HNAE3_FUNC_RESET
, addr
);
2830 static void hclge_reset(struct hclge_dev
*hdev
)
2832 /* perform reset of the stack & ae device for a client */
2834 hclge_notify_client(hdev
, HNAE3_DOWN_CLIENT
);
2836 if (!hclge_reset_wait(hdev
)) {
2838 hclge_notify_client(hdev
, HNAE3_UNINIT_CLIENT
);
2839 hclge_reset_ae_dev(hdev
->ae_dev
);
2840 hclge_notify_client(hdev
, HNAE3_INIT_CLIENT
);
2843 /* schedule again to check pending resets later */
2844 set_bit(hdev
->reset_type
, &hdev
->reset_pending
);
2845 hclge_reset_task_schedule(hdev
);
2848 hclge_notify_client(hdev
, HNAE3_UP_CLIENT
);
2851 static void hclge_reset_event(struct hnae3_handle
*handle
)
2853 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2854 struct hclge_dev
*hdev
= vport
->back
;
2856 /* check if this is a new reset request and we are not here just because
2857 * last reset attempt did not succeed and watchdog hit us again. We will
2858 * know this if last reset request did not occur very recently (watchdog
2859 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2860 * In case of new request we reset the "reset level" to PF reset.
2862 if (time_after(jiffies
, (handle
->last_reset_time
+ 4 * 5 * HZ
)))
2863 handle
->reset_level
= HNAE3_FUNC_RESET
;
2865 dev_info(&hdev
->pdev
->dev
, "received reset event , reset type is %d",
2866 handle
->reset_level
);
2868 /* request reset & schedule reset task */
2869 set_bit(handle
->reset_level
, &hdev
->reset_request
);
2870 hclge_reset_task_schedule(hdev
);
2872 if (handle
->reset_level
< HNAE3_GLOBAL_RESET
)
2873 handle
->reset_level
++;
2875 handle
->last_reset_time
= jiffies
;
2878 static void hclge_reset_subtask(struct hclge_dev
*hdev
)
2880 /* check if there is any ongoing reset in the hardware. This status can
2881 * be checked from reset_pending. If there is then, we need to wait for
2882 * hardware to complete reset.
2883 * a. If we are able to figure out in reasonable time that hardware
2884 * has fully resetted then, we can proceed with driver, client
2886 * b. else, we can come back later to check this status so re-sched
2889 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_pending
);
2890 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2893 /* check if we got any *new* reset requests to be honored */
2894 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_request
);
2895 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2896 hclge_do_reset(hdev
);
2898 hdev
->reset_type
= HNAE3_NONE_RESET
;
2901 static void hclge_reset_service_task(struct work_struct
*work
)
2903 struct hclge_dev
*hdev
=
2904 container_of(work
, struct hclge_dev
, rst_service_task
);
2906 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
2909 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
2911 hclge_reset_subtask(hdev
);
2913 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
2916 static void hclge_mailbox_service_task(struct work_struct
*work
)
2918 struct hclge_dev
*hdev
=
2919 container_of(work
, struct hclge_dev
, mbx_service_task
);
2921 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
))
2924 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
2926 hclge_mbx_handler(hdev
);
2928 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
2931 static void hclge_service_task(struct work_struct
*work
)
2933 struct hclge_dev
*hdev
=
2934 container_of(work
, struct hclge_dev
, service_task
);
2936 /* The total rx/tx packets statstics are wanted to be updated
2937 * per second. Both hclge_update_stats_for_all() and
2938 * hclge_mac_get_traffic_stats() can do it.
2940 if (hdev
->hw_stats
.stats_timer
>= HCLGE_STATS_TIMER_INTERVAL
) {
2941 hclge_update_stats_for_all(hdev
);
2942 hdev
->hw_stats
.stats_timer
= 0;
2944 hclge_mac_get_traffic_stats(hdev
);
2947 hclge_update_speed_duplex(hdev
);
2948 hclge_update_link_status(hdev
);
2949 hclge_update_led_status(hdev
);
2950 hclge_service_complete(hdev
);
2953 static void hclge_disable_sriov(struct hclge_dev
*hdev
)
2955 /* If our VFs are assigned we cannot shut down SR-IOV
2956 * without causing issues, so just leave the hardware
2957 * available but disabled
2959 if (pci_vfs_assigned(hdev
->pdev
)) {
2960 dev_warn(&hdev
->pdev
->dev
,
2961 "disabling driver while VFs are assigned\n");
2965 pci_disable_sriov(hdev
->pdev
);
2968 struct hclge_vport
*hclge_get_vport(struct hnae3_handle
*handle
)
2970 /* VF handle has no client */
2971 if (!handle
->client
)
2972 return container_of(handle
, struct hclge_vport
, nic
);
2973 else if (handle
->client
->type
== HNAE3_CLIENT_ROCE
)
2974 return container_of(handle
, struct hclge_vport
, roce
);
2976 return container_of(handle
, struct hclge_vport
, nic
);
2979 static int hclge_get_vector(struct hnae3_handle
*handle
, u16 vector_num
,
2980 struct hnae3_vector_info
*vector_info
)
2982 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2983 struct hnae3_vector_info
*vector
= vector_info
;
2984 struct hclge_dev
*hdev
= vport
->back
;
2988 vector_num
= min(hdev
->num_msi_left
, vector_num
);
2990 for (j
= 0; j
< vector_num
; j
++) {
2991 for (i
= 1; i
< hdev
->num_msi
; i
++) {
2992 if (hdev
->vector_status
[i
] == HCLGE_INVALID_VPORT
) {
2993 vector
->vector
= pci_irq_vector(hdev
->pdev
, i
);
2994 vector
->io_addr
= hdev
->hw
.io_base
+
2995 HCLGE_VECTOR_REG_BASE
+
2996 (i
- 1) * HCLGE_VECTOR_REG_OFFSET
+
2998 HCLGE_VECTOR_VF_OFFSET
;
2999 hdev
->vector_status
[i
] = vport
->vport_id
;
3000 hdev
->vector_irq
[i
] = vector
->vector
;
3009 hdev
->num_msi_left
-= alloc
;
3010 hdev
->num_msi_used
+= alloc
;
3015 static int hclge_get_vector_index(struct hclge_dev
*hdev
, int vector
)
3019 for (i
= 0; i
< hdev
->num_msi
; i
++)
3020 if (vector
== hdev
->vector_irq
[i
])
3026 static int hclge_put_vector(struct hnae3_handle
*handle
, int vector
)
3028 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3029 struct hclge_dev
*hdev
= vport
->back
;
3032 vector_id
= hclge_get_vector_index(hdev
, vector
);
3033 if (vector_id
< 0) {
3034 dev_err(&hdev
->pdev
->dev
,
3035 "Get vector index fail. vector_id =%d\n", vector_id
);
3039 hclge_free_vector(hdev
, vector_id
);
3044 static u32
hclge_get_rss_key_size(struct hnae3_handle
*handle
)
3046 return HCLGE_RSS_KEY_SIZE
;
3049 static u32
hclge_get_rss_indir_size(struct hnae3_handle
*handle
)
3051 return HCLGE_RSS_IND_TBL_SIZE
;
3054 static int hclge_set_rss_algo_key(struct hclge_dev
*hdev
,
3055 const u8 hfunc
, const u8
*key
)
3057 struct hclge_rss_config_cmd
*req
;
3058 struct hclge_desc desc
;
3063 req
= (struct hclge_rss_config_cmd
*)desc
.data
;
3065 for (key_offset
= 0; key_offset
< 3; key_offset
++) {
3066 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_GENERIC_CONFIG
,
3069 req
->hash_config
|= (hfunc
& HCLGE_RSS_HASH_ALGO_MASK
);
3070 req
->hash_config
|= (key_offset
<< HCLGE_RSS_HASH_KEY_OFFSET_B
);
3072 if (key_offset
== 2)
3074 HCLGE_RSS_KEY_SIZE
- HCLGE_RSS_HASH_KEY_NUM
* 2;
3076 key_size
= HCLGE_RSS_HASH_KEY_NUM
;
3078 memcpy(req
->hash_key
,
3079 key
+ key_offset
* HCLGE_RSS_HASH_KEY_NUM
, key_size
);
3081 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3083 dev_err(&hdev
->pdev
->dev
,
3084 "Configure RSS config fail, status = %d\n",
3092 static int hclge_set_rss_indir_table(struct hclge_dev
*hdev
, const u8
*indir
)
3094 struct hclge_rss_indirection_table_cmd
*req
;
3095 struct hclge_desc desc
;
3099 req
= (struct hclge_rss_indirection_table_cmd
*)desc
.data
;
3101 for (i
= 0; i
< HCLGE_RSS_CFG_TBL_NUM
; i
++) {
3102 hclge_cmd_setup_basic_desc
3103 (&desc
, HCLGE_OPC_RSS_INDIR_TABLE
, false);
3105 req
->start_table_index
=
3106 cpu_to_le16(i
* HCLGE_RSS_CFG_TBL_SIZE
);
3107 req
->rss_set_bitmap
= cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK
);
3109 for (j
= 0; j
< HCLGE_RSS_CFG_TBL_SIZE
; j
++)
3110 req
->rss_result
[j
] =
3111 indir
[i
* HCLGE_RSS_CFG_TBL_SIZE
+ j
];
3113 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3115 dev_err(&hdev
->pdev
->dev
,
3116 "Configure rss indir table fail,status = %d\n",
3124 static int hclge_set_rss_tc_mode(struct hclge_dev
*hdev
, u16
*tc_valid
,
3125 u16
*tc_size
, u16
*tc_offset
)
3127 struct hclge_rss_tc_mode_cmd
*req
;
3128 struct hclge_desc desc
;
3132 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_TC_MODE
, false);
3133 req
= (struct hclge_rss_tc_mode_cmd
*)desc
.data
;
3135 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3138 hnae_set_bit(mode
, HCLGE_RSS_TC_VALID_B
, (tc_valid
[i
] & 0x1));
3139 hnae_set_field(mode
, HCLGE_RSS_TC_SIZE_M
,
3140 HCLGE_RSS_TC_SIZE_S
, tc_size
[i
]);
3141 hnae_set_field(mode
, HCLGE_RSS_TC_OFFSET_M
,
3142 HCLGE_RSS_TC_OFFSET_S
, tc_offset
[i
]);
3144 req
->rss_tc_mode
[i
] = cpu_to_le16(mode
);
3147 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3149 dev_err(&hdev
->pdev
->dev
,
3150 "Configure rss tc mode fail, status = %d\n", ret
);
3157 static int hclge_set_rss_input_tuple(struct hclge_dev
*hdev
)
3159 struct hclge_rss_input_tuple_cmd
*req
;
3160 struct hclge_desc desc
;
3163 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
3165 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3167 /* Get the tuple cfg from pf */
3168 req
->ipv4_tcp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_tcp_en
;
3169 req
->ipv4_udp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_udp_en
;
3170 req
->ipv4_sctp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_sctp_en
;
3171 req
->ipv4_fragment_en
= hdev
->vport
[0].rss_tuple_sets
.ipv4_fragment_en
;
3172 req
->ipv6_tcp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_tcp_en
;
3173 req
->ipv6_udp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_udp_en
;
3174 req
->ipv6_sctp_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_sctp_en
;
3175 req
->ipv6_fragment_en
= hdev
->vport
[0].rss_tuple_sets
.ipv6_fragment_en
;
3176 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3178 dev_err(&hdev
->pdev
->dev
,
3179 "Configure rss input fail, status = %d\n", ret
);
3186 static int hclge_get_rss(struct hnae3_handle
*handle
, u32
*indir
,
3189 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3192 /* Get hash algorithm */
3194 *hfunc
= vport
->rss_algo
;
3196 /* Get the RSS Key required by the user */
3198 memcpy(key
, vport
->rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
3200 /* Get indirect table */
3202 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3203 indir
[i
] = vport
->rss_indirection_tbl
[i
];
3208 static int hclge_set_rss(struct hnae3_handle
*handle
, const u32
*indir
,
3209 const u8
*key
, const u8 hfunc
)
3211 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3212 struct hclge_dev
*hdev
= vport
->back
;
3216 /* Set the RSS Hash Key if specififed by the user */
3219 if (hfunc
== ETH_RSS_HASH_TOP
||
3220 hfunc
== ETH_RSS_HASH_NO_CHANGE
)
3221 hash_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3224 ret
= hclge_set_rss_algo_key(hdev
, hash_algo
, key
);
3228 /* Update the shadow RSS key with user specified qids */
3229 memcpy(vport
->rss_hash_key
, key
, HCLGE_RSS_KEY_SIZE
);
3230 vport
->rss_algo
= hash_algo
;
3233 /* Update the shadow RSS table with user specified qids */
3234 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3235 vport
->rss_indirection_tbl
[i
] = indir
[i
];
3237 /* Update the hardware */
3238 return hclge_set_rss_indir_table(hdev
, vport
->rss_indirection_tbl
);
3241 static u8
hclge_get_rss_hash_bits(struct ethtool_rxnfc
*nfc
)
3243 u8 hash_sets
= nfc
->data
& RXH_L4_B_0_1
? HCLGE_S_PORT_BIT
: 0;
3245 if (nfc
->data
& RXH_L4_B_2_3
)
3246 hash_sets
|= HCLGE_D_PORT_BIT
;
3248 hash_sets
&= ~HCLGE_D_PORT_BIT
;
3250 if (nfc
->data
& RXH_IP_SRC
)
3251 hash_sets
|= HCLGE_S_IP_BIT
;
3253 hash_sets
&= ~HCLGE_S_IP_BIT
;
3255 if (nfc
->data
& RXH_IP_DST
)
3256 hash_sets
|= HCLGE_D_IP_BIT
;
3258 hash_sets
&= ~HCLGE_D_IP_BIT
;
3260 if (nfc
->flow_type
== SCTP_V4_FLOW
|| nfc
->flow_type
== SCTP_V6_FLOW
)
3261 hash_sets
|= HCLGE_V_TAG_BIT
;
3266 static int hclge_set_rss_tuple(struct hnae3_handle
*handle
,
3267 struct ethtool_rxnfc
*nfc
)
3269 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3270 struct hclge_dev
*hdev
= vport
->back
;
3271 struct hclge_rss_input_tuple_cmd
*req
;
3272 struct hclge_desc desc
;
3276 if (nfc
->data
& ~(RXH_IP_SRC
| RXH_IP_DST
|
3277 RXH_L4_B_0_1
| RXH_L4_B_2_3
))
3280 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3281 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
3283 req
->ipv4_tcp_en
= vport
->rss_tuple_sets
.ipv4_tcp_en
;
3284 req
->ipv4_udp_en
= vport
->rss_tuple_sets
.ipv4_udp_en
;
3285 req
->ipv4_sctp_en
= vport
->rss_tuple_sets
.ipv4_sctp_en
;
3286 req
->ipv4_fragment_en
= vport
->rss_tuple_sets
.ipv4_fragment_en
;
3287 req
->ipv6_tcp_en
= vport
->rss_tuple_sets
.ipv6_tcp_en
;
3288 req
->ipv6_udp_en
= vport
->rss_tuple_sets
.ipv6_udp_en
;
3289 req
->ipv6_sctp_en
= vport
->rss_tuple_sets
.ipv6_sctp_en
;
3290 req
->ipv6_fragment_en
= vport
->rss_tuple_sets
.ipv6_fragment_en
;
3292 tuple_sets
= hclge_get_rss_hash_bits(nfc
);
3293 switch (nfc
->flow_type
) {
3295 req
->ipv4_tcp_en
= tuple_sets
;
3298 req
->ipv6_tcp_en
= tuple_sets
;
3301 req
->ipv4_udp_en
= tuple_sets
;
3304 req
->ipv6_udp_en
= tuple_sets
;
3307 req
->ipv4_sctp_en
= tuple_sets
;
3310 if ((nfc
->data
& RXH_L4_B_0_1
) ||
3311 (nfc
->data
& RXH_L4_B_2_3
))
3314 req
->ipv6_sctp_en
= tuple_sets
;
3317 req
->ipv4_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3320 req
->ipv6_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3326 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3328 dev_err(&hdev
->pdev
->dev
,
3329 "Set rss tuple fail, status = %d\n", ret
);
3333 vport
->rss_tuple_sets
.ipv4_tcp_en
= req
->ipv4_tcp_en
;
3334 vport
->rss_tuple_sets
.ipv4_udp_en
= req
->ipv4_udp_en
;
3335 vport
->rss_tuple_sets
.ipv4_sctp_en
= req
->ipv4_sctp_en
;
3336 vport
->rss_tuple_sets
.ipv4_fragment_en
= req
->ipv4_fragment_en
;
3337 vport
->rss_tuple_sets
.ipv6_tcp_en
= req
->ipv6_tcp_en
;
3338 vport
->rss_tuple_sets
.ipv6_udp_en
= req
->ipv6_udp_en
;
3339 vport
->rss_tuple_sets
.ipv6_sctp_en
= req
->ipv6_sctp_en
;
3340 vport
->rss_tuple_sets
.ipv6_fragment_en
= req
->ipv6_fragment_en
;
3344 static int hclge_get_rss_tuple(struct hnae3_handle
*handle
,
3345 struct ethtool_rxnfc
*nfc
)
3347 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3352 switch (nfc
->flow_type
) {
3354 tuple_sets
= vport
->rss_tuple_sets
.ipv4_tcp_en
;
3357 tuple_sets
= vport
->rss_tuple_sets
.ipv4_udp_en
;
3360 tuple_sets
= vport
->rss_tuple_sets
.ipv6_tcp_en
;
3363 tuple_sets
= vport
->rss_tuple_sets
.ipv6_udp_en
;
3366 tuple_sets
= vport
->rss_tuple_sets
.ipv4_sctp_en
;
3369 tuple_sets
= vport
->rss_tuple_sets
.ipv6_sctp_en
;
3373 tuple_sets
= HCLGE_S_IP_BIT
| HCLGE_D_IP_BIT
;
3382 if (tuple_sets
& HCLGE_D_PORT_BIT
)
3383 nfc
->data
|= RXH_L4_B_2_3
;
3384 if (tuple_sets
& HCLGE_S_PORT_BIT
)
3385 nfc
->data
|= RXH_L4_B_0_1
;
3386 if (tuple_sets
& HCLGE_D_IP_BIT
)
3387 nfc
->data
|= RXH_IP_DST
;
3388 if (tuple_sets
& HCLGE_S_IP_BIT
)
3389 nfc
->data
|= RXH_IP_SRC
;
3394 static int hclge_get_tc_size(struct hnae3_handle
*handle
)
3396 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3397 struct hclge_dev
*hdev
= vport
->back
;
3399 return hdev
->rss_size_max
;
3402 int hclge_rss_init_hw(struct hclge_dev
*hdev
)
3404 struct hclge_vport
*vport
= hdev
->vport
;
3405 u8
*rss_indir
= vport
[0].rss_indirection_tbl
;
3406 u16 rss_size
= vport
[0].alloc_rss_size
;
3407 u8
*key
= vport
[0].rss_hash_key
;
3408 u8 hfunc
= vport
[0].rss_algo
;
3409 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
3410 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
3411 u16 tc_size
[HCLGE_MAX_TC_NUM
];
3415 ret
= hclge_set_rss_indir_table(hdev
, rss_indir
);
3419 ret
= hclge_set_rss_algo_key(hdev
, hfunc
, key
);
3423 ret
= hclge_set_rss_input_tuple(hdev
);
3427 /* Each TC have the same queue size, and tc_size set to hardware is
3428 * the log2 of roundup power of two of rss_size, the acutal queue
3429 * size is limited by indirection table.
3431 if (rss_size
> HCLGE_RSS_TC_SIZE_7
|| rss_size
== 0) {
3432 dev_err(&hdev
->pdev
->dev
,
3433 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3438 roundup_size
= roundup_pow_of_two(rss_size
);
3439 roundup_size
= ilog2(roundup_size
);
3441 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3444 if (!(hdev
->hw_tc_map
& BIT(i
)))
3448 tc_size
[i
] = roundup_size
;
3449 tc_offset
[i
] = rss_size
* i
;
3452 return hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
3455 void hclge_rss_indir_init_cfg(struct hclge_dev
*hdev
)
3457 struct hclge_vport
*vport
= hdev
->vport
;
3460 for (j
= 0; j
< hdev
->num_vmdq_vport
+ 1; j
++) {
3461 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3462 vport
[j
].rss_indirection_tbl
[i
] =
3463 i
% vport
[j
].alloc_rss_size
;
3467 static void hclge_rss_init_cfg(struct hclge_dev
*hdev
)
3469 struct hclge_vport
*vport
= hdev
->vport
;
3472 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
3473 vport
[i
].rss_tuple_sets
.ipv4_tcp_en
=
3474 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3475 vport
[i
].rss_tuple_sets
.ipv4_udp_en
=
3476 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3477 vport
[i
].rss_tuple_sets
.ipv4_sctp_en
=
3478 HCLGE_RSS_INPUT_TUPLE_SCTP
;
3479 vport
[i
].rss_tuple_sets
.ipv4_fragment_en
=
3480 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3481 vport
[i
].rss_tuple_sets
.ipv6_tcp_en
=
3482 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3483 vport
[i
].rss_tuple_sets
.ipv6_udp_en
=
3484 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3485 vport
[i
].rss_tuple_sets
.ipv6_sctp_en
=
3486 HCLGE_RSS_INPUT_TUPLE_SCTP
;
3487 vport
[i
].rss_tuple_sets
.ipv6_fragment_en
=
3488 HCLGE_RSS_INPUT_TUPLE_OTHER
;
3490 vport
[i
].rss_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3492 netdev_rss_key_fill(vport
[i
].rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
3495 hclge_rss_indir_init_cfg(hdev
);
3498 int hclge_bind_ring_with_vector(struct hclge_vport
*vport
,
3499 int vector_id
, bool en
,
3500 struct hnae3_ring_chain_node
*ring_chain
)
3502 struct hclge_dev
*hdev
= vport
->back
;
3503 struct hnae3_ring_chain_node
*node
;
3504 struct hclge_desc desc
;
3505 struct hclge_ctrl_vector_chain_cmd
*req
3506 = (struct hclge_ctrl_vector_chain_cmd
*)desc
.data
;
3507 enum hclge_cmd_status status
;
3508 enum hclge_opcode_type op
;
3509 u16 tqp_type_and_id
;
3512 op
= en
? HCLGE_OPC_ADD_RING_TO_VECTOR
: HCLGE_OPC_DEL_RING_TO_VECTOR
;
3513 hclge_cmd_setup_basic_desc(&desc
, op
, false);
3514 req
->int_vector_id
= vector_id
;
3517 for (node
= ring_chain
; node
; node
= node
->next
) {
3518 tqp_type_and_id
= le16_to_cpu(req
->tqp_type_and_id
[i
]);
3519 hnae_set_field(tqp_type_and_id
, HCLGE_INT_TYPE_M
,
3521 hnae_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
3522 hnae_set_field(tqp_type_and_id
, HCLGE_TQP_ID_M
,
3523 HCLGE_TQP_ID_S
, node
->tqp_index
);
3524 hnae_set_field(tqp_type_and_id
, HCLGE_INT_GL_IDX_M
,
3526 hnae_get_field(node
->int_gl_idx
,
3527 HNAE3_RING_GL_IDX_M
,
3528 HNAE3_RING_GL_IDX_S
));
3529 req
->tqp_type_and_id
[i
] = cpu_to_le16(tqp_type_and_id
);
3530 if (++i
>= HCLGE_VECTOR_ELEMENTS_PER_CMD
) {
3531 req
->int_cause_num
= HCLGE_VECTOR_ELEMENTS_PER_CMD
;
3532 req
->vfid
= vport
->vport_id
;
3534 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3536 dev_err(&hdev
->pdev
->dev
,
3537 "Map TQP fail, status is %d.\n",
3543 hclge_cmd_setup_basic_desc(&desc
,
3546 req
->int_vector_id
= vector_id
;
3551 req
->int_cause_num
= i
;
3552 req
->vfid
= vport
->vport_id
;
3553 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3555 dev_err(&hdev
->pdev
->dev
,
3556 "Map TQP fail, status is %d.\n", status
);
3564 static int hclge_map_ring_to_vector(struct hnae3_handle
*handle
,
3566 struct hnae3_ring_chain_node
*ring_chain
)
3568 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3569 struct hclge_dev
*hdev
= vport
->back
;
3572 vector_id
= hclge_get_vector_index(hdev
, vector
);
3573 if (vector_id
< 0) {
3574 dev_err(&hdev
->pdev
->dev
,
3575 "Get vector index fail. vector_id =%d\n", vector_id
);
3579 return hclge_bind_ring_with_vector(vport
, vector_id
, true, ring_chain
);
3582 static int hclge_unmap_ring_frm_vector(struct hnae3_handle
*handle
,
3584 struct hnae3_ring_chain_node
*ring_chain
)
3586 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3587 struct hclge_dev
*hdev
= vport
->back
;
3590 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
3593 vector_id
= hclge_get_vector_index(hdev
, vector
);
3594 if (vector_id
< 0) {
3595 dev_err(&handle
->pdev
->dev
,
3596 "Get vector index fail. ret =%d\n", vector_id
);
3600 ret
= hclge_bind_ring_with_vector(vport
, vector_id
, false, ring_chain
);
3602 dev_err(&handle
->pdev
->dev
,
3603 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3610 int hclge_cmd_set_promisc_mode(struct hclge_dev
*hdev
,
3611 struct hclge_promisc_param
*param
)
3613 struct hclge_promisc_cfg_cmd
*req
;
3614 struct hclge_desc desc
;
3617 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_PROMISC_MODE
, false);
3619 req
= (struct hclge_promisc_cfg_cmd
*)desc
.data
;
3620 req
->vf_id
= param
->vf_id
;
3621 req
->flag
= (param
->enable
<< HCLGE_PROMISC_EN_B
);
3623 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3625 dev_err(&hdev
->pdev
->dev
,
3626 "Set promisc mode fail, status is %d.\n", ret
);
3632 void hclge_promisc_param_init(struct hclge_promisc_param
*param
, bool en_uc
,
3633 bool en_mc
, bool en_bc
, int vport_id
)
3638 memset(param
, 0, sizeof(struct hclge_promisc_param
));
3640 param
->enable
= HCLGE_PROMISC_EN_UC
;
3642 param
->enable
|= HCLGE_PROMISC_EN_MC
;
3644 param
->enable
|= HCLGE_PROMISC_EN_BC
;
3645 param
->vf_id
= vport_id
;
3648 static void hclge_set_promisc_mode(struct hnae3_handle
*handle
, u32 en
)
3650 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3651 struct hclge_dev
*hdev
= vport
->back
;
3652 struct hclge_promisc_param param
;
3654 hclge_promisc_param_init(¶m
, en
, en
, true, vport
->vport_id
);
3655 hclge_cmd_set_promisc_mode(hdev
, ¶m
);
3658 static void hclge_cfg_mac_mode(struct hclge_dev
*hdev
, bool enable
)
3660 struct hclge_desc desc
;
3661 struct hclge_config_mac_mode_cmd
*req
=
3662 (struct hclge_config_mac_mode_cmd
*)desc
.data
;
3666 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAC_MODE
, false);
3667 hnae_set_bit(loop_en
, HCLGE_MAC_TX_EN_B
, enable
);
3668 hnae_set_bit(loop_en
, HCLGE_MAC_RX_EN_B
, enable
);
3669 hnae_set_bit(loop_en
, HCLGE_MAC_PAD_TX_B
, enable
);
3670 hnae_set_bit(loop_en
, HCLGE_MAC_PAD_RX_B
, enable
);
3671 hnae_set_bit(loop_en
, HCLGE_MAC_1588_TX_B
, 0);
3672 hnae_set_bit(loop_en
, HCLGE_MAC_1588_RX_B
, 0);
3673 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 0);
3674 hnae_set_bit(loop_en
, HCLGE_MAC_LINE_LP_B
, 0);
3675 hnae_set_bit(loop_en
, HCLGE_MAC_FCS_TX_B
, enable
);
3676 hnae_set_bit(loop_en
, HCLGE_MAC_RX_FCS_B
, enable
);
3677 hnae_set_bit(loop_en
, HCLGE_MAC_RX_FCS_STRIP_B
, enable
);
3678 hnae_set_bit(loop_en
, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B
, enable
);
3679 hnae_set_bit(loop_en
, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B
, enable
);
3680 hnae_set_bit(loop_en
, HCLGE_MAC_TX_UNDER_MIN_ERR_B
, enable
);
3681 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3683 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3685 dev_err(&hdev
->pdev
->dev
,
3686 "mac enable fail, ret =%d.\n", ret
);
3689 static int hclge_set_loopback(struct hnae3_handle
*handle
,
3690 enum hnae3_loop loop_mode
, bool en
)
3692 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3693 struct hclge_config_mac_mode_cmd
*req
;
3694 struct hclge_dev
*hdev
= vport
->back
;
3695 struct hclge_desc desc
;
3699 switch (loop_mode
) {
3700 case HNAE3_MAC_INTER_LOOP_MAC
:
3701 req
= (struct hclge_config_mac_mode_cmd
*)&desc
.data
[0];
3702 /* 1 Read out the MAC mode config at first */
3703 hclge_cmd_setup_basic_desc(&desc
,
3704 HCLGE_OPC_CONFIG_MAC_MODE
,
3706 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3708 dev_err(&hdev
->pdev
->dev
,
3709 "mac loopback get fail, ret =%d.\n",
3714 /* 2 Then setup the loopback flag */
3715 loop_en
= le32_to_cpu(req
->txrx_pad_fcs_loop_en
);
3717 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 1);
3719 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 0);
3721 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3723 /* 3 Config mac work mode with loopback flag
3724 * and its original configure parameters
3726 hclge_cmd_reuse_desc(&desc
, false);
3727 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3729 dev_err(&hdev
->pdev
->dev
,
3730 "mac loopback set fail, ret =%d.\n", ret
);
3734 dev_err(&hdev
->pdev
->dev
,
3735 "loop_mode %d is not supported\n", loop_mode
);
3742 static int hclge_tqp_enable(struct hclge_dev
*hdev
, int tqp_id
,
3743 int stream_id
, bool enable
)
3745 struct hclge_desc desc
;
3746 struct hclge_cfg_com_tqp_queue_cmd
*req
=
3747 (struct hclge_cfg_com_tqp_queue_cmd
*)desc
.data
;
3750 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_COM_TQP_QUEUE
, false);
3751 req
->tqp_id
= cpu_to_le16(tqp_id
& HCLGE_RING_ID_MASK
);
3752 req
->stream_id
= cpu_to_le16(stream_id
);
3753 req
->enable
|= enable
<< HCLGE_TQP_ENABLE_B
;
3755 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3757 dev_err(&hdev
->pdev
->dev
,
3758 "Tqp enable fail, status =%d.\n", ret
);
3762 static void hclge_reset_tqp_stats(struct hnae3_handle
*handle
)
3764 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3765 struct hnae3_queue
*queue
;
3766 struct hclge_tqp
*tqp
;
3769 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
3770 queue
= handle
->kinfo
.tqp
[i
];
3771 tqp
= container_of(queue
, struct hclge_tqp
, q
);
3772 memset(&tqp
->tqp_stats
, 0, sizeof(tqp
->tqp_stats
));
3776 static int hclge_ae_start(struct hnae3_handle
*handle
)
3778 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3779 struct hclge_dev
*hdev
= vport
->back
;
3782 for (i
= 0; i
< vport
->alloc_tqps
; i
++)
3783 hclge_tqp_enable(hdev
, i
, 0, true);
3786 hclge_cfg_mac_mode(hdev
, true);
3787 clear_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
3788 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
3790 /* reset tqp stats */
3791 hclge_reset_tqp_stats(handle
);
3793 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
3796 ret
= hclge_mac_start_phy(hdev
);
3803 static void hclge_ae_stop(struct hnae3_handle
*handle
)
3805 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3806 struct hclge_dev
*hdev
= vport
->back
;
3809 del_timer_sync(&hdev
->service_timer
);
3810 cancel_work_sync(&hdev
->service_task
);
3812 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
3815 for (i
= 0; i
< vport
->alloc_tqps
; i
++)
3816 hclge_tqp_enable(hdev
, i
, 0, false);
3819 hclge_cfg_mac_mode(hdev
, false);
3821 hclge_mac_stop_phy(hdev
);
3823 /* reset tqp stats */
3824 hclge_reset_tqp_stats(handle
);
3825 hclge_update_link_status(hdev
);
3828 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport
*vport
,
3829 u16 cmdq_resp
, u8 resp_code
,
3830 enum hclge_mac_vlan_tbl_opcode op
)
3832 struct hclge_dev
*hdev
= vport
->back
;
3833 int return_status
= -EIO
;
3836 dev_err(&hdev
->pdev
->dev
,
3837 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3842 if (op
== HCLGE_MAC_VLAN_ADD
) {
3843 if ((!resp_code
) || (resp_code
== 1)) {
3845 } else if (resp_code
== 2) {
3846 return_status
= -ENOSPC
;
3847 dev_err(&hdev
->pdev
->dev
,
3848 "add mac addr failed for uc_overflow.\n");
3849 } else if (resp_code
== 3) {
3850 return_status
= -ENOSPC
;
3851 dev_err(&hdev
->pdev
->dev
,
3852 "add mac addr failed for mc_overflow.\n");
3854 dev_err(&hdev
->pdev
->dev
,
3855 "add mac addr failed for undefined, code=%d.\n",
3858 } else if (op
== HCLGE_MAC_VLAN_REMOVE
) {
3861 } else if (resp_code
== 1) {
3862 return_status
= -ENOENT
;
3863 dev_dbg(&hdev
->pdev
->dev
,
3864 "remove mac addr failed for miss.\n");
3866 dev_err(&hdev
->pdev
->dev
,
3867 "remove mac addr failed for undefined, code=%d.\n",
3870 } else if (op
== HCLGE_MAC_VLAN_LKUP
) {
3873 } else if (resp_code
== 1) {
3874 return_status
= -ENOENT
;
3875 dev_dbg(&hdev
->pdev
->dev
,
3876 "lookup mac addr failed for miss.\n");
3878 dev_err(&hdev
->pdev
->dev
,
3879 "lookup mac addr failed for undefined, code=%d.\n",
3883 return_status
= -EINVAL
;
3884 dev_err(&hdev
->pdev
->dev
,
3885 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3889 return return_status
;
3892 static int hclge_update_desc_vfid(struct hclge_desc
*desc
, int vfid
, bool clr
)
3897 if (vfid
> 255 || vfid
< 0)
3900 if (vfid
>= 0 && vfid
<= 191) {
3901 word_num
= vfid
/ 32;
3902 bit_num
= vfid
% 32;
3904 desc
[1].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3906 desc
[1].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3908 word_num
= (vfid
- 192) / 32;
3909 bit_num
= vfid
% 32;
3911 desc
[2].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3913 desc
[2].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3919 static bool hclge_is_all_function_id_zero(struct hclge_desc
*desc
)
3921 #define HCLGE_DESC_NUMBER 3
3922 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3925 for (i
= 0; i
< HCLGE_DESC_NUMBER
; i
++)
3926 for (j
= 0; j
< HCLGE_FUNC_NUMBER_PER_DESC
; j
++)
3927 if (desc
[i
].data
[j
])
3933 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd
*new_req
,
3936 const unsigned char *mac_addr
= addr
;
3937 u32 high_val
= mac_addr
[2] << 16 | (mac_addr
[3] << 24) |
3938 (mac_addr
[0]) | (mac_addr
[1] << 8);
3939 u32 low_val
= mac_addr
[4] | (mac_addr
[5] << 8);
3941 new_req
->mac_addr_hi32
= cpu_to_le32(high_val
);
3942 new_req
->mac_addr_lo16
= cpu_to_le16(low_val
& 0xffff);
3945 static u16
hclge_get_mac_addr_to_mta_index(struct hclge_vport
*vport
,
3948 u16 high_val
= addr
[1] | (addr
[0] << 8);
3949 struct hclge_dev
*hdev
= vport
->back
;
3950 u32 rsh
= 4 - hdev
->mta_mac_sel_type
;
3951 u16 ret_val
= (high_val
>> rsh
) & 0xfff;
3956 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
3957 enum hclge_mta_dmac_sel_type mta_mac_sel
,
3960 struct hclge_mta_filter_mode_cmd
*req
;
3961 struct hclge_desc desc
;
3964 req
= (struct hclge_mta_filter_mode_cmd
*)desc
.data
;
3965 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_MODE_CFG
, false);
3967 hnae_set_bit(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_EN_B
,
3969 hnae_set_field(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_SEL_M
,
3970 HCLGE_CFG_MTA_MAC_SEL_S
, mta_mac_sel
);
3972 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3974 dev_err(&hdev
->pdev
->dev
,
3975 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3983 int hclge_cfg_func_mta_filter(struct hclge_dev
*hdev
,
3987 struct hclge_cfg_func_mta_filter_cmd
*req
;
3988 struct hclge_desc desc
;
3991 req
= (struct hclge_cfg_func_mta_filter_cmd
*)desc
.data
;
3992 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_FUNC_CFG
, false);
3994 hnae_set_bit(req
->accept
, HCLGE_CFG_FUNC_MTA_ACCEPT_B
,
3996 req
->function_id
= func_id
;
3998 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4000 dev_err(&hdev
->pdev
->dev
,
4001 "Config func_id enable failed for cmd_send, ret =%d.\n",
4009 static int hclge_set_mta_table_item(struct hclge_vport
*vport
,
4013 struct hclge_dev
*hdev
= vport
->back
;
4014 struct hclge_cfg_func_mta_item_cmd
*req
;
4015 struct hclge_desc desc
;
4019 req
= (struct hclge_cfg_func_mta_item_cmd
*)desc
.data
;
4020 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_TBL_ITEM_CFG
, false);
4021 hnae_set_bit(req
->accept
, HCLGE_CFG_MTA_ITEM_ACCEPT_B
, enable
);
4023 hnae_set_field(item_idx
, HCLGE_CFG_MTA_ITEM_IDX_M
,
4024 HCLGE_CFG_MTA_ITEM_IDX_S
, idx
);
4025 req
->item_idx
= cpu_to_le16(item_idx
);
4027 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4029 dev_err(&hdev
->pdev
->dev
,
4030 "Config mta table item failed for cmd_send, ret =%d.\n",
4038 static int hclge_remove_mac_vlan_tbl(struct hclge_vport
*vport
,
4039 struct hclge_mac_vlan_tbl_entry_cmd
*req
)
4041 struct hclge_dev
*hdev
= vport
->back
;
4042 struct hclge_desc desc
;
4047 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_REMOVE
, false);
4049 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4051 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4053 dev_err(&hdev
->pdev
->dev
,
4054 "del mac addr failed for cmd_send, ret =%d.\n",
4058 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4059 retval
= le16_to_cpu(desc
.retval
);
4061 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
4062 HCLGE_MAC_VLAN_REMOVE
);
4065 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport
*vport
,
4066 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
4067 struct hclge_desc
*desc
,
4070 struct hclge_dev
*hdev
= vport
->back
;
4075 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_MAC_VLAN_ADD
, true);
4077 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4078 memcpy(desc
[0].data
,
4080 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4081 hclge_cmd_setup_basic_desc(&desc
[1],
4082 HCLGE_OPC_MAC_VLAN_ADD
,
4084 desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4085 hclge_cmd_setup_basic_desc(&desc
[2],
4086 HCLGE_OPC_MAC_VLAN_ADD
,
4088 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 3);
4090 memcpy(desc
[0].data
,
4092 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4093 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
4096 dev_err(&hdev
->pdev
->dev
,
4097 "lookup mac addr failed for cmd_send, ret =%d.\n",
4101 resp_code
= (le32_to_cpu(desc
[0].data
[0]) >> 8) & 0xff;
4102 retval
= le16_to_cpu(desc
[0].retval
);
4104 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
4105 HCLGE_MAC_VLAN_LKUP
);
4108 static int hclge_add_mac_vlan_tbl(struct hclge_vport
*vport
,
4109 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
4110 struct hclge_desc
*mc_desc
)
4112 struct hclge_dev
*hdev
= vport
->back
;
4119 struct hclge_desc desc
;
4121 hclge_cmd_setup_basic_desc(&desc
,
4122 HCLGE_OPC_MAC_VLAN_ADD
,
4124 memcpy(desc
.data
, req
,
4125 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4126 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4127 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4128 retval
= le16_to_cpu(desc
.retval
);
4130 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
4132 HCLGE_MAC_VLAN_ADD
);
4134 hclge_cmd_reuse_desc(&mc_desc
[0], false);
4135 mc_desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4136 hclge_cmd_reuse_desc(&mc_desc
[1], false);
4137 mc_desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4138 hclge_cmd_reuse_desc(&mc_desc
[2], false);
4139 mc_desc
[2].flag
&= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT
);
4140 memcpy(mc_desc
[0].data
, req
,
4141 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4142 ret
= hclge_cmd_send(&hdev
->hw
, mc_desc
, 3);
4143 resp_code
= (le32_to_cpu(mc_desc
[0].data
[0]) >> 8) & 0xff;
4144 retval
= le16_to_cpu(mc_desc
[0].retval
);
4146 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
4148 HCLGE_MAC_VLAN_ADD
);
4152 dev_err(&hdev
->pdev
->dev
,
4153 "add mac addr failed for cmd_send, ret =%d.\n",
4161 static int hclge_add_uc_addr(struct hnae3_handle
*handle
,
4162 const unsigned char *addr
)
4164 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4166 return hclge_add_uc_addr_common(vport
, addr
);
4169 int hclge_add_uc_addr_common(struct hclge_vport
*vport
,
4170 const unsigned char *addr
)
4172 struct hclge_dev
*hdev
= vport
->back
;
4173 struct hclge_mac_vlan_tbl_entry_cmd req
;
4174 struct hclge_desc desc
;
4175 u16 egress_port
= 0;
4178 /* mac addr check */
4179 if (is_zero_ether_addr(addr
) ||
4180 is_broadcast_ether_addr(addr
) ||
4181 is_multicast_ether_addr(addr
)) {
4182 dev_err(&hdev
->pdev
->dev
,
4183 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4185 is_zero_ether_addr(addr
),
4186 is_broadcast_ether_addr(addr
),
4187 is_multicast_ether_addr(addr
));
4191 memset(&req
, 0, sizeof(req
));
4192 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4193 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4194 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 0);
4195 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4197 hnae_set_bit(egress_port
, HCLGE_MAC_EPORT_SW_EN_B
, 0);
4198 hnae_set_bit(egress_port
, HCLGE_MAC_EPORT_TYPE_B
, 0);
4199 hnae_set_field(egress_port
, HCLGE_MAC_EPORT_VFID_M
,
4200 HCLGE_MAC_EPORT_VFID_S
, vport
->vport_id
);
4201 hnae_set_field(egress_port
, HCLGE_MAC_EPORT_PFID_M
,
4202 HCLGE_MAC_EPORT_PFID_S
, 0);
4204 req
.egress_port
= cpu_to_le16(egress_port
);
4206 hclge_prepare_mac_addr(&req
, addr
);
4208 /* Lookup the mac address in the mac_vlan table, and add
4209 * it if the entry is inexistent. Repeated unicast entry
4210 * is not allowed in the mac vlan table.
4212 ret
= hclge_lookup_mac_vlan_tbl(vport
, &req
, &desc
, false);
4214 return hclge_add_mac_vlan_tbl(vport
, &req
, NULL
);
4216 /* check if we just hit the duplicate */
4220 dev_err(&hdev
->pdev
->dev
,
4221 "PF failed to add unicast entry(%pM) in the MAC table\n",
4227 static int hclge_rm_uc_addr(struct hnae3_handle
*handle
,
4228 const unsigned char *addr
)
4230 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4232 return hclge_rm_uc_addr_common(vport
, addr
);
4235 int hclge_rm_uc_addr_common(struct hclge_vport
*vport
,
4236 const unsigned char *addr
)
4238 struct hclge_dev
*hdev
= vport
->back
;
4239 struct hclge_mac_vlan_tbl_entry_cmd req
;
4242 /* mac addr check */
4243 if (is_zero_ether_addr(addr
) ||
4244 is_broadcast_ether_addr(addr
) ||
4245 is_multicast_ether_addr(addr
)) {
4246 dev_dbg(&hdev
->pdev
->dev
,
4247 "Remove mac err! invalid mac:%pM.\n",
4252 memset(&req
, 0, sizeof(req
));
4253 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4254 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4255 hclge_prepare_mac_addr(&req
, addr
);
4256 ret
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4261 static int hclge_add_mc_addr(struct hnae3_handle
*handle
,
4262 const unsigned char *addr
)
4264 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4266 return hclge_add_mc_addr_common(vport
, addr
);
4269 int hclge_add_mc_addr_common(struct hclge_vport
*vport
,
4270 const unsigned char *addr
)
4272 struct hclge_dev
*hdev
= vport
->back
;
4273 struct hclge_mac_vlan_tbl_entry_cmd req
;
4274 struct hclge_desc desc
[3];
4278 /* mac addr check */
4279 if (!is_multicast_ether_addr(addr
)) {
4280 dev_err(&hdev
->pdev
->dev
,
4281 "Add mc mac err! invalid mac:%pM.\n",
4285 memset(&req
, 0, sizeof(req
));
4286 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4287 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4288 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4289 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4290 hclge_prepare_mac_addr(&req
, addr
);
4291 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4293 /* This mac addr exist, update VFID for it */
4294 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4295 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4297 /* This mac addr do not exist, add new entry for it */
4298 memset(desc
[0].data
, 0, sizeof(desc
[0].data
));
4299 memset(desc
[1].data
, 0, sizeof(desc
[0].data
));
4300 memset(desc
[2].data
, 0, sizeof(desc
[0].data
));
4301 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4302 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4305 /* Set MTA table for this MAC address */
4306 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
4307 status
= hclge_set_mta_table_item(vport
, tbl_idx
, true);
4312 static int hclge_rm_mc_addr(struct hnae3_handle
*handle
,
4313 const unsigned char *addr
)
4315 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4317 return hclge_rm_mc_addr_common(vport
, addr
);
4320 int hclge_rm_mc_addr_common(struct hclge_vport
*vport
,
4321 const unsigned char *addr
)
4323 struct hclge_dev
*hdev
= vport
->back
;
4324 struct hclge_mac_vlan_tbl_entry_cmd req
;
4325 enum hclge_cmd_status status
;
4326 struct hclge_desc desc
[3];
4329 /* mac addr check */
4330 if (!is_multicast_ether_addr(addr
)) {
4331 dev_dbg(&hdev
->pdev
->dev
,
4332 "Remove mc mac err! invalid mac:%pM.\n",
4337 memset(&req
, 0, sizeof(req
));
4338 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4339 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4340 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4341 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4342 hclge_prepare_mac_addr(&req
, addr
);
4343 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4345 /* This mac addr exist, remove this handle's VFID for it */
4346 hclge_update_desc_vfid(desc
, vport
->vport_id
, true);
4348 if (hclge_is_all_function_id_zero(desc
))
4349 /* All the vfid is zero, so need to delete this entry */
4350 status
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4352 /* Not all the vfid is zero, update the vfid */
4353 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4356 /* This mac addr do not exist, can't delete it */
4357 dev_err(&hdev
->pdev
->dev
,
4358 "Rm multicast mac addr failed, ret = %d.\n",
4363 /* Set MTB table for this MAC address */
4364 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
4365 status
= hclge_set_mta_table_item(vport
, tbl_idx
, false);
4370 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev
*hdev
,
4371 u16 cmdq_resp
, u8 resp_code
)
4373 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4374 #define HCLGE_ETHERTYPE_ALREADY_ADD 1
4375 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4376 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4381 dev_err(&hdev
->pdev
->dev
,
4382 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4387 switch (resp_code
) {
4388 case HCLGE_ETHERTYPE_SUCCESS_ADD
:
4389 case HCLGE_ETHERTYPE_ALREADY_ADD
:
4392 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW
:
4393 dev_err(&hdev
->pdev
->dev
,
4394 "add mac ethertype failed for manager table overflow.\n");
4395 return_status
= -EIO
;
4397 case HCLGE_ETHERTYPE_KEY_CONFLICT
:
4398 dev_err(&hdev
->pdev
->dev
,
4399 "add mac ethertype failed for key conflict.\n");
4400 return_status
= -EIO
;
4403 dev_err(&hdev
->pdev
->dev
,
4404 "add mac ethertype failed for undefined, code=%d.\n",
4406 return_status
= -EIO
;
4409 return return_status
;
4412 static int hclge_add_mgr_tbl(struct hclge_dev
*hdev
,
4413 const struct hclge_mac_mgr_tbl_entry_cmd
*req
)
4415 struct hclge_desc desc
;
4420 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_ETHTYPE_ADD
, false);
4421 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_mgr_tbl_entry_cmd
));
4423 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4425 dev_err(&hdev
->pdev
->dev
,
4426 "add mac ethertype failed for cmd_send, ret =%d.\n",
4431 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4432 retval
= le16_to_cpu(desc
.retval
);
4434 return hclge_get_mac_ethertype_cmd_status(hdev
, retval
, resp_code
);
4437 static int init_mgr_tbl(struct hclge_dev
*hdev
)
4442 for (i
= 0; i
< ARRAY_SIZE(hclge_mgr_table
); i
++) {
4443 ret
= hclge_add_mgr_tbl(hdev
, &hclge_mgr_table
[i
]);
4445 dev_err(&hdev
->pdev
->dev
,
4446 "add mac ethertype failed, ret =%d.\n",
4455 static void hclge_get_mac_addr(struct hnae3_handle
*handle
, u8
*p
)
4457 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4458 struct hclge_dev
*hdev
= vport
->back
;
4460 ether_addr_copy(p
, hdev
->hw
.mac
.mac_addr
);
4463 static int hclge_set_mac_addr(struct hnae3_handle
*handle
, void *p
,
4466 const unsigned char *new_addr
= (const unsigned char *)p
;
4467 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4468 struct hclge_dev
*hdev
= vport
->back
;
4471 /* mac addr check */
4472 if (is_zero_ether_addr(new_addr
) ||
4473 is_broadcast_ether_addr(new_addr
) ||
4474 is_multicast_ether_addr(new_addr
)) {
4475 dev_err(&hdev
->pdev
->dev
,
4476 "Change uc mac err! invalid mac:%p.\n",
4481 if (!is_first
&& hclge_rm_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
))
4482 dev_warn(&hdev
->pdev
->dev
,
4483 "remove old uc mac address fail.\n");
4485 ret
= hclge_add_uc_addr(handle
, new_addr
);
4487 dev_err(&hdev
->pdev
->dev
,
4488 "add uc mac address fail, ret =%d.\n",
4492 hclge_add_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
))
4493 dev_err(&hdev
->pdev
->dev
,
4494 "restore uc mac address fail.\n");
4499 ret
= hclge_pause_addr_cfg(hdev
, new_addr
);
4501 dev_err(&hdev
->pdev
->dev
,
4502 "configure mac pause address fail, ret =%d.\n",
4507 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, new_addr
);
4512 static int hclge_set_vlan_filter_ctrl(struct hclge_dev
*hdev
, u8 vlan_type
,
4515 struct hclge_vlan_filter_ctrl_cmd
*req
;
4516 struct hclge_desc desc
;
4519 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_CTRL
, false);
4521 req
= (struct hclge_vlan_filter_ctrl_cmd
*)desc
.data
;
4522 req
->vlan_type
= vlan_type
;
4523 req
->vlan_fe
= filter_en
;
4525 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4527 dev_err(&hdev
->pdev
->dev
, "set vlan filter fail, ret =%d.\n",
4535 #define HCLGE_FILTER_TYPE_VF 0
4536 #define HCLGE_FILTER_TYPE_PORT 1
4538 static void hclge_enable_vlan_filter(struct hnae3_handle
*handle
, bool enable
)
4540 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4541 struct hclge_dev
*hdev
= vport
->back
;
4543 hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, enable
);
4546 int hclge_set_vf_vlan_common(struct hclge_dev
*hdev
, int vfid
,
4547 bool is_kill
, u16 vlan
, u8 qos
, __be16 proto
)
4549 #define HCLGE_MAX_VF_BYTES 16
4550 struct hclge_vlan_filter_vf_cfg_cmd
*req0
;
4551 struct hclge_vlan_filter_vf_cfg_cmd
*req1
;
4552 struct hclge_desc desc
[2];
4557 hclge_cmd_setup_basic_desc(&desc
[0],
4558 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4559 hclge_cmd_setup_basic_desc(&desc
[1],
4560 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4562 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4564 vf_byte_off
= vfid
/ 8;
4565 vf_byte_val
= 1 << (vfid
% 8);
4567 req0
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[0].data
;
4568 req1
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[1].data
;
4570 req0
->vlan_id
= cpu_to_le16(vlan
);
4571 req0
->vlan_cfg
= is_kill
;
4573 if (vf_byte_off
< HCLGE_MAX_VF_BYTES
)
4574 req0
->vf_bitmap
[vf_byte_off
] = vf_byte_val
;
4576 req1
->vf_bitmap
[vf_byte_off
- HCLGE_MAX_VF_BYTES
] = vf_byte_val
;
4578 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
4580 dev_err(&hdev
->pdev
->dev
,
4581 "Send vf vlan command fail, ret =%d.\n",
4587 if (!req0
->resp_code
|| req0
->resp_code
== 1)
4590 dev_err(&hdev
->pdev
->dev
,
4591 "Add vf vlan filter fail, ret =%d.\n",
4594 if (!req0
->resp_code
)
4597 dev_err(&hdev
->pdev
->dev
,
4598 "Kill vf vlan filter fail, ret =%d.\n",
4605 static int hclge_set_port_vlan_filter(struct hnae3_handle
*handle
,
4606 __be16 proto
, u16 vlan_id
,
4609 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4610 struct hclge_dev
*hdev
= vport
->back
;
4611 struct hclge_vlan_filter_pf_cfg_cmd
*req
;
4612 struct hclge_desc desc
;
4613 u8 vlan_offset_byte_val
;
4614 u8 vlan_offset_byte
;
4618 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_PF_CFG
, false);
4620 vlan_offset_160
= vlan_id
/ 160;
4621 vlan_offset_byte
= (vlan_id
% 160) / 8;
4622 vlan_offset_byte_val
= 1 << (vlan_id
% 8);
4624 req
= (struct hclge_vlan_filter_pf_cfg_cmd
*)desc
.data
;
4625 req
->vlan_offset
= vlan_offset_160
;
4626 req
->vlan_cfg
= is_kill
;
4627 req
->vlan_offset_bitmap
[vlan_offset_byte
] = vlan_offset_byte_val
;
4629 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4631 dev_err(&hdev
->pdev
->dev
,
4632 "port vlan command, send fail, ret =%d.\n",
4637 ret
= hclge_set_vf_vlan_common(hdev
, 0, is_kill
, vlan_id
, 0, proto
);
4639 dev_err(&hdev
->pdev
->dev
,
4640 "Set pf vlan filter config fail, ret =%d.\n",
4648 static int hclge_set_vf_vlan_filter(struct hnae3_handle
*handle
, int vfid
,
4649 u16 vlan
, u8 qos
, __be16 proto
)
4651 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4652 struct hclge_dev
*hdev
= vport
->back
;
4654 if ((vfid
>= hdev
->num_alloc_vfs
) || (vlan
> 4095) || (qos
> 7))
4656 if (proto
!= htons(ETH_P_8021Q
))
4657 return -EPROTONOSUPPORT
;
4659 return hclge_set_vf_vlan_common(hdev
, vfid
, false, vlan
, qos
, proto
);
4662 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport
*vport
)
4664 struct hclge_tx_vtag_cfg
*vcfg
= &vport
->txvlan_cfg
;
4665 struct hclge_vport_vtag_tx_cfg_cmd
*req
;
4666 struct hclge_dev
*hdev
= vport
->back
;
4667 struct hclge_desc desc
;
4670 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_TX_CFG
, false);
4672 req
= (struct hclge_vport_vtag_tx_cfg_cmd
*)desc
.data
;
4673 req
->def_vlan_tag1
= cpu_to_le16(vcfg
->default_tag1
);
4674 req
->def_vlan_tag2
= cpu_to_le16(vcfg
->default_tag2
);
4675 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_TAG_B
,
4676 vcfg
->accept_tag
? 1 : 0);
4677 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_UNTAG_B
,
4678 vcfg
->accept_untag
? 1 : 0);
4679 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG1_EN_B
,
4680 vcfg
->insert_tag1_en
? 1 : 0);
4681 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG2_EN_B
,
4682 vcfg
->insert_tag2_en
? 1 : 0);
4683 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_CFG_NIC_ROCE_SEL_B
, 0);
4685 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4686 req
->vf_bitmap
[req
->vf_offset
] =
4687 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4689 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4691 dev_err(&hdev
->pdev
->dev
,
4692 "Send port txvlan cfg command fail, ret =%d\n",
4698 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport
*vport
)
4700 struct hclge_rx_vtag_cfg
*vcfg
= &vport
->rxvlan_cfg
;
4701 struct hclge_vport_vtag_rx_cfg_cmd
*req
;
4702 struct hclge_dev
*hdev
= vport
->back
;
4703 struct hclge_desc desc
;
4706 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_RX_CFG
, false);
4708 req
= (struct hclge_vport_vtag_rx_cfg_cmd
*)desc
.data
;
4709 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG1_EN_B
,
4710 vcfg
->strip_tag1_en
? 1 : 0);
4711 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG2_EN_B
,
4712 vcfg
->strip_tag2_en
? 1 : 0);
4713 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG1_EN_B
,
4714 vcfg
->vlan1_vlan_prionly
? 1 : 0);
4715 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG2_EN_B
,
4716 vcfg
->vlan2_vlan_prionly
? 1 : 0);
4718 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4719 req
->vf_bitmap
[req
->vf_offset
] =
4720 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4722 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4724 dev_err(&hdev
->pdev
->dev
,
4725 "Send port rxvlan cfg command fail, ret =%d\n",
4731 static int hclge_set_vlan_protocol_type(struct hclge_dev
*hdev
)
4733 struct hclge_rx_vlan_type_cfg_cmd
*rx_req
;
4734 struct hclge_tx_vlan_type_cfg_cmd
*tx_req
;
4735 struct hclge_desc desc
;
4738 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_TYPE_ID
, false);
4739 rx_req
= (struct hclge_rx_vlan_type_cfg_cmd
*)desc
.data
;
4740 rx_req
->ot_fst_vlan_type
=
4741 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
);
4742 rx_req
->ot_sec_vlan_type
=
4743 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
);
4744 rx_req
->in_fst_vlan_type
=
4745 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
);
4746 rx_req
->in_sec_vlan_type
=
4747 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
);
4749 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4751 dev_err(&hdev
->pdev
->dev
,
4752 "Send rxvlan protocol type command fail, ret =%d\n",
4757 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_INSERT
, false);
4759 tx_req
= (struct hclge_tx_vlan_type_cfg_cmd
*)&desc
.data
;
4760 tx_req
->ot_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_ot_vlan_type
);
4761 tx_req
->in_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_in_vlan_type
);
4763 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4765 dev_err(&hdev
->pdev
->dev
,
4766 "Send txvlan protocol type command fail, ret =%d\n",
4772 static int hclge_init_vlan_config(struct hclge_dev
*hdev
)
4774 #define HCLGE_DEF_VLAN_TYPE 0x8100
4776 struct hnae3_handle
*handle
;
4777 struct hclge_vport
*vport
;
4781 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, true);
4785 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_PORT
, true);
4789 hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4790 hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4791 hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4792 hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4793 hdev
->vlan_type_cfg
.tx_ot_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4794 hdev
->vlan_type_cfg
.tx_in_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4796 ret
= hclge_set_vlan_protocol_type(hdev
);
4800 for (i
= 0; i
< hdev
->num_alloc_vport
; i
++) {
4801 vport
= &hdev
->vport
[i
];
4802 vport
->txvlan_cfg
.accept_tag
= true;
4803 vport
->txvlan_cfg
.accept_untag
= true;
4804 vport
->txvlan_cfg
.insert_tag1_en
= false;
4805 vport
->txvlan_cfg
.insert_tag2_en
= false;
4806 vport
->txvlan_cfg
.default_tag1
= 0;
4807 vport
->txvlan_cfg
.default_tag2
= 0;
4809 ret
= hclge_set_vlan_tx_offload_cfg(vport
);
4813 vport
->rxvlan_cfg
.strip_tag1_en
= false;
4814 vport
->rxvlan_cfg
.strip_tag2_en
= true;
4815 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
4816 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
4818 ret
= hclge_set_vlan_rx_offload_cfg(vport
);
4823 handle
= &hdev
->vport
[0].nic
;
4824 return hclge_set_port_vlan_filter(handle
, htons(ETH_P_8021Q
), 0, false);
4827 static int hclge_en_hw_strip_rxvtag(struct hnae3_handle
*handle
, bool enable
)
4829 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4831 vport
->rxvlan_cfg
.strip_tag1_en
= false;
4832 vport
->rxvlan_cfg
.strip_tag2_en
= enable
;
4833 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
4834 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
4836 return hclge_set_vlan_rx_offload_cfg(vport
);
4839 static int hclge_set_mac_mtu(struct hclge_dev
*hdev
, int new_mtu
)
4841 struct hclge_config_max_frm_size_cmd
*req
;
4842 struct hclge_desc desc
;
4846 max_frm_size
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
;
4848 if (max_frm_size
< HCLGE_MAC_MIN_FRAME
||
4849 max_frm_size
> HCLGE_MAC_MAX_FRAME
)
4852 max_frm_size
= max(max_frm_size
, HCLGE_MAC_DEFAULT_FRAME
);
4854 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAX_FRM_SIZE
, false);
4856 req
= (struct hclge_config_max_frm_size_cmd
*)desc
.data
;
4857 req
->max_frm_size
= cpu_to_le16(max_frm_size
);
4859 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4861 dev_err(&hdev
->pdev
->dev
, "set mtu fail, ret =%d.\n", ret
);
4865 hdev
->mps
= max_frm_size
;
4870 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
)
4872 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4873 struct hclge_dev
*hdev
= vport
->back
;
4876 ret
= hclge_set_mac_mtu(hdev
, new_mtu
);
4878 dev_err(&hdev
->pdev
->dev
,
4879 "Change mtu fail, ret =%d\n", ret
);
4883 ret
= hclge_buffer_alloc(hdev
);
4885 dev_err(&hdev
->pdev
->dev
,
4886 "Allocate buffer fail, ret =%d\n", ret
);
4891 static int hclge_send_reset_tqp_cmd(struct hclge_dev
*hdev
, u16 queue_id
,
4894 struct hclge_reset_tqp_queue_cmd
*req
;
4895 struct hclge_desc desc
;
4898 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, false);
4900 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
4901 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
4902 hnae_set_bit(req
->reset_req
, HCLGE_TQP_RESET_B
, enable
);
4904 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4906 dev_err(&hdev
->pdev
->dev
,
4907 "Send tqp reset cmd error, status =%d\n", ret
);
4914 static int hclge_get_reset_status(struct hclge_dev
*hdev
, u16 queue_id
)
4916 struct hclge_reset_tqp_queue_cmd
*req
;
4917 struct hclge_desc desc
;
4920 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, true);
4922 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
4923 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
4925 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4927 dev_err(&hdev
->pdev
->dev
,
4928 "Get reset status error, status =%d\n", ret
);
4932 return hnae_get_bit(req
->ready_to_reset
, HCLGE_TQP_RESET_B
);
4935 static u16
hclge_covert_handle_qid_global(struct hnae3_handle
*handle
,
4938 struct hnae3_queue
*queue
;
4939 struct hclge_tqp
*tqp
;
4941 queue
= handle
->kinfo
.tqp
[queue_id
];
4942 tqp
= container_of(queue
, struct hclge_tqp
, q
);
4947 void hclge_reset_tqp(struct hnae3_handle
*handle
, u16 queue_id
)
4949 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4950 struct hclge_dev
*hdev
= vport
->back
;
4951 int reset_try_times
= 0;
4956 if (test_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
4959 queue_gid
= hclge_covert_handle_qid_global(handle
, queue_id
);
4961 ret
= hclge_tqp_enable(hdev
, queue_id
, 0, false);
4963 dev_warn(&hdev
->pdev
->dev
, "Disable tqp fail, ret = %d\n", ret
);
4967 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, true);
4969 dev_warn(&hdev
->pdev
->dev
,
4970 "Send reset tqp cmd fail, ret = %d\n", ret
);
4974 reset_try_times
= 0;
4975 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
4976 /* Wait for tqp hw reset */
4978 reset_status
= hclge_get_reset_status(hdev
, queue_gid
);
4983 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
4984 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
4988 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, false);
4990 dev_warn(&hdev
->pdev
->dev
,
4991 "Deassert the soft reset fail, ret = %d\n", ret
);
4996 void hclge_reset_vf_queue(struct hclge_vport
*vport
, u16 queue_id
)
4998 struct hclge_dev
*hdev
= vport
->back
;
4999 int reset_try_times
= 0;
5004 queue_gid
= hclge_covert_handle_qid_global(&vport
->nic
, queue_id
);
5006 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, true);
5008 dev_warn(&hdev
->pdev
->dev
,
5009 "Send reset tqp cmd fail, ret = %d\n", ret
);
5013 reset_try_times
= 0;
5014 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
5015 /* Wait for tqp hw reset */
5017 reset_status
= hclge_get_reset_status(hdev
, queue_gid
);
5022 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
5023 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
5027 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, false);
5029 dev_warn(&hdev
->pdev
->dev
,
5030 "Deassert the soft reset fail, ret = %d\n", ret
);
5033 static u32
hclge_get_fw_version(struct hnae3_handle
*handle
)
5035 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5036 struct hclge_dev
*hdev
= vport
->back
;
5038 return hdev
->fw_version
;
5041 static void hclge_get_flowctrl_adv(struct hnae3_handle
*handle
,
5044 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5045 struct hclge_dev
*hdev
= vport
->back
;
5046 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5051 *flowctrl_adv
|= (phydev
->advertising
& ADVERTISED_Pause
) |
5052 (phydev
->advertising
& ADVERTISED_Asym_Pause
);
5055 static void hclge_set_flowctrl_adv(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
5057 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5062 phydev
->advertising
&= ~(ADVERTISED_Pause
| ADVERTISED_Asym_Pause
);
5065 phydev
->advertising
|= ADVERTISED_Pause
| ADVERTISED_Asym_Pause
;
5068 phydev
->advertising
^= ADVERTISED_Asym_Pause
;
5071 static int hclge_cfg_pauseparam(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
5076 hdev
->fc_mode_last_time
= HCLGE_FC_FULL
;
5077 else if (rx_en
&& !tx_en
)
5078 hdev
->fc_mode_last_time
= HCLGE_FC_RX_PAUSE
;
5079 else if (!rx_en
&& tx_en
)
5080 hdev
->fc_mode_last_time
= HCLGE_FC_TX_PAUSE
;
5082 hdev
->fc_mode_last_time
= HCLGE_FC_NONE
;
5084 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
)
5087 ret
= hclge_mac_pause_en_cfg(hdev
, tx_en
, rx_en
);
5089 dev_err(&hdev
->pdev
->dev
, "configure pauseparam error, ret = %d.\n",
5094 hdev
->tm_info
.fc_mode
= hdev
->fc_mode_last_time
;
5099 int hclge_cfg_flowctrl(struct hclge_dev
*hdev
)
5101 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5102 u16 remote_advertising
= 0;
5103 u16 local_advertising
= 0;
5104 u32 rx_pause
, tx_pause
;
5107 if (!phydev
->link
|| !phydev
->autoneg
)
5110 if (phydev
->advertising
& ADVERTISED_Pause
)
5111 local_advertising
= ADVERTISE_PAUSE_CAP
;
5113 if (phydev
->advertising
& ADVERTISED_Asym_Pause
)
5114 local_advertising
|= ADVERTISE_PAUSE_ASYM
;
5117 remote_advertising
= LPA_PAUSE_CAP
;
5119 if (phydev
->asym_pause
)
5120 remote_advertising
|= LPA_PAUSE_ASYM
;
5122 flowctl
= mii_resolve_flowctrl_fdx(local_advertising
,
5123 remote_advertising
);
5124 tx_pause
= flowctl
& FLOW_CTRL_TX
;
5125 rx_pause
= flowctl
& FLOW_CTRL_RX
;
5127 if (phydev
->duplex
== HCLGE_MAC_HALF
) {
5132 return hclge_cfg_pauseparam(hdev
, rx_pause
, tx_pause
);
5135 static void hclge_get_pauseparam(struct hnae3_handle
*handle
, u32
*auto_neg
,
5136 u32
*rx_en
, u32
*tx_en
)
5138 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5139 struct hclge_dev
*hdev
= vport
->back
;
5141 *auto_neg
= hclge_get_autoneg(handle
);
5143 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
5149 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_RX_PAUSE
) {
5152 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_TX_PAUSE
) {
5155 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_FULL
) {
5164 static int hclge_set_pauseparam(struct hnae3_handle
*handle
, u32 auto_neg
,
5165 u32 rx_en
, u32 tx_en
)
5167 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5168 struct hclge_dev
*hdev
= vport
->back
;
5169 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5172 fc_autoneg
= hclge_get_autoneg(handle
);
5173 if (auto_neg
!= fc_autoneg
) {
5174 dev_info(&hdev
->pdev
->dev
,
5175 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5179 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
5180 dev_info(&hdev
->pdev
->dev
,
5181 "Priority flow control enabled. Cannot set link flow control.\n");
5185 hclge_set_flowctrl_adv(hdev
, rx_en
, tx_en
);
5188 return hclge_cfg_pauseparam(hdev
, rx_en
, tx_en
);
5190 /* Only support flow control negotiation for netdev with
5191 * phy attached for now.
5196 return phy_start_aneg(phydev
);
5199 static void hclge_get_ksettings_an_result(struct hnae3_handle
*handle
,
5200 u8
*auto_neg
, u32
*speed
, u8
*duplex
)
5202 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5203 struct hclge_dev
*hdev
= vport
->back
;
5206 *speed
= hdev
->hw
.mac
.speed
;
5208 *duplex
= hdev
->hw
.mac
.duplex
;
5210 *auto_neg
= hdev
->hw
.mac
.autoneg
;
5213 static void hclge_get_media_type(struct hnae3_handle
*handle
, u8
*media_type
)
5215 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5216 struct hclge_dev
*hdev
= vport
->back
;
5219 *media_type
= hdev
->hw
.mac
.media_type
;
5222 static void hclge_get_mdix_mode(struct hnae3_handle
*handle
,
5223 u8
*tp_mdix_ctrl
, u8
*tp_mdix
)
5225 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5226 struct hclge_dev
*hdev
= vport
->back
;
5227 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5228 int mdix_ctrl
, mdix
, retval
, is_resolved
;
5231 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
5232 *tp_mdix
= ETH_TP_MDI_INVALID
;
5236 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_MDIX
);
5238 retval
= phy_read(phydev
, HCLGE_PHY_CSC_REG
);
5239 mdix_ctrl
= hnae_get_field(retval
, HCLGE_PHY_MDIX_CTRL_M
,
5240 HCLGE_PHY_MDIX_CTRL_S
);
5242 retval
= phy_read(phydev
, HCLGE_PHY_CSS_REG
);
5243 mdix
= hnae_get_bit(retval
, HCLGE_PHY_MDIX_STATUS_B
);
5244 is_resolved
= hnae_get_bit(retval
, HCLGE_PHY_SPEED_DUP_RESOLVE_B
);
5246 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_COPPER
);
5248 switch (mdix_ctrl
) {
5250 *tp_mdix_ctrl
= ETH_TP_MDI
;
5253 *tp_mdix_ctrl
= ETH_TP_MDI_X
;
5256 *tp_mdix_ctrl
= ETH_TP_MDI_AUTO
;
5259 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
5264 *tp_mdix
= ETH_TP_MDI_INVALID
;
5266 *tp_mdix
= ETH_TP_MDI_X
;
5268 *tp_mdix
= ETH_TP_MDI
;
5271 static int hclge_init_client_instance(struct hnae3_client
*client
,
5272 struct hnae3_ae_dev
*ae_dev
)
5274 struct hclge_dev
*hdev
= ae_dev
->priv
;
5275 struct hclge_vport
*vport
;
5278 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
5279 vport
= &hdev
->vport
[i
];
5281 switch (client
->type
) {
5282 case HNAE3_CLIENT_KNIC
:
5284 hdev
->nic_client
= client
;
5285 vport
->nic
.client
= client
;
5286 ret
= client
->ops
->init_instance(&vport
->nic
);
5290 if (hdev
->roce_client
&&
5291 hnae3_dev_roce_supported(hdev
)) {
5292 struct hnae3_client
*rc
= hdev
->roce_client
;
5294 ret
= hclge_init_roce_base_info(vport
);
5298 ret
= rc
->ops
->init_instance(&vport
->roce
);
5304 case HNAE3_CLIENT_UNIC
:
5305 hdev
->nic_client
= client
;
5306 vport
->nic
.client
= client
;
5308 ret
= client
->ops
->init_instance(&vport
->nic
);
5313 case HNAE3_CLIENT_ROCE
:
5314 if (hnae3_dev_roce_supported(hdev
)) {
5315 hdev
->roce_client
= client
;
5316 vport
->roce
.client
= client
;
5319 if (hdev
->roce_client
&& hdev
->nic_client
) {
5320 ret
= hclge_init_roce_base_info(vport
);
5324 ret
= client
->ops
->init_instance(&vport
->roce
);
5336 static void hclge_uninit_client_instance(struct hnae3_client
*client
,
5337 struct hnae3_ae_dev
*ae_dev
)
5339 struct hclge_dev
*hdev
= ae_dev
->priv
;
5340 struct hclge_vport
*vport
;
5343 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
5344 vport
= &hdev
->vport
[i
];
5345 if (hdev
->roce_client
) {
5346 hdev
->roce_client
->ops
->uninit_instance(&vport
->roce
,
5348 hdev
->roce_client
= NULL
;
5349 vport
->roce
.client
= NULL
;
5351 if (client
->type
== HNAE3_CLIENT_ROCE
)
5353 if (client
->ops
->uninit_instance
) {
5354 client
->ops
->uninit_instance(&vport
->nic
, 0);
5355 hdev
->nic_client
= NULL
;
5356 vport
->nic
.client
= NULL
;
5361 static int hclge_pci_init(struct hclge_dev
*hdev
)
5363 struct pci_dev
*pdev
= hdev
->pdev
;
5364 struct hclge_hw
*hw
;
5367 ret
= pci_enable_device(pdev
);
5369 dev_err(&pdev
->dev
, "failed to enable PCI device\n");
5370 goto err_no_drvdata
;
5373 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64));
5375 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32));
5378 "can't set consistent PCI DMA");
5379 goto err_disable_device
;
5381 dev_warn(&pdev
->dev
, "set DMA mask to 32 bits\n");
5384 ret
= pci_request_regions(pdev
, HCLGE_DRIVER_NAME
);
5386 dev_err(&pdev
->dev
, "PCI request regions failed %d\n", ret
);
5387 goto err_disable_device
;
5390 pci_set_master(pdev
);
5393 hw
->io_base
= pcim_iomap(pdev
, 2, 0);
5395 dev_err(&pdev
->dev
, "Can't map configuration register space\n");
5397 goto err_clr_master
;
5400 hdev
->num_req_vfs
= pci_sriov_get_totalvfs(pdev
);
5404 pci_clear_master(pdev
);
5405 pci_release_regions(pdev
);
5407 pci_disable_device(pdev
);
5409 pci_set_drvdata(pdev
, NULL
);
5414 static void hclge_pci_uninit(struct hclge_dev
*hdev
)
5416 struct pci_dev
*pdev
= hdev
->pdev
;
5418 pci_free_irq_vectors(pdev
);
5419 pci_clear_master(pdev
);
5420 pci_release_mem_regions(pdev
);
5421 pci_disable_device(pdev
);
5424 static int hclge_init_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5426 struct pci_dev
*pdev
= ae_dev
->pdev
;
5427 struct hclge_dev
*hdev
;
5430 hdev
= devm_kzalloc(&pdev
->dev
, sizeof(*hdev
), GFP_KERNEL
);
5437 hdev
->ae_dev
= ae_dev
;
5438 hdev
->reset_type
= HNAE3_NONE_RESET
;
5439 hdev
->reset_request
= 0;
5440 hdev
->reset_pending
= 0;
5441 ae_dev
->priv
= hdev
;
5443 ret
= hclge_pci_init(hdev
);
5445 dev_err(&pdev
->dev
, "PCI init failed\n");
5449 /* Firmware command queue initialize */
5450 ret
= hclge_cmd_queue_init(hdev
);
5452 dev_err(&pdev
->dev
, "Cmd queue init failed, ret = %d.\n", ret
);
5453 goto err_pci_uninit
;
5456 /* Firmware command initialize */
5457 ret
= hclge_cmd_init(hdev
);
5459 goto err_cmd_uninit
;
5461 ret
= hclge_get_cap(hdev
);
5463 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5465 goto err_cmd_uninit
;
5468 ret
= hclge_configure(hdev
);
5470 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5471 goto err_cmd_uninit
;
5474 ret
= hclge_init_msi(hdev
);
5476 dev_err(&pdev
->dev
, "Init MSI/MSI-X error, ret = %d.\n", ret
);
5477 goto err_cmd_uninit
;
5480 ret
= hclge_misc_irq_init(hdev
);
5483 "Misc IRQ(vector0) init error, ret = %d.\n",
5485 goto err_msi_uninit
;
5488 ret
= hclge_alloc_tqps(hdev
);
5490 dev_err(&pdev
->dev
, "Allocate TQPs error, ret = %d.\n", ret
);
5491 goto err_msi_irq_uninit
;
5494 ret
= hclge_alloc_vport(hdev
);
5496 dev_err(&pdev
->dev
, "Allocate vport error, ret = %d.\n", ret
);
5497 goto err_msi_irq_uninit
;
5500 ret
= hclge_map_tqp(hdev
);
5502 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5503 goto err_sriov_disable
;
5506 if (hdev
->hw
.mac
.media_type
== HNAE3_MEDIA_TYPE_COPPER
) {
5507 ret
= hclge_mac_mdio_config(hdev
);
5509 dev_err(&hdev
->pdev
->dev
,
5510 "mdio config fail ret=%d\n", ret
);
5511 goto err_sriov_disable
;
5515 ret
= hclge_mac_init(hdev
);
5517 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5518 goto err_mdiobus_unreg
;
5521 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5523 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5524 goto err_mdiobus_unreg
;
5527 ret
= hclge_init_vlan_config(hdev
);
5529 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5530 goto err_mdiobus_unreg
;
5533 ret
= hclge_tm_schd_init(hdev
);
5535 dev_err(&pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5536 goto err_mdiobus_unreg
;
5539 hclge_rss_init_cfg(hdev
);
5540 ret
= hclge_rss_init_hw(hdev
);
5542 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5543 goto err_mdiobus_unreg
;
5546 ret
= init_mgr_tbl(hdev
);
5548 dev_err(&pdev
->dev
, "manager table init fail, ret =%d\n", ret
);
5549 goto err_mdiobus_unreg
;
5552 hclge_dcb_ops_set(hdev
);
5554 timer_setup(&hdev
->service_timer
, hclge_service_timer
, 0);
5555 INIT_WORK(&hdev
->service_task
, hclge_service_task
);
5556 INIT_WORK(&hdev
->rst_service_task
, hclge_reset_service_task
);
5557 INIT_WORK(&hdev
->mbx_service_task
, hclge_mailbox_service_task
);
5559 /* Enable MISC vector(vector0) */
5560 hclge_enable_vector(&hdev
->misc_vector
, true);
5562 set_bit(HCLGE_STATE_SERVICE_INITED
, &hdev
->state
);
5563 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5564 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
5565 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
5566 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
5567 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
5569 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME
);
5573 if (hdev
->hw
.mac
.phydev
)
5574 mdiobus_unregister(hdev
->hw
.mac
.mdio_bus
);
5576 if (IS_ENABLED(CONFIG_PCI_IOV
))
5577 hclge_disable_sriov(hdev
);
5579 hclge_misc_irq_uninit(hdev
);
5581 pci_free_irq_vectors(pdev
);
5583 hclge_destroy_cmd_queue(&hdev
->hw
);
5585 pci_clear_master(pdev
);
5586 pci_release_regions(pdev
);
5587 pci_disable_device(pdev
);
5588 pci_set_drvdata(pdev
, NULL
);
5593 static void hclge_stats_clear(struct hclge_dev
*hdev
)
5595 memset(&hdev
->hw_stats
, 0, sizeof(hdev
->hw_stats
));
5598 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5600 struct hclge_dev
*hdev
= ae_dev
->priv
;
5601 struct pci_dev
*pdev
= ae_dev
->pdev
;
5604 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5606 hclge_stats_clear(hdev
);
5608 ret
= hclge_cmd_init(hdev
);
5610 dev_err(&pdev
->dev
, "Cmd queue init failed\n");
5614 ret
= hclge_get_cap(hdev
);
5616 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5621 ret
= hclge_configure(hdev
);
5623 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5627 ret
= hclge_map_tqp(hdev
);
5629 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5633 ret
= hclge_mac_init(hdev
);
5635 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5639 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5641 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5645 ret
= hclge_init_vlan_config(hdev
);
5647 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5651 ret
= hclge_tm_init_hw(hdev
);
5653 dev_err(&pdev
->dev
, "tm init hw fail, ret =%d\n", ret
);
5657 ret
= hclge_rss_init_hw(hdev
);
5659 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5663 /* Enable MISC vector(vector0) */
5664 hclge_enable_vector(&hdev
->misc_vector
, true);
5666 dev_info(&pdev
->dev
, "Reset done, %s driver initialization finished.\n",
5672 static void hclge_uninit_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5674 struct hclge_dev
*hdev
= ae_dev
->priv
;
5675 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
5677 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5679 if (IS_ENABLED(CONFIG_PCI_IOV
))
5680 hclge_disable_sriov(hdev
);
5682 if (hdev
->service_timer
.function
)
5683 del_timer_sync(&hdev
->service_timer
);
5684 if (hdev
->service_task
.func
)
5685 cancel_work_sync(&hdev
->service_task
);
5686 if (hdev
->rst_service_task
.func
)
5687 cancel_work_sync(&hdev
->rst_service_task
);
5688 if (hdev
->mbx_service_task
.func
)
5689 cancel_work_sync(&hdev
->mbx_service_task
);
5692 mdiobus_unregister(mac
->mdio_bus
);
5694 /* Disable MISC vector(vector0) */
5695 hclge_enable_vector(&hdev
->misc_vector
, false);
5696 hclge_destroy_cmd_queue(&hdev
->hw
);
5697 hclge_misc_irq_uninit(hdev
);
5698 hclge_pci_uninit(hdev
);
5699 ae_dev
->priv
= NULL
;
5702 static u32
hclge_get_max_channels(struct hnae3_handle
*handle
)
5704 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
5705 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5706 struct hclge_dev
*hdev
= vport
->back
;
5708 return min_t(u32
, hdev
->rss_size_max
* kinfo
->num_tc
, hdev
->num_tqps
);
5711 static void hclge_get_channels(struct hnae3_handle
*handle
,
5712 struct ethtool_channels
*ch
)
5714 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5716 ch
->max_combined
= hclge_get_max_channels(handle
);
5717 ch
->other_count
= 1;
5719 ch
->combined_count
= vport
->alloc_tqps
;
5722 static void hclge_get_tqps_and_rss_info(struct hnae3_handle
*handle
,
5723 u16
*free_tqps
, u16
*max_rss_size
)
5725 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5726 struct hclge_dev
*hdev
= vport
->back
;
5730 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
5731 if (!hdev
->htqp
[i
].alloced
)
5734 *free_tqps
= temp_tqps
;
5735 *max_rss_size
= hdev
->rss_size_max
;
5738 static void hclge_release_tqp(struct hclge_vport
*vport
)
5740 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5741 struct hclge_dev
*hdev
= vport
->back
;
5744 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
5745 struct hclge_tqp
*tqp
=
5746 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
5748 tqp
->q
.handle
= NULL
;
5749 tqp
->q
.tqp_index
= 0;
5750 tqp
->alloced
= false;
5753 devm_kfree(&hdev
->pdev
->dev
, kinfo
->tqp
);
5757 static int hclge_set_channels(struct hnae3_handle
*handle
, u32 new_tqps_num
)
5759 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5760 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5761 struct hclge_dev
*hdev
= vport
->back
;
5762 int cur_rss_size
= kinfo
->rss_size
;
5763 int cur_tqps
= kinfo
->num_tqps
;
5764 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
5765 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
5766 u16 tc_size
[HCLGE_MAX_TC_NUM
];
5771 hclge_release_tqp(vport
);
5773 ret
= hclge_knic_setup(vport
, new_tqps_num
);
5775 dev_err(&hdev
->pdev
->dev
, "setup nic fail, ret =%d\n", ret
);
5779 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
5781 dev_err(&hdev
->pdev
->dev
, "map vport tqp fail, ret =%d\n", ret
);
5785 ret
= hclge_tm_schd_init(hdev
);
5787 dev_err(&hdev
->pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5791 roundup_size
= roundup_pow_of_two(kinfo
->rss_size
);
5792 roundup_size
= ilog2(roundup_size
);
5793 /* Set the RSS TC mode according to the new RSS size */
5794 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
5797 if (!(hdev
->hw_tc_map
& BIT(i
)))
5801 tc_size
[i
] = roundup_size
;
5802 tc_offset
[i
] = kinfo
->rss_size
* i
;
5804 ret
= hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
5808 /* Reinitializes the rss indirect table according to the new RSS size */
5809 rss_indir
= kcalloc(HCLGE_RSS_IND_TBL_SIZE
, sizeof(u32
), GFP_KERNEL
);
5813 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
5814 rss_indir
[i
] = i
% kinfo
->rss_size
;
5816 ret
= hclge_set_rss(handle
, rss_indir
, NULL
, 0);
5818 dev_err(&hdev
->pdev
->dev
, "set rss indir table fail, ret=%d\n",
5824 dev_info(&hdev
->pdev
->dev
,
5825 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5826 cur_rss_size
, kinfo
->rss_size
,
5827 cur_tqps
, kinfo
->rss_size
* kinfo
->num_tc
);
5832 static int hclge_get_regs_num(struct hclge_dev
*hdev
, u32
*regs_num_32_bit
,
5833 u32
*regs_num_64_bit
)
5835 struct hclge_desc desc
;
5839 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_REG_NUM
, true);
5840 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5842 dev_err(&hdev
->pdev
->dev
,
5843 "Query register number cmd failed, ret = %d.\n", ret
);
5847 *regs_num_32_bit
= le32_to_cpu(desc
.data
[0]);
5848 *regs_num_64_bit
= le32_to_cpu(desc
.data
[1]);
5850 total_num
= *regs_num_32_bit
+ *regs_num_64_bit
;
5857 static int hclge_get_32_bit_regs(struct hclge_dev
*hdev
, u32 regs_num
,
5860 #define HCLGE_32_BIT_REG_RTN_DATANUM 8
5862 struct hclge_desc
*desc
;
5863 u32
*reg_val
= data
;
5872 cmd_num
= DIV_ROUND_UP(regs_num
+ 2, HCLGE_32_BIT_REG_RTN_DATANUM
);
5873 desc
= kcalloc(cmd_num
, sizeof(struct hclge_desc
), GFP_KERNEL
);
5877 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_QUERY_32_BIT_REG
, true);
5878 ret
= hclge_cmd_send(&hdev
->hw
, desc
, cmd_num
);
5880 dev_err(&hdev
->pdev
->dev
,
5881 "Query 32 bit register cmd failed, ret = %d.\n", ret
);
5886 for (i
= 0; i
< cmd_num
; i
++) {
5888 desc_data
= (__le32
*)(&desc
[i
].data
[0]);
5889 n
= HCLGE_32_BIT_REG_RTN_DATANUM
- 2;
5891 desc_data
= (__le32
*)(&desc
[i
]);
5892 n
= HCLGE_32_BIT_REG_RTN_DATANUM
;
5894 for (k
= 0; k
< n
; k
++) {
5895 *reg_val
++ = le32_to_cpu(*desc_data
++);
5907 static int hclge_get_64_bit_regs(struct hclge_dev
*hdev
, u32 regs_num
,
5910 #define HCLGE_64_BIT_REG_RTN_DATANUM 4
5912 struct hclge_desc
*desc
;
5913 u64
*reg_val
= data
;
5922 cmd_num
= DIV_ROUND_UP(regs_num
+ 1, HCLGE_64_BIT_REG_RTN_DATANUM
);
5923 desc
= kcalloc(cmd_num
, sizeof(struct hclge_desc
), GFP_KERNEL
);
5927 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_QUERY_64_BIT_REG
, true);
5928 ret
= hclge_cmd_send(&hdev
->hw
, desc
, cmd_num
);
5930 dev_err(&hdev
->pdev
->dev
,
5931 "Query 64 bit register cmd failed, ret = %d.\n", ret
);
5936 for (i
= 0; i
< cmd_num
; i
++) {
5938 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
5939 n
= HCLGE_64_BIT_REG_RTN_DATANUM
- 1;
5941 desc_data
= (__le64
*)(&desc
[i
]);
5942 n
= HCLGE_64_BIT_REG_RTN_DATANUM
;
5944 for (k
= 0; k
< n
; k
++) {
5945 *reg_val
++ = le64_to_cpu(*desc_data
++);
5957 static int hclge_get_regs_len(struct hnae3_handle
*handle
)
5959 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5960 struct hclge_dev
*hdev
= vport
->back
;
5961 u32 regs_num_32_bit
, regs_num_64_bit
;
5964 ret
= hclge_get_regs_num(hdev
, ®s_num_32_bit
, ®s_num_64_bit
);
5966 dev_err(&hdev
->pdev
->dev
,
5967 "Get register number failed, ret = %d.\n", ret
);
5971 return regs_num_32_bit
* sizeof(u32
) + regs_num_64_bit
* sizeof(u64
);
5974 static void hclge_get_regs(struct hnae3_handle
*handle
, u32
*version
,
5977 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5978 struct hclge_dev
*hdev
= vport
->back
;
5979 u32 regs_num_32_bit
, regs_num_64_bit
;
5982 *version
= hdev
->fw_version
;
5984 ret
= hclge_get_regs_num(hdev
, ®s_num_32_bit
, ®s_num_64_bit
);
5986 dev_err(&hdev
->pdev
->dev
,
5987 "Get register number failed, ret = %d.\n", ret
);
5991 ret
= hclge_get_32_bit_regs(hdev
, regs_num_32_bit
, data
);
5993 dev_err(&hdev
->pdev
->dev
,
5994 "Get 32 bit register failed, ret = %d.\n", ret
);
5998 data
= (u32
*)data
+ regs_num_32_bit
;
5999 ret
= hclge_get_64_bit_regs(hdev
, regs_num_64_bit
,
6002 dev_err(&hdev
->pdev
->dev
,
6003 "Get 64 bit register failed, ret = %d.\n", ret
);
6006 static int hclge_set_led_status_sfp(struct hclge_dev
*hdev
, u8 speed_led_status
,
6007 u8 act_led_status
, u8 link_led_status
,
6008 u8 locate_led_status
)
6010 struct hclge_set_led_state_cmd
*req
;
6011 struct hclge_desc desc
;
6014 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_LED_STATUS_CFG
, false);
6016 req
= (struct hclge_set_led_state_cmd
*)desc
.data
;
6017 hnae_set_field(req
->port_speed_led_config
, HCLGE_LED_PORT_SPEED_STATE_M
,
6018 HCLGE_LED_PORT_SPEED_STATE_S
, speed_led_status
);
6019 hnae_set_field(req
->link_led_config
, HCLGE_LED_ACTIVITY_STATE_M
,
6020 HCLGE_LED_ACTIVITY_STATE_S
, act_led_status
);
6021 hnae_set_field(req
->activity_led_config
, HCLGE_LED_LINK_STATE_M
,
6022 HCLGE_LED_LINK_STATE_S
, link_led_status
);
6023 hnae_set_field(req
->locate_led_config
, HCLGE_LED_LOCATE_STATE_M
,
6024 HCLGE_LED_LOCATE_STATE_S
, locate_led_status
);
6026 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
6028 dev_err(&hdev
->pdev
->dev
,
6029 "Send set led state cmd error, ret =%d\n", ret
);
6034 enum hclge_led_status
{
6037 HCLGE_LED_NO_CHANGE
= 0xFF,
6040 static int hclge_set_led_id(struct hnae3_handle
*handle
,
6041 enum ethtool_phys_id_state status
)
6043 #define BLINK_FREQUENCY 2
6044 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6045 struct hclge_dev
*hdev
= vport
->back
;
6046 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
6049 if (phydev
|| hdev
->hw
.mac
.media_type
!= HNAE3_MEDIA_TYPE_FIBER
)
6053 case ETHTOOL_ID_ACTIVE
:
6054 ret
= hclge_set_led_status_sfp(hdev
,
6055 HCLGE_LED_NO_CHANGE
,
6056 HCLGE_LED_NO_CHANGE
,
6057 HCLGE_LED_NO_CHANGE
,
6060 case ETHTOOL_ID_INACTIVE
:
6061 ret
= hclge_set_led_status_sfp(hdev
,
6062 HCLGE_LED_NO_CHANGE
,
6063 HCLGE_LED_NO_CHANGE
,
6064 HCLGE_LED_NO_CHANGE
,
6075 enum hclge_led_port_speed
{
6076 HCLGE_SPEED_LED_FOR_1G
,
6077 HCLGE_SPEED_LED_FOR_10G
,
6078 HCLGE_SPEED_LED_FOR_25G
,
6079 HCLGE_SPEED_LED_FOR_40G
,
6080 HCLGE_SPEED_LED_FOR_50G
,
6081 HCLGE_SPEED_LED_FOR_100G
,
6084 static u8
hclge_led_get_speed_status(u32 speed
)
6089 case HCLGE_MAC_SPEED_1G
:
6090 speed_led
= HCLGE_SPEED_LED_FOR_1G
;
6092 case HCLGE_MAC_SPEED_10G
:
6093 speed_led
= HCLGE_SPEED_LED_FOR_10G
;
6095 case HCLGE_MAC_SPEED_25G
:
6096 speed_led
= HCLGE_SPEED_LED_FOR_25G
;
6098 case HCLGE_MAC_SPEED_40G
:
6099 speed_led
= HCLGE_SPEED_LED_FOR_40G
;
6101 case HCLGE_MAC_SPEED_50G
:
6102 speed_led
= HCLGE_SPEED_LED_FOR_50G
;
6104 case HCLGE_MAC_SPEED_100G
:
6105 speed_led
= HCLGE_SPEED_LED_FOR_100G
;
6108 speed_led
= HCLGE_LED_NO_CHANGE
;
6114 static int hclge_update_led_status(struct hclge_dev
*hdev
)
6116 u8 port_speed_status
, link_status
, activity_status
;
6117 u64 rx_pkts
, tx_pkts
;
6119 if (hdev
->hw
.mac
.media_type
!= HNAE3_MEDIA_TYPE_FIBER
)
6122 port_speed_status
= hclge_led_get_speed_status(hdev
->hw
.mac
.speed
);
6124 rx_pkts
= hdev
->hw_stats
.mac_stats
.mac_rx_total_pkt_num
;
6125 tx_pkts
= hdev
->hw_stats
.mac_stats
.mac_tx_total_pkt_num
;
6126 if (rx_pkts
!= hdev
->rx_pkts_for_led
||
6127 tx_pkts
!= hdev
->tx_pkts_for_led
)
6128 activity_status
= HCLGE_LED_ON
;
6130 activity_status
= HCLGE_LED_OFF
;
6131 hdev
->rx_pkts_for_led
= rx_pkts
;
6132 hdev
->tx_pkts_for_led
= tx_pkts
;
6134 if (hdev
->hw
.mac
.link
)
6135 link_status
= HCLGE_LED_ON
;
6137 link_status
= HCLGE_LED_OFF
;
6139 return hclge_set_led_status_sfp(hdev
, port_speed_status
,
6140 activity_status
, link_status
,
6141 HCLGE_LED_NO_CHANGE
);
6144 static void hclge_get_link_mode(struct hnae3_handle
*handle
,
6145 unsigned long *supported
,
6146 unsigned long *advertising
)
6148 unsigned int size
= BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS
);
6149 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6150 struct hclge_dev
*hdev
= vport
->back
;
6151 unsigned int idx
= 0;
6153 for (; idx
< size
; idx
++) {
6154 supported
[idx
] = hdev
->hw
.mac
.supported
[idx
];
6155 advertising
[idx
] = hdev
->hw
.mac
.advertising
[idx
];
6159 static void hclge_get_port_type(struct hnae3_handle
*handle
,
6162 struct hclge_vport
*vport
= hclge_get_vport(handle
);
6163 struct hclge_dev
*hdev
= vport
->back
;
6164 u8 media_type
= hdev
->hw
.mac
.media_type
;
6166 switch (media_type
) {
6167 case HNAE3_MEDIA_TYPE_FIBER
:
6168 *port_type
= PORT_FIBRE
;
6170 case HNAE3_MEDIA_TYPE_COPPER
:
6171 *port_type
= PORT_TP
;
6173 case HNAE3_MEDIA_TYPE_UNKNOWN
:
6175 *port_type
= PORT_OTHER
;
6180 static const struct hnae3_ae_ops hclge_ops
= {
6181 .init_ae_dev
= hclge_init_ae_dev
,
6182 .uninit_ae_dev
= hclge_uninit_ae_dev
,
6183 .init_client_instance
= hclge_init_client_instance
,
6184 .uninit_client_instance
= hclge_uninit_client_instance
,
6185 .map_ring_to_vector
= hclge_map_ring_to_vector
,
6186 .unmap_ring_from_vector
= hclge_unmap_ring_frm_vector
,
6187 .get_vector
= hclge_get_vector
,
6188 .put_vector
= hclge_put_vector
,
6189 .set_promisc_mode
= hclge_set_promisc_mode
,
6190 .set_loopback
= hclge_set_loopback
,
6191 .start
= hclge_ae_start
,
6192 .stop
= hclge_ae_stop
,
6193 .get_status
= hclge_get_status
,
6194 .get_ksettings_an_result
= hclge_get_ksettings_an_result
,
6195 .update_speed_duplex_h
= hclge_update_speed_duplex_h
,
6196 .cfg_mac_speed_dup_h
= hclge_cfg_mac_speed_dup_h
,
6197 .get_media_type
= hclge_get_media_type
,
6198 .get_rss_key_size
= hclge_get_rss_key_size
,
6199 .get_rss_indir_size
= hclge_get_rss_indir_size
,
6200 .get_rss
= hclge_get_rss
,
6201 .set_rss
= hclge_set_rss
,
6202 .set_rss_tuple
= hclge_set_rss_tuple
,
6203 .get_rss_tuple
= hclge_get_rss_tuple
,
6204 .get_tc_size
= hclge_get_tc_size
,
6205 .get_mac_addr
= hclge_get_mac_addr
,
6206 .set_mac_addr
= hclge_set_mac_addr
,
6207 .add_uc_addr
= hclge_add_uc_addr
,
6208 .rm_uc_addr
= hclge_rm_uc_addr
,
6209 .add_mc_addr
= hclge_add_mc_addr
,
6210 .rm_mc_addr
= hclge_rm_mc_addr
,
6211 .set_autoneg
= hclge_set_autoneg
,
6212 .get_autoneg
= hclge_get_autoneg
,
6213 .get_pauseparam
= hclge_get_pauseparam
,
6214 .set_pauseparam
= hclge_set_pauseparam
,
6215 .set_mtu
= hclge_set_mtu
,
6216 .reset_queue
= hclge_reset_tqp
,
6217 .get_stats
= hclge_get_stats
,
6218 .update_stats
= hclge_update_stats
,
6219 .get_strings
= hclge_get_strings
,
6220 .get_sset_count
= hclge_get_sset_count
,
6221 .get_fw_version
= hclge_get_fw_version
,
6222 .get_mdix_mode
= hclge_get_mdix_mode
,
6223 .enable_vlan_filter
= hclge_enable_vlan_filter
,
6224 .set_vlan_filter
= hclge_set_port_vlan_filter
,
6225 .set_vf_vlan_filter
= hclge_set_vf_vlan_filter
,
6226 .enable_hw_strip_rxvtag
= hclge_en_hw_strip_rxvtag
,
6227 .reset_event
= hclge_reset_event
,
6228 .get_tqps_and_rss_info
= hclge_get_tqps_and_rss_info
,
6229 .set_channels
= hclge_set_channels
,
6230 .get_channels
= hclge_get_channels
,
6231 .get_flowctrl_adv
= hclge_get_flowctrl_adv
,
6232 .get_regs_len
= hclge_get_regs_len
,
6233 .get_regs
= hclge_get_regs
,
6234 .set_led_id
= hclge_set_led_id
,
6235 .get_link_mode
= hclge_get_link_mode
,
6236 .get_port_type
= hclge_get_port_type
,
6239 static struct hnae3_ae_algo ae_algo
= {
6242 .pdev_id_table
= ae_algo_pci_tbl
,
6245 static int hclge_init(void)
6247 pr_info("%s is initializing\n", HCLGE_NAME
);
6249 return hnae3_register_ae_algo(&ae_algo
);
6252 static void hclge_exit(void)
6254 hnae3_unregister_ae_algo(&ae_algo
);
6256 module_init(hclge_init
);
6257 module_exit(hclge_exit
);
6259 MODULE_LICENSE("GPL");
6260 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6261 MODULE_DESCRIPTION("HCLGE Driver");
6262 MODULE_VERSION(HCLGE_MOD_VERSION
);
projects / mirror_ubuntu-bionic-kernel.git / blob