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net: hns3: add support for get_regs
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
1 /*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10 #include <linux/acpi.h>
11 #include <linux/device.h>
12 #include <linux/etherdevice.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
20 #include <linux/if_vlan.h>
21 #include <net/rtnetlink.h>
22 #include "hclge_cmd.h"
23 #include "hclge_dcb.h"
24 #include "hclge_main.h"
25 #include "hclge_mbx.h"
26 #include "hclge_mdio.h"
27 #include "hclge_tm.h"
28 #include "hnae3.h"
29
30 #define HCLGE_NAME "hclge"
31 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
32 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
33 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
34 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
35
36 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
37 enum hclge_mta_dmac_sel_type mta_mac_sel,
38 bool enable);
39 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
40 static int hclge_init_vlan_config(struct hclge_dev *hdev);
41 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
42
43 static struct hnae3_ae_algo ae_algo;
44
45 static const struct pci_device_id ae_algo_pci_tbl[] = {
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
50 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
51 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
52 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
53 /* required last entry */
54 {0, }
55 };
56
57 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
58 "Mac Loopback test",
59 "Serdes Loopback test",
60 "Phy Loopback test"
61 };
62
63 static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
64 {"igu_rx_oversize_pkt",
65 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
66 {"igu_rx_undersize_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
68 {"igu_rx_out_all_pkt",
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
70 {"igu_rx_uni_pkt",
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
72 {"igu_rx_multi_pkt",
73 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
74 {"igu_rx_broad_pkt",
75 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
76 {"egu_tx_out_all_pkt",
77 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
78 {"egu_tx_uni_pkt",
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
80 {"egu_tx_multi_pkt",
81 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
82 {"egu_tx_broad_pkt",
83 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
84 {"ssu_ppp_mac_key_num",
85 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
86 {"ssu_ppp_host_key_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
88 {"ppp_ssu_mac_rlt_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
90 {"ppp_ssu_host_rlt_num",
91 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
92 {"ssu_tx_in_num",
93 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
94 {"ssu_tx_out_num",
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
96 {"ssu_rx_in_num",
97 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
98 {"ssu_rx_out_num",
99 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
100 };
101
102 static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
103 {"igu_rx_err_pkt",
104 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
105 {"igu_rx_no_eof_pkt",
106 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
107 {"igu_rx_no_sof_pkt",
108 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
109 {"egu_tx_1588_pkt",
110 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
111 {"ssu_full_drop_num",
112 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
113 {"ssu_part_drop_num",
114 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
115 {"ppp_key_drop_num",
116 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
117 {"ppp_rlt_drop_num",
118 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
119 {"ssu_key_drop_num",
120 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
121 {"pkt_curr_buf_cnt",
122 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
123 {"qcn_fb_rcv_cnt",
124 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
125 {"qcn_fb_drop_cnt",
126 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
127 {"qcn_fb_invaild_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
129 {"rx_packet_tc0_in_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
131 {"rx_packet_tc1_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
133 {"rx_packet_tc2_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
135 {"rx_packet_tc3_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
137 {"rx_packet_tc4_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
139 {"rx_packet_tc5_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
141 {"rx_packet_tc6_in_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
143 {"rx_packet_tc7_in_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
145 {"rx_packet_tc0_out_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
147 {"rx_packet_tc1_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
149 {"rx_packet_tc2_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
151 {"rx_packet_tc3_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
153 {"rx_packet_tc4_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
155 {"rx_packet_tc5_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
157 {"rx_packet_tc6_out_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
159 {"rx_packet_tc7_out_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
161 {"tx_packet_tc0_in_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
163 {"tx_packet_tc1_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
165 {"tx_packet_tc2_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
167 {"tx_packet_tc3_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
169 {"tx_packet_tc4_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
171 {"tx_packet_tc5_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
173 {"tx_packet_tc6_in_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
175 {"tx_packet_tc7_in_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
177 {"tx_packet_tc0_out_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
179 {"tx_packet_tc1_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
181 {"tx_packet_tc2_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
183 {"tx_packet_tc3_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
185 {"tx_packet_tc4_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
187 {"tx_packet_tc5_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
189 {"tx_packet_tc6_out_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
191 {"tx_packet_tc7_out_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
193 {"pkt_curr_buf_tc0_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
195 {"pkt_curr_buf_tc1_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
197 {"pkt_curr_buf_tc2_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
199 {"pkt_curr_buf_tc3_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
201 {"pkt_curr_buf_tc4_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
203 {"pkt_curr_buf_tc5_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
205 {"pkt_curr_buf_tc6_cnt",
206 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
207 {"pkt_curr_buf_tc7_cnt",
208 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
209 {"mb_uncopy_num",
210 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
211 {"lo_pri_unicast_rlt_drop_num",
212 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
213 {"hi_pri_multicast_rlt_drop_num",
214 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
215 {"lo_pri_multicast_rlt_drop_num",
216 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
217 {"rx_oq_drop_pkt_cnt",
218 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
219 {"tx_oq_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
221 {"nic_l2_err_drop_pkt_cnt",
222 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
223 {"roc_l2_err_drop_pkt_cnt",
224 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
225 };
226
227 static const struct hclge_comm_stats_str g_mac_stats_string[] = {
228 {"mac_tx_mac_pause_num",
229 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
230 {"mac_rx_mac_pause_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
232 {"mac_tx_pfc_pri0_pkt_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
234 {"mac_tx_pfc_pri1_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
236 {"mac_tx_pfc_pri2_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
238 {"mac_tx_pfc_pri3_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
240 {"mac_tx_pfc_pri4_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
242 {"mac_tx_pfc_pri5_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
244 {"mac_tx_pfc_pri6_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
246 {"mac_tx_pfc_pri7_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
248 {"mac_rx_pfc_pri0_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
250 {"mac_rx_pfc_pri1_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
252 {"mac_rx_pfc_pri2_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
254 {"mac_rx_pfc_pri3_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
256 {"mac_rx_pfc_pri4_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
258 {"mac_rx_pfc_pri5_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
260 {"mac_rx_pfc_pri6_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
262 {"mac_rx_pfc_pri7_pkt_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
264 {"mac_tx_total_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
266 {"mac_tx_total_oct_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
268 {"mac_tx_good_pkt_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
270 {"mac_tx_bad_pkt_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
272 {"mac_tx_good_oct_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
274 {"mac_tx_bad_oct_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
276 {"mac_tx_uni_pkt_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
278 {"mac_tx_multi_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
280 {"mac_tx_broad_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
282 {"mac_tx_undersize_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
284 {"mac_tx_oversize_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
286 {"mac_tx_64_oct_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
288 {"mac_tx_65_127_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
290 {"mac_tx_128_255_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
292 {"mac_tx_256_511_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
294 {"mac_tx_512_1023_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
296 {"mac_tx_1024_1518_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
298 {"mac_tx_1519_2047_oct_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
300 {"mac_tx_2048_4095_oct_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
302 {"mac_tx_4096_8191_oct_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
304 {"mac_tx_8192_12287_oct_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_12287_oct_pkt_num)},
306 {"mac_tx_8192_9216_oct_pkt_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
308 {"mac_tx_9217_12287_oct_pkt_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
310 {"mac_tx_12288_16383_oct_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
312 {"mac_tx_1519_max_good_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
314 {"mac_tx_1519_max_bad_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
316 {"mac_rx_total_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
318 {"mac_rx_total_oct_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
320 {"mac_rx_good_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
322 {"mac_rx_bad_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
324 {"mac_rx_good_oct_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
326 {"mac_rx_bad_oct_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
328 {"mac_rx_uni_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
330 {"mac_rx_multi_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
332 {"mac_rx_broad_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
334 {"mac_rx_undersize_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
336 {"mac_rx_oversize_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
338 {"mac_rx_64_oct_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
340 {"mac_rx_65_127_oct_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
342 {"mac_rx_128_255_oct_pkt_num",
343 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
344 {"mac_rx_256_511_oct_pkt_num",
345 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
346 {"mac_rx_512_1023_oct_pkt_num",
347 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
348 {"mac_rx_1024_1518_oct_pkt_num",
349 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
350 {"mac_rx_1519_2047_oct_pkt_num",
351 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
352 {"mac_rx_2048_4095_oct_pkt_num",
353 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
354 {"mac_rx_4096_8191_oct_pkt_num",
355 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
356 {"mac_rx_8192_12287_oct_pkt_num",
357 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_12287_oct_pkt_num)},
358 {"mac_rx_8192_9216_oct_pkt_num",
359 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
360 {"mac_rx_9217_12287_oct_pkt_num",
361 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
362 {"mac_rx_12288_16383_oct_pkt_num",
363 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
364 {"mac_rx_1519_max_good_pkt_num",
365 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
366 {"mac_rx_1519_max_bad_pkt_num",
367 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
368
369 {"mac_tx_fragment_pkt_num",
370 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
371 {"mac_tx_undermin_pkt_num",
372 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
373 {"mac_tx_jabber_pkt_num",
374 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
375 {"mac_tx_err_all_pkt_num",
376 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
377 {"mac_tx_from_app_good_pkt_num",
378 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
379 {"mac_tx_from_app_bad_pkt_num",
380 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
381 {"mac_rx_fragment_pkt_num",
382 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
383 {"mac_rx_undermin_pkt_num",
384 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
385 {"mac_rx_jabber_pkt_num",
386 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
387 {"mac_rx_fcs_err_pkt_num",
388 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
389 {"mac_rx_send_app_good_pkt_num",
390 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
391 {"mac_rx_send_app_bad_pkt_num",
392 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
393 };
394
395 static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
396 {
397 #define HCLGE_64_BIT_CMD_NUM 5
398 #define HCLGE_64_BIT_RTN_DATANUM 4
399 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
400 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
401 __le64 *desc_data;
402 int i, k, n;
403 int ret;
404
405 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
406 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
407 if (ret) {
408 dev_err(&hdev->pdev->dev,
409 "Get 64 bit pkt stats fail, status = %d.\n", ret);
410 return ret;
411 }
412
413 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
414 if (unlikely(i == 0)) {
415 desc_data = (__le64 *)(&desc[i].data[0]);
416 n = HCLGE_64_BIT_RTN_DATANUM - 1;
417 } else {
418 desc_data = (__le64 *)(&desc[i]);
419 n = HCLGE_64_BIT_RTN_DATANUM;
420 }
421 for (k = 0; k < n; k++) {
422 *data++ += le64_to_cpu(*desc_data);
423 desc_data++;
424 }
425 }
426
427 return 0;
428 }
429
430 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
431 {
432 stats->pkt_curr_buf_cnt = 0;
433 stats->pkt_curr_buf_tc0_cnt = 0;
434 stats->pkt_curr_buf_tc1_cnt = 0;
435 stats->pkt_curr_buf_tc2_cnt = 0;
436 stats->pkt_curr_buf_tc3_cnt = 0;
437 stats->pkt_curr_buf_tc4_cnt = 0;
438 stats->pkt_curr_buf_tc5_cnt = 0;
439 stats->pkt_curr_buf_tc6_cnt = 0;
440 stats->pkt_curr_buf_tc7_cnt = 0;
441 }
442
443 static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
444 {
445 #define HCLGE_32_BIT_CMD_NUM 8
446 #define HCLGE_32_BIT_RTN_DATANUM 8
447
448 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
449 struct hclge_32_bit_stats *all_32_bit_stats;
450 __le32 *desc_data;
451 int i, k, n;
452 u64 *data;
453 int ret;
454
455 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
456 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
457
458 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
459 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
460 if (ret) {
461 dev_err(&hdev->pdev->dev,
462 "Get 32 bit pkt stats fail, status = %d.\n", ret);
463
464 return ret;
465 }
466
467 hclge_reset_partial_32bit_counter(all_32_bit_stats);
468 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
469 if (unlikely(i == 0)) {
470 __le16 *desc_data_16bit;
471
472 all_32_bit_stats->igu_rx_err_pkt +=
473 le32_to_cpu(desc[i].data[0]);
474
475 desc_data_16bit = (__le16 *)&desc[i].data[1];
476 all_32_bit_stats->igu_rx_no_eof_pkt +=
477 le16_to_cpu(*desc_data_16bit);
478
479 desc_data_16bit++;
480 all_32_bit_stats->igu_rx_no_sof_pkt +=
481 le16_to_cpu(*desc_data_16bit);
482
483 desc_data = &desc[i].data[2];
484 n = HCLGE_32_BIT_RTN_DATANUM - 4;
485 } else {
486 desc_data = (__le32 *)&desc[i];
487 n = HCLGE_32_BIT_RTN_DATANUM;
488 }
489 for (k = 0; k < n; k++) {
490 *data++ += le32_to_cpu(*desc_data);
491 desc_data++;
492 }
493 }
494
495 return 0;
496 }
497
498 static int hclge_mac_update_stats(struct hclge_dev *hdev)
499 {
500 #define HCLGE_MAC_CMD_NUM 21
501 #define HCLGE_RTN_DATA_NUM 4
502
503 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
504 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
505 __le64 *desc_data;
506 int i, k, n;
507 int ret;
508
509 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
510 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
511 if (ret) {
512 dev_err(&hdev->pdev->dev,
513 "Get MAC pkt stats fail, status = %d.\n", ret);
514
515 return ret;
516 }
517
518 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
519 if (unlikely(i == 0)) {
520 desc_data = (__le64 *)(&desc[i].data[0]);
521 n = HCLGE_RTN_DATA_NUM - 2;
522 } else {
523 desc_data = (__le64 *)(&desc[i]);
524 n = HCLGE_RTN_DATA_NUM;
525 }
526 for (k = 0; k < n; k++) {
527 *data++ += le64_to_cpu(*desc_data);
528 desc_data++;
529 }
530 }
531
532 return 0;
533 }
534
535 static int hclge_tqps_update_stats(struct hnae3_handle *handle)
536 {
537 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
538 struct hclge_vport *vport = hclge_get_vport(handle);
539 struct hclge_dev *hdev = vport->back;
540 struct hnae3_queue *queue;
541 struct hclge_desc desc[1];
542 struct hclge_tqp *tqp;
543 int ret, i;
544
545 for (i = 0; i < kinfo->num_tqps; i++) {
546 queue = handle->kinfo.tqp[i];
547 tqp = container_of(queue, struct hclge_tqp, q);
548 /* command : HCLGE_OPC_QUERY_IGU_STAT */
549 hclge_cmd_setup_basic_desc(&desc[0],
550 HCLGE_OPC_QUERY_RX_STATUS,
551 true);
552
553 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
554 ret = hclge_cmd_send(&hdev->hw, desc, 1);
555 if (ret) {
556 dev_err(&hdev->pdev->dev,
557 "Query tqp stat fail, status = %d,queue = %d\n",
558 ret, i);
559 return ret;
560 }
561 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
562 le32_to_cpu(desc[0].data[1]);
563 }
564
565 for (i = 0; i < kinfo->num_tqps; i++) {
566 queue = handle->kinfo.tqp[i];
567 tqp = container_of(queue, struct hclge_tqp, q);
568 /* command : HCLGE_OPC_QUERY_IGU_STAT */
569 hclge_cmd_setup_basic_desc(&desc[0],
570 HCLGE_OPC_QUERY_TX_STATUS,
571 true);
572
573 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
574 ret = hclge_cmd_send(&hdev->hw, desc, 1);
575 if (ret) {
576 dev_err(&hdev->pdev->dev,
577 "Query tqp stat fail, status = %d,queue = %d\n",
578 ret, i);
579 return ret;
580 }
581 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
582 le32_to_cpu(desc[0].data[1]);
583 }
584
585 return 0;
586 }
587
588 static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
589 {
590 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
591 struct hclge_tqp *tqp;
592 u64 *buff = data;
593 int i;
594
595 for (i = 0; i < kinfo->num_tqps; i++) {
596 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
597 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
598 }
599
600 for (i = 0; i < kinfo->num_tqps; i++) {
601 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
602 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
603 }
604
605 return buff;
606 }
607
608 static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
609 {
610 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
611
612 return kinfo->num_tqps * (2);
613 }
614
615 static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
616 {
617 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
618 u8 *buff = data;
619 int i = 0;
620
621 for (i = 0; i < kinfo->num_tqps; i++) {
622 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
623 struct hclge_tqp, q);
624 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd",
625 tqp->index);
626 buff = buff + ETH_GSTRING_LEN;
627 }
628
629 for (i = 0; i < kinfo->num_tqps; i++) {
630 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
631 struct hclge_tqp, q);
632 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd",
633 tqp->index);
634 buff = buff + ETH_GSTRING_LEN;
635 }
636
637 return buff;
638 }
639
640 static u64 *hclge_comm_get_stats(void *comm_stats,
641 const struct hclge_comm_stats_str strs[],
642 int size, u64 *data)
643 {
644 u64 *buf = data;
645 u32 i;
646
647 for (i = 0; i < size; i++)
648 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
649
650 return buf + size;
651 }
652
653 static u8 *hclge_comm_get_strings(u32 stringset,
654 const struct hclge_comm_stats_str strs[],
655 int size, u8 *data)
656 {
657 char *buff = (char *)data;
658 u32 i;
659
660 if (stringset != ETH_SS_STATS)
661 return buff;
662
663 for (i = 0; i < size; i++) {
664 snprintf(buff, ETH_GSTRING_LEN,
665 strs[i].desc);
666 buff = buff + ETH_GSTRING_LEN;
667 }
668
669 return (u8 *)buff;
670 }
671
672 static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
673 struct net_device_stats *net_stats)
674 {
675 net_stats->tx_dropped = 0;
676 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
677 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
678 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
679
680 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
681 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
682 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
683 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
684 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
685
686 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
687 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
688
689 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
690 net_stats->rx_length_errors =
691 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
692 net_stats->rx_length_errors +=
693 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
694 net_stats->rx_over_errors =
695 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
696 }
697
698 static void hclge_update_stats_for_all(struct hclge_dev *hdev)
699 {
700 struct hnae3_handle *handle;
701 int status;
702
703 handle = &hdev->vport[0].nic;
704 if (handle->client) {
705 status = hclge_tqps_update_stats(handle);
706 if (status) {
707 dev_err(&hdev->pdev->dev,
708 "Update TQPS stats fail, status = %d.\n",
709 status);
710 }
711 }
712
713 status = hclge_mac_update_stats(hdev);
714 if (status)
715 dev_err(&hdev->pdev->dev,
716 "Update MAC stats fail, status = %d.\n", status);
717
718 status = hclge_32_bit_update_stats(hdev);
719 if (status)
720 dev_err(&hdev->pdev->dev,
721 "Update 32 bit stats fail, status = %d.\n",
722 status);
723
724 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
725 }
726
727 static void hclge_update_stats(struct hnae3_handle *handle,
728 struct net_device_stats *net_stats)
729 {
730 struct hclge_vport *vport = hclge_get_vport(handle);
731 struct hclge_dev *hdev = vport->back;
732 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
733 int status;
734
735 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
736 return;
737
738 status = hclge_mac_update_stats(hdev);
739 if (status)
740 dev_err(&hdev->pdev->dev,
741 "Update MAC stats fail, status = %d.\n",
742 status);
743
744 status = hclge_32_bit_update_stats(hdev);
745 if (status)
746 dev_err(&hdev->pdev->dev,
747 "Update 32 bit stats fail, status = %d.\n",
748 status);
749
750 status = hclge_64_bit_update_stats(hdev);
751 if (status)
752 dev_err(&hdev->pdev->dev,
753 "Update 64 bit stats fail, status = %d.\n",
754 status);
755
756 status = hclge_tqps_update_stats(handle);
757 if (status)
758 dev_err(&hdev->pdev->dev,
759 "Update TQPS stats fail, status = %d.\n",
760 status);
761
762 hclge_update_netstat(hw_stats, net_stats);
763
764 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
765 }
766
767 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
768 {
769 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
770
771 struct hclge_vport *vport = hclge_get_vport(handle);
772 struct hclge_dev *hdev = vport->back;
773 int count = 0;
774
775 /* Loopback test support rules:
776 * mac: only GE mode support
777 * serdes: all mac mode will support include GE/XGE/LGE/CGE
778 * phy: only support when phy device exist on board
779 */
780 if (stringset == ETH_SS_TEST) {
781 /* clear loopback bit flags at first */
782 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
783 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
784 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
785 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
786 count += 1;
787 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
788 } else {
789 count = -EOPNOTSUPP;
790 }
791 } else if (stringset == ETH_SS_STATS) {
792 count = ARRAY_SIZE(g_mac_stats_string) +
793 ARRAY_SIZE(g_all_32bit_stats_string) +
794 ARRAY_SIZE(g_all_64bit_stats_string) +
795 hclge_tqps_get_sset_count(handle, stringset);
796 }
797
798 return count;
799 }
800
801 static void hclge_get_strings(struct hnae3_handle *handle,
802 u32 stringset,
803 u8 *data)
804 {
805 u8 *p = (char *)data;
806 int size;
807
808 if (stringset == ETH_SS_STATS) {
809 size = ARRAY_SIZE(g_mac_stats_string);
810 p = hclge_comm_get_strings(stringset,
811 g_mac_stats_string,
812 size,
813 p);
814 size = ARRAY_SIZE(g_all_32bit_stats_string);
815 p = hclge_comm_get_strings(stringset,
816 g_all_32bit_stats_string,
817 size,
818 p);
819 size = ARRAY_SIZE(g_all_64bit_stats_string);
820 p = hclge_comm_get_strings(stringset,
821 g_all_64bit_stats_string,
822 size,
823 p);
824 p = hclge_tqps_get_strings(handle, p);
825 } else if (stringset == ETH_SS_TEST) {
826 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
827 memcpy(p,
828 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
829 ETH_GSTRING_LEN);
830 p += ETH_GSTRING_LEN;
831 }
832 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
833 memcpy(p,
834 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
835 ETH_GSTRING_LEN);
836 p += ETH_GSTRING_LEN;
837 }
838 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
839 memcpy(p,
840 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
841 ETH_GSTRING_LEN);
842 p += ETH_GSTRING_LEN;
843 }
844 }
845 }
846
847 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
848 {
849 struct hclge_vport *vport = hclge_get_vport(handle);
850 struct hclge_dev *hdev = vport->back;
851 u64 *p;
852
853 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
854 g_mac_stats_string,
855 ARRAY_SIZE(g_mac_stats_string),
856 data);
857 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
858 g_all_32bit_stats_string,
859 ARRAY_SIZE(g_all_32bit_stats_string),
860 p);
861 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
862 g_all_64bit_stats_string,
863 ARRAY_SIZE(g_all_64bit_stats_string),
864 p);
865 p = hclge_tqps_get_stats(handle, p);
866 }
867
868 static int hclge_parse_func_status(struct hclge_dev *hdev,
869 struct hclge_func_status_cmd *status)
870 {
871 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
872 return -EINVAL;
873
874 /* Set the pf to main pf */
875 if (status->pf_state & HCLGE_PF_STATE_MAIN)
876 hdev->flag |= HCLGE_FLAG_MAIN;
877 else
878 hdev->flag &= ~HCLGE_FLAG_MAIN;
879
880 return 0;
881 }
882
883 static int hclge_query_function_status(struct hclge_dev *hdev)
884 {
885 struct hclge_func_status_cmd *req;
886 struct hclge_desc desc;
887 int timeout = 0;
888 int ret;
889
890 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
891 req = (struct hclge_func_status_cmd *)desc.data;
892
893 do {
894 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
895 if (ret) {
896 dev_err(&hdev->pdev->dev,
897 "query function status failed %d.\n",
898 ret);
899
900 return ret;
901 }
902
903 /* Check pf reset is done */
904 if (req->pf_state)
905 break;
906 usleep_range(1000, 2000);
907 } while (timeout++ < 5);
908
909 ret = hclge_parse_func_status(hdev, req);
910
911 return ret;
912 }
913
914 static int hclge_query_pf_resource(struct hclge_dev *hdev)
915 {
916 struct hclge_pf_res_cmd *req;
917 struct hclge_desc desc;
918 int ret;
919
920 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
921 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
922 if (ret) {
923 dev_err(&hdev->pdev->dev,
924 "query pf resource failed %d.\n", ret);
925 return ret;
926 }
927
928 req = (struct hclge_pf_res_cmd *)desc.data;
929 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
930 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
931
932 if (hnae3_dev_roce_supported(hdev)) {
933 hdev->num_roce_msi =
934 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
935 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
936
937 /* PF should have NIC vectors and Roce vectors,
938 * NIC vectors are queued before Roce vectors.
939 */
940 hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET;
941 } else {
942 hdev->num_msi =
943 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
944 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
945 }
946
947 return 0;
948 }
949
950 static int hclge_parse_speed(int speed_cmd, int *speed)
951 {
952 switch (speed_cmd) {
953 case 6:
954 *speed = HCLGE_MAC_SPEED_10M;
955 break;
956 case 7:
957 *speed = HCLGE_MAC_SPEED_100M;
958 break;
959 case 0:
960 *speed = HCLGE_MAC_SPEED_1G;
961 break;
962 case 1:
963 *speed = HCLGE_MAC_SPEED_10G;
964 break;
965 case 2:
966 *speed = HCLGE_MAC_SPEED_25G;
967 break;
968 case 3:
969 *speed = HCLGE_MAC_SPEED_40G;
970 break;
971 case 4:
972 *speed = HCLGE_MAC_SPEED_50G;
973 break;
974 case 5:
975 *speed = HCLGE_MAC_SPEED_100G;
976 break;
977 default:
978 return -EINVAL;
979 }
980
981 return 0;
982 }
983
984 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
985 {
986 struct hclge_cfg_param_cmd *req;
987 u64 mac_addr_tmp_high;
988 u64 mac_addr_tmp;
989 int i;
990
991 req = (struct hclge_cfg_param_cmd *)desc[0].data;
992
993 /* get the configuration */
994 cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]),
995 HCLGE_CFG_VMDQ_M,
996 HCLGE_CFG_VMDQ_S);
997 cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
998 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
999 cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
1000 HCLGE_CFG_TQP_DESC_N_M,
1001 HCLGE_CFG_TQP_DESC_N_S);
1002
1003 cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]),
1004 HCLGE_CFG_PHY_ADDR_M,
1005 HCLGE_CFG_PHY_ADDR_S);
1006 cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]),
1007 HCLGE_CFG_MEDIA_TP_M,
1008 HCLGE_CFG_MEDIA_TP_S);
1009 cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]),
1010 HCLGE_CFG_RX_BUF_LEN_M,
1011 HCLGE_CFG_RX_BUF_LEN_S);
1012 /* get mac_address */
1013 mac_addr_tmp = __le32_to_cpu(req->param[2]);
1014 mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]),
1015 HCLGE_CFG_MAC_ADDR_H_M,
1016 HCLGE_CFG_MAC_ADDR_H_S);
1017
1018 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1019
1020 cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]),
1021 HCLGE_CFG_DEFAULT_SPEED_M,
1022 HCLGE_CFG_DEFAULT_SPEED_S);
1023 cfg->rss_size_max = hnae_get_field(__le32_to_cpu(req->param[3]),
1024 HCLGE_CFG_RSS_SIZE_M,
1025 HCLGE_CFG_RSS_SIZE_S);
1026
1027 for (i = 0; i < ETH_ALEN; i++)
1028 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1029
1030 req = (struct hclge_cfg_param_cmd *)desc[1].data;
1031 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
1032 }
1033
1034 /* hclge_get_cfg: query the static parameter from flash
1035 * @hdev: pointer to struct hclge_dev
1036 * @hcfg: the config structure to be getted
1037 */
1038 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1039 {
1040 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
1041 struct hclge_cfg_param_cmd *req;
1042 int i, ret;
1043
1044 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
1045 u32 offset = 0;
1046
1047 req = (struct hclge_cfg_param_cmd *)desc[i].data;
1048 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1049 true);
1050 hnae_set_field(offset, HCLGE_CFG_OFFSET_M,
1051 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1052 /* Len should be united by 4 bytes when send to hardware */
1053 hnae_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
1054 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
1055 req->offset = cpu_to_le32(offset);
1056 }
1057
1058 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1059 if (ret) {
1060 dev_err(&hdev->pdev->dev,
1061 "get config failed %d.\n", ret);
1062 return ret;
1063 }
1064
1065 hclge_parse_cfg(hcfg, desc);
1066 return 0;
1067 }
1068
1069 static int hclge_get_cap(struct hclge_dev *hdev)
1070 {
1071 int ret;
1072
1073 ret = hclge_query_function_status(hdev);
1074 if (ret) {
1075 dev_err(&hdev->pdev->dev,
1076 "query function status error %d.\n", ret);
1077 return ret;
1078 }
1079
1080 /* get pf resource */
1081 ret = hclge_query_pf_resource(hdev);
1082 if (ret) {
1083 dev_err(&hdev->pdev->dev,
1084 "query pf resource error %d.\n", ret);
1085 return ret;
1086 }
1087
1088 return 0;
1089 }
1090
1091 static int hclge_configure(struct hclge_dev *hdev)
1092 {
1093 struct hclge_cfg cfg;
1094 int ret, i;
1095
1096 ret = hclge_get_cfg(hdev, &cfg);
1097 if (ret) {
1098 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1099 return ret;
1100 }
1101
1102 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1103 hdev->base_tqp_pid = 0;
1104 hdev->rss_size_max = cfg.rss_size_max;
1105 hdev->rx_buf_len = cfg.rx_buf_len;
1106 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
1107 hdev->hw.mac.media_type = cfg.media_type;
1108 hdev->hw.mac.phy_addr = cfg.phy_addr;
1109 hdev->num_desc = cfg.tqp_desc_num;
1110 hdev->tm_info.num_pg = 1;
1111 hdev->tc_max = cfg.tc_num;
1112 hdev->tm_info.hw_pfc_map = 0;
1113
1114 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1115 if (ret) {
1116 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1117 return ret;
1118 }
1119
1120 if ((hdev->tc_max > HNAE3_MAX_TC) ||
1121 (hdev->tc_max < 1)) {
1122 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
1123 hdev->tc_max);
1124 hdev->tc_max = 1;
1125 }
1126
1127 /* Dev does not support DCB */
1128 if (!hnae3_dev_dcb_supported(hdev)) {
1129 hdev->tc_max = 1;
1130 hdev->pfc_max = 0;
1131 } else {
1132 hdev->pfc_max = hdev->tc_max;
1133 }
1134
1135 hdev->tm_info.num_tc = hdev->tc_max;
1136
1137 /* Currently not support uncontiuous tc */
1138 for (i = 0; i < hdev->tm_info.num_tc; i++)
1139 hnae_set_bit(hdev->hw_tc_map, i, 1);
1140
1141 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1142
1143 return ret;
1144 }
1145
1146 static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1147 int tso_mss_max)
1148 {
1149 struct hclge_cfg_tso_status_cmd *req;
1150 struct hclge_desc desc;
1151 u16 tso_mss;
1152
1153 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1154
1155 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
1156
1157 tso_mss = 0;
1158 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1159 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
1160 req->tso_mss_min = cpu_to_le16(tso_mss);
1161
1162 tso_mss = 0;
1163 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1164 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
1165 req->tso_mss_max = cpu_to_le16(tso_mss);
1166
1167 return hclge_cmd_send(&hdev->hw, &desc, 1);
1168 }
1169
1170 static int hclge_alloc_tqps(struct hclge_dev *hdev)
1171 {
1172 struct hclge_tqp *tqp;
1173 int i;
1174
1175 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1176 sizeof(struct hclge_tqp), GFP_KERNEL);
1177 if (!hdev->htqp)
1178 return -ENOMEM;
1179
1180 tqp = hdev->htqp;
1181
1182 for (i = 0; i < hdev->num_tqps; i++) {
1183 tqp->dev = &hdev->pdev->dev;
1184 tqp->index = i;
1185
1186 tqp->q.ae_algo = &ae_algo;
1187 tqp->q.buf_size = hdev->rx_buf_len;
1188 tqp->q.desc_num = hdev->num_desc;
1189 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1190 i * HCLGE_TQP_REG_SIZE;
1191
1192 tqp++;
1193 }
1194
1195 return 0;
1196 }
1197
1198 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1199 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1200 {
1201 struct hclge_tqp_map_cmd *req;
1202 struct hclge_desc desc;
1203 int ret;
1204
1205 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1206
1207 req = (struct hclge_tqp_map_cmd *)desc.data;
1208 req->tqp_id = cpu_to_le16(tqp_pid);
1209 req->tqp_vf = func_id;
1210 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1211 1 << HCLGE_TQP_MAP_EN_B;
1212 req->tqp_vid = cpu_to_le16(tqp_vid);
1213
1214 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1215 if (ret) {
1216 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n",
1217 ret);
1218 return ret;
1219 }
1220
1221 return 0;
1222 }
1223
1224 static int hclge_assign_tqp(struct hclge_vport *vport,
1225 struct hnae3_queue **tqp, u16 num_tqps)
1226 {
1227 struct hclge_dev *hdev = vport->back;
1228 int i, alloced;
1229
1230 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1231 alloced < num_tqps; i++) {
1232 if (!hdev->htqp[i].alloced) {
1233 hdev->htqp[i].q.handle = &vport->nic;
1234 hdev->htqp[i].q.tqp_index = alloced;
1235 tqp[alloced] = &hdev->htqp[i].q;
1236 hdev->htqp[i].alloced = true;
1237 alloced++;
1238 }
1239 }
1240 vport->alloc_tqps = num_tqps;
1241
1242 return 0;
1243 }
1244
1245 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1246 {
1247 struct hnae3_handle *nic = &vport->nic;
1248 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1249 struct hclge_dev *hdev = vport->back;
1250 int i, ret;
1251
1252 kinfo->num_desc = hdev->num_desc;
1253 kinfo->rx_buf_len = hdev->rx_buf_len;
1254 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1255 kinfo->rss_size
1256 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1257 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1258
1259 for (i = 0; i < HNAE3_MAX_TC; i++) {
1260 if (hdev->hw_tc_map & BIT(i)) {
1261 kinfo->tc_info[i].enable = true;
1262 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1263 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1264 kinfo->tc_info[i].tc = i;
1265 } else {
1266 /* Set to default queue if TC is disable */
1267 kinfo->tc_info[i].enable = false;
1268 kinfo->tc_info[i].tqp_offset = 0;
1269 kinfo->tc_info[i].tqp_count = 1;
1270 kinfo->tc_info[i].tc = 0;
1271 }
1272 }
1273
1274 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1275 sizeof(struct hnae3_queue *), GFP_KERNEL);
1276 if (!kinfo->tqp)
1277 return -ENOMEM;
1278
1279 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
1280 if (ret) {
1281 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1282 return -EINVAL;
1283 }
1284
1285 return 0;
1286 }
1287
1288 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1289 struct hclge_vport *vport)
1290 {
1291 struct hnae3_handle *nic = &vport->nic;
1292 struct hnae3_knic_private_info *kinfo;
1293 u16 i;
1294
1295 kinfo = &nic->kinfo;
1296 for (i = 0; i < kinfo->num_tqps; i++) {
1297 struct hclge_tqp *q =
1298 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1299 bool is_pf;
1300 int ret;
1301
1302 is_pf = !(vport->vport_id);
1303 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1304 i, is_pf);
1305 if (ret)
1306 return ret;
1307 }
1308
1309 return 0;
1310 }
1311
1312 static int hclge_map_tqp(struct hclge_dev *hdev)
1313 {
1314 struct hclge_vport *vport = hdev->vport;
1315 u16 i, num_vport;
1316
1317 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1318 for (i = 0; i < num_vport; i++) {
1319 int ret;
1320
1321 ret = hclge_map_tqp_to_vport(hdev, vport);
1322 if (ret)
1323 return ret;
1324
1325 vport++;
1326 }
1327
1328 return 0;
1329 }
1330
1331 static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1332 {
1333 /* this would be initialized later */
1334 }
1335
1336 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1337 {
1338 struct hnae3_handle *nic = &vport->nic;
1339 struct hclge_dev *hdev = vport->back;
1340 int ret;
1341
1342 nic->pdev = hdev->pdev;
1343 nic->ae_algo = &ae_algo;
1344 nic->numa_node_mask = hdev->numa_node_mask;
1345
1346 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1347 ret = hclge_knic_setup(vport, num_tqps);
1348 if (ret) {
1349 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1350 ret);
1351 return ret;
1352 }
1353 } else {
1354 hclge_unic_setup(vport, num_tqps);
1355 }
1356
1357 return 0;
1358 }
1359
1360 static int hclge_alloc_vport(struct hclge_dev *hdev)
1361 {
1362 struct pci_dev *pdev = hdev->pdev;
1363 struct hclge_vport *vport;
1364 u32 tqp_main_vport;
1365 u32 tqp_per_vport;
1366 int num_vport, i;
1367 int ret;
1368
1369 /* We need to alloc a vport for main NIC of PF */
1370 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1371
1372 if (hdev->num_tqps < num_vport)
1373 num_vport = hdev->num_tqps;
1374
1375 /* Alloc the same number of TQPs for every vport */
1376 tqp_per_vport = hdev->num_tqps / num_vport;
1377 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1378
1379 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1380 GFP_KERNEL);
1381 if (!vport)
1382 return -ENOMEM;
1383
1384 hdev->vport = vport;
1385 hdev->num_alloc_vport = num_vport;
1386
1387 #ifdef CONFIG_PCI_IOV
1388 /* Enable SRIOV */
1389 if (hdev->num_req_vfs) {
1390 dev_info(&pdev->dev, "active VFs(%d) found, enabling SRIOV\n",
1391 hdev->num_req_vfs);
1392 ret = pci_enable_sriov(hdev->pdev, hdev->num_req_vfs);
1393 if (ret) {
1394 hdev->num_alloc_vfs = 0;
1395 dev_err(&pdev->dev, "SRIOV enable failed %d\n",
1396 ret);
1397 return ret;
1398 }
1399 }
1400 hdev->num_alloc_vfs = hdev->num_req_vfs;
1401 #endif
1402
1403 for (i = 0; i < num_vport; i++) {
1404 vport->back = hdev;
1405 vport->vport_id = i;
1406
1407 if (i == 0)
1408 ret = hclge_vport_setup(vport, tqp_main_vport);
1409 else
1410 ret = hclge_vport_setup(vport, tqp_per_vport);
1411 if (ret) {
1412 dev_err(&pdev->dev,
1413 "vport setup failed for vport %d, %d\n",
1414 i, ret);
1415 return ret;
1416 }
1417
1418 vport++;
1419 }
1420
1421 return 0;
1422 }
1423
1424 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1425 struct hclge_pkt_buf_alloc *buf_alloc)
1426 {
1427 /* TX buffer size is unit by 128 byte */
1428 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1429 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1430 struct hclge_tx_buff_alloc_cmd *req;
1431 struct hclge_desc desc;
1432 int ret;
1433 u8 i;
1434
1435 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
1436
1437 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
1438 for (i = 0; i < HCLGE_TC_NUM; i++) {
1439 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1440
1441 req->tx_pkt_buff[i] =
1442 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1443 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
1444 }
1445
1446 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1447 if (ret) {
1448 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1449 ret);
1450 return ret;
1451 }
1452
1453 return 0;
1454 }
1455
1456 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1457 struct hclge_pkt_buf_alloc *buf_alloc)
1458 {
1459 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
1460
1461 if (ret) {
1462 dev_err(&hdev->pdev->dev,
1463 "tx buffer alloc failed %d\n", ret);
1464 return ret;
1465 }
1466
1467 return 0;
1468 }
1469
1470 static int hclge_get_tc_num(struct hclge_dev *hdev)
1471 {
1472 int i, cnt = 0;
1473
1474 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1475 if (hdev->hw_tc_map & BIT(i))
1476 cnt++;
1477 return cnt;
1478 }
1479
1480 static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1481 {
1482 int i, cnt = 0;
1483
1484 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1485 if (hdev->hw_tc_map & BIT(i) &&
1486 hdev->tm_info.hw_pfc_map & BIT(i))
1487 cnt++;
1488 return cnt;
1489 }
1490
1491 /* Get the number of pfc enabled TCs, which have private buffer */
1492 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1493 struct hclge_pkt_buf_alloc *buf_alloc)
1494 {
1495 struct hclge_priv_buf *priv;
1496 int i, cnt = 0;
1497
1498 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1499 priv = &buf_alloc->priv_buf[i];
1500 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1501 priv->enable)
1502 cnt++;
1503 }
1504
1505 return cnt;
1506 }
1507
1508 /* Get the number of pfc disabled TCs, which have private buffer */
1509 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1510 struct hclge_pkt_buf_alloc *buf_alloc)
1511 {
1512 struct hclge_priv_buf *priv;
1513 int i, cnt = 0;
1514
1515 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1516 priv = &buf_alloc->priv_buf[i];
1517 if (hdev->hw_tc_map & BIT(i) &&
1518 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1519 priv->enable)
1520 cnt++;
1521 }
1522
1523 return cnt;
1524 }
1525
1526 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1527 {
1528 struct hclge_priv_buf *priv;
1529 u32 rx_priv = 0;
1530 int i;
1531
1532 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1533 priv = &buf_alloc->priv_buf[i];
1534 if (priv->enable)
1535 rx_priv += priv->buf_size;
1536 }
1537 return rx_priv;
1538 }
1539
1540 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1541 {
1542 u32 i, total_tx_size = 0;
1543
1544 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1545 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
1546
1547 return total_tx_size;
1548 }
1549
1550 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1551 struct hclge_pkt_buf_alloc *buf_alloc,
1552 u32 rx_all)
1553 {
1554 u32 shared_buf_min, shared_buf_tc, shared_std;
1555 int tc_num, pfc_enable_num;
1556 u32 shared_buf;
1557 u32 rx_priv;
1558 int i;
1559
1560 tc_num = hclge_get_tc_num(hdev);
1561 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1562
1563 if (hnae3_dev_dcb_supported(hdev))
1564 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1565 else
1566 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1567
1568 shared_buf_tc = pfc_enable_num * hdev->mps +
1569 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1570 hdev->mps;
1571 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1572
1573 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
1574 if (rx_all <= rx_priv + shared_std)
1575 return false;
1576
1577 shared_buf = rx_all - rx_priv;
1578 buf_alloc->s_buf.buf_size = shared_buf;
1579 buf_alloc->s_buf.self.high = shared_buf;
1580 buf_alloc->s_buf.self.low = 2 * hdev->mps;
1581
1582 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1583 if ((hdev->hw_tc_map & BIT(i)) &&
1584 (hdev->tm_info.hw_pfc_map & BIT(i))) {
1585 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1586 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
1587 } else {
1588 buf_alloc->s_buf.tc_thrd[i].low = 0;
1589 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
1590 }
1591 }
1592
1593 return true;
1594 }
1595
1596 static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1597 struct hclge_pkt_buf_alloc *buf_alloc)
1598 {
1599 u32 i, total_size;
1600
1601 total_size = hdev->pkt_buf_size;
1602
1603 /* alloc tx buffer for all enabled tc */
1604 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1605 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1606
1607 if (total_size < HCLGE_DEFAULT_TX_BUF)
1608 return -ENOMEM;
1609
1610 if (hdev->hw_tc_map & BIT(i))
1611 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1612 else
1613 priv->tx_buf_size = 0;
1614
1615 total_size -= priv->tx_buf_size;
1616 }
1617
1618 return 0;
1619 }
1620
1621 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1622 * @hdev: pointer to struct hclge_dev
1623 * @buf_alloc: pointer to buffer calculation data
1624 * @return: 0: calculate sucessful, negative: fail
1625 */
1626 static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1627 struct hclge_pkt_buf_alloc *buf_alloc)
1628 {
1629 u32 rx_all = hdev->pkt_buf_size;
1630 int no_pfc_priv_num, pfc_priv_num;
1631 struct hclge_priv_buf *priv;
1632 int i;
1633
1634 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
1635
1636 /* When DCB is not supported, rx private
1637 * buffer is not allocated.
1638 */
1639 if (!hnae3_dev_dcb_supported(hdev)) {
1640 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1641 return -ENOMEM;
1642
1643 return 0;
1644 }
1645
1646 /* step 1, try to alloc private buffer for all enabled tc */
1647 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1648 priv = &buf_alloc->priv_buf[i];
1649 if (hdev->hw_tc_map & BIT(i)) {
1650 priv->enable = 1;
1651 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1652 priv->wl.low = hdev->mps;
1653 priv->wl.high = priv->wl.low + hdev->mps;
1654 priv->buf_size = priv->wl.high +
1655 HCLGE_DEFAULT_DV;
1656 } else {
1657 priv->wl.low = 0;
1658 priv->wl.high = 2 * hdev->mps;
1659 priv->buf_size = priv->wl.high;
1660 }
1661 } else {
1662 priv->enable = 0;
1663 priv->wl.low = 0;
1664 priv->wl.high = 0;
1665 priv->buf_size = 0;
1666 }
1667 }
1668
1669 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1670 return 0;
1671
1672 /* step 2, try to decrease the buffer size of
1673 * no pfc TC's private buffer
1674 */
1675 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1676 priv = &buf_alloc->priv_buf[i];
1677
1678 priv->enable = 0;
1679 priv->wl.low = 0;
1680 priv->wl.high = 0;
1681 priv->buf_size = 0;
1682
1683 if (!(hdev->hw_tc_map & BIT(i)))
1684 continue;
1685
1686 priv->enable = 1;
1687
1688 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1689 priv->wl.low = 128;
1690 priv->wl.high = priv->wl.low + hdev->mps;
1691 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1692 } else {
1693 priv->wl.low = 0;
1694 priv->wl.high = hdev->mps;
1695 priv->buf_size = priv->wl.high;
1696 }
1697 }
1698
1699 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1700 return 0;
1701
1702 /* step 3, try to reduce the number of pfc disabled TCs,
1703 * which have private buffer
1704 */
1705 /* get the total no pfc enable TC number, which have private buffer */
1706 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
1707
1708 /* let the last to be cleared first */
1709 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1710 priv = &buf_alloc->priv_buf[i];
1711
1712 if (hdev->hw_tc_map & BIT(i) &&
1713 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1714 /* Clear the no pfc TC private buffer */
1715 priv->wl.low = 0;
1716 priv->wl.high = 0;
1717 priv->buf_size = 0;
1718 priv->enable = 0;
1719 no_pfc_priv_num--;
1720 }
1721
1722 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1723 no_pfc_priv_num == 0)
1724 break;
1725 }
1726
1727 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1728 return 0;
1729
1730 /* step 4, try to reduce the number of pfc enabled TCs
1731 * which have private buffer.
1732 */
1733 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
1734
1735 /* let the last to be cleared first */
1736 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1737 priv = &buf_alloc->priv_buf[i];
1738
1739 if (hdev->hw_tc_map & BIT(i) &&
1740 hdev->tm_info.hw_pfc_map & BIT(i)) {
1741 /* Reduce the number of pfc TC with private buffer */
1742 priv->wl.low = 0;
1743 priv->enable = 0;
1744 priv->wl.high = 0;
1745 priv->buf_size = 0;
1746 pfc_priv_num--;
1747 }
1748
1749 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1750 pfc_priv_num == 0)
1751 break;
1752 }
1753 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1754 return 0;
1755
1756 return -ENOMEM;
1757 }
1758
1759 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1760 struct hclge_pkt_buf_alloc *buf_alloc)
1761 {
1762 struct hclge_rx_priv_buff_cmd *req;
1763 struct hclge_desc desc;
1764 int ret;
1765 int i;
1766
1767 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
1768 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
1769
1770 /* Alloc private buffer TCs */
1771 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1772 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1773
1774 req->buf_num[i] =
1775 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1776 req->buf_num[i] |=
1777 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
1778 }
1779
1780 req->shared_buf =
1781 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
1782 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1783
1784 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1785 if (ret) {
1786 dev_err(&hdev->pdev->dev,
1787 "rx private buffer alloc cmd failed %d\n", ret);
1788 return ret;
1789 }
1790
1791 return 0;
1792 }
1793
1794 #define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1795
1796 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1797 struct hclge_pkt_buf_alloc *buf_alloc)
1798 {
1799 struct hclge_rx_priv_wl_buf *req;
1800 struct hclge_priv_buf *priv;
1801 struct hclge_desc desc[2];
1802 int i, j;
1803 int ret;
1804
1805 for (i = 0; i < 2; i++) {
1806 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1807 false);
1808 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1809
1810 /* The first descriptor set the NEXT bit to 1 */
1811 if (i == 0)
1812 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1813 else
1814 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1815
1816 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1817 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1818
1819 priv = &buf_alloc->priv_buf[idx];
1820 req->tc_wl[j].high =
1821 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1822 req->tc_wl[j].high |=
1823 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
1824 HCLGE_RX_PRIV_EN_B);
1825 req->tc_wl[j].low =
1826 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1827 req->tc_wl[j].low |=
1828 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
1829 HCLGE_RX_PRIV_EN_B);
1830 }
1831 }
1832
1833 /* Send 2 descriptor at one time */
1834 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1835 if (ret) {
1836 dev_err(&hdev->pdev->dev,
1837 "rx private waterline config cmd failed %d\n",
1838 ret);
1839 return ret;
1840 }
1841 return 0;
1842 }
1843
1844 static int hclge_common_thrd_config(struct hclge_dev *hdev,
1845 struct hclge_pkt_buf_alloc *buf_alloc)
1846 {
1847 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
1848 struct hclge_rx_com_thrd *req;
1849 struct hclge_desc desc[2];
1850 struct hclge_tc_thrd *tc;
1851 int i, j;
1852 int ret;
1853
1854 for (i = 0; i < 2; i++) {
1855 hclge_cmd_setup_basic_desc(&desc[i],
1856 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1857 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1858
1859 /* The first descriptor set the NEXT bit to 1 */
1860 if (i == 0)
1861 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1862 else
1863 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1864
1865 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1866 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1867
1868 req->com_thrd[j].high =
1869 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1870 req->com_thrd[j].high |=
1871 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
1872 HCLGE_RX_PRIV_EN_B);
1873 req->com_thrd[j].low =
1874 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1875 req->com_thrd[j].low |=
1876 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
1877 HCLGE_RX_PRIV_EN_B);
1878 }
1879 }
1880
1881 /* Send 2 descriptors at one time */
1882 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1883 if (ret) {
1884 dev_err(&hdev->pdev->dev,
1885 "common threshold config cmd failed %d\n", ret);
1886 return ret;
1887 }
1888 return 0;
1889 }
1890
1891 static int hclge_common_wl_config(struct hclge_dev *hdev,
1892 struct hclge_pkt_buf_alloc *buf_alloc)
1893 {
1894 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
1895 struct hclge_rx_com_wl *req;
1896 struct hclge_desc desc;
1897 int ret;
1898
1899 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1900
1901 req = (struct hclge_rx_com_wl *)desc.data;
1902 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1903 req->com_wl.high |=
1904 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
1905 HCLGE_RX_PRIV_EN_B);
1906
1907 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1908 req->com_wl.low |=
1909 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
1910 HCLGE_RX_PRIV_EN_B);
1911
1912 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1913 if (ret) {
1914 dev_err(&hdev->pdev->dev,
1915 "common waterline config cmd failed %d\n", ret);
1916 return ret;
1917 }
1918
1919 return 0;
1920 }
1921
1922 int hclge_buffer_alloc(struct hclge_dev *hdev)
1923 {
1924 struct hclge_pkt_buf_alloc *pkt_buf;
1925 int ret;
1926
1927 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1928 if (!pkt_buf)
1929 return -ENOMEM;
1930
1931 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
1932 if (ret) {
1933 dev_err(&hdev->pdev->dev,
1934 "could not calc tx buffer size for all TCs %d\n", ret);
1935 goto out;
1936 }
1937
1938 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
1939 if (ret) {
1940 dev_err(&hdev->pdev->dev,
1941 "could not alloc tx buffers %d\n", ret);
1942 goto out;
1943 }
1944
1945 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
1946 if (ret) {
1947 dev_err(&hdev->pdev->dev,
1948 "could not calc rx priv buffer size for all TCs %d\n",
1949 ret);
1950 goto out;
1951 }
1952
1953 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
1954 if (ret) {
1955 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1956 ret);
1957 goto out;
1958 }
1959
1960 if (hnae3_dev_dcb_supported(hdev)) {
1961 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
1962 if (ret) {
1963 dev_err(&hdev->pdev->dev,
1964 "could not configure rx private waterline %d\n",
1965 ret);
1966 goto out;
1967 }
1968
1969 ret = hclge_common_thrd_config(hdev, pkt_buf);
1970 if (ret) {
1971 dev_err(&hdev->pdev->dev,
1972 "could not configure common threshold %d\n",
1973 ret);
1974 goto out;
1975 }
1976 }
1977
1978 ret = hclge_common_wl_config(hdev, pkt_buf);
1979 if (ret)
1980 dev_err(&hdev->pdev->dev,
1981 "could not configure common waterline %d\n", ret);
1982
1983 out:
1984 kfree(pkt_buf);
1985 return ret;
1986 }
1987
1988 static int hclge_init_roce_base_info(struct hclge_vport *vport)
1989 {
1990 struct hnae3_handle *roce = &vport->roce;
1991 struct hnae3_handle *nic = &vport->nic;
1992
1993 roce->rinfo.num_vectors = vport->back->num_roce_msi;
1994
1995 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1996 vport->back->num_msi_left == 0)
1997 return -EINVAL;
1998
1999 roce->rinfo.base_vector = vport->back->roce_base_vector;
2000
2001 roce->rinfo.netdev = nic->kinfo.netdev;
2002 roce->rinfo.roce_io_base = vport->back->hw.io_base;
2003
2004 roce->pdev = nic->pdev;
2005 roce->ae_algo = nic->ae_algo;
2006 roce->numa_node_mask = nic->numa_node_mask;
2007
2008 return 0;
2009 }
2010
2011 static int hclge_init_msi(struct hclge_dev *hdev)
2012 {
2013 struct pci_dev *pdev = hdev->pdev;
2014 int vectors;
2015 int i;
2016
2017 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
2018 PCI_IRQ_MSI | PCI_IRQ_MSIX);
2019 if (vectors < 0) {
2020 dev_err(&pdev->dev,
2021 "failed(%d) to allocate MSI/MSI-X vectors\n",
2022 vectors);
2023 return vectors;
2024 }
2025 if (vectors < hdev->num_msi)
2026 dev_warn(&hdev->pdev->dev,
2027 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2028 hdev->num_msi, vectors);
2029
2030 hdev->num_msi = vectors;
2031 hdev->num_msi_left = vectors;
2032 hdev->base_msi_vector = pdev->irq;
2033 hdev->roce_base_vector = hdev->base_msi_vector +
2034 HCLGE_ROCE_VECTOR_OFFSET;
2035
2036 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2037 sizeof(u16), GFP_KERNEL);
2038 if (!hdev->vector_status) {
2039 pci_free_irq_vectors(pdev);
2040 return -ENOMEM;
2041 }
2042
2043 for (i = 0; i < hdev->num_msi; i++)
2044 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2045
2046 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2047 sizeof(int), GFP_KERNEL);
2048 if (!hdev->vector_irq) {
2049 pci_free_irq_vectors(pdev);
2050 return -ENOMEM;
2051 }
2052
2053 return 0;
2054 }
2055
2056 static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
2057 {
2058 struct hclge_mac *mac = &hdev->hw.mac;
2059
2060 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
2061 mac->duplex = (u8)duplex;
2062 else
2063 mac->duplex = HCLGE_MAC_FULL;
2064
2065 mac->speed = speed;
2066 }
2067
2068 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2069 {
2070 struct hclge_config_mac_speed_dup_cmd *req;
2071 struct hclge_desc desc;
2072 int ret;
2073
2074 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
2075
2076 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2077
2078 hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
2079
2080 switch (speed) {
2081 case HCLGE_MAC_SPEED_10M:
2082 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2083 HCLGE_CFG_SPEED_S, 6);
2084 break;
2085 case HCLGE_MAC_SPEED_100M:
2086 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2087 HCLGE_CFG_SPEED_S, 7);
2088 break;
2089 case HCLGE_MAC_SPEED_1G:
2090 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2091 HCLGE_CFG_SPEED_S, 0);
2092 break;
2093 case HCLGE_MAC_SPEED_10G:
2094 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2095 HCLGE_CFG_SPEED_S, 1);
2096 break;
2097 case HCLGE_MAC_SPEED_25G:
2098 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2099 HCLGE_CFG_SPEED_S, 2);
2100 break;
2101 case HCLGE_MAC_SPEED_40G:
2102 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2103 HCLGE_CFG_SPEED_S, 3);
2104 break;
2105 case HCLGE_MAC_SPEED_50G:
2106 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2107 HCLGE_CFG_SPEED_S, 4);
2108 break;
2109 case HCLGE_MAC_SPEED_100G:
2110 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2111 HCLGE_CFG_SPEED_S, 5);
2112 break;
2113 default:
2114 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
2115 return -EINVAL;
2116 }
2117
2118 hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2119 1);
2120
2121 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2122 if (ret) {
2123 dev_err(&hdev->pdev->dev,
2124 "mac speed/duplex config cmd failed %d.\n", ret);
2125 return ret;
2126 }
2127
2128 hclge_check_speed_dup(hdev, duplex, speed);
2129
2130 return 0;
2131 }
2132
2133 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2134 u8 duplex)
2135 {
2136 struct hclge_vport *vport = hclge_get_vport(handle);
2137 struct hclge_dev *hdev = vport->back;
2138
2139 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2140 }
2141
2142 static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2143 u8 *duplex)
2144 {
2145 struct hclge_query_an_speed_dup_cmd *req;
2146 struct hclge_desc desc;
2147 int speed_tmp;
2148 int ret;
2149
2150 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
2151
2152 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2153 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2154 if (ret) {
2155 dev_err(&hdev->pdev->dev,
2156 "mac speed/autoneg/duplex query cmd failed %d\n",
2157 ret);
2158 return ret;
2159 }
2160
2161 *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2162 speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2163 HCLGE_QUERY_SPEED_S);
2164
2165 ret = hclge_parse_speed(speed_tmp, speed);
2166 if (ret) {
2167 dev_err(&hdev->pdev->dev,
2168 "could not parse speed(=%d), %d\n", speed_tmp, ret);
2169 return -EIO;
2170 }
2171
2172 return 0;
2173 }
2174
2175 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2176 {
2177 struct hclge_config_auto_neg_cmd *req;
2178 struct hclge_desc desc;
2179 u32 flag = 0;
2180 int ret;
2181
2182 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2183
2184 req = (struct hclge_config_auto_neg_cmd *)desc.data;
2185 hnae_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2186 req->cfg_an_cmd_flag = cpu_to_le32(flag);
2187
2188 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2189 if (ret) {
2190 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2191 ret);
2192 return ret;
2193 }
2194
2195 return 0;
2196 }
2197
2198 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2199 {
2200 struct hclge_vport *vport = hclge_get_vport(handle);
2201 struct hclge_dev *hdev = vport->back;
2202
2203 return hclge_set_autoneg_en(hdev, enable);
2204 }
2205
2206 static int hclge_get_autoneg(struct hnae3_handle *handle)
2207 {
2208 struct hclge_vport *vport = hclge_get_vport(handle);
2209 struct hclge_dev *hdev = vport->back;
2210 struct phy_device *phydev = hdev->hw.mac.phydev;
2211
2212 if (phydev)
2213 return phydev->autoneg;
2214
2215 return hdev->hw.mac.autoneg;
2216 }
2217
2218 static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev,
2219 bool mask_vlan,
2220 u8 *mac_mask)
2221 {
2222 struct hclge_mac_vlan_mask_entry_cmd *req;
2223 struct hclge_desc desc;
2224 int status;
2225
2226 req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data;
2227 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false);
2228
2229 hnae_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B,
2230 mask_vlan ? 1 : 0);
2231 ether_addr_copy(req->mac_mask, mac_mask);
2232
2233 status = hclge_cmd_send(&hdev->hw, &desc, 1);
2234 if (status)
2235 dev_err(&hdev->pdev->dev,
2236 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2237 status);
2238
2239 return status;
2240 }
2241
2242 static int hclge_mac_init(struct hclge_dev *hdev)
2243 {
2244 struct hnae3_handle *handle = &hdev->vport[0].nic;
2245 struct net_device *netdev = handle->kinfo.netdev;
2246 struct hclge_mac *mac = &hdev->hw.mac;
2247 u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
2248 int mtu;
2249 int ret;
2250
2251 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2252 if (ret) {
2253 dev_err(&hdev->pdev->dev,
2254 "Config mac speed dup fail ret=%d\n", ret);
2255 return ret;
2256 }
2257
2258 mac->link = 0;
2259
2260 /* Initialize the MTA table work mode */
2261 hdev->accept_mta_mc = true;
2262 hdev->enable_mta = true;
2263 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2264
2265 ret = hclge_set_mta_filter_mode(hdev,
2266 hdev->mta_mac_sel_type,
2267 hdev->enable_mta);
2268 if (ret) {
2269 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2270 ret);
2271 return ret;
2272 }
2273
2274 ret = hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc);
2275 if (ret) {
2276 dev_err(&hdev->pdev->dev,
2277 "set mta filter mode fail ret=%d\n", ret);
2278 return ret;
2279 }
2280
2281 ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask);
2282 if (ret) {
2283 dev_err(&hdev->pdev->dev,
2284 "set default mac_vlan_mask fail ret=%d\n", ret);
2285 return ret;
2286 }
2287
2288 if (netdev)
2289 mtu = netdev->mtu;
2290 else
2291 mtu = ETH_DATA_LEN;
2292
2293 ret = hclge_set_mtu(handle, mtu);
2294 if (ret) {
2295 dev_err(&hdev->pdev->dev,
2296 "set mtu failed ret=%d\n", ret);
2297 return ret;
2298 }
2299
2300 return 0;
2301 }
2302
2303 static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2304 {
2305 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2306 schedule_work(&hdev->mbx_service_task);
2307 }
2308
2309 static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2310 {
2311 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2312 schedule_work(&hdev->rst_service_task);
2313 }
2314
2315 static void hclge_task_schedule(struct hclge_dev *hdev)
2316 {
2317 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2318 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2319 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2320 (void)schedule_work(&hdev->service_task);
2321 }
2322
2323 static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2324 {
2325 struct hclge_link_status_cmd *req;
2326 struct hclge_desc desc;
2327 int link_status;
2328 int ret;
2329
2330 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2331 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2332 if (ret) {
2333 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2334 ret);
2335 return ret;
2336 }
2337
2338 req = (struct hclge_link_status_cmd *)desc.data;
2339 link_status = req->status & HCLGE_LINK_STATUS;
2340
2341 return !!link_status;
2342 }
2343
2344 static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2345 {
2346 int mac_state;
2347 int link_stat;
2348
2349 mac_state = hclge_get_mac_link_status(hdev);
2350
2351 if (hdev->hw.mac.phydev) {
2352 if (!genphy_read_status(hdev->hw.mac.phydev))
2353 link_stat = mac_state &
2354 hdev->hw.mac.phydev->link;
2355 else
2356 link_stat = 0;
2357
2358 } else {
2359 link_stat = mac_state;
2360 }
2361
2362 return !!link_stat;
2363 }
2364
2365 static void hclge_update_link_status(struct hclge_dev *hdev)
2366 {
2367 struct hnae3_client *client = hdev->nic_client;
2368 struct hnae3_handle *handle;
2369 int state;
2370 int i;
2371
2372 if (!client)
2373 return;
2374 state = hclge_get_mac_phy_link(hdev);
2375 if (state != hdev->hw.mac.link) {
2376 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2377 handle = &hdev->vport[i].nic;
2378 client->ops->link_status_change(handle, state);
2379 }
2380 hdev->hw.mac.link = state;
2381 }
2382 }
2383
2384 static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2385 {
2386 struct hclge_mac mac = hdev->hw.mac;
2387 u8 duplex;
2388 int speed;
2389 int ret;
2390
2391 /* get the speed and duplex as autoneg'result from mac cmd when phy
2392 * doesn't exit.
2393 */
2394 if (mac.phydev || !mac.autoneg)
2395 return 0;
2396
2397 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2398 if (ret) {
2399 dev_err(&hdev->pdev->dev,
2400 "mac autoneg/speed/duplex query failed %d\n", ret);
2401 return ret;
2402 }
2403
2404 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2405 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2406 if (ret) {
2407 dev_err(&hdev->pdev->dev,
2408 "mac speed/duplex config failed %d\n", ret);
2409 return ret;
2410 }
2411 }
2412
2413 return 0;
2414 }
2415
2416 static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2417 {
2418 struct hclge_vport *vport = hclge_get_vport(handle);
2419 struct hclge_dev *hdev = vport->back;
2420
2421 return hclge_update_speed_duplex(hdev);
2422 }
2423
2424 static int hclge_get_status(struct hnae3_handle *handle)
2425 {
2426 struct hclge_vport *vport = hclge_get_vport(handle);
2427 struct hclge_dev *hdev = vport->back;
2428
2429 hclge_update_link_status(hdev);
2430
2431 return hdev->hw.mac.link;
2432 }
2433
2434 static void hclge_service_timer(struct timer_list *t)
2435 {
2436 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
2437
2438 mod_timer(&hdev->service_timer, jiffies + HZ);
2439 hdev->hw_stats.stats_timer++;
2440 hclge_task_schedule(hdev);
2441 }
2442
2443 static void hclge_service_complete(struct hclge_dev *hdev)
2444 {
2445 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2446
2447 /* Flush memory before next watchdog */
2448 smp_mb__before_atomic();
2449 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2450 }
2451
2452 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2453 {
2454 u32 rst_src_reg;
2455 u32 cmdq_src_reg;
2456
2457 /* fetch the events from their corresponding regs */
2458 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);
2459 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2460
2461 /* Assumption: If by any chance reset and mailbox events are reported
2462 * together then we will only process reset event in this go and will
2463 * defer the processing of the mailbox events. Since, we would have not
2464 * cleared RX CMDQ event this time we would receive again another
2465 * interrupt from H/W just for the mailbox.
2466 */
2467
2468 /* check for vector0 reset event sources */
2469 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2470 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2471 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2472 return HCLGE_VECTOR0_EVENT_RST;
2473 }
2474
2475 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2476 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2477 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2478 return HCLGE_VECTOR0_EVENT_RST;
2479 }
2480
2481 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2482 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2483 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2484 return HCLGE_VECTOR0_EVENT_RST;
2485 }
2486
2487 /* check for vector0 mailbox(=CMDQ RX) event source */
2488 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2489 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2490 *clearval = cmdq_src_reg;
2491 return HCLGE_VECTOR0_EVENT_MBX;
2492 }
2493
2494 return HCLGE_VECTOR0_EVENT_OTHER;
2495 }
2496
2497 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2498 u32 regclr)
2499 {
2500 switch (event_type) {
2501 case HCLGE_VECTOR0_EVENT_RST:
2502 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
2503 break;
2504 case HCLGE_VECTOR0_EVENT_MBX:
2505 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2506 break;
2507 }
2508 }
2509
2510 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2511 {
2512 writel(enable ? 1 : 0, vector->addr);
2513 }
2514
2515 static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2516 {
2517 struct hclge_dev *hdev = data;
2518 u32 event_cause;
2519 u32 clearval;
2520
2521 hclge_enable_vector(&hdev->misc_vector, false);
2522 event_cause = hclge_check_event_cause(hdev, &clearval);
2523
2524 /* vector 0 interrupt is shared with reset and mailbox source events.*/
2525 switch (event_cause) {
2526 case HCLGE_VECTOR0_EVENT_RST:
2527 hclge_reset_task_schedule(hdev);
2528 break;
2529 case HCLGE_VECTOR0_EVENT_MBX:
2530 /* If we are here then,
2531 * 1. Either we are not handling any mbx task and we are not
2532 * scheduled as well
2533 * OR
2534 * 2. We could be handling a mbx task but nothing more is
2535 * scheduled.
2536 * In both cases, we should schedule mbx task as there are more
2537 * mbx messages reported by this interrupt.
2538 */
2539 hclge_mbx_task_schedule(hdev);
2540
2541 default:
2542 dev_dbg(&hdev->pdev->dev,
2543 "received unknown or unhandled event of vector0\n");
2544 break;
2545 }
2546
2547 /* we should clear the source of interrupt */
2548 hclge_clear_event_cause(hdev, event_cause, clearval);
2549 hclge_enable_vector(&hdev->misc_vector, true);
2550
2551 return IRQ_HANDLED;
2552 }
2553
2554 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2555 {
2556 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2557 hdev->num_msi_left += 1;
2558 hdev->num_msi_used -= 1;
2559 }
2560
2561 static void hclge_get_misc_vector(struct hclge_dev *hdev)
2562 {
2563 struct hclge_misc_vector *vector = &hdev->misc_vector;
2564
2565 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2566
2567 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2568 hdev->vector_status[0] = 0;
2569
2570 hdev->num_msi_left -= 1;
2571 hdev->num_msi_used += 1;
2572 }
2573
2574 static int hclge_misc_irq_init(struct hclge_dev *hdev)
2575 {
2576 int ret;
2577
2578 hclge_get_misc_vector(hdev);
2579
2580 /* this would be explicitly freed in the end */
2581 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2582 0, "hclge_misc", hdev);
2583 if (ret) {
2584 hclge_free_vector(hdev, 0);
2585 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2586 hdev->misc_vector.vector_irq);
2587 }
2588
2589 return ret;
2590 }
2591
2592 static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2593 {
2594 free_irq(hdev->misc_vector.vector_irq, hdev);
2595 hclge_free_vector(hdev, 0);
2596 }
2597
2598 static int hclge_notify_client(struct hclge_dev *hdev,
2599 enum hnae3_reset_notify_type type)
2600 {
2601 struct hnae3_client *client = hdev->nic_client;
2602 u16 i;
2603
2604 if (!client->ops->reset_notify)
2605 return -EOPNOTSUPP;
2606
2607 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2608 struct hnae3_handle *handle = &hdev->vport[i].nic;
2609 int ret;
2610
2611 ret = client->ops->reset_notify(handle, type);
2612 if (ret)
2613 return ret;
2614 }
2615
2616 return 0;
2617 }
2618
2619 static int hclge_reset_wait(struct hclge_dev *hdev)
2620 {
2621 #define HCLGE_RESET_WATI_MS 100
2622 #define HCLGE_RESET_WAIT_CNT 5
2623 u32 val, reg, reg_bit;
2624 u32 cnt = 0;
2625
2626 switch (hdev->reset_type) {
2627 case HNAE3_GLOBAL_RESET:
2628 reg = HCLGE_GLOBAL_RESET_REG;
2629 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2630 break;
2631 case HNAE3_CORE_RESET:
2632 reg = HCLGE_GLOBAL_RESET_REG;
2633 reg_bit = HCLGE_CORE_RESET_BIT;
2634 break;
2635 case HNAE3_FUNC_RESET:
2636 reg = HCLGE_FUN_RST_ING;
2637 reg_bit = HCLGE_FUN_RST_ING_B;
2638 break;
2639 default:
2640 dev_err(&hdev->pdev->dev,
2641 "Wait for unsupported reset type: %d\n",
2642 hdev->reset_type);
2643 return -EINVAL;
2644 }
2645
2646 val = hclge_read_dev(&hdev->hw, reg);
2647 while (hnae_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
2648 msleep(HCLGE_RESET_WATI_MS);
2649 val = hclge_read_dev(&hdev->hw, reg);
2650 cnt++;
2651 }
2652
2653 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2654 dev_warn(&hdev->pdev->dev,
2655 "Wait for reset timeout: %d\n", hdev->reset_type);
2656 return -EBUSY;
2657 }
2658
2659 return 0;
2660 }
2661
2662 static int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
2663 {
2664 struct hclge_desc desc;
2665 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2666 int ret;
2667
2668 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2669 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_MAC_B, 0);
2670 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2671 req->fun_reset_vfid = func_id;
2672
2673 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2674 if (ret)
2675 dev_err(&hdev->pdev->dev,
2676 "send function reset cmd fail, status =%d\n", ret);
2677
2678 return ret;
2679 }
2680
2681 static void hclge_do_reset(struct hclge_dev *hdev)
2682 {
2683 struct pci_dev *pdev = hdev->pdev;
2684 u32 val;
2685
2686 switch (hdev->reset_type) {
2687 case HNAE3_GLOBAL_RESET:
2688 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2689 hnae_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2690 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2691 dev_info(&pdev->dev, "Global Reset requested\n");
2692 break;
2693 case HNAE3_CORE_RESET:
2694 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2695 hnae_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2696 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2697 dev_info(&pdev->dev, "Core Reset requested\n");
2698 break;
2699 case HNAE3_FUNC_RESET:
2700 dev_info(&pdev->dev, "PF Reset requested\n");
2701 hclge_func_reset_cmd(hdev, 0);
2702 /* schedule again to check later */
2703 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2704 hclge_reset_task_schedule(hdev);
2705 break;
2706 default:
2707 dev_warn(&pdev->dev,
2708 "Unsupported reset type: %d\n", hdev->reset_type);
2709 break;
2710 }
2711 }
2712
2713 static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2714 unsigned long *addr)
2715 {
2716 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2717
2718 /* return the highest priority reset level amongst all */
2719 if (test_bit(HNAE3_GLOBAL_RESET, addr))
2720 rst_level = HNAE3_GLOBAL_RESET;
2721 else if (test_bit(HNAE3_CORE_RESET, addr))
2722 rst_level = HNAE3_CORE_RESET;
2723 else if (test_bit(HNAE3_IMP_RESET, addr))
2724 rst_level = HNAE3_IMP_RESET;
2725 else if (test_bit(HNAE3_FUNC_RESET, addr))
2726 rst_level = HNAE3_FUNC_RESET;
2727
2728 /* now, clear all other resets */
2729 clear_bit(HNAE3_GLOBAL_RESET, addr);
2730 clear_bit(HNAE3_CORE_RESET, addr);
2731 clear_bit(HNAE3_IMP_RESET, addr);
2732 clear_bit(HNAE3_FUNC_RESET, addr);
2733
2734 return rst_level;
2735 }
2736
2737 static void hclge_reset(struct hclge_dev *hdev)
2738 {
2739 /* perform reset of the stack & ae device for a client */
2740
2741 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2742
2743 if (!hclge_reset_wait(hdev)) {
2744 rtnl_lock();
2745 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2746 hclge_reset_ae_dev(hdev->ae_dev);
2747 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2748 rtnl_unlock();
2749 } else {
2750 /* schedule again to check pending resets later */
2751 set_bit(hdev->reset_type, &hdev->reset_pending);
2752 hclge_reset_task_schedule(hdev);
2753 }
2754
2755 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2756 }
2757
2758 static void hclge_reset_event(struct hnae3_handle *handle,
2759 enum hnae3_reset_type reset)
2760 {
2761 struct hclge_vport *vport = hclge_get_vport(handle);
2762 struct hclge_dev *hdev = vport->back;
2763
2764 dev_info(&hdev->pdev->dev,
2765 "Receive reset event , reset_type is %d", reset);
2766
2767 switch (reset) {
2768 case HNAE3_FUNC_RESET:
2769 case HNAE3_CORE_RESET:
2770 case HNAE3_GLOBAL_RESET:
2771 /* request reset & schedule reset task */
2772 set_bit(reset, &hdev->reset_request);
2773 hclge_reset_task_schedule(hdev);
2774 break;
2775 default:
2776 dev_warn(&hdev->pdev->dev, "Unsupported reset event:%d", reset);
2777 break;
2778 }
2779 }
2780
2781 static void hclge_reset_subtask(struct hclge_dev *hdev)
2782 {
2783 /* check if there is any ongoing reset in the hardware. This status can
2784 * be checked from reset_pending. If there is then, we need to wait for
2785 * hardware to complete reset.
2786 * a. If we are able to figure out in reasonable time that hardware
2787 * has fully resetted then, we can proceed with driver, client
2788 * reset.
2789 * b. else, we can come back later to check this status so re-sched
2790 * now.
2791 */
2792 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2793 if (hdev->reset_type != HNAE3_NONE_RESET)
2794 hclge_reset(hdev);
2795
2796 /* check if we got any *new* reset requests to be honored */
2797 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2798 if (hdev->reset_type != HNAE3_NONE_RESET)
2799 hclge_do_reset(hdev);
2800
2801 hdev->reset_type = HNAE3_NONE_RESET;
2802 }
2803
2804 static void hclge_reset_service_task(struct work_struct *work)
2805 {
2806 struct hclge_dev *hdev =
2807 container_of(work, struct hclge_dev, rst_service_task);
2808
2809 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2810 return;
2811
2812 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2813
2814 hclge_reset_subtask(hdev);
2815
2816 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
2817 }
2818
2819 static void hclge_mailbox_service_task(struct work_struct *work)
2820 {
2821 struct hclge_dev *hdev =
2822 container_of(work, struct hclge_dev, mbx_service_task);
2823
2824 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2825 return;
2826
2827 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2828
2829 hclge_mbx_handler(hdev);
2830
2831 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2832 }
2833
2834 static void hclge_service_task(struct work_struct *work)
2835 {
2836 struct hclge_dev *hdev =
2837 container_of(work, struct hclge_dev, service_task);
2838
2839 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2840 hclge_update_stats_for_all(hdev);
2841 hdev->hw_stats.stats_timer = 0;
2842 }
2843
2844 hclge_update_speed_duplex(hdev);
2845 hclge_update_link_status(hdev);
2846 hclge_service_complete(hdev);
2847 }
2848
2849 static void hclge_disable_sriov(struct hclge_dev *hdev)
2850 {
2851 /* If our VFs are assigned we cannot shut down SR-IOV
2852 * without causing issues, so just leave the hardware
2853 * available but disabled
2854 */
2855 if (pci_vfs_assigned(hdev->pdev)) {
2856 dev_warn(&hdev->pdev->dev,
2857 "disabling driver while VFs are assigned\n");
2858 return;
2859 }
2860
2861 pci_disable_sriov(hdev->pdev);
2862 }
2863
2864 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2865 {
2866 /* VF handle has no client */
2867 if (!handle->client)
2868 return container_of(handle, struct hclge_vport, nic);
2869 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2870 return container_of(handle, struct hclge_vport, roce);
2871 else
2872 return container_of(handle, struct hclge_vport, nic);
2873 }
2874
2875 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2876 struct hnae3_vector_info *vector_info)
2877 {
2878 struct hclge_vport *vport = hclge_get_vport(handle);
2879 struct hnae3_vector_info *vector = vector_info;
2880 struct hclge_dev *hdev = vport->back;
2881 int alloc = 0;
2882 int i, j;
2883
2884 vector_num = min(hdev->num_msi_left, vector_num);
2885
2886 for (j = 0; j < vector_num; j++) {
2887 for (i = 1; i < hdev->num_msi; i++) {
2888 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2889 vector->vector = pci_irq_vector(hdev->pdev, i);
2890 vector->io_addr = hdev->hw.io_base +
2891 HCLGE_VECTOR_REG_BASE +
2892 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2893 vport->vport_id *
2894 HCLGE_VECTOR_VF_OFFSET;
2895 hdev->vector_status[i] = vport->vport_id;
2896 hdev->vector_irq[i] = vector->vector;
2897
2898 vector++;
2899 alloc++;
2900
2901 break;
2902 }
2903 }
2904 }
2905 hdev->num_msi_left -= alloc;
2906 hdev->num_msi_used += alloc;
2907
2908 return alloc;
2909 }
2910
2911 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2912 {
2913 int i;
2914
2915 for (i = 0; i < hdev->num_msi; i++)
2916 if (vector == hdev->vector_irq[i])
2917 return i;
2918
2919 return -EINVAL;
2920 }
2921
2922 static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2923 {
2924 return HCLGE_RSS_KEY_SIZE;
2925 }
2926
2927 static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2928 {
2929 return HCLGE_RSS_IND_TBL_SIZE;
2930 }
2931
2932 static int hclge_get_rss_algo(struct hclge_dev *hdev)
2933 {
2934 struct hclge_rss_config_cmd *req;
2935 struct hclge_desc desc;
2936 int rss_hash_algo;
2937 int ret;
2938
2939 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, true);
2940
2941 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2942 if (ret) {
2943 dev_err(&hdev->pdev->dev,
2944 "Get link status error, status =%d\n", ret);
2945 return ret;
2946 }
2947
2948 req = (struct hclge_rss_config_cmd *)desc.data;
2949 rss_hash_algo = (req->hash_config & HCLGE_RSS_HASH_ALGO_MASK);
2950
2951 if (rss_hash_algo == HCLGE_RSS_HASH_ALGO_TOEPLITZ)
2952 return ETH_RSS_HASH_TOP;
2953
2954 return -EINVAL;
2955 }
2956
2957 static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2958 const u8 hfunc, const u8 *key)
2959 {
2960 struct hclge_rss_config_cmd *req;
2961 struct hclge_desc desc;
2962 int key_offset;
2963 int key_size;
2964 int ret;
2965
2966 req = (struct hclge_rss_config_cmd *)desc.data;
2967
2968 for (key_offset = 0; key_offset < 3; key_offset++) {
2969 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2970 false);
2971
2972 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
2973 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
2974
2975 if (key_offset == 2)
2976 key_size =
2977 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
2978 else
2979 key_size = HCLGE_RSS_HASH_KEY_NUM;
2980
2981 memcpy(req->hash_key,
2982 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
2983
2984 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2985 if (ret) {
2986 dev_err(&hdev->pdev->dev,
2987 "Configure RSS config fail, status = %d\n",
2988 ret);
2989 return ret;
2990 }
2991 }
2992 return 0;
2993 }
2994
2995 static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u32 *indir)
2996 {
2997 struct hclge_rss_indirection_table_cmd *req;
2998 struct hclge_desc desc;
2999 int i, j;
3000 int ret;
3001
3002 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
3003
3004 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
3005 hclge_cmd_setup_basic_desc
3006 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
3007
3008 req->start_table_index =
3009 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
3010 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
3011
3012 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
3013 req->rss_result[j] =
3014 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
3015
3016 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3017 if (ret) {
3018 dev_err(&hdev->pdev->dev,
3019 "Configure rss indir table fail,status = %d\n",
3020 ret);
3021 return ret;
3022 }
3023 }
3024 return 0;
3025 }
3026
3027 static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
3028 u16 *tc_size, u16 *tc_offset)
3029 {
3030 struct hclge_rss_tc_mode_cmd *req;
3031 struct hclge_desc desc;
3032 int ret;
3033 int i;
3034
3035 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
3036 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
3037
3038 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3039 u16 mode = 0;
3040
3041 hnae_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
3042 hnae_set_field(mode, HCLGE_RSS_TC_SIZE_M,
3043 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
3044 hnae_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
3045 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
3046
3047 req->rss_tc_mode[i] = cpu_to_le16(mode);
3048 }
3049
3050 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3051 if (ret) {
3052 dev_err(&hdev->pdev->dev,
3053 "Configure rss tc mode fail, status = %d\n", ret);
3054 return ret;
3055 }
3056
3057 return 0;
3058 }
3059
3060 static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3061 {
3062 struct hclge_rss_input_tuple_cmd *req;
3063 struct hclge_desc desc;
3064 int ret;
3065
3066 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3067
3068 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3069 req->ipv4_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3070 req->ipv4_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3071 req->ipv4_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
3072 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3073 req->ipv6_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3074 req->ipv6_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3075 req->ipv6_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
3076 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3077 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3078 if (ret) {
3079 dev_err(&hdev->pdev->dev,
3080 "Configure rss input fail, status = %d\n", ret);
3081 return ret;
3082 }
3083
3084 return 0;
3085 }
3086
3087 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3088 u8 *key, u8 *hfunc)
3089 {
3090 struct hclge_vport *vport = hclge_get_vport(handle);
3091 struct hclge_dev *hdev = vport->back;
3092 int i;
3093
3094 /* Get hash algorithm */
3095 if (hfunc)
3096 *hfunc = hclge_get_rss_algo(hdev);
3097
3098 /* Get the RSS Key required by the user */
3099 if (key)
3100 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3101
3102 /* Get indirect table */
3103 if (indir)
3104 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3105 indir[i] = vport->rss_indirection_tbl[i];
3106
3107 return 0;
3108 }
3109
3110 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3111 const u8 *key, const u8 hfunc)
3112 {
3113 struct hclge_vport *vport = hclge_get_vport(handle);
3114 struct hclge_dev *hdev = vport->back;
3115 u8 hash_algo;
3116 int ret, i;
3117
3118 /* Set the RSS Hash Key if specififed by the user */
3119 if (key) {
3120 /* Update the shadow RSS key with user specified qids */
3121 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3122
3123 if (hfunc == ETH_RSS_HASH_TOP ||
3124 hfunc == ETH_RSS_HASH_NO_CHANGE)
3125 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3126 else
3127 return -EINVAL;
3128 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3129 if (ret)
3130 return ret;
3131 }
3132
3133 /* Update the shadow RSS table with user specified qids */
3134 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3135 vport->rss_indirection_tbl[i] = indir[i];
3136
3137 /* Update the hardware */
3138 ret = hclge_set_rss_indir_table(hdev, indir);
3139 return ret;
3140 }
3141
3142 static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3143 {
3144 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3145
3146 if (nfc->data & RXH_L4_B_2_3)
3147 hash_sets |= HCLGE_D_PORT_BIT;
3148 else
3149 hash_sets &= ~HCLGE_D_PORT_BIT;
3150
3151 if (nfc->data & RXH_IP_SRC)
3152 hash_sets |= HCLGE_S_IP_BIT;
3153 else
3154 hash_sets &= ~HCLGE_S_IP_BIT;
3155
3156 if (nfc->data & RXH_IP_DST)
3157 hash_sets |= HCLGE_D_IP_BIT;
3158 else
3159 hash_sets &= ~HCLGE_D_IP_BIT;
3160
3161 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3162 hash_sets |= HCLGE_V_TAG_BIT;
3163
3164 return hash_sets;
3165 }
3166
3167 static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3168 struct ethtool_rxnfc *nfc)
3169 {
3170 struct hclge_vport *vport = hclge_get_vport(handle);
3171 struct hclge_dev *hdev = vport->back;
3172 struct hclge_rss_input_tuple_cmd *req;
3173 struct hclge_desc desc;
3174 u8 tuple_sets;
3175 int ret;
3176
3177 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3178 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3179 return -EINVAL;
3180
3181 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3182 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3183 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3184 if (ret) {
3185 dev_err(&hdev->pdev->dev,
3186 "Read rss tuple fail, status = %d\n", ret);
3187 return ret;
3188 }
3189
3190 hclge_cmd_reuse_desc(&desc, false);
3191
3192 tuple_sets = hclge_get_rss_hash_bits(nfc);
3193 switch (nfc->flow_type) {
3194 case TCP_V4_FLOW:
3195 req->ipv4_tcp_en = tuple_sets;
3196 break;
3197 case TCP_V6_FLOW:
3198 req->ipv6_tcp_en = tuple_sets;
3199 break;
3200 case UDP_V4_FLOW:
3201 req->ipv4_udp_en = tuple_sets;
3202 break;
3203 case UDP_V6_FLOW:
3204 req->ipv6_udp_en = tuple_sets;
3205 break;
3206 case SCTP_V4_FLOW:
3207 req->ipv4_sctp_en = tuple_sets;
3208 break;
3209 case SCTP_V6_FLOW:
3210 if ((nfc->data & RXH_L4_B_0_1) ||
3211 (nfc->data & RXH_L4_B_2_3))
3212 return -EINVAL;
3213
3214 req->ipv6_sctp_en = tuple_sets;
3215 break;
3216 case IPV4_FLOW:
3217 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3218 break;
3219 case IPV6_FLOW:
3220 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3221 break;
3222 default:
3223 return -EINVAL;
3224 }
3225
3226 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3227 if (ret)
3228 dev_err(&hdev->pdev->dev,
3229 "Set rss tuple fail, status = %d\n", ret);
3230
3231 return ret;
3232 }
3233
3234 static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3235 struct ethtool_rxnfc *nfc)
3236 {
3237 struct hclge_vport *vport = hclge_get_vport(handle);
3238 struct hclge_dev *hdev = vport->back;
3239 struct hclge_rss_input_tuple_cmd *req;
3240 struct hclge_desc desc;
3241 u8 tuple_sets;
3242 int ret;
3243
3244 nfc->data = 0;
3245
3246 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3247 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3248 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3249 if (ret) {
3250 dev_err(&hdev->pdev->dev,
3251 "Read rss tuple fail, status = %d\n", ret);
3252 return ret;
3253 }
3254
3255 switch (nfc->flow_type) {
3256 case TCP_V4_FLOW:
3257 tuple_sets = req->ipv4_tcp_en;
3258 break;
3259 case UDP_V4_FLOW:
3260 tuple_sets = req->ipv4_udp_en;
3261 break;
3262 case TCP_V6_FLOW:
3263 tuple_sets = req->ipv6_tcp_en;
3264 break;
3265 case UDP_V6_FLOW:
3266 tuple_sets = req->ipv6_udp_en;
3267 break;
3268 case SCTP_V4_FLOW:
3269 tuple_sets = req->ipv4_sctp_en;
3270 break;
3271 case SCTP_V6_FLOW:
3272 tuple_sets = req->ipv6_sctp_en;
3273 break;
3274 case IPV4_FLOW:
3275 case IPV6_FLOW:
3276 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3277 break;
3278 default:
3279 return -EINVAL;
3280 }
3281
3282 if (!tuple_sets)
3283 return 0;
3284
3285 if (tuple_sets & HCLGE_D_PORT_BIT)
3286 nfc->data |= RXH_L4_B_2_3;
3287 if (tuple_sets & HCLGE_S_PORT_BIT)
3288 nfc->data |= RXH_L4_B_0_1;
3289 if (tuple_sets & HCLGE_D_IP_BIT)
3290 nfc->data |= RXH_IP_DST;
3291 if (tuple_sets & HCLGE_S_IP_BIT)
3292 nfc->data |= RXH_IP_SRC;
3293
3294 return 0;
3295 }
3296
3297 static int hclge_get_tc_size(struct hnae3_handle *handle)
3298 {
3299 struct hclge_vport *vport = hclge_get_vport(handle);
3300 struct hclge_dev *hdev = vport->back;
3301
3302 return hdev->rss_size_max;
3303 }
3304
3305 int hclge_rss_init_hw(struct hclge_dev *hdev)
3306 {
3307 const u8 hfunc = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3308 struct hclge_vport *vport = hdev->vport;
3309 u16 tc_offset[HCLGE_MAX_TC_NUM];
3310 u8 rss_key[HCLGE_RSS_KEY_SIZE];
3311 u16 tc_valid[HCLGE_MAX_TC_NUM];
3312 u16 tc_size[HCLGE_MAX_TC_NUM];
3313 u32 *rss_indir = NULL;
3314 u16 rss_size = 0, roundup_size;
3315 const u8 *key;
3316 int i, ret, j;
3317
3318 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
3319 if (!rss_indir)
3320 return -ENOMEM;
3321
3322 /* Get default RSS key */
3323 netdev_rss_key_fill(rss_key, HCLGE_RSS_KEY_SIZE);
3324
3325 /* Initialize RSS indirect table for each vport */
3326 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3327 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) {
3328 vport[j].rss_indirection_tbl[i] =
3329 i % vport[j].alloc_rss_size;
3330
3331 /* vport 0 is for PF */
3332 if (j != 0)
3333 continue;
3334
3335 rss_size = vport[j].alloc_rss_size;
3336 rss_indir[i] = vport[j].rss_indirection_tbl[i];
3337 }
3338 }
3339 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3340 if (ret)
3341 goto err;
3342
3343 key = rss_key;
3344 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3345 if (ret)
3346 goto err;
3347
3348 ret = hclge_set_rss_input_tuple(hdev);
3349 if (ret)
3350 goto err;
3351
3352 /* Each TC have the same queue size, and tc_size set to hardware is
3353 * the log2 of roundup power of two of rss_size, the acutal queue
3354 * size is limited by indirection table.
3355 */
3356 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3357 dev_err(&hdev->pdev->dev,
3358 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3359 rss_size);
3360 ret = -EINVAL;
3361 goto err;
3362 }
3363
3364 roundup_size = roundup_pow_of_two(rss_size);
3365 roundup_size = ilog2(roundup_size);
3366
3367 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3368 tc_valid[i] = 0;
3369
3370 if (!(hdev->hw_tc_map & BIT(i)))
3371 continue;
3372
3373 tc_valid[i] = 1;
3374 tc_size[i] = roundup_size;
3375 tc_offset[i] = rss_size * i;
3376 }
3377
3378 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3379
3380 err:
3381 kfree(rss_indir);
3382
3383 return ret;
3384 }
3385
3386 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3387 int vector_id, bool en,
3388 struct hnae3_ring_chain_node *ring_chain)
3389 {
3390 struct hclge_dev *hdev = vport->back;
3391 struct hnae3_ring_chain_node *node;
3392 struct hclge_desc desc;
3393 struct hclge_ctrl_vector_chain_cmd *req
3394 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3395 enum hclge_cmd_status status;
3396 enum hclge_opcode_type op;
3397 u16 tqp_type_and_id;
3398 int i;
3399
3400 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3401 hclge_cmd_setup_basic_desc(&desc, op, false);
3402 req->int_vector_id = vector_id;
3403
3404 i = 0;
3405 for (node = ring_chain; node; node = node->next) {
3406 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
3407 hnae_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3408 HCLGE_INT_TYPE_S,
3409 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
3410 hnae_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3411 HCLGE_TQP_ID_S, node->tqp_index);
3412 hnae_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3413 HCLGE_INT_GL_IDX_S,
3414 hnae_get_field(node->int_gl_idx,
3415 HNAE3_RING_GL_IDX_M,
3416 HNAE3_RING_GL_IDX_S));
3417 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
3418 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3419 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
3420 req->vfid = vport->vport_id;
3421
3422 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3423 if (status) {
3424 dev_err(&hdev->pdev->dev,
3425 "Map TQP fail, status is %d.\n",
3426 status);
3427 return -EIO;
3428 }
3429 i = 0;
3430
3431 hclge_cmd_setup_basic_desc(&desc,
3432 op,
3433 false);
3434 req->int_vector_id = vector_id;
3435 }
3436 }
3437
3438 if (i > 0) {
3439 req->int_cause_num = i;
3440 req->vfid = vport->vport_id;
3441 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3442 if (status) {
3443 dev_err(&hdev->pdev->dev,
3444 "Map TQP fail, status is %d.\n", status);
3445 return -EIO;
3446 }
3447 }
3448
3449 return 0;
3450 }
3451
3452 static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3453 int vector,
3454 struct hnae3_ring_chain_node *ring_chain)
3455 {
3456 struct hclge_vport *vport = hclge_get_vport(handle);
3457 struct hclge_dev *hdev = vport->back;
3458 int vector_id;
3459
3460 vector_id = hclge_get_vector_index(hdev, vector);
3461 if (vector_id < 0) {
3462 dev_err(&hdev->pdev->dev,
3463 "Get vector index fail. vector_id =%d\n", vector_id);
3464 return vector_id;
3465 }
3466
3467 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
3468 }
3469
3470 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3471 int vector,
3472 struct hnae3_ring_chain_node *ring_chain)
3473 {
3474 struct hclge_vport *vport = hclge_get_vport(handle);
3475 struct hclge_dev *hdev = vport->back;
3476 int vector_id, ret;
3477
3478 vector_id = hclge_get_vector_index(hdev, vector);
3479 if (vector_id < 0) {
3480 dev_err(&handle->pdev->dev,
3481 "Get vector index fail. ret =%d\n", vector_id);
3482 return vector_id;
3483 }
3484
3485 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
3486 if (ret) {
3487 dev_err(&handle->pdev->dev,
3488 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3489 vector_id,
3490 ret);
3491 return ret;
3492 }
3493
3494 /* Free this MSIX or MSI vector */
3495 hclge_free_vector(hdev, vector_id);
3496
3497 return 0;
3498 }
3499
3500 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3501 struct hclge_promisc_param *param)
3502 {
3503 struct hclge_promisc_cfg_cmd *req;
3504 struct hclge_desc desc;
3505 int ret;
3506
3507 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3508
3509 req = (struct hclge_promisc_cfg_cmd *)desc.data;
3510 req->vf_id = param->vf_id;
3511 req->flag = (param->enable << HCLGE_PROMISC_EN_B);
3512
3513 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3514 if (ret) {
3515 dev_err(&hdev->pdev->dev,
3516 "Set promisc mode fail, status is %d.\n", ret);
3517 return ret;
3518 }
3519 return 0;
3520 }
3521
3522 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3523 bool en_mc, bool en_bc, int vport_id)
3524 {
3525 if (!param)
3526 return;
3527
3528 memset(param, 0, sizeof(struct hclge_promisc_param));
3529 if (en_uc)
3530 param->enable = HCLGE_PROMISC_EN_UC;
3531 if (en_mc)
3532 param->enable |= HCLGE_PROMISC_EN_MC;
3533 if (en_bc)
3534 param->enable |= HCLGE_PROMISC_EN_BC;
3535 param->vf_id = vport_id;
3536 }
3537
3538 static void hclge_set_promisc_mode(struct hnae3_handle *handle, u32 en)
3539 {
3540 struct hclge_vport *vport = hclge_get_vport(handle);
3541 struct hclge_dev *hdev = vport->back;
3542 struct hclge_promisc_param param;
3543
3544 hclge_promisc_param_init(&param, en, en, true, vport->vport_id);
3545 hclge_cmd_set_promisc_mode(hdev, &param);
3546 }
3547
3548 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3549 {
3550 struct hclge_desc desc;
3551 struct hclge_config_mac_mode_cmd *req =
3552 (struct hclge_config_mac_mode_cmd *)desc.data;
3553 u32 loop_en = 0;
3554 int ret;
3555
3556 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
3557 hnae_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3558 hnae_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3559 hnae_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3560 hnae_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3561 hnae_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3562 hnae_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3563 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3564 hnae_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3565 hnae_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3566 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3567 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3568 hnae_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3569 hnae_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3570 hnae_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
3571 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3572
3573 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3574 if (ret)
3575 dev_err(&hdev->pdev->dev,
3576 "mac enable fail, ret =%d.\n", ret);
3577 }
3578
3579 static int hclge_set_loopback(struct hnae3_handle *handle,
3580 enum hnae3_loop loop_mode, bool en)
3581 {
3582 struct hclge_vport *vport = hclge_get_vport(handle);
3583 struct hclge_config_mac_mode_cmd *req;
3584 struct hclge_dev *hdev = vport->back;
3585 struct hclge_desc desc;
3586 u32 loop_en;
3587 int ret;
3588
3589 switch (loop_mode) {
3590 case HNAE3_MAC_INTER_LOOP_MAC:
3591 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3592 /* 1 Read out the MAC mode config at first */
3593 hclge_cmd_setup_basic_desc(&desc,
3594 HCLGE_OPC_CONFIG_MAC_MODE,
3595 true);
3596 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3597 if (ret) {
3598 dev_err(&hdev->pdev->dev,
3599 "mac loopback get fail, ret =%d.\n",
3600 ret);
3601 return ret;
3602 }
3603
3604 /* 2 Then setup the loopback flag */
3605 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
3606 if (en)
3607 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 1);
3608 else
3609 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3610
3611 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3612
3613 /* 3 Config mac work mode with loopback flag
3614 * and its original configure parameters
3615 */
3616 hclge_cmd_reuse_desc(&desc, false);
3617 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3618 if (ret)
3619 dev_err(&hdev->pdev->dev,
3620 "mac loopback set fail, ret =%d.\n", ret);
3621 break;
3622 default:
3623 ret = -ENOTSUPP;
3624 dev_err(&hdev->pdev->dev,
3625 "loop_mode %d is not supported\n", loop_mode);
3626 break;
3627 }
3628
3629 return ret;
3630 }
3631
3632 static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3633 int stream_id, bool enable)
3634 {
3635 struct hclge_desc desc;
3636 struct hclge_cfg_com_tqp_queue_cmd *req =
3637 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
3638 int ret;
3639
3640 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3641 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3642 req->stream_id = cpu_to_le16(stream_id);
3643 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3644
3645 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3646 if (ret)
3647 dev_err(&hdev->pdev->dev,
3648 "Tqp enable fail, status =%d.\n", ret);
3649 return ret;
3650 }
3651
3652 static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3653 {
3654 struct hclge_vport *vport = hclge_get_vport(handle);
3655 struct hnae3_queue *queue;
3656 struct hclge_tqp *tqp;
3657 int i;
3658
3659 for (i = 0; i < vport->alloc_tqps; i++) {
3660 queue = handle->kinfo.tqp[i];
3661 tqp = container_of(queue, struct hclge_tqp, q);
3662 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3663 }
3664 }
3665
3666 static int hclge_ae_start(struct hnae3_handle *handle)
3667 {
3668 struct hclge_vport *vport = hclge_get_vport(handle);
3669 struct hclge_dev *hdev = vport->back;
3670 int i, queue_id, ret;
3671
3672 for (i = 0; i < vport->alloc_tqps; i++) {
3673 /* todo clear interrupt */
3674 /* ring enable */
3675 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3676 if (queue_id < 0) {
3677 dev_warn(&hdev->pdev->dev,
3678 "Get invalid queue id, ignore it\n");
3679 continue;
3680 }
3681
3682 hclge_tqp_enable(hdev, queue_id, 0, true);
3683 }
3684 /* mac enable */
3685 hclge_cfg_mac_mode(hdev, true);
3686 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
3687 mod_timer(&hdev->service_timer, jiffies + HZ);
3688
3689 ret = hclge_mac_start_phy(hdev);
3690 if (ret)
3691 return ret;
3692
3693 /* reset tqp stats */
3694 hclge_reset_tqp_stats(handle);
3695
3696 return 0;
3697 }
3698
3699 static void hclge_ae_stop(struct hnae3_handle *handle)
3700 {
3701 struct hclge_vport *vport = hclge_get_vport(handle);
3702 struct hclge_dev *hdev = vport->back;
3703 int i, queue_id;
3704
3705 for (i = 0; i < vport->alloc_tqps; i++) {
3706 /* Ring disable */
3707 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3708 if (queue_id < 0) {
3709 dev_warn(&hdev->pdev->dev,
3710 "Get invalid queue id, ignore it\n");
3711 continue;
3712 }
3713
3714 hclge_tqp_enable(hdev, queue_id, 0, false);
3715 }
3716 /* Mac disable */
3717 hclge_cfg_mac_mode(hdev, false);
3718
3719 hclge_mac_stop_phy(hdev);
3720
3721 /* reset tqp stats */
3722 hclge_reset_tqp_stats(handle);
3723 }
3724
3725 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3726 u16 cmdq_resp, u8 resp_code,
3727 enum hclge_mac_vlan_tbl_opcode op)
3728 {
3729 struct hclge_dev *hdev = vport->back;
3730 int return_status = -EIO;
3731
3732 if (cmdq_resp) {
3733 dev_err(&hdev->pdev->dev,
3734 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3735 cmdq_resp);
3736 return -EIO;
3737 }
3738
3739 if (op == HCLGE_MAC_VLAN_ADD) {
3740 if ((!resp_code) || (resp_code == 1)) {
3741 return_status = 0;
3742 } else if (resp_code == 2) {
3743 return_status = -EIO;
3744 dev_err(&hdev->pdev->dev,
3745 "add mac addr failed for uc_overflow.\n");
3746 } else if (resp_code == 3) {
3747 return_status = -EIO;
3748 dev_err(&hdev->pdev->dev,
3749 "add mac addr failed for mc_overflow.\n");
3750 } else {
3751 dev_err(&hdev->pdev->dev,
3752 "add mac addr failed for undefined, code=%d.\n",
3753 resp_code);
3754 }
3755 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3756 if (!resp_code) {
3757 return_status = 0;
3758 } else if (resp_code == 1) {
3759 return_status = -EIO;
3760 dev_dbg(&hdev->pdev->dev,
3761 "remove mac addr failed for miss.\n");
3762 } else {
3763 dev_err(&hdev->pdev->dev,
3764 "remove mac addr failed for undefined, code=%d.\n",
3765 resp_code);
3766 }
3767 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3768 if (!resp_code) {
3769 return_status = 0;
3770 } else if (resp_code == 1) {
3771 return_status = -EIO;
3772 dev_dbg(&hdev->pdev->dev,
3773 "lookup mac addr failed for miss.\n");
3774 } else {
3775 dev_err(&hdev->pdev->dev,
3776 "lookup mac addr failed for undefined, code=%d.\n",
3777 resp_code);
3778 }
3779 } else {
3780 return_status = -EIO;
3781 dev_err(&hdev->pdev->dev,
3782 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3783 op);
3784 }
3785
3786 return return_status;
3787 }
3788
3789 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3790 {
3791 int word_num;
3792 int bit_num;
3793
3794 if (vfid > 255 || vfid < 0)
3795 return -EIO;
3796
3797 if (vfid >= 0 && vfid <= 191) {
3798 word_num = vfid / 32;
3799 bit_num = vfid % 32;
3800 if (clr)
3801 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
3802 else
3803 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
3804 } else {
3805 word_num = (vfid - 192) / 32;
3806 bit_num = vfid % 32;
3807 if (clr)
3808 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
3809 else
3810 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
3811 }
3812
3813 return 0;
3814 }
3815
3816 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3817 {
3818 #define HCLGE_DESC_NUMBER 3
3819 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3820 int i, j;
3821
3822 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3823 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3824 if (desc[i].data[j])
3825 return false;
3826
3827 return true;
3828 }
3829
3830 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
3831 const u8 *addr)
3832 {
3833 const unsigned char *mac_addr = addr;
3834 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3835 (mac_addr[0]) | (mac_addr[1] << 8);
3836 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3837
3838 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3839 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3840 }
3841
3842 static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3843 const u8 *addr)
3844 {
3845 u16 high_val = addr[1] | (addr[0] << 8);
3846 struct hclge_dev *hdev = vport->back;
3847 u32 rsh = 4 - hdev->mta_mac_sel_type;
3848 u16 ret_val = (high_val >> rsh) & 0xfff;
3849
3850 return ret_val;
3851 }
3852
3853 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3854 enum hclge_mta_dmac_sel_type mta_mac_sel,
3855 bool enable)
3856 {
3857 struct hclge_mta_filter_mode_cmd *req;
3858 struct hclge_desc desc;
3859 int ret;
3860
3861 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
3862 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3863
3864 hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3865 enable);
3866 hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3867 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3868
3869 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3870 if (ret) {
3871 dev_err(&hdev->pdev->dev,
3872 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3873 ret);
3874 return ret;
3875 }
3876
3877 return 0;
3878 }
3879
3880 int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3881 u8 func_id,
3882 bool enable)
3883 {
3884 struct hclge_cfg_func_mta_filter_cmd *req;
3885 struct hclge_desc desc;
3886 int ret;
3887
3888 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
3889 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3890
3891 hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3892 enable);
3893 req->function_id = func_id;
3894
3895 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3896 if (ret) {
3897 dev_err(&hdev->pdev->dev,
3898 "Config func_id enable failed for cmd_send, ret =%d.\n",
3899 ret);
3900 return ret;
3901 }
3902
3903 return 0;
3904 }
3905
3906 static int hclge_set_mta_table_item(struct hclge_vport *vport,
3907 u16 idx,
3908 bool enable)
3909 {
3910 struct hclge_dev *hdev = vport->back;
3911 struct hclge_cfg_func_mta_item_cmd *req;
3912 struct hclge_desc desc;
3913 u16 item_idx = 0;
3914 int ret;
3915
3916 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
3917 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
3918 hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
3919
3920 hnae_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
3921 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
3922 req->item_idx = cpu_to_le16(item_idx);
3923
3924 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3925 if (ret) {
3926 dev_err(&hdev->pdev->dev,
3927 "Config mta table item failed for cmd_send, ret =%d.\n",
3928 ret);
3929 return ret;
3930 }
3931
3932 return 0;
3933 }
3934
3935 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
3936 struct hclge_mac_vlan_tbl_entry_cmd *req)
3937 {
3938 struct hclge_dev *hdev = vport->back;
3939 struct hclge_desc desc;
3940 u8 resp_code;
3941 u16 retval;
3942 int ret;
3943
3944 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
3945
3946 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
3947
3948 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3949 if (ret) {
3950 dev_err(&hdev->pdev->dev,
3951 "del mac addr failed for cmd_send, ret =%d.\n",
3952 ret);
3953 return ret;
3954 }
3955 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3956 retval = le16_to_cpu(desc.retval);
3957
3958 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
3959 HCLGE_MAC_VLAN_REMOVE);
3960 }
3961
3962 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
3963 struct hclge_mac_vlan_tbl_entry_cmd *req,
3964 struct hclge_desc *desc,
3965 bool is_mc)
3966 {
3967 struct hclge_dev *hdev = vport->back;
3968 u8 resp_code;
3969 u16 retval;
3970 int ret;
3971
3972 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
3973 if (is_mc) {
3974 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3975 memcpy(desc[0].data,
3976 req,
3977 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
3978 hclge_cmd_setup_basic_desc(&desc[1],
3979 HCLGE_OPC_MAC_VLAN_ADD,
3980 true);
3981 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3982 hclge_cmd_setup_basic_desc(&desc[2],
3983 HCLGE_OPC_MAC_VLAN_ADD,
3984 true);
3985 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3986 } else {
3987 memcpy(desc[0].data,
3988 req,
3989 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
3990 ret = hclge_cmd_send(&hdev->hw, desc, 1);
3991 }
3992 if (ret) {
3993 dev_err(&hdev->pdev->dev,
3994 "lookup mac addr failed for cmd_send, ret =%d.\n",
3995 ret);
3996 return ret;
3997 }
3998 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
3999 retval = le16_to_cpu(desc[0].retval);
4000
4001 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
4002 HCLGE_MAC_VLAN_LKUP);
4003 }
4004
4005 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
4006 struct hclge_mac_vlan_tbl_entry_cmd *req,
4007 struct hclge_desc *mc_desc)
4008 {
4009 struct hclge_dev *hdev = vport->back;
4010 int cfg_status;
4011 u8 resp_code;
4012 u16 retval;
4013 int ret;
4014
4015 if (!mc_desc) {
4016 struct hclge_desc desc;
4017
4018 hclge_cmd_setup_basic_desc(&desc,
4019 HCLGE_OPC_MAC_VLAN_ADD,
4020 false);
4021 memcpy(desc.data, req,
4022 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
4023 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4024 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4025 retval = le16_to_cpu(desc.retval);
4026
4027 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
4028 resp_code,
4029 HCLGE_MAC_VLAN_ADD);
4030 } else {
4031 hclge_cmd_reuse_desc(&mc_desc[0], false);
4032 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4033 hclge_cmd_reuse_desc(&mc_desc[1], false);
4034 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4035 hclge_cmd_reuse_desc(&mc_desc[2], false);
4036 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
4037 memcpy(mc_desc[0].data, req,
4038 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
4039 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
4040 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
4041 retval = le16_to_cpu(mc_desc[0].retval);
4042
4043 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
4044 resp_code,
4045 HCLGE_MAC_VLAN_ADD);
4046 }
4047
4048 if (ret) {
4049 dev_err(&hdev->pdev->dev,
4050 "add mac addr failed for cmd_send, ret =%d.\n",
4051 ret);
4052 return ret;
4053 }
4054
4055 return cfg_status;
4056 }
4057
4058 static int hclge_add_uc_addr(struct hnae3_handle *handle,
4059 const unsigned char *addr)
4060 {
4061 struct hclge_vport *vport = hclge_get_vport(handle);
4062
4063 return hclge_add_uc_addr_common(vport, addr);
4064 }
4065
4066 int hclge_add_uc_addr_common(struct hclge_vport *vport,
4067 const unsigned char *addr)
4068 {
4069 struct hclge_dev *hdev = vport->back;
4070 struct hclge_mac_vlan_tbl_entry_cmd req;
4071 enum hclge_cmd_status status;
4072 u16 egress_port = 0;
4073
4074 /* mac addr check */
4075 if (is_zero_ether_addr(addr) ||
4076 is_broadcast_ether_addr(addr) ||
4077 is_multicast_ether_addr(addr)) {
4078 dev_err(&hdev->pdev->dev,
4079 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4080 addr,
4081 is_zero_ether_addr(addr),
4082 is_broadcast_ether_addr(addr),
4083 is_multicast_ether_addr(addr));
4084 return -EINVAL;
4085 }
4086
4087 memset(&req, 0, sizeof(req));
4088 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4089 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4090 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0);
4091 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4092
4093 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_SW_EN_B, 0);
4094 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_TYPE_B, 0);
4095 hnae_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
4096 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
4097 hnae_set_field(egress_port, HCLGE_MAC_EPORT_PFID_M,
4098 HCLGE_MAC_EPORT_PFID_S, 0);
4099
4100 req.egress_port = cpu_to_le16(egress_port);
4101
4102 hclge_prepare_mac_addr(&req, addr);
4103
4104 status = hclge_add_mac_vlan_tbl(vport, &req, NULL);
4105
4106 return status;
4107 }
4108
4109 static int hclge_rm_uc_addr(struct hnae3_handle *handle,
4110 const unsigned char *addr)
4111 {
4112 struct hclge_vport *vport = hclge_get_vport(handle);
4113
4114 return hclge_rm_uc_addr_common(vport, addr);
4115 }
4116
4117 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4118 const unsigned char *addr)
4119 {
4120 struct hclge_dev *hdev = vport->back;
4121 struct hclge_mac_vlan_tbl_entry_cmd req;
4122 enum hclge_cmd_status status;
4123
4124 /* mac addr check */
4125 if (is_zero_ether_addr(addr) ||
4126 is_broadcast_ether_addr(addr) ||
4127 is_multicast_ether_addr(addr)) {
4128 dev_dbg(&hdev->pdev->dev,
4129 "Remove mac err! invalid mac:%pM.\n",
4130 addr);
4131 return -EINVAL;
4132 }
4133
4134 memset(&req, 0, sizeof(req));
4135 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4136 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4137 hclge_prepare_mac_addr(&req, addr);
4138 status = hclge_remove_mac_vlan_tbl(vport, &req);
4139
4140 return status;
4141 }
4142
4143 static int hclge_add_mc_addr(struct hnae3_handle *handle,
4144 const unsigned char *addr)
4145 {
4146 struct hclge_vport *vport = hclge_get_vport(handle);
4147
4148 return hclge_add_mc_addr_common(vport, addr);
4149 }
4150
4151 int hclge_add_mc_addr_common(struct hclge_vport *vport,
4152 const unsigned char *addr)
4153 {
4154 struct hclge_dev *hdev = vport->back;
4155 struct hclge_mac_vlan_tbl_entry_cmd req;
4156 struct hclge_desc desc[3];
4157 u16 tbl_idx;
4158 int status;
4159
4160 /* mac addr check */
4161 if (!is_multicast_ether_addr(addr)) {
4162 dev_err(&hdev->pdev->dev,
4163 "Add mc mac err! invalid mac:%pM.\n",
4164 addr);
4165 return -EINVAL;
4166 }
4167 memset(&req, 0, sizeof(req));
4168 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4169 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4170 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4171 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4172 hclge_prepare_mac_addr(&req, addr);
4173 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4174 if (!status) {
4175 /* This mac addr exist, update VFID for it */
4176 hclge_update_desc_vfid(desc, vport->vport_id, false);
4177 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4178 } else {
4179 /* This mac addr do not exist, add new entry for it */
4180 memset(desc[0].data, 0, sizeof(desc[0].data));
4181 memset(desc[1].data, 0, sizeof(desc[0].data));
4182 memset(desc[2].data, 0, sizeof(desc[0].data));
4183 hclge_update_desc_vfid(desc, vport->vport_id, false);
4184 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4185 }
4186
4187 /* Set MTA table for this MAC address */
4188 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4189 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4190
4191 return status;
4192 }
4193
4194 static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4195 const unsigned char *addr)
4196 {
4197 struct hclge_vport *vport = hclge_get_vport(handle);
4198
4199 return hclge_rm_mc_addr_common(vport, addr);
4200 }
4201
4202 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4203 const unsigned char *addr)
4204 {
4205 struct hclge_dev *hdev = vport->back;
4206 struct hclge_mac_vlan_tbl_entry_cmd req;
4207 enum hclge_cmd_status status;
4208 struct hclge_desc desc[3];
4209 u16 tbl_idx;
4210
4211 /* mac addr check */
4212 if (!is_multicast_ether_addr(addr)) {
4213 dev_dbg(&hdev->pdev->dev,
4214 "Remove mc mac err! invalid mac:%pM.\n",
4215 addr);
4216 return -EINVAL;
4217 }
4218
4219 memset(&req, 0, sizeof(req));
4220 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4221 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4222 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4223 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4224 hclge_prepare_mac_addr(&req, addr);
4225 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4226 if (!status) {
4227 /* This mac addr exist, remove this handle's VFID for it */
4228 hclge_update_desc_vfid(desc, vport->vport_id, true);
4229
4230 if (hclge_is_all_function_id_zero(desc))
4231 /* All the vfid is zero, so need to delete this entry */
4232 status = hclge_remove_mac_vlan_tbl(vport, &req);
4233 else
4234 /* Not all the vfid is zero, update the vfid */
4235 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4236
4237 } else {
4238 /* This mac addr do not exist, can't delete it */
4239 dev_err(&hdev->pdev->dev,
4240 "Rm multicast mac addr failed, ret = %d.\n",
4241 status);
4242 return -EIO;
4243 }
4244
4245 /* Set MTB table for this MAC address */
4246 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4247 status = hclge_set_mta_table_item(vport, tbl_idx, false);
4248
4249 return status;
4250 }
4251
4252 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4253 {
4254 struct hclge_vport *vport = hclge_get_vport(handle);
4255 struct hclge_dev *hdev = vport->back;
4256
4257 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4258 }
4259
4260 static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p)
4261 {
4262 const unsigned char *new_addr = (const unsigned char *)p;
4263 struct hclge_vport *vport = hclge_get_vport(handle);
4264 struct hclge_dev *hdev = vport->back;
4265 int ret;
4266
4267 /* mac addr check */
4268 if (is_zero_ether_addr(new_addr) ||
4269 is_broadcast_ether_addr(new_addr) ||
4270 is_multicast_ether_addr(new_addr)) {
4271 dev_err(&hdev->pdev->dev,
4272 "Change uc mac err! invalid mac:%p.\n",
4273 new_addr);
4274 return -EINVAL;
4275 }
4276
4277 ret = hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr);
4278 if (ret)
4279 dev_warn(&hdev->pdev->dev,
4280 "remove old uc mac address fail, ret =%d.\n",
4281 ret);
4282
4283 ret = hclge_add_uc_addr(handle, new_addr);
4284 if (ret) {
4285 dev_err(&hdev->pdev->dev,
4286 "add uc mac address fail, ret =%d.\n",
4287 ret);
4288
4289 ret = hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr);
4290 if (ret) {
4291 dev_err(&hdev->pdev->dev,
4292 "restore uc mac address fail, ret =%d.\n",
4293 ret);
4294 }
4295
4296 return -EIO;
4297 }
4298
4299 ret = hclge_mac_pause_addr_cfg(hdev, new_addr);
4300 if (ret) {
4301 dev_err(&hdev->pdev->dev,
4302 "configure mac pause address fail, ret =%d.\n",
4303 ret);
4304 return -EIO;
4305 }
4306
4307 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4308
4309 return 0;
4310 }
4311
4312 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4313 bool filter_en)
4314 {
4315 struct hclge_vlan_filter_ctrl_cmd *req;
4316 struct hclge_desc desc;
4317 int ret;
4318
4319 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4320
4321 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
4322 req->vlan_type = vlan_type;
4323 req->vlan_fe = filter_en;
4324
4325 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4326 if (ret) {
4327 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4328 ret);
4329 return ret;
4330 }
4331
4332 return 0;
4333 }
4334
4335 #define HCLGE_FILTER_TYPE_VF 0
4336 #define HCLGE_FILTER_TYPE_PORT 1
4337
4338 static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
4339 {
4340 struct hclge_vport *vport = hclge_get_vport(handle);
4341 struct hclge_dev *hdev = vport->back;
4342
4343 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable);
4344 }
4345
4346 int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4347 bool is_kill, u16 vlan, u8 qos, __be16 proto)
4348 {
4349 #define HCLGE_MAX_VF_BYTES 16
4350 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4351 struct hclge_vlan_filter_vf_cfg_cmd *req1;
4352 struct hclge_desc desc[2];
4353 u8 vf_byte_val;
4354 u8 vf_byte_off;
4355 int ret;
4356
4357 hclge_cmd_setup_basic_desc(&desc[0],
4358 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4359 hclge_cmd_setup_basic_desc(&desc[1],
4360 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4361
4362 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4363
4364 vf_byte_off = vfid / 8;
4365 vf_byte_val = 1 << (vfid % 8);
4366
4367 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4368 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
4369
4370 req0->vlan_id = cpu_to_le16(vlan);
4371 req0->vlan_cfg = is_kill;
4372
4373 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4374 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4375 else
4376 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4377
4378 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4379 if (ret) {
4380 dev_err(&hdev->pdev->dev,
4381 "Send vf vlan command fail, ret =%d.\n",
4382 ret);
4383 return ret;
4384 }
4385
4386 if (!is_kill) {
4387 if (!req0->resp_code || req0->resp_code == 1)
4388 return 0;
4389
4390 dev_err(&hdev->pdev->dev,
4391 "Add vf vlan filter fail, ret =%d.\n",
4392 req0->resp_code);
4393 } else {
4394 if (!req0->resp_code)
4395 return 0;
4396
4397 dev_err(&hdev->pdev->dev,
4398 "Kill vf vlan filter fail, ret =%d.\n",
4399 req0->resp_code);
4400 }
4401
4402 return -EIO;
4403 }
4404
4405 static int hclge_set_port_vlan_filter(struct hnae3_handle *handle,
4406 __be16 proto, u16 vlan_id,
4407 bool is_kill)
4408 {
4409 struct hclge_vport *vport = hclge_get_vport(handle);
4410 struct hclge_dev *hdev = vport->back;
4411 struct hclge_vlan_filter_pf_cfg_cmd *req;
4412 struct hclge_desc desc;
4413 u8 vlan_offset_byte_val;
4414 u8 vlan_offset_byte;
4415 u8 vlan_offset_160;
4416 int ret;
4417
4418 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4419
4420 vlan_offset_160 = vlan_id / 160;
4421 vlan_offset_byte = (vlan_id % 160) / 8;
4422 vlan_offset_byte_val = 1 << (vlan_id % 8);
4423
4424 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
4425 req->vlan_offset = vlan_offset_160;
4426 req->vlan_cfg = is_kill;
4427 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4428
4429 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4430 if (ret) {
4431 dev_err(&hdev->pdev->dev,
4432 "port vlan command, send fail, ret =%d.\n",
4433 ret);
4434 return ret;
4435 }
4436
4437 ret = hclge_set_vf_vlan_common(hdev, 0, is_kill, vlan_id, 0, proto);
4438 if (ret) {
4439 dev_err(&hdev->pdev->dev,
4440 "Set pf vlan filter config fail, ret =%d.\n",
4441 ret);
4442 return -EIO;
4443 }
4444
4445 return 0;
4446 }
4447
4448 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4449 u16 vlan, u8 qos, __be16 proto)
4450 {
4451 struct hclge_vport *vport = hclge_get_vport(handle);
4452 struct hclge_dev *hdev = vport->back;
4453
4454 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4455 return -EINVAL;
4456 if (proto != htons(ETH_P_8021Q))
4457 return -EPROTONOSUPPORT;
4458
4459 return hclge_set_vf_vlan_common(hdev, vfid, false, vlan, qos, proto);
4460 }
4461
4462 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
4463 {
4464 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
4465 struct hclge_vport_vtag_tx_cfg_cmd *req;
4466 struct hclge_dev *hdev = vport->back;
4467 struct hclge_desc desc;
4468 int status;
4469
4470 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
4471
4472 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
4473 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
4474 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
4475 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG_B,
4476 vcfg->accept_tag ? 1 : 0);
4477 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG_B,
4478 vcfg->accept_untag ? 1 : 0);
4479 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
4480 vcfg->insert_tag1_en ? 1 : 0);
4481 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
4482 vcfg->insert_tag2_en ? 1 : 0);
4483 hnae_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
4484
4485 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4486 req->vf_bitmap[req->vf_offset] =
4487 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4488
4489 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4490 if (status)
4491 dev_err(&hdev->pdev->dev,
4492 "Send port txvlan cfg command fail, ret =%d\n",
4493 status);
4494
4495 return status;
4496 }
4497
4498 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
4499 {
4500 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
4501 struct hclge_vport_vtag_rx_cfg_cmd *req;
4502 struct hclge_dev *hdev = vport->back;
4503 struct hclge_desc desc;
4504 int status;
4505
4506 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
4507
4508 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
4509 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
4510 vcfg->strip_tag1_en ? 1 : 0);
4511 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
4512 vcfg->strip_tag2_en ? 1 : 0);
4513 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
4514 vcfg->vlan1_vlan_prionly ? 1 : 0);
4515 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
4516 vcfg->vlan2_vlan_prionly ? 1 : 0);
4517
4518 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4519 req->vf_bitmap[req->vf_offset] =
4520 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4521
4522 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4523 if (status)
4524 dev_err(&hdev->pdev->dev,
4525 "Send port rxvlan cfg command fail, ret =%d\n",
4526 status);
4527
4528 return status;
4529 }
4530
4531 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
4532 {
4533 struct hclge_rx_vlan_type_cfg_cmd *rx_req;
4534 struct hclge_tx_vlan_type_cfg_cmd *tx_req;
4535 struct hclge_desc desc;
4536 int status;
4537
4538 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
4539 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
4540 rx_req->ot_fst_vlan_type =
4541 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
4542 rx_req->ot_sec_vlan_type =
4543 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
4544 rx_req->in_fst_vlan_type =
4545 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
4546 rx_req->in_sec_vlan_type =
4547 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
4548
4549 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4550 if (status) {
4551 dev_err(&hdev->pdev->dev,
4552 "Send rxvlan protocol type command fail, ret =%d\n",
4553 status);
4554 return status;
4555 }
4556
4557 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
4558
4559 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data;
4560 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
4561 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
4562
4563 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4564 if (status)
4565 dev_err(&hdev->pdev->dev,
4566 "Send txvlan protocol type command fail, ret =%d\n",
4567 status);
4568
4569 return status;
4570 }
4571
4572 static int hclge_init_vlan_config(struct hclge_dev *hdev)
4573 {
4574 #define HCLGE_DEF_VLAN_TYPE 0x8100
4575
4576 struct hnae3_handle *handle;
4577 struct hclge_vport *vport;
4578 int ret;
4579 int i;
4580
4581 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true);
4582 if (ret)
4583 return ret;
4584
4585 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true);
4586 if (ret)
4587 return ret;
4588
4589 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4590 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4591 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4592 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4593 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
4594 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
4595
4596 ret = hclge_set_vlan_protocol_type(hdev);
4597 if (ret)
4598 return ret;
4599
4600 for (i = 0; i < hdev->num_alloc_vport; i++) {
4601 vport = &hdev->vport[i];
4602 vport->txvlan_cfg.accept_tag = true;
4603 vport->txvlan_cfg.accept_untag = true;
4604 vport->txvlan_cfg.insert_tag1_en = false;
4605 vport->txvlan_cfg.insert_tag2_en = false;
4606 vport->txvlan_cfg.default_tag1 = 0;
4607 vport->txvlan_cfg.default_tag2 = 0;
4608
4609 ret = hclge_set_vlan_tx_offload_cfg(vport);
4610 if (ret)
4611 return ret;
4612
4613 vport->rxvlan_cfg.strip_tag1_en = false;
4614 vport->rxvlan_cfg.strip_tag2_en = true;
4615 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4616 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4617
4618 ret = hclge_set_vlan_rx_offload_cfg(vport);
4619 if (ret)
4620 return ret;
4621 }
4622
4623 handle = &hdev->vport[0].nic;
4624 return hclge_set_port_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
4625 }
4626
4627 static int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
4628 {
4629 struct hclge_vport *vport = hclge_get_vport(handle);
4630
4631 vport->rxvlan_cfg.strip_tag1_en = false;
4632 vport->rxvlan_cfg.strip_tag2_en = enable;
4633 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4634 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4635
4636 return hclge_set_vlan_rx_offload_cfg(vport);
4637 }
4638
4639 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
4640 {
4641 struct hclge_vport *vport = hclge_get_vport(handle);
4642 struct hclge_config_max_frm_size_cmd *req;
4643 struct hclge_dev *hdev = vport->back;
4644 struct hclge_desc desc;
4645 int max_frm_size;
4646 int ret;
4647
4648 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4649
4650 if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
4651 max_frm_size > HCLGE_MAC_MAX_FRAME)
4652 return -EINVAL;
4653
4654 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
4655
4656 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
4657
4658 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
4659 req->max_frm_size = cpu_to_le16(max_frm_size);
4660
4661 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4662 if (ret) {
4663 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
4664 return ret;
4665 }
4666
4667 hdev->mps = max_frm_size;
4668
4669 return 0;
4670 }
4671
4672 static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
4673 bool enable)
4674 {
4675 struct hclge_reset_tqp_queue_cmd *req;
4676 struct hclge_desc desc;
4677 int ret;
4678
4679 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
4680
4681 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
4682 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4683 hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
4684
4685 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4686 if (ret) {
4687 dev_err(&hdev->pdev->dev,
4688 "Send tqp reset cmd error, status =%d\n", ret);
4689 return ret;
4690 }
4691
4692 return 0;
4693 }
4694
4695 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
4696 {
4697 struct hclge_reset_tqp_queue_cmd *req;
4698 struct hclge_desc desc;
4699 int ret;
4700
4701 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
4702
4703 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
4704 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4705
4706 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4707 if (ret) {
4708 dev_err(&hdev->pdev->dev,
4709 "Get reset status error, status =%d\n", ret);
4710 return ret;
4711 }
4712
4713 return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
4714 }
4715
4716 void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
4717 {
4718 struct hclge_vport *vport = hclge_get_vport(handle);
4719 struct hclge_dev *hdev = vport->back;
4720 int reset_try_times = 0;
4721 int reset_status;
4722 int ret;
4723
4724 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
4725 if (ret) {
4726 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
4727 return;
4728 }
4729
4730 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, true);
4731 if (ret) {
4732 dev_warn(&hdev->pdev->dev,
4733 "Send reset tqp cmd fail, ret = %d\n", ret);
4734 return;
4735 }
4736
4737 reset_try_times = 0;
4738 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
4739 /* Wait for tqp hw reset */
4740 msleep(20);
4741 reset_status = hclge_get_reset_status(hdev, queue_id);
4742 if (reset_status)
4743 break;
4744 }
4745
4746 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
4747 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
4748 return;
4749 }
4750
4751 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, false);
4752 if (ret) {
4753 dev_warn(&hdev->pdev->dev,
4754 "Deassert the soft reset fail, ret = %d\n", ret);
4755 return;
4756 }
4757 }
4758
4759 static u32 hclge_get_fw_version(struct hnae3_handle *handle)
4760 {
4761 struct hclge_vport *vport = hclge_get_vport(handle);
4762 struct hclge_dev *hdev = vport->back;
4763
4764 return hdev->fw_version;
4765 }
4766
4767 static void hclge_get_flowctrl_adv(struct hnae3_handle *handle,
4768 u32 *flowctrl_adv)
4769 {
4770 struct hclge_vport *vport = hclge_get_vport(handle);
4771 struct hclge_dev *hdev = vport->back;
4772 struct phy_device *phydev = hdev->hw.mac.phydev;
4773
4774 if (!phydev)
4775 return;
4776
4777 *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) |
4778 (phydev->advertising & ADVERTISED_Asym_Pause);
4779 }
4780
4781 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
4782 {
4783 struct phy_device *phydev = hdev->hw.mac.phydev;
4784
4785 if (!phydev)
4786 return;
4787
4788 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
4789
4790 if (rx_en)
4791 phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
4792
4793 if (tx_en)
4794 phydev->advertising ^= ADVERTISED_Asym_Pause;
4795 }
4796
4797 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
4798 {
4799 int ret;
4800
4801 if (rx_en && tx_en)
4802 hdev->fc_mode_last_time = HCLGE_FC_FULL;
4803 else if (rx_en && !tx_en)
4804 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
4805 else if (!rx_en && tx_en)
4806 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
4807 else
4808 hdev->fc_mode_last_time = HCLGE_FC_NONE;
4809
4810 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
4811 return 0;
4812
4813 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
4814 if (ret) {
4815 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
4816 ret);
4817 return ret;
4818 }
4819
4820 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
4821
4822 return 0;
4823 }
4824
4825 int hclge_cfg_flowctrl(struct hclge_dev *hdev)
4826 {
4827 struct phy_device *phydev = hdev->hw.mac.phydev;
4828 u16 remote_advertising = 0;
4829 u16 local_advertising = 0;
4830 u32 rx_pause, tx_pause;
4831 u8 flowctl;
4832
4833 if (!phydev->link || !phydev->autoneg)
4834 return 0;
4835
4836 if (phydev->advertising & ADVERTISED_Pause)
4837 local_advertising = ADVERTISE_PAUSE_CAP;
4838
4839 if (phydev->advertising & ADVERTISED_Asym_Pause)
4840 local_advertising |= ADVERTISE_PAUSE_ASYM;
4841
4842 if (phydev->pause)
4843 remote_advertising = LPA_PAUSE_CAP;
4844
4845 if (phydev->asym_pause)
4846 remote_advertising |= LPA_PAUSE_ASYM;
4847
4848 flowctl = mii_resolve_flowctrl_fdx(local_advertising,
4849 remote_advertising);
4850 tx_pause = flowctl & FLOW_CTRL_TX;
4851 rx_pause = flowctl & FLOW_CTRL_RX;
4852
4853 if (phydev->duplex == HCLGE_MAC_HALF) {
4854 tx_pause = 0;
4855 rx_pause = 0;
4856 }
4857
4858 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
4859 }
4860
4861 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
4862 u32 *rx_en, u32 *tx_en)
4863 {
4864 struct hclge_vport *vport = hclge_get_vport(handle);
4865 struct hclge_dev *hdev = vport->back;
4866
4867 *auto_neg = hclge_get_autoneg(handle);
4868
4869 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
4870 *rx_en = 0;
4871 *tx_en = 0;
4872 return;
4873 }
4874
4875 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
4876 *rx_en = 1;
4877 *tx_en = 0;
4878 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
4879 *tx_en = 1;
4880 *rx_en = 0;
4881 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
4882 *rx_en = 1;
4883 *tx_en = 1;
4884 } else {
4885 *rx_en = 0;
4886 *tx_en = 0;
4887 }
4888 }
4889
4890 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
4891 u32 rx_en, u32 tx_en)
4892 {
4893 struct hclge_vport *vport = hclge_get_vport(handle);
4894 struct hclge_dev *hdev = vport->back;
4895 struct phy_device *phydev = hdev->hw.mac.phydev;
4896 u32 fc_autoneg;
4897
4898 /* Only support flow control negotiation for netdev with
4899 * phy attached for now.
4900 */
4901 if (!phydev)
4902 return -EOPNOTSUPP;
4903
4904 fc_autoneg = hclge_get_autoneg(handle);
4905 if (auto_neg != fc_autoneg) {
4906 dev_info(&hdev->pdev->dev,
4907 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
4908 return -EOPNOTSUPP;
4909 }
4910
4911 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
4912 dev_info(&hdev->pdev->dev,
4913 "Priority flow control enabled. Cannot set link flow control.\n");
4914 return -EOPNOTSUPP;
4915 }
4916
4917 hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
4918
4919 if (!fc_autoneg)
4920 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
4921
4922 return phy_start_aneg(phydev);
4923 }
4924
4925 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
4926 u8 *auto_neg, u32 *speed, u8 *duplex)
4927 {
4928 struct hclge_vport *vport = hclge_get_vport(handle);
4929 struct hclge_dev *hdev = vport->back;
4930
4931 if (speed)
4932 *speed = hdev->hw.mac.speed;
4933 if (duplex)
4934 *duplex = hdev->hw.mac.duplex;
4935 if (auto_neg)
4936 *auto_neg = hdev->hw.mac.autoneg;
4937 }
4938
4939 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
4940 {
4941 struct hclge_vport *vport = hclge_get_vport(handle);
4942 struct hclge_dev *hdev = vport->back;
4943
4944 if (media_type)
4945 *media_type = hdev->hw.mac.media_type;
4946 }
4947
4948 static void hclge_get_mdix_mode(struct hnae3_handle *handle,
4949 u8 *tp_mdix_ctrl, u8 *tp_mdix)
4950 {
4951 struct hclge_vport *vport = hclge_get_vport(handle);
4952 struct hclge_dev *hdev = vport->back;
4953 struct phy_device *phydev = hdev->hw.mac.phydev;
4954 int mdix_ctrl, mdix, retval, is_resolved;
4955
4956 if (!phydev) {
4957 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
4958 *tp_mdix = ETH_TP_MDI_INVALID;
4959 return;
4960 }
4961
4962 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
4963
4964 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
4965 mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
4966 HCLGE_PHY_MDIX_CTRL_S);
4967
4968 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
4969 mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
4970 is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
4971
4972 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
4973
4974 switch (mdix_ctrl) {
4975 case 0x0:
4976 *tp_mdix_ctrl = ETH_TP_MDI;
4977 break;
4978 case 0x1:
4979 *tp_mdix_ctrl = ETH_TP_MDI_X;
4980 break;
4981 case 0x3:
4982 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
4983 break;
4984 default:
4985 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
4986 break;
4987 }
4988
4989 if (!is_resolved)
4990 *tp_mdix = ETH_TP_MDI_INVALID;
4991 else if (mdix)
4992 *tp_mdix = ETH_TP_MDI_X;
4993 else
4994 *tp_mdix = ETH_TP_MDI;
4995 }
4996
4997 static int hclge_init_client_instance(struct hnae3_client *client,
4998 struct hnae3_ae_dev *ae_dev)
4999 {
5000 struct hclge_dev *hdev = ae_dev->priv;
5001 struct hclge_vport *vport;
5002 int i, ret;
5003
5004 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5005 vport = &hdev->vport[i];
5006
5007 switch (client->type) {
5008 case HNAE3_CLIENT_KNIC:
5009
5010 hdev->nic_client = client;
5011 vport->nic.client = client;
5012 ret = client->ops->init_instance(&vport->nic);
5013 if (ret)
5014 goto err;
5015
5016 if (hdev->roce_client &&
5017 hnae3_dev_roce_supported(hdev)) {
5018 struct hnae3_client *rc = hdev->roce_client;
5019
5020 ret = hclge_init_roce_base_info(vport);
5021 if (ret)
5022 goto err;
5023
5024 ret = rc->ops->init_instance(&vport->roce);
5025 if (ret)
5026 goto err;
5027 }
5028
5029 break;
5030 case HNAE3_CLIENT_UNIC:
5031 hdev->nic_client = client;
5032 vport->nic.client = client;
5033
5034 ret = client->ops->init_instance(&vport->nic);
5035 if (ret)
5036 goto err;
5037
5038 break;
5039 case HNAE3_CLIENT_ROCE:
5040 if (hnae3_dev_roce_supported(hdev)) {
5041 hdev->roce_client = client;
5042 vport->roce.client = client;
5043 }
5044
5045 if (hdev->roce_client && hdev->nic_client) {
5046 ret = hclge_init_roce_base_info(vport);
5047 if (ret)
5048 goto err;
5049
5050 ret = client->ops->init_instance(&vport->roce);
5051 if (ret)
5052 goto err;
5053 }
5054 }
5055 }
5056
5057 return 0;
5058 err:
5059 return ret;
5060 }
5061
5062 static void hclge_uninit_client_instance(struct hnae3_client *client,
5063 struct hnae3_ae_dev *ae_dev)
5064 {
5065 struct hclge_dev *hdev = ae_dev->priv;
5066 struct hclge_vport *vport;
5067 int i;
5068
5069 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5070 vport = &hdev->vport[i];
5071 if (hdev->roce_client) {
5072 hdev->roce_client->ops->uninit_instance(&vport->roce,
5073 0);
5074 hdev->roce_client = NULL;
5075 vport->roce.client = NULL;
5076 }
5077 if (client->type == HNAE3_CLIENT_ROCE)
5078 return;
5079 if (client->ops->uninit_instance) {
5080 client->ops->uninit_instance(&vport->nic, 0);
5081 hdev->nic_client = NULL;
5082 vport->nic.client = NULL;
5083 }
5084 }
5085 }
5086
5087 static int hclge_pci_init(struct hclge_dev *hdev)
5088 {
5089 struct pci_dev *pdev = hdev->pdev;
5090 struct hclge_hw *hw;
5091 int ret;
5092
5093 ret = pci_enable_device(pdev);
5094 if (ret) {
5095 dev_err(&pdev->dev, "failed to enable PCI device\n");
5096 goto err_no_drvdata;
5097 }
5098
5099 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
5100 if (ret) {
5101 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
5102 if (ret) {
5103 dev_err(&pdev->dev,
5104 "can't set consistent PCI DMA");
5105 goto err_disable_device;
5106 }
5107 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
5108 }
5109
5110 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
5111 if (ret) {
5112 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
5113 goto err_disable_device;
5114 }
5115
5116 pci_set_master(pdev);
5117 hw = &hdev->hw;
5118 hw->back = hdev;
5119 hw->io_base = pcim_iomap(pdev, 2, 0);
5120 if (!hw->io_base) {
5121 dev_err(&pdev->dev, "Can't map configuration register space\n");
5122 ret = -ENOMEM;
5123 goto err_clr_master;
5124 }
5125
5126 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
5127
5128 return 0;
5129 err_clr_master:
5130 pci_clear_master(pdev);
5131 pci_release_regions(pdev);
5132 err_disable_device:
5133 pci_disable_device(pdev);
5134 err_no_drvdata:
5135 pci_set_drvdata(pdev, NULL);
5136
5137 return ret;
5138 }
5139
5140 static void hclge_pci_uninit(struct hclge_dev *hdev)
5141 {
5142 struct pci_dev *pdev = hdev->pdev;
5143
5144 pci_free_irq_vectors(pdev);
5145 pci_clear_master(pdev);
5146 pci_release_mem_regions(pdev);
5147 pci_disable_device(pdev);
5148 }
5149
5150 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
5151 {
5152 struct pci_dev *pdev = ae_dev->pdev;
5153 struct hclge_dev *hdev;
5154 int ret;
5155
5156 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
5157 if (!hdev) {
5158 ret = -ENOMEM;
5159 goto err_hclge_dev;
5160 }
5161
5162 hdev->pdev = pdev;
5163 hdev->ae_dev = ae_dev;
5164 hdev->reset_type = HNAE3_NONE_RESET;
5165 hdev->reset_request = 0;
5166 hdev->reset_pending = 0;
5167 ae_dev->priv = hdev;
5168
5169 ret = hclge_pci_init(hdev);
5170 if (ret) {
5171 dev_err(&pdev->dev, "PCI init failed\n");
5172 goto err_pci_init;
5173 }
5174
5175 /* Firmware command queue initialize */
5176 ret = hclge_cmd_queue_init(hdev);
5177 if (ret) {
5178 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
5179 return ret;
5180 }
5181
5182 /* Firmware command initialize */
5183 ret = hclge_cmd_init(hdev);
5184 if (ret)
5185 goto err_cmd_init;
5186
5187 ret = hclge_get_cap(hdev);
5188 if (ret) {
5189 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5190 ret);
5191 return ret;
5192 }
5193
5194 ret = hclge_configure(hdev);
5195 if (ret) {
5196 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5197 return ret;
5198 }
5199
5200 ret = hclge_init_msi(hdev);
5201 if (ret) {
5202 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
5203 return ret;
5204 }
5205
5206 ret = hclge_misc_irq_init(hdev);
5207 if (ret) {
5208 dev_err(&pdev->dev,
5209 "Misc IRQ(vector0) init error, ret = %d.\n",
5210 ret);
5211 return ret;
5212 }
5213
5214 ret = hclge_alloc_tqps(hdev);
5215 if (ret) {
5216 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
5217 return ret;
5218 }
5219
5220 ret = hclge_alloc_vport(hdev);
5221 if (ret) {
5222 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
5223 return ret;
5224 }
5225
5226 ret = hclge_map_tqp(hdev);
5227 if (ret) {
5228 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5229 return ret;
5230 }
5231
5232 ret = hclge_mac_mdio_config(hdev);
5233 if (ret) {
5234 dev_warn(&hdev->pdev->dev,
5235 "mdio config fail ret=%d\n", ret);
5236 return ret;
5237 }
5238
5239 ret = hclge_mac_init(hdev);
5240 if (ret) {
5241 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5242 return ret;
5243 }
5244 ret = hclge_buffer_alloc(hdev);
5245 if (ret) {
5246 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
5247 return ret;
5248 }
5249
5250 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5251 if (ret) {
5252 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5253 return ret;
5254 }
5255
5256 ret = hclge_init_vlan_config(hdev);
5257 if (ret) {
5258 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5259 return ret;
5260 }
5261
5262 ret = hclge_tm_schd_init(hdev);
5263 if (ret) {
5264 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
5265 return ret;
5266 }
5267
5268 ret = hclge_rss_init_hw(hdev);
5269 if (ret) {
5270 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5271 return ret;
5272 }
5273
5274 hclge_dcb_ops_set(hdev);
5275
5276 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
5277 INIT_WORK(&hdev->service_task, hclge_service_task);
5278 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
5279 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
5280
5281 /* Enable MISC vector(vector0) */
5282 hclge_enable_vector(&hdev->misc_vector, true);
5283
5284 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
5285 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5286 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
5287 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
5288 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
5289 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
5290
5291 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
5292 return 0;
5293
5294 err_cmd_init:
5295 pci_release_regions(pdev);
5296 err_pci_init:
5297 pci_set_drvdata(pdev, NULL);
5298 err_hclge_dev:
5299 return ret;
5300 }
5301
5302 static void hclge_stats_clear(struct hclge_dev *hdev)
5303 {
5304 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
5305 }
5306
5307 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
5308 {
5309 struct hclge_dev *hdev = ae_dev->priv;
5310 struct pci_dev *pdev = ae_dev->pdev;
5311 int ret;
5312
5313 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5314
5315 hclge_stats_clear(hdev);
5316
5317 ret = hclge_cmd_init(hdev);
5318 if (ret) {
5319 dev_err(&pdev->dev, "Cmd queue init failed\n");
5320 return ret;
5321 }
5322
5323 ret = hclge_get_cap(hdev);
5324 if (ret) {
5325 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5326 ret);
5327 return ret;
5328 }
5329
5330 ret = hclge_configure(hdev);
5331 if (ret) {
5332 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5333 return ret;
5334 }
5335
5336 ret = hclge_map_tqp(hdev);
5337 if (ret) {
5338 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5339 return ret;
5340 }
5341
5342 ret = hclge_mac_init(hdev);
5343 if (ret) {
5344 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5345 return ret;
5346 }
5347
5348 ret = hclge_buffer_alloc(hdev);
5349 if (ret) {
5350 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
5351 return ret;
5352 }
5353
5354 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5355 if (ret) {
5356 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5357 return ret;
5358 }
5359
5360 ret = hclge_init_vlan_config(hdev);
5361 if (ret) {
5362 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5363 return ret;
5364 }
5365
5366 ret = hclge_tm_schd_init(hdev);
5367 if (ret) {
5368 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
5369 return ret;
5370 }
5371
5372 ret = hclge_rss_init_hw(hdev);
5373 if (ret) {
5374 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5375 return ret;
5376 }
5377
5378 /* Enable MISC vector(vector0) */
5379 hclge_enable_vector(&hdev->misc_vector, true);
5380
5381 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
5382 HCLGE_DRIVER_NAME);
5383
5384 return 0;
5385 }
5386
5387 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
5388 {
5389 struct hclge_dev *hdev = ae_dev->priv;
5390 struct hclge_mac *mac = &hdev->hw.mac;
5391
5392 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5393
5394 if (IS_ENABLED(CONFIG_PCI_IOV))
5395 hclge_disable_sriov(hdev);
5396
5397 if (hdev->service_timer.function)
5398 del_timer_sync(&hdev->service_timer);
5399 if (hdev->service_task.func)
5400 cancel_work_sync(&hdev->service_task);
5401 if (hdev->rst_service_task.func)
5402 cancel_work_sync(&hdev->rst_service_task);
5403 if (hdev->mbx_service_task.func)
5404 cancel_work_sync(&hdev->mbx_service_task);
5405
5406 if (mac->phydev)
5407 mdiobus_unregister(mac->mdio_bus);
5408
5409 /* Disable MISC vector(vector0) */
5410 hclge_enable_vector(&hdev->misc_vector, false);
5411 hclge_destroy_cmd_queue(&hdev->hw);
5412 hclge_misc_irq_uninit(hdev);
5413 hclge_pci_uninit(hdev);
5414 ae_dev->priv = NULL;
5415 }
5416
5417 static u32 hclge_get_max_channels(struct hnae3_handle *handle)
5418 {
5419 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5420 struct hclge_vport *vport = hclge_get_vport(handle);
5421 struct hclge_dev *hdev = vport->back;
5422
5423 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
5424 }
5425
5426 static void hclge_get_channels(struct hnae3_handle *handle,
5427 struct ethtool_channels *ch)
5428 {
5429 struct hclge_vport *vport = hclge_get_vport(handle);
5430
5431 ch->max_combined = hclge_get_max_channels(handle);
5432 ch->other_count = 1;
5433 ch->max_other = 1;
5434 ch->combined_count = vport->alloc_tqps;
5435 }
5436
5437 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
5438 u16 *free_tqps, u16 *max_rss_size)
5439 {
5440 struct hclge_vport *vport = hclge_get_vport(handle);
5441 struct hclge_dev *hdev = vport->back;
5442 u16 temp_tqps = 0;
5443 int i;
5444
5445 for (i = 0; i < hdev->num_tqps; i++) {
5446 if (!hdev->htqp[i].alloced)
5447 temp_tqps++;
5448 }
5449 *free_tqps = temp_tqps;
5450 *max_rss_size = hdev->rss_size_max;
5451 }
5452
5453 static void hclge_release_tqp(struct hclge_vport *vport)
5454 {
5455 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5456 struct hclge_dev *hdev = vport->back;
5457 int i;
5458
5459 for (i = 0; i < kinfo->num_tqps; i++) {
5460 struct hclge_tqp *tqp =
5461 container_of(kinfo->tqp[i], struct hclge_tqp, q);
5462
5463 tqp->q.handle = NULL;
5464 tqp->q.tqp_index = 0;
5465 tqp->alloced = false;
5466 }
5467
5468 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
5469 kinfo->tqp = NULL;
5470 }
5471
5472 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
5473 {
5474 struct hclge_vport *vport = hclge_get_vport(handle);
5475 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5476 struct hclge_dev *hdev = vport->back;
5477 int cur_rss_size = kinfo->rss_size;
5478 int cur_tqps = kinfo->num_tqps;
5479 u16 tc_offset[HCLGE_MAX_TC_NUM];
5480 u16 tc_valid[HCLGE_MAX_TC_NUM];
5481 u16 tc_size[HCLGE_MAX_TC_NUM];
5482 u16 roundup_size;
5483 u32 *rss_indir;
5484 int ret, i;
5485
5486 hclge_release_tqp(vport);
5487
5488 ret = hclge_knic_setup(vport, new_tqps_num);
5489 if (ret) {
5490 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
5491 return ret;
5492 }
5493
5494 ret = hclge_map_tqp_to_vport(hdev, vport);
5495 if (ret) {
5496 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
5497 return ret;
5498 }
5499
5500 ret = hclge_tm_schd_init(hdev);
5501 if (ret) {
5502 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
5503 return ret;
5504 }
5505
5506 roundup_size = roundup_pow_of_two(kinfo->rss_size);
5507 roundup_size = ilog2(roundup_size);
5508 /* Set the RSS TC mode according to the new RSS size */
5509 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
5510 tc_valid[i] = 0;
5511
5512 if (!(hdev->hw_tc_map & BIT(i)))
5513 continue;
5514
5515 tc_valid[i] = 1;
5516 tc_size[i] = roundup_size;
5517 tc_offset[i] = kinfo->rss_size * i;
5518 }
5519 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
5520 if (ret)
5521 return ret;
5522
5523 /* Reinitializes the rss indirect table according to the new RSS size */
5524 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
5525 if (!rss_indir)
5526 return -ENOMEM;
5527
5528 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
5529 rss_indir[i] = i % kinfo->rss_size;
5530
5531 ret = hclge_set_rss(handle, rss_indir, NULL, 0);
5532 if (ret)
5533 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
5534 ret);
5535
5536 kfree(rss_indir);
5537
5538 if (!ret)
5539 dev_info(&hdev->pdev->dev,
5540 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5541 cur_rss_size, kinfo->rss_size,
5542 cur_tqps, kinfo->rss_size * kinfo->num_tc);
5543
5544 return ret;
5545 }
5546
5547 static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
5548 u32 *regs_num_64_bit)
5549 {
5550 struct hclge_desc desc;
5551 u32 total_num;
5552 int ret;
5553
5554 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
5555 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5556 if (ret) {
5557 dev_err(&hdev->pdev->dev,
5558 "Query register number cmd failed, ret = %d.\n", ret);
5559 return ret;
5560 }
5561
5562 *regs_num_32_bit = le32_to_cpu(desc.data[0]);
5563 *regs_num_64_bit = le32_to_cpu(desc.data[1]);
5564
5565 total_num = *regs_num_32_bit + *regs_num_64_bit;
5566 if (!total_num)
5567 return -EINVAL;
5568
5569 return 0;
5570 }
5571
5572 static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
5573 void *data)
5574 {
5575 #define HCLGE_32_BIT_REG_RTN_DATANUM 8
5576
5577 struct hclge_desc *desc;
5578 u32 *reg_val = data;
5579 __le32 *desc_data;
5580 int cmd_num;
5581 int i, k, n;
5582 int ret;
5583
5584 if (regs_num == 0)
5585 return 0;
5586
5587 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
5588 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
5589 if (!desc)
5590 return -ENOMEM;
5591
5592 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
5593 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
5594 if (ret) {
5595 dev_err(&hdev->pdev->dev,
5596 "Query 32 bit register cmd failed, ret = %d.\n", ret);
5597 kfree(desc);
5598 return ret;
5599 }
5600
5601 for (i = 0; i < cmd_num; i++) {
5602 if (i == 0) {
5603 desc_data = (__le32 *)(&desc[i].data[0]);
5604 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
5605 } else {
5606 desc_data = (__le32 *)(&desc[i]);
5607 n = HCLGE_32_BIT_REG_RTN_DATANUM;
5608 }
5609 for (k = 0; k < n; k++) {
5610 *reg_val++ = le32_to_cpu(*desc_data++);
5611
5612 regs_num--;
5613 if (!regs_num)
5614 break;
5615 }
5616 }
5617
5618 kfree(desc);
5619 return 0;
5620 }
5621
5622 static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
5623 void *data)
5624 {
5625 #define HCLGE_64_BIT_REG_RTN_DATANUM 4
5626
5627 struct hclge_desc *desc;
5628 u64 *reg_val = data;
5629 __le64 *desc_data;
5630 int cmd_num;
5631 int i, k, n;
5632 int ret;
5633
5634 if (regs_num == 0)
5635 return 0;
5636
5637 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
5638 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
5639 if (!desc)
5640 return -ENOMEM;
5641
5642 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
5643 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
5644 if (ret) {
5645 dev_err(&hdev->pdev->dev,
5646 "Query 64 bit register cmd failed, ret = %d.\n", ret);
5647 kfree(desc);
5648 return ret;
5649 }
5650
5651 for (i = 0; i < cmd_num; i++) {
5652 if (i == 0) {
5653 desc_data = (__le64 *)(&desc[i].data[0]);
5654 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
5655 } else {
5656 desc_data = (__le64 *)(&desc[i]);
5657 n = HCLGE_64_BIT_REG_RTN_DATANUM;
5658 }
5659 for (k = 0; k < n; k++) {
5660 *reg_val++ = le64_to_cpu(*desc_data++);
5661
5662 regs_num--;
5663 if (!regs_num)
5664 break;
5665 }
5666 }
5667
5668 kfree(desc);
5669 return 0;
5670 }
5671
5672 static int hclge_get_regs_len(struct hnae3_handle *handle)
5673 {
5674 struct hclge_vport *vport = hclge_get_vport(handle);
5675 struct hclge_dev *hdev = vport->back;
5676 u32 regs_num_32_bit, regs_num_64_bit;
5677 int ret;
5678
5679 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
5680 if (ret) {
5681 dev_err(&hdev->pdev->dev,
5682 "Get register number failed, ret = %d.\n", ret);
5683 return -EOPNOTSUPP;
5684 }
5685
5686 return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
5687 }
5688
5689 static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
5690 void *data)
5691 {
5692 struct hclge_vport *vport = hclge_get_vport(handle);
5693 struct hclge_dev *hdev = vport->back;
5694 u32 regs_num_32_bit, regs_num_64_bit;
5695 int ret;
5696
5697 *version = hdev->fw_version;
5698
5699 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
5700 if (ret) {
5701 dev_err(&hdev->pdev->dev,
5702 "Get register number failed, ret = %d.\n", ret);
5703 return;
5704 }
5705
5706 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
5707 if (ret) {
5708 dev_err(&hdev->pdev->dev,
5709 "Get 32 bit register failed, ret = %d.\n", ret);
5710 return;
5711 }
5712
5713 data = (u32 *)data + regs_num_32_bit;
5714 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
5715 data);
5716 if (ret)
5717 dev_err(&hdev->pdev->dev,
5718 "Get 64 bit register failed, ret = %d.\n", ret);
5719 }
5720
5721 static const struct hnae3_ae_ops hclge_ops = {
5722 .init_ae_dev = hclge_init_ae_dev,
5723 .uninit_ae_dev = hclge_uninit_ae_dev,
5724 .init_client_instance = hclge_init_client_instance,
5725 .uninit_client_instance = hclge_uninit_client_instance,
5726 .map_ring_to_vector = hclge_map_ring_to_vector,
5727 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
5728 .get_vector = hclge_get_vector,
5729 .set_promisc_mode = hclge_set_promisc_mode,
5730 .set_loopback = hclge_set_loopback,
5731 .start = hclge_ae_start,
5732 .stop = hclge_ae_stop,
5733 .get_status = hclge_get_status,
5734 .get_ksettings_an_result = hclge_get_ksettings_an_result,
5735 .update_speed_duplex_h = hclge_update_speed_duplex_h,
5736 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
5737 .get_media_type = hclge_get_media_type,
5738 .get_rss_key_size = hclge_get_rss_key_size,
5739 .get_rss_indir_size = hclge_get_rss_indir_size,
5740 .get_rss = hclge_get_rss,
5741 .set_rss = hclge_set_rss,
5742 .set_rss_tuple = hclge_set_rss_tuple,
5743 .get_rss_tuple = hclge_get_rss_tuple,
5744 .get_tc_size = hclge_get_tc_size,
5745 .get_mac_addr = hclge_get_mac_addr,
5746 .set_mac_addr = hclge_set_mac_addr,
5747 .add_uc_addr = hclge_add_uc_addr,
5748 .rm_uc_addr = hclge_rm_uc_addr,
5749 .add_mc_addr = hclge_add_mc_addr,
5750 .rm_mc_addr = hclge_rm_mc_addr,
5751 .set_autoneg = hclge_set_autoneg,
5752 .get_autoneg = hclge_get_autoneg,
5753 .get_pauseparam = hclge_get_pauseparam,
5754 .set_pauseparam = hclge_set_pauseparam,
5755 .set_mtu = hclge_set_mtu,
5756 .reset_queue = hclge_reset_tqp,
5757 .get_stats = hclge_get_stats,
5758 .update_stats = hclge_update_stats,
5759 .get_strings = hclge_get_strings,
5760 .get_sset_count = hclge_get_sset_count,
5761 .get_fw_version = hclge_get_fw_version,
5762 .get_mdix_mode = hclge_get_mdix_mode,
5763 .enable_vlan_filter = hclge_enable_vlan_filter,
5764 .set_vlan_filter = hclge_set_port_vlan_filter,
5765 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
5766 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
5767 .reset_event = hclge_reset_event,
5768 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
5769 .set_channels = hclge_set_channels,
5770 .get_channels = hclge_get_channels,
5771 .get_flowctrl_adv = hclge_get_flowctrl_adv,
5772 .get_regs_len = hclge_get_regs_len,
5773 .get_regs = hclge_get_regs,
5774 };
5775
5776 static struct hnae3_ae_algo ae_algo = {
5777 .ops = &hclge_ops,
5778 .name = HCLGE_NAME,
5779 .pdev_id_table = ae_algo_pci_tbl,
5780 };
5781
5782 static int hclge_init(void)
5783 {
5784 pr_info("%s is initializing\n", HCLGE_NAME);
5785
5786 return hnae3_register_ae_algo(&ae_algo);
5787 }
5788
5789 static void hclge_exit(void)
5790 {
5791 hnae3_unregister_ae_algo(&ae_algo);
5792 }
5793 module_init(hclge_init);
5794 module_exit(hclge_exit);
5795
5796 MODULE_LICENSE("GPL");
5797 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
5798 MODULE_DESCRIPTION("HCLGE Driver");
5799 MODULE_VERSION(HCLGE_MOD_VERSION);
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