2 * Copyright (c) 2016-2017 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/acpi.h>
11 #include <linux/device.h>
12 #include <linux/etherdevice.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
20 #include <linux/if_vlan.h>
21 #include <net/rtnetlink.h>
22 #include "hclge_cmd.h"
23 #include "hclge_dcb.h"
24 #include "hclge_main.h"
25 #include "hclge_mbx.h"
26 #include "hclge_mdio.h"
30 #define HCLGE_NAME "hclge"
31 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
32 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
33 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
34 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
36 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
37 enum hclge_mta_dmac_sel_type mta_mac_sel
,
39 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
);
40 static int hclge_init_vlan_config(struct hclge_dev
*hdev
);
41 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
);
42 static int hclge_update_led_status(struct hclge_dev
*hdev
);
44 static struct hnae3_ae_algo ae_algo
;
46 static const struct pci_device_id ae_algo_pci_tbl
[] = {
47 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_GE
), 0},
48 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE
), 0},
49 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA
), 0},
50 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA_MACSEC
), 0},
51 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA
), 0},
52 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA_MACSEC
), 0},
53 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_100G_RDMA_MACSEC
), 0},
54 /* required last entry */
58 MODULE_DEVICE_TABLE(pci
, ae_algo_pci_tbl
);
60 static const char hns3_nic_test_strs
[][ETH_GSTRING_LEN
] = {
62 "Serdes Loopback test",
66 static const struct hclge_comm_stats_str g_all_64bit_stats_string
[] = {
67 {"igu_rx_oversize_pkt",
68 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt
)},
69 {"igu_rx_undersize_pkt",
70 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt
)},
71 {"igu_rx_out_all_pkt",
72 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt
)},
74 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt
)},
76 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt
)},
78 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt
)},
79 {"egu_tx_out_all_pkt",
80 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt
)},
82 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt
)},
84 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt
)},
86 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt
)},
87 {"ssu_ppp_mac_key_num",
88 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num
)},
89 {"ssu_ppp_host_key_num",
90 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num
)},
91 {"ppp_ssu_mac_rlt_num",
92 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num
)},
93 {"ppp_ssu_host_rlt_num",
94 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num
)},
96 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num
)},
98 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num
)},
100 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num
)},
102 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num
)}
105 static const struct hclge_comm_stats_str g_all_32bit_stats_string
[] = {
107 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt
)},
108 {"igu_rx_no_eof_pkt",
109 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt
)},
110 {"igu_rx_no_sof_pkt",
111 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt
)},
113 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt
)},
114 {"ssu_full_drop_num",
115 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num
)},
116 {"ssu_part_drop_num",
117 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num
)},
119 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num
)},
121 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num
)},
123 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num
)},
125 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt
)},
127 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt
)},
129 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt
)},
130 {"qcn_fb_invaild_cnt",
131 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt
)},
132 {"rx_packet_tc0_in_cnt",
133 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt
)},
134 {"rx_packet_tc1_in_cnt",
135 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt
)},
136 {"rx_packet_tc2_in_cnt",
137 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt
)},
138 {"rx_packet_tc3_in_cnt",
139 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt
)},
140 {"rx_packet_tc4_in_cnt",
141 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt
)},
142 {"rx_packet_tc5_in_cnt",
143 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt
)},
144 {"rx_packet_tc6_in_cnt",
145 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt
)},
146 {"rx_packet_tc7_in_cnt",
147 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt
)},
148 {"rx_packet_tc0_out_cnt",
149 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt
)},
150 {"rx_packet_tc1_out_cnt",
151 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt
)},
152 {"rx_packet_tc2_out_cnt",
153 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt
)},
154 {"rx_packet_tc3_out_cnt",
155 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt
)},
156 {"rx_packet_tc4_out_cnt",
157 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt
)},
158 {"rx_packet_tc5_out_cnt",
159 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt
)},
160 {"rx_packet_tc6_out_cnt",
161 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt
)},
162 {"rx_packet_tc7_out_cnt",
163 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt
)},
164 {"tx_packet_tc0_in_cnt",
165 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt
)},
166 {"tx_packet_tc1_in_cnt",
167 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt
)},
168 {"tx_packet_tc2_in_cnt",
169 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt
)},
170 {"tx_packet_tc3_in_cnt",
171 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt
)},
172 {"tx_packet_tc4_in_cnt",
173 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt
)},
174 {"tx_packet_tc5_in_cnt",
175 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt
)},
176 {"tx_packet_tc6_in_cnt",
177 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt
)},
178 {"tx_packet_tc7_in_cnt",
179 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt
)},
180 {"tx_packet_tc0_out_cnt",
181 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt
)},
182 {"tx_packet_tc1_out_cnt",
183 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt
)},
184 {"tx_packet_tc2_out_cnt",
185 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt
)},
186 {"tx_packet_tc3_out_cnt",
187 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt
)},
188 {"tx_packet_tc4_out_cnt",
189 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt
)},
190 {"tx_packet_tc5_out_cnt",
191 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt
)},
192 {"tx_packet_tc6_out_cnt",
193 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt
)},
194 {"tx_packet_tc7_out_cnt",
195 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt
)},
196 {"pkt_curr_buf_tc0_cnt",
197 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt
)},
198 {"pkt_curr_buf_tc1_cnt",
199 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt
)},
200 {"pkt_curr_buf_tc2_cnt",
201 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt
)},
202 {"pkt_curr_buf_tc3_cnt",
203 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt
)},
204 {"pkt_curr_buf_tc4_cnt",
205 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt
)},
206 {"pkt_curr_buf_tc5_cnt",
207 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt
)},
208 {"pkt_curr_buf_tc6_cnt",
209 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt
)},
210 {"pkt_curr_buf_tc7_cnt",
211 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt
)},
213 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num
)},
214 {"lo_pri_unicast_rlt_drop_num",
215 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num
)},
216 {"hi_pri_multicast_rlt_drop_num",
217 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num
)},
218 {"lo_pri_multicast_rlt_drop_num",
219 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num
)},
220 {"rx_oq_drop_pkt_cnt",
221 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt
)},
222 {"tx_oq_drop_pkt_cnt",
223 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt
)},
224 {"nic_l2_err_drop_pkt_cnt",
225 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt
)},
226 {"roc_l2_err_drop_pkt_cnt",
227 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt
)}
230 static const struct hclge_comm_stats_str g_mac_stats_string
[] = {
231 {"mac_tx_mac_pause_num",
232 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num
)},
233 {"mac_rx_mac_pause_num",
234 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num
)},
235 {"mac_tx_pfc_pri0_pkt_num",
236 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num
)},
237 {"mac_tx_pfc_pri1_pkt_num",
238 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num
)},
239 {"mac_tx_pfc_pri2_pkt_num",
240 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num
)},
241 {"mac_tx_pfc_pri3_pkt_num",
242 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num
)},
243 {"mac_tx_pfc_pri4_pkt_num",
244 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num
)},
245 {"mac_tx_pfc_pri5_pkt_num",
246 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num
)},
247 {"mac_tx_pfc_pri6_pkt_num",
248 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num
)},
249 {"mac_tx_pfc_pri7_pkt_num",
250 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num
)},
251 {"mac_rx_pfc_pri0_pkt_num",
252 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num
)},
253 {"mac_rx_pfc_pri1_pkt_num",
254 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num
)},
255 {"mac_rx_pfc_pri2_pkt_num",
256 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num
)},
257 {"mac_rx_pfc_pri3_pkt_num",
258 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num
)},
259 {"mac_rx_pfc_pri4_pkt_num",
260 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num
)},
261 {"mac_rx_pfc_pri5_pkt_num",
262 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num
)},
263 {"mac_rx_pfc_pri6_pkt_num",
264 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num
)},
265 {"mac_rx_pfc_pri7_pkt_num",
266 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num
)},
267 {"mac_tx_total_pkt_num",
268 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num
)},
269 {"mac_tx_total_oct_num",
270 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num
)},
271 {"mac_tx_good_pkt_num",
272 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num
)},
273 {"mac_tx_bad_pkt_num",
274 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num
)},
275 {"mac_tx_good_oct_num",
276 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num
)},
277 {"mac_tx_bad_oct_num",
278 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num
)},
279 {"mac_tx_uni_pkt_num",
280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num
)},
281 {"mac_tx_multi_pkt_num",
282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num
)},
283 {"mac_tx_broad_pkt_num",
284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num
)},
285 {"mac_tx_undersize_pkt_num",
286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num
)},
287 {"mac_tx_oversize_pkt_num",
288 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num
)},
289 {"mac_tx_64_oct_pkt_num",
290 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num
)},
291 {"mac_tx_65_127_oct_pkt_num",
292 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num
)},
293 {"mac_tx_128_255_oct_pkt_num",
294 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num
)},
295 {"mac_tx_256_511_oct_pkt_num",
296 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num
)},
297 {"mac_tx_512_1023_oct_pkt_num",
298 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num
)},
299 {"mac_tx_1024_1518_oct_pkt_num",
300 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num
)},
301 {"mac_tx_1519_2047_oct_pkt_num",
302 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num
)},
303 {"mac_tx_2048_4095_oct_pkt_num",
304 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num
)},
305 {"mac_tx_4096_8191_oct_pkt_num",
306 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num
)},
307 {"mac_tx_8192_12287_oct_pkt_num",
308 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_12287_oct_pkt_num
)},
309 {"mac_tx_8192_9216_oct_pkt_num",
310 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num
)},
311 {"mac_tx_9217_12287_oct_pkt_num",
312 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num
)},
313 {"mac_tx_12288_16383_oct_pkt_num",
314 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num
)},
315 {"mac_tx_1519_max_good_pkt_num",
316 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num
)},
317 {"mac_tx_1519_max_bad_pkt_num",
318 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num
)},
319 {"mac_rx_total_pkt_num",
320 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num
)},
321 {"mac_rx_total_oct_num",
322 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num
)},
323 {"mac_rx_good_pkt_num",
324 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num
)},
325 {"mac_rx_bad_pkt_num",
326 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num
)},
327 {"mac_rx_good_oct_num",
328 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num
)},
329 {"mac_rx_bad_oct_num",
330 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num
)},
331 {"mac_rx_uni_pkt_num",
332 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num
)},
333 {"mac_rx_multi_pkt_num",
334 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num
)},
335 {"mac_rx_broad_pkt_num",
336 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num
)},
337 {"mac_rx_undersize_pkt_num",
338 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num
)},
339 {"mac_rx_oversize_pkt_num",
340 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num
)},
341 {"mac_rx_64_oct_pkt_num",
342 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num
)},
343 {"mac_rx_65_127_oct_pkt_num",
344 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num
)},
345 {"mac_rx_128_255_oct_pkt_num",
346 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num
)},
347 {"mac_rx_256_511_oct_pkt_num",
348 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num
)},
349 {"mac_rx_512_1023_oct_pkt_num",
350 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num
)},
351 {"mac_rx_1024_1518_oct_pkt_num",
352 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num
)},
353 {"mac_rx_1519_2047_oct_pkt_num",
354 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num
)},
355 {"mac_rx_2048_4095_oct_pkt_num",
356 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num
)},
357 {"mac_rx_4096_8191_oct_pkt_num",
358 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num
)},
359 {"mac_rx_8192_12287_oct_pkt_num",
360 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_12287_oct_pkt_num
)},
361 {"mac_rx_8192_9216_oct_pkt_num",
362 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num
)},
363 {"mac_rx_9217_12287_oct_pkt_num",
364 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num
)},
365 {"mac_rx_12288_16383_oct_pkt_num",
366 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num
)},
367 {"mac_rx_1519_max_good_pkt_num",
368 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num
)},
369 {"mac_rx_1519_max_bad_pkt_num",
370 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num
)},
372 {"mac_tx_fragment_pkt_num",
373 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num
)},
374 {"mac_tx_undermin_pkt_num",
375 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num
)},
376 {"mac_tx_jabber_pkt_num",
377 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num
)},
378 {"mac_tx_err_all_pkt_num",
379 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num
)},
380 {"mac_tx_from_app_good_pkt_num",
381 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num
)},
382 {"mac_tx_from_app_bad_pkt_num",
383 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num
)},
384 {"mac_rx_fragment_pkt_num",
385 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num
)},
386 {"mac_rx_undermin_pkt_num",
387 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num
)},
388 {"mac_rx_jabber_pkt_num",
389 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num
)},
390 {"mac_rx_fcs_err_pkt_num",
391 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num
)},
392 {"mac_rx_send_app_good_pkt_num",
393 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num
)},
394 {"mac_rx_send_app_bad_pkt_num",
395 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num
)}
398 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table
[] = {
400 .flags
= HCLGE_MAC_MGR_MASK_VLAN_B
,
401 .ethter_type
= cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP
),
402 .mac_addr_hi32
= cpu_to_le32(htonl(0x0180C200)),
403 .mac_addr_lo16
= cpu_to_le16(htons(0x000E)),
404 .i_port_bitmap
= 0x1,
408 static int hclge_64_bit_update_stats(struct hclge_dev
*hdev
)
410 #define HCLGE_64_BIT_CMD_NUM 5
411 #define HCLGE_64_BIT_RTN_DATANUM 4
412 u64
*data
= (u64
*)(&hdev
->hw_stats
.all_64_bit_stats
);
413 struct hclge_desc desc
[HCLGE_64_BIT_CMD_NUM
];
418 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_64_BIT
, true);
419 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_64_BIT_CMD_NUM
);
421 dev_err(&hdev
->pdev
->dev
,
422 "Get 64 bit pkt stats fail, status = %d.\n", ret
);
426 for (i
= 0; i
< HCLGE_64_BIT_CMD_NUM
; i
++) {
427 if (unlikely(i
== 0)) {
428 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
429 n
= HCLGE_64_BIT_RTN_DATANUM
- 1;
431 desc_data
= (__le64
*)(&desc
[i
]);
432 n
= HCLGE_64_BIT_RTN_DATANUM
;
434 for (k
= 0; k
< n
; k
++) {
435 *data
++ += le64_to_cpu(*desc_data
);
443 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats
*stats
)
445 stats
->pkt_curr_buf_cnt
= 0;
446 stats
->pkt_curr_buf_tc0_cnt
= 0;
447 stats
->pkt_curr_buf_tc1_cnt
= 0;
448 stats
->pkt_curr_buf_tc2_cnt
= 0;
449 stats
->pkt_curr_buf_tc3_cnt
= 0;
450 stats
->pkt_curr_buf_tc4_cnt
= 0;
451 stats
->pkt_curr_buf_tc5_cnt
= 0;
452 stats
->pkt_curr_buf_tc6_cnt
= 0;
453 stats
->pkt_curr_buf_tc7_cnt
= 0;
456 static int hclge_32_bit_update_stats(struct hclge_dev
*hdev
)
458 #define HCLGE_32_BIT_CMD_NUM 8
459 #define HCLGE_32_BIT_RTN_DATANUM 8
461 struct hclge_desc desc
[HCLGE_32_BIT_CMD_NUM
];
462 struct hclge_32_bit_stats
*all_32_bit_stats
;
468 all_32_bit_stats
= &hdev
->hw_stats
.all_32_bit_stats
;
469 data
= (u64
*)(&all_32_bit_stats
->egu_tx_1588_pkt
);
471 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_32_BIT
, true);
472 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_32_BIT_CMD_NUM
);
474 dev_err(&hdev
->pdev
->dev
,
475 "Get 32 bit pkt stats fail, status = %d.\n", ret
);
480 hclge_reset_partial_32bit_counter(all_32_bit_stats
);
481 for (i
= 0; i
< HCLGE_32_BIT_CMD_NUM
; i
++) {
482 if (unlikely(i
== 0)) {
483 __le16
*desc_data_16bit
;
485 all_32_bit_stats
->igu_rx_err_pkt
+=
486 le32_to_cpu(desc
[i
].data
[0]);
488 desc_data_16bit
= (__le16
*)&desc
[i
].data
[1];
489 all_32_bit_stats
->igu_rx_no_eof_pkt
+=
490 le16_to_cpu(*desc_data_16bit
);
493 all_32_bit_stats
->igu_rx_no_sof_pkt
+=
494 le16_to_cpu(*desc_data_16bit
);
496 desc_data
= &desc
[i
].data
[2];
497 n
= HCLGE_32_BIT_RTN_DATANUM
- 4;
499 desc_data
= (__le32
*)&desc
[i
];
500 n
= HCLGE_32_BIT_RTN_DATANUM
;
502 for (k
= 0; k
< n
; k
++) {
503 *data
++ += le32_to_cpu(*desc_data
);
511 static int hclge_mac_get_traffic_stats(struct hclge_dev
*hdev
)
513 struct hclge_mac_stats
*mac_stats
= &hdev
->hw_stats
.mac_stats
;
514 struct hclge_desc desc
;
518 /* for fiber port, need to query the total rx/tx packets statstics,
519 * used for data transferring checking.
521 if (hdev
->hw
.mac
.media_type
!= HNAE3_MEDIA_TYPE_FIBER
)
524 if (test_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
))
527 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_STATS_MAC_TRAFFIC
, true);
528 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
530 dev_err(&hdev
->pdev
->dev
,
531 "Get MAC total pkt stats fail, ret = %d\n", ret
);
536 desc_data
= (__le64
*)(&desc
.data
[0]);
537 mac_stats
->mac_tx_total_pkt_num
+= le64_to_cpu(*desc_data
++);
538 mac_stats
->mac_rx_total_pkt_num
+= le64_to_cpu(*desc_data
);
543 static int hclge_mac_update_stats(struct hclge_dev
*hdev
)
545 #define HCLGE_MAC_CMD_NUM 21
546 #define HCLGE_RTN_DATA_NUM 4
548 u64
*data
= (u64
*)(&hdev
->hw_stats
.mac_stats
);
549 struct hclge_desc desc
[HCLGE_MAC_CMD_NUM
];
554 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_MAC
, true);
555 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_MAC_CMD_NUM
);
557 dev_err(&hdev
->pdev
->dev
,
558 "Get MAC pkt stats fail, status = %d.\n", ret
);
563 for (i
= 0; i
< HCLGE_MAC_CMD_NUM
; i
++) {
564 if (unlikely(i
== 0)) {
565 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
566 n
= HCLGE_RTN_DATA_NUM
- 2;
568 desc_data
= (__le64
*)(&desc
[i
]);
569 n
= HCLGE_RTN_DATA_NUM
;
571 for (k
= 0; k
< n
; k
++) {
572 *data
++ += le64_to_cpu(*desc_data
);
580 static int hclge_tqps_update_stats(struct hnae3_handle
*handle
)
582 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
583 struct hclge_vport
*vport
= hclge_get_vport(handle
);
584 struct hclge_dev
*hdev
= vport
->back
;
585 struct hnae3_queue
*queue
;
586 struct hclge_desc desc
[1];
587 struct hclge_tqp
*tqp
;
590 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
591 queue
= handle
->kinfo
.tqp
[i
];
592 tqp
= container_of(queue
, struct hclge_tqp
, q
);
593 /* command : HCLGE_OPC_QUERY_IGU_STAT */
594 hclge_cmd_setup_basic_desc(&desc
[0],
595 HCLGE_OPC_QUERY_RX_STATUS
,
598 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
599 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
601 dev_err(&hdev
->pdev
->dev
,
602 "Query tqp stat fail, status = %d,queue = %d\n",
606 tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
+=
607 le32_to_cpu(desc
[0].data
[1]);
610 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
611 queue
= handle
->kinfo
.tqp
[i
];
612 tqp
= container_of(queue
, struct hclge_tqp
, q
);
613 /* command : HCLGE_OPC_QUERY_IGU_STAT */
614 hclge_cmd_setup_basic_desc(&desc
[0],
615 HCLGE_OPC_QUERY_TX_STATUS
,
618 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
619 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
621 dev_err(&hdev
->pdev
->dev
,
622 "Query tqp stat fail, status = %d,queue = %d\n",
626 tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
+=
627 le32_to_cpu(desc
[0].data
[1]);
633 static u64
*hclge_tqps_get_stats(struct hnae3_handle
*handle
, u64
*data
)
635 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
636 struct hclge_tqp
*tqp
;
640 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
641 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
642 *buff
++ = tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
;
645 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
646 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
647 *buff
++ = tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
;
653 static int hclge_tqps_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
655 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
657 return kinfo
->num_tqps
* (2);
660 static u8
*hclge_tqps_get_strings(struct hnae3_handle
*handle
, u8
*data
)
662 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
666 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
667 struct hclge_tqp
*tqp
= container_of(handle
->kinfo
.tqp
[i
],
668 struct hclge_tqp
, q
);
669 snprintf(buff
, ETH_GSTRING_LEN
, "txq#%d_pktnum_rcd",
671 buff
= buff
+ ETH_GSTRING_LEN
;
674 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
675 struct hclge_tqp
*tqp
= container_of(kinfo
->tqp
[i
],
676 struct hclge_tqp
, q
);
677 snprintf(buff
, ETH_GSTRING_LEN
, "rxq#%d_pktnum_rcd",
679 buff
= buff
+ ETH_GSTRING_LEN
;
685 static u64
*hclge_comm_get_stats(void *comm_stats
,
686 const struct hclge_comm_stats_str strs
[],
692 for (i
= 0; i
< size
; i
++)
693 buf
[i
] = HCLGE_STATS_READ(comm_stats
, strs
[i
].offset
);
698 static u8
*hclge_comm_get_strings(u32 stringset
,
699 const struct hclge_comm_stats_str strs
[],
702 char *buff
= (char *)data
;
705 if (stringset
!= ETH_SS_STATS
)
708 for (i
= 0; i
< size
; i
++) {
709 snprintf(buff
, ETH_GSTRING_LEN
,
711 buff
= buff
+ ETH_GSTRING_LEN
;
717 static void hclge_update_netstat(struct hclge_hw_stats
*hw_stats
,
718 struct net_device_stats
*net_stats
)
720 net_stats
->tx_dropped
= 0;
721 net_stats
->rx_dropped
= hw_stats
->all_32_bit_stats
.ssu_full_drop_num
;
722 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ppp_key_drop_num
;
723 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ssu_key_drop_num
;
725 net_stats
->rx_errors
= hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
726 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
727 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_eof_pkt
;
728 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_sof_pkt
;
729 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
731 net_stats
->multicast
= hw_stats
->mac_stats
.mac_tx_multi_pkt_num
;
732 net_stats
->multicast
+= hw_stats
->mac_stats
.mac_rx_multi_pkt_num
;
734 net_stats
->rx_crc_errors
= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
735 net_stats
->rx_length_errors
=
736 hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
737 net_stats
->rx_length_errors
+=
738 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
739 net_stats
->rx_over_errors
=
740 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
743 static void hclge_update_stats_for_all(struct hclge_dev
*hdev
)
745 struct hnae3_handle
*handle
;
748 handle
= &hdev
->vport
[0].nic
;
749 if (handle
->client
) {
750 status
= hclge_tqps_update_stats(handle
);
752 dev_err(&hdev
->pdev
->dev
,
753 "Update TQPS stats fail, status = %d.\n",
758 status
= hclge_mac_update_stats(hdev
);
760 dev_err(&hdev
->pdev
->dev
,
761 "Update MAC stats fail, status = %d.\n", status
);
763 status
= hclge_32_bit_update_stats(hdev
);
765 dev_err(&hdev
->pdev
->dev
,
766 "Update 32 bit stats fail, status = %d.\n",
769 hclge_update_netstat(&hdev
->hw_stats
, &handle
->kinfo
.netdev
->stats
);
772 static void hclge_update_stats(struct hnae3_handle
*handle
,
773 struct net_device_stats
*net_stats
)
775 struct hclge_vport
*vport
= hclge_get_vport(handle
);
776 struct hclge_dev
*hdev
= vport
->back
;
777 struct hclge_hw_stats
*hw_stats
= &hdev
->hw_stats
;
780 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
))
783 status
= hclge_mac_update_stats(hdev
);
785 dev_err(&hdev
->pdev
->dev
,
786 "Update MAC stats fail, status = %d.\n",
789 status
= hclge_32_bit_update_stats(hdev
);
791 dev_err(&hdev
->pdev
->dev
,
792 "Update 32 bit stats fail, status = %d.\n",
795 status
= hclge_64_bit_update_stats(hdev
);
797 dev_err(&hdev
->pdev
->dev
,
798 "Update 64 bit stats fail, status = %d.\n",
801 status
= hclge_tqps_update_stats(handle
);
803 dev_err(&hdev
->pdev
->dev
,
804 "Update TQPS stats fail, status = %d.\n",
807 hclge_update_netstat(hw_stats
, net_stats
);
809 clear_bit(HCLGE_STATE_STATISTICS_UPDATING
, &hdev
->state
);
812 static int hclge_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
814 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
816 struct hclge_vport
*vport
= hclge_get_vport(handle
);
817 struct hclge_dev
*hdev
= vport
->back
;
820 /* Loopback test support rules:
821 * mac: only GE mode support
822 * serdes: all mac mode will support include GE/XGE/LGE/CGE
823 * phy: only support when phy device exist on board
825 if (stringset
== ETH_SS_TEST
) {
826 /* clear loopback bit flags at first */
827 handle
->flags
= (handle
->flags
& (~HCLGE_LOOPBACK_TEST_FLAGS
));
828 if (hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_10M
||
829 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_100M
||
830 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_1G
) {
832 handle
->flags
|= HNAE3_SUPPORT_MAC_LOOPBACK
;
836 } else if (stringset
== ETH_SS_STATS
) {
837 count
= ARRAY_SIZE(g_mac_stats_string
) +
838 ARRAY_SIZE(g_all_32bit_stats_string
) +
839 ARRAY_SIZE(g_all_64bit_stats_string
) +
840 hclge_tqps_get_sset_count(handle
, stringset
);
846 static void hclge_get_strings(struct hnae3_handle
*handle
,
850 u8
*p
= (char *)data
;
853 if (stringset
== ETH_SS_STATS
) {
854 size
= ARRAY_SIZE(g_mac_stats_string
);
855 p
= hclge_comm_get_strings(stringset
,
859 size
= ARRAY_SIZE(g_all_32bit_stats_string
);
860 p
= hclge_comm_get_strings(stringset
,
861 g_all_32bit_stats_string
,
864 size
= ARRAY_SIZE(g_all_64bit_stats_string
);
865 p
= hclge_comm_get_strings(stringset
,
866 g_all_64bit_stats_string
,
869 p
= hclge_tqps_get_strings(handle
, p
);
870 } else if (stringset
== ETH_SS_TEST
) {
871 if (handle
->flags
& HNAE3_SUPPORT_MAC_LOOPBACK
) {
873 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_MAC
],
875 p
+= ETH_GSTRING_LEN
;
877 if (handle
->flags
& HNAE3_SUPPORT_SERDES_LOOPBACK
) {
879 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_SERDES
],
881 p
+= ETH_GSTRING_LEN
;
883 if (handle
->flags
& HNAE3_SUPPORT_PHY_LOOPBACK
) {
885 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_PHY
],
887 p
+= ETH_GSTRING_LEN
;
892 static void hclge_get_stats(struct hnae3_handle
*handle
, u64
*data
)
894 struct hclge_vport
*vport
= hclge_get_vport(handle
);
895 struct hclge_dev
*hdev
= vport
->back
;
898 p
= hclge_comm_get_stats(&hdev
->hw_stats
.mac_stats
,
900 ARRAY_SIZE(g_mac_stats_string
),
902 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_32_bit_stats
,
903 g_all_32bit_stats_string
,
904 ARRAY_SIZE(g_all_32bit_stats_string
),
906 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_64_bit_stats
,
907 g_all_64bit_stats_string
,
908 ARRAY_SIZE(g_all_64bit_stats_string
),
910 p
= hclge_tqps_get_stats(handle
, p
);
913 static int hclge_parse_func_status(struct hclge_dev
*hdev
,
914 struct hclge_func_status_cmd
*status
)
916 if (!(status
->pf_state
& HCLGE_PF_STATE_DONE
))
919 /* Set the pf to main pf */
920 if (status
->pf_state
& HCLGE_PF_STATE_MAIN
)
921 hdev
->flag
|= HCLGE_FLAG_MAIN
;
923 hdev
->flag
&= ~HCLGE_FLAG_MAIN
;
928 static int hclge_query_function_status(struct hclge_dev
*hdev
)
930 struct hclge_func_status_cmd
*req
;
931 struct hclge_desc desc
;
935 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_FUNC_STATUS
, true);
936 req
= (struct hclge_func_status_cmd
*)desc
.data
;
939 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
941 dev_err(&hdev
->pdev
->dev
,
942 "query function status failed %d.\n",
948 /* Check pf reset is done */
951 usleep_range(1000, 2000);
952 } while (timeout
++ < 5);
954 ret
= hclge_parse_func_status(hdev
, req
);
959 static int hclge_query_pf_resource(struct hclge_dev
*hdev
)
961 struct hclge_pf_res_cmd
*req
;
962 struct hclge_desc desc
;
965 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_PF_RSRC
, true);
966 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
968 dev_err(&hdev
->pdev
->dev
,
969 "query pf resource failed %d.\n", ret
);
973 req
= (struct hclge_pf_res_cmd
*)desc
.data
;
974 hdev
->num_tqps
= __le16_to_cpu(req
->tqp_num
);
975 hdev
->pkt_buf_size
= __le16_to_cpu(req
->buf_size
) << HCLGE_BUF_UNIT_S
;
977 if (hnae3_dev_roce_supported(hdev
)) {
979 hnae_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
980 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
982 /* PF should have NIC vectors and Roce vectors,
983 * NIC vectors are queued before Roce vectors.
985 hdev
->num_msi
= hdev
->num_roce_msi
+ HCLGE_ROCE_VECTOR_OFFSET
;
988 hnae_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
989 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
995 static int hclge_parse_speed(int speed_cmd
, int *speed
)
999 *speed
= HCLGE_MAC_SPEED_10M
;
1002 *speed
= HCLGE_MAC_SPEED_100M
;
1005 *speed
= HCLGE_MAC_SPEED_1G
;
1008 *speed
= HCLGE_MAC_SPEED_10G
;
1011 *speed
= HCLGE_MAC_SPEED_25G
;
1014 *speed
= HCLGE_MAC_SPEED_40G
;
1017 *speed
= HCLGE_MAC_SPEED_50G
;
1020 *speed
= HCLGE_MAC_SPEED_100G
;
1029 static void hclge_parse_cfg(struct hclge_cfg
*cfg
, struct hclge_desc
*desc
)
1031 struct hclge_cfg_param_cmd
*req
;
1032 u64 mac_addr_tmp_high
;
1036 req
= (struct hclge_cfg_param_cmd
*)desc
[0].data
;
1038 /* get the configuration */
1039 cfg
->vmdq_vport_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
1042 cfg
->tc_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
1043 HCLGE_CFG_TC_NUM_M
, HCLGE_CFG_TC_NUM_S
);
1044 cfg
->tqp_desc_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
1045 HCLGE_CFG_TQP_DESC_N_M
,
1046 HCLGE_CFG_TQP_DESC_N_S
);
1048 cfg
->phy_addr
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
1049 HCLGE_CFG_PHY_ADDR_M
,
1050 HCLGE_CFG_PHY_ADDR_S
);
1051 cfg
->media_type
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
1052 HCLGE_CFG_MEDIA_TP_M
,
1053 HCLGE_CFG_MEDIA_TP_S
);
1054 cfg
->rx_buf_len
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
1055 HCLGE_CFG_RX_BUF_LEN_M
,
1056 HCLGE_CFG_RX_BUF_LEN_S
);
1057 /* get mac_address */
1058 mac_addr_tmp
= __le32_to_cpu(req
->param
[2]);
1059 mac_addr_tmp_high
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
1060 HCLGE_CFG_MAC_ADDR_H_M
,
1061 HCLGE_CFG_MAC_ADDR_H_S
);
1063 mac_addr_tmp
|= (mac_addr_tmp_high
<< 31) << 1;
1065 cfg
->default_speed
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
1066 HCLGE_CFG_DEFAULT_SPEED_M
,
1067 HCLGE_CFG_DEFAULT_SPEED_S
);
1068 cfg
->rss_size_max
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
1069 HCLGE_CFG_RSS_SIZE_M
,
1070 HCLGE_CFG_RSS_SIZE_S
);
1072 for (i
= 0; i
< ETH_ALEN
; i
++)
1073 cfg
->mac_addr
[i
] = (mac_addr_tmp
>> (8 * i
)) & 0xff;
1075 req
= (struct hclge_cfg_param_cmd
*)desc
[1].data
;
1076 cfg
->numa_node_map
= __le32_to_cpu(req
->param
[0]);
1079 /* hclge_get_cfg: query the static parameter from flash
1080 * @hdev: pointer to struct hclge_dev
1081 * @hcfg: the config structure to be getted
1083 static int hclge_get_cfg(struct hclge_dev
*hdev
, struct hclge_cfg
*hcfg
)
1085 struct hclge_desc desc
[HCLGE_PF_CFG_DESC_NUM
];
1086 struct hclge_cfg_param_cmd
*req
;
1089 for (i
= 0; i
< HCLGE_PF_CFG_DESC_NUM
; i
++) {
1092 req
= (struct hclge_cfg_param_cmd
*)desc
[i
].data
;
1093 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_GET_CFG_PARAM
,
1095 hnae_set_field(offset
, HCLGE_CFG_OFFSET_M
,
1096 HCLGE_CFG_OFFSET_S
, i
* HCLGE_CFG_RD_LEN_BYTES
);
1097 /* Len should be united by 4 bytes when send to hardware */
1098 hnae_set_field(offset
, HCLGE_CFG_RD_LEN_M
, HCLGE_CFG_RD_LEN_S
,
1099 HCLGE_CFG_RD_LEN_BYTES
/ HCLGE_CFG_RD_LEN_UNIT
);
1100 req
->offset
= cpu_to_le32(offset
);
1103 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_PF_CFG_DESC_NUM
);
1105 dev_err(&hdev
->pdev
->dev
,
1106 "get config failed %d.\n", ret
);
1110 hclge_parse_cfg(hcfg
, desc
);
1114 static int hclge_get_cap(struct hclge_dev
*hdev
)
1118 ret
= hclge_query_function_status(hdev
);
1120 dev_err(&hdev
->pdev
->dev
,
1121 "query function status error %d.\n", ret
);
1125 /* get pf resource */
1126 ret
= hclge_query_pf_resource(hdev
);
1128 dev_err(&hdev
->pdev
->dev
,
1129 "query pf resource error %d.\n", ret
);
1136 static int hclge_configure(struct hclge_dev
*hdev
)
1138 struct hclge_cfg cfg
;
1141 ret
= hclge_get_cfg(hdev
, &cfg
);
1143 dev_err(&hdev
->pdev
->dev
, "get mac mode error %d.\n", ret
);
1147 hdev
->num_vmdq_vport
= cfg
.vmdq_vport_num
;
1148 hdev
->base_tqp_pid
= 0;
1149 hdev
->rss_size_max
= cfg
.rss_size_max
;
1150 hdev
->rx_buf_len
= cfg
.rx_buf_len
;
1151 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, cfg
.mac_addr
);
1152 hdev
->hw
.mac
.media_type
= cfg
.media_type
;
1153 hdev
->hw
.mac
.phy_addr
= cfg
.phy_addr
;
1154 hdev
->num_desc
= cfg
.tqp_desc_num
;
1155 hdev
->tm_info
.num_pg
= 1;
1156 hdev
->tc_max
= cfg
.tc_num
;
1157 hdev
->tm_info
.hw_pfc_map
= 0;
1159 ret
= hclge_parse_speed(cfg
.default_speed
, &hdev
->hw
.mac
.speed
);
1161 dev_err(&hdev
->pdev
->dev
, "Get wrong speed ret=%d.\n", ret
);
1165 if ((hdev
->tc_max
> HNAE3_MAX_TC
) ||
1166 (hdev
->tc_max
< 1)) {
1167 dev_warn(&hdev
->pdev
->dev
, "TC num = %d.\n",
1172 /* Dev does not support DCB */
1173 if (!hnae3_dev_dcb_supported(hdev
)) {
1177 hdev
->pfc_max
= hdev
->tc_max
;
1180 hdev
->tm_info
.num_tc
= hdev
->tc_max
;
1182 /* Currently not support uncontiuous tc */
1183 for (i
= 0; i
< hdev
->tm_info
.num_tc
; i
++)
1184 hnae_set_bit(hdev
->hw_tc_map
, i
, 1);
1186 hdev
->tx_sch_mode
= HCLGE_FLAG_TC_BASE_SCH_MODE
;
1191 static int hclge_config_tso(struct hclge_dev
*hdev
, int tso_mss_min
,
1194 struct hclge_cfg_tso_status_cmd
*req
;
1195 struct hclge_desc desc
;
1198 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TSO_GENERIC_CONFIG
, false);
1200 req
= (struct hclge_cfg_tso_status_cmd
*)desc
.data
;
1203 hnae_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1204 HCLGE_TSO_MSS_MIN_S
, tso_mss_min
);
1205 req
->tso_mss_min
= cpu_to_le16(tso_mss
);
1208 hnae_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1209 HCLGE_TSO_MSS_MIN_S
, tso_mss_max
);
1210 req
->tso_mss_max
= cpu_to_le16(tso_mss
);
1212 return hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1215 static int hclge_alloc_tqps(struct hclge_dev
*hdev
)
1217 struct hclge_tqp
*tqp
;
1220 hdev
->htqp
= devm_kcalloc(&hdev
->pdev
->dev
, hdev
->num_tqps
,
1221 sizeof(struct hclge_tqp
), GFP_KERNEL
);
1227 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
1228 tqp
->dev
= &hdev
->pdev
->dev
;
1231 tqp
->q
.ae_algo
= &ae_algo
;
1232 tqp
->q
.buf_size
= hdev
->rx_buf_len
;
1233 tqp
->q
.desc_num
= hdev
->num_desc
;
1234 tqp
->q
.io_base
= hdev
->hw
.io_base
+ HCLGE_TQP_REG_OFFSET
+
1235 i
* HCLGE_TQP_REG_SIZE
;
1243 static int hclge_map_tqps_to_func(struct hclge_dev
*hdev
, u16 func_id
,
1244 u16 tqp_pid
, u16 tqp_vid
, bool is_pf
)
1246 struct hclge_tqp_map_cmd
*req
;
1247 struct hclge_desc desc
;
1250 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SET_TQP_MAP
, false);
1252 req
= (struct hclge_tqp_map_cmd
*)desc
.data
;
1253 req
->tqp_id
= cpu_to_le16(tqp_pid
);
1254 req
->tqp_vf
= func_id
;
1255 req
->tqp_flag
= !is_pf
<< HCLGE_TQP_MAP_TYPE_B
|
1256 1 << HCLGE_TQP_MAP_EN_B
;
1257 req
->tqp_vid
= cpu_to_le16(tqp_vid
);
1259 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1261 dev_err(&hdev
->pdev
->dev
, "TQP map failed %d.\n",
1269 static int hclge_assign_tqp(struct hclge_vport
*vport
,
1270 struct hnae3_queue
**tqp
, u16 num_tqps
)
1272 struct hclge_dev
*hdev
= vport
->back
;
1275 for (i
= 0, alloced
= 0; i
< hdev
->num_tqps
&&
1276 alloced
< num_tqps
; i
++) {
1277 if (!hdev
->htqp
[i
].alloced
) {
1278 hdev
->htqp
[i
].q
.handle
= &vport
->nic
;
1279 hdev
->htqp
[i
].q
.tqp_index
= alloced
;
1280 tqp
[alloced
] = &hdev
->htqp
[i
].q
;
1281 hdev
->htqp
[i
].alloced
= true;
1285 vport
->alloc_tqps
= num_tqps
;
1290 static int hclge_knic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1292 struct hnae3_handle
*nic
= &vport
->nic
;
1293 struct hnae3_knic_private_info
*kinfo
= &nic
->kinfo
;
1294 struct hclge_dev
*hdev
= vport
->back
;
1297 kinfo
->num_desc
= hdev
->num_desc
;
1298 kinfo
->rx_buf_len
= hdev
->rx_buf_len
;
1299 kinfo
->num_tc
= min_t(u16
, num_tqps
, hdev
->tm_info
.num_tc
);
1301 = min_t(u16
, hdev
->rss_size_max
, num_tqps
/ kinfo
->num_tc
);
1302 kinfo
->num_tqps
= kinfo
->rss_size
* kinfo
->num_tc
;
1304 for (i
= 0; i
< HNAE3_MAX_TC
; i
++) {
1305 if (hdev
->hw_tc_map
& BIT(i
)) {
1306 kinfo
->tc_info
[i
].enable
= true;
1307 kinfo
->tc_info
[i
].tqp_offset
= i
* kinfo
->rss_size
;
1308 kinfo
->tc_info
[i
].tqp_count
= kinfo
->rss_size
;
1309 kinfo
->tc_info
[i
].tc
= i
;
1311 /* Set to default queue if TC is disable */
1312 kinfo
->tc_info
[i
].enable
= false;
1313 kinfo
->tc_info
[i
].tqp_offset
= 0;
1314 kinfo
->tc_info
[i
].tqp_count
= 1;
1315 kinfo
->tc_info
[i
].tc
= 0;
1319 kinfo
->tqp
= devm_kcalloc(&hdev
->pdev
->dev
, kinfo
->num_tqps
,
1320 sizeof(struct hnae3_queue
*), GFP_KERNEL
);
1324 ret
= hclge_assign_tqp(vport
, kinfo
->tqp
, kinfo
->num_tqps
);
1326 dev_err(&hdev
->pdev
->dev
, "fail to assign TQPs %d.\n", ret
);
1333 static int hclge_map_tqp_to_vport(struct hclge_dev
*hdev
,
1334 struct hclge_vport
*vport
)
1336 struct hnae3_handle
*nic
= &vport
->nic
;
1337 struct hnae3_knic_private_info
*kinfo
;
1340 kinfo
= &nic
->kinfo
;
1341 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
1342 struct hclge_tqp
*q
=
1343 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
1347 is_pf
= !(vport
->vport_id
);
1348 ret
= hclge_map_tqps_to_func(hdev
, vport
->vport_id
, q
->index
,
1357 static int hclge_map_tqp(struct hclge_dev
*hdev
)
1359 struct hclge_vport
*vport
= hdev
->vport
;
1362 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1363 for (i
= 0; i
< num_vport
; i
++) {
1366 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
1376 static void hclge_unic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1378 /* this would be initialized later */
1381 static int hclge_vport_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1383 struct hnae3_handle
*nic
= &vport
->nic
;
1384 struct hclge_dev
*hdev
= vport
->back
;
1387 nic
->pdev
= hdev
->pdev
;
1388 nic
->ae_algo
= &ae_algo
;
1389 nic
->numa_node_mask
= hdev
->numa_node_mask
;
1391 if (hdev
->ae_dev
->dev_type
== HNAE3_DEV_KNIC
) {
1392 ret
= hclge_knic_setup(vport
, num_tqps
);
1394 dev_err(&hdev
->pdev
->dev
, "knic setup failed %d\n",
1399 hclge_unic_setup(vport
, num_tqps
);
1405 static int hclge_alloc_vport(struct hclge_dev
*hdev
)
1407 struct pci_dev
*pdev
= hdev
->pdev
;
1408 struct hclge_vport
*vport
;
1414 /* We need to alloc a vport for main NIC of PF */
1415 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1417 if (hdev
->num_tqps
< num_vport
)
1418 num_vport
= hdev
->num_tqps
;
1420 /* Alloc the same number of TQPs for every vport */
1421 tqp_per_vport
= hdev
->num_tqps
/ num_vport
;
1422 tqp_main_vport
= tqp_per_vport
+ hdev
->num_tqps
% num_vport
;
1424 vport
= devm_kcalloc(&pdev
->dev
, num_vport
, sizeof(struct hclge_vport
),
1429 hdev
->vport
= vport
;
1430 hdev
->num_alloc_vport
= num_vport
;
1432 #ifdef CONFIG_PCI_IOV
1434 if (hdev
->num_req_vfs
) {
1435 dev_info(&pdev
->dev
, "active VFs(%d) found, enabling SRIOV\n",
1437 ret
= pci_enable_sriov(hdev
->pdev
, hdev
->num_req_vfs
);
1439 hdev
->num_alloc_vfs
= 0;
1440 dev_err(&pdev
->dev
, "SRIOV enable failed %d\n",
1445 hdev
->num_alloc_vfs
= hdev
->num_req_vfs
;
1448 for (i
= 0; i
< num_vport
; i
++) {
1450 vport
->vport_id
= i
;
1453 ret
= hclge_vport_setup(vport
, tqp_main_vport
);
1455 ret
= hclge_vport_setup(vport
, tqp_per_vport
);
1458 "vport setup failed for vport %d, %d\n",
1469 static int hclge_cmd_alloc_tx_buff(struct hclge_dev
*hdev
,
1470 struct hclge_pkt_buf_alloc
*buf_alloc
)
1472 /* TX buffer size is unit by 128 byte */
1473 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1474 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1475 struct hclge_tx_buff_alloc_cmd
*req
;
1476 struct hclge_desc desc
;
1480 req
= (struct hclge_tx_buff_alloc_cmd
*)desc
.data
;
1482 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TX_BUFF_ALLOC
, 0);
1483 for (i
= 0; i
< HCLGE_TC_NUM
; i
++) {
1484 u32 buf_size
= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1486 req
->tx_pkt_buff
[i
] =
1487 cpu_to_le16((buf_size
>> HCLGE_BUF_SIZE_UNIT_SHIFT
) |
1488 HCLGE_BUF_SIZE_UPDATE_EN_MSK
);
1491 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1493 dev_err(&hdev
->pdev
->dev
, "tx buffer alloc cmd failed %d.\n",
1501 static int hclge_tx_buffer_alloc(struct hclge_dev
*hdev
,
1502 struct hclge_pkt_buf_alloc
*buf_alloc
)
1504 int ret
= hclge_cmd_alloc_tx_buff(hdev
, buf_alloc
);
1507 dev_err(&hdev
->pdev
->dev
,
1508 "tx buffer alloc failed %d\n", ret
);
1515 static int hclge_get_tc_num(struct hclge_dev
*hdev
)
1519 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1520 if (hdev
->hw_tc_map
& BIT(i
))
1525 static int hclge_get_pfc_enalbe_num(struct hclge_dev
*hdev
)
1529 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1530 if (hdev
->hw_tc_map
& BIT(i
) &&
1531 hdev
->tm_info
.hw_pfc_map
& BIT(i
))
1536 /* Get the number of pfc enabled TCs, which have private buffer */
1537 static int hclge_get_pfc_priv_num(struct hclge_dev
*hdev
,
1538 struct hclge_pkt_buf_alloc
*buf_alloc
)
1540 struct hclge_priv_buf
*priv
;
1543 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1544 priv
= &buf_alloc
->priv_buf
[i
];
1545 if ((hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1553 /* Get the number of pfc disabled TCs, which have private buffer */
1554 static int hclge_get_no_pfc_priv_num(struct hclge_dev
*hdev
,
1555 struct hclge_pkt_buf_alloc
*buf_alloc
)
1557 struct hclge_priv_buf
*priv
;
1560 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1561 priv
= &buf_alloc
->priv_buf
[i
];
1562 if (hdev
->hw_tc_map
& BIT(i
) &&
1563 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1571 static u32
hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1573 struct hclge_priv_buf
*priv
;
1577 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1578 priv
= &buf_alloc
->priv_buf
[i
];
1580 rx_priv
+= priv
->buf_size
;
1585 static u32
hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1587 u32 i
, total_tx_size
= 0;
1589 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1590 total_tx_size
+= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1592 return total_tx_size
;
1595 static bool hclge_is_rx_buf_ok(struct hclge_dev
*hdev
,
1596 struct hclge_pkt_buf_alloc
*buf_alloc
,
1599 u32 shared_buf_min
, shared_buf_tc
, shared_std
;
1600 int tc_num
, pfc_enable_num
;
1605 tc_num
= hclge_get_tc_num(hdev
);
1606 pfc_enable_num
= hclge_get_pfc_enalbe_num(hdev
);
1608 if (hnae3_dev_dcb_supported(hdev
))
1609 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_DV
;
1611 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_NON_DCB_DV
;
1613 shared_buf_tc
= pfc_enable_num
* hdev
->mps
+
1614 (tc_num
- pfc_enable_num
) * hdev
->mps
/ 2 +
1616 shared_std
= max_t(u32
, shared_buf_min
, shared_buf_tc
);
1618 rx_priv
= hclge_get_rx_priv_buff_alloced(buf_alloc
);
1619 if (rx_all
<= rx_priv
+ shared_std
)
1622 shared_buf
= rx_all
- rx_priv
;
1623 buf_alloc
->s_buf
.buf_size
= shared_buf
;
1624 buf_alloc
->s_buf
.self
.high
= shared_buf
;
1625 buf_alloc
->s_buf
.self
.low
= 2 * hdev
->mps
;
1627 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1628 if ((hdev
->hw_tc_map
& BIT(i
)) &&
1629 (hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1630 buf_alloc
->s_buf
.tc_thrd
[i
].low
= hdev
->mps
;
1631 buf_alloc
->s_buf
.tc_thrd
[i
].high
= 2 * hdev
->mps
;
1633 buf_alloc
->s_buf
.tc_thrd
[i
].low
= 0;
1634 buf_alloc
->s_buf
.tc_thrd
[i
].high
= hdev
->mps
;
1641 static int hclge_tx_buffer_calc(struct hclge_dev
*hdev
,
1642 struct hclge_pkt_buf_alloc
*buf_alloc
)
1646 total_size
= hdev
->pkt_buf_size
;
1648 /* alloc tx buffer for all enabled tc */
1649 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1650 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1652 if (total_size
< HCLGE_DEFAULT_TX_BUF
)
1655 if (hdev
->hw_tc_map
& BIT(i
))
1656 priv
->tx_buf_size
= HCLGE_DEFAULT_TX_BUF
;
1658 priv
->tx_buf_size
= 0;
1660 total_size
-= priv
->tx_buf_size
;
1666 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1667 * @hdev: pointer to struct hclge_dev
1668 * @buf_alloc: pointer to buffer calculation data
1669 * @return: 0: calculate sucessful, negative: fail
1671 static int hclge_rx_buffer_calc(struct hclge_dev
*hdev
,
1672 struct hclge_pkt_buf_alloc
*buf_alloc
)
1674 u32 rx_all
= hdev
->pkt_buf_size
;
1675 int no_pfc_priv_num
, pfc_priv_num
;
1676 struct hclge_priv_buf
*priv
;
1679 rx_all
-= hclge_get_tx_buff_alloced(buf_alloc
);
1681 /* When DCB is not supported, rx private
1682 * buffer is not allocated.
1684 if (!hnae3_dev_dcb_supported(hdev
)) {
1685 if (!hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1691 /* step 1, try to alloc private buffer for all enabled tc */
1692 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1693 priv
= &buf_alloc
->priv_buf
[i
];
1694 if (hdev
->hw_tc_map
& BIT(i
)) {
1696 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1697 priv
->wl
.low
= hdev
->mps
;
1698 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1699 priv
->buf_size
= priv
->wl
.high
+
1703 priv
->wl
.high
= 2 * hdev
->mps
;
1704 priv
->buf_size
= priv
->wl
.high
;
1714 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1717 /* step 2, try to decrease the buffer size of
1718 * no pfc TC's private buffer
1720 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1721 priv
= &buf_alloc
->priv_buf
[i
];
1728 if (!(hdev
->hw_tc_map
& BIT(i
)))
1733 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1735 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1736 priv
->buf_size
= priv
->wl
.high
+ HCLGE_DEFAULT_DV
;
1739 priv
->wl
.high
= hdev
->mps
;
1740 priv
->buf_size
= priv
->wl
.high
;
1744 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1747 /* step 3, try to reduce the number of pfc disabled TCs,
1748 * which have private buffer
1750 /* get the total no pfc enable TC number, which have private buffer */
1751 no_pfc_priv_num
= hclge_get_no_pfc_priv_num(hdev
, buf_alloc
);
1753 /* let the last to be cleared first */
1754 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1755 priv
= &buf_alloc
->priv_buf
[i
];
1757 if (hdev
->hw_tc_map
& BIT(i
) &&
1758 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1759 /* Clear the no pfc TC private buffer */
1767 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1768 no_pfc_priv_num
== 0)
1772 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1775 /* step 4, try to reduce the number of pfc enabled TCs
1776 * which have private buffer.
1778 pfc_priv_num
= hclge_get_pfc_priv_num(hdev
, buf_alloc
);
1780 /* let the last to be cleared first */
1781 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1782 priv
= &buf_alloc
->priv_buf
[i
];
1784 if (hdev
->hw_tc_map
& BIT(i
) &&
1785 hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1786 /* Reduce the number of pfc TC with private buffer */
1794 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1798 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1804 static int hclge_rx_priv_buf_alloc(struct hclge_dev
*hdev
,
1805 struct hclge_pkt_buf_alloc
*buf_alloc
)
1807 struct hclge_rx_priv_buff_cmd
*req
;
1808 struct hclge_desc desc
;
1812 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_PRIV_BUFF_ALLOC
, false);
1813 req
= (struct hclge_rx_priv_buff_cmd
*)desc
.data
;
1815 /* Alloc private buffer TCs */
1816 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1817 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1820 cpu_to_le16(priv
->buf_size
>> HCLGE_BUF_UNIT_S
);
1822 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B
);
1826 cpu_to_le16((buf_alloc
->s_buf
.buf_size
>> HCLGE_BUF_UNIT_S
) |
1827 (1 << HCLGE_TC0_PRI_BUF_EN_B
));
1829 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1831 dev_err(&hdev
->pdev
->dev
,
1832 "rx private buffer alloc cmd failed %d\n", ret
);
1839 #define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1841 static int hclge_rx_priv_wl_config(struct hclge_dev
*hdev
,
1842 struct hclge_pkt_buf_alloc
*buf_alloc
)
1844 struct hclge_rx_priv_wl_buf
*req
;
1845 struct hclge_priv_buf
*priv
;
1846 struct hclge_desc desc
[2];
1850 for (i
= 0; i
< 2; i
++) {
1851 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_RX_PRIV_WL_ALLOC
,
1853 req
= (struct hclge_rx_priv_wl_buf
*)desc
[i
].data
;
1855 /* The first descriptor set the NEXT bit to 1 */
1857 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1859 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1861 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1862 u32 idx
= i
* HCLGE_TC_NUM_ONE_DESC
+ j
;
1864 priv
= &buf_alloc
->priv_buf
[idx
];
1865 req
->tc_wl
[j
].high
=
1866 cpu_to_le16(priv
->wl
.high
>> HCLGE_BUF_UNIT_S
);
1867 req
->tc_wl
[j
].high
|=
1868 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.high
) <<
1869 HCLGE_RX_PRIV_EN_B
);
1871 cpu_to_le16(priv
->wl
.low
>> HCLGE_BUF_UNIT_S
);
1872 req
->tc_wl
[j
].low
|=
1873 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.low
) <<
1874 HCLGE_RX_PRIV_EN_B
);
1878 /* Send 2 descriptor at one time */
1879 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1881 dev_err(&hdev
->pdev
->dev
,
1882 "rx private waterline config cmd failed %d\n",
1889 static int hclge_common_thrd_config(struct hclge_dev
*hdev
,
1890 struct hclge_pkt_buf_alloc
*buf_alloc
)
1892 struct hclge_shared_buf
*s_buf
= &buf_alloc
->s_buf
;
1893 struct hclge_rx_com_thrd
*req
;
1894 struct hclge_desc desc
[2];
1895 struct hclge_tc_thrd
*tc
;
1899 for (i
= 0; i
< 2; i
++) {
1900 hclge_cmd_setup_basic_desc(&desc
[i
],
1901 HCLGE_OPC_RX_COM_THRD_ALLOC
, false);
1902 req
= (struct hclge_rx_com_thrd
*)&desc
[i
].data
;
1904 /* The first descriptor set the NEXT bit to 1 */
1906 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1908 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1910 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1911 tc
= &s_buf
->tc_thrd
[i
* HCLGE_TC_NUM_ONE_DESC
+ j
];
1913 req
->com_thrd
[j
].high
=
1914 cpu_to_le16(tc
->high
>> HCLGE_BUF_UNIT_S
);
1915 req
->com_thrd
[j
].high
|=
1916 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->high
) <<
1917 HCLGE_RX_PRIV_EN_B
);
1918 req
->com_thrd
[j
].low
=
1919 cpu_to_le16(tc
->low
>> HCLGE_BUF_UNIT_S
);
1920 req
->com_thrd
[j
].low
|=
1921 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->low
) <<
1922 HCLGE_RX_PRIV_EN_B
);
1926 /* Send 2 descriptors at one time */
1927 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1929 dev_err(&hdev
->pdev
->dev
,
1930 "common threshold config cmd failed %d\n", ret
);
1936 static int hclge_common_wl_config(struct hclge_dev
*hdev
,
1937 struct hclge_pkt_buf_alloc
*buf_alloc
)
1939 struct hclge_shared_buf
*buf
= &buf_alloc
->s_buf
;
1940 struct hclge_rx_com_wl
*req
;
1941 struct hclge_desc desc
;
1944 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_COM_WL_ALLOC
, false);
1946 req
= (struct hclge_rx_com_wl
*)desc
.data
;
1947 req
->com_wl
.high
= cpu_to_le16(buf
->self
.high
>> HCLGE_BUF_UNIT_S
);
1949 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.high
) <<
1950 HCLGE_RX_PRIV_EN_B
);
1952 req
->com_wl
.low
= cpu_to_le16(buf
->self
.low
>> HCLGE_BUF_UNIT_S
);
1954 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.low
) <<
1955 HCLGE_RX_PRIV_EN_B
);
1957 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1959 dev_err(&hdev
->pdev
->dev
,
1960 "common waterline config cmd failed %d\n", ret
);
1967 int hclge_buffer_alloc(struct hclge_dev
*hdev
)
1969 struct hclge_pkt_buf_alloc
*pkt_buf
;
1972 pkt_buf
= kzalloc(sizeof(*pkt_buf
), GFP_KERNEL
);
1976 ret
= hclge_tx_buffer_calc(hdev
, pkt_buf
);
1978 dev_err(&hdev
->pdev
->dev
,
1979 "could not calc tx buffer size for all TCs %d\n", ret
);
1983 ret
= hclge_tx_buffer_alloc(hdev
, pkt_buf
);
1985 dev_err(&hdev
->pdev
->dev
,
1986 "could not alloc tx buffers %d\n", ret
);
1990 ret
= hclge_rx_buffer_calc(hdev
, pkt_buf
);
1992 dev_err(&hdev
->pdev
->dev
,
1993 "could not calc rx priv buffer size for all TCs %d\n",
1998 ret
= hclge_rx_priv_buf_alloc(hdev
, pkt_buf
);
2000 dev_err(&hdev
->pdev
->dev
, "could not alloc rx priv buffer %d\n",
2005 if (hnae3_dev_dcb_supported(hdev
)) {
2006 ret
= hclge_rx_priv_wl_config(hdev
, pkt_buf
);
2008 dev_err(&hdev
->pdev
->dev
,
2009 "could not configure rx private waterline %d\n",
2014 ret
= hclge_common_thrd_config(hdev
, pkt_buf
);
2016 dev_err(&hdev
->pdev
->dev
,
2017 "could not configure common threshold %d\n",
2023 ret
= hclge_common_wl_config(hdev
, pkt_buf
);
2025 dev_err(&hdev
->pdev
->dev
,
2026 "could not configure common waterline %d\n", ret
);
2033 static int hclge_init_roce_base_info(struct hclge_vport
*vport
)
2035 struct hnae3_handle
*roce
= &vport
->roce
;
2036 struct hnae3_handle
*nic
= &vport
->nic
;
2038 roce
->rinfo
.num_vectors
= vport
->back
->num_roce_msi
;
2040 if (vport
->back
->num_msi_left
< vport
->roce
.rinfo
.num_vectors
||
2041 vport
->back
->num_msi_left
== 0)
2044 roce
->rinfo
.base_vector
= vport
->back
->roce_base_vector
;
2046 roce
->rinfo
.netdev
= nic
->kinfo
.netdev
;
2047 roce
->rinfo
.roce_io_base
= vport
->back
->hw
.io_base
;
2049 roce
->pdev
= nic
->pdev
;
2050 roce
->ae_algo
= nic
->ae_algo
;
2051 roce
->numa_node_mask
= nic
->numa_node_mask
;
2056 static int hclge_init_msi(struct hclge_dev
*hdev
)
2058 struct pci_dev
*pdev
= hdev
->pdev
;
2062 vectors
= pci_alloc_irq_vectors(pdev
, 1, hdev
->num_msi
,
2063 PCI_IRQ_MSI
| PCI_IRQ_MSIX
);
2066 "failed(%d) to allocate MSI/MSI-X vectors\n",
2070 if (vectors
< hdev
->num_msi
)
2071 dev_warn(&hdev
->pdev
->dev
,
2072 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2073 hdev
->num_msi
, vectors
);
2075 hdev
->num_msi
= vectors
;
2076 hdev
->num_msi_left
= vectors
;
2077 hdev
->base_msi_vector
= pdev
->irq
;
2078 hdev
->roce_base_vector
= hdev
->base_msi_vector
+
2079 HCLGE_ROCE_VECTOR_OFFSET
;
2081 hdev
->vector_status
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2082 sizeof(u16
), GFP_KERNEL
);
2083 if (!hdev
->vector_status
) {
2084 pci_free_irq_vectors(pdev
);
2088 for (i
= 0; i
< hdev
->num_msi
; i
++)
2089 hdev
->vector_status
[i
] = HCLGE_INVALID_VPORT
;
2091 hdev
->vector_irq
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2092 sizeof(int), GFP_KERNEL
);
2093 if (!hdev
->vector_irq
) {
2094 pci_free_irq_vectors(pdev
);
2101 static void hclge_check_speed_dup(struct hclge_dev
*hdev
, int duplex
, int speed
)
2103 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2105 if ((speed
== HCLGE_MAC_SPEED_10M
) || (speed
== HCLGE_MAC_SPEED_100M
))
2106 mac
->duplex
= (u8
)duplex
;
2108 mac
->duplex
= HCLGE_MAC_FULL
;
2113 int hclge_cfg_mac_speed_dup(struct hclge_dev
*hdev
, int speed
, u8 duplex
)
2115 struct hclge_config_mac_speed_dup_cmd
*req
;
2116 struct hclge_desc desc
;
2119 req
= (struct hclge_config_mac_speed_dup_cmd
*)desc
.data
;
2121 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_SPEED_DUP
, false);
2123 hnae_set_bit(req
->speed_dup
, HCLGE_CFG_DUPLEX_B
, !!duplex
);
2126 case HCLGE_MAC_SPEED_10M
:
2127 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2128 HCLGE_CFG_SPEED_S
, 6);
2130 case HCLGE_MAC_SPEED_100M
:
2131 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2132 HCLGE_CFG_SPEED_S
, 7);
2134 case HCLGE_MAC_SPEED_1G
:
2135 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2136 HCLGE_CFG_SPEED_S
, 0);
2138 case HCLGE_MAC_SPEED_10G
:
2139 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2140 HCLGE_CFG_SPEED_S
, 1);
2142 case HCLGE_MAC_SPEED_25G
:
2143 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2144 HCLGE_CFG_SPEED_S
, 2);
2146 case HCLGE_MAC_SPEED_40G
:
2147 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2148 HCLGE_CFG_SPEED_S
, 3);
2150 case HCLGE_MAC_SPEED_50G
:
2151 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2152 HCLGE_CFG_SPEED_S
, 4);
2154 case HCLGE_MAC_SPEED_100G
:
2155 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2156 HCLGE_CFG_SPEED_S
, 5);
2159 dev_err(&hdev
->pdev
->dev
, "invalid speed (%d)\n", speed
);
2163 hnae_set_bit(req
->mac_change_fec_en
, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B
,
2166 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2168 dev_err(&hdev
->pdev
->dev
,
2169 "mac speed/duplex config cmd failed %d.\n", ret
);
2173 hclge_check_speed_dup(hdev
, duplex
, speed
);
2178 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle
*handle
, int speed
,
2181 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2182 struct hclge_dev
*hdev
= vport
->back
;
2184 return hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2187 static int hclge_query_mac_an_speed_dup(struct hclge_dev
*hdev
, int *speed
,
2190 struct hclge_query_an_speed_dup_cmd
*req
;
2191 struct hclge_desc desc
;
2195 req
= (struct hclge_query_an_speed_dup_cmd
*)desc
.data
;
2197 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_AN_RESULT
, true);
2198 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2200 dev_err(&hdev
->pdev
->dev
,
2201 "mac speed/autoneg/duplex query cmd failed %d\n",
2206 *duplex
= hnae_get_bit(req
->an_syn_dup_speed
, HCLGE_QUERY_DUPLEX_B
);
2207 speed_tmp
= hnae_get_field(req
->an_syn_dup_speed
, HCLGE_QUERY_SPEED_M
,
2208 HCLGE_QUERY_SPEED_S
);
2210 ret
= hclge_parse_speed(speed_tmp
, speed
);
2212 dev_err(&hdev
->pdev
->dev
,
2213 "could not parse speed(=%d), %d\n", speed_tmp
, ret
);
2220 static int hclge_set_autoneg_en(struct hclge_dev
*hdev
, bool enable
)
2222 struct hclge_config_auto_neg_cmd
*req
;
2223 struct hclge_desc desc
;
2227 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_AN_MODE
, false);
2229 req
= (struct hclge_config_auto_neg_cmd
*)desc
.data
;
2230 hnae_set_bit(flag
, HCLGE_MAC_CFG_AN_EN_B
, !!enable
);
2231 req
->cfg_an_cmd_flag
= cpu_to_le32(flag
);
2233 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2235 dev_err(&hdev
->pdev
->dev
, "auto neg set cmd failed %d.\n",
2243 static int hclge_set_autoneg(struct hnae3_handle
*handle
, bool enable
)
2245 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2246 struct hclge_dev
*hdev
= vport
->back
;
2248 return hclge_set_autoneg_en(hdev
, enable
);
2251 static int hclge_get_autoneg(struct hnae3_handle
*handle
)
2253 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2254 struct hclge_dev
*hdev
= vport
->back
;
2255 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
2258 return phydev
->autoneg
;
2260 return hdev
->hw
.mac
.autoneg
;
2263 static int hclge_set_default_mac_vlan_mask(struct hclge_dev
*hdev
,
2267 struct hclge_mac_vlan_mask_entry_cmd
*req
;
2268 struct hclge_desc desc
;
2271 req
= (struct hclge_mac_vlan_mask_entry_cmd
*)desc
.data
;
2272 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_MASK_SET
, false);
2274 hnae_set_bit(req
->vlan_mask
, HCLGE_VLAN_MASK_EN_B
,
2276 ether_addr_copy(req
->mac_mask
, mac_mask
);
2278 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2280 dev_err(&hdev
->pdev
->dev
,
2281 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2287 static int hclge_mac_init(struct hclge_dev
*hdev
)
2289 struct hnae3_handle
*handle
= &hdev
->vport
[0].nic
;
2290 struct net_device
*netdev
= handle
->kinfo
.netdev
;
2291 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2292 u8 mac_mask
[ETH_ALEN
] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
2296 ret
= hclge_cfg_mac_speed_dup(hdev
, hdev
->hw
.mac
.speed
, HCLGE_MAC_FULL
);
2298 dev_err(&hdev
->pdev
->dev
,
2299 "Config mac speed dup fail ret=%d\n", ret
);
2305 /* Initialize the MTA table work mode */
2306 hdev
->accept_mta_mc
= true;
2307 hdev
->enable_mta
= true;
2308 hdev
->mta_mac_sel_type
= HCLGE_MAC_ADDR_47_36
;
2310 ret
= hclge_set_mta_filter_mode(hdev
,
2311 hdev
->mta_mac_sel_type
,
2314 dev_err(&hdev
->pdev
->dev
, "set mta filter mode failed %d\n",
2319 ret
= hclge_cfg_func_mta_filter(hdev
, 0, hdev
->accept_mta_mc
);
2321 dev_err(&hdev
->pdev
->dev
,
2322 "set mta filter mode fail ret=%d\n", ret
);
2326 ret
= hclge_set_default_mac_vlan_mask(hdev
, true, mac_mask
);
2328 dev_err(&hdev
->pdev
->dev
,
2329 "set default mac_vlan_mask fail ret=%d\n", ret
);
2338 ret
= hclge_set_mtu(handle
, mtu
);
2340 dev_err(&hdev
->pdev
->dev
,
2341 "set mtu failed ret=%d\n", ret
);
2348 static void hclge_mbx_task_schedule(struct hclge_dev
*hdev
)
2350 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
))
2351 schedule_work(&hdev
->mbx_service_task
);
2354 static void hclge_reset_task_schedule(struct hclge_dev
*hdev
)
2356 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
))
2357 schedule_work(&hdev
->rst_service_task
);
2360 static void hclge_task_schedule(struct hclge_dev
*hdev
)
2362 if (!test_bit(HCLGE_STATE_DOWN
, &hdev
->state
) &&
2363 !test_bit(HCLGE_STATE_REMOVING
, &hdev
->state
) &&
2364 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
))
2365 (void)schedule_work(&hdev
->service_task
);
2368 static int hclge_get_mac_link_status(struct hclge_dev
*hdev
)
2370 struct hclge_link_status_cmd
*req
;
2371 struct hclge_desc desc
;
2375 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_LINK_STATUS
, true);
2376 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2378 dev_err(&hdev
->pdev
->dev
, "get link status cmd failed %d\n",
2383 req
= (struct hclge_link_status_cmd
*)desc
.data
;
2384 link_status
= req
->status
& HCLGE_LINK_STATUS
;
2386 return !!link_status
;
2389 static int hclge_get_mac_phy_link(struct hclge_dev
*hdev
)
2394 mac_state
= hclge_get_mac_link_status(hdev
);
2396 if (hdev
->hw
.mac
.phydev
) {
2397 if (!genphy_read_status(hdev
->hw
.mac
.phydev
))
2398 link_stat
= mac_state
&
2399 hdev
->hw
.mac
.phydev
->link
;
2404 link_stat
= mac_state
;
2410 static void hclge_update_link_status(struct hclge_dev
*hdev
)
2412 struct hnae3_client
*client
= hdev
->nic_client
;
2413 struct hnae3_handle
*handle
;
2419 state
= hclge_get_mac_phy_link(hdev
);
2420 if (state
!= hdev
->hw
.mac
.link
) {
2421 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2422 handle
= &hdev
->vport
[i
].nic
;
2423 client
->ops
->link_status_change(handle
, state
);
2425 hdev
->hw
.mac
.link
= state
;
2429 static int hclge_update_speed_duplex(struct hclge_dev
*hdev
)
2431 struct hclge_mac mac
= hdev
->hw
.mac
;
2436 /* get the speed and duplex as autoneg'result from mac cmd when phy
2439 if (mac
.phydev
|| !mac
.autoneg
)
2442 ret
= hclge_query_mac_an_speed_dup(hdev
, &speed
, &duplex
);
2444 dev_err(&hdev
->pdev
->dev
,
2445 "mac autoneg/speed/duplex query failed %d\n", ret
);
2449 if ((mac
.speed
!= speed
) || (mac
.duplex
!= duplex
)) {
2450 ret
= hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2452 dev_err(&hdev
->pdev
->dev
,
2453 "mac speed/duplex config failed %d\n", ret
);
2461 static int hclge_update_speed_duplex_h(struct hnae3_handle
*handle
)
2463 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2464 struct hclge_dev
*hdev
= vport
->back
;
2466 return hclge_update_speed_duplex(hdev
);
2469 static int hclge_get_status(struct hnae3_handle
*handle
)
2471 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2472 struct hclge_dev
*hdev
= vport
->back
;
2474 hclge_update_link_status(hdev
);
2476 return hdev
->hw
.mac
.link
;
2479 static void hclge_service_timer(struct timer_list
*t
)
2481 struct hclge_dev
*hdev
= from_timer(hdev
, t
, service_timer
);
2483 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
2484 hdev
->hw_stats
.stats_timer
++;
2485 hclge_task_schedule(hdev
);
2488 static void hclge_service_complete(struct hclge_dev
*hdev
)
2490 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
));
2492 /* Flush memory before next watchdog */
2493 smp_mb__before_atomic();
2494 clear_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
);
2497 static u32
hclge_check_event_cause(struct hclge_dev
*hdev
, u32
*clearval
)
2502 /* fetch the events from their corresponding regs */
2503 rst_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
);
2504 cmdq_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
);
2506 /* Assumption: If by any chance reset and mailbox events are reported
2507 * together then we will only process reset event in this go and will
2508 * defer the processing of the mailbox events. Since, we would have not
2509 * cleared RX CMDQ event this time we would receive again another
2510 * interrupt from H/W just for the mailbox.
2513 /* check for vector0 reset event sources */
2514 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
) & rst_src_reg
) {
2515 set_bit(HNAE3_GLOBAL_RESET
, &hdev
->reset_pending
);
2516 *clearval
= BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
);
2517 return HCLGE_VECTOR0_EVENT_RST
;
2520 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B
) & rst_src_reg
) {
2521 set_bit(HNAE3_CORE_RESET
, &hdev
->reset_pending
);
2522 *clearval
= BIT(HCLGE_VECTOR0_CORERESET_INT_B
);
2523 return HCLGE_VECTOR0_EVENT_RST
;
2526 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B
) & rst_src_reg
) {
2527 set_bit(HNAE3_IMP_RESET
, &hdev
->reset_pending
);
2528 *clearval
= BIT(HCLGE_VECTOR0_IMPRESET_INT_B
);
2529 return HCLGE_VECTOR0_EVENT_RST
;
2532 /* check for vector0 mailbox(=CMDQ RX) event source */
2533 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
) & cmdq_src_reg
) {
2534 cmdq_src_reg
&= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
);
2535 *clearval
= cmdq_src_reg
;
2536 return HCLGE_VECTOR0_EVENT_MBX
;
2539 return HCLGE_VECTOR0_EVENT_OTHER
;
2542 static void hclge_clear_event_cause(struct hclge_dev
*hdev
, u32 event_type
,
2545 switch (event_type
) {
2546 case HCLGE_VECTOR0_EVENT_RST
:
2547 hclge_write_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
, regclr
);
2549 case HCLGE_VECTOR0_EVENT_MBX
:
2550 hclge_write_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
, regclr
);
2555 static void hclge_enable_vector(struct hclge_misc_vector
*vector
, bool enable
)
2557 writel(enable
? 1 : 0, vector
->addr
);
2560 static irqreturn_t
hclge_misc_irq_handle(int irq
, void *data
)
2562 struct hclge_dev
*hdev
= data
;
2566 hclge_enable_vector(&hdev
->misc_vector
, false);
2567 event_cause
= hclge_check_event_cause(hdev
, &clearval
);
2569 /* vector 0 interrupt is shared with reset and mailbox source events.*/
2570 switch (event_cause
) {
2571 case HCLGE_VECTOR0_EVENT_RST
:
2572 hclge_reset_task_schedule(hdev
);
2574 case HCLGE_VECTOR0_EVENT_MBX
:
2575 /* If we are here then,
2576 * 1. Either we are not handling any mbx task and we are not
2579 * 2. We could be handling a mbx task but nothing more is
2581 * In both cases, we should schedule mbx task as there are more
2582 * mbx messages reported by this interrupt.
2584 hclge_mbx_task_schedule(hdev
);
2587 dev_dbg(&hdev
->pdev
->dev
,
2588 "received unknown or unhandled event of vector0\n");
2592 /* we should clear the source of interrupt */
2593 hclge_clear_event_cause(hdev
, event_cause
, clearval
);
2594 hclge_enable_vector(&hdev
->misc_vector
, true);
2599 static void hclge_free_vector(struct hclge_dev
*hdev
, int vector_id
)
2601 hdev
->vector_status
[vector_id
] = HCLGE_INVALID_VPORT
;
2602 hdev
->num_msi_left
+= 1;
2603 hdev
->num_msi_used
-= 1;
2606 static void hclge_get_misc_vector(struct hclge_dev
*hdev
)
2608 struct hclge_misc_vector
*vector
= &hdev
->misc_vector
;
2610 vector
->vector_irq
= pci_irq_vector(hdev
->pdev
, 0);
2612 vector
->addr
= hdev
->hw
.io_base
+ HCLGE_MISC_VECTOR_REG_BASE
;
2613 hdev
->vector_status
[0] = 0;
2615 hdev
->num_msi_left
-= 1;
2616 hdev
->num_msi_used
+= 1;
2619 static int hclge_misc_irq_init(struct hclge_dev
*hdev
)
2623 hclge_get_misc_vector(hdev
);
2625 /* this would be explicitly freed in the end */
2626 ret
= request_irq(hdev
->misc_vector
.vector_irq
, hclge_misc_irq_handle
,
2627 0, "hclge_misc", hdev
);
2629 hclge_free_vector(hdev
, 0);
2630 dev_err(&hdev
->pdev
->dev
, "request misc irq(%d) fail\n",
2631 hdev
->misc_vector
.vector_irq
);
2637 static void hclge_misc_irq_uninit(struct hclge_dev
*hdev
)
2639 free_irq(hdev
->misc_vector
.vector_irq
, hdev
);
2640 hclge_free_vector(hdev
, 0);
2643 static int hclge_notify_client(struct hclge_dev
*hdev
,
2644 enum hnae3_reset_notify_type type
)
2646 struct hnae3_client
*client
= hdev
->nic_client
;
2649 if (!client
->ops
->reset_notify
)
2652 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2653 struct hnae3_handle
*handle
= &hdev
->vport
[i
].nic
;
2656 ret
= client
->ops
->reset_notify(handle
, type
);
2664 static int hclge_reset_wait(struct hclge_dev
*hdev
)
2666 #define HCLGE_RESET_WATI_MS 100
2667 #define HCLGE_RESET_WAIT_CNT 5
2668 u32 val
, reg
, reg_bit
;
2671 switch (hdev
->reset_type
) {
2672 case HNAE3_GLOBAL_RESET
:
2673 reg
= HCLGE_GLOBAL_RESET_REG
;
2674 reg_bit
= HCLGE_GLOBAL_RESET_BIT
;
2676 case HNAE3_CORE_RESET
:
2677 reg
= HCLGE_GLOBAL_RESET_REG
;
2678 reg_bit
= HCLGE_CORE_RESET_BIT
;
2680 case HNAE3_FUNC_RESET
:
2681 reg
= HCLGE_FUN_RST_ING
;
2682 reg_bit
= HCLGE_FUN_RST_ING_B
;
2685 dev_err(&hdev
->pdev
->dev
,
2686 "Wait for unsupported reset type: %d\n",
2691 val
= hclge_read_dev(&hdev
->hw
, reg
);
2692 while (hnae_get_bit(val
, reg_bit
) && cnt
< HCLGE_RESET_WAIT_CNT
) {
2693 msleep(HCLGE_RESET_WATI_MS
);
2694 val
= hclge_read_dev(&hdev
->hw
, reg
);
2698 if (cnt
>= HCLGE_RESET_WAIT_CNT
) {
2699 dev_warn(&hdev
->pdev
->dev
,
2700 "Wait for reset timeout: %d\n", hdev
->reset_type
);
2707 static int hclge_func_reset_cmd(struct hclge_dev
*hdev
, int func_id
)
2709 struct hclge_desc desc
;
2710 struct hclge_reset_cmd
*req
= (struct hclge_reset_cmd
*)desc
.data
;
2713 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_RST_TRIGGER
, false);
2714 hnae_set_bit(req
->mac_func_reset
, HCLGE_CFG_RESET_MAC_B
, 0);
2715 hnae_set_bit(req
->mac_func_reset
, HCLGE_CFG_RESET_FUNC_B
, 1);
2716 req
->fun_reset_vfid
= func_id
;
2718 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2720 dev_err(&hdev
->pdev
->dev
,
2721 "send function reset cmd fail, status =%d\n", ret
);
2726 static void hclge_do_reset(struct hclge_dev
*hdev
)
2728 struct pci_dev
*pdev
= hdev
->pdev
;
2731 switch (hdev
->reset_type
) {
2732 case HNAE3_GLOBAL_RESET
:
2733 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2734 hnae_set_bit(val
, HCLGE_GLOBAL_RESET_BIT
, 1);
2735 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2736 dev_info(&pdev
->dev
, "Global Reset requested\n");
2738 case HNAE3_CORE_RESET
:
2739 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2740 hnae_set_bit(val
, HCLGE_CORE_RESET_BIT
, 1);
2741 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2742 dev_info(&pdev
->dev
, "Core Reset requested\n");
2744 case HNAE3_FUNC_RESET
:
2745 dev_info(&pdev
->dev
, "PF Reset requested\n");
2746 hclge_func_reset_cmd(hdev
, 0);
2747 /* schedule again to check later */
2748 set_bit(HNAE3_FUNC_RESET
, &hdev
->reset_pending
);
2749 hclge_reset_task_schedule(hdev
);
2752 dev_warn(&pdev
->dev
,
2753 "Unsupported reset type: %d\n", hdev
->reset_type
);
2758 static enum hnae3_reset_type
hclge_get_reset_level(struct hclge_dev
*hdev
,
2759 unsigned long *addr
)
2761 enum hnae3_reset_type rst_level
= HNAE3_NONE_RESET
;
2763 /* return the highest priority reset level amongst all */
2764 if (test_bit(HNAE3_GLOBAL_RESET
, addr
))
2765 rst_level
= HNAE3_GLOBAL_RESET
;
2766 else if (test_bit(HNAE3_CORE_RESET
, addr
))
2767 rst_level
= HNAE3_CORE_RESET
;
2768 else if (test_bit(HNAE3_IMP_RESET
, addr
))
2769 rst_level
= HNAE3_IMP_RESET
;
2770 else if (test_bit(HNAE3_FUNC_RESET
, addr
))
2771 rst_level
= HNAE3_FUNC_RESET
;
2773 /* now, clear all other resets */
2774 clear_bit(HNAE3_GLOBAL_RESET
, addr
);
2775 clear_bit(HNAE3_CORE_RESET
, addr
);
2776 clear_bit(HNAE3_IMP_RESET
, addr
);
2777 clear_bit(HNAE3_FUNC_RESET
, addr
);
2782 static void hclge_reset(struct hclge_dev
*hdev
)
2784 /* perform reset of the stack & ae device for a client */
2786 hclge_notify_client(hdev
, HNAE3_DOWN_CLIENT
);
2788 if (!hclge_reset_wait(hdev
)) {
2790 hclge_notify_client(hdev
, HNAE3_UNINIT_CLIENT
);
2791 hclge_reset_ae_dev(hdev
->ae_dev
);
2792 hclge_notify_client(hdev
, HNAE3_INIT_CLIENT
);
2795 /* schedule again to check pending resets later */
2796 set_bit(hdev
->reset_type
, &hdev
->reset_pending
);
2797 hclge_reset_task_schedule(hdev
);
2800 hclge_notify_client(hdev
, HNAE3_UP_CLIENT
);
2803 static void hclge_reset_event(struct hnae3_handle
*handle
,
2804 enum hnae3_reset_type reset
)
2806 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2807 struct hclge_dev
*hdev
= vport
->back
;
2809 dev_info(&hdev
->pdev
->dev
,
2810 "Receive reset event , reset_type is %d", reset
);
2813 case HNAE3_FUNC_RESET
:
2814 case HNAE3_CORE_RESET
:
2815 case HNAE3_GLOBAL_RESET
:
2816 /* request reset & schedule reset task */
2817 set_bit(reset
, &hdev
->reset_request
);
2818 hclge_reset_task_schedule(hdev
);
2821 dev_warn(&hdev
->pdev
->dev
, "Unsupported reset event:%d", reset
);
2826 static void hclge_reset_subtask(struct hclge_dev
*hdev
)
2828 /* check if there is any ongoing reset in the hardware. This status can
2829 * be checked from reset_pending. If there is then, we need to wait for
2830 * hardware to complete reset.
2831 * a. If we are able to figure out in reasonable time that hardware
2832 * has fully resetted then, we can proceed with driver, client
2834 * b. else, we can come back later to check this status so re-sched
2837 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_pending
);
2838 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2841 /* check if we got any *new* reset requests to be honored */
2842 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_request
);
2843 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2844 hclge_do_reset(hdev
);
2846 hdev
->reset_type
= HNAE3_NONE_RESET
;
2849 static void hclge_reset_service_task(struct work_struct
*work
)
2851 struct hclge_dev
*hdev
=
2852 container_of(work
, struct hclge_dev
, rst_service_task
);
2854 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
2857 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
2859 hclge_reset_subtask(hdev
);
2861 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
2864 static void hclge_mailbox_service_task(struct work_struct
*work
)
2866 struct hclge_dev
*hdev
=
2867 container_of(work
, struct hclge_dev
, mbx_service_task
);
2869 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
))
2872 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
2874 hclge_mbx_handler(hdev
);
2876 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
2879 static void hclge_service_task(struct work_struct
*work
)
2881 struct hclge_dev
*hdev
=
2882 container_of(work
, struct hclge_dev
, service_task
);
2884 /* The total rx/tx packets statstics are wanted to be updated
2885 * per second. Both hclge_update_stats_for_all() and
2886 * hclge_mac_get_traffic_stats() can do it.
2888 if (hdev
->hw_stats
.stats_timer
>= HCLGE_STATS_TIMER_INTERVAL
) {
2889 hclge_update_stats_for_all(hdev
);
2890 hdev
->hw_stats
.stats_timer
= 0;
2892 hclge_mac_get_traffic_stats(hdev
);
2895 hclge_update_speed_duplex(hdev
);
2896 hclge_update_link_status(hdev
);
2897 hclge_update_led_status(hdev
);
2898 hclge_service_complete(hdev
);
2901 static void hclge_disable_sriov(struct hclge_dev
*hdev
)
2903 /* If our VFs are assigned we cannot shut down SR-IOV
2904 * without causing issues, so just leave the hardware
2905 * available but disabled
2907 if (pci_vfs_assigned(hdev
->pdev
)) {
2908 dev_warn(&hdev
->pdev
->dev
,
2909 "disabling driver while VFs are assigned\n");
2913 pci_disable_sriov(hdev
->pdev
);
2916 struct hclge_vport
*hclge_get_vport(struct hnae3_handle
*handle
)
2918 /* VF handle has no client */
2919 if (!handle
->client
)
2920 return container_of(handle
, struct hclge_vport
, nic
);
2921 else if (handle
->client
->type
== HNAE3_CLIENT_ROCE
)
2922 return container_of(handle
, struct hclge_vport
, roce
);
2924 return container_of(handle
, struct hclge_vport
, nic
);
2927 static int hclge_get_vector(struct hnae3_handle
*handle
, u16 vector_num
,
2928 struct hnae3_vector_info
*vector_info
)
2930 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2931 struct hnae3_vector_info
*vector
= vector_info
;
2932 struct hclge_dev
*hdev
= vport
->back
;
2936 vector_num
= min(hdev
->num_msi_left
, vector_num
);
2938 for (j
= 0; j
< vector_num
; j
++) {
2939 for (i
= 1; i
< hdev
->num_msi
; i
++) {
2940 if (hdev
->vector_status
[i
] == HCLGE_INVALID_VPORT
) {
2941 vector
->vector
= pci_irq_vector(hdev
->pdev
, i
);
2942 vector
->io_addr
= hdev
->hw
.io_base
+
2943 HCLGE_VECTOR_REG_BASE
+
2944 (i
- 1) * HCLGE_VECTOR_REG_OFFSET
+
2946 HCLGE_VECTOR_VF_OFFSET
;
2947 hdev
->vector_status
[i
] = vport
->vport_id
;
2948 hdev
->vector_irq
[i
] = vector
->vector
;
2957 hdev
->num_msi_left
-= alloc
;
2958 hdev
->num_msi_used
+= alloc
;
2963 static int hclge_get_vector_index(struct hclge_dev
*hdev
, int vector
)
2967 for (i
= 0; i
< hdev
->num_msi
; i
++)
2968 if (vector
== hdev
->vector_irq
[i
])
2974 static u32
hclge_get_rss_key_size(struct hnae3_handle
*handle
)
2976 return HCLGE_RSS_KEY_SIZE
;
2979 static u32
hclge_get_rss_indir_size(struct hnae3_handle
*handle
)
2981 return HCLGE_RSS_IND_TBL_SIZE
;
2984 static int hclge_get_rss_algo(struct hclge_dev
*hdev
)
2986 struct hclge_rss_config_cmd
*req
;
2987 struct hclge_desc desc
;
2991 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_GENERIC_CONFIG
, true);
2993 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2995 dev_err(&hdev
->pdev
->dev
,
2996 "Get link status error, status =%d\n", ret
);
3000 req
= (struct hclge_rss_config_cmd
*)desc
.data
;
3001 rss_hash_algo
= (req
->hash_config
& HCLGE_RSS_HASH_ALGO_MASK
);
3003 if (rss_hash_algo
== HCLGE_RSS_HASH_ALGO_TOEPLITZ
)
3004 return ETH_RSS_HASH_TOP
;
3009 static int hclge_set_rss_algo_key(struct hclge_dev
*hdev
,
3010 const u8 hfunc
, const u8
*key
)
3012 struct hclge_rss_config_cmd
*req
;
3013 struct hclge_desc desc
;
3018 req
= (struct hclge_rss_config_cmd
*)desc
.data
;
3020 for (key_offset
= 0; key_offset
< 3; key_offset
++) {
3021 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_GENERIC_CONFIG
,
3024 req
->hash_config
|= (hfunc
& HCLGE_RSS_HASH_ALGO_MASK
);
3025 req
->hash_config
|= (key_offset
<< HCLGE_RSS_HASH_KEY_OFFSET_B
);
3027 if (key_offset
== 2)
3029 HCLGE_RSS_KEY_SIZE
- HCLGE_RSS_HASH_KEY_NUM
* 2;
3031 key_size
= HCLGE_RSS_HASH_KEY_NUM
;
3033 memcpy(req
->hash_key
,
3034 key
+ key_offset
* HCLGE_RSS_HASH_KEY_NUM
, key_size
);
3036 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3038 dev_err(&hdev
->pdev
->dev
,
3039 "Configure RSS config fail, status = %d\n",
3047 static int hclge_set_rss_indir_table(struct hclge_dev
*hdev
, const u32
*indir
)
3049 struct hclge_rss_indirection_table_cmd
*req
;
3050 struct hclge_desc desc
;
3054 req
= (struct hclge_rss_indirection_table_cmd
*)desc
.data
;
3056 for (i
= 0; i
< HCLGE_RSS_CFG_TBL_NUM
; i
++) {
3057 hclge_cmd_setup_basic_desc
3058 (&desc
, HCLGE_OPC_RSS_INDIR_TABLE
, false);
3060 req
->start_table_index
=
3061 cpu_to_le16(i
* HCLGE_RSS_CFG_TBL_SIZE
);
3062 req
->rss_set_bitmap
= cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK
);
3064 for (j
= 0; j
< HCLGE_RSS_CFG_TBL_SIZE
; j
++)
3065 req
->rss_result
[j
] =
3066 indir
[i
* HCLGE_RSS_CFG_TBL_SIZE
+ j
];
3068 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3070 dev_err(&hdev
->pdev
->dev
,
3071 "Configure rss indir table fail,status = %d\n",
3079 static int hclge_set_rss_tc_mode(struct hclge_dev
*hdev
, u16
*tc_valid
,
3080 u16
*tc_size
, u16
*tc_offset
)
3082 struct hclge_rss_tc_mode_cmd
*req
;
3083 struct hclge_desc desc
;
3087 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_TC_MODE
, false);
3088 req
= (struct hclge_rss_tc_mode_cmd
*)desc
.data
;
3090 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3093 hnae_set_bit(mode
, HCLGE_RSS_TC_VALID_B
, (tc_valid
[i
] & 0x1));
3094 hnae_set_field(mode
, HCLGE_RSS_TC_SIZE_M
,
3095 HCLGE_RSS_TC_SIZE_S
, tc_size
[i
]);
3096 hnae_set_field(mode
, HCLGE_RSS_TC_OFFSET_M
,
3097 HCLGE_RSS_TC_OFFSET_S
, tc_offset
[i
]);
3099 req
->rss_tc_mode
[i
] = cpu_to_le16(mode
);
3102 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3104 dev_err(&hdev
->pdev
->dev
,
3105 "Configure rss tc mode fail, status = %d\n", ret
);
3112 static int hclge_set_rss_input_tuple(struct hclge_dev
*hdev
)
3114 struct hclge_rss_input_tuple_cmd
*req
;
3115 struct hclge_desc desc
;
3118 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
3120 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3121 req
->ipv4_tcp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3122 req
->ipv4_udp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3123 req
->ipv4_sctp_en
= HCLGE_RSS_INPUT_TUPLE_SCTP
;
3124 req
->ipv4_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3125 req
->ipv6_tcp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3126 req
->ipv6_udp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3127 req
->ipv6_sctp_en
= HCLGE_RSS_INPUT_TUPLE_SCTP
;
3128 req
->ipv6_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3129 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3131 dev_err(&hdev
->pdev
->dev
,
3132 "Configure rss input fail, status = %d\n", ret
);
3139 static int hclge_get_rss(struct hnae3_handle
*handle
, u32
*indir
,
3142 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3143 struct hclge_dev
*hdev
= vport
->back
;
3146 /* Get hash algorithm */
3148 *hfunc
= hclge_get_rss_algo(hdev
);
3150 /* Get the RSS Key required by the user */
3152 memcpy(key
, vport
->rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
3154 /* Get indirect table */
3156 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3157 indir
[i
] = vport
->rss_indirection_tbl
[i
];
3162 static int hclge_set_rss(struct hnae3_handle
*handle
, const u32
*indir
,
3163 const u8
*key
, const u8 hfunc
)
3165 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3166 struct hclge_dev
*hdev
= vport
->back
;
3170 /* Set the RSS Hash Key if specififed by the user */
3172 /* Update the shadow RSS key with user specified qids */
3173 memcpy(vport
->rss_hash_key
, key
, HCLGE_RSS_KEY_SIZE
);
3175 if (hfunc
== ETH_RSS_HASH_TOP
||
3176 hfunc
== ETH_RSS_HASH_NO_CHANGE
)
3177 hash_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3180 ret
= hclge_set_rss_algo_key(hdev
, hash_algo
, key
);
3185 /* Update the shadow RSS table with user specified qids */
3186 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3187 vport
->rss_indirection_tbl
[i
] = indir
[i
];
3189 /* Update the hardware */
3190 ret
= hclge_set_rss_indir_table(hdev
, indir
);
3194 static u8
hclge_get_rss_hash_bits(struct ethtool_rxnfc
*nfc
)
3196 u8 hash_sets
= nfc
->data
& RXH_L4_B_0_1
? HCLGE_S_PORT_BIT
: 0;
3198 if (nfc
->data
& RXH_L4_B_2_3
)
3199 hash_sets
|= HCLGE_D_PORT_BIT
;
3201 hash_sets
&= ~HCLGE_D_PORT_BIT
;
3203 if (nfc
->data
& RXH_IP_SRC
)
3204 hash_sets
|= HCLGE_S_IP_BIT
;
3206 hash_sets
&= ~HCLGE_S_IP_BIT
;
3208 if (nfc
->data
& RXH_IP_DST
)
3209 hash_sets
|= HCLGE_D_IP_BIT
;
3211 hash_sets
&= ~HCLGE_D_IP_BIT
;
3213 if (nfc
->flow_type
== SCTP_V4_FLOW
|| nfc
->flow_type
== SCTP_V6_FLOW
)
3214 hash_sets
|= HCLGE_V_TAG_BIT
;
3219 static int hclge_set_rss_tuple(struct hnae3_handle
*handle
,
3220 struct ethtool_rxnfc
*nfc
)
3222 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3223 struct hclge_dev
*hdev
= vport
->back
;
3224 struct hclge_rss_input_tuple_cmd
*req
;
3225 struct hclge_desc desc
;
3229 if (nfc
->data
& ~(RXH_IP_SRC
| RXH_IP_DST
|
3230 RXH_L4_B_0_1
| RXH_L4_B_2_3
))
3233 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3234 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, true);
3235 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3237 dev_err(&hdev
->pdev
->dev
,
3238 "Read rss tuple fail, status = %d\n", ret
);
3242 hclge_cmd_reuse_desc(&desc
, false);
3244 tuple_sets
= hclge_get_rss_hash_bits(nfc
);
3245 switch (nfc
->flow_type
) {
3247 req
->ipv4_tcp_en
= tuple_sets
;
3250 req
->ipv6_tcp_en
= tuple_sets
;
3253 req
->ipv4_udp_en
= tuple_sets
;
3256 req
->ipv6_udp_en
= tuple_sets
;
3259 req
->ipv4_sctp_en
= tuple_sets
;
3262 if ((nfc
->data
& RXH_L4_B_0_1
) ||
3263 (nfc
->data
& RXH_L4_B_2_3
))
3266 req
->ipv6_sctp_en
= tuple_sets
;
3269 req
->ipv4_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3272 req
->ipv6_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3278 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3280 dev_err(&hdev
->pdev
->dev
,
3281 "Set rss tuple fail, status = %d\n", ret
);
3286 static int hclge_get_rss_tuple(struct hnae3_handle
*handle
,
3287 struct ethtool_rxnfc
*nfc
)
3289 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3290 struct hclge_dev
*hdev
= vport
->back
;
3291 struct hclge_rss_input_tuple_cmd
*req
;
3292 struct hclge_desc desc
;
3298 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3299 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, true);
3300 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3302 dev_err(&hdev
->pdev
->dev
,
3303 "Read rss tuple fail, status = %d\n", ret
);
3307 switch (nfc
->flow_type
) {
3309 tuple_sets
= req
->ipv4_tcp_en
;
3312 tuple_sets
= req
->ipv4_udp_en
;
3315 tuple_sets
= req
->ipv6_tcp_en
;
3318 tuple_sets
= req
->ipv6_udp_en
;
3321 tuple_sets
= req
->ipv4_sctp_en
;
3324 tuple_sets
= req
->ipv6_sctp_en
;
3328 tuple_sets
= HCLGE_S_IP_BIT
| HCLGE_D_IP_BIT
;
3337 if (tuple_sets
& HCLGE_D_PORT_BIT
)
3338 nfc
->data
|= RXH_L4_B_2_3
;
3339 if (tuple_sets
& HCLGE_S_PORT_BIT
)
3340 nfc
->data
|= RXH_L4_B_0_1
;
3341 if (tuple_sets
& HCLGE_D_IP_BIT
)
3342 nfc
->data
|= RXH_IP_DST
;
3343 if (tuple_sets
& HCLGE_S_IP_BIT
)
3344 nfc
->data
|= RXH_IP_SRC
;
3349 static int hclge_get_tc_size(struct hnae3_handle
*handle
)
3351 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3352 struct hclge_dev
*hdev
= vport
->back
;
3354 return hdev
->rss_size_max
;
3357 int hclge_rss_init_hw(struct hclge_dev
*hdev
)
3359 const u8 hfunc
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3360 struct hclge_vport
*vport
= hdev
->vport
;
3361 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
3362 u8 rss_key
[HCLGE_RSS_KEY_SIZE
];
3363 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
3364 u16 tc_size
[HCLGE_MAX_TC_NUM
];
3365 u32
*rss_indir
= NULL
;
3366 u16 rss_size
= 0, roundup_size
;
3370 rss_indir
= kcalloc(HCLGE_RSS_IND_TBL_SIZE
, sizeof(u32
), GFP_KERNEL
);
3374 /* Get default RSS key */
3375 netdev_rss_key_fill(rss_key
, HCLGE_RSS_KEY_SIZE
);
3377 /* Initialize RSS indirect table for each vport */
3378 for (j
= 0; j
< hdev
->num_vmdq_vport
+ 1; j
++) {
3379 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++) {
3380 vport
[j
].rss_indirection_tbl
[i
] =
3381 i
% vport
[j
].alloc_rss_size
;
3383 /* vport 0 is for PF */
3387 rss_size
= vport
[j
].alloc_rss_size
;
3388 rss_indir
[i
] = vport
[j
].rss_indirection_tbl
[i
];
3391 ret
= hclge_set_rss_indir_table(hdev
, rss_indir
);
3396 ret
= hclge_set_rss_algo_key(hdev
, hfunc
, key
);
3400 ret
= hclge_set_rss_input_tuple(hdev
);
3404 /* Each TC have the same queue size, and tc_size set to hardware is
3405 * the log2 of roundup power of two of rss_size, the acutal queue
3406 * size is limited by indirection table.
3408 if (rss_size
> HCLGE_RSS_TC_SIZE_7
|| rss_size
== 0) {
3409 dev_err(&hdev
->pdev
->dev
,
3410 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3416 roundup_size
= roundup_pow_of_two(rss_size
);
3417 roundup_size
= ilog2(roundup_size
);
3419 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3422 if (!(hdev
->hw_tc_map
& BIT(i
)))
3426 tc_size
[i
] = roundup_size
;
3427 tc_offset
[i
] = rss_size
* i
;
3430 ret
= hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
3438 int hclge_bind_ring_with_vector(struct hclge_vport
*vport
,
3439 int vector_id
, bool en
,
3440 struct hnae3_ring_chain_node
*ring_chain
)
3442 struct hclge_dev
*hdev
= vport
->back
;
3443 struct hnae3_ring_chain_node
*node
;
3444 struct hclge_desc desc
;
3445 struct hclge_ctrl_vector_chain_cmd
*req
3446 = (struct hclge_ctrl_vector_chain_cmd
*)desc
.data
;
3447 enum hclge_cmd_status status
;
3448 enum hclge_opcode_type op
;
3449 u16 tqp_type_and_id
;
3452 op
= en
? HCLGE_OPC_ADD_RING_TO_VECTOR
: HCLGE_OPC_DEL_RING_TO_VECTOR
;
3453 hclge_cmd_setup_basic_desc(&desc
, op
, false);
3454 req
->int_vector_id
= vector_id
;
3457 for (node
= ring_chain
; node
; node
= node
->next
) {
3458 tqp_type_and_id
= le16_to_cpu(req
->tqp_type_and_id
[i
]);
3459 hnae_set_field(tqp_type_and_id
, HCLGE_INT_TYPE_M
,
3461 hnae_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
3462 hnae_set_field(tqp_type_and_id
, HCLGE_TQP_ID_M
,
3463 HCLGE_TQP_ID_S
, node
->tqp_index
);
3464 hnae_set_field(tqp_type_and_id
, HCLGE_INT_GL_IDX_M
,
3466 hnae_get_field(node
->int_gl_idx
,
3467 HNAE3_RING_GL_IDX_M
,
3468 HNAE3_RING_GL_IDX_S
));
3469 req
->tqp_type_and_id
[i
] = cpu_to_le16(tqp_type_and_id
);
3470 if (++i
>= HCLGE_VECTOR_ELEMENTS_PER_CMD
) {
3471 req
->int_cause_num
= HCLGE_VECTOR_ELEMENTS_PER_CMD
;
3472 req
->vfid
= vport
->vport_id
;
3474 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3476 dev_err(&hdev
->pdev
->dev
,
3477 "Map TQP fail, status is %d.\n",
3483 hclge_cmd_setup_basic_desc(&desc
,
3486 req
->int_vector_id
= vector_id
;
3491 req
->int_cause_num
= i
;
3492 req
->vfid
= vport
->vport_id
;
3493 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3495 dev_err(&hdev
->pdev
->dev
,
3496 "Map TQP fail, status is %d.\n", status
);
3504 static int hclge_map_ring_to_vector(struct hnae3_handle
*handle
,
3506 struct hnae3_ring_chain_node
*ring_chain
)
3508 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3509 struct hclge_dev
*hdev
= vport
->back
;
3512 vector_id
= hclge_get_vector_index(hdev
, vector
);
3513 if (vector_id
< 0) {
3514 dev_err(&hdev
->pdev
->dev
,
3515 "Get vector index fail. vector_id =%d\n", vector_id
);
3519 return hclge_bind_ring_with_vector(vport
, vector_id
, true, ring_chain
);
3522 static int hclge_unmap_ring_frm_vector(struct hnae3_handle
*handle
,
3524 struct hnae3_ring_chain_node
*ring_chain
)
3526 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3527 struct hclge_dev
*hdev
= vport
->back
;
3530 vector_id
= hclge_get_vector_index(hdev
, vector
);
3531 if (vector_id
< 0) {
3532 dev_err(&handle
->pdev
->dev
,
3533 "Get vector index fail. ret =%d\n", vector_id
);
3537 ret
= hclge_bind_ring_with_vector(vport
, vector_id
, false, ring_chain
);
3539 dev_err(&handle
->pdev
->dev
,
3540 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3546 /* Free this MSIX or MSI vector */
3547 hclge_free_vector(hdev
, vector_id
);
3552 int hclge_cmd_set_promisc_mode(struct hclge_dev
*hdev
,
3553 struct hclge_promisc_param
*param
)
3555 struct hclge_promisc_cfg_cmd
*req
;
3556 struct hclge_desc desc
;
3559 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_PROMISC_MODE
, false);
3561 req
= (struct hclge_promisc_cfg_cmd
*)desc
.data
;
3562 req
->vf_id
= param
->vf_id
;
3563 req
->flag
= (param
->enable
<< HCLGE_PROMISC_EN_B
);
3565 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3567 dev_err(&hdev
->pdev
->dev
,
3568 "Set promisc mode fail, status is %d.\n", ret
);
3574 void hclge_promisc_param_init(struct hclge_promisc_param
*param
, bool en_uc
,
3575 bool en_mc
, bool en_bc
, int vport_id
)
3580 memset(param
, 0, sizeof(struct hclge_promisc_param
));
3582 param
->enable
= HCLGE_PROMISC_EN_UC
;
3584 param
->enable
|= HCLGE_PROMISC_EN_MC
;
3586 param
->enable
|= HCLGE_PROMISC_EN_BC
;
3587 param
->vf_id
= vport_id
;
3590 static void hclge_set_promisc_mode(struct hnae3_handle
*handle
, u32 en
)
3592 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3593 struct hclge_dev
*hdev
= vport
->back
;
3594 struct hclge_promisc_param param
;
3596 hclge_promisc_param_init(¶m
, en
, en
, true, vport
->vport_id
);
3597 hclge_cmd_set_promisc_mode(hdev
, ¶m
);
3600 static void hclge_cfg_mac_mode(struct hclge_dev
*hdev
, bool enable
)
3602 struct hclge_desc desc
;
3603 struct hclge_config_mac_mode_cmd
*req
=
3604 (struct hclge_config_mac_mode_cmd
*)desc
.data
;
3608 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAC_MODE
, false);
3609 hnae_set_bit(loop_en
, HCLGE_MAC_TX_EN_B
, enable
);
3610 hnae_set_bit(loop_en
, HCLGE_MAC_RX_EN_B
, enable
);
3611 hnae_set_bit(loop_en
, HCLGE_MAC_PAD_TX_B
, enable
);
3612 hnae_set_bit(loop_en
, HCLGE_MAC_PAD_RX_B
, enable
);
3613 hnae_set_bit(loop_en
, HCLGE_MAC_1588_TX_B
, 0);
3614 hnae_set_bit(loop_en
, HCLGE_MAC_1588_RX_B
, 0);
3615 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 0);
3616 hnae_set_bit(loop_en
, HCLGE_MAC_LINE_LP_B
, 0);
3617 hnae_set_bit(loop_en
, HCLGE_MAC_FCS_TX_B
, enable
);
3618 hnae_set_bit(loop_en
, HCLGE_MAC_RX_FCS_B
, enable
);
3619 hnae_set_bit(loop_en
, HCLGE_MAC_RX_FCS_STRIP_B
, enable
);
3620 hnae_set_bit(loop_en
, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B
, enable
);
3621 hnae_set_bit(loop_en
, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B
, enable
);
3622 hnae_set_bit(loop_en
, HCLGE_MAC_TX_UNDER_MIN_ERR_B
, enable
);
3623 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3625 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3627 dev_err(&hdev
->pdev
->dev
,
3628 "mac enable fail, ret =%d.\n", ret
);
3631 static int hclge_set_loopback(struct hnae3_handle
*handle
,
3632 enum hnae3_loop loop_mode
, bool en
)
3634 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3635 struct hclge_config_mac_mode_cmd
*req
;
3636 struct hclge_dev
*hdev
= vport
->back
;
3637 struct hclge_desc desc
;
3641 switch (loop_mode
) {
3642 case HNAE3_MAC_INTER_LOOP_MAC
:
3643 req
= (struct hclge_config_mac_mode_cmd
*)&desc
.data
[0];
3644 /* 1 Read out the MAC mode config at first */
3645 hclge_cmd_setup_basic_desc(&desc
,
3646 HCLGE_OPC_CONFIG_MAC_MODE
,
3648 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3650 dev_err(&hdev
->pdev
->dev
,
3651 "mac loopback get fail, ret =%d.\n",
3656 /* 2 Then setup the loopback flag */
3657 loop_en
= le32_to_cpu(req
->txrx_pad_fcs_loop_en
);
3659 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 1);
3661 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 0);
3663 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3665 /* 3 Config mac work mode with loopback flag
3666 * and its original configure parameters
3668 hclge_cmd_reuse_desc(&desc
, false);
3669 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3671 dev_err(&hdev
->pdev
->dev
,
3672 "mac loopback set fail, ret =%d.\n", ret
);
3676 dev_err(&hdev
->pdev
->dev
,
3677 "loop_mode %d is not supported\n", loop_mode
);
3684 static int hclge_tqp_enable(struct hclge_dev
*hdev
, int tqp_id
,
3685 int stream_id
, bool enable
)
3687 struct hclge_desc desc
;
3688 struct hclge_cfg_com_tqp_queue_cmd
*req
=
3689 (struct hclge_cfg_com_tqp_queue_cmd
*)desc
.data
;
3692 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_COM_TQP_QUEUE
, false);
3693 req
->tqp_id
= cpu_to_le16(tqp_id
& HCLGE_RING_ID_MASK
);
3694 req
->stream_id
= cpu_to_le16(stream_id
);
3695 req
->enable
|= enable
<< HCLGE_TQP_ENABLE_B
;
3697 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3699 dev_err(&hdev
->pdev
->dev
,
3700 "Tqp enable fail, status =%d.\n", ret
);
3704 static void hclge_reset_tqp_stats(struct hnae3_handle
*handle
)
3706 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3707 struct hnae3_queue
*queue
;
3708 struct hclge_tqp
*tqp
;
3711 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
3712 queue
= handle
->kinfo
.tqp
[i
];
3713 tqp
= container_of(queue
, struct hclge_tqp
, q
);
3714 memset(&tqp
->tqp_stats
, 0, sizeof(tqp
->tqp_stats
));
3718 static int hclge_ae_start(struct hnae3_handle
*handle
)
3720 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3721 struct hclge_dev
*hdev
= vport
->back
;
3724 for (i
= 0; i
< vport
->alloc_tqps
; i
++)
3725 hclge_tqp_enable(hdev
, i
, 0, true);
3728 hclge_cfg_mac_mode(hdev
, true);
3729 clear_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
3730 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
3732 ret
= hclge_mac_start_phy(hdev
);
3736 /* reset tqp stats */
3737 hclge_reset_tqp_stats(handle
);
3742 static void hclge_ae_stop(struct hnae3_handle
*handle
)
3744 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3745 struct hclge_dev
*hdev
= vport
->back
;
3748 for (i
= 0; i
< vport
->alloc_tqps
; i
++)
3749 hclge_tqp_enable(hdev
, i
, 0, false);
3752 hclge_cfg_mac_mode(hdev
, false);
3754 hclge_mac_stop_phy(hdev
);
3756 /* reset tqp stats */
3757 hclge_reset_tqp_stats(handle
);
3760 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport
*vport
,
3761 u16 cmdq_resp
, u8 resp_code
,
3762 enum hclge_mac_vlan_tbl_opcode op
)
3764 struct hclge_dev
*hdev
= vport
->back
;
3765 int return_status
= -EIO
;
3768 dev_err(&hdev
->pdev
->dev
,
3769 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3774 if (op
== HCLGE_MAC_VLAN_ADD
) {
3775 if ((!resp_code
) || (resp_code
== 1)) {
3777 } else if (resp_code
== 2) {
3778 return_status
= -EIO
;
3779 dev_err(&hdev
->pdev
->dev
,
3780 "add mac addr failed for uc_overflow.\n");
3781 } else if (resp_code
== 3) {
3782 return_status
= -EIO
;
3783 dev_err(&hdev
->pdev
->dev
,
3784 "add mac addr failed for mc_overflow.\n");
3786 dev_err(&hdev
->pdev
->dev
,
3787 "add mac addr failed for undefined, code=%d.\n",
3790 } else if (op
== HCLGE_MAC_VLAN_REMOVE
) {
3793 } else if (resp_code
== 1) {
3794 return_status
= -EIO
;
3795 dev_dbg(&hdev
->pdev
->dev
,
3796 "remove mac addr failed for miss.\n");
3798 dev_err(&hdev
->pdev
->dev
,
3799 "remove mac addr failed for undefined, code=%d.\n",
3802 } else if (op
== HCLGE_MAC_VLAN_LKUP
) {
3805 } else if (resp_code
== 1) {
3806 return_status
= -EIO
;
3807 dev_dbg(&hdev
->pdev
->dev
,
3808 "lookup mac addr failed for miss.\n");
3810 dev_err(&hdev
->pdev
->dev
,
3811 "lookup mac addr failed for undefined, code=%d.\n",
3815 return_status
= -EIO
;
3816 dev_err(&hdev
->pdev
->dev
,
3817 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3821 return return_status
;
3824 static int hclge_update_desc_vfid(struct hclge_desc
*desc
, int vfid
, bool clr
)
3829 if (vfid
> 255 || vfid
< 0)
3832 if (vfid
>= 0 && vfid
<= 191) {
3833 word_num
= vfid
/ 32;
3834 bit_num
= vfid
% 32;
3836 desc
[1].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3838 desc
[1].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3840 word_num
= (vfid
- 192) / 32;
3841 bit_num
= vfid
% 32;
3843 desc
[2].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3845 desc
[2].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3851 static bool hclge_is_all_function_id_zero(struct hclge_desc
*desc
)
3853 #define HCLGE_DESC_NUMBER 3
3854 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3857 for (i
= 0; i
< HCLGE_DESC_NUMBER
; i
++)
3858 for (j
= 0; j
< HCLGE_FUNC_NUMBER_PER_DESC
; j
++)
3859 if (desc
[i
].data
[j
])
3865 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd
*new_req
,
3868 const unsigned char *mac_addr
= addr
;
3869 u32 high_val
= mac_addr
[2] << 16 | (mac_addr
[3] << 24) |
3870 (mac_addr
[0]) | (mac_addr
[1] << 8);
3871 u32 low_val
= mac_addr
[4] | (mac_addr
[5] << 8);
3873 new_req
->mac_addr_hi32
= cpu_to_le32(high_val
);
3874 new_req
->mac_addr_lo16
= cpu_to_le16(low_val
& 0xffff);
3877 static u16
hclge_get_mac_addr_to_mta_index(struct hclge_vport
*vport
,
3880 u16 high_val
= addr
[1] | (addr
[0] << 8);
3881 struct hclge_dev
*hdev
= vport
->back
;
3882 u32 rsh
= 4 - hdev
->mta_mac_sel_type
;
3883 u16 ret_val
= (high_val
>> rsh
) & 0xfff;
3888 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
3889 enum hclge_mta_dmac_sel_type mta_mac_sel
,
3892 struct hclge_mta_filter_mode_cmd
*req
;
3893 struct hclge_desc desc
;
3896 req
= (struct hclge_mta_filter_mode_cmd
*)desc
.data
;
3897 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_MODE_CFG
, false);
3899 hnae_set_bit(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_EN_B
,
3901 hnae_set_field(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_SEL_M
,
3902 HCLGE_CFG_MTA_MAC_SEL_S
, mta_mac_sel
);
3904 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3906 dev_err(&hdev
->pdev
->dev
,
3907 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3915 int hclge_cfg_func_mta_filter(struct hclge_dev
*hdev
,
3919 struct hclge_cfg_func_mta_filter_cmd
*req
;
3920 struct hclge_desc desc
;
3923 req
= (struct hclge_cfg_func_mta_filter_cmd
*)desc
.data
;
3924 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_FUNC_CFG
, false);
3926 hnae_set_bit(req
->accept
, HCLGE_CFG_FUNC_MTA_ACCEPT_B
,
3928 req
->function_id
= func_id
;
3930 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3932 dev_err(&hdev
->pdev
->dev
,
3933 "Config func_id enable failed for cmd_send, ret =%d.\n",
3941 static int hclge_set_mta_table_item(struct hclge_vport
*vport
,
3945 struct hclge_dev
*hdev
= vport
->back
;
3946 struct hclge_cfg_func_mta_item_cmd
*req
;
3947 struct hclge_desc desc
;
3951 req
= (struct hclge_cfg_func_mta_item_cmd
*)desc
.data
;
3952 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_TBL_ITEM_CFG
, false);
3953 hnae_set_bit(req
->accept
, HCLGE_CFG_MTA_ITEM_ACCEPT_B
, enable
);
3955 hnae_set_field(item_idx
, HCLGE_CFG_MTA_ITEM_IDX_M
,
3956 HCLGE_CFG_MTA_ITEM_IDX_S
, idx
);
3957 req
->item_idx
= cpu_to_le16(item_idx
);
3959 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3961 dev_err(&hdev
->pdev
->dev
,
3962 "Config mta table item failed for cmd_send, ret =%d.\n",
3970 static int hclge_remove_mac_vlan_tbl(struct hclge_vport
*vport
,
3971 struct hclge_mac_vlan_tbl_entry_cmd
*req
)
3973 struct hclge_dev
*hdev
= vport
->back
;
3974 struct hclge_desc desc
;
3979 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_REMOVE
, false);
3981 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
3983 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3985 dev_err(&hdev
->pdev
->dev
,
3986 "del mac addr failed for cmd_send, ret =%d.\n",
3990 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
3991 retval
= le16_to_cpu(desc
.retval
);
3993 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
3994 HCLGE_MAC_VLAN_REMOVE
);
3997 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport
*vport
,
3998 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
3999 struct hclge_desc
*desc
,
4002 struct hclge_dev
*hdev
= vport
->back
;
4007 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_MAC_VLAN_ADD
, true);
4009 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4010 memcpy(desc
[0].data
,
4012 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4013 hclge_cmd_setup_basic_desc(&desc
[1],
4014 HCLGE_OPC_MAC_VLAN_ADD
,
4016 desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4017 hclge_cmd_setup_basic_desc(&desc
[2],
4018 HCLGE_OPC_MAC_VLAN_ADD
,
4020 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 3);
4022 memcpy(desc
[0].data
,
4024 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4025 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
4028 dev_err(&hdev
->pdev
->dev
,
4029 "lookup mac addr failed for cmd_send, ret =%d.\n",
4033 resp_code
= (le32_to_cpu(desc
[0].data
[0]) >> 8) & 0xff;
4034 retval
= le16_to_cpu(desc
[0].retval
);
4036 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
4037 HCLGE_MAC_VLAN_LKUP
);
4040 static int hclge_add_mac_vlan_tbl(struct hclge_vport
*vport
,
4041 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
4042 struct hclge_desc
*mc_desc
)
4044 struct hclge_dev
*hdev
= vport
->back
;
4051 struct hclge_desc desc
;
4053 hclge_cmd_setup_basic_desc(&desc
,
4054 HCLGE_OPC_MAC_VLAN_ADD
,
4056 memcpy(desc
.data
, req
,
4057 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4058 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4059 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4060 retval
= le16_to_cpu(desc
.retval
);
4062 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
4064 HCLGE_MAC_VLAN_ADD
);
4066 hclge_cmd_reuse_desc(&mc_desc
[0], false);
4067 mc_desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4068 hclge_cmd_reuse_desc(&mc_desc
[1], false);
4069 mc_desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4070 hclge_cmd_reuse_desc(&mc_desc
[2], false);
4071 mc_desc
[2].flag
&= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT
);
4072 memcpy(mc_desc
[0].data
, req
,
4073 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
4074 ret
= hclge_cmd_send(&hdev
->hw
, mc_desc
, 3);
4075 resp_code
= (le32_to_cpu(mc_desc
[0].data
[0]) >> 8) & 0xff;
4076 retval
= le16_to_cpu(mc_desc
[0].retval
);
4078 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
4080 HCLGE_MAC_VLAN_ADD
);
4084 dev_err(&hdev
->pdev
->dev
,
4085 "add mac addr failed for cmd_send, ret =%d.\n",
4093 static int hclge_add_uc_addr(struct hnae3_handle
*handle
,
4094 const unsigned char *addr
)
4096 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4098 return hclge_add_uc_addr_common(vport
, addr
);
4101 int hclge_add_uc_addr_common(struct hclge_vport
*vport
,
4102 const unsigned char *addr
)
4104 struct hclge_dev
*hdev
= vport
->back
;
4105 struct hclge_mac_vlan_tbl_entry_cmd req
;
4106 enum hclge_cmd_status status
;
4107 u16 egress_port
= 0;
4109 /* mac addr check */
4110 if (is_zero_ether_addr(addr
) ||
4111 is_broadcast_ether_addr(addr
) ||
4112 is_multicast_ether_addr(addr
)) {
4113 dev_err(&hdev
->pdev
->dev
,
4114 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4116 is_zero_ether_addr(addr
),
4117 is_broadcast_ether_addr(addr
),
4118 is_multicast_ether_addr(addr
));
4122 memset(&req
, 0, sizeof(req
));
4123 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4124 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4125 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 0);
4126 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4128 hnae_set_bit(egress_port
, HCLGE_MAC_EPORT_SW_EN_B
, 0);
4129 hnae_set_bit(egress_port
, HCLGE_MAC_EPORT_TYPE_B
, 0);
4130 hnae_set_field(egress_port
, HCLGE_MAC_EPORT_VFID_M
,
4131 HCLGE_MAC_EPORT_VFID_S
, vport
->vport_id
);
4132 hnae_set_field(egress_port
, HCLGE_MAC_EPORT_PFID_M
,
4133 HCLGE_MAC_EPORT_PFID_S
, 0);
4135 req
.egress_port
= cpu_to_le16(egress_port
);
4137 hclge_prepare_mac_addr(&req
, addr
);
4139 status
= hclge_add_mac_vlan_tbl(vport
, &req
, NULL
);
4144 static int hclge_rm_uc_addr(struct hnae3_handle
*handle
,
4145 const unsigned char *addr
)
4147 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4149 return hclge_rm_uc_addr_common(vport
, addr
);
4152 int hclge_rm_uc_addr_common(struct hclge_vport
*vport
,
4153 const unsigned char *addr
)
4155 struct hclge_dev
*hdev
= vport
->back
;
4156 struct hclge_mac_vlan_tbl_entry_cmd req
;
4157 enum hclge_cmd_status status
;
4159 /* mac addr check */
4160 if (is_zero_ether_addr(addr
) ||
4161 is_broadcast_ether_addr(addr
) ||
4162 is_multicast_ether_addr(addr
)) {
4163 dev_dbg(&hdev
->pdev
->dev
,
4164 "Remove mac err! invalid mac:%pM.\n",
4169 memset(&req
, 0, sizeof(req
));
4170 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4171 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4172 hclge_prepare_mac_addr(&req
, addr
);
4173 status
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4178 static int hclge_add_mc_addr(struct hnae3_handle
*handle
,
4179 const unsigned char *addr
)
4181 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4183 return hclge_add_mc_addr_common(vport
, addr
);
4186 int hclge_add_mc_addr_common(struct hclge_vport
*vport
,
4187 const unsigned char *addr
)
4189 struct hclge_dev
*hdev
= vport
->back
;
4190 struct hclge_mac_vlan_tbl_entry_cmd req
;
4191 struct hclge_desc desc
[3];
4195 /* mac addr check */
4196 if (!is_multicast_ether_addr(addr
)) {
4197 dev_err(&hdev
->pdev
->dev
,
4198 "Add mc mac err! invalid mac:%pM.\n",
4202 memset(&req
, 0, sizeof(req
));
4203 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4204 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4205 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4206 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4207 hclge_prepare_mac_addr(&req
, addr
);
4208 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4210 /* This mac addr exist, update VFID for it */
4211 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4212 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4214 /* This mac addr do not exist, add new entry for it */
4215 memset(desc
[0].data
, 0, sizeof(desc
[0].data
));
4216 memset(desc
[1].data
, 0, sizeof(desc
[0].data
));
4217 memset(desc
[2].data
, 0, sizeof(desc
[0].data
));
4218 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4219 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4222 /* Set MTA table for this MAC address */
4223 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
4224 status
= hclge_set_mta_table_item(vport
, tbl_idx
, true);
4229 static int hclge_rm_mc_addr(struct hnae3_handle
*handle
,
4230 const unsigned char *addr
)
4232 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4234 return hclge_rm_mc_addr_common(vport
, addr
);
4237 int hclge_rm_mc_addr_common(struct hclge_vport
*vport
,
4238 const unsigned char *addr
)
4240 struct hclge_dev
*hdev
= vport
->back
;
4241 struct hclge_mac_vlan_tbl_entry_cmd req
;
4242 enum hclge_cmd_status status
;
4243 struct hclge_desc desc
[3];
4246 /* mac addr check */
4247 if (!is_multicast_ether_addr(addr
)) {
4248 dev_dbg(&hdev
->pdev
->dev
,
4249 "Remove mc mac err! invalid mac:%pM.\n",
4254 memset(&req
, 0, sizeof(req
));
4255 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4256 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4257 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4258 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4259 hclge_prepare_mac_addr(&req
, addr
);
4260 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4262 /* This mac addr exist, remove this handle's VFID for it */
4263 hclge_update_desc_vfid(desc
, vport
->vport_id
, true);
4265 if (hclge_is_all_function_id_zero(desc
))
4266 /* All the vfid is zero, so need to delete this entry */
4267 status
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4269 /* Not all the vfid is zero, update the vfid */
4270 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4273 /* This mac addr do not exist, can't delete it */
4274 dev_err(&hdev
->pdev
->dev
,
4275 "Rm multicast mac addr failed, ret = %d.\n",
4280 /* Set MTB table for this MAC address */
4281 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
4282 status
= hclge_set_mta_table_item(vport
, tbl_idx
, false);
4287 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev
*hdev
,
4288 u16 cmdq_resp
, u8 resp_code
)
4290 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4291 #define HCLGE_ETHERTYPE_ALREADY_ADD 1
4292 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4293 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4298 dev_err(&hdev
->pdev
->dev
,
4299 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4304 switch (resp_code
) {
4305 case HCLGE_ETHERTYPE_SUCCESS_ADD
:
4306 case HCLGE_ETHERTYPE_ALREADY_ADD
:
4309 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW
:
4310 dev_err(&hdev
->pdev
->dev
,
4311 "add mac ethertype failed for manager table overflow.\n");
4312 return_status
= -EIO
;
4314 case HCLGE_ETHERTYPE_KEY_CONFLICT
:
4315 dev_err(&hdev
->pdev
->dev
,
4316 "add mac ethertype failed for key conflict.\n");
4317 return_status
= -EIO
;
4320 dev_err(&hdev
->pdev
->dev
,
4321 "add mac ethertype failed for undefined, code=%d.\n",
4323 return_status
= -EIO
;
4326 return return_status
;
4329 static int hclge_add_mgr_tbl(struct hclge_dev
*hdev
,
4330 const struct hclge_mac_mgr_tbl_entry_cmd
*req
)
4332 struct hclge_desc desc
;
4337 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_ETHTYPE_ADD
, false);
4338 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_mgr_tbl_entry_cmd
));
4340 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4342 dev_err(&hdev
->pdev
->dev
,
4343 "add mac ethertype failed for cmd_send, ret =%d.\n",
4348 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
4349 retval
= le16_to_cpu(desc
.retval
);
4351 return hclge_get_mac_ethertype_cmd_status(hdev
, retval
, resp_code
);
4354 static int init_mgr_tbl(struct hclge_dev
*hdev
)
4359 for (i
= 0; i
< ARRAY_SIZE(hclge_mgr_table
); i
++) {
4360 ret
= hclge_add_mgr_tbl(hdev
, &hclge_mgr_table
[i
]);
4362 dev_err(&hdev
->pdev
->dev
,
4363 "add mac ethertype failed, ret =%d.\n",
4372 static void hclge_get_mac_addr(struct hnae3_handle
*handle
, u8
*p
)
4374 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4375 struct hclge_dev
*hdev
= vport
->back
;
4377 ether_addr_copy(p
, hdev
->hw
.mac
.mac_addr
);
4380 static int hclge_set_mac_addr(struct hnae3_handle
*handle
, void *p
)
4382 const unsigned char *new_addr
= (const unsigned char *)p
;
4383 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4384 struct hclge_dev
*hdev
= vport
->back
;
4387 /* mac addr check */
4388 if (is_zero_ether_addr(new_addr
) ||
4389 is_broadcast_ether_addr(new_addr
) ||
4390 is_multicast_ether_addr(new_addr
)) {
4391 dev_err(&hdev
->pdev
->dev
,
4392 "Change uc mac err! invalid mac:%p.\n",
4397 ret
= hclge_rm_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
);
4399 dev_warn(&hdev
->pdev
->dev
,
4400 "remove old uc mac address fail, ret =%d.\n",
4403 ret
= hclge_add_uc_addr(handle
, new_addr
);
4405 dev_err(&hdev
->pdev
->dev
,
4406 "add uc mac address fail, ret =%d.\n",
4409 ret
= hclge_add_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
);
4411 dev_err(&hdev
->pdev
->dev
,
4412 "restore uc mac address fail, ret =%d.\n",
4419 ret
= hclge_mac_pause_addr_cfg(hdev
, new_addr
);
4421 dev_err(&hdev
->pdev
->dev
,
4422 "configure mac pause address fail, ret =%d.\n",
4427 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, new_addr
);
4432 static int hclge_set_vlan_filter_ctrl(struct hclge_dev
*hdev
, u8 vlan_type
,
4435 struct hclge_vlan_filter_ctrl_cmd
*req
;
4436 struct hclge_desc desc
;
4439 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_CTRL
, false);
4441 req
= (struct hclge_vlan_filter_ctrl_cmd
*)desc
.data
;
4442 req
->vlan_type
= vlan_type
;
4443 req
->vlan_fe
= filter_en
;
4445 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4447 dev_err(&hdev
->pdev
->dev
, "set vlan filter fail, ret =%d.\n",
4455 #define HCLGE_FILTER_TYPE_VF 0
4456 #define HCLGE_FILTER_TYPE_PORT 1
4458 static void hclge_enable_vlan_filter(struct hnae3_handle
*handle
, bool enable
)
4460 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4461 struct hclge_dev
*hdev
= vport
->back
;
4463 hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, enable
);
4466 int hclge_set_vf_vlan_common(struct hclge_dev
*hdev
, int vfid
,
4467 bool is_kill
, u16 vlan
, u8 qos
, __be16 proto
)
4469 #define HCLGE_MAX_VF_BYTES 16
4470 struct hclge_vlan_filter_vf_cfg_cmd
*req0
;
4471 struct hclge_vlan_filter_vf_cfg_cmd
*req1
;
4472 struct hclge_desc desc
[2];
4477 hclge_cmd_setup_basic_desc(&desc
[0],
4478 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4479 hclge_cmd_setup_basic_desc(&desc
[1],
4480 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4482 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4484 vf_byte_off
= vfid
/ 8;
4485 vf_byte_val
= 1 << (vfid
% 8);
4487 req0
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[0].data
;
4488 req1
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[1].data
;
4490 req0
->vlan_id
= cpu_to_le16(vlan
);
4491 req0
->vlan_cfg
= is_kill
;
4493 if (vf_byte_off
< HCLGE_MAX_VF_BYTES
)
4494 req0
->vf_bitmap
[vf_byte_off
] = vf_byte_val
;
4496 req1
->vf_bitmap
[vf_byte_off
- HCLGE_MAX_VF_BYTES
] = vf_byte_val
;
4498 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
4500 dev_err(&hdev
->pdev
->dev
,
4501 "Send vf vlan command fail, ret =%d.\n",
4507 if (!req0
->resp_code
|| req0
->resp_code
== 1)
4510 dev_err(&hdev
->pdev
->dev
,
4511 "Add vf vlan filter fail, ret =%d.\n",
4514 if (!req0
->resp_code
)
4517 dev_err(&hdev
->pdev
->dev
,
4518 "Kill vf vlan filter fail, ret =%d.\n",
4525 static int hclge_set_port_vlan_filter(struct hnae3_handle
*handle
,
4526 __be16 proto
, u16 vlan_id
,
4529 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4530 struct hclge_dev
*hdev
= vport
->back
;
4531 struct hclge_vlan_filter_pf_cfg_cmd
*req
;
4532 struct hclge_desc desc
;
4533 u8 vlan_offset_byte_val
;
4534 u8 vlan_offset_byte
;
4538 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_PF_CFG
, false);
4540 vlan_offset_160
= vlan_id
/ 160;
4541 vlan_offset_byte
= (vlan_id
% 160) / 8;
4542 vlan_offset_byte_val
= 1 << (vlan_id
% 8);
4544 req
= (struct hclge_vlan_filter_pf_cfg_cmd
*)desc
.data
;
4545 req
->vlan_offset
= vlan_offset_160
;
4546 req
->vlan_cfg
= is_kill
;
4547 req
->vlan_offset_bitmap
[vlan_offset_byte
] = vlan_offset_byte_val
;
4549 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4551 dev_err(&hdev
->pdev
->dev
,
4552 "port vlan command, send fail, ret =%d.\n",
4557 ret
= hclge_set_vf_vlan_common(hdev
, 0, is_kill
, vlan_id
, 0, proto
);
4559 dev_err(&hdev
->pdev
->dev
,
4560 "Set pf vlan filter config fail, ret =%d.\n",
4568 static int hclge_set_vf_vlan_filter(struct hnae3_handle
*handle
, int vfid
,
4569 u16 vlan
, u8 qos
, __be16 proto
)
4571 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4572 struct hclge_dev
*hdev
= vport
->back
;
4574 if ((vfid
>= hdev
->num_alloc_vfs
) || (vlan
> 4095) || (qos
> 7))
4576 if (proto
!= htons(ETH_P_8021Q
))
4577 return -EPROTONOSUPPORT
;
4579 return hclge_set_vf_vlan_common(hdev
, vfid
, false, vlan
, qos
, proto
);
4582 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport
*vport
)
4584 struct hclge_tx_vtag_cfg
*vcfg
= &vport
->txvlan_cfg
;
4585 struct hclge_vport_vtag_tx_cfg_cmd
*req
;
4586 struct hclge_dev
*hdev
= vport
->back
;
4587 struct hclge_desc desc
;
4590 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_TX_CFG
, false);
4592 req
= (struct hclge_vport_vtag_tx_cfg_cmd
*)desc
.data
;
4593 req
->def_vlan_tag1
= cpu_to_le16(vcfg
->default_tag1
);
4594 req
->def_vlan_tag2
= cpu_to_le16(vcfg
->default_tag2
);
4595 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_TAG_B
,
4596 vcfg
->accept_tag
? 1 : 0);
4597 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_UNTAG_B
,
4598 vcfg
->accept_untag
? 1 : 0);
4599 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG1_EN_B
,
4600 vcfg
->insert_tag1_en
? 1 : 0);
4601 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG2_EN_B
,
4602 vcfg
->insert_tag2_en
? 1 : 0);
4603 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_CFG_NIC_ROCE_SEL_B
, 0);
4605 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4606 req
->vf_bitmap
[req
->vf_offset
] =
4607 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4609 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4611 dev_err(&hdev
->pdev
->dev
,
4612 "Send port txvlan cfg command fail, ret =%d\n",
4618 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport
*vport
)
4620 struct hclge_rx_vtag_cfg
*vcfg
= &vport
->rxvlan_cfg
;
4621 struct hclge_vport_vtag_rx_cfg_cmd
*req
;
4622 struct hclge_dev
*hdev
= vport
->back
;
4623 struct hclge_desc desc
;
4626 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_RX_CFG
, false);
4628 req
= (struct hclge_vport_vtag_rx_cfg_cmd
*)desc
.data
;
4629 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG1_EN_B
,
4630 vcfg
->strip_tag1_en
? 1 : 0);
4631 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG2_EN_B
,
4632 vcfg
->strip_tag2_en
? 1 : 0);
4633 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG1_EN_B
,
4634 vcfg
->vlan1_vlan_prionly
? 1 : 0);
4635 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG2_EN_B
,
4636 vcfg
->vlan2_vlan_prionly
? 1 : 0);
4638 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4639 req
->vf_bitmap
[req
->vf_offset
] =
4640 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4642 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4644 dev_err(&hdev
->pdev
->dev
,
4645 "Send port rxvlan cfg command fail, ret =%d\n",
4651 static int hclge_set_vlan_protocol_type(struct hclge_dev
*hdev
)
4653 struct hclge_rx_vlan_type_cfg_cmd
*rx_req
;
4654 struct hclge_tx_vlan_type_cfg_cmd
*tx_req
;
4655 struct hclge_desc desc
;
4658 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_TYPE_ID
, false);
4659 rx_req
= (struct hclge_rx_vlan_type_cfg_cmd
*)desc
.data
;
4660 rx_req
->ot_fst_vlan_type
=
4661 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
);
4662 rx_req
->ot_sec_vlan_type
=
4663 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
);
4664 rx_req
->in_fst_vlan_type
=
4665 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
);
4666 rx_req
->in_sec_vlan_type
=
4667 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
);
4669 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4671 dev_err(&hdev
->pdev
->dev
,
4672 "Send rxvlan protocol type command fail, ret =%d\n",
4677 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_INSERT
, false);
4679 tx_req
= (struct hclge_tx_vlan_type_cfg_cmd
*)&desc
.data
;
4680 tx_req
->ot_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_ot_vlan_type
);
4681 tx_req
->in_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_in_vlan_type
);
4683 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4685 dev_err(&hdev
->pdev
->dev
,
4686 "Send txvlan protocol type command fail, ret =%d\n",
4692 static int hclge_init_vlan_config(struct hclge_dev
*hdev
)
4694 #define HCLGE_DEF_VLAN_TYPE 0x8100
4696 struct hnae3_handle
*handle
;
4697 struct hclge_vport
*vport
;
4701 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, true);
4705 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_PORT
, true);
4709 hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4710 hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4711 hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4712 hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4713 hdev
->vlan_type_cfg
.tx_ot_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4714 hdev
->vlan_type_cfg
.tx_in_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4716 ret
= hclge_set_vlan_protocol_type(hdev
);
4720 for (i
= 0; i
< hdev
->num_alloc_vport
; i
++) {
4721 vport
= &hdev
->vport
[i
];
4722 vport
->txvlan_cfg
.accept_tag
= true;
4723 vport
->txvlan_cfg
.accept_untag
= true;
4724 vport
->txvlan_cfg
.insert_tag1_en
= false;
4725 vport
->txvlan_cfg
.insert_tag2_en
= false;
4726 vport
->txvlan_cfg
.default_tag1
= 0;
4727 vport
->txvlan_cfg
.default_tag2
= 0;
4729 ret
= hclge_set_vlan_tx_offload_cfg(vport
);
4733 vport
->rxvlan_cfg
.strip_tag1_en
= false;
4734 vport
->rxvlan_cfg
.strip_tag2_en
= true;
4735 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
4736 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
4738 ret
= hclge_set_vlan_rx_offload_cfg(vport
);
4743 handle
= &hdev
->vport
[0].nic
;
4744 return hclge_set_port_vlan_filter(handle
, htons(ETH_P_8021Q
), 0, false);
4747 static int hclge_en_hw_strip_rxvtag(struct hnae3_handle
*handle
, bool enable
)
4749 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4751 vport
->rxvlan_cfg
.strip_tag1_en
= false;
4752 vport
->rxvlan_cfg
.strip_tag2_en
= enable
;
4753 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
4754 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
4756 return hclge_set_vlan_rx_offload_cfg(vport
);
4759 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
)
4761 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4762 struct hclge_config_max_frm_size_cmd
*req
;
4763 struct hclge_dev
*hdev
= vport
->back
;
4764 struct hclge_desc desc
;
4768 max_frm_size
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
;
4770 if (max_frm_size
< HCLGE_MAC_MIN_FRAME
||
4771 max_frm_size
> HCLGE_MAC_MAX_FRAME
)
4774 max_frm_size
= max(max_frm_size
, HCLGE_MAC_DEFAULT_FRAME
);
4776 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAX_FRM_SIZE
, false);
4778 req
= (struct hclge_config_max_frm_size_cmd
*)desc
.data
;
4779 req
->max_frm_size
= cpu_to_le16(max_frm_size
);
4781 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4783 dev_err(&hdev
->pdev
->dev
, "set mtu fail, ret =%d.\n", ret
);
4787 hdev
->mps
= max_frm_size
;
4792 static int hclge_send_reset_tqp_cmd(struct hclge_dev
*hdev
, u16 queue_id
,
4795 struct hclge_reset_tqp_queue_cmd
*req
;
4796 struct hclge_desc desc
;
4799 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, false);
4801 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
4802 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
4803 hnae_set_bit(req
->reset_req
, HCLGE_TQP_RESET_B
, enable
);
4805 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4807 dev_err(&hdev
->pdev
->dev
,
4808 "Send tqp reset cmd error, status =%d\n", ret
);
4815 static int hclge_get_reset_status(struct hclge_dev
*hdev
, u16 queue_id
)
4817 struct hclge_reset_tqp_queue_cmd
*req
;
4818 struct hclge_desc desc
;
4821 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, true);
4823 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
4824 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
4826 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4828 dev_err(&hdev
->pdev
->dev
,
4829 "Get reset status error, status =%d\n", ret
);
4833 return hnae_get_bit(req
->ready_to_reset
, HCLGE_TQP_RESET_B
);
4836 static u16
hclge_covert_handle_qid_global(struct hnae3_handle
*handle
,
4839 struct hnae3_queue
*queue
;
4840 struct hclge_tqp
*tqp
;
4842 queue
= handle
->kinfo
.tqp
[queue_id
];
4843 tqp
= container_of(queue
, struct hclge_tqp
, q
);
4848 void hclge_reset_tqp(struct hnae3_handle
*handle
, u16 queue_id
)
4850 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4851 struct hclge_dev
*hdev
= vport
->back
;
4852 int reset_try_times
= 0;
4857 queue_gid
= hclge_covert_handle_qid_global(handle
, queue_id
);
4859 ret
= hclge_tqp_enable(hdev
, queue_id
, 0, false);
4861 dev_warn(&hdev
->pdev
->dev
, "Disable tqp fail, ret = %d\n", ret
);
4865 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, true);
4867 dev_warn(&hdev
->pdev
->dev
,
4868 "Send reset tqp cmd fail, ret = %d\n", ret
);
4872 reset_try_times
= 0;
4873 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
4874 /* Wait for tqp hw reset */
4876 reset_status
= hclge_get_reset_status(hdev
, queue_gid
);
4881 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
4882 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
4886 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_gid
, false);
4888 dev_warn(&hdev
->pdev
->dev
,
4889 "Deassert the soft reset fail, ret = %d\n", ret
);
4894 static u32
hclge_get_fw_version(struct hnae3_handle
*handle
)
4896 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4897 struct hclge_dev
*hdev
= vport
->back
;
4899 return hdev
->fw_version
;
4902 static void hclge_get_flowctrl_adv(struct hnae3_handle
*handle
,
4905 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4906 struct hclge_dev
*hdev
= vport
->back
;
4907 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
4912 *flowctrl_adv
|= (phydev
->advertising
& ADVERTISED_Pause
) |
4913 (phydev
->advertising
& ADVERTISED_Asym_Pause
);
4916 static void hclge_set_flowctrl_adv(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
4918 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
4923 phydev
->advertising
&= ~(ADVERTISED_Pause
| ADVERTISED_Asym_Pause
);
4926 phydev
->advertising
|= ADVERTISED_Pause
| ADVERTISED_Asym_Pause
;
4929 phydev
->advertising
^= ADVERTISED_Asym_Pause
;
4932 static int hclge_cfg_pauseparam(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
4937 hdev
->fc_mode_last_time
= HCLGE_FC_FULL
;
4938 else if (rx_en
&& !tx_en
)
4939 hdev
->fc_mode_last_time
= HCLGE_FC_RX_PAUSE
;
4940 else if (!rx_en
&& tx_en
)
4941 hdev
->fc_mode_last_time
= HCLGE_FC_TX_PAUSE
;
4943 hdev
->fc_mode_last_time
= HCLGE_FC_NONE
;
4945 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
)
4948 ret
= hclge_mac_pause_en_cfg(hdev
, tx_en
, rx_en
);
4950 dev_err(&hdev
->pdev
->dev
, "configure pauseparam error, ret = %d.\n",
4955 hdev
->tm_info
.fc_mode
= hdev
->fc_mode_last_time
;
4960 int hclge_cfg_flowctrl(struct hclge_dev
*hdev
)
4962 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
4963 u16 remote_advertising
= 0;
4964 u16 local_advertising
= 0;
4965 u32 rx_pause
, tx_pause
;
4968 if (!phydev
->link
|| !phydev
->autoneg
)
4971 if (phydev
->advertising
& ADVERTISED_Pause
)
4972 local_advertising
= ADVERTISE_PAUSE_CAP
;
4974 if (phydev
->advertising
& ADVERTISED_Asym_Pause
)
4975 local_advertising
|= ADVERTISE_PAUSE_ASYM
;
4978 remote_advertising
= LPA_PAUSE_CAP
;
4980 if (phydev
->asym_pause
)
4981 remote_advertising
|= LPA_PAUSE_ASYM
;
4983 flowctl
= mii_resolve_flowctrl_fdx(local_advertising
,
4984 remote_advertising
);
4985 tx_pause
= flowctl
& FLOW_CTRL_TX
;
4986 rx_pause
= flowctl
& FLOW_CTRL_RX
;
4988 if (phydev
->duplex
== HCLGE_MAC_HALF
) {
4993 return hclge_cfg_pauseparam(hdev
, rx_pause
, tx_pause
);
4996 static void hclge_get_pauseparam(struct hnae3_handle
*handle
, u32
*auto_neg
,
4997 u32
*rx_en
, u32
*tx_en
)
4999 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5000 struct hclge_dev
*hdev
= vport
->back
;
5002 *auto_neg
= hclge_get_autoneg(handle
);
5004 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
5010 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_RX_PAUSE
) {
5013 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_TX_PAUSE
) {
5016 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_FULL
) {
5025 static int hclge_set_pauseparam(struct hnae3_handle
*handle
, u32 auto_neg
,
5026 u32 rx_en
, u32 tx_en
)
5028 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5029 struct hclge_dev
*hdev
= vport
->back
;
5030 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5033 /* Only support flow control negotiation for netdev with
5034 * phy attached for now.
5039 fc_autoneg
= hclge_get_autoneg(handle
);
5040 if (auto_neg
!= fc_autoneg
) {
5041 dev_info(&hdev
->pdev
->dev
,
5042 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5046 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
5047 dev_info(&hdev
->pdev
->dev
,
5048 "Priority flow control enabled. Cannot set link flow control.\n");
5052 hclge_set_flowctrl_adv(hdev
, rx_en
, tx_en
);
5055 return hclge_cfg_pauseparam(hdev
, rx_en
, tx_en
);
5057 return phy_start_aneg(phydev
);
5060 static void hclge_get_ksettings_an_result(struct hnae3_handle
*handle
,
5061 u8
*auto_neg
, u32
*speed
, u8
*duplex
)
5063 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5064 struct hclge_dev
*hdev
= vport
->back
;
5067 *speed
= hdev
->hw
.mac
.speed
;
5069 *duplex
= hdev
->hw
.mac
.duplex
;
5071 *auto_neg
= hdev
->hw
.mac
.autoneg
;
5074 static void hclge_get_media_type(struct hnae3_handle
*handle
, u8
*media_type
)
5076 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5077 struct hclge_dev
*hdev
= vport
->back
;
5080 *media_type
= hdev
->hw
.mac
.media_type
;
5083 static void hclge_get_mdix_mode(struct hnae3_handle
*handle
,
5084 u8
*tp_mdix_ctrl
, u8
*tp_mdix
)
5086 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5087 struct hclge_dev
*hdev
= vport
->back
;
5088 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5089 int mdix_ctrl
, mdix
, retval
, is_resolved
;
5092 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
5093 *tp_mdix
= ETH_TP_MDI_INVALID
;
5097 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_MDIX
);
5099 retval
= phy_read(phydev
, HCLGE_PHY_CSC_REG
);
5100 mdix_ctrl
= hnae_get_field(retval
, HCLGE_PHY_MDIX_CTRL_M
,
5101 HCLGE_PHY_MDIX_CTRL_S
);
5103 retval
= phy_read(phydev
, HCLGE_PHY_CSS_REG
);
5104 mdix
= hnae_get_bit(retval
, HCLGE_PHY_MDIX_STATUS_B
);
5105 is_resolved
= hnae_get_bit(retval
, HCLGE_PHY_SPEED_DUP_RESOLVE_B
);
5107 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_COPPER
);
5109 switch (mdix_ctrl
) {
5111 *tp_mdix_ctrl
= ETH_TP_MDI
;
5114 *tp_mdix_ctrl
= ETH_TP_MDI_X
;
5117 *tp_mdix_ctrl
= ETH_TP_MDI_AUTO
;
5120 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
5125 *tp_mdix
= ETH_TP_MDI_INVALID
;
5127 *tp_mdix
= ETH_TP_MDI_X
;
5129 *tp_mdix
= ETH_TP_MDI
;
5132 static int hclge_init_client_instance(struct hnae3_client
*client
,
5133 struct hnae3_ae_dev
*ae_dev
)
5135 struct hclge_dev
*hdev
= ae_dev
->priv
;
5136 struct hclge_vport
*vport
;
5139 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
5140 vport
= &hdev
->vport
[i
];
5142 switch (client
->type
) {
5143 case HNAE3_CLIENT_KNIC
:
5145 hdev
->nic_client
= client
;
5146 vport
->nic
.client
= client
;
5147 ret
= client
->ops
->init_instance(&vport
->nic
);
5151 if (hdev
->roce_client
&&
5152 hnae3_dev_roce_supported(hdev
)) {
5153 struct hnae3_client
*rc
= hdev
->roce_client
;
5155 ret
= hclge_init_roce_base_info(vport
);
5159 ret
= rc
->ops
->init_instance(&vport
->roce
);
5165 case HNAE3_CLIENT_UNIC
:
5166 hdev
->nic_client
= client
;
5167 vport
->nic
.client
= client
;
5169 ret
= client
->ops
->init_instance(&vport
->nic
);
5174 case HNAE3_CLIENT_ROCE
:
5175 if (hnae3_dev_roce_supported(hdev
)) {
5176 hdev
->roce_client
= client
;
5177 vport
->roce
.client
= client
;
5180 if (hdev
->roce_client
&& hdev
->nic_client
) {
5181 ret
= hclge_init_roce_base_info(vport
);
5185 ret
= client
->ops
->init_instance(&vport
->roce
);
5197 static void hclge_uninit_client_instance(struct hnae3_client
*client
,
5198 struct hnae3_ae_dev
*ae_dev
)
5200 struct hclge_dev
*hdev
= ae_dev
->priv
;
5201 struct hclge_vport
*vport
;
5204 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
5205 vport
= &hdev
->vport
[i
];
5206 if (hdev
->roce_client
) {
5207 hdev
->roce_client
->ops
->uninit_instance(&vport
->roce
,
5209 hdev
->roce_client
= NULL
;
5210 vport
->roce
.client
= NULL
;
5212 if (client
->type
== HNAE3_CLIENT_ROCE
)
5214 if (client
->ops
->uninit_instance
) {
5215 client
->ops
->uninit_instance(&vport
->nic
, 0);
5216 hdev
->nic_client
= NULL
;
5217 vport
->nic
.client
= NULL
;
5222 static int hclge_pci_init(struct hclge_dev
*hdev
)
5224 struct pci_dev
*pdev
= hdev
->pdev
;
5225 struct hclge_hw
*hw
;
5228 ret
= pci_enable_device(pdev
);
5230 dev_err(&pdev
->dev
, "failed to enable PCI device\n");
5231 goto err_no_drvdata
;
5234 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64));
5236 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32));
5239 "can't set consistent PCI DMA");
5240 goto err_disable_device
;
5242 dev_warn(&pdev
->dev
, "set DMA mask to 32 bits\n");
5245 ret
= pci_request_regions(pdev
, HCLGE_DRIVER_NAME
);
5247 dev_err(&pdev
->dev
, "PCI request regions failed %d\n", ret
);
5248 goto err_disable_device
;
5251 pci_set_master(pdev
);
5254 hw
->io_base
= pcim_iomap(pdev
, 2, 0);
5256 dev_err(&pdev
->dev
, "Can't map configuration register space\n");
5258 goto err_clr_master
;
5261 hdev
->num_req_vfs
= pci_sriov_get_totalvfs(pdev
);
5265 pci_clear_master(pdev
);
5266 pci_release_regions(pdev
);
5268 pci_disable_device(pdev
);
5270 pci_set_drvdata(pdev
, NULL
);
5275 static void hclge_pci_uninit(struct hclge_dev
*hdev
)
5277 struct pci_dev
*pdev
= hdev
->pdev
;
5279 pci_free_irq_vectors(pdev
);
5280 pci_clear_master(pdev
);
5281 pci_release_mem_regions(pdev
);
5282 pci_disable_device(pdev
);
5285 static int hclge_init_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5287 struct pci_dev
*pdev
= ae_dev
->pdev
;
5288 struct hclge_dev
*hdev
;
5291 hdev
= devm_kzalloc(&pdev
->dev
, sizeof(*hdev
), GFP_KERNEL
);
5298 hdev
->ae_dev
= ae_dev
;
5299 hdev
->reset_type
= HNAE3_NONE_RESET
;
5300 hdev
->reset_request
= 0;
5301 hdev
->reset_pending
= 0;
5302 ae_dev
->priv
= hdev
;
5304 ret
= hclge_pci_init(hdev
);
5306 dev_err(&pdev
->dev
, "PCI init failed\n");
5310 /* Firmware command queue initialize */
5311 ret
= hclge_cmd_queue_init(hdev
);
5313 dev_err(&pdev
->dev
, "Cmd queue init failed, ret = %d.\n", ret
);
5317 /* Firmware command initialize */
5318 ret
= hclge_cmd_init(hdev
);
5322 ret
= hclge_get_cap(hdev
);
5324 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5329 ret
= hclge_configure(hdev
);
5331 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5335 ret
= hclge_init_msi(hdev
);
5337 dev_err(&pdev
->dev
, "Init MSI/MSI-X error, ret = %d.\n", ret
);
5341 ret
= hclge_misc_irq_init(hdev
);
5344 "Misc IRQ(vector0) init error, ret = %d.\n",
5349 ret
= hclge_alloc_tqps(hdev
);
5351 dev_err(&pdev
->dev
, "Allocate TQPs error, ret = %d.\n", ret
);
5355 ret
= hclge_alloc_vport(hdev
);
5357 dev_err(&pdev
->dev
, "Allocate vport error, ret = %d.\n", ret
);
5361 ret
= hclge_map_tqp(hdev
);
5363 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5367 ret
= hclge_mac_mdio_config(hdev
);
5369 dev_warn(&hdev
->pdev
->dev
,
5370 "mdio config fail ret=%d\n", ret
);
5374 ret
= hclge_mac_init(hdev
);
5376 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5379 ret
= hclge_buffer_alloc(hdev
);
5381 dev_err(&pdev
->dev
, "Buffer allocate fail, ret =%d\n", ret
);
5385 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5387 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5391 ret
= hclge_init_vlan_config(hdev
);
5393 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5397 ret
= hclge_tm_schd_init(hdev
);
5399 dev_err(&pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5403 ret
= hclge_rss_init_hw(hdev
);
5405 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5409 ret
= init_mgr_tbl(hdev
);
5411 dev_err(&pdev
->dev
, "manager table init fail, ret =%d\n", ret
);
5415 hclge_dcb_ops_set(hdev
);
5417 timer_setup(&hdev
->service_timer
, hclge_service_timer
, 0);
5418 INIT_WORK(&hdev
->service_task
, hclge_service_task
);
5419 INIT_WORK(&hdev
->rst_service_task
, hclge_reset_service_task
);
5420 INIT_WORK(&hdev
->mbx_service_task
, hclge_mailbox_service_task
);
5422 /* Enable MISC vector(vector0) */
5423 hclge_enable_vector(&hdev
->misc_vector
, true);
5425 set_bit(HCLGE_STATE_SERVICE_INITED
, &hdev
->state
);
5426 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5427 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
5428 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
5429 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
5430 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
5432 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME
);
5436 pci_release_regions(pdev
);
5438 pci_set_drvdata(pdev
, NULL
);
5443 static void hclge_stats_clear(struct hclge_dev
*hdev
)
5445 memset(&hdev
->hw_stats
, 0, sizeof(hdev
->hw_stats
));
5448 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5450 struct hclge_dev
*hdev
= ae_dev
->priv
;
5451 struct pci_dev
*pdev
= ae_dev
->pdev
;
5454 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5456 hclge_stats_clear(hdev
);
5458 ret
= hclge_cmd_init(hdev
);
5460 dev_err(&pdev
->dev
, "Cmd queue init failed\n");
5464 ret
= hclge_get_cap(hdev
);
5466 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5471 ret
= hclge_configure(hdev
);
5473 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5477 ret
= hclge_map_tqp(hdev
);
5479 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5483 ret
= hclge_mac_init(hdev
);
5485 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5489 ret
= hclge_buffer_alloc(hdev
);
5491 dev_err(&pdev
->dev
, "Buffer allocate fail, ret =%d\n", ret
);
5495 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5497 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5501 ret
= hclge_init_vlan_config(hdev
);
5503 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5507 ret
= hclge_tm_schd_init(hdev
);
5509 dev_err(&pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5513 ret
= hclge_rss_init_hw(hdev
);
5515 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5519 /* Enable MISC vector(vector0) */
5520 hclge_enable_vector(&hdev
->misc_vector
, true);
5522 dev_info(&pdev
->dev
, "Reset done, %s driver initialization finished.\n",
5528 static void hclge_uninit_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5530 struct hclge_dev
*hdev
= ae_dev
->priv
;
5531 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
5533 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5535 if (IS_ENABLED(CONFIG_PCI_IOV
))
5536 hclge_disable_sriov(hdev
);
5538 if (hdev
->service_timer
.function
)
5539 del_timer_sync(&hdev
->service_timer
);
5540 if (hdev
->service_task
.func
)
5541 cancel_work_sync(&hdev
->service_task
);
5542 if (hdev
->rst_service_task
.func
)
5543 cancel_work_sync(&hdev
->rst_service_task
);
5544 if (hdev
->mbx_service_task
.func
)
5545 cancel_work_sync(&hdev
->mbx_service_task
);
5548 mdiobus_unregister(mac
->mdio_bus
);
5550 /* Disable MISC vector(vector0) */
5551 hclge_enable_vector(&hdev
->misc_vector
, false);
5552 hclge_destroy_cmd_queue(&hdev
->hw
);
5553 hclge_misc_irq_uninit(hdev
);
5554 hclge_pci_uninit(hdev
);
5555 ae_dev
->priv
= NULL
;
5558 static u32
hclge_get_max_channels(struct hnae3_handle
*handle
)
5560 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
5561 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5562 struct hclge_dev
*hdev
= vport
->back
;
5564 return min_t(u32
, hdev
->rss_size_max
* kinfo
->num_tc
, hdev
->num_tqps
);
5567 static void hclge_get_channels(struct hnae3_handle
*handle
,
5568 struct ethtool_channels
*ch
)
5570 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5572 ch
->max_combined
= hclge_get_max_channels(handle
);
5573 ch
->other_count
= 1;
5575 ch
->combined_count
= vport
->alloc_tqps
;
5578 static void hclge_get_tqps_and_rss_info(struct hnae3_handle
*handle
,
5579 u16
*free_tqps
, u16
*max_rss_size
)
5581 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5582 struct hclge_dev
*hdev
= vport
->back
;
5586 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
5587 if (!hdev
->htqp
[i
].alloced
)
5590 *free_tqps
= temp_tqps
;
5591 *max_rss_size
= hdev
->rss_size_max
;
5594 static void hclge_release_tqp(struct hclge_vport
*vport
)
5596 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5597 struct hclge_dev
*hdev
= vport
->back
;
5600 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
5601 struct hclge_tqp
*tqp
=
5602 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
5604 tqp
->q
.handle
= NULL
;
5605 tqp
->q
.tqp_index
= 0;
5606 tqp
->alloced
= false;
5609 devm_kfree(&hdev
->pdev
->dev
, kinfo
->tqp
);
5613 static int hclge_set_channels(struct hnae3_handle
*handle
, u32 new_tqps_num
)
5615 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5616 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5617 struct hclge_dev
*hdev
= vport
->back
;
5618 int cur_rss_size
= kinfo
->rss_size
;
5619 int cur_tqps
= kinfo
->num_tqps
;
5620 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
5621 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
5622 u16 tc_size
[HCLGE_MAX_TC_NUM
];
5627 hclge_release_tqp(vport
);
5629 ret
= hclge_knic_setup(vport
, new_tqps_num
);
5631 dev_err(&hdev
->pdev
->dev
, "setup nic fail, ret =%d\n", ret
);
5635 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
5637 dev_err(&hdev
->pdev
->dev
, "map vport tqp fail, ret =%d\n", ret
);
5641 ret
= hclge_tm_schd_init(hdev
);
5643 dev_err(&hdev
->pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5647 roundup_size
= roundup_pow_of_two(kinfo
->rss_size
);
5648 roundup_size
= ilog2(roundup_size
);
5649 /* Set the RSS TC mode according to the new RSS size */
5650 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
5653 if (!(hdev
->hw_tc_map
& BIT(i
)))
5657 tc_size
[i
] = roundup_size
;
5658 tc_offset
[i
] = kinfo
->rss_size
* i
;
5660 ret
= hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
5664 /* Reinitializes the rss indirect table according to the new RSS size */
5665 rss_indir
= kcalloc(HCLGE_RSS_IND_TBL_SIZE
, sizeof(u32
), GFP_KERNEL
);
5669 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
5670 rss_indir
[i
] = i
% kinfo
->rss_size
;
5672 ret
= hclge_set_rss(handle
, rss_indir
, NULL
, 0);
5674 dev_err(&hdev
->pdev
->dev
, "set rss indir table fail, ret=%d\n",
5680 dev_info(&hdev
->pdev
->dev
,
5681 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5682 cur_rss_size
, kinfo
->rss_size
,
5683 cur_tqps
, kinfo
->rss_size
* kinfo
->num_tc
);
5688 static int hclge_get_regs_num(struct hclge_dev
*hdev
, u32
*regs_num_32_bit
,
5689 u32
*regs_num_64_bit
)
5691 struct hclge_desc desc
;
5695 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_REG_NUM
, true);
5696 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5698 dev_err(&hdev
->pdev
->dev
,
5699 "Query register number cmd failed, ret = %d.\n", ret
);
5703 *regs_num_32_bit
= le32_to_cpu(desc
.data
[0]);
5704 *regs_num_64_bit
= le32_to_cpu(desc
.data
[1]);
5706 total_num
= *regs_num_32_bit
+ *regs_num_64_bit
;
5713 static int hclge_get_32_bit_regs(struct hclge_dev
*hdev
, u32 regs_num
,
5716 #define HCLGE_32_BIT_REG_RTN_DATANUM 8
5718 struct hclge_desc
*desc
;
5719 u32
*reg_val
= data
;
5728 cmd_num
= DIV_ROUND_UP(regs_num
+ 2, HCLGE_32_BIT_REG_RTN_DATANUM
);
5729 desc
= kcalloc(cmd_num
, sizeof(struct hclge_desc
), GFP_KERNEL
);
5733 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_QUERY_32_BIT_REG
, true);
5734 ret
= hclge_cmd_send(&hdev
->hw
, desc
, cmd_num
);
5736 dev_err(&hdev
->pdev
->dev
,
5737 "Query 32 bit register cmd failed, ret = %d.\n", ret
);
5742 for (i
= 0; i
< cmd_num
; i
++) {
5744 desc_data
= (__le32
*)(&desc
[i
].data
[0]);
5745 n
= HCLGE_32_BIT_REG_RTN_DATANUM
- 2;
5747 desc_data
= (__le32
*)(&desc
[i
]);
5748 n
= HCLGE_32_BIT_REG_RTN_DATANUM
;
5750 for (k
= 0; k
< n
; k
++) {
5751 *reg_val
++ = le32_to_cpu(*desc_data
++);
5763 static int hclge_get_64_bit_regs(struct hclge_dev
*hdev
, u32 regs_num
,
5766 #define HCLGE_64_BIT_REG_RTN_DATANUM 4
5768 struct hclge_desc
*desc
;
5769 u64
*reg_val
= data
;
5778 cmd_num
= DIV_ROUND_UP(regs_num
+ 1, HCLGE_64_BIT_REG_RTN_DATANUM
);
5779 desc
= kcalloc(cmd_num
, sizeof(struct hclge_desc
), GFP_KERNEL
);
5783 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_QUERY_64_BIT_REG
, true);
5784 ret
= hclge_cmd_send(&hdev
->hw
, desc
, cmd_num
);
5786 dev_err(&hdev
->pdev
->dev
,
5787 "Query 64 bit register cmd failed, ret = %d.\n", ret
);
5792 for (i
= 0; i
< cmd_num
; i
++) {
5794 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
5795 n
= HCLGE_64_BIT_REG_RTN_DATANUM
- 1;
5797 desc_data
= (__le64
*)(&desc
[i
]);
5798 n
= HCLGE_64_BIT_REG_RTN_DATANUM
;
5800 for (k
= 0; k
< n
; k
++) {
5801 *reg_val
++ = le64_to_cpu(*desc_data
++);
5813 static int hclge_get_regs_len(struct hnae3_handle
*handle
)
5815 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5816 struct hclge_dev
*hdev
= vport
->back
;
5817 u32 regs_num_32_bit
, regs_num_64_bit
;
5820 ret
= hclge_get_regs_num(hdev
, ®s_num_32_bit
, ®s_num_64_bit
);
5822 dev_err(&hdev
->pdev
->dev
,
5823 "Get register number failed, ret = %d.\n", ret
);
5827 return regs_num_32_bit
* sizeof(u32
) + regs_num_64_bit
* sizeof(u64
);
5830 static void hclge_get_regs(struct hnae3_handle
*handle
, u32
*version
,
5833 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5834 struct hclge_dev
*hdev
= vport
->back
;
5835 u32 regs_num_32_bit
, regs_num_64_bit
;
5838 *version
= hdev
->fw_version
;
5840 ret
= hclge_get_regs_num(hdev
, ®s_num_32_bit
, ®s_num_64_bit
);
5842 dev_err(&hdev
->pdev
->dev
,
5843 "Get register number failed, ret = %d.\n", ret
);
5847 ret
= hclge_get_32_bit_regs(hdev
, regs_num_32_bit
, data
);
5849 dev_err(&hdev
->pdev
->dev
,
5850 "Get 32 bit register failed, ret = %d.\n", ret
);
5854 data
= (u32
*)data
+ regs_num_32_bit
;
5855 ret
= hclge_get_64_bit_regs(hdev
, regs_num_64_bit
,
5858 dev_err(&hdev
->pdev
->dev
,
5859 "Get 64 bit register failed, ret = %d.\n", ret
);
5862 static int hclge_set_led_status_sfp(struct hclge_dev
*hdev
, u8 speed_led_status
,
5863 u8 act_led_status
, u8 link_led_status
,
5864 u8 locate_led_status
)
5866 struct hclge_set_led_state_cmd
*req
;
5867 struct hclge_desc desc
;
5870 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_LED_STATUS_CFG
, false);
5872 req
= (struct hclge_set_led_state_cmd
*)desc
.data
;
5873 hnae_set_field(req
->port_speed_led_config
, HCLGE_LED_PORT_SPEED_STATE_M
,
5874 HCLGE_LED_PORT_SPEED_STATE_S
, speed_led_status
);
5875 hnae_set_field(req
->link_led_config
, HCLGE_LED_ACTIVITY_STATE_M
,
5876 HCLGE_LED_ACTIVITY_STATE_S
, act_led_status
);
5877 hnae_set_field(req
->activity_led_config
, HCLGE_LED_LINK_STATE_M
,
5878 HCLGE_LED_LINK_STATE_S
, link_led_status
);
5879 hnae_set_field(req
->locate_led_config
, HCLGE_LED_LOCATE_STATE_M
,
5880 HCLGE_LED_LOCATE_STATE_S
, locate_led_status
);
5882 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
5884 dev_err(&hdev
->pdev
->dev
,
5885 "Send set led state cmd error, ret =%d\n", ret
);
5890 enum hclge_led_status
{
5893 HCLGE_LED_NO_CHANGE
= 0xFF,
5896 static int hclge_set_led_id(struct hnae3_handle
*handle
,
5897 enum ethtool_phys_id_state status
)
5899 #define BLINK_FREQUENCY 2
5900 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5901 struct hclge_dev
*hdev
= vport
->back
;
5902 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
5905 if (phydev
|| hdev
->hw
.mac
.media_type
!= HNAE3_MEDIA_TYPE_FIBER
)
5909 case ETHTOOL_ID_ACTIVE
:
5910 ret
= hclge_set_led_status_sfp(hdev
,
5911 HCLGE_LED_NO_CHANGE
,
5912 HCLGE_LED_NO_CHANGE
,
5913 HCLGE_LED_NO_CHANGE
,
5916 case ETHTOOL_ID_INACTIVE
:
5917 ret
= hclge_set_led_status_sfp(hdev
,
5918 HCLGE_LED_NO_CHANGE
,
5919 HCLGE_LED_NO_CHANGE
,
5920 HCLGE_LED_NO_CHANGE
,
5931 enum hclge_led_port_speed
{
5932 HCLGE_SPEED_LED_FOR_1G
,
5933 HCLGE_SPEED_LED_FOR_10G
,
5934 HCLGE_SPEED_LED_FOR_25G
,
5935 HCLGE_SPEED_LED_FOR_40G
,
5936 HCLGE_SPEED_LED_FOR_50G
,
5937 HCLGE_SPEED_LED_FOR_100G
,
5940 static u8
hclge_led_get_speed_status(u32 speed
)
5945 case HCLGE_MAC_SPEED_1G
:
5946 speed_led
= HCLGE_SPEED_LED_FOR_1G
;
5948 case HCLGE_MAC_SPEED_10G
:
5949 speed_led
= HCLGE_SPEED_LED_FOR_10G
;
5951 case HCLGE_MAC_SPEED_25G
:
5952 speed_led
= HCLGE_SPEED_LED_FOR_25G
;
5954 case HCLGE_MAC_SPEED_40G
:
5955 speed_led
= HCLGE_SPEED_LED_FOR_40G
;
5957 case HCLGE_MAC_SPEED_50G
:
5958 speed_led
= HCLGE_SPEED_LED_FOR_50G
;
5960 case HCLGE_MAC_SPEED_100G
:
5961 speed_led
= HCLGE_SPEED_LED_FOR_100G
;
5964 speed_led
= HCLGE_LED_NO_CHANGE
;
5970 static int hclge_update_led_status(struct hclge_dev
*hdev
)
5972 u8 port_speed_status
, link_status
, activity_status
;
5973 u64 rx_pkts
, tx_pkts
;
5975 if (hdev
->hw
.mac
.media_type
!= HNAE3_MEDIA_TYPE_FIBER
)
5978 port_speed_status
= hclge_led_get_speed_status(hdev
->hw
.mac
.speed
);
5980 rx_pkts
= hdev
->hw_stats
.mac_stats
.mac_rx_total_pkt_num
;
5981 tx_pkts
= hdev
->hw_stats
.mac_stats
.mac_tx_total_pkt_num
;
5982 if (rx_pkts
!= hdev
->rx_pkts_for_led
||
5983 tx_pkts
!= hdev
->tx_pkts_for_led
)
5984 activity_status
= HCLGE_LED_ON
;
5986 activity_status
= HCLGE_LED_OFF
;
5987 hdev
->rx_pkts_for_led
= rx_pkts
;
5988 hdev
->tx_pkts_for_led
= tx_pkts
;
5990 if (hdev
->hw
.mac
.link
)
5991 link_status
= HCLGE_LED_ON
;
5993 link_status
= HCLGE_LED_OFF
;
5995 return hclge_set_led_status_sfp(hdev
, port_speed_status
,
5996 activity_status
, link_status
,
5997 HCLGE_LED_NO_CHANGE
);
6000 static const struct hnae3_ae_ops hclge_ops
= {
6001 .init_ae_dev
= hclge_init_ae_dev
,
6002 .uninit_ae_dev
= hclge_uninit_ae_dev
,
6003 .init_client_instance
= hclge_init_client_instance
,
6004 .uninit_client_instance
= hclge_uninit_client_instance
,
6005 .map_ring_to_vector
= hclge_map_ring_to_vector
,
6006 .unmap_ring_from_vector
= hclge_unmap_ring_frm_vector
,
6007 .get_vector
= hclge_get_vector
,
6008 .set_promisc_mode
= hclge_set_promisc_mode
,
6009 .set_loopback
= hclge_set_loopback
,
6010 .start
= hclge_ae_start
,
6011 .stop
= hclge_ae_stop
,
6012 .get_status
= hclge_get_status
,
6013 .get_ksettings_an_result
= hclge_get_ksettings_an_result
,
6014 .update_speed_duplex_h
= hclge_update_speed_duplex_h
,
6015 .cfg_mac_speed_dup_h
= hclge_cfg_mac_speed_dup_h
,
6016 .get_media_type
= hclge_get_media_type
,
6017 .get_rss_key_size
= hclge_get_rss_key_size
,
6018 .get_rss_indir_size
= hclge_get_rss_indir_size
,
6019 .get_rss
= hclge_get_rss
,
6020 .set_rss
= hclge_set_rss
,
6021 .set_rss_tuple
= hclge_set_rss_tuple
,
6022 .get_rss_tuple
= hclge_get_rss_tuple
,
6023 .get_tc_size
= hclge_get_tc_size
,
6024 .get_mac_addr
= hclge_get_mac_addr
,
6025 .set_mac_addr
= hclge_set_mac_addr
,
6026 .add_uc_addr
= hclge_add_uc_addr
,
6027 .rm_uc_addr
= hclge_rm_uc_addr
,
6028 .add_mc_addr
= hclge_add_mc_addr
,
6029 .rm_mc_addr
= hclge_rm_mc_addr
,
6030 .set_autoneg
= hclge_set_autoneg
,
6031 .get_autoneg
= hclge_get_autoneg
,
6032 .get_pauseparam
= hclge_get_pauseparam
,
6033 .set_pauseparam
= hclge_set_pauseparam
,
6034 .set_mtu
= hclge_set_mtu
,
6035 .reset_queue
= hclge_reset_tqp
,
6036 .get_stats
= hclge_get_stats
,
6037 .update_stats
= hclge_update_stats
,
6038 .get_strings
= hclge_get_strings
,
6039 .get_sset_count
= hclge_get_sset_count
,
6040 .get_fw_version
= hclge_get_fw_version
,
6041 .get_mdix_mode
= hclge_get_mdix_mode
,
6042 .enable_vlan_filter
= hclge_enable_vlan_filter
,
6043 .set_vlan_filter
= hclge_set_port_vlan_filter
,
6044 .set_vf_vlan_filter
= hclge_set_vf_vlan_filter
,
6045 .enable_hw_strip_rxvtag
= hclge_en_hw_strip_rxvtag
,
6046 .reset_event
= hclge_reset_event
,
6047 .get_tqps_and_rss_info
= hclge_get_tqps_and_rss_info
,
6048 .set_channels
= hclge_set_channels
,
6049 .get_channels
= hclge_get_channels
,
6050 .get_flowctrl_adv
= hclge_get_flowctrl_adv
,
6051 .get_regs_len
= hclge_get_regs_len
,
6052 .get_regs
= hclge_get_regs
,
6053 .set_led_id
= hclge_set_led_id
,
6056 static struct hnae3_ae_algo ae_algo
= {
6059 .pdev_id_table
= ae_algo_pci_tbl
,
6062 static int hclge_init(void)
6064 pr_info("%s is initializing\n", HCLGE_NAME
);
6066 return hnae3_register_ae_algo(&ae_algo
);
6069 static void hclge_exit(void)
6071 hnae3_unregister_ae_algo(&ae_algo
);
6073 module_init(hclge_init
);
6074 module_exit(hclge_exit
);
6076 MODULE_LICENSE("GPL");
6077 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6078 MODULE_DESCRIPTION("HCLGE Driver");
6079 MODULE_VERSION(HCLGE_MOD_VERSION
);